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-rw-r--r--drivers/net/wireless/adm8211.c1
-rw-r--r--drivers/net/wireless/ath/ath.h1
-rw-r--r--drivers/net/wireless/ath/ath5k/ahb.c49
-rw-r--r--drivers/net/wireless/ath/ath5k/ani.c89
-rw-r--r--drivers/net/wireless/ath/ath5k/ath5k.h438
-rw-r--r--drivers/net/wireless/ath/ath5k/attach.c55
-rw-r--r--drivers/net/wireless/ath/ath5k/base.c1201
-rw-r--r--drivers/net/wireless/ath/ath5k/base.h206
-rw-r--r--drivers/net/wireless/ath/ath5k/caps.c49
-rw-r--r--drivers/net/wireless/ath/ath5k/debug.c423
-rw-r--r--drivers/net/wireless/ath/ath5k/debug.h21
-rw-r--r--drivers/net/wireless/ath/ath5k/desc.c10
-rw-r--r--drivers/net/wireless/ath/ath5k/desc.h4
-rw-r--r--drivers/net/wireless/ath/ath5k/dma.c20
-rw-r--r--drivers/net/wireless/ath/ath5k/eeprom.c50
-rw-r--r--drivers/net/wireless/ath/ath5k/eeprom.h12
-rw-r--r--drivers/net/wireless/ath/ath5k/initvals.c16
-rw-r--r--drivers/net/wireless/ath/ath5k/led.c74
-rw-r--r--drivers/net/wireless/ath/ath5k/mac80211-ops.c263
-rw-r--r--drivers/net/wireless/ath/ath5k/pci.c55
-rw-r--r--drivers/net/wireless/ath/ath5k/pcu.c40
-rw-r--r--drivers/net/wireless/ath/ath5k/phy.c133
-rw-r--r--drivers/net/wireless/ath/ath5k/qcu.c9
-rw-r--r--drivers/net/wireless/ath/ath5k/reg.h89
-rw-r--r--drivers/net/wireless/ath/ath5k/reset.c93
-rw-r--r--drivers/net/wireless/ath/ath5k/rfbuffer.h4
-rw-r--r--drivers/net/wireless/ath/ath5k/rfgain.h8
-rw-r--r--drivers/net/wireless/ath/ath5k/rfkill.c65
-rw-r--r--drivers/net/wireless/ath/ath5k/sysfs.c45
-rw-r--r--drivers/net/wireless/ath/ath5k/trace.h21
-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c4
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c5
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c39
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_mac.c6
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.c34
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h10
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c51
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c182
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_mac.c19
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_paprd.c131
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.c41
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_phy.h9
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h1147
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h1080
-rw-r--r--drivers/net/wireless/ath/ath9k/ath9k.h18
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c30
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c81
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h1
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c12
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c12
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c12
-rw-r--r--drivers/net/wireless/ath/ath9k/hif_usb.c11
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_beacon.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_debug.c7
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_init.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/htc_drv_main.c9
-rw-r--r--drivers/net/wireless/ath/ath9k/hw-ops.h5
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c218
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h14
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c39
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c3
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c179
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c56
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c200
-rw-r--r--drivers/net/wireless/ath/ath9k/reg.h44
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c353
-rw-r--r--drivers/net/wireless/ath/carl9170/carl9170.h13
-rw-r--r--drivers/net/wireless/ath/carl9170/cmd.h4
-rw-r--r--drivers/net/wireless/ath/carl9170/debug.c2
-rw-r--r--drivers/net/wireless/ath/carl9170/fw.c2
-rw-r--r--drivers/net/wireless/ath/carl9170/fwcmd.h19
-rw-r--r--drivers/net/wireless/ath/carl9170/fwdesc.h21
-rw-r--r--drivers/net/wireless/ath/carl9170/hw.h56
-rw-r--r--drivers/net/wireless/ath/carl9170/led.c2
-rw-r--r--drivers/net/wireless/ath/carl9170/mac.c129
-rw-r--r--drivers/net/wireless/ath/carl9170/main.c21
-rw-r--r--drivers/net/wireless/ath/carl9170/phy.c12
-rw-r--r--drivers/net/wireless/ath/carl9170/rx.c2
-rw-r--r--drivers/net/wireless/ath/carl9170/tx.c290
-rw-r--r--drivers/net/wireless/ath/carl9170/usb.c2
-rw-r--r--drivers/net/wireless/ath/carl9170/version.h6
-rw-r--r--drivers/net/wireless/ath/carl9170/wlan.h25
-rw-r--r--drivers/net/wireless/ath/key.c7
-rw-r--r--drivers/net/wireless/atmel.c1
-rw-r--r--drivers/net/wireless/b43/Kconfig32
-rw-r--r--drivers/net/wireless/b43/Makefile5
-rw-r--r--drivers/net/wireless/b43/b43.h63
-rw-r--r--drivers/net/wireless/b43/bus.c253
-rw-r--r--drivers/net/wireless/b43/bus.h70
-rw-r--r--drivers/net/wireless/b43/dma.c75
-rw-r--r--drivers/net/wireless/b43/dma.h4
-rw-r--r--drivers/net/wireless/b43/leds.c15
-rw-r--r--drivers/net/wireless/b43/lo.c6
-rw-r--r--drivers/net/wireless/b43/main.c678
-rw-r--r--drivers/net/wireless/b43/main.h2
-rw-r--r--drivers/net/wireless/b43/phy_a.c21
-rw-r--r--drivers/net/wireless/b43/phy_common.c20
-rw-r--r--drivers/net/wireless/b43/phy_common.h6
-rw-r--r--drivers/net/wireless/b43/phy_g.c92
-rw-r--r--drivers/net/wireless/b43/phy_ht.c413
-rw-r--r--drivers/net/wireless/b43/phy_ht.h46
-rw-r--r--drivers/net/wireless/b43/phy_lcn.c52
-rw-r--r--drivers/net/wireless/b43/phy_lcn.h14
-rw-r--r--drivers/net/wireless/b43/phy_lp.c135
-rw-r--r--drivers/net/wireless/b43/phy_n.c120
-rw-r--r--drivers/net/wireless/b43/pio.c10
-rw-r--r--drivers/net/wireless/b43/radio_2055.h5
-rw-r--r--drivers/net/wireless/b43/radio_2056.h5
-rw-r--r--drivers/net/wireless/b43/radio_2059.c174
-rw-r--r--drivers/net/wireless/b43/radio_2059.h54
-rw-r--r--drivers/net/wireless/b43/rfkill.c9
-rw-r--r--drivers/net/wireless/b43/sdio.c10
-rw-r--r--drivers/net/wireless/b43/sysfs.c4
-rw-r--r--drivers/net/wireless/b43/tables_lpphy.c15
-rw-r--r--drivers/net/wireless/b43/tables_nphy.h8
-rw-r--r--drivers/net/wireless/b43/tables_phy_ht.c750
-rw-r--r--drivers/net/wireless/b43/tables_phy_ht.h22
-rw-r--r--drivers/net/wireless/b43/tables_phy_lcn.c34
-rw-r--r--drivers/net/wireless/b43/tables_phy_lcn.h6
-rw-r--r--drivers/net/wireless/b43/wa.c24
-rw-r--r--drivers/net/wireless/b43/xmit.c5
-rw-r--r--drivers/net/wireless/b43legacy/b43legacy.h2
-rw-r--r--drivers/net/wireless/b43legacy/dma.c17
-rw-r--r--drivers/net/wireless/b43legacy/main.c10
-rw-r--r--drivers/net/wireless/b43legacy/xmit.c2
-rw-r--r--drivers/net/wireless/hostap/hostap_wlan.h1
-rw-r--r--drivers/net/wireless/ipw2x00/ipw2100.c2
-rw-r--r--drivers/net/wireless/ipw2x00/ipw2200.h1
-rw-r--r--drivers/net/wireless/ipw2x00/libipw_rx.c4
-rw-r--r--drivers/net/wireless/ipw2x00/libipw_wx.c1
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-3945.c4
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-4965-lib.c79
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-4965-rs.c3
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-4965-rx.c78
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-4965-tx.c3
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-4965.c10
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-commands.h7
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-core.c91
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-core.h17
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-debugfs.c192
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-dev.h61
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-devtrace.c3
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-devtrace.h60
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-eeprom.c1
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-helpers.h9
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-rx.c21
-rw-r--r--drivers/net/wireless/iwlegacy/iwl-scan.c92
-rw-r--r--drivers/net/wireless/iwlegacy/iwl3945-base.c301
-rw-r--r--drivers/net/wireless/iwlegacy/iwl4965-base.c465
-rw-r--r--drivers/net/wireless/iwlwifi/Makefile8
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-1000.c32
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-2000.c117
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000-hw.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-5000.c78
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-6000.c115
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-calib.c74
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-calib.h7
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c20
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c328
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-hw.h7
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-ict.c306
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-lib.c774
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-rs.c38
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-rxon.c235
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-sta.c394
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-tt.c38
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-tx.c614
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-ucode.c224
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.c2038
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.h87
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-bus.h139
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-commands.h218
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.c166
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-core.h194
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-csr.h1
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-debug.h20
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-debugfs.c94
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-dev.h181
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.c42
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-eeprom.h26
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-fh.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-hcmd.c291
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-helpers.h9
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.h7
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-led.c17
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-pci.c569
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-power.c46
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-power.h2
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-prph.h93
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-rx.c296
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-scan.c26
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sta.c22
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sta.h5
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-sv-open.c194
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-testmode.h251
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h82
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c979
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c (renamed from drivers/net/wireless/iwlwifi/iwl-tx.c)727
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans.c1172
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-trans.h225
-rw-r--r--drivers/net/wireless/iwmc3200wifi/fw.c2
-rw-r--r--drivers/net/wireless/libertas/cfg.c1
-rw-r--r--drivers/net/wireless/libertas/cmd.c47
-rw-r--r--drivers/net/wireless/libertas/cmd.h2
-rw-r--r--drivers/net/wireless/libertas/cmdresp.c7
-rw-r--r--drivers/net/wireless/libertas/debugfs.c1
-rw-r--r--drivers/net/wireless/libertas/dev.h2
-rw-r--r--drivers/net/wireless/libertas/ethtool.c1
-rw-r--r--drivers/net/wireless/libertas/if_sdio.c34
-rw-r--r--drivers/net/wireless/libertas/if_spi.c8
-rw-r--r--drivers/net/wireless/libertas/main.c15
-rw-r--r--drivers/net/wireless/libertas/mesh.c973
-rw-r--r--drivers/net/wireless/libertas/mesh.h31
-rw-r--r--drivers/net/wireless/libertas/rx.c1
-rw-r--r--drivers/net/wireless/libertas/tx.c3
-rw-r--r--drivers/net/wireless/libertas_tf/cmd.c1
-rw-r--r--drivers/net/wireless/libertas_tf/main.c3
-rw-r--r--drivers/net/wireless/mac80211_hwsim.c464
-rw-r--r--drivers/net/wireless/mac80211_hwsim.h133
-rw-r--r--drivers/net/wireless/mwifiex/11n.c33
-rw-r--r--drivers/net/wireless/mwifiex/11n.h14
-rw-r--r--drivers/net/wireless/mwifiex/11n_aggr.c54
-rw-r--r--drivers/net/wireless/mwifiex/11n_rxreorder.c5
-rw-r--r--drivers/net/wireless/mwifiex/11n_rxreorder.h5
-rw-r--r--drivers/net/wireless/mwifiex/cfg80211.c56
-rw-r--r--drivers/net/wireless/mwifiex/cmdevt.c28
-rw-r--r--drivers/net/wireless/mwifiex/debugfs.c35
-rw-r--r--drivers/net/wireless/mwifiex/decl.h4
-rw-r--r--drivers/net/wireless/mwifiex/fw.h11
-rw-r--r--drivers/net/wireless/mwifiex/ioctl.h1
-rw-r--r--drivers/net/wireless/mwifiex/join.c23
-rw-r--r--drivers/net/wireless/mwifiex/main.c36
-rw-r--r--drivers/net/wireless/mwifiex/main.h30
-rw-r--r--drivers/net/wireless/mwifiex/scan.c6
-rw-r--r--drivers/net/wireless/mwifiex/sdio.c94
-rw-r--r--drivers/net/wireless/mwifiex/sdio.h6
-rw-r--r--drivers/net/wireless/mwifiex/sta_cmd.c113
-rw-r--r--drivers/net/wireless/mwifiex/sta_cmdresp.c50
-rw-r--r--drivers/net/wireless/mwifiex/sta_ioctl.c14
-rw-r--r--drivers/net/wireless/mwifiex/sta_rx.c2
-rw-r--r--drivers/net/wireless/mwifiex/sta_tx.c13
-rw-r--r--drivers/net/wireless/mwifiex/txrx.c2
-rw-r--r--drivers/net/wireless/mwifiex/wmm.c32
-rw-r--r--drivers/net/wireless/mwl8k.c7
-rw-r--r--drivers/net/wireless/orinoco/airport.c9
-rw-r--r--drivers/net/wireless/orinoco/cfg.c6
-rw-r--r--drivers/net/wireless/orinoco/fw.c7
-rw-r--r--drivers/net/wireless/orinoco/fw.h2
-rw-r--r--drivers/net/wireless/orinoco/hermes.c40
-rw-r--r--drivers/net/wireless/orinoco/hermes.h37
-rw-r--r--drivers/net/wireless/orinoco/hermes_dld.c8
-rw-r--r--drivers/net/wireless/orinoco/hermes_dld.h12
-rw-r--r--drivers/net/wireless/orinoco/hw.c48
-rw-r--r--drivers/net/wireless/orinoco/hw.h2
-rw-r--r--drivers/net/wireless/orinoco/main.c48
-rw-r--r--drivers/net/wireless/orinoco/mic.c8
-rw-r--r--drivers/net/wireless/orinoco/orinoco.h16
-rw-r--r--drivers/net/wireless/orinoco/orinoco_cs.c6
-rw-r--r--drivers/net/wireless/orinoco/orinoco_nortel.c3
-rw-r--r--drivers/net/wireless/orinoco/orinoco_pci.c4
-rw-r--r--drivers/net/wireless/orinoco/orinoco_plx.c6
-rw-r--r--drivers/net/wireless/orinoco/orinoco_tmd.c2
-rw-r--r--drivers/net/wireless/orinoco/orinoco_usb.c23
-rw-r--r--drivers/net/wireless/orinoco/spectrum_cs.c10
-rw-r--r--drivers/net/wireless/orinoco/wext.c14
-rw-r--r--drivers/net/wireless/p54/p54pci.h1
-rw-r--r--drivers/net/wireless/prism54/islpci_dev.c1
-rw-r--r--drivers/net/wireless/prism54/islpci_dev.h1
-rw-r--r--drivers/net/wireless/prism54/islpci_hotplug.c1
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig9
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c1
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c1
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c1
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h16
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c378
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.h1
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c8
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c90
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00crypto.c6
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dev.c13
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00lib.h3
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00mac.c14
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.c113
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h4
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c1
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c1
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c1
-rw-r--r--drivers/net/wireless/rtl818x/rtl8180/dev.c1
-rw-r--r--drivers/net/wireless/rtlwifi/Kconfig15
-rw-r--r--drivers/net/wireless/rtlwifi/Makefile1
-rw-r--r--drivers/net/wireless/rtlwifi/base.c26
-rw-r--r--drivers/net/wireless/rtlwifi/cam.c8
-rw-r--r--drivers/net/wireless/rtlwifi/core.c18
-rw-r--r--drivers/net/wireless/rtlwifi/core.h2
-rw-r--r--drivers/net/wireless/rtlwifi/debug.h5
-rw-r--r--drivers/net/wireless/rtlwifi/efuse.c14
-rw-r--r--drivers/net/wireless/rtlwifi/pci.c249
-rw-r--r--drivers/net/wireless/rtlwifi/pci.h12
-rw-r--r--drivers/net/wireless/rtlwifi/ps.c97
-rw-r--r--drivers/net/wireless/rtlwifi/ps.h3
-rw-r--r--drivers/net/wireless/rtlwifi/rc.c2
-rw-r--r--drivers/net/wireless/rtlwifi/regd.c18
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c4
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c7
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c12
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/hw.c23
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/led.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/phy.c14
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/reg.h2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/rf.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/trx.c12
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/hw.c77
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/led.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/mac.c22
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/phy.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/rf.c4
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/sw.c1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/trx.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/Makefile14
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/def.h269
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/dm.c1355
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/dm.h212
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/fw.c790
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/fw.h155
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/hw.c2329
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/hw.h66
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/led.c159
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/led.h38
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/phy.c3831
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/phy.h178
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/reg.h1313
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/rf.c628
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/rf.h44
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/sw.c423
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/sw.h37
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/table.c1690
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/table.h57
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/trx.c959
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/trx.h756
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/dm.c7
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/fw.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/hw.c38
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/led.c2
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/phy.c27
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/reg.h6
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/rf.c6
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/sw.c6
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/trx.c12
-rw-r--r--drivers/net/wireless/rtlwifi/usb.c12
-rw-r--r--drivers/net/wireless/rtlwifi/wifi.h10
-rw-r--r--drivers/net/wireless/wl1251/sdio.c1
-rw-r--r--drivers/net/wireless/wl1251/spi.c1
-rw-r--r--drivers/net/wireless/wl12xx/Kconfig2
-rw-r--r--drivers/net/wireless/wl12xx/acx.c61
-rw-r--r--drivers/net/wireless/wl12xx/acx.h20
-rw-r--r--drivers/net/wireless/wl12xx/boot.c40
-rw-r--r--drivers/net/wireless/wl12xx/cmd.c109
-rw-r--r--drivers/net/wireless/wl12xx/cmd.h62
-rw-r--r--drivers/net/wireless/wl12xx/conf.h65
-rw-r--r--drivers/net/wireless/wl12xx/debugfs.c153
-rw-r--r--drivers/net/wireless/wl12xx/event.c101
-rw-r--r--drivers/net/wireless/wl12xx/event.h29
-rw-r--r--drivers/net/wireless/wl12xx/ini.h3
-rw-r--r--drivers/net/wireless/wl12xx/init.c27
-rw-r--r--drivers/net/wireless/wl12xx/io.c7
-rw-r--r--drivers/net/wireless/wl12xx/io.h15
-rw-r--r--drivers/net/wireless/wl12xx/main.c793
-rw-r--r--drivers/net/wireless/wl12xx/ps.c21
-rw-r--r--drivers/net/wireless/wl12xx/rx.c39
-rw-r--r--drivers/net/wireless/wl12xx/rx.h12
-rw-r--r--drivers/net/wireless/wl12xx/scan.c90
-rw-r--r--drivers/net/wireless/wl12xx/scan.h18
-rw-r--r--drivers/net/wireless/wl12xx/sdio.c83
-rw-r--r--drivers/net/wireless/wl12xx/spi.c16
-rw-r--r--drivers/net/wireless/wl12xx/testmode.c2
-rw-r--r--drivers/net/wireless/wl12xx/tx.c176
-rw-r--r--drivers/net/wireless/wl12xx/tx.h28
-rw-r--r--drivers/net/wireless/wl12xx/wl12xx.h63
-rw-r--r--drivers/net/wireless/zd1211rw/zd_chip.h2
-rw-r--r--drivers/net/wireless/zd1211rw/zd_def.h6
-rw-r--r--drivers/net/wireless/zd1211rw/zd_mac.c118
-rw-r--r--drivers/net/wireless/zd1211rw/zd_mac.h1
-rw-r--r--drivers/net/wireless/zd1211rw/zd_usb.c129
-rw-r--r--drivers/net/wireless/zd1211rw/zd_usb.h5
386 files changed, 34607 insertions, 11825 deletions
diff --git a/drivers/net/wireless/adm8211.c b/drivers/net/wireless/adm8211.c
index afe2cbc6cb24..43ebc44fc82c 100644
--- a/drivers/net/wireless/adm8211.c
+++ b/drivers/net/wireless/adm8211.c
@@ -16,6 +16,7 @@
16 */ 16 */
17 17
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/interrupt.h>
19#include <linux/if.h> 20#include <linux/if.h>
20#include <linux/skbuff.h> 21#include <linux/skbuff.h>
21#include <linux/slab.h> 22#include <linux/slab.h>
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index 7cf4317a2a84..17c4b56c3874 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -161,6 +161,7 @@ struct ath_common {
161 const struct ath_bus_ops *bus_ops; 161 const struct ath_bus_ops *bus_ops;
162 162
163 bool btcoex_enabled; 163 bool btcoex_enabled;
164 bool disable_ani;
164}; 165};
165 166
166struct sk_buff *ath_rxbuf_alloc(struct ath_common *common, 167struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
diff --git a/drivers/net/wireless/ath/ath5k/ahb.c b/drivers/net/wireless/ath/ath5k/ahb.c
index ea9982781559..9f69a4c9a3f3 100644
--- a/drivers/net/wireless/ath/ath5k/ahb.c
+++ b/drivers/net/wireless/ath/ath5k/ahb.c
@@ -35,8 +35,8 @@ static void ath5k_ahb_read_cachesize(struct ath_common *common, int *csz)
35static bool 35static bool
36ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data) 36ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
37{ 37{
38 struct ath5k_softc *sc = common->priv; 38 struct ath5k_hw *ah = common->priv;
39 struct platform_device *pdev = to_platform_device(sc->dev); 39 struct platform_device *pdev = to_platform_device(ah->dev);
40 struct ar231x_board_config *bcfg = pdev->dev.platform_data; 40 struct ar231x_board_config *bcfg = pdev->dev.platform_data;
41 u16 *eeprom, *eeprom_end; 41 u16 *eeprom, *eeprom_end;
42 42
@@ -56,8 +56,7 @@ ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
56 56
57int ath5k_hw_read_srev(struct ath5k_hw *ah) 57int ath5k_hw_read_srev(struct ath5k_hw *ah)
58{ 58{
59 struct ath5k_softc *sc = ah->ah_sc; 59 struct platform_device *pdev = to_platform_device(ah->dev);
60 struct platform_device *pdev = to_platform_device(sc->dev);
61 struct ar231x_board_config *bcfg = pdev->dev.platform_data; 60 struct ar231x_board_config *bcfg = pdev->dev.platform_data;
62 ah->ah_mac_srev = bcfg->devid; 61 ah->ah_mac_srev = bcfg->devid;
63 return 0; 62 return 0;
@@ -65,12 +64,11 @@ int ath5k_hw_read_srev(struct ath5k_hw *ah)
65 64
66static int ath5k_ahb_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac) 65static int ath5k_ahb_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
67{ 66{
68 struct ath5k_softc *sc = ah->ah_sc; 67 struct platform_device *pdev = to_platform_device(ah->dev);
69 struct platform_device *pdev = to_platform_device(sc->dev);
70 struct ar231x_board_config *bcfg = pdev->dev.platform_data; 68 struct ar231x_board_config *bcfg = pdev->dev.platform_data;
71 u8 *cfg_mac; 69 u8 *cfg_mac;
72 70
73 if (to_platform_device(sc->dev)->id == 0) 71 if (to_platform_device(ah->dev)->id == 0)
74 cfg_mac = bcfg->config->wlan0_mac; 72 cfg_mac = bcfg->config->wlan0_mac;
75 else 73 else
76 cfg_mac = bcfg->config->wlan1_mac; 74 cfg_mac = bcfg->config->wlan1_mac;
@@ -90,7 +88,7 @@ static const struct ath_bus_ops ath_ahb_bus_ops = {
90static int ath_ahb_probe(struct platform_device *pdev) 88static int ath_ahb_probe(struct platform_device *pdev)
91{ 89{
92 struct ar231x_board_config *bcfg = pdev->dev.platform_data; 90 struct ar231x_board_config *bcfg = pdev->dev.platform_data;
93 struct ath5k_softc *sc; 91 struct ath5k_hw *ah;
94 struct ieee80211_hw *hw; 92 struct ieee80211_hw *hw;
95 struct resource *res; 93 struct resource *res;
96 void __iomem *mem; 94 void __iomem *mem;
@@ -127,19 +125,19 @@ static int ath_ahb_probe(struct platform_device *pdev)
127 125
128 irq = res->start; 126 irq = res->start;
129 127
130 hw = ieee80211_alloc_hw(sizeof(struct ath5k_softc), &ath5k_hw_ops); 128 hw = ieee80211_alloc_hw(sizeof(struct ath5k_hw), &ath5k_hw_ops);
131 if (hw == NULL) { 129 if (hw == NULL) {
132 dev_err(&pdev->dev, "no memory for ieee80211_hw\n"); 130 dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
133 ret = -ENOMEM; 131 ret = -ENOMEM;
134 goto err_out; 132 goto err_out;
135 } 133 }
136 134
137 sc = hw->priv; 135 ah = hw->priv;
138 sc->hw = hw; 136 ah->hw = hw;
139 sc->dev = &pdev->dev; 137 ah->dev = &pdev->dev;
140 sc->iobase = mem; 138 ah->iobase = mem;
141 sc->irq = irq; 139 ah->irq = irq;
142 sc->devid = bcfg->devid; 140 ah->devid = bcfg->devid;
143 141
144 if (bcfg->devid >= AR5K_SREV_AR2315_R6) { 142 if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
145 /* Enable WMAC AHB arbitration */ 143 /* Enable WMAC AHB arbitration */
@@ -155,7 +153,7 @@ static int ath_ahb_probe(struct platform_device *pdev)
155 /* Enable WMAC DMA access (assuming 5312 or 231x*/ 153 /* Enable WMAC DMA access (assuming 5312 or 231x*/
156 /* TODO: check other platforms */ 154 /* TODO: check other platforms */
157 reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE); 155 reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE);
158 if (to_platform_device(sc->dev)->id == 0) 156 if (to_platform_device(ah->dev)->id == 0)
159 reg |= AR5K_AR5312_ENABLE_WLAN0; 157 reg |= AR5K_AR5312_ENABLE_WLAN0;
160 else 158 else
161 reg |= AR5K_AR5312_ENABLE_WLAN1; 159 reg |= AR5K_AR5312_ENABLE_WLAN1;
@@ -166,13 +164,13 @@ static int ath_ahb_probe(struct platform_device *pdev)
166 * used as pass-through. Disable 2 GHz support in the 164 * used as pass-through. Disable 2 GHz support in the
167 * driver for it 165 * driver for it
168 */ 166 */
169 if (to_platform_device(sc->dev)->id == 0 && 167 if (to_platform_device(ah->dev)->id == 0 &&
170 (bcfg->config->flags & (BD_WLAN0|BD_WLAN1)) == 168 (bcfg->config->flags & (BD_WLAN0 | BD_WLAN1)) ==
171 (BD_WLAN1|BD_WLAN0)) 169 (BD_WLAN1 | BD_WLAN0))
172 __set_bit(ATH_STAT_2G_DISABLED, sc->status); 170 __set_bit(ATH_STAT_2G_DISABLED, ah->status);
173 } 171 }
174 172
175 ret = ath5k_init_softc(sc, &ath_ahb_bus_ops); 173 ret = ath5k_init_softc(ah, &ath_ahb_bus_ops);
176 if (ret != 0) { 174 if (ret != 0) {
177 dev_err(&pdev->dev, "failed to attach device, err=%d\n", ret); 175 dev_err(&pdev->dev, "failed to attach device, err=%d\n", ret);
178 ret = -ENODEV; 176 ret = -ENODEV;
@@ -194,13 +192,13 @@ static int ath_ahb_remove(struct platform_device *pdev)
194{ 192{
195 struct ar231x_board_config *bcfg = pdev->dev.platform_data; 193 struct ar231x_board_config *bcfg = pdev->dev.platform_data;
196 struct ieee80211_hw *hw = platform_get_drvdata(pdev); 194 struct ieee80211_hw *hw = platform_get_drvdata(pdev);
197 struct ath5k_softc *sc; 195 struct ath5k_hw *ah;
198 u32 reg; 196 u32 reg;
199 197
200 if (!hw) 198 if (!hw)
201 return 0; 199 return 0;
202 200
203 sc = hw->priv; 201 ah = hw->priv;
204 202
205 if (bcfg->devid >= AR5K_SREV_AR2315_R6) { 203 if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
206 /* Disable WMAC AHB arbitration */ 204 /* Disable WMAC AHB arbitration */
@@ -210,15 +208,16 @@ static int ath_ahb_remove(struct platform_device *pdev)
210 } else { 208 } else {
211 /*Stop DMA access */ 209 /*Stop DMA access */
212 reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE); 210 reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE);
213 if (to_platform_device(sc->dev)->id == 0) 211 if (to_platform_device(ah->dev)->id == 0)
214 reg &= ~AR5K_AR5312_ENABLE_WLAN0; 212 reg &= ~AR5K_AR5312_ENABLE_WLAN0;
215 else 213 else
216 reg &= ~AR5K_AR5312_ENABLE_WLAN1; 214 reg &= ~AR5K_AR5312_ENABLE_WLAN1;
217 __raw_writel(reg, (void __iomem *) AR5K_AR5312_ENABLE); 215 __raw_writel(reg, (void __iomem *) AR5K_AR5312_ENABLE);
218 } 216 }
219 217
220 ath5k_deinit_softc(sc); 218 ath5k_deinit_softc(ah);
221 platform_set_drvdata(pdev, NULL); 219 platform_set_drvdata(pdev, NULL);
220 ieee80211_free_hw(hw);
222 221
223 return 0; 222 return 0;
224} 223}
diff --git a/drivers/net/wireless/ath/ath5k/ani.c b/drivers/net/wireless/ath/ath5k/ani.c
index f915f404302d..603ae15f139b 100644
--- a/drivers/net/wireless/ath/ath5k/ani.c
+++ b/drivers/net/wireless/ath/ath5k/ani.c
@@ -74,7 +74,7 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
74 static const s8 fr[] = { -78, -80 }; 74 static const s8 fr[] = { -78, -80 };
75#endif 75#endif
76 if (level < 0 || level >= ARRAY_SIZE(sz)) { 76 if (level < 0 || level >= ARRAY_SIZE(sz)) {
77 ATH5K_ERR(ah->ah_sc, "noise immuniy level %d out of range", 77 ATH5K_ERR(ah, "noise immunity level %d out of range",
78 level); 78 level);
79 return; 79 return;
80 } 80 }
@@ -88,8 +88,8 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
88 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, 88 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
89 AR5K_PHY_SIG_FIRPWR, fr[level]); 89 AR5K_PHY_SIG_FIRPWR, fr[level]);
90 90
91 ah->ah_sc->ani_state.noise_imm_level = level; 91 ah->ani_state.noise_imm_level = level;
92 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 92 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
93} 93}
94 94
95 95
@@ -105,8 +105,8 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
105 static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; 105 static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
106 106
107 if (level < 0 || level >= ARRAY_SIZE(val) || 107 if (level < 0 || level >= ARRAY_SIZE(val) ||
108 level > ah->ah_sc->ani_state.max_spur_level) { 108 level > ah->ani_state.max_spur_level) {
109 ATH5K_ERR(ah->ah_sc, "spur immunity level %d out of range", 109 ATH5K_ERR(ah, "spur immunity level %d out of range",
110 level); 110 level);
111 return; 111 return;
112 } 112 }
@@ -114,8 +114,8 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
114 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 114 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
115 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]); 115 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]);
116 116
117 ah->ah_sc->ani_state.spur_level = level; 117 ah->ani_state.spur_level = level;
118 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 118 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
119} 119}
120 120
121 121
@@ -130,15 +130,15 @@ ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
130 static const int val[] = { 0, 4, 8 }; 130 static const int val[] = { 0, 4, 8 };
131 131
132 if (level < 0 || level >= ARRAY_SIZE(val)) { 132 if (level < 0 || level >= ARRAY_SIZE(val)) {
133 ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level); 133 ATH5K_ERR(ah, "firstep level %d out of range", level);
134 return; 134 return;
135 } 135 }
136 136
137 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, 137 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG,
138 AR5K_PHY_SIG_FIRSTEP, val[level]); 138 AR5K_PHY_SIG_FIRSTEP, val[level]);
139 139
140 ah->ah_sc->ani_state.firstep_level = level; 140 ah->ani_state.firstep_level = level;
141 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 141 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "new level %d", level);
142} 142}
143 143
144 144
@@ -178,8 +178,8 @@ ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
178 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 178 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
179 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN); 179 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN);
180 180
181 ah->ah_sc->ani_state.ofdm_weak_sig = on; 181 ah->ani_state.ofdm_weak_sig = on;
182 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s", 182 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
183 on ? "on" : "off"); 183 on ? "on" : "off");
184} 184}
185 185
@@ -195,8 +195,8 @@ ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
195 static const int val[] = { 8, 6 }; 195 static const int val[] = { 8, 6 };
196 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR, 196 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
197 AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]); 197 AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]);
198 ah->ah_sc->ani_state.cck_weak_sig = on; 198 ah->ani_state.cck_weak_sig = on;
199 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s", 199 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "turned %s",
200 on ? "on" : "off"); 200 on ? "on" : "off");
201} 201}
202 202
@@ -218,7 +218,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
218{ 218{
219 int rssi = ewma_read(&ah->ah_beacon_rssi_avg); 219 int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
220 220
221 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)", 221 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "raise immunity (%s)",
222 ofdm_trigger ? "ODFM" : "CCK"); 222 ofdm_trigger ? "ODFM" : "CCK");
223 223
224 /* first: raise noise immunity */ 224 /* first: raise noise immunity */
@@ -229,13 +229,13 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
229 229
230 /* only OFDM: raise spur immunity level */ 230 /* only OFDM: raise spur immunity level */
231 if (ofdm_trigger && 231 if (ofdm_trigger &&
232 as->spur_level < ah->ah_sc->ani_state.max_spur_level) { 232 as->spur_level < ah->ani_state.max_spur_level) {
233 ath5k_ani_set_spur_immunity_level(ah, as->spur_level + 1); 233 ath5k_ani_set_spur_immunity_level(ah, as->spur_level + 1);
234 return; 234 return;
235 } 235 }
236 236
237 /* AP mode */ 237 /* AP mode */
238 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) { 238 if (ah->opmode == NL80211_IFTYPE_AP) {
239 if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) 239 if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL)
240 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); 240 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1);
241 return; 241 return;
@@ -248,7 +248,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
248 * don't shut out a remote node by raising immunity too high. */ 248 * don't shut out a remote node by raising immunity too high. */
249 249
250 if (rssi > ATH5K_ANI_RSSI_THR_HIGH) { 250 if (rssi > ATH5K_ANI_RSSI_THR_HIGH) {
251 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 251 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
252 "beacon RSSI high"); 252 "beacon RSSI high");
253 /* only OFDM: beacon RSSI is high, we can disable ODFM weak 253 /* only OFDM: beacon RSSI is high, we can disable ODFM weak
254 * signal detection */ 254 * signal detection */
@@ -265,7 +265,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
265 } else if (rssi > ATH5K_ANI_RSSI_THR_LOW) { 265 } else if (rssi > ATH5K_ANI_RSSI_THR_LOW) {
266 /* beacon RSSI in mid range, we need OFDM weak signal detect, 266 /* beacon RSSI in mid range, we need OFDM weak signal detect,
267 * but can raise firstep level */ 267 * but can raise firstep level */
268 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 268 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
269 "beacon RSSI mid"); 269 "beacon RSSI mid");
270 if (ofdm_trigger && as->ofdm_weak_sig == false) 270 if (ofdm_trigger && as->ofdm_weak_sig == false)
271 ath5k_ani_set_ofdm_weak_signal_detection(ah, true); 271 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
@@ -275,7 +275,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
275 } else if (ah->ah_current_channel->band == IEEE80211_BAND_2GHZ) { 275 } else if (ah->ah_current_channel->band == IEEE80211_BAND_2GHZ) {
276 /* beacon RSSI is low. in B/G mode turn of OFDM weak signal 276 /* beacon RSSI is low. in B/G mode turn of OFDM weak signal
277 * detect and zero firstep level to maximize CCK sensitivity */ 277 * detect and zero firstep level to maximize CCK sensitivity */
278 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 278 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
279 "beacon RSSI low, 2GHz"); 279 "beacon RSSI low, 2GHz");
280 if (ofdm_trigger && as->ofdm_weak_sig == true) 280 if (ofdm_trigger && as->ofdm_weak_sig == true)
281 ath5k_ani_set_ofdm_weak_signal_detection(ah, false); 281 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
@@ -303,9 +303,9 @@ ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
303{ 303{
304 int rssi = ewma_read(&ah->ah_beacon_rssi_avg); 304 int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
305 305
306 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity"); 306 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "lower immunity");
307 307
308 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) { 308 if (ah->opmode == NL80211_IFTYPE_AP) {
309 /* AP mode */ 309 /* AP mode */
310 if (as->firstep_level > 0) { 310 if (as->firstep_level > 0) {
311 ath5k_ani_set_firstep_level(ah, as->firstep_level - 1); 311 ath5k_ani_set_firstep_level(ah, as->firstep_level - 1);
@@ -464,7 +464,7 @@ ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as)
464void 464void
465ath5k_ani_calibration(struct ath5k_hw *ah) 465ath5k_ani_calibration(struct ath5k_hw *ah)
466{ 466{
467 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 467 struct ath5k_ani_state *as = &ah->ani_state;
468 int listen, ofdm_high, ofdm_low, cck_high, cck_low; 468 int listen, ofdm_high, ofdm_low, cck_high, cck_low;
469 469
470 /* get listen time since last call and add it to the counter because we 470 /* get listen time since last call and add it to the counter because we
@@ -483,9 +483,9 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
483 ofdm_low = as->listen_time * ATH5K_ANI_OFDM_TRIG_LOW / 1000; 483 ofdm_low = as->listen_time * ATH5K_ANI_OFDM_TRIG_LOW / 1000;
484 cck_low = as->listen_time * ATH5K_ANI_CCK_TRIG_LOW / 1000; 484 cck_low = as->listen_time * ATH5K_ANI_CCK_TRIG_LOW / 1000;
485 485
486 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 486 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
487 "listen %d (now %d)", as->listen_time, listen); 487 "listen %d (now %d)", as->listen_time, listen);
488 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 488 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
489 "check high ofdm %d/%d cck %d/%d", 489 "check high ofdm %d/%d cck %d/%d",
490 as->ofdm_errors, ofdm_high, as->cck_errors, cck_high); 490 as->ofdm_errors, ofdm_high, as->cck_errors, cck_high);
491 491
@@ -498,7 +498,7 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
498 } else if (as->listen_time > 5 * ATH5K_ANI_LISTEN_PERIOD) { 498 } else if (as->listen_time > 5 * ATH5K_ANI_LISTEN_PERIOD) {
499 /* If more than 5 (TODO: why 5?) periods have passed and we got 499 /* If more than 5 (TODO: why 5?) periods have passed and we got
500 * relatively little errors we can try to lower immunity */ 500 * relatively little errors we can try to lower immunity */
501 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 501 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
502 "check low ofdm %d/%d cck %d/%d", 502 "check low ofdm %d/%d cck %d/%d",
503 as->ofdm_errors, ofdm_low, as->cck_errors, cck_low); 503 as->ofdm_errors, ofdm_low, as->cck_errors, cck_low);
504 504
@@ -525,7 +525,7 @@ ath5k_ani_calibration(struct ath5k_hw *ah)
525void 525void
526ath5k_ani_mib_intr(struct ath5k_hw *ah) 526ath5k_ani_mib_intr(struct ath5k_hw *ah)
527{ 527{
528 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 528 struct ath5k_ani_state *as = &ah->ani_state;
529 529
530 /* nothing to do here if HW does not have PHY error counters - they 530 /* nothing to do here if HW does not have PHY error counters - they
531 * can't be the reason for the MIB interrupt then */ 531 * can't be the reason for the MIB interrupt then */
@@ -536,7 +536,7 @@ ath5k_ani_mib_intr(struct ath5k_hw *ah)
536 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); 536 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT);
537 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 537 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT);
538 538
539 if (ah->ah_sc->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO) 539 if (ah->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO)
540 return; 540 return;
541 541
542 /* If one of the errors triggered, we can get a superfluous second 542 /* If one of the errors triggered, we can get a superfluous second
@@ -547,7 +547,7 @@ ath5k_ani_mib_intr(struct ath5k_hw *ah)
547 547
548 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH || 548 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH ||
549 as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH) 549 as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH)
550 tasklet_schedule(&ah->ah_sc->ani_tasklet); 550 tasklet_schedule(&ah->ani_tasklet);
551} 551}
552 552
553 553
@@ -561,16 +561,16 @@ void
561ath5k_ani_phy_error_report(struct ath5k_hw *ah, 561ath5k_ani_phy_error_report(struct ath5k_hw *ah,
562 enum ath5k_phy_error_code phyerr) 562 enum ath5k_phy_error_code phyerr)
563{ 563{
564 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 564 struct ath5k_ani_state *as = &ah->ani_state;
565 565
566 if (phyerr == AR5K_RX_PHY_ERROR_OFDM_TIMING) { 566 if (phyerr == AR5K_RX_PHY_ERROR_OFDM_TIMING) {
567 as->ofdm_errors++; 567 as->ofdm_errors++;
568 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH) 568 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH)
569 tasklet_schedule(&ah->ah_sc->ani_tasklet); 569 tasklet_schedule(&ah->ani_tasklet);
570 } else if (phyerr == AR5K_RX_PHY_ERROR_CCK_TIMING) { 570 } else if (phyerr == AR5K_RX_PHY_ERROR_CCK_TIMING) {
571 as->cck_errors++; 571 as->cck_errors++;
572 if (as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH) 572 if (as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH)
573 tasklet_schedule(&ah->ah_sc->ani_tasklet); 573 tasklet_schedule(&ah->ani_tasklet);
574 } 574 }
575} 575}
576 576
@@ -630,20 +630,25 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
630 if (ah->ah_version < AR5K_AR5212) 630 if (ah->ah_version < AR5K_AR5212)
631 return; 631 return;
632 632
633 if (mode < ATH5K_ANI_MODE_OFF || mode > ATH5K_ANI_MODE_AUTO) {
634 ATH5K_ERR(ah, "ANI mode %d out of range", mode);
635 return;
636 }
637
633 /* clear old state information */ 638 /* clear old state information */
634 memset(&ah->ah_sc->ani_state, 0, sizeof(ah->ah_sc->ani_state)); 639 memset(&ah->ani_state, 0, sizeof(ah->ani_state));
635 640
636 /* older hardware has more spur levels than newer */ 641 /* older hardware has more spur levels than newer */
637 if (ah->ah_mac_srev < AR5K_SREV_AR2414) 642 if (ah->ah_mac_srev < AR5K_SREV_AR2414)
638 ah->ah_sc->ani_state.max_spur_level = 7; 643 ah->ani_state.max_spur_level = 7;
639 else 644 else
640 ah->ah_sc->ani_state.max_spur_level = 2; 645 ah->ani_state.max_spur_level = 2;
641 646
642 /* initial values for our ani parameters */ 647 /* initial values for our ani parameters */
643 if (mode == ATH5K_ANI_MODE_OFF) { 648 if (mode == ATH5K_ANI_MODE_OFF) {
644 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI off\n"); 649 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "ANI off\n");
645 } else if (mode == ATH5K_ANI_MODE_MANUAL_LOW) { 650 } else if (mode == ATH5K_ANI_MODE_MANUAL_LOW) {
646 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 651 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
647 "ANI manual low -> high sensitivity\n"); 652 "ANI manual low -> high sensitivity\n");
648 ath5k_ani_set_noise_immunity_level(ah, 0); 653 ath5k_ani_set_noise_immunity_level(ah, 0);
649 ath5k_ani_set_spur_immunity_level(ah, 0); 654 ath5k_ani_set_spur_immunity_level(ah, 0);
@@ -651,17 +656,17 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
651 ath5k_ani_set_ofdm_weak_signal_detection(ah, true); 656 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
652 ath5k_ani_set_cck_weak_signal_detection(ah, true); 657 ath5k_ani_set_cck_weak_signal_detection(ah, true);
653 } else if (mode == ATH5K_ANI_MODE_MANUAL_HIGH) { 658 } else if (mode == ATH5K_ANI_MODE_MANUAL_HIGH) {
654 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 659 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI,
655 "ANI manual high -> low sensitivity\n"); 660 "ANI manual high -> low sensitivity\n");
656 ath5k_ani_set_noise_immunity_level(ah, 661 ath5k_ani_set_noise_immunity_level(ah,
657 ATH5K_ANI_MAX_NOISE_IMM_LVL); 662 ATH5K_ANI_MAX_NOISE_IMM_LVL);
658 ath5k_ani_set_spur_immunity_level(ah, 663 ath5k_ani_set_spur_immunity_level(ah,
659 ah->ah_sc->ani_state.max_spur_level); 664 ah->ani_state.max_spur_level);
660 ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL); 665 ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL);
661 ath5k_ani_set_ofdm_weak_signal_detection(ah, false); 666 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
662 ath5k_ani_set_cck_weak_signal_detection(ah, false); 667 ath5k_ani_set_cck_weak_signal_detection(ah, false);
663 } else if (mode == ATH5K_ANI_MODE_AUTO) { 668 } else if (mode == ATH5K_ANI_MODE_AUTO) {
664 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI auto\n"); 669 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_ANI, "ANI auto\n");
665 ath5k_ani_set_noise_immunity_level(ah, 0); 670 ath5k_ani_set_noise_immunity_level(ah, 0);
666 ath5k_ani_set_spur_immunity_level(ah, 0); 671 ath5k_ani_set_spur_immunity_level(ah, 0);
667 ath5k_ani_set_firstep_level(ah, 0); 672 ath5k_ani_set_firstep_level(ah, 0);
@@ -687,7 +692,7 @@ ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode)
687 ~AR5K_RX_FILTER_PHYERR); 692 ~AR5K_RX_FILTER_PHYERR);
688 } 693 }
689 694
690 ah->ah_sc->ani_state.ani_mode = mode; 695 ah->ani_state.ani_mode = mode;
691} 696}
692 697
693 698
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index bb50700436fe..277d5cbe0068 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -18,14 +18,16 @@
18#ifndef _ATH5K_H 18#ifndef _ATH5K_H
19#define _ATH5K_H 19#define _ATH5K_H
20 20
21/* TODO: Clean up channel debuging -doesn't work anyway- and start 21/* TODO: Clean up channel debugging (doesn't work anyway) and start
22 * working on reg. control code using all available eeprom information 22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */ 23 * (rev. engineering needed) */
24#define CHAN_DEBUG 0 24#define CHAN_DEBUG 0
25 25
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/interrupt.h>
27#include <linux/types.h> 28#include <linux/types.h>
28#include <linux/average.h> 29#include <linux/average.h>
30#include <linux/leds.h>
29#include <net/mac80211.h> 31#include <net/mac80211.h>
30 32
31/* RX/TX descriptor hw structs 33/* RX/TX descriptor hw structs
@@ -36,43 +38,46 @@
36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 38 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
37 * and clean up common bits, then introduce set/get functions in eeprom.c */ 39 * and clean up common bits, then introduce set/get functions in eeprom.c */
38#include "eeprom.h" 40#include "eeprom.h"
41#include "debug.h"
39#include "../ath.h" 42#include "../ath.h"
43#include "ani.h"
40 44
41/* PCI IDs */ 45/* PCI IDs */
42#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 46#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
43#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 47#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
44#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 48#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
45#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 49#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
46#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 50#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
47#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 51#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
48#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 52#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
49#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 53#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
50#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 54#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 55#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
52#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 56#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
53#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 57#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 58#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
55#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 59#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 60#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 61#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
58#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 62#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 63#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 64#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 65#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 66#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 67#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
64#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 68#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
65#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 69#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
66#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 70#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
67#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 71#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
68#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 72#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
69#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 73#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
70 74
71/****************************\ 75/****************************\
72 GENERIC DRIVER DEFINITIONS 76 GENERIC DRIVER DEFINITIONS
73\****************************/ 77\****************************/
74 78
75#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 79#define ATH5K_PRINTF(fmt, ...) \
80 printk(KERN_WARNING "%s: " fmt, __func__, ##__VA_ARGS__)
76 81
77#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 82#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
78 printk(_level "ath5k %s: " _fmt, \ 83 printk(_level "ath5k %s: " _fmt, \
@@ -155,7 +160,7 @@
155} while (0) 160} while (0)
156 161
157/* 162/*
158 * Some tuneable values (these should be changeable by the user) 163 * Some tunable values (these should be changeable by the user)
159 * TODO: Make use of them and add more options OR use debug/configfs 164 * TODO: Make use of them and add more options OR use debug/configfs
160 */ 165 */
161#define AR5K_TUNE_DMA_BEACON_RESP 2 166#define AR5K_TUNE_DMA_BEACON_RESP 2
@@ -170,8 +175,8 @@
170#define AR5K_TUNE_RSSI_THRES 129 175#define AR5K_TUNE_RSSI_THRES 129
171/* This must be set when setting the RSSI threshold otherwise it can 176/* This must be set when setting the RSSI threshold otherwise it can
172 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 177 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
173 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 178 * the BMISS_THRES will be seen as 0, seems hardware doesn't keep
174 * track of it. Max value depends on harware. For AR5210 this is just 7. 179 * track of it. Max value depends on hardware. For AR5210 this is just 7.
175 * For AR5211+ this seems to be up to 255. */ 180 * For AR5211+ this seems to be up to 255. */
176#define AR5K_TUNE_BMISS_THRES 7 181#define AR5K_TUNE_BMISS_THRES 7
177#define AR5K_TUNE_REGISTER_DWELL_TIME 20000 182#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
@@ -361,7 +366,7 @@ struct ath5k_srev_name {
361/* 366/*
362 * Some of this information is based on Documentation from: 367 * Some of this information is based on Documentation from:
363 * 368 *
364 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 369 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
365 * 370 *
366 * Modulation for Atheros' eXtended Range - range enhancing extension that is 371 * Modulation for Atheros' eXtended Range - range enhancing extension that is
367 * supposed to double the distance an Atheros client device can keep a 372 * supposed to double the distance an Atheros client device can keep a
@@ -374,12 +379,12 @@ struct ath5k_srev_name {
374 * they are exclusive. 379 * they are exclusive.
375 * 380 *
376 */ 381 */
377#define MODULATION_XR 0x00000200 382#define MODULATION_XR 0x00000200
378/* 383/*
379 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 384 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
380 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 385 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
381 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 386 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
382 * channels. To use this feature your Access Point must also suport it. 387 * channels. To use this feature your Access Point must also support it.
383 * There is also a distinction between "static" and "dynamic" turbo modes: 388 * There is also a distinction between "static" and "dynamic" turbo modes:
384 * 389 *
385 * - Static: is the dumb version: devices set to this mode stick to it until 390 * - Static: is the dumb version: devices set to this mode stick to it until
@@ -495,9 +500,9 @@ enum ath5k_tx_queue {
495 */ 500 */
496enum ath5k_tx_queue_subtype { 501enum ath5k_tx_queue_subtype {
497 AR5K_WME_AC_BK = 0, /*Background traffic*/ 502 AR5K_WME_AC_BK = 0, /*Background traffic*/
498 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 503 AR5K_WME_AC_BE, /*Best-effort (normal) traffic*/
499 AR5K_WME_AC_VI, /*Video traffic*/ 504 AR5K_WME_AC_VI, /*Video traffic*/
500 AR5K_WME_AC_VO, /*Voice traffic*/ 505 AR5K_WME_AC_VO, /*Voice traffic*/
501}; 506};
502 507
503/* 508/*
@@ -537,6 +542,27 @@ enum ath5k_tx_queue_id {
537#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 542#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
538 543
539/* 544/*
545 * Data transmit queue state. One of these exists for each
546 * hardware transmit queue. Packets sent to us from above
547 * are assigned to queues based on their priority. Not all
548 * devices support a complete set of hardware transmit queues.
549 * For those devices the array sc_ac2q will map multiple
550 * priorities to fewer hardware queues (typically all to one
551 * hardware queue).
552 */
553struct ath5k_txq {
554 unsigned int qnum; /* hardware q number */
555 u32 *link; /* link ptr in last TX desc */
556 struct list_head q; /* transmit queue */
557 spinlock_t lock; /* lock on q and link */
558 bool setup;
559 int txq_len; /* number of queued buffers */
560 int txq_max; /* max allowed num of queued buffers */
561 bool txq_poll_mark;
562 unsigned int txq_stuck; /* informational counter */
563};
564
565/*
540 * A struct to hold tx queue's parameters 566 * A struct to hold tx queue's parameters
541 */ 567 */
542struct ath5k_txq_info { 568struct ath5k_txq_info {
@@ -616,8 +642,8 @@ struct ath5k_rx_status {
616#define AR5K_RXERR_FIFO 0x04 642#define AR5K_RXERR_FIFO 0x04
617#define AR5K_RXERR_DECRYPT 0x08 643#define AR5K_RXERR_DECRYPT 0x08
618#define AR5K_RXERR_MIC 0x10 644#define AR5K_RXERR_MIC 0x10
619#define AR5K_RXKEYIX_INVALID ((u8) - 1) 645#define AR5K_RXKEYIX_INVALID ((u8) -1)
620#define AR5K_TXKEYIX_INVALID ((u32) - 1) 646#define AR5K_TXKEYIX_INVALID ((u32) -1)
621 647
622 648
623/**************************\ 649/**************************\
@@ -678,17 +704,18 @@ struct ath5k_gain {
678#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 704#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
679#define CHANNEL_XR 0x0800 /* XR channel */ 705#define CHANNEL_XR 0x0800 /* XR channel */
680 706
681#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 707#define CHANNEL_A (CHANNEL_5GHZ | CHANNEL_OFDM)
682#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 708#define CHANNEL_B (CHANNEL_2GHZ | CHANNEL_CCK)
683#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 709#define CHANNEL_G (CHANNEL_2GHZ | CHANNEL_OFDM)
684#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 710#define CHANNEL_X (CHANNEL_5GHZ | CHANNEL_OFDM | CHANNEL_XR)
685 711
686#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ) 712#define CHANNEL_ALL (CHANNEL_OFDM | CHANNEL_CCK | \
713 CHANNEL_2GHZ | CHANNEL_5GHZ)
687 714
688#define CHANNEL_MODES CHANNEL_ALL 715#define CHANNEL_MODES CHANNEL_ALL
689 716
690/* 717/*
691 * Used internaly for reset_tx_queue). 718 * Used internally for ath5k_hw_reset_tx_queue().
692 * Also see struct struct ieee80211_channel. 719 * Also see struct struct ieee80211_channel.
693 */ 720 */
694#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 721#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
@@ -710,7 +737,7 @@ struct ath5k_athchan_2ghz {
710\******************/ 737\******************/
711 738
712/** 739/**
713 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 740 * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
714 * 741 *
715 * The rate code is used to get the RX rate or set the TX rate on the 742 * The rate code is used to get the RX rate or set the TX rate on the
716 * hardware descriptors. It is also used for internal modulation control 743 * hardware descriptors. It is also used for internal modulation control
@@ -767,6 +794,7 @@ struct ath5k_athchan_2ghz {
767 */ 794 */
768 795
769#define AR5K_KEYCACHE_SIZE 8 796#define AR5K_KEYCACHE_SIZE 8
797extern int ath5k_modparam_nohwcrypt;
770 798
771/***********************\ 799/***********************\
772 HW RELATED DEFINITIONS 800 HW RELATED DEFINITIONS
@@ -775,11 +803,11 @@ struct ath5k_athchan_2ghz {
775/* 803/*
776 * Misc definitions 804 * Misc definitions
777 */ 805 */
778#define AR5K_RSSI_EP_MULTIPLIER (1<<7) 806#define AR5K_RSSI_EP_MULTIPLIER (1 << 7)
779 807
780#define AR5K_ASSERT_ENTRY(_e, _s) do { \ 808#define AR5K_ASSERT_ENTRY(_e, _s) do { \
781 if (_e >= _s) \ 809 if (_e >= _s) \
782 return (false); \ 810 return false; \
783} while (0) 811} while (0)
784 812
785/* 813/*
@@ -790,52 +818,52 @@ struct ath5k_athchan_2ghz {
790 * enum ath5k_int - Hardware interrupt masks helpers 818 * enum ath5k_int - Hardware interrupt masks helpers
791 * 819 *
792 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 820 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
793 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 821 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
794 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 822 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
795 * @AR5K_INT_RXNOFRM: No frame received (?) 823 * @AR5K_INT_RXNOFRM: No frame received (?)
796 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 824 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
797 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 825 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
798 * LinkPtr is NULL. For more details, refer to: 826 * LinkPtr is NULL. For more details, refer to:
799 * http://www.freepatentsonline.com/20030225739.html 827 * http://www.freepatentsonline.com/20030225739.html
800 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 828 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
801 * Note that Rx overrun is not always fatal, on some chips we can continue 829 * Note that Rx overrun is not always fatal, on some chips we can continue
802 * operation without reseting the card, that's why int_fatal is not 830 * operation without resetting the card, that's why int_fatal is not
803 * common for all chips. 831 * common for all chips.
804 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 832 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
805 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 833 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
806 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 834 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
807 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 835 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
808 * We currently do increments on interrupt by 836 * We currently do increments on interrupt by
809 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 837 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
810 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 838 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
811 * one of the PHY error counters reached the maximum value and should be 839 * one of the PHY error counters reached the maximum value and should be
812 * read and cleared. 840 * read and cleared.
813 * @AR5K_INT_RXPHY: RX PHY Error 841 * @AR5K_INT_RXPHY: RX PHY Error
814 * @AR5K_INT_RXKCM: RX Key cache miss 842 * @AR5K_INT_RXKCM: RX Key cache miss
815 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 843 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
816 * beacon that must be handled in software. The alternative is if you 844 * beacon that must be handled in software. The alternative is if you
817 * have VEOL support, in that case you let the hardware deal with things. 845 * have VEOL support, in that case you let the hardware deal with things.
818 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 846 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
819 * beacons from the AP have associated with, we should probably try to 847 * beacons from the AP have associated with, we should probably try to
820 * reassociate. When in IBSS mode this might mean we have not received 848 * reassociate. When in IBSS mode this might mean we have not received
821 * any beacons from any local stations. Note that every station in an 849 * any beacons from any local stations. Note that every station in an
822 * IBSS schedules to send beacons at the Target Beacon Transmission Time 850 * IBSS schedules to send beacons at the Target Beacon Transmission Time
823 * (TBTT) with a random backoff. 851 * (TBTT) with a random backoff.
824 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 852 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
825 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 853 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
826 * until properly handled 854 * until properly handled
827 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 855 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
828 * errors. These types of errors we can enable seem to be of type 856 * errors. These types of errors we can enable seem to be of type
829 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 857 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
830 * @AR5K_INT_GLOBAL: Used to clear and set the IER 858 * @AR5K_INT_GLOBAL: Used to clear and set the IER
831 * @AR5K_INT_NOCARD: signals the card has been removed 859 * @AR5K_INT_NOCARD: signals the card has been removed
832 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 860 * @AR5K_INT_COMMON: common interrupts shared among MACs with the same
833 * bit value 861 * bit value
834 * 862 *
835 * These are mapped to take advantage of some common bits 863 * These are mapped to take advantage of some common bits
836 * between the MACs, to be able to set intr properties 864 * between the MACs, to be able to set intr properties
837 * easier. Some of them are not used yet inside hw.c. Most map 865 * easier. Some of them are not used yet inside hw.c. Most map
838 * to the respective hw interrupt value as they are common amogst different 866 * to the respective hw interrupt value as they are common among different
839 * MACs. 867 * MACs.
840 */ 868 */
841enum ath5k_int { 869enum ath5k_int {
@@ -944,35 +972,6 @@ enum ath5k_power_mode {
944#define AR5K_SOFTLED_ON 0 972#define AR5K_SOFTLED_ON 0
945#define AR5K_SOFTLED_OFF 1 973#define AR5K_SOFTLED_OFF 1
946 974
947/*
948 * Chipset capabilities -see ath5k_hw_get_capability-
949 * get_capability function is not yet fully implemented
950 * in ath5k so most of these don't work yet...
951 * TODO: Implement these & merge with _TUNE_ stuff above
952 */
953enum ath5k_capability_type {
954 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
955 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
956 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
957 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
958 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
959 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
960 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
961 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
962 AR5K_CAP_BURST = 9, /* Supports packet bursting */
963 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
964 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
965 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
966 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
967 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
968 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
969 AR5K_CAP_XR = 16, /* Supports XR mode */
970 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
971 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
972 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
973 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
974};
975
976 975
977/* XXX: we *may* move cap_range stuff to struct wiphy */ 976/* XXX: we *may* move cap_range stuff to struct wiphy */
978struct ath5k_capabilities { 977struct ath5k_capabilities {
@@ -1009,8 +1008,7 @@ struct ath5k_capabilities {
1009 1008
1010/* size of noise floor history (keep it a power of two) */ 1009/* size of noise floor history (keep it a power of two) */
1011#define ATH5K_NF_CAL_HIST_MAX 8 1010#define ATH5K_NF_CAL_HIST_MAX 8
1012struct ath5k_nfcal_hist 1011struct ath5k_nfcal_hist {
1013{
1014 s16 index; /* current index into nfval */ 1012 s16 index; /* current index into nfval */
1015 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 1013 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1016}; 1014};
@@ -1025,9 +1023,66 @@ struct ath5k_avg_val {
1025 int avg_weight; 1023 int avg_weight;
1026}; 1024};
1027 1025
1028/***************************************\ 1026#define ATH5K_LED_MAX_NAME_LEN 31
1029 HARDWARE ABSTRACTION LAYER STRUCTURE 1027
1030\***************************************/ 1028/*
1029 * State for LED triggers
1030 */
1031struct ath5k_led {
1032 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
1033 struct ath5k_hw *ah; /* driver state */
1034 struct led_classdev led_dev; /* led classdev */
1035};
1036
1037/* Rfkill */
1038struct ath5k_rfkill {
1039 /* GPIO PIN for rfkill */
1040 u16 gpio;
1041 /* polarity of rfkill GPIO PIN */
1042 bool polarity;
1043 /* RFKILL toggle tasklet */
1044 struct tasklet_struct toggleq;
1045};
1046
1047/* statistics */
1048struct ath5k_statistics {
1049 /* antenna use */
1050 unsigned int antenna_rx[5]; /* frames count per antenna RX */
1051 unsigned int antenna_tx[5]; /* frames count per antenna TX */
1052
1053 /* frame errors */
1054 unsigned int rx_all_count; /* all RX frames, including errors */
1055 unsigned int tx_all_count; /* all TX frames, including errors */
1056 unsigned int rx_bytes_count; /* all RX bytes, including errored pkts
1057 * and the MAC headers for each packet
1058 */
1059 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
1060 * and the MAC headers and padding for
1061 * each packet.
1062 */
1063 unsigned int rxerr_crc;
1064 unsigned int rxerr_phy;
1065 unsigned int rxerr_phy_code[32];
1066 unsigned int rxerr_fifo;
1067 unsigned int rxerr_decrypt;
1068 unsigned int rxerr_mic;
1069 unsigned int rxerr_proc;
1070 unsigned int rxerr_jumbo;
1071 unsigned int txerr_retry;
1072 unsigned int txerr_fifo;
1073 unsigned int txerr_filt;
1074
1075 /* MIB counters */
1076 unsigned int ack_fail;
1077 unsigned int rts_fail;
1078 unsigned int rts_ok;
1079 unsigned int fcs_error;
1080 unsigned int beacons;
1081
1082 unsigned int mib_intr;
1083 unsigned int rxorn_intr;
1084 unsigned int rxeol_intr;
1085};
1031 1086
1032/* 1087/*
1033 * Misc defines 1088 * Misc defines
@@ -1036,12 +1091,114 @@ struct ath5k_avg_val {
1036#define AR5K_MAX_GPIO 10 1091#define AR5K_MAX_GPIO 10
1037#define AR5K_MAX_RF_BANKS 8 1092#define AR5K_MAX_RF_BANKS 8
1038 1093
1039/* TODO: Clean up and merge with ath5k_softc */ 1094#if CHAN_DEBUG
1095#define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
1096#else
1097#define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
1098#endif
1099
1100#define ATH_RXBUF 40 /* number of RX buffers */
1101#define ATH_TXBUF 200 /* number of TX buffers */
1102#define ATH_BCBUF 4 /* number of beacon buffers */
1103#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
1104#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
1105
1106/* Driver state associated with an instance of a device */
1040struct ath5k_hw { 1107struct ath5k_hw {
1041 struct ath_common common; 1108 struct ath_common common;
1042 1109
1043 struct ath5k_softc *ah_sc; 1110 struct pci_dev *pdev;
1044 void __iomem *ah_iobase; 1111 struct device *dev; /* for dma mapping */
1112 int irq;
1113 u16 devid;
1114 void __iomem *iobase; /* address of the device */
1115 struct mutex lock; /* dev-level lock */
1116 struct ieee80211_hw *hw; /* IEEE 802.11 common */
1117 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1118 struct ieee80211_channel channels[ATH_CHAN_MAX];
1119 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1120 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1121 enum nl80211_iftype opmode;
1122
1123#ifdef CONFIG_ATH5K_DEBUG
1124 struct ath5k_dbg_info debug; /* debug info */
1125#endif /* CONFIG_ATH5K_DEBUG */
1126
1127 struct ath5k_buf *bufptr; /* allocated buffer ptr */
1128 struct ath5k_desc *desc; /* TX/RX descriptors */
1129 dma_addr_t desc_daddr; /* DMA (physical) address */
1130 size_t desc_len; /* size of TX/RX descriptors */
1131
1132 DECLARE_BITMAP(status, 6);
1133#define ATH_STAT_INVALID 0 /* disable hardware accesses */
1134#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
1135#define ATH_STAT_PROMISC 2
1136#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
1137#define ATH_STAT_STARTED 4 /* opened & irqs enabled */
1138#define ATH_STAT_2G_DISABLED 5 /* multiband radio without 2G */
1139
1140 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
1141 struct ieee80211_channel *curchan; /* current h/w channel */
1142
1143 u16 nvifs;
1144
1145 enum ath5k_int imask; /* interrupt mask copy */
1146
1147 spinlock_t irqlock;
1148 bool rx_pending; /* rx tasklet pending */
1149 bool tx_pending; /* tx tasklet pending */
1150
1151 u8 lladdr[ETH_ALEN];
1152 u8 bssidmask[ETH_ALEN];
1153
1154 unsigned int led_pin, /* GPIO pin for driving LED */
1155 led_on; /* pin setting for LED on */
1156
1157 struct work_struct reset_work; /* deferred chip reset */
1158
1159 unsigned int rxbufsize; /* rx size based on mtu */
1160 struct list_head rxbuf; /* receive buffer */
1161 spinlock_t rxbuflock;
1162 u32 *rxlink; /* link ptr in last RX desc */
1163 struct tasklet_struct rxtq; /* rx intr tasklet */
1164 struct ath5k_led rx_led; /* rx led */
1165
1166 struct list_head txbuf; /* transmit buffer */
1167 spinlock_t txbuflock;
1168 unsigned int txbuf_len; /* buf count in txbuf list */
1169 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
1170 struct tasklet_struct txtq; /* tx intr tasklet */
1171 struct ath5k_led tx_led; /* tx led */
1172
1173 struct ath5k_rfkill rf_kill;
1174
1175 struct tasklet_struct calib; /* calibration tasklet */
1176
1177 spinlock_t block; /* protects beacon */
1178 struct tasklet_struct beacontq; /* beacon intr tasklet */
1179 struct list_head bcbuf; /* beacon buffer */
1180 struct ieee80211_vif *bslot[ATH_BCBUF];
1181 u16 num_ap_vifs;
1182 u16 num_adhoc_vifs;
1183 unsigned int bhalq, /* SW q for outgoing beacons */
1184 bmisscount, /* missed beacon transmits */
1185 bintval, /* beacon interval in TU */
1186 bsent;
1187 unsigned int nexttbtt; /* next beacon time in TU */
1188 struct ath5k_txq *cabq; /* content after beacon */
1189
1190 int power_level; /* Requested tx power in dBm */
1191 bool assoc; /* associate state */
1192 bool enable_beacon; /* true if beacons are on */
1193
1194 struct ath5k_statistics stats;
1195
1196 struct ath5k_ani_state ani_state;
1197 struct tasklet_struct ani_tasklet; /* ANI calibration */
1198
1199 struct delayed_work tx_complete_work;
1200
1201 struct survey_info survey; /* collected survey info */
1045 1202
1046 enum ath5k_int ah_imr; 1203 enum ath5k_int ah_imr;
1047 1204
@@ -1065,6 +1222,8 @@ struct ath5k_hw {
1065 u8 ah_retry_long; 1222 u8 ah_retry_long;
1066 u8 ah_retry_short; 1223 u8 ah_retry_short;
1067 1224
1225 u32 ah_use_32khz_clock;
1226
1068 u8 ah_coverage_class; 1227 u8 ah_coverage_class;
1069 bool ah_ack_bitrate_high; 1228 bool ah_ack_bitrate_high;
1070 u8 ah_bwmode; 1229 u8 ah_bwmode;
@@ -1168,43 +1327,43 @@ struct ath_bus_ops {
1168extern const struct ieee80211_ops ath5k_hw_ops; 1327extern const struct ieee80211_ops ath5k_hw_ops;
1169 1328
1170/* Initialization and detach functions */ 1329/* Initialization and detach functions */
1171int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops); 1330int ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops);
1172void ath5k_deinit_softc(struct ath5k_softc *sc); 1331void ath5k_deinit_softc(struct ath5k_hw *ah);
1173int ath5k_hw_init(struct ath5k_softc *sc); 1332int ath5k_hw_init(struct ath5k_hw *ah);
1174void ath5k_hw_deinit(struct ath5k_hw *ah); 1333void ath5k_hw_deinit(struct ath5k_hw *ah);
1175 1334
1176int ath5k_sysfs_register(struct ath5k_softc *sc); 1335int ath5k_sysfs_register(struct ath5k_hw *ah);
1177void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1336void ath5k_sysfs_unregister(struct ath5k_hw *ah);
1178 1337
1179/* base.c */ 1338/* base.c */
1180struct ath5k_buf; 1339struct ath5k_buf;
1181struct ath5k_txq; 1340struct ath5k_txq;
1182 1341
1183void set_beacon_filter(struct ieee80211_hw *hw, bool enable); 1342void ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable);
1184bool ath_any_vif_assoc(struct ath5k_softc *sc); 1343bool ath5k_any_vif_assoc(struct ath5k_hw *ah);
1185void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1344void ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1186 struct ath5k_txq *txq); 1345 struct ath5k_txq *txq);
1187int ath5k_init_hw(struct ath5k_softc *sc); 1346int ath5k_start(struct ieee80211_hw *hw);
1188int ath5k_stop_hw(struct ath5k_softc *sc); 1347void ath5k_stop(struct ieee80211_hw *hw);
1189void ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif); 1348void ath5k_mode_setup(struct ath5k_hw *ah, struct ieee80211_vif *vif);
1190void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, 1349void ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
1191 struct ieee80211_vif *vif); 1350 struct ieee80211_vif *vif);
1192int ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan); 1351int ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan);
1193void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); 1352void ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf);
1194int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1353int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1195void ath5k_beacon_config(struct ath5k_softc *sc); 1354void ath5k_beacon_config(struct ath5k_hw *ah);
1196void ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf); 1355void ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf);
1197void ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf); 1356void ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf);
1198 1357
1199/*Chip id helper functions */ 1358/*Chip id helper functions */
1200const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val); 1359const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
1201int ath5k_hw_read_srev(struct ath5k_hw *ah); 1360int ath5k_hw_read_srev(struct ath5k_hw *ah);
1202 1361
1203/* LED functions */ 1362/* LED functions */
1204int ath5k_init_leds(struct ath5k_softc *sc); 1363int ath5k_init_leds(struct ath5k_hw *ah);
1205void ath5k_led_enable(struct ath5k_softc *sc); 1364void ath5k_led_enable(struct ath5k_hw *ah);
1206void ath5k_led_off(struct ath5k_softc *sc); 1365void ath5k_led_off(struct ath5k_hw *ah);
1207void ath5k_unregister_leds(struct ath5k_softc *sc); 1366void ath5k_unregister_leds(struct ath5k_hw *ah);
1208 1367
1209 1368
1210/* Reset Functions */ 1369/* Reset Functions */
@@ -1253,7 +1412,7 @@ int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
1253 int len, struct ieee80211_rate *rate, bool shortpre); 1412 int len, struct ieee80211_rate *rate, bool shortpre);
1254unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); 1413unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
1255unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); 1414unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
1256extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1415int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1257void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1416void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1258/* RX filter control*/ 1417/* RX filter control*/
1259int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1418int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
@@ -1318,9 +1477,6 @@ void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1318 1477
1319/* Misc functions TODO: Cleanup */ 1478/* Misc functions TODO: Cleanup */
1320int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1479int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1321int ath5k_hw_get_capability(struct ath5k_hw *ah,
1322 enum ath5k_capability_type cap_type, u32 capability,
1323 u32 *result);
1324int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1480int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1325int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1481int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1326 1482
@@ -1356,17 +1512,17 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1356 u8 mode, bool fast); 1512 u8 mode, bool fast);
1357 1513
1358/* 1514/*
1359 * Functions used internaly 1515 * Functions used internally
1360 */ 1516 */
1361 1517
1362static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1518static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1363{ 1519{
1364 return &ah->common; 1520 return &ah->common;
1365} 1521}
1366 1522
1367static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1523static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1368{ 1524{
1369 return &(ath5k_hw_common(ah)->regulatory); 1525 return &(ath5k_hw_common(ah)->regulatory);
1370} 1526}
1371 1527
1372#ifdef CONFIG_ATHEROS_AR231X 1528#ifdef CONFIG_ATHEROS_AR231X
@@ -1377,10 +1533,10 @@ static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
1377 /* On AR2315 and AR2317 the PCI clock domain registers 1533 /* On AR2315 and AR2317 the PCI clock domain registers
1378 * are outside of the WMAC register space */ 1534 * are outside of the WMAC register space */
1379 if (unlikely((reg >= 0x4000) && (reg < 0x5000) && 1535 if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
1380 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6))) 1536 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
1381 return AR5K_AR2315_PCI_BASE + reg; 1537 return AR5K_AR2315_PCI_BASE + reg;
1382 1538
1383 return ah->ah_iobase + reg; 1539 return ah->iobase + reg;
1384} 1540}
1385 1541
1386static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1542static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
@@ -1397,12 +1553,12 @@ static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1397 1553
1398static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1554static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1399{ 1555{
1400 return ioread32(ah->ah_iobase + reg); 1556 return ioread32(ah->iobase + reg);
1401} 1557}
1402 1558
1403static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1559static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1404{ 1560{
1405 iowrite32(val, ah->ah_iobase + reg); 1561 iowrite32(val, ah->iobase + reg);
1406} 1562}
1407 1563
1408#endif 1564#endif
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
index 1588401de3c4..f8a6b380d96d 100644
--- a/drivers/net/wireless/ath/ath5k/attach.c
+++ b/drivers/net/wireless/ath/ath5k/attach.c
@@ -59,7 +59,7 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
59 cur_val = ath5k_hw_reg_read(ah, cur_reg); 59 cur_val = ath5k_hw_reg_read(ah, cur_reg);
60 60
61 if (cur_val != var_pattern) { 61 if (cur_val != var_pattern) {
62 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n"); 62 ATH5K_ERR(ah, "POST Failed !!!\n");
63 return -EAGAIN; 63 return -EAGAIN;
64 } 64 }
65 65
@@ -74,7 +74,7 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
74 cur_val = ath5k_hw_reg_read(ah, cur_reg); 74 cur_val = ath5k_hw_reg_read(ah, cur_reg);
75 75
76 if (cur_val != var_pattern) { 76 if (cur_val != var_pattern) {
77 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n"); 77 ATH5K_ERR(ah, "POST Failed !!!\n");
78 return -EAGAIN; 78 return -EAGAIN;
79 } 79 }
80 80
@@ -95,18 +95,18 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
95/** 95/**
96 * ath5k_hw_init - Check if hw is supported and init the needed structs 96 * ath5k_hw_init - Check if hw is supported and init the needed structs
97 * 97 *
98 * @sc: The &struct ath5k_softc we got from the driver's init_softc function 98 * @ah: The &struct ath5k_hw we got from the driver's init_softc function
99 * 99 *
100 * Check if the device is supported, perform a POST and initialize the needed 100 * Check if the device is supported, perform a POST and initialize the needed
101 * structs. Returns -ENOMEM if we don't have memory for the needed structs, 101 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
102 * -ENODEV if the device is not supported or prints an error msg if something 102 * -ENODEV if the device is not supported or prints an error msg if something
103 * else went wrong. 103 * else went wrong.
104 */ 104 */
105int ath5k_hw_init(struct ath5k_softc *sc) 105int ath5k_hw_init(struct ath5k_hw *ah)
106{ 106{
107 struct ath5k_hw *ah = sc->ah; 107 static const u8 zero_mac[ETH_ALEN] = { };
108 struct ath_common *common = ath5k_hw_common(ah); 108 struct ath_common *common = ath5k_hw_common(ah);
109 struct pci_dev *pdev = sc->pdev; 109 struct pci_dev *pdev = ah->pdev;
110 struct ath5k_eeprom_info *ee; 110 struct ath5k_eeprom_info *ee;
111 int ret; 111 int ret;
112 u32 srev; 112 u32 srev;
@@ -122,8 +122,8 @@ int ath5k_hw_init(struct ath5k_softc *sc)
122 ah->ah_retry_long = AR5K_INIT_RETRY_LONG; 122 ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
123 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT; 123 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
124 ah->ah_noise_floor = -95; /* until first NF calibration is run */ 124 ah->ah_noise_floor = -95; /* until first NF calibration is run */
125 sc->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO; 125 ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
126 ah->ah_current_channel = &sc->channels[0]; 126 ah->ah_current_channel = &ah->channels[0];
127 127
128 /* 128 /*
129 * Find the mac version 129 * Find the mac version
@@ -191,7 +191,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
191 break; 191 break;
192 case AR5K_SREV_RAD_5424: 192 case AR5K_SREV_RAD_5424:
193 if (ah->ah_mac_version == AR5K_SREV_AR2425 || 193 if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
194 ah->ah_mac_version == AR5K_SREV_AR2417){ 194 ah->ah_mac_version == AR5K_SREV_AR2417) {
195 ah->ah_radio = AR5K_RF2425; 195 ah->ah_radio = AR5K_RF2425;
196 ah->ah_single_chip = true; 196 ah->ah_single_chip = true;
197 } else { 197 } else {
@@ -210,43 +210,42 @@ int ath5k_hw_init(struct ath5k_softc *sc)
210 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 210 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
211 CHANNEL_2GHZ); 211 CHANNEL_2GHZ);
212 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) || 212 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
213 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) || 213 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
214 ah->ah_phy_revision == AR5K_SREV_PHY_2425) { 214 ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
215 ah->ah_radio = AR5K_RF2425; 215 ah->ah_radio = AR5K_RF2425;
216 ah->ah_single_chip = true; 216 ah->ah_single_chip = true;
217 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425; 217 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
218 } else if (srev == AR5K_SREV_AR5213A && 218 } else if (srev == AR5K_SREV_AR5213A &&
219 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) { 219 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
220 ah->ah_radio = AR5K_RF5112; 220 ah->ah_radio = AR5K_RF5112;
221 ah->ah_single_chip = false; 221 ah->ah_single_chip = false;
222 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B; 222 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
223 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) || 223 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
224 ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) { 224 ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
225 ah->ah_radio = AR5K_RF2316; 225 ah->ah_radio = AR5K_RF2316;
226 ah->ah_single_chip = true; 226 ah->ah_single_chip = true;
227 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316; 227 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
228 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) || 228 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
229 ah->ah_phy_revision == AR5K_SREV_PHY_5413) { 229 ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
230 ah->ah_radio = AR5K_RF5413; 230 ah->ah_radio = AR5K_RF5413;
231 ah->ah_single_chip = true; 231 ah->ah_single_chip = true;
232 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413; 232 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
233 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) || 233 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
234 ah->ah_phy_revision == AR5K_SREV_PHY_2413) { 234 ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
235 ah->ah_radio = AR5K_RF2413; 235 ah->ah_radio = AR5K_RF2413;
236 ah->ah_single_chip = true; 236 ah->ah_single_chip = true;
237 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413; 237 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
238 } else { 238 } else {
239 ATH5K_ERR(sc, "Couldn't identify radio revision.\n"); 239 ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
240 ret = -ENODEV; 240 ret = -ENODEV;
241 goto err; 241 goto err;
242 } 242 }
243 } 243 }
244 244
245 245
246 /* Return on unsuported chips (unsupported eeprom etc) */ 246 /* Return on unsupported chips (unsupported eeprom etc) */
247 if ((srev >= AR5K_SREV_AR5416) && 247 if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
248 (srev < AR5K_SREV_AR2425)) { 248 ATH5K_ERR(ah, "Device not yet supported.\n");
249 ATH5K_ERR(sc, "Device not yet supported.\n");
250 ret = -ENODEV; 249 ret = -ENODEV;
251 goto err; 250 goto err;
252 } 251 }
@@ -268,7 +267,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
268 */ 267 */
269 ret = ath5k_eeprom_init(ah); 268 ret = ath5k_eeprom_init(ah);
270 if (ret) { 269 if (ret) {
271 ATH5K_ERR(sc, "unable to init EEPROM\n"); 270 ATH5K_ERR(ah, "unable to init EEPROM\n");
272 goto err; 271 goto err;
273 } 272 }
274 273
@@ -285,7 +284,7 @@ int ath5k_hw_init(struct ath5k_softc *sc)
285 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES); 284 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
286 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES); 285 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
287 286
288 /* If serdes programing is enabled, increase PCI-E 287 /* If serdes programming is enabled, increase PCI-E
289 * tx power for systems with long trace from host 288 * tx power for systems with long trace from host
290 * to minicard connector. */ 289 * to minicard connector. */
291 if (ee->ee_serdes) 290 if (ee->ee_serdes)
@@ -309,17 +308,17 @@ int ath5k_hw_init(struct ath5k_softc *sc)
309 /* Get misc capabilities */ 308 /* Get misc capabilities */
310 ret = ath5k_hw_set_capabilities(ah); 309 ret = ath5k_hw_set_capabilities(ah);
311 if (ret) { 310 if (ret) {
312 ATH5K_ERR(sc, "unable to get device capabilities\n"); 311 ATH5K_ERR(ah, "unable to get device capabilities\n");
313 goto err; 312 goto err;
314 } 313 }
315 314
316 if (test_bit(ATH_STAT_2G_DISABLED, sc->status)) { 315 if (test_bit(ATH_STAT_2G_DISABLED, ah->status)) {
317 __clear_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode); 316 __clear_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode);
318 __clear_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode); 317 __clear_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode);
319 } 318 }
320 319
321 /* Crypto settings */ 320 /* Crypto settings */
322 common->keymax = (sc->ah->ah_version == AR5K_AR5210 ? 321 common->keymax = (ah->ah_version == AR5K_AR5210 ?
323 AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211); 322 AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
324 323
325 if (srev >= AR5K_SREV_AR5212_V4 && 324 if (srev >= AR5K_SREV_AR5212_V4 &&
@@ -334,12 +333,12 @@ int ath5k_hw_init(struct ath5k_softc *sc)
334 } 333 }
335 334
336 /* MAC address is cleared until add_interface */ 335 /* MAC address is cleared until add_interface */
337 ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){}); 336 ath5k_hw_set_lladdr(ah, zero_mac);
338 337
339 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */ 338 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
340 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN); 339 memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
341 ath5k_hw_set_bssid(ah); 340 ath5k_hw_set_bssid(ah);
342 ath5k_hw_set_opmode(ah, sc->opmode); 341 ath5k_hw_set_opmode(ah, ah->opmode);
343 342
344 ath5k_hw_rfgain_opt_init(ah); 343 ath5k_hw_rfgain_opt_init(ah);
345 344
@@ -360,7 +359,7 @@ err:
360 */ 359 */
361void ath5k_hw_deinit(struct ath5k_hw *ah) 360void ath5k_hw_deinit(struct ath5k_hw *ah)
362{ 361{
363 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status); 362 __set_bit(ATH_STAT_INVALID, ah->status);
364 363
365 if (ah->ah_rf_banks != NULL) 364 if (ah->ah_rf_banks != NULL)
366 kfree(ah->ah_rf_banks); 365 kfree(ah->ah_rf_banks);
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index b6c5d3715b96..f54dff44ed50 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -42,6 +42,7 @@
42 42
43#include <linux/module.h> 43#include <linux/module.h>
44#include <linux/delay.h> 44#include <linux/delay.h>
45#include <linux/dma-mapping.h>
45#include <linux/hardirq.h> 46#include <linux/hardirq.h>
46#include <linux/if.h> 47#include <linux/if.h>
47#include <linux/io.h> 48#include <linux/io.h>
@@ -85,10 +86,8 @@ MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
85MODULE_LICENSE("Dual BSD/GPL"); 86MODULE_LICENSE("Dual BSD/GPL");
86 87
87static int ath5k_init(struct ieee80211_hw *hw); 88static int ath5k_init(struct ieee80211_hw *hw);
88static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 89static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
89 bool skip_pcu); 90 bool skip_pcu);
90int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
91void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
92 91
93/* Known SREVs */ 92/* Known SREVs */
94static const struct ath5k_srev_name srev_names[] = { 93static const struct ath5k_srev_name srev_names[] = {
@@ -239,8 +238,8 @@ static const struct ath_ops ath5k_common_ops = {
239static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 238static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
240{ 239{
241 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
242 struct ath5k_softc *sc = hw->priv; 241 struct ath5k_hw *ah = hw->priv;
243 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); 242 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
244 243
245 return ath_reg_notifier_apply(wiphy, request, regulatory); 244 return ath_reg_notifier_apply(wiphy, request, regulatory);
246} 245}
@@ -290,7 +289,7 @@ ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
290 band = IEEE80211_BAND_2GHZ; 289 band = IEEE80211_BAND_2GHZ;
291 break; 290 break;
292 default: 291 default:
293 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 292 ATH5K_WARN(ah, "bad mode, not copying channels\n");
294 return 0; 293 return 0;
295 } 294 }
296 295
@@ -328,51 +327,50 @@ ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
328} 327}
329 328
330static void 329static void
331ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 330ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
332{ 331{
333 u8 i; 332 u8 i;
334 333
335 for (i = 0; i < AR5K_MAX_RATES; i++) 334 for (i = 0; i < AR5K_MAX_RATES; i++)
336 sc->rate_idx[b->band][i] = -1; 335 ah->rate_idx[b->band][i] = -1;
337 336
338 for (i = 0; i < b->n_bitrates; i++) { 337 for (i = 0; i < b->n_bitrates; i++) {
339 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 338 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
340 if (b->bitrates[i].hw_value_short) 339 if (b->bitrates[i].hw_value_short)
341 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 340 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
342 } 341 }
343} 342}
344 343
345static int 344static int
346ath5k_setup_bands(struct ieee80211_hw *hw) 345ath5k_setup_bands(struct ieee80211_hw *hw)
347{ 346{
348 struct ath5k_softc *sc = hw->priv; 347 struct ath5k_hw *ah = hw->priv;
349 struct ath5k_hw *ah = sc->ah;
350 struct ieee80211_supported_band *sband; 348 struct ieee80211_supported_band *sband;
351 int max_c, count_c = 0; 349 int max_c, count_c = 0;
352 int i; 350 int i;
353 351
354 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 352 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
355 max_c = ARRAY_SIZE(sc->channels); 353 max_c = ARRAY_SIZE(ah->channels);
356 354
357 /* 2GHz band */ 355 /* 2GHz band */
358 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 356 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
359 sband->band = IEEE80211_BAND_2GHZ; 357 sband->band = IEEE80211_BAND_2GHZ;
360 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 358 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
361 359
362 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 360 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
363 /* G mode */ 361 /* G mode */
364 memcpy(sband->bitrates, &ath5k_rates[0], 362 memcpy(sband->bitrates, &ath5k_rates[0],
365 sizeof(struct ieee80211_rate) * 12); 363 sizeof(struct ieee80211_rate) * 12);
366 sband->n_bitrates = 12; 364 sband->n_bitrates = 12;
367 365
368 sband->channels = sc->channels; 366 sband->channels = ah->channels;
369 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
370 AR5K_MODE_11G, max_c); 368 AR5K_MODE_11G, max_c);
371 369
372 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
373 count_c = sband->n_channels; 371 count_c = sband->n_channels;
374 max_c -= count_c; 372 max_c -= count_c;
375 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 373 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
376 /* B mode */ 374 /* B mode */
377 memcpy(sband->bitrates, &ath5k_rates[0], 375 memcpy(sband->bitrates, &ath5k_rates[0],
378 sizeof(struct ieee80211_rate) * 4); 376 sizeof(struct ieee80211_rate) * 4);
@@ -391,7 +389,7 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
391 } 389 }
392 } 390 }
393 391
394 sband->channels = sc->channels; 392 sband->channels = ah->channels;
395 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
396 AR5K_MODE_11B, max_c); 394 AR5K_MODE_11B, max_c);
397 395
@@ -399,27 +397,27 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
399 count_c = sband->n_channels; 397 count_c = sband->n_channels;
400 max_c -= count_c; 398 max_c -= count_c;
401 } 399 }
402 ath5k_setup_rate_idx(sc, sband); 400 ath5k_setup_rate_idx(ah, sband);
403 401
404 /* 5GHz band, A mode */ 402 /* 5GHz band, A mode */
405 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 403 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
406 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 404 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
407 sband->band = IEEE80211_BAND_5GHZ; 405 sband->band = IEEE80211_BAND_5GHZ;
408 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 406 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
409 407
410 memcpy(sband->bitrates, &ath5k_rates[4], 408 memcpy(sband->bitrates, &ath5k_rates[4],
411 sizeof(struct ieee80211_rate) * 8); 409 sizeof(struct ieee80211_rate) * 8);
412 sband->n_bitrates = 8; 410 sband->n_bitrates = 8;
413 411
414 sband->channels = &sc->channels[count_c]; 412 sband->channels = &ah->channels[count_c];
415 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
416 AR5K_MODE_11A, max_c); 414 AR5K_MODE_11A, max_c);
417 415
418 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
419 } 417 }
420 ath5k_setup_rate_idx(sc, sband); 418 ath5k_setup_rate_idx(ah, sband);
421 419
422 ath5k_debug_dump_bands(sc); 420 ath5k_debug_dump_bands(ah);
423 421
424 return 0; 422 return 0;
425} 423}
@@ -429,14 +427,14 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
429 * To accomplish this we must first cleanup any pending DMA, 427 * To accomplish this we must first cleanup any pending DMA,
430 * then restart stuff after a la ath5k_init. 428 * then restart stuff after a la ath5k_init.
431 * 429 *
432 * Called with sc->lock. 430 * Called with ah->lock.
433 */ 431 */
434int 432int
435ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 433ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
436{ 434{
437 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 435 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
438 "channel set, resetting (%u -> %u MHz)\n", 436 "channel set, resetting (%u -> %u MHz)\n",
439 sc->curchan->center_freq, chan->center_freq); 437 ah->curchan->center_freq, chan->center_freq);
440 438
441 /* 439 /*
442 * To switch channels clear any pending DMA operations; 440 * To switch channels clear any pending DMA operations;
@@ -444,7 +442,7 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
444 * hardware at the new frequency, and then re-enable 442 * hardware at the new frequency, and then re-enable
445 * the relevant bits of the h/w. 443 * the relevant bits of the h/w.
446 */ 444 */
447 return ath5k_reset(sc, chan, true); 445 return ath5k_reset(ah, chan, true);
448} 446}
449 447
450void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 448void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
@@ -488,10 +486,10 @@ void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
488} 486}
489 487
490void 488void
491ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, 489ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
492 struct ieee80211_vif *vif) 490 struct ieee80211_vif *vif)
493{ 491{
494 struct ath_common *common = ath5k_hw_common(sc->ah); 492 struct ath_common *common = ath5k_hw_common(ah);
495 struct ath5k_vif_iter_data iter_data; 493 struct ath5k_vif_iter_data iter_data;
496 u32 rfilt; 494 u32 rfilt;
497 495
@@ -510,41 +508,41 @@ ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
510 ath5k_vif_iter(&iter_data, vif->addr, vif); 508 ath5k_vif_iter(&iter_data, vif->addr, vif);
511 509
512 /* Get list of all active MAC addresses */ 510 /* Get list of all active MAC addresses */
513 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 511 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
514 &iter_data); 512 &iter_data);
515 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN); 513 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
516 514
517 sc->opmode = iter_data.opmode; 515 ah->opmode = iter_data.opmode;
518 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED) 516 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
519 /* Nothing active, default to station mode */ 517 /* Nothing active, default to station mode */
520 sc->opmode = NL80211_IFTYPE_STATION; 518 ah->opmode = NL80211_IFTYPE_STATION;
521 519
522 ath5k_hw_set_opmode(sc->ah, sc->opmode); 520 ath5k_hw_set_opmode(ah, ah->opmode);
523 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 521 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
524 sc->opmode, ath_opmode_to_string(sc->opmode)); 522 ah->opmode, ath_opmode_to_string(ah->opmode));
525 523
526 if (iter_data.need_set_hw_addr && iter_data.found_active) 524 if (iter_data.need_set_hw_addr && iter_data.found_active)
527 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac); 525 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
528 526
529 if (ath5k_hw_hasbssidmask(sc->ah)) 527 if (ath5k_hw_hasbssidmask(ah))
530 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 528 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
531 529
532 /* Set up RX Filter */ 530 /* Set up RX Filter */
533 if (iter_data.n_stas > 1) { 531 if (iter_data.n_stas > 1) {
534 /* If you have multiple STA interfaces connected to 532 /* If you have multiple STA interfaces connected to
535 * different APs, ARPs are not received (most of the time?) 533 * different APs, ARPs are not received (most of the time?)
536 * Enabling PROMISC appears to fix that probem. 534 * Enabling PROMISC appears to fix that problem.
537 */ 535 */
538 sc->filter_flags |= AR5K_RX_FILTER_PROM; 536 ah->filter_flags |= AR5K_RX_FILTER_PROM;
539 } 537 }
540 538
541 rfilt = sc->filter_flags; 539 rfilt = ah->filter_flags;
542 ath5k_hw_set_rx_filter(sc->ah, rfilt); 540 ath5k_hw_set_rx_filter(ah, rfilt);
543 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 541 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
544} 542}
545 543
546static inline int 544static inline int
547ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 545ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
548{ 546{
549 int rix; 547 int rix;
550 548
@@ -553,7 +551,7 @@ ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
553 "hw_rix out of bounds: %x\n", hw_rix)) 551 "hw_rix out of bounds: %x\n", hw_rix))
554 return 0; 552 return 0;
555 553
556 rix = sc->rate_idx[sc->curchan->band][hw_rix]; 554 rix = ah->rate_idx[ah->curchan->band][hw_rix];
557 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 555 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
558 rix = 0; 556 rix = 0;
559 557
@@ -565,9 +563,9 @@ ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
565\***************/ 563\***************/
566 564
567static 565static
568struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 566struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
569{ 567{
570 struct ath_common *common = ath5k_hw_common(sc->ah); 568 struct ath_common *common = ath5k_hw_common(ah);
571 struct sk_buff *skb; 569 struct sk_buff *skb;
572 570
573 /* 571 /*
@@ -579,17 +577,17 @@ struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
579 GFP_ATOMIC); 577 GFP_ATOMIC);
580 578
581 if (!skb) { 579 if (!skb) {
582 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 580 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
583 common->rx_bufsize); 581 common->rx_bufsize);
584 return NULL; 582 return NULL;
585 } 583 }
586 584
587 *skb_addr = dma_map_single(sc->dev, 585 *skb_addr = dma_map_single(ah->dev,
588 skb->data, common->rx_bufsize, 586 skb->data, common->rx_bufsize,
589 DMA_FROM_DEVICE); 587 DMA_FROM_DEVICE);
590 588
591 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) { 589 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
592 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 590 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
593 dev_kfree_skb(skb); 591 dev_kfree_skb(skb);
594 return NULL; 592 return NULL;
595 } 593 }
@@ -597,15 +595,14 @@ struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
597} 595}
598 596
599static int 597static int
600ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 598ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
601{ 599{
602 struct ath5k_hw *ah = sc->ah;
603 struct sk_buff *skb = bf->skb; 600 struct sk_buff *skb = bf->skb;
604 struct ath5k_desc *ds; 601 struct ath5k_desc *ds;
605 int ret; 602 int ret;
606 603
607 if (!skb) { 604 if (!skb) {
608 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 605 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
609 if (!skb) 606 if (!skb)
610 return -ENOMEM; 607 return -ENOMEM;
611 bf->skb = skb; 608 bf->skb = skb;
@@ -631,13 +628,13 @@ ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
631 ds->ds_data = bf->skbaddr; 628 ds->ds_data = bf->skbaddr;
632 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 629 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
633 if (ret) { 630 if (ret) {
634 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__); 631 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
635 return ret; 632 return ret;
636 } 633 }
637 634
638 if (sc->rxlink != NULL) 635 if (ah->rxlink != NULL)
639 *sc->rxlink = bf->daddr; 636 *ah->rxlink = bf->daddr;
640 sc->rxlink = &ds->ds_link; 637 ah->rxlink = &ds->ds_link;
641 return 0; 638 return 0;
642} 639}
643 640
@@ -665,10 +662,9 @@ static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
665} 662}
666 663
667static int 664static int
668ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 665ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
669 struct ath5k_txq *txq, int padsize) 666 struct ath5k_txq *txq, int padsize)
670{ 667{
671 struct ath5k_hw *ah = sc->ah;
672 struct ath5k_desc *ds = bf->desc; 668 struct ath5k_desc *ds = bf->desc;
673 struct sk_buff *skb = bf->skb; 669 struct sk_buff *skb = bf->skb;
674 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
@@ -684,10 +680,10 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
684 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 680 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
685 681
686 /* XXX endianness */ 682 /* XXX endianness */
687 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 683 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
688 DMA_TO_DEVICE); 684 DMA_TO_DEVICE);
689 685
690 rate = ieee80211_get_tx_rate(sc->hw, info); 686 rate = ieee80211_get_tx_rate(ah->hw, info);
691 if (!rate) { 687 if (!rate) {
692 ret = -EINVAL; 688 ret = -EINVAL;
693 goto err_unmap; 689 goto err_unmap;
@@ -711,20 +707,20 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
711 } 707 }
712 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 708 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
713 flags |= AR5K_TXDESC_RTSENA; 709 flags |= AR5K_TXDESC_RTSENA;
714 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 710 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
715 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 711 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
716 info->control.vif, pktlen, info)); 712 info->control.vif, pktlen, info));
717 } 713 }
718 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 714 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
719 flags |= AR5K_TXDESC_CTSENA; 715 flags |= AR5K_TXDESC_CTSENA;
720 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 716 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
721 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 717 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
722 info->control.vif, pktlen, info)); 718 info->control.vif, pktlen, info));
723 } 719 }
724 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 720 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
725 ieee80211_get_hdrlen_from_skb(skb), padsize, 721 ieee80211_get_hdrlen_from_skb(skb), padsize,
726 get_hw_packet_type(skb), 722 get_hw_packet_type(skb),
727 (sc->power_level * 2), 723 (ah->power_level * 2),
728 hw_rate, 724 hw_rate,
729 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 725 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
730 cts_rate, duration); 726 cts_rate, duration);
@@ -734,7 +730,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
734 memset(mrr_rate, 0, sizeof(mrr_rate)); 730 memset(mrr_rate, 0, sizeof(mrr_rate));
735 memset(mrr_tries, 0, sizeof(mrr_tries)); 731 memset(mrr_tries, 0, sizeof(mrr_tries));
736 for (i = 0; i < 3; i++) { 732 for (i = 0; i < 3; i++) {
737 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 733 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
738 if (!rate) 734 if (!rate)
739 break; 735 break;
740 736
@@ -765,7 +761,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
765 761
766 return 0; 762 return 0;
767err_unmap: 763err_unmap:
768 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 764 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
769 return ret; 765 return ret;
770} 766}
771 767
@@ -774,7 +770,7 @@ err_unmap:
774\*******************/ 770\*******************/
775 771
776static int 772static int
777ath5k_desc_alloc(struct ath5k_softc *sc) 773ath5k_desc_alloc(struct ath5k_hw *ah)
778{ 774{
779 struct ath5k_desc *ds; 775 struct ath5k_desc *ds;
780 struct ath5k_buf *bf; 776 struct ath5k_buf *bf;
@@ -783,69 +779,68 @@ ath5k_desc_alloc(struct ath5k_softc *sc)
783 int ret; 779 int ret;
784 780
785 /* allocate descriptors */ 781 /* allocate descriptors */
786 sc->desc_len = sizeof(struct ath5k_desc) * 782 ah->desc_len = sizeof(struct ath5k_desc) *
787 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 783 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
788 784
789 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len, 785 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
790 &sc->desc_daddr, GFP_KERNEL); 786 &ah->desc_daddr, GFP_KERNEL);
791 if (sc->desc == NULL) { 787 if (ah->desc == NULL) {
792 ATH5K_ERR(sc, "can't allocate descriptors\n"); 788 ATH5K_ERR(ah, "can't allocate descriptors\n");
793 ret = -ENOMEM; 789 ret = -ENOMEM;
794 goto err; 790 goto err;
795 } 791 }
796 ds = sc->desc; 792 ds = ah->desc;
797 da = sc->desc_daddr; 793 da = ah->desc_daddr;
798 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 794 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
799 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 795 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
800 796
801 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 797 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
802 sizeof(struct ath5k_buf), GFP_KERNEL); 798 sizeof(struct ath5k_buf), GFP_KERNEL);
803 if (bf == NULL) { 799 if (bf == NULL) {
804 ATH5K_ERR(sc, "can't allocate bufptr\n"); 800 ATH5K_ERR(ah, "can't allocate bufptr\n");
805 ret = -ENOMEM; 801 ret = -ENOMEM;
806 goto err_free; 802 goto err_free;
807 } 803 }
808 sc->bufptr = bf; 804 ah->bufptr = bf;
809 805
810 INIT_LIST_HEAD(&sc->rxbuf); 806 INIT_LIST_HEAD(&ah->rxbuf);
811 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 807 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
812 bf->desc = ds; 808 bf->desc = ds;
813 bf->daddr = da; 809 bf->daddr = da;
814 list_add_tail(&bf->list, &sc->rxbuf); 810 list_add_tail(&bf->list, &ah->rxbuf);
815 } 811 }
816 812
817 INIT_LIST_HEAD(&sc->txbuf); 813 INIT_LIST_HEAD(&ah->txbuf);
818 sc->txbuf_len = ATH_TXBUF; 814 ah->txbuf_len = ATH_TXBUF;
819 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, 815 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
820 da += sizeof(*ds)) {
821 bf->desc = ds; 816 bf->desc = ds;
822 bf->daddr = da; 817 bf->daddr = da;
823 list_add_tail(&bf->list, &sc->txbuf); 818 list_add_tail(&bf->list, &ah->txbuf);
824 } 819 }
825 820
826 /* beacon buffers */ 821 /* beacon buffers */
827 INIT_LIST_HEAD(&sc->bcbuf); 822 INIT_LIST_HEAD(&ah->bcbuf);
828 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
829 bf->desc = ds; 824 bf->desc = ds;
830 bf->daddr = da; 825 bf->daddr = da;
831 list_add_tail(&bf->list, &sc->bcbuf); 826 list_add_tail(&bf->list, &ah->bcbuf);
832 } 827 }
833 828
834 return 0; 829 return 0;
835err_free: 830err_free:
836 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 831 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
837err: 832err:
838 sc->desc = NULL; 833 ah->desc = NULL;
839 return ret; 834 return ret;
840} 835}
841 836
842void 837void
843ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 838ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
844{ 839{
845 BUG_ON(!bf); 840 BUG_ON(!bf);
846 if (!bf->skb) 841 if (!bf->skb)
847 return; 842 return;
848 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len, 843 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
849 DMA_TO_DEVICE); 844 DMA_TO_DEVICE);
850 dev_kfree_skb_any(bf->skb); 845 dev_kfree_skb_any(bf->skb);
851 bf->skb = NULL; 846 bf->skb = NULL;
@@ -854,15 +849,14 @@ ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
854} 849}
855 850
856void 851void
857ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 852ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
858{ 853{
859 struct ath5k_hw *ah = sc->ah;
860 struct ath_common *common = ath5k_hw_common(ah); 854 struct ath_common *common = ath5k_hw_common(ah);
861 855
862 BUG_ON(!bf); 856 BUG_ON(!bf);
863 if (!bf->skb) 857 if (!bf->skb)
864 return; 858 return;
865 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize, 859 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
866 DMA_FROM_DEVICE); 860 DMA_FROM_DEVICE);
867 dev_kfree_skb_any(bf->skb); 861 dev_kfree_skb_any(bf->skb);
868 bf->skb = NULL; 862 bf->skb = NULL;
@@ -871,24 +865,24 @@ ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
871} 865}
872 866
873static void 867static void
874ath5k_desc_free(struct ath5k_softc *sc) 868ath5k_desc_free(struct ath5k_hw *ah)
875{ 869{
876 struct ath5k_buf *bf; 870 struct ath5k_buf *bf;
877 871
878 list_for_each_entry(bf, &sc->txbuf, list) 872 list_for_each_entry(bf, &ah->txbuf, list)
879 ath5k_txbuf_free_skb(sc, bf); 873 ath5k_txbuf_free_skb(ah, bf);
880 list_for_each_entry(bf, &sc->rxbuf, list) 874 list_for_each_entry(bf, &ah->rxbuf, list)
881 ath5k_rxbuf_free_skb(sc, bf); 875 ath5k_rxbuf_free_skb(ah, bf);
882 list_for_each_entry(bf, &sc->bcbuf, list) 876 list_for_each_entry(bf, &ah->bcbuf, list)
883 ath5k_txbuf_free_skb(sc, bf); 877 ath5k_txbuf_free_skb(ah, bf);
884 878
885 /* Free memory associated with all descriptors */ 879 /* Free memory associated with all descriptors */
886 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 880 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
887 sc->desc = NULL; 881 ah->desc = NULL;
888 sc->desc_daddr = 0; 882 ah->desc_daddr = 0;
889 883
890 kfree(sc->bufptr); 884 kfree(ah->bufptr);
891 sc->bufptr = NULL; 885 ah->bufptr = NULL;
892} 886}
893 887
894 888
@@ -897,10 +891,9 @@ ath5k_desc_free(struct ath5k_softc *sc)
897\**************/ 891\**************/
898 892
899static struct ath5k_txq * 893static struct ath5k_txq *
900ath5k_txq_setup(struct ath5k_softc *sc, 894ath5k_txq_setup(struct ath5k_hw *ah,
901 int qtype, int subtype) 895 int qtype, int subtype)
902{ 896{
903 struct ath5k_hw *ah = sc->ah;
904 struct ath5k_txq *txq; 897 struct ath5k_txq *txq;
905 struct ath5k_txq_info qi = { 898 struct ath5k_txq_info qi = {
906 .tqi_subtype = subtype, 899 .tqi_subtype = subtype,
@@ -934,13 +927,13 @@ ath5k_txq_setup(struct ath5k_softc *sc,
934 */ 927 */
935 return ERR_PTR(qnum); 928 return ERR_PTR(qnum);
936 } 929 }
937 if (qnum >= ARRAY_SIZE(sc->txqs)) { 930 if (qnum >= ARRAY_SIZE(ah->txqs)) {
938 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 931 ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
939 qnum, ARRAY_SIZE(sc->txqs)); 932 qnum, ARRAY_SIZE(ah->txqs));
940 ath5k_hw_release_tx_queue(ah, qnum); 933 ath5k_hw_release_tx_queue(ah, qnum);
941 return ERR_PTR(-EINVAL); 934 return ERR_PTR(-EINVAL);
942 } 935 }
943 txq = &sc->txqs[qnum]; 936 txq = &ah->txqs[qnum];
944 if (!txq->setup) { 937 if (!txq->setup) {
945 txq->qnum = qnum; 938 txq->qnum = qnum;
946 txq->link = NULL; 939 txq->link = NULL;
@@ -952,7 +945,7 @@ ath5k_txq_setup(struct ath5k_softc *sc,
952 txq->txq_poll_mark = false; 945 txq->txq_poll_mark = false;
953 txq->txq_stuck = 0; 946 txq->txq_stuck = 0;
954 } 947 }
955 return &sc->txqs[qnum]; 948 return &ah->txqs[qnum];
956} 949}
957 950
958static int 951static int
@@ -972,18 +965,17 @@ ath5k_beaconq_setup(struct ath5k_hw *ah)
972} 965}
973 966
974static int 967static int
975ath5k_beaconq_config(struct ath5k_softc *sc) 968ath5k_beaconq_config(struct ath5k_hw *ah)
976{ 969{
977 struct ath5k_hw *ah = sc->ah;
978 struct ath5k_txq_info qi; 970 struct ath5k_txq_info qi;
979 int ret; 971 int ret;
980 972
981 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 973 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
982 if (ret) 974 if (ret)
983 goto err; 975 goto err;
984 976
985 if (sc->opmode == NL80211_IFTYPE_AP || 977 if (ah->opmode == NL80211_IFTYPE_AP ||
986 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 978 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
987 /* 979 /*
988 * Always burst out beacon and CAB traffic 980 * Always burst out beacon and CAB traffic
989 * (aifs = cwmin = cwmax = 0) 981 * (aifs = cwmin = cwmax = 0)
@@ -991,7 +983,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
991 qi.tqi_aifs = 0; 983 qi.tqi_aifs = 0;
992 qi.tqi_cw_min = 0; 984 qi.tqi_cw_min = 0;
993 qi.tqi_cw_max = 0; 985 qi.tqi_cw_max = 0;
994 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 986 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
995 /* 987 /*
996 * Adhoc mode; backoff between 0 and (2 * cw_min). 988 * Adhoc mode; backoff between 0 and (2 * cw_min).
997 */ 989 */
@@ -1000,17 +992,17 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
1000 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 992 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
1001 } 993 }
1002 994
1003 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1004 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 996 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1005 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 997 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1006 998
1007 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 999 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
1008 if (ret) { 1000 if (ret) {
1009 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1001 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
1010 "hardware queue!\n", __func__); 1002 "hardware queue!\n", __func__);
1011 goto err; 1003 goto err;
1012 } 1004 }
1013 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */ 1005 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
1014 if (ret) 1006 if (ret)
1015 goto err; 1007 goto err;
1016 1008
@@ -1019,7 +1011,7 @@ ath5k_beaconq_config(struct ath5k_softc *sc)
1019 if (ret) 1011 if (ret)
1020 goto err; 1012 goto err;
1021 1013
1022 qi.tqi_ready_time = (sc->bintval * 80) / 100; 1014 qi.tqi_ready_time = (ah->bintval * 80) / 100;
1023 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1015 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1024 if (ret) 1016 if (ret)
1025 goto err; 1017 goto err;
@@ -1032,7 +1024,7 @@ err:
1032/** 1024/**
1033 * ath5k_drain_tx_buffs - Empty tx buffers 1025 * ath5k_drain_tx_buffs - Empty tx buffers
1034 * 1026 *
1035 * @sc The &struct ath5k_softc 1027 * @ah The &struct ath5k_hw
1036 * 1028 *
1037 * Empty tx buffers from all queues in preparation 1029 * Empty tx buffers from all queues in preparation
1038 * of a reset or during shutdown. 1030 * of a reset or during shutdown.
@@ -1041,26 +1033,26 @@ err:
1041 * we do not need to block ath5k_tx_tasklet 1033 * we do not need to block ath5k_tx_tasklet
1042 */ 1034 */
1043static void 1035static void
1044ath5k_drain_tx_buffs(struct ath5k_softc *sc) 1036ath5k_drain_tx_buffs(struct ath5k_hw *ah)
1045{ 1037{
1046 struct ath5k_txq *txq; 1038 struct ath5k_txq *txq;
1047 struct ath5k_buf *bf, *bf0; 1039 struct ath5k_buf *bf, *bf0;
1048 int i; 1040 int i;
1049 1041
1050 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 1042 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1051 if (sc->txqs[i].setup) { 1043 if (ah->txqs[i].setup) {
1052 txq = &sc->txqs[i]; 1044 txq = &ah->txqs[i];
1053 spin_lock_bh(&txq->lock); 1045 spin_lock_bh(&txq->lock);
1054 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1046 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1055 ath5k_debug_printtxbuf(sc, bf); 1047 ath5k_debug_printtxbuf(ah, bf);
1056 1048
1057 ath5k_txbuf_free_skb(sc, bf); 1049 ath5k_txbuf_free_skb(ah, bf);
1058 1050
1059 spin_lock_bh(&sc->txbuflock); 1051 spin_lock_bh(&ah->txbuflock);
1060 list_move_tail(&bf->list, &sc->txbuf); 1052 list_move_tail(&bf->list, &ah->txbuf);
1061 sc->txbuf_len++; 1053 ah->txbuf_len++;
1062 txq->txq_len--; 1054 txq->txq_len--;
1063 spin_unlock_bh(&sc->txbuflock); 1055 spin_unlock_bh(&ah->txbuflock);
1064 } 1056 }
1065 txq->link = NULL; 1057 txq->link = NULL;
1066 txq->txq_poll_mark = false; 1058 txq->txq_poll_mark = false;
@@ -1070,14 +1062,14 @@ ath5k_drain_tx_buffs(struct ath5k_softc *sc)
1070} 1062}
1071 1063
1072static void 1064static void
1073ath5k_txq_release(struct ath5k_softc *sc) 1065ath5k_txq_release(struct ath5k_hw *ah)
1074{ 1066{
1075 struct ath5k_txq *txq = sc->txqs; 1067 struct ath5k_txq *txq = ah->txqs;
1076 unsigned int i; 1068 unsigned int i;
1077 1069
1078 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1070 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
1079 if (txq->setup) { 1071 if (txq->setup) {
1080 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1072 ath5k_hw_release_tx_queue(ah, txq->qnum);
1081 txq->setup = false; 1073 txq->setup = false;
1082 } 1074 }
1083} 1075}
@@ -1091,33 +1083,32 @@ ath5k_txq_release(struct ath5k_softc *sc)
1091 * Enable the receive h/w following a reset. 1083 * Enable the receive h/w following a reset.
1092 */ 1084 */
1093static int 1085static int
1094ath5k_rx_start(struct ath5k_softc *sc) 1086ath5k_rx_start(struct ath5k_hw *ah)
1095{ 1087{
1096 struct ath5k_hw *ah = sc->ah;
1097 struct ath_common *common = ath5k_hw_common(ah); 1088 struct ath_common *common = ath5k_hw_common(ah);
1098 struct ath5k_buf *bf; 1089 struct ath5k_buf *bf;
1099 int ret; 1090 int ret;
1100 1091
1101 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1092 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
1102 1093
1103 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1094 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1104 common->cachelsz, common->rx_bufsize); 1095 common->cachelsz, common->rx_bufsize);
1105 1096
1106 spin_lock_bh(&sc->rxbuflock); 1097 spin_lock_bh(&ah->rxbuflock);
1107 sc->rxlink = NULL; 1098 ah->rxlink = NULL;
1108 list_for_each_entry(bf, &sc->rxbuf, list) { 1099 list_for_each_entry(bf, &ah->rxbuf, list) {
1109 ret = ath5k_rxbuf_setup(sc, bf); 1100 ret = ath5k_rxbuf_setup(ah, bf);
1110 if (ret != 0) { 1101 if (ret != 0) {
1111 spin_unlock_bh(&sc->rxbuflock); 1102 spin_unlock_bh(&ah->rxbuflock);
1112 goto err; 1103 goto err;
1113 } 1104 }
1114 } 1105 }
1115 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1106 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1116 ath5k_hw_set_rxdp(ah, bf->daddr); 1107 ath5k_hw_set_rxdp(ah, bf->daddr);
1117 spin_unlock_bh(&sc->rxbuflock); 1108 spin_unlock_bh(&ah->rxbuflock);
1118 1109
1119 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1110 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1120 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */ 1111 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
1121 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1112 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1122 1113
1123 return 0; 1114 return 0;
@@ -1133,21 +1124,19 @@ err:
1133 * does. 1124 * does.
1134 */ 1125 */
1135static void 1126static void
1136ath5k_rx_stop(struct ath5k_softc *sc) 1127ath5k_rx_stop(struct ath5k_hw *ah)
1137{ 1128{
1138 struct ath5k_hw *ah = sc->ah;
1139 1129
1140 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1130 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1141 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1131 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1142 1132
1143 ath5k_debug_printrxbuffs(sc, ah); 1133 ath5k_debug_printrxbuffs(ah);
1144} 1134}
1145 1135
1146static unsigned int 1136static unsigned int
1147ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb, 1137ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
1148 struct ath5k_rx_status *rs) 1138 struct ath5k_rx_status *rs)
1149{ 1139{
1150 struct ath5k_hw *ah = sc->ah;
1151 struct ath_common *common = ath5k_hw_common(ah); 1140 struct ath_common *common = ath5k_hw_common(ah);
1152 struct ieee80211_hdr *hdr = (void *)skb->data; 1141 struct ieee80211_hdr *hdr = (void *)skb->data;
1153 unsigned int keyix, hlen; 1142 unsigned int keyix, hlen;
@@ -1174,10 +1163,10 @@ ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1174 1163
1175 1164
1176static void 1165static void
1177ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1166ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
1178 struct ieee80211_rx_status *rxs) 1167 struct ieee80211_rx_status *rxs)
1179{ 1168{
1180 struct ath_common *common = ath5k_hw_common(sc->ah); 1169 struct ath_common *common = ath5k_hw_common(ah);
1181 u64 tsf, bc_tstamp; 1170 u64 tsf, bc_tstamp;
1182 u32 hw_tu; 1171 u32 hw_tu;
1183 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1172 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
@@ -1190,11 +1179,11 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1190 * have updated the local TSF. We have to work around various 1179 * have updated the local TSF. We have to work around various
1191 * hardware bugs, though... 1180 * hardware bugs, though...
1192 */ 1181 */
1193 tsf = ath5k_hw_get_tsf64(sc->ah); 1182 tsf = ath5k_hw_get_tsf64(ah);
1194 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1183 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1195 hw_tu = TSF_TO_TU(tsf); 1184 hw_tu = TSF_TO_TU(tsf);
1196 1185
1197 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1186 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1198 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1187 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1199 (unsigned long long)bc_tstamp, 1188 (unsigned long long)bc_tstamp,
1200 (unsigned long long)rxs->mactime, 1189 (unsigned long long)rxs->mactime,
@@ -1213,7 +1202,7 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1213 * received, not like mac80211 which defines it at the start. 1202 * received, not like mac80211 which defines it at the start.
1214 */ 1203 */
1215 if (bc_tstamp > rxs->mactime) { 1204 if (bc_tstamp > rxs->mactime) {
1216 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1205 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1217 "fixing mactime from %llx to %llx\n", 1206 "fixing mactime from %llx to %llx\n",
1218 (unsigned long long)rxs->mactime, 1207 (unsigned long long)rxs->mactime,
1219 (unsigned long long)tsf); 1208 (unsigned long long)tsf);
@@ -1226,25 +1215,24 @@ ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1226 * beacons. This also takes care of synchronizing beacon sending 1215 * beacons. This also takes care of synchronizing beacon sending
1227 * times with other stations. 1216 * times with other stations.
1228 */ 1217 */
1229 if (hw_tu >= sc->nexttbtt) 1218 if (hw_tu >= ah->nexttbtt)
1230 ath5k_beacon_update_timers(sc, bc_tstamp); 1219 ath5k_beacon_update_timers(ah, bc_tstamp);
1231 1220
1232 /* Check if the beacon timers are still correct, because a TSF 1221 /* Check if the beacon timers are still correct, because a TSF
1233 * update might have created a window between them - for a 1222 * update might have created a window between them - for a
1234 * longer description see the comment of this function: */ 1223 * longer description see the comment of this function: */
1235 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) { 1224 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1236 ath5k_beacon_update_timers(sc, bc_tstamp); 1225 ath5k_beacon_update_timers(ah, bc_tstamp);
1237 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1226 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
1238 "fixed beacon timers after beacon receive\n"); 1227 "fixed beacon timers after beacon receive\n");
1239 } 1228 }
1240 } 1229 }
1241} 1230}
1242 1231
1243static void 1232static void
1244ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi) 1233ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
1245{ 1234{
1246 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1235 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1247 struct ath5k_hw *ah = sc->ah;
1248 struct ath_common *common = ath5k_hw_common(ah); 1236 struct ath_common *common = ath5k_hw_common(ah);
1249 1237
1250 /* only beacons from our BSSID */ 1238 /* only beacons from our BSSID */
@@ -1263,16 +1251,15 @@ ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1263 */ 1251 */
1264static int ath5k_common_padpos(struct sk_buff *skb) 1252static int ath5k_common_padpos(struct sk_buff *skb)
1265{ 1253{
1266 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 1254 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1267 __le16 frame_control = hdr->frame_control; 1255 __le16 frame_control = hdr->frame_control;
1268 int padpos = 24; 1256 int padpos = 24;
1269 1257
1270 if (ieee80211_has_a4(frame_control)) { 1258 if (ieee80211_has_a4(frame_control))
1271 padpos += ETH_ALEN; 1259 padpos += ETH_ALEN;
1272 } 1260
1273 if (ieee80211_is_data_qos(frame_control)) { 1261 if (ieee80211_is_data_qos(frame_control))
1274 padpos += IEEE80211_QOS_CTL_LEN; 1262 padpos += IEEE80211_QOS_CTL_LEN;
1275 }
1276 1263
1277 return padpos; 1264 return padpos;
1278} 1265}
@@ -1286,13 +1273,13 @@ static int ath5k_add_padding(struct sk_buff *skb)
1286 int padpos = ath5k_common_padpos(skb); 1273 int padpos = ath5k_common_padpos(skb);
1287 int padsize = padpos & 3; 1274 int padsize = padpos & 3;
1288 1275
1289 if (padsize && skb->len>padpos) { 1276 if (padsize && skb->len > padpos) {
1290 1277
1291 if (skb_headroom(skb) < padsize) 1278 if (skb_headroom(skb) < padsize)
1292 return -1; 1279 return -1;
1293 1280
1294 skb_push(skb, padsize); 1281 skb_push(skb, padsize);
1295 memmove(skb->data, skb->data+padsize, padpos); 1282 memmove(skb->data, skb->data + padsize, padpos);
1296 return padsize; 1283 return padsize;
1297 } 1284 }
1298 1285
@@ -1317,7 +1304,7 @@ static int ath5k_remove_padding(struct sk_buff *skb)
1317 int padpos = ath5k_common_padpos(skb); 1304 int padpos = ath5k_common_padpos(skb);
1318 int padsize = padpos & 3; 1305 int padsize = padpos & 3;
1319 1306
1320 if (padsize && skb->len>=padpos+padsize) { 1307 if (padsize && skb->len >= padpos + padsize) {
1321 memmove(skb->data + padsize, skb->data, padpos); 1308 memmove(skb->data + padsize, skb->data, padpos);
1322 skb_pull(skb, padsize); 1309 skb_pull(skb, padsize);
1323 return padsize; 1310 return padsize;
@@ -1327,7 +1314,7 @@ static int ath5k_remove_padding(struct sk_buff *skb)
1327} 1314}
1328 1315
1329static void 1316static void
1330ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb, 1317ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
1331 struct ath5k_rx_status *rs) 1318 struct ath5k_rx_status *rs)
1332{ 1319{
1333 struct ieee80211_rx_status *rxs; 1320 struct ieee80211_rx_status *rxs;
@@ -1353,44 +1340,44 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1353 * timestamp (beginning of phy frame, data frame, end of rx?). 1340 * timestamp (beginning of phy frame, data frame, end of rx?).
1354 * The only thing we know is that it is hardware specific... 1341 * The only thing we know is that it is hardware specific...
1355 * On AR5213 it seems the rx timestamp is at the end of the 1342 * On AR5213 it seems the rx timestamp is at the end of the
1356 * frame, but i'm not sure. 1343 * frame, but I'm not sure.
1357 * 1344 *
1358 * NOTE: mac80211 defines mactime at the beginning of the first 1345 * NOTE: mac80211 defines mactime at the beginning of the first
1359 * data symbol. Since we don't have any time references it's 1346 * data symbol. Since we don't have any time references it's
1360 * impossible to comply to that. This affects IBSS merge only 1347 * impossible to comply to that. This affects IBSS merge only
1361 * right now, so it's not too bad... 1348 * right now, so it's not too bad...
1362 */ 1349 */
1363 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp); 1350 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
1364 rxs->flag |= RX_FLAG_MACTIME_MPDU; 1351 rxs->flag |= RX_FLAG_MACTIME_MPDU;
1365 1352
1366 rxs->freq = sc->curchan->center_freq; 1353 rxs->freq = ah->curchan->center_freq;
1367 rxs->band = sc->curchan->band; 1354 rxs->band = ah->curchan->band;
1368 1355
1369 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi; 1356 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
1370 1357
1371 rxs->antenna = rs->rs_antenna; 1358 rxs->antenna = rs->rs_antenna;
1372 1359
1373 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1360 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1374 sc->stats.antenna_rx[rs->rs_antenna]++; 1361 ah->stats.antenna_rx[rs->rs_antenna]++;
1375 else 1362 else
1376 sc->stats.antenna_rx[0]++; /* invalid */ 1363 ah->stats.antenna_rx[0]++; /* invalid */
1377 1364
1378 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate); 1365 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1379 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs); 1366 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
1380 1367
1381 if (rxs->rate_idx >= 0 && rs->rs_rate == 1368 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1382 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1369 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
1383 rxs->flag |= RX_FLAG_SHORTPRE; 1370 rxs->flag |= RX_FLAG_SHORTPRE;
1384 1371
1385 trace_ath5k_rx(sc, skb); 1372 trace_ath5k_rx(ah, skb);
1386 1373
1387 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi); 1374 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
1388 1375
1389 /* check beacons in IBSS mode */ 1376 /* check beacons in IBSS mode */
1390 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1377 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1391 ath5k_check_ibss_tsf(sc, skb, rxs); 1378 ath5k_check_ibss_tsf(ah, skb, rxs);
1392 1379
1393 ieee80211_rx(sc->hw, skb); 1380 ieee80211_rx(ah->hw, skb);
1394} 1381}
1395 1382
1396/** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1383/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
@@ -1399,20 +1386,20 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1399 * statistics. Return true if we want this frame, false if not. 1386 * statistics. Return true if we want this frame, false if not.
1400 */ 1387 */
1401static bool 1388static bool
1402ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs) 1389ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
1403{ 1390{
1404 sc->stats.rx_all_count++; 1391 ah->stats.rx_all_count++;
1405 sc->stats.rx_bytes_count += rs->rs_datalen; 1392 ah->stats.rx_bytes_count += rs->rs_datalen;
1406 1393
1407 if (unlikely(rs->rs_status)) { 1394 if (unlikely(rs->rs_status)) {
1408 if (rs->rs_status & AR5K_RXERR_CRC) 1395 if (rs->rs_status & AR5K_RXERR_CRC)
1409 sc->stats.rxerr_crc++; 1396 ah->stats.rxerr_crc++;
1410 if (rs->rs_status & AR5K_RXERR_FIFO) 1397 if (rs->rs_status & AR5K_RXERR_FIFO)
1411 sc->stats.rxerr_fifo++; 1398 ah->stats.rxerr_fifo++;
1412 if (rs->rs_status & AR5K_RXERR_PHY) { 1399 if (rs->rs_status & AR5K_RXERR_PHY) {
1413 sc->stats.rxerr_phy++; 1400 ah->stats.rxerr_phy++;
1414 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1401 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1415 sc->stats.rxerr_phy_code[rs->rs_phyerr]++; 1402 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
1416 return false; 1403 return false;
1417 } 1404 }
1418 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1405 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
@@ -1426,13 +1413,13 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1426 * 1413 *
1427 * XXX do key cache faulting 1414 * XXX do key cache faulting
1428 */ 1415 */
1429 sc->stats.rxerr_decrypt++; 1416 ah->stats.rxerr_decrypt++;
1430 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1417 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1431 !(rs->rs_status & AR5K_RXERR_CRC)) 1418 !(rs->rs_status & AR5K_RXERR_CRC))
1432 return true; 1419 return true;
1433 } 1420 }
1434 if (rs->rs_status & AR5K_RXERR_MIC) { 1421 if (rs->rs_status & AR5K_RXERR_MIC) {
1435 sc->stats.rxerr_mic++; 1422 ah->stats.rxerr_mic++;
1436 return true; 1423 return true;
1437 } 1424 }
1438 1425
@@ -1442,25 +1429,26 @@ ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
1442 } 1429 }
1443 1430
1444 if (unlikely(rs->rs_more)) { 1431 if (unlikely(rs->rs_more)) {
1445 sc->stats.rxerr_jumbo++; 1432 ah->stats.rxerr_jumbo++;
1446 return false; 1433 return false;
1447 } 1434 }
1448 return true; 1435 return true;
1449} 1436}
1450 1437
1451static void 1438static void
1452ath5k_set_current_imask(struct ath5k_softc *sc) 1439ath5k_set_current_imask(struct ath5k_hw *ah)
1453{ 1440{
1454 enum ath5k_int imask = sc->imask; 1441 enum ath5k_int imask;
1455 unsigned long flags; 1442 unsigned long flags;
1456 1443
1457 spin_lock_irqsave(&sc->irqlock, flags); 1444 spin_lock_irqsave(&ah->irqlock, flags);
1458 if (sc->rx_pending) 1445 imask = ah->imask;
1446 if (ah->rx_pending)
1459 imask &= ~AR5K_INT_RX_ALL; 1447 imask &= ~AR5K_INT_RX_ALL;
1460 if (sc->tx_pending) 1448 if (ah->tx_pending)
1461 imask &= ~AR5K_INT_TX_ALL; 1449 imask &= ~AR5K_INT_TX_ALL;
1462 ath5k_hw_set_imr(sc->ah, imask); 1450 ath5k_hw_set_imr(ah, imask);
1463 spin_unlock_irqrestore(&sc->irqlock, flags); 1451 spin_unlock_irqrestore(&ah->irqlock, flags);
1464} 1452}
1465 1453
1466static void 1454static void
@@ -1469,39 +1457,38 @@ ath5k_tasklet_rx(unsigned long data)
1469 struct ath5k_rx_status rs = {}; 1457 struct ath5k_rx_status rs = {};
1470 struct sk_buff *skb, *next_skb; 1458 struct sk_buff *skb, *next_skb;
1471 dma_addr_t next_skb_addr; 1459 dma_addr_t next_skb_addr;
1472 struct ath5k_softc *sc = (void *)data; 1460 struct ath5k_hw *ah = (void *)data;
1473 struct ath5k_hw *ah = sc->ah;
1474 struct ath_common *common = ath5k_hw_common(ah); 1461 struct ath_common *common = ath5k_hw_common(ah);
1475 struct ath5k_buf *bf; 1462 struct ath5k_buf *bf;
1476 struct ath5k_desc *ds; 1463 struct ath5k_desc *ds;
1477 int ret; 1464 int ret;
1478 1465
1479 spin_lock(&sc->rxbuflock); 1466 spin_lock(&ah->rxbuflock);
1480 if (list_empty(&sc->rxbuf)) { 1467 if (list_empty(&ah->rxbuf)) {
1481 ATH5K_WARN(sc, "empty rx buf pool\n"); 1468 ATH5K_WARN(ah, "empty rx buf pool\n");
1482 goto unlock; 1469 goto unlock;
1483 } 1470 }
1484 do { 1471 do {
1485 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1472 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
1486 BUG_ON(bf->skb == NULL); 1473 BUG_ON(bf->skb == NULL);
1487 skb = bf->skb; 1474 skb = bf->skb;
1488 ds = bf->desc; 1475 ds = bf->desc;
1489 1476
1490 /* bail if HW is still using self-linked descriptor */ 1477 /* bail if HW is still using self-linked descriptor */
1491 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1478 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
1492 break; 1479 break;
1493 1480
1494 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1481 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
1495 if (unlikely(ret == -EINPROGRESS)) 1482 if (unlikely(ret == -EINPROGRESS))
1496 break; 1483 break;
1497 else if (unlikely(ret)) { 1484 else if (unlikely(ret)) {
1498 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1485 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1499 sc->stats.rxerr_proc++; 1486 ah->stats.rxerr_proc++;
1500 break; 1487 break;
1501 } 1488 }
1502 1489
1503 if (ath5k_receive_frame_ok(sc, &rs)) { 1490 if (ath5k_receive_frame_ok(ah, &rs)) {
1504 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1491 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
1505 1492
1506 /* 1493 /*
1507 * If we can't replace bf->skb with a new skb under 1494 * If we can't replace bf->skb with a new skb under
@@ -1510,24 +1497,24 @@ ath5k_tasklet_rx(unsigned long data)
1510 if (!next_skb) 1497 if (!next_skb)
1511 goto next; 1498 goto next;
1512 1499
1513 dma_unmap_single(sc->dev, bf->skbaddr, 1500 dma_unmap_single(ah->dev, bf->skbaddr,
1514 common->rx_bufsize, 1501 common->rx_bufsize,
1515 DMA_FROM_DEVICE); 1502 DMA_FROM_DEVICE);
1516 1503
1517 skb_put(skb, rs.rs_datalen); 1504 skb_put(skb, rs.rs_datalen);
1518 1505
1519 ath5k_receive_frame(sc, skb, &rs); 1506 ath5k_receive_frame(ah, skb, &rs);
1520 1507
1521 bf->skb = next_skb; 1508 bf->skb = next_skb;
1522 bf->skbaddr = next_skb_addr; 1509 bf->skbaddr = next_skb_addr;
1523 } 1510 }
1524next: 1511next:
1525 list_move_tail(&bf->list, &sc->rxbuf); 1512 list_move_tail(&bf->list, &ah->rxbuf);
1526 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1513 } while (ath5k_rxbuf_setup(ah, bf) == 0);
1527unlock: 1514unlock:
1528 spin_unlock(&sc->rxbuflock); 1515 spin_unlock(&ah->rxbuflock);
1529 sc->rx_pending = false; 1516 ah->rx_pending = false;
1530 ath5k_set_current_imask(sc); 1517 ath5k_set_current_imask(ah);
1531} 1518}
1532 1519
1533 1520
@@ -1539,12 +1526,12 @@ void
1539ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1526ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1540 struct ath5k_txq *txq) 1527 struct ath5k_txq *txq)
1541{ 1528{
1542 struct ath5k_softc *sc = hw->priv; 1529 struct ath5k_hw *ah = hw->priv;
1543 struct ath5k_buf *bf; 1530 struct ath5k_buf *bf;
1544 unsigned long flags; 1531 unsigned long flags;
1545 int padsize; 1532 int padsize;
1546 1533
1547 trace_ath5k_tx(sc, skb, txq); 1534 trace_ath5k_tx(ah, skb, txq);
1548 1535
1549 /* 1536 /*
1550 * The hardware expects the header padded to 4 byte boundaries. 1537 * The hardware expects the header padded to 4 byte boundaries.
@@ -1552,36 +1539,37 @@ ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1552 */ 1539 */
1553 padsize = ath5k_add_padding(skb); 1540 padsize = ath5k_add_padding(skb);
1554 if (padsize < 0) { 1541 if (padsize < 0) {
1555 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough" 1542 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
1556 " headroom to pad"); 1543 " headroom to pad");
1557 goto drop_packet; 1544 goto drop_packet;
1558 } 1545 }
1559 1546
1560 if (txq->txq_len >= txq->txq_max) 1547 if (txq->txq_len >= txq->txq_max &&
1548 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
1561 ieee80211_stop_queue(hw, txq->qnum); 1549 ieee80211_stop_queue(hw, txq->qnum);
1562 1550
1563 spin_lock_irqsave(&sc->txbuflock, flags); 1551 spin_lock_irqsave(&ah->txbuflock, flags);
1564 if (list_empty(&sc->txbuf)) { 1552 if (list_empty(&ah->txbuf)) {
1565 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 1553 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1566 spin_unlock_irqrestore(&sc->txbuflock, flags); 1554 spin_unlock_irqrestore(&ah->txbuflock, flags);
1567 ieee80211_stop_queues(hw); 1555 ieee80211_stop_queues(hw);
1568 goto drop_packet; 1556 goto drop_packet;
1569 } 1557 }
1570 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 1558 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
1571 list_del(&bf->list); 1559 list_del(&bf->list);
1572 sc->txbuf_len--; 1560 ah->txbuf_len--;
1573 if (list_empty(&sc->txbuf)) 1561 if (list_empty(&ah->txbuf))
1574 ieee80211_stop_queues(hw); 1562 ieee80211_stop_queues(hw);
1575 spin_unlock_irqrestore(&sc->txbuflock, flags); 1563 spin_unlock_irqrestore(&ah->txbuflock, flags);
1576 1564
1577 bf->skb = skb; 1565 bf->skb = skb;
1578 1566
1579 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) { 1567 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
1580 bf->skb = NULL; 1568 bf->skb = NULL;
1581 spin_lock_irqsave(&sc->txbuflock, flags); 1569 spin_lock_irqsave(&ah->txbuflock, flags);
1582 list_add_tail(&bf->list, &sc->txbuf); 1570 list_add_tail(&bf->list, &ah->txbuf);
1583 sc->txbuf_len++; 1571 ah->txbuf_len++;
1584 spin_unlock_irqrestore(&sc->txbuflock, flags); 1572 spin_unlock_irqrestore(&ah->txbuflock, flags);
1585 goto drop_packet; 1573 goto drop_packet;
1586 } 1574 }
1587 return; 1575 return;
@@ -1591,15 +1579,15 @@ drop_packet:
1591} 1579}
1592 1580
1593static void 1581static void
1594ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb, 1582ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
1595 struct ath5k_txq *txq, struct ath5k_tx_status *ts) 1583 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1596{ 1584{
1597 struct ieee80211_tx_info *info; 1585 struct ieee80211_tx_info *info;
1598 u8 tries[3]; 1586 u8 tries[3];
1599 int i; 1587 int i;
1600 1588
1601 sc->stats.tx_all_count++; 1589 ah->stats.tx_all_count++;
1602 sc->stats.tx_bytes_count += skb->len; 1590 ah->stats.tx_bytes_count += skb->len;
1603 info = IEEE80211_SKB_CB(skb); 1591 info = IEEE80211_SKB_CB(skb);
1604 1592
1605 tries[0] = info->status.rates[0].count; 1593 tries[0] = info->status.rates[0].count;
@@ -1619,15 +1607,15 @@ ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1619 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1607 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1620 1608
1621 if (unlikely(ts->ts_status)) { 1609 if (unlikely(ts->ts_status)) {
1622 sc->stats.ack_fail++; 1610 ah->stats.ack_fail++;
1623 if (ts->ts_status & AR5K_TXERR_FILT) { 1611 if (ts->ts_status & AR5K_TXERR_FILT) {
1624 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1612 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1625 sc->stats.txerr_filt++; 1613 ah->stats.txerr_filt++;
1626 } 1614 }
1627 if (ts->ts_status & AR5K_TXERR_XRETRY) 1615 if (ts->ts_status & AR5K_TXERR_XRETRY)
1628 sc->stats.txerr_retry++; 1616 ah->stats.txerr_retry++;
1629 if (ts->ts_status & AR5K_TXERR_FIFO) 1617 if (ts->ts_status & AR5K_TXERR_FIFO)
1630 sc->stats.txerr_fifo++; 1618 ah->stats.txerr_fifo++;
1631 } else { 1619 } else {
1632 info->flags |= IEEE80211_TX_STAT_ACK; 1620 info->flags |= IEEE80211_TX_STAT_ACK;
1633 info->status.ack_signal = ts->ts_rssi; 1621 info->status.ack_signal = ts->ts_rssi;
@@ -1643,16 +1631,16 @@ ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1643 ath5k_remove_padding(skb); 1631 ath5k_remove_padding(skb);
1644 1632
1645 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1633 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1646 sc->stats.antenna_tx[ts->ts_antenna]++; 1634 ah->stats.antenna_tx[ts->ts_antenna]++;
1647 else 1635 else
1648 sc->stats.antenna_tx[0]++; /* invalid */ 1636 ah->stats.antenna_tx[0]++; /* invalid */
1649 1637
1650 trace_ath5k_tx_complete(sc, skb, txq, ts); 1638 trace_ath5k_tx_complete(ah, skb, txq, ts);
1651 ieee80211_tx_status(sc->hw, skb); 1639 ieee80211_tx_status(ah->hw, skb);
1652} 1640}
1653 1641
1654static void 1642static void
1655ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1643ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
1656{ 1644{
1657 struct ath5k_tx_status ts = {}; 1645 struct ath5k_tx_status ts = {};
1658 struct ath5k_buf *bf, *bf0; 1646 struct ath5k_buf *bf, *bf0;
@@ -1669,11 +1657,11 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1669 if (bf->skb != NULL) { 1657 if (bf->skb != NULL) {
1670 ds = bf->desc; 1658 ds = bf->desc;
1671 1659
1672 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1660 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
1673 if (unlikely(ret == -EINPROGRESS)) 1661 if (unlikely(ret == -EINPROGRESS))
1674 break; 1662 break;
1675 else if (unlikely(ret)) { 1663 else if (unlikely(ret)) {
1676 ATH5K_ERR(sc, 1664 ATH5K_ERR(ah,
1677 "error %d while processing " 1665 "error %d while processing "
1678 "queue %u\n", ret, txq->qnum); 1666 "queue %u\n", ret, txq->qnum);
1679 break; 1667 break;
@@ -1682,9 +1670,9 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1682 skb = bf->skb; 1670 skb = bf->skb;
1683 bf->skb = NULL; 1671 bf->skb = NULL;
1684 1672
1685 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, 1673 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
1686 DMA_TO_DEVICE); 1674 DMA_TO_DEVICE);
1687 ath5k_tx_frame_completed(sc, skb, txq, &ts); 1675 ath5k_tx_frame_completed(ah, skb, txq, &ts);
1688 } 1676 }
1689 1677
1690 /* 1678 /*
@@ -1693,31 +1681,31 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1693 * host memory and moved on. 1681 * host memory and moved on.
1694 * Always keep the last descriptor to avoid HW races... 1682 * Always keep the last descriptor to avoid HW races...
1695 */ 1683 */
1696 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) { 1684 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1697 spin_lock(&sc->txbuflock); 1685 spin_lock(&ah->txbuflock);
1698 list_move_tail(&bf->list, &sc->txbuf); 1686 list_move_tail(&bf->list, &ah->txbuf);
1699 sc->txbuf_len++; 1687 ah->txbuf_len++;
1700 txq->txq_len--; 1688 txq->txq_len--;
1701 spin_unlock(&sc->txbuflock); 1689 spin_unlock(&ah->txbuflock);
1702 } 1690 }
1703 } 1691 }
1704 spin_unlock(&txq->lock); 1692 spin_unlock(&txq->lock);
1705 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
1706 ieee80211_wake_queue(sc->hw, txq->qnum); 1694 ieee80211_wake_queue(ah->hw, txq->qnum);
1707} 1695}
1708 1696
1709static void 1697static void
1710ath5k_tasklet_tx(unsigned long data) 1698ath5k_tasklet_tx(unsigned long data)
1711{ 1699{
1712 int i; 1700 int i;
1713 struct ath5k_softc *sc = (void *)data; 1701 struct ath5k_hw *ah = (void *)data;
1714 1702
1715 for (i=0; i < AR5K_NUM_TX_QUEUES; i++) 1703 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
1716 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 1704 if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
1717 ath5k_tx_processq(sc, &sc->txqs[i]); 1705 ath5k_tx_processq(ah, &ah->txqs[i]);
1718 1706
1719 sc->tx_pending = false; 1707 ah->tx_pending = false;
1720 ath5k_set_current_imask(sc); 1708 ath5k_set_current_imask(ah);
1721} 1709}
1722 1710
1723 1711
@@ -1729,25 +1717,24 @@ ath5k_tasklet_tx(unsigned long data)
1729 * Setup the beacon frame for transmit. 1717 * Setup the beacon frame for transmit.
1730 */ 1718 */
1731static int 1719static int
1732ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1720ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
1733{ 1721{
1734 struct sk_buff *skb = bf->skb; 1722 struct sk_buff *skb = bf->skb;
1735 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1736 struct ath5k_hw *ah = sc->ah;
1737 struct ath5k_desc *ds; 1724 struct ath5k_desc *ds;
1738 int ret = 0; 1725 int ret = 0;
1739 u8 antenna; 1726 u8 antenna;
1740 u32 flags; 1727 u32 flags;
1741 const int padsize = 0; 1728 const int padsize = 0;
1742 1729
1743 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 1730 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
1744 DMA_TO_DEVICE); 1731 DMA_TO_DEVICE);
1745 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1732 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1746 "skbaddr %llx\n", skb, skb->data, skb->len, 1733 "skbaddr %llx\n", skb, skb->data, skb->len,
1747 (unsigned long long)bf->skbaddr); 1734 (unsigned long long)bf->skbaddr);
1748 1735
1749 if (dma_mapping_error(sc->dev, bf->skbaddr)) { 1736 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1750 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 1737 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
1751 return -EIO; 1738 return -EIO;
1752 } 1739 }
1753 1740
@@ -1755,7 +1742,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1755 antenna = ah->ah_tx_ant; 1742 antenna = ah->ah_tx_ant;
1756 1743
1757 flags = AR5K_TXDESC_NOACK; 1744 flags = AR5K_TXDESC_NOACK;
1758 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1745 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1759 ds->ds_link = bf->daddr; /* self-linked */ 1746 ds->ds_link = bf->daddr; /* self-linked */
1760 flags |= AR5K_TXDESC_VEOL; 1747 flags |= AR5K_TXDESC_VEOL;
1761 } else 1748 } else
@@ -1767,7 +1754,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1767 * 4 beacons to make sure everybody hears our AP. 1754 * 4 beacons to make sure everybody hears our AP.
1768 * When a client tries to associate, hw will keep 1755 * When a client tries to associate, hw will keep
1769 * track of the tx antenna to be used for this client 1756 * track of the tx antenna to be used for this client
1770 * automaticaly, based on ACKed packets. 1757 * automatically, based on ACKed packets.
1771 * 1758 *
1772 * Note: AP still listens and transmits RTS on the 1759 * Note: AP still listens and transmits RTS on the
1773 * default antenna which is supposed to be an omni. 1760 * default antenna which is supposed to be an omni.
@@ -1780,7 +1767,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1780 * on all of them. 1767 * on all of them.
1781 */ 1768 */
1782 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1769 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1783 antenna = sc->bsent & 4 ? 2 : 1; 1770 antenna = ah->bsent & 4 ? 2 : 1;
1784 1771
1785 1772
1786 /* FIXME: If we are in g mode and rate is a CCK rate 1773 /* FIXME: If we are in g mode and rate is a CCK rate
@@ -1789,8 +1776,8 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1789 ds->ds_data = bf->skbaddr; 1776 ds->ds_data = bf->skbaddr;
1790 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1777 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1791 ieee80211_get_hdrlen_from_skb(skb), padsize, 1778 ieee80211_get_hdrlen_from_skb(skb), padsize,
1792 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 1779 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
1793 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 1780 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
1794 1, AR5K_TXKEYIX_INVALID, 1781 1, AR5K_TXKEYIX_INVALID,
1795 antenna, flags, 0, 0); 1782 antenna, flags, 0, 0);
1796 if (ret) 1783 if (ret)
@@ -1798,7 +1785,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1798 1785
1799 return 0; 1786 return 0;
1800err_unmap: 1787err_unmap:
1801 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1788 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
1802 return ret; 1789 return ret;
1803} 1790}
1804 1791
@@ -1813,7 +1800,7 @@ int
1813ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1800ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1814{ 1801{
1815 int ret; 1802 int ret;
1816 struct ath5k_softc *sc = hw->priv; 1803 struct ath5k_hw *ah = hw->priv;
1817 struct ath5k_vif *avf = (void *)vif->drv_priv; 1804 struct ath5k_vif *avf = (void *)vif->drv_priv;
1818 struct sk_buff *skb; 1805 struct sk_buff *skb;
1819 1806
@@ -1829,9 +1816,9 @@ ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1829 goto out; 1816 goto out;
1830 } 1817 }
1831 1818
1832 ath5k_txbuf_free_skb(sc, avf->bbuf); 1819 ath5k_txbuf_free_skb(ah, avf->bbuf);
1833 avf->bbuf->skb = skb; 1820 avf->bbuf->skb = skb;
1834 ret = ath5k_beacon_setup(sc, avf->bbuf); 1821 ret = ath5k_beacon_setup(ah, avf->bbuf);
1835 if (ret) 1822 if (ret)
1836 avf->bbuf->skb = NULL; 1823 avf->bbuf->skb = NULL;
1837out: 1824out:
@@ -1847,15 +1834,14 @@ out:
1847 * or user context from ath5k_beacon_config. 1834 * or user context from ath5k_beacon_config.
1848 */ 1835 */
1849static void 1836static void
1850ath5k_beacon_send(struct ath5k_softc *sc) 1837ath5k_beacon_send(struct ath5k_hw *ah)
1851{ 1838{
1852 struct ath5k_hw *ah = sc->ah;
1853 struct ieee80211_vif *vif; 1839 struct ieee80211_vif *vif;
1854 struct ath5k_vif *avf; 1840 struct ath5k_vif *avf;
1855 struct ath5k_buf *bf; 1841 struct ath5k_buf *bf;
1856 struct sk_buff *skb; 1842 struct sk_buff *skb;
1857 1843
1858 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1844 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1859 1845
1860 /* 1846 /*
1861 * Check if the previous beacon has gone out. If 1847 * Check if the previous beacon has gone out. If
@@ -1864,47 +1850,47 @@ ath5k_beacon_send(struct ath5k_softc *sc)
1864 * indicate a problem and should not occur. If we 1850 * indicate a problem and should not occur. If we
1865 * miss too many consecutive beacons reset the device. 1851 * miss too many consecutive beacons reset the device.
1866 */ 1852 */
1867 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 1853 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1868 sc->bmisscount++; 1854 ah->bmisscount++;
1869 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1855 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1870 "missed %u consecutive beacons\n", sc->bmisscount); 1856 "missed %u consecutive beacons\n", ah->bmisscount);
1871 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 1857 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1872 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1858 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1873 "stuck beacon time (%u missed)\n", 1859 "stuck beacon time (%u missed)\n",
1874 sc->bmisscount); 1860 ah->bmisscount);
1875 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 1861 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1876 "stuck beacon, resetting\n"); 1862 "stuck beacon, resetting\n");
1877 ieee80211_queue_work(sc->hw, &sc->reset_work); 1863 ieee80211_queue_work(ah->hw, &ah->reset_work);
1878 } 1864 }
1879 return; 1865 return;
1880 } 1866 }
1881 if (unlikely(sc->bmisscount != 0)) { 1867 if (unlikely(ah->bmisscount != 0)) {
1882 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1868 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1883 "resume beacon xmit after %u misses\n", 1869 "resume beacon xmit after %u misses\n",
1884 sc->bmisscount); 1870 ah->bmisscount);
1885 sc->bmisscount = 0; 1871 ah->bmisscount = 0;
1886 } 1872 }
1887 1873
1888 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) || 1874 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
1889 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1875 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1890 u64 tsf = ath5k_hw_get_tsf64(ah); 1876 u64 tsf = ath5k_hw_get_tsf64(ah);
1891 u32 tsftu = TSF_TO_TU(tsf); 1877 u32 tsftu = TSF_TO_TU(tsf);
1892 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; 1878 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1893 vif = sc->bslot[(slot + 1) % ATH_BCBUF]; 1879 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1894 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1880 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1895 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1881 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1896 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif); 1882 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
1897 } else /* only one interface */ 1883 } else /* only one interface */
1898 vif = sc->bslot[0]; 1884 vif = ah->bslot[0];
1899 1885
1900 if (!vif) 1886 if (!vif)
1901 return; 1887 return;
1902 1888
1903 avf = (void *)vif->drv_priv; 1889 avf = (void *)vif->drv_priv;
1904 bf = avf->bbuf; 1890 bf = avf->bbuf;
1905 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 1891 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1906 sc->opmode == NL80211_IFTYPE_MONITOR)) { 1892 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1907 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 1893 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1908 return; 1894 return;
1909 } 1895 }
1910 1896
@@ -1913,36 +1899,40 @@ ath5k_beacon_send(struct ath5k_softc *sc)
1913 * This should never fail since we check above that no frames 1899 * This should never fail since we check above that no frames
1914 * are still pending on the queue. 1900 * are still pending on the queue.
1915 */ 1901 */
1916 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) { 1902 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1917 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 1903 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
1918 /* NB: hw still stops DMA, so proceed */ 1904 /* NB: hw still stops DMA, so proceed */
1919 } 1905 }
1920 1906
1921 /* refresh the beacon for AP or MESH mode */ 1907 /* refresh the beacon for AP or MESH mode */
1922 if (sc->opmode == NL80211_IFTYPE_AP || 1908 if (ah->opmode == NL80211_IFTYPE_AP ||
1923 sc->opmode == NL80211_IFTYPE_MESH_POINT) 1909 ah->opmode == NL80211_IFTYPE_MESH_POINT)
1924 ath5k_beacon_update(sc->hw, vif); 1910 ath5k_beacon_update(ah->hw, vif);
1925 1911
1926 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]); 1912 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
1927 1913
1928 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 1914 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1929 ath5k_hw_start_tx_dma(ah, sc->bhalq); 1915 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1930 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1916 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1931 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 1917 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
1932 1918
1933 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1919 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1934 while (skb) { 1920 while (skb) {
1935 ath5k_tx_queue(sc->hw, skb, sc->cabq); 1921 ath5k_tx_queue(ah->hw, skb, ah->cabq);
1936 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1922
1923 if (ah->cabq->txq_len >= ah->cabq->txq_max)
1924 break;
1925
1926 skb = ieee80211_get_buffered_bc(ah->hw, vif);
1937 } 1927 }
1938 1928
1939 sc->bsent++; 1929 ah->bsent++;
1940} 1930}
1941 1931
1942/** 1932/**
1943 * ath5k_beacon_update_timers - update beacon timers 1933 * ath5k_beacon_update_timers - update beacon timers
1944 * 1934 *
1945 * @sc: struct ath5k_softc pointer we are operating on 1935 * @ah: struct ath5k_hw pointer we are operating on
1946 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 1936 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1947 * beacon timer update based on the current HW TSF. 1937 * beacon timer update based on the current HW TSF.
1948 * 1938 *
@@ -1956,17 +1946,16 @@ ath5k_beacon_send(struct ath5k_softc *sc)
1956 * function to have it all together in one place. 1946 * function to have it all together in one place.
1957 */ 1947 */
1958void 1948void
1959ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 1949ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
1960{ 1950{
1961 struct ath5k_hw *ah = sc->ah;
1962 u32 nexttbtt, intval, hw_tu, bc_tu; 1951 u32 nexttbtt, intval, hw_tu, bc_tu;
1963 u64 hw_tsf; 1952 u64 hw_tsf;
1964 1953
1965 intval = sc->bintval & AR5K_BEACON_PERIOD; 1954 intval = ah->bintval & AR5K_BEACON_PERIOD;
1966 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { 1955 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
1967 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 1956 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1968 if (intval < 15) 1957 if (intval < 15)
1969 ATH5K_WARN(sc, "intval %u is too low, min 15\n", 1958 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
1970 intval); 1959 intval);
1971 } 1960 }
1972 if (WARN_ON(!intval)) 1961 if (WARN_ON(!intval))
@@ -1979,7 +1968,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
1979 hw_tsf = ath5k_hw_get_tsf64(ah); 1968 hw_tsf = ath5k_hw_get_tsf64(ah);
1980 hw_tu = TSF_TO_TU(hw_tsf); 1969 hw_tu = TSF_TO_TU(hw_tsf);
1981 1970
1982#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3 1971#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
1983 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 1972 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1984 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 1973 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1985 * configuration we need to make sure it is bigger than that. */ 1974 * configuration we need to make sure it is bigger than that. */
@@ -2005,7 +1994,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2005 * automatically update the TSF and then we need to reconfigure 1994 * automatically update the TSF and then we need to reconfigure
2006 * the timers. 1995 * the timers.
2007 */ 1996 */
2008 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1997 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2009 "need to wait for HW TSF sync\n"); 1998 "need to wait for HW TSF sync\n");
2010 return; 1999 return;
2011 } else { 2000 } else {
@@ -2020,7 +2009,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2020 } 2009 }
2021#undef FUDGE 2010#undef FUDGE
2022 2011
2023 sc->nexttbtt = nexttbtt; 2012 ah->nexttbtt = nexttbtt;
2024 2013
2025 intval |= AR5K_BEACON_ENA; 2014 intval |= AR5K_BEACON_ENA;
2026 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2015 ath5k_hw_init_beacon(ah, nexttbtt, intval);
@@ -2030,20 +2019,20 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2030 * of this function 2019 * of this function
2031 */ 2020 */
2032 if (bc_tsf == -1) 2021 if (bc_tsf == -1)
2033 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2022 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2034 "reconfigured timers based on HW TSF\n"); 2023 "reconfigured timers based on HW TSF\n");
2035 else if (bc_tsf == 0) 2024 else if (bc_tsf == 0)
2036 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2025 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2037 "reset HW TSF and timers\n"); 2026 "reset HW TSF and timers\n");
2038 else 2027 else
2039 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2028 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2040 "updated timers based on beacon TSF\n"); 2029 "updated timers based on beacon TSF\n");
2041 2030
2042 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2031 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
2043 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2032 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2044 (unsigned long long) bc_tsf, 2033 (unsigned long long) bc_tsf,
2045 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2034 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2046 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2047 intval & AR5K_BEACON_PERIOD, 2036 intval & AR5K_BEACON_PERIOD,
2048 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2037 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2049 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2038 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
@@ -2052,22 +2041,21 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2052/** 2041/**
2053 * ath5k_beacon_config - Configure the beacon queues and interrupts 2042 * ath5k_beacon_config - Configure the beacon queues and interrupts
2054 * 2043 *
2055 * @sc: struct ath5k_softc pointer we are operating on 2044 * @ah: struct ath5k_hw pointer we are operating on
2056 * 2045 *
2057 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2046 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2058 * interrupts to detect TSF updates only. 2047 * interrupts to detect TSF updates only.
2059 */ 2048 */
2060void 2049void
2061ath5k_beacon_config(struct ath5k_softc *sc) 2050ath5k_beacon_config(struct ath5k_hw *ah)
2062{ 2051{
2063 struct ath5k_hw *ah = sc->ah;
2064 unsigned long flags; 2052 unsigned long flags;
2065 2053
2066 spin_lock_irqsave(&sc->block, flags); 2054 spin_lock_irqsave(&ah->block, flags);
2067 sc->bmisscount = 0; 2055 ah->bmisscount = 0;
2068 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2056 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2069 2057
2070 if (sc->enable_beacon) { 2058 if (ah->enable_beacon) {
2071 /* 2059 /*
2072 * In IBSS mode we use a self-linked tx descriptor and let the 2060 * In IBSS mode we use a self-linked tx descriptor and let the
2073 * hardware send the beacons automatically. We have to load it 2061 * hardware send the beacons automatically. We have to load it
@@ -2075,50 +2063,50 @@ ath5k_beacon_config(struct ath5k_softc *sc)
2075 * We use the SWBA interrupt only to keep track of the beacon 2063 * We use the SWBA interrupt only to keep track of the beacon
2076 * timers in order to detect automatic TSF updates. 2064 * timers in order to detect automatic TSF updates.
2077 */ 2065 */
2078 ath5k_beaconq_config(sc); 2066 ath5k_beaconq_config(ah);
2079 2067
2080 sc->imask |= AR5K_INT_SWBA; 2068 ah->imask |= AR5K_INT_SWBA;
2081 2069
2082 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2070 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2083 if (ath5k_hw_hasveol(ah)) 2071 if (ath5k_hw_hasveol(ah))
2084 ath5k_beacon_send(sc); 2072 ath5k_beacon_send(ah);
2085 } else 2073 } else
2086 ath5k_beacon_update_timers(sc, -1); 2074 ath5k_beacon_update_timers(ah, -1);
2087 } else { 2075 } else {
2088 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq); 2076 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
2089 } 2077 }
2090 2078
2091 ath5k_hw_set_imr(ah, sc->imask); 2079 ath5k_hw_set_imr(ah, ah->imask);
2092 mmiowb(); 2080 mmiowb();
2093 spin_unlock_irqrestore(&sc->block, flags); 2081 spin_unlock_irqrestore(&ah->block, flags);
2094} 2082}
2095 2083
2096static void ath5k_tasklet_beacon(unsigned long data) 2084static void ath5k_tasklet_beacon(unsigned long data)
2097{ 2085{
2098 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2086 struct ath5k_hw *ah = (struct ath5k_hw *) data;
2099 2087
2100 /* 2088 /*
2101 * Software beacon alert--time to send a beacon. 2089 * Software beacon alert--time to send a beacon.
2102 * 2090 *
2103 * In IBSS mode we use this interrupt just to 2091 * In IBSS mode we use this interrupt just to
2104 * keep track of the next TBTT (target beacon 2092 * keep track of the next TBTT (target beacon
2105 * transmission time) in order to detect wether 2093 * transmission time) in order to detect whether
2106 * automatic TSF updates happened. 2094 * automatic TSF updates happened.
2107 */ 2095 */
2108 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2096 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
2109 /* XXX: only if VEOL suppported */ 2097 /* XXX: only if VEOL supported */
2110 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2098 u64 tsf = ath5k_hw_get_tsf64(ah);
2111 sc->nexttbtt += sc->bintval; 2099 ah->nexttbtt += ah->bintval;
2112 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2100 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
2113 "SWBA nexttbtt: %x hw_tu: %x " 2101 "SWBA nexttbtt: %x hw_tu: %x "
2114 "TSF: %llx\n", 2102 "TSF: %llx\n",
2115 sc->nexttbtt, 2103 ah->nexttbtt,
2116 TSF_TO_TU(tsf), 2104 TSF_TO_TU(tsf),
2117 (unsigned long long) tsf); 2105 (unsigned long long) tsf);
2118 } else { 2106 } else {
2119 spin_lock(&sc->block); 2107 spin_lock(&ah->block);
2120 ath5k_beacon_send(sc); 2108 ath5k_beacon_send(ah);
2121 spin_unlock(&sc->block); 2109 spin_unlock(&ah->block);
2122 } 2110 }
2123} 2111}
2124 2112
@@ -2135,12 +2123,12 @@ ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2135 /* run ANI only when full calibration is not active */ 2123 /* run ANI only when full calibration is not active */
2136 ah->ah_cal_next_ani = jiffies + 2124 ah->ah_cal_next_ani = jiffies +
2137 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2125 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2138 tasklet_schedule(&ah->ah_sc->ani_tasklet); 2126 tasklet_schedule(&ah->ani_tasklet);
2139 2127
2140 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2128 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2141 ah->ah_cal_next_full = jiffies + 2129 ah->ah_cal_next_full = jiffies +
2142 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2130 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2143 tasklet_schedule(&ah->ah_sc->calib); 2131 tasklet_schedule(&ah->calib);
2144 } 2132 }
2145 /* we could use SWI to generate enough interrupts to meet our 2133 /* we could use SWI to generate enough interrupts to meet our
2146 * calibration interval requirements, if necessary: 2134 * calibration interval requirements, if necessary:
@@ -2148,44 +2136,43 @@ ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2148} 2136}
2149 2137
2150static void 2138static void
2151ath5k_schedule_rx(struct ath5k_softc *sc) 2139ath5k_schedule_rx(struct ath5k_hw *ah)
2152{ 2140{
2153 sc->rx_pending = true; 2141 ah->rx_pending = true;
2154 tasklet_schedule(&sc->rxtq); 2142 tasklet_schedule(&ah->rxtq);
2155} 2143}
2156 2144
2157static void 2145static void
2158ath5k_schedule_tx(struct ath5k_softc *sc) 2146ath5k_schedule_tx(struct ath5k_hw *ah)
2159{ 2147{
2160 sc->tx_pending = true; 2148 ah->tx_pending = true;
2161 tasklet_schedule(&sc->txtq); 2149 tasklet_schedule(&ah->txtq);
2162} 2150}
2163 2151
2164irqreturn_t 2152static irqreturn_t
2165ath5k_intr(int irq, void *dev_id) 2153ath5k_intr(int irq, void *dev_id)
2166{ 2154{
2167 struct ath5k_softc *sc = dev_id; 2155 struct ath5k_hw *ah = dev_id;
2168 struct ath5k_hw *ah = sc->ah;
2169 enum ath5k_int status; 2156 enum ath5k_int status;
2170 unsigned int counter = 1000; 2157 unsigned int counter = 1000;
2171 2158
2172 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2159 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
2173 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2160 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2174 !ath5k_hw_is_intr_pending(ah)))) 2161 !ath5k_hw_is_intr_pending(ah))))
2175 return IRQ_NONE; 2162 return IRQ_NONE;
2176 2163
2177 do { 2164 do {
2178 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2165 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2179 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2166 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2180 status, sc->imask); 2167 status, ah->imask);
2181 if (unlikely(status & AR5K_INT_FATAL)) { 2168 if (unlikely(status & AR5K_INT_FATAL)) {
2182 /* 2169 /*
2183 * Fatal errors are unrecoverable. 2170 * Fatal errors are unrecoverable.
2184 * Typically these are caused by DMA errors. 2171 * Typically these are caused by DMA errors.
2185 */ 2172 */
2186 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2173 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2187 "fatal int, resetting\n"); 2174 "fatal int, resetting\n");
2188 ieee80211_queue_work(sc->hw, &sc->reset_work); 2175 ieee80211_queue_work(ah->hw, &ah->reset_work);
2189 } else if (unlikely(status & AR5K_INT_RXORN)) { 2176 } else if (unlikely(status & AR5K_INT_RXORN)) {
2190 /* 2177 /*
2191 * Receive buffers are full. Either the bus is busy or 2178 * Receive buffers are full. Either the bus is busy or
@@ -2196,45 +2183,44 @@ ath5k_intr(int irq, void *dev_id)
2196 * We don't know exactly which versions need a reset - 2183 * We don't know exactly which versions need a reset -
2197 * this guess is copied from the HAL. 2184 * this guess is copied from the HAL.
2198 */ 2185 */
2199 sc->stats.rxorn_intr++; 2186 ah->stats.rxorn_intr++;
2200 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2187 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2201 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2188 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2202 "rx overrun, resetting\n"); 2189 "rx overrun, resetting\n");
2203 ieee80211_queue_work(sc->hw, &sc->reset_work); 2190 ieee80211_queue_work(ah->hw, &ah->reset_work);
2204 } 2191 } else
2205 else 2192 ath5k_schedule_rx(ah);
2206 ath5k_schedule_rx(sc);
2207 } else { 2193 } else {
2208 if (status & AR5K_INT_SWBA) { 2194 if (status & AR5K_INT_SWBA)
2209 tasklet_hi_schedule(&sc->beacontq); 2195 tasklet_hi_schedule(&ah->beacontq);
2210 } 2196
2211 if (status & AR5K_INT_RXEOL) { 2197 if (status & AR5K_INT_RXEOL) {
2212 /* 2198 /*
2213 * NB: the hardware should re-read the link when 2199 * NB: the hardware should re-read the link when
2214 * RXE bit is written, but it doesn't work at 2200 * RXE bit is written, but it doesn't work at
2215 * least on older hardware revs. 2201 * least on older hardware revs.
2216 */ 2202 */
2217 sc->stats.rxeol_intr++; 2203 ah->stats.rxeol_intr++;
2218 } 2204 }
2219 if (status & AR5K_INT_TXURN) { 2205 if (status & AR5K_INT_TXURN) {
2220 /* bump tx trigger level */ 2206 /* bump tx trigger level */
2221 ath5k_hw_update_tx_triglevel(ah, true); 2207 ath5k_hw_update_tx_triglevel(ah, true);
2222 } 2208 }
2223 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2209 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2224 ath5k_schedule_rx(sc); 2210 ath5k_schedule_rx(ah);
2225 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2211 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2226 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2212 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2227 ath5k_schedule_tx(sc); 2213 ath5k_schedule_tx(ah);
2228 if (status & AR5K_INT_BMISS) { 2214 if (status & AR5K_INT_BMISS) {
2229 /* TODO */ 2215 /* TODO */
2230 } 2216 }
2231 if (status & AR5K_INT_MIB) { 2217 if (status & AR5K_INT_MIB) {
2232 sc->stats.mib_intr++; 2218 ah->stats.mib_intr++;
2233 ath5k_hw_update_mib_counters(ah); 2219 ath5k_hw_update_mib_counters(ah);
2234 ath5k_ani_mib_intr(ah); 2220 ath5k_ani_mib_intr(ah);
2235 } 2221 }
2236 if (status & AR5K_INT_GPIO) 2222 if (status & AR5K_INT_GPIO)
2237 tasklet_schedule(&sc->rf_kill.toggleq); 2223 tasklet_schedule(&ah->rf_kill.toggleq);
2238 2224
2239 } 2225 }
2240 2226
@@ -2243,11 +2229,11 @@ ath5k_intr(int irq, void *dev_id)
2243 2229
2244 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2230 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2245 2231
2246 if (sc->rx_pending || sc->tx_pending) 2232 if (ah->rx_pending || ah->tx_pending)
2247 ath5k_set_current_imask(sc); 2233 ath5k_set_current_imask(ah);
2248 2234
2249 if (unlikely(!counter)) 2235 if (unlikely(!counter))
2250 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2236 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
2251 2237
2252 ath5k_intr_calibration_poll(ah); 2238 ath5k_intr_calibration_poll(ah);
2253 2239
@@ -2261,28 +2247,27 @@ ath5k_intr(int irq, void *dev_id)
2261static void 2247static void
2262ath5k_tasklet_calibrate(unsigned long data) 2248ath5k_tasklet_calibrate(unsigned long data)
2263{ 2249{
2264 struct ath5k_softc *sc = (void *)data; 2250 struct ath5k_hw *ah = (void *)data;
2265 struct ath5k_hw *ah = sc->ah;
2266 2251
2267 /* Only full calibration for now */ 2252 /* Only full calibration for now */
2268 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2253 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2269 2254
2270 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2255 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2271 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2256 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2272 sc->curchan->hw_value); 2257 ah->curchan->hw_value);
2273 2258
2274 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2259 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2275 /* 2260 /*
2276 * Rfgain is out of bounds, reset the chip 2261 * Rfgain is out of bounds, reset the chip
2277 * to load new gain values. 2262 * to load new gain values.
2278 */ 2263 */
2279 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2264 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2280 ieee80211_queue_work(sc->hw, &sc->reset_work); 2265 ieee80211_queue_work(ah->hw, &ah->reset_work);
2281 } 2266 }
2282 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2267 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2283 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2268 ATH5K_ERR(ah, "calibration of channel %u failed\n",
2284 ieee80211_frequency_to_channel( 2269 ieee80211_frequency_to_channel(
2285 sc->curchan->center_freq)); 2270 ah->curchan->center_freq));
2286 2271
2287 /* Noise floor calibration interrupts rx/tx path while I/Q calibration 2272 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2288 * doesn't. 2273 * doesn't.
@@ -2301,8 +2286,7 @@ ath5k_tasklet_calibrate(unsigned long data)
2301static void 2286static void
2302ath5k_tasklet_ani(unsigned long data) 2287ath5k_tasklet_ani(unsigned long data)
2303{ 2288{
2304 struct ath5k_softc *sc = (void *)data; 2289 struct ath5k_hw *ah = (void *)data;
2305 struct ath5k_hw *ah = sc->ah;
2306 2290
2307 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2291 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2308 ath5k_ani_calibration(ah); 2292 ath5k_ani_calibration(ah);
@@ -2313,21 +2297,21 @@ ath5k_tasklet_ani(unsigned long data)
2313static void 2297static void
2314ath5k_tx_complete_poll_work(struct work_struct *work) 2298ath5k_tx_complete_poll_work(struct work_struct *work)
2315{ 2299{
2316 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2300 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2317 tx_complete_work.work); 2301 tx_complete_work.work);
2318 struct ath5k_txq *txq; 2302 struct ath5k_txq *txq;
2319 int i; 2303 int i;
2320 bool needreset = false; 2304 bool needreset = false;
2321 2305
2322 mutex_lock(&sc->lock); 2306 mutex_lock(&ah->lock);
2323 2307
2324 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 2308 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2325 if (sc->txqs[i].setup) { 2309 if (ah->txqs[i].setup) {
2326 txq = &sc->txqs[i]; 2310 txq = &ah->txqs[i];
2327 spin_lock_bh(&txq->lock); 2311 spin_lock_bh(&txq->lock);
2328 if (txq->txq_len > 1) { 2312 if (txq->txq_len > 1) {
2329 if (txq->txq_poll_mark) { 2313 if (txq->txq_poll_mark) {
2330 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, 2314 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
2331 "TX queue stuck %d\n", 2315 "TX queue stuck %d\n",
2332 txq->qnum); 2316 txq->qnum);
2333 needreset = true; 2317 needreset = true;
@@ -2343,14 +2327,14 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
2343 } 2327 }
2344 2328
2345 if (needreset) { 2329 if (needreset) {
2346 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2330 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2347 "TX queues stuck, resetting\n"); 2331 "TX queues stuck, resetting\n");
2348 ath5k_reset(sc, NULL, true); 2332 ath5k_reset(ah, NULL, true);
2349 } 2333 }
2350 2334
2351 mutex_unlock(&sc->lock); 2335 mutex_unlock(&ah->lock);
2352 2336
2353 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2337 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2354 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2338 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2355} 2339}
2356 2340
@@ -2359,16 +2343,16 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
2359* Initialization routines * 2343* Initialization routines *
2360\*************************/ 2344\*************************/
2361 2345
2362int 2346int __devinit
2363ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops) 2347ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
2364{ 2348{
2365 struct ieee80211_hw *hw = sc->hw; 2349 struct ieee80211_hw *hw = ah->hw;
2366 struct ath_common *common; 2350 struct ath_common *common;
2367 int ret; 2351 int ret;
2368 int csz; 2352 int csz;
2369 2353
2370 /* Initialize driver private data */ 2354 /* Initialize driver private data */
2371 SET_IEEE80211_DEV(hw, sc->dev); 2355 SET_IEEE80211_DEV(hw, ah->dev);
2372 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2356 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
2373 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2357 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2374 IEEE80211_HW_SIGNAL_DBM | 2358 IEEE80211_HW_SIGNAL_DBM |
@@ -2391,39 +2375,30 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2391 * Mark the device as detached to avoid processing 2375 * Mark the device as detached to avoid processing
2392 * interrupts until setup is complete. 2376 * interrupts until setup is complete.
2393 */ 2377 */
2394 __set_bit(ATH_STAT_INVALID, sc->status); 2378 __set_bit(ATH_STAT_INVALID, ah->status);
2395 2379
2396 sc->opmode = NL80211_IFTYPE_STATION; 2380 ah->opmode = NL80211_IFTYPE_STATION;
2397 sc->bintval = 1000; 2381 ah->bintval = 1000;
2398 mutex_init(&sc->lock); 2382 mutex_init(&ah->lock);
2399 spin_lock_init(&sc->rxbuflock); 2383 spin_lock_init(&ah->rxbuflock);
2400 spin_lock_init(&sc->txbuflock); 2384 spin_lock_init(&ah->txbuflock);
2401 spin_lock_init(&sc->block); 2385 spin_lock_init(&ah->block);
2402 spin_lock_init(&sc->irqlock); 2386 spin_lock_init(&ah->irqlock);
2403 2387
2404 /* Setup interrupt handler */ 2388 /* Setup interrupt handler */
2405 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 2389 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
2406 if (ret) { 2390 if (ret) {
2407 ATH5K_ERR(sc, "request_irq failed\n"); 2391 ATH5K_ERR(ah, "request_irq failed\n");
2408 goto err; 2392 goto err;
2409 } 2393 }
2410 2394
2411 /* If we passed the test, malloc an ath5k_hw struct */ 2395 common = ath5k_hw_common(ah);
2412 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2413 if (!sc->ah) {
2414 ret = -ENOMEM;
2415 ATH5K_ERR(sc, "out of memory\n");
2416 goto err_irq;
2417 }
2418
2419 sc->ah->ah_sc = sc;
2420 sc->ah->ah_iobase = sc->iobase;
2421 common = ath5k_hw_common(sc->ah);
2422 common->ops = &ath5k_common_ops; 2396 common->ops = &ath5k_common_ops;
2423 common->bus_ops = bus_ops; 2397 common->bus_ops = bus_ops;
2424 common->ah = sc->ah; 2398 common->ah = ah;
2425 common->hw = hw; 2399 common->hw = hw;
2426 common->priv = sc; 2400 common->priv = ah;
2401 common->clockrate = 40;
2427 2402
2428 /* 2403 /*
2429 * Cache line size is used to size and align various 2404 * Cache line size is used to size and align various
@@ -2435,12 +2410,12 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2435 spin_lock_init(&common->cc_lock); 2410 spin_lock_init(&common->cc_lock);
2436 2411
2437 /* Initialize device */ 2412 /* Initialize device */
2438 ret = ath5k_hw_init(sc); 2413 ret = ath5k_hw_init(ah);
2439 if (ret) 2414 if (ret)
2440 goto err_free_ah; 2415 goto err_irq;
2441 2416
2442 /* set up multi-rate retry capabilities */ 2417 /* set up multi-rate retry capabilities */
2443 if (sc->ah->ah_version == AR5K_AR5212) { 2418 if (ah->ah_version == AR5K_AR5212) {
2444 hw->max_rates = 4; 2419 hw->max_rates = 4;
2445 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2420 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2446 AR5K_INIT_RETRY_LONG); 2421 AR5K_INIT_RETRY_LONG);
@@ -2453,77 +2428,74 @@ ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2453 if (ret) 2428 if (ret)
2454 goto err_ah; 2429 goto err_ah;
2455 2430
2456 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2431 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2457 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 2432 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2458 sc->ah->ah_mac_srev, 2433 ah->ah_mac_srev,
2459 sc->ah->ah_phy_revision); 2434 ah->ah_phy_revision);
2460 2435
2461 if (!sc->ah->ah_single_chip) { 2436 if (!ah->ah_single_chip) {
2462 /* Single chip radio (!RF5111) */ 2437 /* Single chip radio (!RF5111) */
2463 if (sc->ah->ah_radio_5ghz_revision && 2438 if (ah->ah_radio_5ghz_revision &&
2464 !sc->ah->ah_radio_2ghz_revision) { 2439 !ah->ah_radio_2ghz_revision) {
2465 /* No 5GHz support -> report 2GHz radio */ 2440 /* No 5GHz support -> report 2GHz radio */
2466 if (!test_bit(AR5K_MODE_11A, 2441 if (!test_bit(AR5K_MODE_11A,
2467 sc->ah->ah_capabilities.cap_mode)) { 2442 ah->ah_capabilities.cap_mode)) {
2468 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2443 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2469 ath5k_chip_name(AR5K_VERSION_RAD, 2444 ath5k_chip_name(AR5K_VERSION_RAD,
2470 sc->ah->ah_radio_5ghz_revision), 2445 ah->ah_radio_5ghz_revision),
2471 sc->ah->ah_radio_5ghz_revision); 2446 ah->ah_radio_5ghz_revision);
2472 /* No 2GHz support (5110 and some 2447 /* No 2GHz support (5110 and some
2473 * 5Ghz only cards) -> report 5Ghz radio */ 2448 * 5GHz only cards) -> report 5GHz radio */
2474 } else if (!test_bit(AR5K_MODE_11B, 2449 } else if (!test_bit(AR5K_MODE_11B,
2475 sc->ah->ah_capabilities.cap_mode)) { 2450 ah->ah_capabilities.cap_mode)) {
2476 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2451 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2477 ath5k_chip_name(AR5K_VERSION_RAD, 2452 ath5k_chip_name(AR5K_VERSION_RAD,
2478 sc->ah->ah_radio_5ghz_revision), 2453 ah->ah_radio_5ghz_revision),
2479 sc->ah->ah_radio_5ghz_revision); 2454 ah->ah_radio_5ghz_revision);
2480 /* Multiband radio */ 2455 /* Multiband radio */
2481 } else { 2456 } else {
2482 ATH5K_INFO(sc, "RF%s multiband radio found" 2457 ATH5K_INFO(ah, "RF%s multiband radio found"
2483 " (0x%x)\n", 2458 " (0x%x)\n",
2484 ath5k_chip_name(AR5K_VERSION_RAD, 2459 ath5k_chip_name(AR5K_VERSION_RAD,
2485 sc->ah->ah_radio_5ghz_revision), 2460 ah->ah_radio_5ghz_revision),
2486 sc->ah->ah_radio_5ghz_revision); 2461 ah->ah_radio_5ghz_revision);
2487 } 2462 }
2488 } 2463 }
2489 /* Multi chip radio (RF5111 - RF2111) -> 2464 /* Multi chip radio (RF5111 - RF2111) ->
2490 * report both 2GHz/5GHz radios */ 2465 * report both 2GHz/5GHz radios */
2491 else if (sc->ah->ah_radio_5ghz_revision && 2466 else if (ah->ah_radio_5ghz_revision &&
2492 sc->ah->ah_radio_2ghz_revision){ 2467 ah->ah_radio_2ghz_revision) {
2493 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2468 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
2494 ath5k_chip_name(AR5K_VERSION_RAD, 2469 ath5k_chip_name(AR5K_VERSION_RAD,
2495 sc->ah->ah_radio_5ghz_revision), 2470 ah->ah_radio_5ghz_revision),
2496 sc->ah->ah_radio_5ghz_revision); 2471 ah->ah_radio_5ghz_revision);
2497 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2472 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
2498 ath5k_chip_name(AR5K_VERSION_RAD, 2473 ath5k_chip_name(AR5K_VERSION_RAD,
2499 sc->ah->ah_radio_2ghz_revision), 2474 ah->ah_radio_2ghz_revision),
2500 sc->ah->ah_radio_2ghz_revision); 2475 ah->ah_radio_2ghz_revision);
2501 } 2476 }
2502 } 2477 }
2503 2478
2504 ath5k_debug_init_device(sc); 2479 ath5k_debug_init_device(ah);
2505 2480
2506 /* ready to process interrupts */ 2481 /* ready to process interrupts */
2507 __clear_bit(ATH_STAT_INVALID, sc->status); 2482 __clear_bit(ATH_STAT_INVALID, ah->status);
2508 2483
2509 return 0; 2484 return 0;
2510err_ah: 2485err_ah:
2511 ath5k_hw_deinit(sc->ah); 2486 ath5k_hw_deinit(ah);
2512err_free_ah:
2513 kfree(sc->ah);
2514err_irq: 2487err_irq:
2515 free_irq(sc->irq, sc); 2488 free_irq(ah->irq, ah);
2516err: 2489err:
2517 return ret; 2490 return ret;
2518} 2491}
2519 2492
2520static int 2493static int
2521ath5k_stop_locked(struct ath5k_softc *sc) 2494ath5k_stop_locked(struct ath5k_hw *ah)
2522{ 2495{
2523 struct ath5k_hw *ah = sc->ah;
2524 2496
2525 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2497 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2526 test_bit(ATH_STAT_INVALID, sc->status)); 2498 test_bit(ATH_STAT_INVALID, ah->status));
2527 2499
2528 /* 2500 /*
2529 * Shutdown the hardware and driver: 2501 * Shutdown the hardware and driver:
@@ -2540,37 +2512,36 @@ ath5k_stop_locked(struct ath5k_softc *sc)
2540 * Note that some of this work is not possible if the 2512 * Note that some of this work is not possible if the
2541 * hardware is gone (invalid). 2513 * hardware is gone (invalid).
2542 */ 2514 */
2543 ieee80211_stop_queues(sc->hw); 2515 ieee80211_stop_queues(ah->hw);
2544 2516
2545 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2517 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2546 ath5k_led_off(sc); 2518 ath5k_led_off(ah);
2547 ath5k_hw_set_imr(ah, 0); 2519 ath5k_hw_set_imr(ah, 0);
2548 synchronize_irq(sc->irq); 2520 synchronize_irq(ah->irq);
2549 ath5k_rx_stop(sc); 2521 ath5k_rx_stop(ah);
2550 ath5k_hw_dma_stop(ah); 2522 ath5k_hw_dma_stop(ah);
2551 ath5k_drain_tx_buffs(sc); 2523 ath5k_drain_tx_buffs(ah);
2552 ath5k_hw_phy_disable(ah); 2524 ath5k_hw_phy_disable(ah);
2553 } 2525 }
2554 2526
2555 return 0; 2527 return 0;
2556} 2528}
2557 2529
2558int 2530int ath5k_start(struct ieee80211_hw *hw)
2559ath5k_init_hw(struct ath5k_softc *sc)
2560{ 2531{
2561 struct ath5k_hw *ah = sc->ah; 2532 struct ath5k_hw *ah = hw->priv;
2562 struct ath_common *common = ath5k_hw_common(ah); 2533 struct ath_common *common = ath5k_hw_common(ah);
2563 int ret, i; 2534 int ret, i;
2564 2535
2565 mutex_lock(&sc->lock); 2536 mutex_lock(&ah->lock);
2566 2537
2567 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2538 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
2568 2539
2569 /* 2540 /*
2570 * Stop anything previously setup. This is safe 2541 * Stop anything previously setup. This is safe
2571 * no matter this is the first time through or not. 2542 * no matter this is the first time through or not.
2572 */ 2543 */
2573 ath5k_stop_locked(sc); 2544 ath5k_stop_locked(ah);
2574 2545
2575 /* 2546 /*
2576 * The basic interface to setting the hardware in a good 2547 * The basic interface to setting the hardware in a good
@@ -2579,12 +2550,12 @@ ath5k_init_hw(struct ath5k_softc *sc)
2579 * be followed by initialization of the appropriate bits 2550 * be followed by initialization of the appropriate bits
2580 * and then setup of the interrupt mask. 2551 * and then setup of the interrupt mask.
2581 */ 2552 */
2582 sc->curchan = sc->hw->conf.channel; 2553 ah->curchan = ah->hw->conf.channel;
2583 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2554 ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2584 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2555 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2585 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; 2556 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2586 2557
2587 ret = ath5k_reset(sc, NULL, false); 2558 ret = ath5k_reset(ah, NULL, false);
2588 if (ret) 2559 if (ret)
2589 goto done; 2560 goto done;
2590 2561
@@ -2601,29 +2572,29 @@ ath5k_init_hw(struct ath5k_softc *sc)
2601 * rate */ 2572 * rate */
2602 ah->ah_ack_bitrate_high = true; 2573 ah->ah_ack_bitrate_high = true;
2603 2574
2604 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++) 2575 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2605 sc->bslot[i] = NULL; 2576 ah->bslot[i] = NULL;
2606 2577
2607 ret = 0; 2578 ret = 0;
2608done: 2579done:
2609 mmiowb(); 2580 mmiowb();
2610 mutex_unlock(&sc->lock); 2581 mutex_unlock(&ah->lock);
2611 2582
2612 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2583 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
2613 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2584 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2614 2585
2615 return ret; 2586 return ret;
2616} 2587}
2617 2588
2618static void stop_tasklets(struct ath5k_softc *sc) 2589static void ath5k_stop_tasklets(struct ath5k_hw *ah)
2619{ 2590{
2620 sc->rx_pending = false; 2591 ah->rx_pending = false;
2621 sc->tx_pending = false; 2592 ah->tx_pending = false;
2622 tasklet_kill(&sc->rxtq); 2593 tasklet_kill(&ah->rxtq);
2623 tasklet_kill(&sc->txtq); 2594 tasklet_kill(&ah->txtq);
2624 tasklet_kill(&sc->calib); 2595 tasklet_kill(&ah->calib);
2625 tasklet_kill(&sc->beacontq); 2596 tasklet_kill(&ah->beacontq);
2626 tasklet_kill(&sc->ani_tasklet); 2597 tasklet_kill(&ah->ani_tasklet);
2627} 2598}
2628 2599
2629/* 2600/*
@@ -2632,14 +2603,14 @@ static void stop_tasklets(struct ath5k_softc *sc)
2632 * if another thread does a system call and the thread doing the 2603 * if another thread does a system call and the thread doing the
2633 * stop is preempted). 2604 * stop is preempted).
2634 */ 2605 */
2635int 2606void ath5k_stop(struct ieee80211_hw *hw)
2636ath5k_stop_hw(struct ath5k_softc *sc)
2637{ 2607{
2608 struct ath5k_hw *ah = hw->priv;
2638 int ret; 2609 int ret;
2639 2610
2640 mutex_lock(&sc->lock); 2611 mutex_lock(&ah->lock);
2641 ret = ath5k_stop_locked(sc); 2612 ret = ath5k_stop_locked(ah);
2642 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2613 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
2643 /* 2614 /*
2644 * Don't set the card in full sleep mode! 2615 * Don't set the card in full sleep mode!
2645 * 2616 *
@@ -2660,82 +2631,78 @@ ath5k_stop_hw(struct ath5k_softc *sc)
2660 * and Sam's HAL do anyway). Instead Perform a full reset 2631 * and Sam's HAL do anyway). Instead Perform a full reset
2661 * on the device (same as initial state after attach) and 2632 * on the device (same as initial state after attach) and
2662 * leave it idle (keep MAC/BB on warm reset) */ 2633 * leave it idle (keep MAC/BB on warm reset) */
2663 ret = ath5k_hw_on_hold(sc->ah); 2634 ret = ath5k_hw_on_hold(ah);
2664 2635
2665 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2636 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2666 "putting device to sleep\n"); 2637 "putting device to sleep\n");
2667 } 2638 }
2668 2639
2669 mmiowb(); 2640 mmiowb();
2670 mutex_unlock(&sc->lock); 2641 mutex_unlock(&ah->lock);
2671 2642
2672 stop_tasklets(sc); 2643 ath5k_stop_tasklets(ah);
2673 2644
2674 cancel_delayed_work_sync(&sc->tx_complete_work); 2645 cancel_delayed_work_sync(&ah->tx_complete_work);
2675 2646
2676 ath5k_rfkill_hw_stop(sc->ah); 2647 ath5k_rfkill_hw_stop(ah);
2677
2678 return ret;
2679} 2648}
2680 2649
2681/* 2650/*
2682 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2651 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2683 * and change to the given channel. 2652 * and change to the given channel.
2684 * 2653 *
2685 * This should be called with sc->lock. 2654 * This should be called with ah->lock.
2686 */ 2655 */
2687static int 2656static int
2688ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 2657ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
2689 bool skip_pcu) 2658 bool skip_pcu)
2690{ 2659{
2691 struct ath5k_hw *ah = sc->ah;
2692 struct ath_common *common = ath5k_hw_common(ah); 2660 struct ath_common *common = ath5k_hw_common(ah);
2693 int ret, ani_mode; 2661 int ret, ani_mode;
2694 bool fast; 2662 bool fast;
2695 2663
2696 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2664 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
2697 2665
2698 ath5k_hw_set_imr(ah, 0); 2666 ath5k_hw_set_imr(ah, 0);
2699 synchronize_irq(sc->irq); 2667 synchronize_irq(ah->irq);
2700 stop_tasklets(sc); 2668 ath5k_stop_tasklets(ah);
2701 2669
2702 /* Save ani mode and disable ANI during 2670 /* Save ani mode and disable ANI during
2703 * reset. If we don't we might get false 2671 * reset. If we don't we might get false
2704 * PHY error interrupts. */ 2672 * PHY error interrupts. */
2705 ani_mode = ah->ah_sc->ani_state.ani_mode; 2673 ani_mode = ah->ani_state.ani_mode;
2706 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2674 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2707 2675
2708 /* We are going to empty hw queues 2676 /* We are going to empty hw queues
2709 * so we should also free any remaining 2677 * so we should also free any remaining
2710 * tx buffers */ 2678 * tx buffers */
2711 ath5k_drain_tx_buffs(sc); 2679 ath5k_drain_tx_buffs(ah);
2712 if (chan) 2680 if (chan)
2713 sc->curchan = chan; 2681 ah->curchan = chan;
2714 2682
2715 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; 2683 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2716 2684
2717 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast, 2685 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
2718 skip_pcu);
2719 if (ret) { 2686 if (ret) {
2720 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2687 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
2721 goto err; 2688 goto err;
2722 } 2689 }
2723 2690
2724 ret = ath5k_rx_start(sc); 2691 ret = ath5k_rx_start(ah);
2725 if (ret) { 2692 if (ret) {
2726 ATH5K_ERR(sc, "can't start recv logic\n"); 2693 ATH5K_ERR(ah, "can't start recv logic\n");
2727 goto err; 2694 goto err;
2728 } 2695 }
2729 2696
2730 ath5k_ani_init(ah, ani_mode); 2697 ath5k_ani_init(ah, ani_mode);
2731 2698
2732 ah->ah_cal_next_full = jiffies; 2699 ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100);
2733 ah->ah_cal_next_ani = jiffies; 2700 ah->ah_cal_next_ani = jiffies;
2734 ah->ah_cal_next_nf = jiffies; 2701 ah->ah_cal_next_nf = jiffies;
2735 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2702 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
2736 2703
2737 /* clear survey data and cycle counters */ 2704 /* clear survey data and cycle counters */
2738 memset(&sc->survey, 0, sizeof(sc->survey)); 2705 memset(&ah->survey, 0, sizeof(ah->survey));
2739 spin_lock_bh(&common->cc_lock); 2706 spin_lock_bh(&common->cc_lock);
2740 ath_hw_cycle_counters_update(common); 2707 ath_hw_cycle_counters_update(common);
2741 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2708 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
@@ -2751,12 +2718,12 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2751 * 2718 *
2752 * XXX needed? 2719 * XXX needed?
2753 */ 2720 */
2754/* ath5k_chan_change(sc, c); */ 2721/* ath5k_chan_change(ah, c); */
2755 2722
2756 ath5k_beacon_config(sc); 2723 ath5k_beacon_config(ah);
2757 /* intrs are enabled by ath5k_beacon_config */ 2724 /* intrs are enabled by ath5k_beacon_config */
2758 2725
2759 ieee80211_wake_queues(sc->hw); 2726 ieee80211_wake_queues(ah->hw);
2760 2727
2761 return 0; 2728 return 0;
2762err: 2729err:
@@ -2765,20 +2732,19 @@ err:
2765 2732
2766static void ath5k_reset_work(struct work_struct *work) 2733static void ath5k_reset_work(struct work_struct *work)
2767{ 2734{
2768 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2735 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2769 reset_work); 2736 reset_work);
2770 2737
2771 mutex_lock(&sc->lock); 2738 mutex_lock(&ah->lock);
2772 ath5k_reset(sc, NULL, true); 2739 ath5k_reset(ah, NULL, true);
2773 mutex_unlock(&sc->lock); 2740 mutex_unlock(&ah->lock);
2774} 2741}
2775 2742
2776static int 2743static int __devinit
2777ath5k_init(struct ieee80211_hw *hw) 2744ath5k_init(struct ieee80211_hw *hw)
2778{ 2745{
2779 2746
2780 struct ath5k_softc *sc = hw->priv; 2747 struct ath5k_hw *ah = hw->priv;
2781 struct ath5k_hw *ah = sc->ah;
2782 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2783 struct ath5k_txq *txq; 2749 struct ath5k_txq *txq;
2784 u8 mac[ETH_ALEN] = {}; 2750 u8 mac[ETH_ALEN] = {};
@@ -2797,26 +2763,26 @@ ath5k_init(struct ieee80211_hw *hw)
2797 if (ret < 0) 2763 if (ret < 0)
2798 goto err; 2764 goto err;
2799 if (ret > 0) 2765 if (ret > 0)
2800 __set_bit(ATH_STAT_MRRETRY, sc->status); 2766 __set_bit(ATH_STAT_MRRETRY, ah->status);
2801 2767
2802 /* 2768 /*
2803 * Collect the channel list. The 802.11 layer 2769 * Collect the channel list. The 802.11 layer
2804 * is resposible for filtering this list based 2770 * is responsible for filtering this list based
2805 * on settings like the phy mode and regulatory 2771 * on settings like the phy mode and regulatory
2806 * domain restrictions. 2772 * domain restrictions.
2807 */ 2773 */
2808 ret = ath5k_setup_bands(hw); 2774 ret = ath5k_setup_bands(hw);
2809 if (ret) { 2775 if (ret) {
2810 ATH5K_ERR(sc, "can't get channels\n"); 2776 ATH5K_ERR(ah, "can't get channels\n");
2811 goto err; 2777 goto err;
2812 } 2778 }
2813 2779
2814 /* 2780 /*
2815 * Allocate tx+rx descriptors and populate the lists. 2781 * Allocate tx+rx descriptors and populate the lists.
2816 */ 2782 */
2817 ret = ath5k_desc_alloc(sc); 2783 ret = ath5k_desc_alloc(ah);
2818 if (ret) { 2784 if (ret) {
2819 ATH5K_ERR(sc, "can't allocate descriptors\n"); 2785 ATH5K_ERR(ah, "can't allocate descriptors\n");
2820 goto err; 2786 goto err;
2821 } 2787 }
2822 2788
@@ -2828,14 +2794,14 @@ ath5k_init(struct ieee80211_hw *hw)
2828 */ 2794 */
2829 ret = ath5k_beaconq_setup(ah); 2795 ret = ath5k_beaconq_setup(ah);
2830 if (ret < 0) { 2796 if (ret < 0) {
2831 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 2797 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
2832 goto err_desc; 2798 goto err_desc;
2833 } 2799 }
2834 sc->bhalq = ret; 2800 ah->bhalq = ret;
2835 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 2801 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2836 if (IS_ERR(sc->cabq)) { 2802 if (IS_ERR(ah->cabq)) {
2837 ATH5K_ERR(sc, "can't setup cab queue\n"); 2803 ATH5K_ERR(ah, "can't setup cab queue\n");
2838 ret = PTR_ERR(sc->cabq); 2804 ret = PTR_ERR(ah->cabq);
2839 goto err_bhal; 2805 goto err_bhal;
2840 } 2806 }
2841 2807
@@ -2844,97 +2810,97 @@ ath5k_init(struct ieee80211_hw *hw)
2844 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2810 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2845 /* This order matches mac80211's queue priority, so we can 2811 /* This order matches mac80211's queue priority, so we can
2846 * directly use the mac80211 queue number without any mapping */ 2812 * directly use the mac80211 queue number without any mapping */
2847 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2813 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2848 if (IS_ERR(txq)) { 2814 if (IS_ERR(txq)) {
2849 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2815 ATH5K_ERR(ah, "can't setup xmit queue\n");
2850 ret = PTR_ERR(txq); 2816 ret = PTR_ERR(txq);
2851 goto err_queues; 2817 goto err_queues;
2852 } 2818 }
2853 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2819 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2854 if (IS_ERR(txq)) { 2820 if (IS_ERR(txq)) {
2855 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2821 ATH5K_ERR(ah, "can't setup xmit queue\n");
2856 ret = PTR_ERR(txq); 2822 ret = PTR_ERR(txq);
2857 goto err_queues; 2823 goto err_queues;
2858 } 2824 }
2859 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2825 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2860 if (IS_ERR(txq)) { 2826 if (IS_ERR(txq)) {
2861 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2827 ATH5K_ERR(ah, "can't setup xmit queue\n");
2862 ret = PTR_ERR(txq); 2828 ret = PTR_ERR(txq);
2863 goto err_queues; 2829 goto err_queues;
2864 } 2830 }
2865 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2831 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2866 if (IS_ERR(txq)) { 2832 if (IS_ERR(txq)) {
2867 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2833 ATH5K_ERR(ah, "can't setup xmit queue\n");
2868 ret = PTR_ERR(txq); 2834 ret = PTR_ERR(txq);
2869 goto err_queues; 2835 goto err_queues;
2870 } 2836 }
2871 hw->queues = 4; 2837 hw->queues = 4;
2872 } else { 2838 } else {
2873 /* older hardware (5210) can only support one data queue */ 2839 /* older hardware (5210) can only support one data queue */
2874 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2840 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2875 if (IS_ERR(txq)) { 2841 if (IS_ERR(txq)) {
2876 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2842 ATH5K_ERR(ah, "can't setup xmit queue\n");
2877 ret = PTR_ERR(txq); 2843 ret = PTR_ERR(txq);
2878 goto err_queues; 2844 goto err_queues;
2879 } 2845 }
2880 hw->queues = 1; 2846 hw->queues = 1;
2881 } 2847 }
2882 2848
2883 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 2849 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2884 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 2850 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2885 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 2851 tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
2886 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 2852 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2887 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc); 2853 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
2888 2854
2889 INIT_WORK(&sc->reset_work, ath5k_reset_work); 2855 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2890 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work); 2856 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
2891 2857
2892 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 2858 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
2893 if (ret) { 2859 if (ret) {
2894 ATH5K_ERR(sc, "unable to read address from EEPROM\n"); 2860 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
2895 goto err_queues; 2861 goto err_queues;
2896 } 2862 }
2897 2863
2898 SET_IEEE80211_PERM_ADDR(hw, mac); 2864 SET_IEEE80211_PERM_ADDR(hw, mac);
2899 memcpy(&sc->lladdr, mac, ETH_ALEN); 2865 memcpy(&ah->lladdr, mac, ETH_ALEN);
2900 /* All MAC address bits matter for ACKs */ 2866 /* All MAC address bits matter for ACKs */
2901 ath5k_update_bssid_mask_and_opmode(sc, NULL); 2867 ath5k_update_bssid_mask_and_opmode(ah, NULL);
2902 2868
2903 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 2869 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2904 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 2870 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2905 if (ret) { 2871 if (ret) {
2906 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 2872 ATH5K_ERR(ah, "can't initialize regulatory system\n");
2907 goto err_queues; 2873 goto err_queues;
2908 } 2874 }
2909 2875
2910 ret = ieee80211_register_hw(hw); 2876 ret = ieee80211_register_hw(hw);
2911 if (ret) { 2877 if (ret) {
2912 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 2878 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
2913 goto err_queues; 2879 goto err_queues;
2914 } 2880 }
2915 2881
2916 if (!ath_is_world_regd(regulatory)) 2882 if (!ath_is_world_regd(regulatory))
2917 regulatory_hint(hw->wiphy, regulatory->alpha2); 2883 regulatory_hint(hw->wiphy, regulatory->alpha2);
2918 2884
2919 ath5k_init_leds(sc); 2885 ath5k_init_leds(ah);
2920 2886
2921 ath5k_sysfs_register(sc); 2887 ath5k_sysfs_register(ah);
2922 2888
2923 return 0; 2889 return 0;
2924err_queues: 2890err_queues:
2925 ath5k_txq_release(sc); 2891 ath5k_txq_release(ah);
2926err_bhal: 2892err_bhal:
2927 ath5k_hw_release_tx_queue(ah, sc->bhalq); 2893 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2928err_desc: 2894err_desc:
2929 ath5k_desc_free(sc); 2895 ath5k_desc_free(ah);
2930err: 2896err:
2931 return ret; 2897 return ret;
2932} 2898}
2933 2899
2934void 2900void
2935ath5k_deinit_softc(struct ath5k_softc *sc) 2901ath5k_deinit_softc(struct ath5k_hw *ah)
2936{ 2902{
2937 struct ieee80211_hw *hw = sc->hw; 2903 struct ieee80211_hw *hw = ah->hw;
2938 2904
2939 /* 2905 /*
2940 * NB: the order of these is important: 2906 * NB: the order of these is important:
@@ -2950,23 +2916,23 @@ ath5k_deinit_softc(struct ath5k_softc *sc)
2950 * Other than that, it's straightforward... 2916 * Other than that, it's straightforward...
2951 */ 2917 */
2952 ieee80211_unregister_hw(hw); 2918 ieee80211_unregister_hw(hw);
2953 ath5k_desc_free(sc); 2919 ath5k_desc_free(ah);
2954 ath5k_txq_release(sc); 2920 ath5k_txq_release(ah);
2955 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 2921 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2956 ath5k_unregister_leds(sc); 2922 ath5k_unregister_leds(ah);
2957 2923
2958 ath5k_sysfs_unregister(sc); 2924 ath5k_sysfs_unregister(ah);
2959 /* 2925 /*
2960 * NB: can't reclaim these until after ieee80211_ifdetach 2926 * NB: can't reclaim these until after ieee80211_ifdetach
2961 * returns because we'll get called back to reclaim node 2927 * returns because we'll get called back to reclaim node
2962 * state and potentially want to use them. 2928 * state and potentially want to use them.
2963 */ 2929 */
2964 ath5k_hw_deinit(sc->ah); 2930 ath5k_hw_deinit(ah);
2965 free_irq(sc->irq, sc); 2931 free_irq(ah->irq, ah);
2966} 2932}
2967 2933
2968bool 2934bool
2969ath_any_vif_assoc(struct ath5k_softc *sc) 2935ath5k_any_vif_assoc(struct ath5k_hw *ah)
2970{ 2936{
2971 struct ath5k_vif_iter_data iter_data; 2937 struct ath5k_vif_iter_data iter_data;
2972 iter_data.hw_macaddr = NULL; 2938 iter_data.hw_macaddr = NULL;
@@ -2974,16 +2940,15 @@ ath_any_vif_assoc(struct ath5k_softc *sc)
2974 iter_data.need_set_hw_addr = false; 2940 iter_data.need_set_hw_addr = false;
2975 iter_data.found_active = true; 2941 iter_data.found_active = true;
2976 2942
2977 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 2943 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
2978 &iter_data); 2944 &iter_data);
2979 return iter_data.any_assoc; 2945 return iter_data.any_assoc;
2980} 2946}
2981 2947
2982void 2948void
2983set_beacon_filter(struct ieee80211_hw *hw, bool enable) 2949ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2984{ 2950{
2985 struct ath5k_softc *sc = hw->priv; 2951 struct ath5k_hw *ah = hw->priv;
2986 struct ath5k_hw *ah = sc->ah;
2987 u32 rfilt; 2952 u32 rfilt;
2988 rfilt = ath5k_hw_get_rx_filter(ah); 2953 rfilt = ath5k_hw_get_rx_filter(ah);
2989 if (enable) 2954 if (enable)
@@ -2991,5 +2956,5 @@ set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2991 else 2956 else
2992 rfilt &= ~AR5K_RX_FILTER_BEACON; 2957 rfilt &= ~AR5K_RX_FILTER_BEACON;
2993 ath5k_hw_set_rx_filter(ah, rfilt); 2958 ath5k_hw_set_rx_filter(ah, rfilt);
2994 sc->filter_flags = rfilt; 2959 ah->filter_flags = rfilt;
2995} 2960}
diff --git a/drivers/net/wireless/ath/ath5k/base.h b/drivers/net/wireless/ath/ath5k/base.h
index b294f3305011..a81f28d5bddc 100644
--- a/drivers/net/wireless/ath/ath5k/base.h
+++ b/drivers/net/wireless/ath/ath5k/base.h
@@ -45,23 +45,13 @@
45#include <linux/list.h> 45#include <linux/list.h>
46#include <linux/wireless.h> 46#include <linux/wireless.h>
47#include <linux/if_ether.h> 47#include <linux/if_ether.h>
48#include <linux/leds.h>
49#include <linux/rfkill.h> 48#include <linux/rfkill.h>
50#include <linux/workqueue.h> 49#include <linux/workqueue.h>
51 50
52#include "ath5k.h" 51#include "ath5k.h"
53#include "debug.h"
54#include "ani.h"
55
56#include "../regd.h" 52#include "../regd.h"
57#include "../ath.h" 53#include "../ath.h"
58 54
59#define ATH_RXBUF 40 /* number of RX buffers */
60#define ATH_TXBUF 200 /* number of TX buffers */
61#define ATH_BCBUF 4 /* number of beacon buffers */
62#define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
63#define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
64
65struct ath5k_buf { 55struct ath5k_buf {
66 struct list_head list; 56 struct list_head list;
67 struct ath5k_desc *desc; /* virtual addr of desc */ 57 struct ath5k_desc *desc; /* virtual addr of desc */
@@ -70,95 +60,6 @@ struct ath5k_buf {
70 dma_addr_t skbaddr;/* physical addr of skb data */ 60 dma_addr_t skbaddr;/* physical addr of skb data */
71}; 61};
72 62
73/*
74 * Data transmit queue state. One of these exists for each
75 * hardware transmit queue. Packets sent to us from above
76 * are assigned to queues based on their priority. Not all
77 * devices support a complete set of hardware transmit queues.
78 * For those devices the array sc_ac2q will map multiple
79 * priorities to fewer hardware queues (typically all to one
80 * hardware queue).
81 */
82struct ath5k_txq {
83 unsigned int qnum; /* hardware q number */
84 u32 *link; /* link ptr in last TX desc */
85 struct list_head q; /* transmit queue */
86 spinlock_t lock; /* lock on q and link */
87 bool setup;
88 int txq_len; /* number of queued buffers */
89 int txq_max; /* max allowed num of queued buffers */
90 bool txq_poll_mark;
91 unsigned int txq_stuck; /* informational counter */
92};
93
94#define ATH5K_LED_MAX_NAME_LEN 31
95
96/*
97 * State for LED triggers
98 */
99struct ath5k_led
100{
101 char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
102 struct ath5k_softc *sc; /* driver state */
103 struct led_classdev led_dev; /* led classdev */
104};
105
106/* Rfkill */
107struct ath5k_rfkill {
108 /* GPIO PIN for rfkill */
109 u16 gpio;
110 /* polarity of rfkill GPIO PIN */
111 bool polarity;
112 /* RFKILL toggle tasklet */
113 struct tasklet_struct toggleq;
114};
115
116/* statistics */
117struct ath5k_statistics {
118 /* antenna use */
119 unsigned int antenna_rx[5]; /* frames count per antenna RX */
120 unsigned int antenna_tx[5]; /* frames count per antenna TX */
121
122 /* frame errors */
123 unsigned int rx_all_count; /* all RX frames, including errors */
124 unsigned int tx_all_count; /* all TX frames, including errors */
125 unsigned int rx_bytes_count; /* all RX bytes, including errored pks
126 * and the MAC headers for each packet
127 */
128 unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
129 * and the MAC headers and padding for
130 * each packet.
131 */
132 unsigned int rxerr_crc;
133 unsigned int rxerr_phy;
134 unsigned int rxerr_phy_code[32];
135 unsigned int rxerr_fifo;
136 unsigned int rxerr_decrypt;
137 unsigned int rxerr_mic;
138 unsigned int rxerr_proc;
139 unsigned int rxerr_jumbo;
140 unsigned int txerr_retry;
141 unsigned int txerr_fifo;
142 unsigned int txerr_filt;
143
144 /* MIB counters */
145 unsigned int ack_fail;
146 unsigned int rts_fail;
147 unsigned int rts_ok;
148 unsigned int fcs_error;
149 unsigned int beacons;
150
151 unsigned int mib_intr;
152 unsigned int rxorn_intr;
153 unsigned int rxeol_intr;
154};
155
156#if CHAN_DEBUG
157#define ATH_CHAN_MAX (26+26+26+200+200)
158#else
159#define ATH_CHAN_MAX (14+14+14+252+20)
160#endif
161
162struct ath5k_vif { 63struct ath5k_vif {
163 bool assoc; /* are we associated or not */ 64 bool assoc; /* are we associated or not */
164 enum nl80211_iftype opmode; 65 enum nl80211_iftype opmode;
@@ -167,104 +68,6 @@ struct ath5k_vif {
167 u8 lladdr[ETH_ALEN]; 68 u8 lladdr[ETH_ALEN];
168}; 69};
169 70
170/* Software Carrier, keeps track of the driver state
171 * associated with an instance of a device */
172struct ath5k_softc {
173 struct pci_dev *pdev;
174 struct device *dev; /* for dma mapping */
175 int irq;
176 u16 devid;
177 void __iomem *iobase; /* address of the device */
178 struct mutex lock; /* dev-level lock */
179 struct ieee80211_hw *hw; /* IEEE 802.11 common */
180 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
181 struct ieee80211_channel channels[ATH_CHAN_MAX];
182 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
183 s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
184 enum nl80211_iftype opmode;
185 struct ath5k_hw *ah; /* Atheros HW */
186
187#ifdef CONFIG_ATH5K_DEBUG
188 struct ath5k_dbg_info debug; /* debug info */
189#endif /* CONFIG_ATH5K_DEBUG */
190
191 struct ath5k_buf *bufptr; /* allocated buffer ptr */
192 struct ath5k_desc *desc; /* TX/RX descriptors */
193 dma_addr_t desc_daddr; /* DMA (physical) address */
194 size_t desc_len; /* size of TX/RX descriptors */
195
196 DECLARE_BITMAP(status, 6);
197#define ATH_STAT_INVALID 0 /* disable hardware accesses */
198#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
199#define ATH_STAT_PROMISC 2
200#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
201#define ATH_STAT_STARTED 4 /* opened & irqs enabled */
202#define ATH_STAT_2G_DISABLED 5 /* multiband radio without 2G */
203
204 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
205 struct ieee80211_channel *curchan; /* current h/w channel */
206
207 u16 nvifs;
208
209 enum ath5k_int imask; /* interrupt mask copy */
210
211 spinlock_t irqlock;
212 bool rx_pending; /* rx tasklet pending */
213 bool tx_pending; /* tx tasklet pending */
214
215 u8 lladdr[ETH_ALEN];
216 u8 bssidmask[ETH_ALEN];
217
218 unsigned int led_pin, /* GPIO pin for driving LED */
219 led_on; /* pin setting for LED on */
220
221 struct work_struct reset_work; /* deferred chip reset */
222
223 unsigned int rxbufsize; /* rx size based on mtu */
224 struct list_head rxbuf; /* receive buffer */
225 spinlock_t rxbuflock;
226 u32 *rxlink; /* link ptr in last RX desc */
227 struct tasklet_struct rxtq; /* rx intr tasklet */
228 struct ath5k_led rx_led; /* rx led */
229
230 struct list_head txbuf; /* transmit buffer */
231 spinlock_t txbuflock;
232 unsigned int txbuf_len; /* buf count in txbuf list */
233 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
234 struct tasklet_struct txtq; /* tx intr tasklet */
235 struct ath5k_led tx_led; /* tx led */
236
237 struct ath5k_rfkill rf_kill;
238
239 struct tasklet_struct calib; /* calibration tasklet */
240
241 spinlock_t block; /* protects beacon */
242 struct tasklet_struct beacontq; /* beacon intr tasklet */
243 struct list_head bcbuf; /* beacon buffer */
244 struct ieee80211_vif *bslot[ATH_BCBUF];
245 u16 num_ap_vifs;
246 u16 num_adhoc_vifs;
247 unsigned int bhalq, /* SW q for outgoing beacons */
248 bmisscount, /* missed beacon transmits */
249 bintval, /* beacon interval in TU */
250 bsent;
251 unsigned int nexttbtt; /* next beacon time in TU */
252 struct ath5k_txq *cabq; /* content after beacon */
253
254 int power_level; /* Requested tx power in dbm */
255 bool assoc; /* associate state */
256 bool enable_beacon; /* true if beacons are on */
257
258 struct ath5k_statistics stats;
259
260 struct ath5k_ani_state ani_state;
261 struct tasklet_struct ani_tasklet; /* ANI calibration */
262
263 struct delayed_work tx_complete_work;
264
265 struct survey_info survey; /* collected survey info */
266};
267
268struct ath5k_vif_iter_data { 71struct ath5k_vif_iter_data {
269 const u8 *hw_macaddr; 72 const u8 *hw_macaddr;
270 u8 mask[ETH_ALEN]; 73 u8 mask[ETH_ALEN];
@@ -278,9 +81,10 @@ struct ath5k_vif_iter_data {
278void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif); 81void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif);
279 82
280 83
281#define ath5k_hw_hasbssidmask(_ah) \ 84/* Check whether BSSID mask is supported */
282 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) 85#define ath5k_hw_hasbssidmask(_ah) (ah->ah_version == AR5K_AR5212)
283#define ath5k_hw_hasveol(_ah) \ 86
284 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) 87/* Check whether virtual EOL is supported */
88#define ath5k_hw_hasveol(_ah) (ah->ah_version != AR5K_AR5210)
285 89
286#endif 90#endif
diff --git a/drivers/net/wireless/ath/ath5k/caps.c b/drivers/net/wireless/ath/ath5k/caps.c
index 7dd88e1c3ff8..eefe670e28a7 100644
--- a/drivers/net/wireless/ath/ath5k/caps.c
+++ b/drivers/net/wireless/ath/ath5k/caps.c
@@ -52,8 +52,8 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
52 __set_bit(AR5K_MODE_11A, caps->cap_mode); 52 __set_bit(AR5K_MODE_11A, caps->cap_mode);
53 } else { 53 } else {
54 /* 54 /*
55 * XXX The tranceiver supports frequencies from 4920 to 6100GHz 55 * XXX The transceiver supports frequencies from 4920 to 6100MHz
56 * XXX and from 2312 to 2732GHz. There are problems with the 56 * XXX and from 2312 to 2732MHz. There are problems with the
57 * XXX current ieee80211 implementation because the IEEE 57 * XXX current ieee80211 implementation because the IEEE
58 * XXX channel mapping does not support negative channel 58 * XXX channel mapping does not support negative channel
59 * XXX numbers (2312MHz is channel -19). Of course, this 59 * XXX numbers (2312MHz is channel -19). Of course, this
@@ -112,51 +112,6 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
112 return 0; 112 return 0;
113} 113}
114 114
115/* Main function used by the driver part to check caps */
116int ath5k_hw_get_capability(struct ath5k_hw *ah,
117 enum ath5k_capability_type cap_type,
118 u32 capability, u32 *result)
119{
120 switch (cap_type) {
121 case AR5K_CAP_NUM_TXQUEUES:
122 if (result) {
123 if (ah->ah_version == AR5K_AR5210)
124 *result = AR5K_NUM_TX_QUEUES_NOQCU;
125 else
126 *result = AR5K_NUM_TX_QUEUES;
127 goto yes;
128 }
129 case AR5K_CAP_VEOL:
130 goto yes;
131 case AR5K_CAP_COMPRESSION:
132 if (ah->ah_version == AR5K_AR5212)
133 goto yes;
134 else
135 goto no;
136 case AR5K_CAP_BURST:
137 goto yes;
138 case AR5K_CAP_TPC:
139 goto yes;
140 case AR5K_CAP_BSSIDMASK:
141 if (ah->ah_version == AR5K_AR5212)
142 goto yes;
143 else
144 goto no;
145 case AR5K_CAP_XR:
146 if (ah->ah_version == AR5K_AR5212)
147 goto yes;
148 else
149 goto no;
150 default:
151 goto no;
152 }
153
154no:
155 return -EINVAL;
156yes:
157 return 0;
158}
159
160/* 115/*
161 * TODO: Following functions should be part of a new function 116 * TODO: Following functions should be part of a new function
162 * set_capability 117 * set_capability
diff --git a/drivers/net/wireless/ath/ath5k/debug.c b/drivers/net/wireless/ath/ath5k/debug.c
index 0bf7313b8a17..ccca724de173 100644
--- a/drivers/net/wireless/ath/ath5k/debug.c
+++ b/drivers/net/wireless/ath/ath5k/debug.c
@@ -157,10 +157,10 @@ static void *reg_next(struct seq_file *seq, void *p, loff_t *pos)
157 157
158static int reg_show(struct seq_file *seq, void *p) 158static int reg_show(struct seq_file *seq, void *p)
159{ 159{
160 struct ath5k_softc *sc = seq->private; 160 struct ath5k_hw *ah = seq->private;
161 struct reg *r = p; 161 struct reg *r = p;
162 seq_printf(seq, "%-25s0x%08x\n", r->name, 162 seq_printf(seq, "%-25s0x%08x\n", r->name,
163 ath5k_hw_reg_read(sc->ah, r->addr)); 163 ath5k_hw_reg_read(ah, r->addr));
164 return 0; 164 return 0;
165} 165}
166 166
@@ -197,43 +197,42 @@ static const struct file_operations fops_registers = {
197static ssize_t read_file_beacon(struct file *file, char __user *user_buf, 197static ssize_t read_file_beacon(struct file *file, char __user *user_buf,
198 size_t count, loff_t *ppos) 198 size_t count, loff_t *ppos)
199{ 199{
200 struct ath5k_softc *sc = file->private_data; 200 struct ath5k_hw *ah = file->private_data;
201 struct ath5k_hw *ah = sc->ah;
202 char buf[500]; 201 char buf[500];
203 unsigned int len = 0; 202 unsigned int len = 0;
204 unsigned int v; 203 unsigned int v;
205 u64 tsf; 204 u64 tsf;
206 205
207 v = ath5k_hw_reg_read(sc->ah, AR5K_BEACON); 206 v = ath5k_hw_reg_read(ah, AR5K_BEACON);
208 len += snprintf(buf+len, sizeof(buf)-len, 207 len += snprintf(buf + len, sizeof(buf) - len,
209 "%-24s0x%08x\tintval: %d\tTIM: 0x%x\n", 208 "%-24s0x%08x\tintval: %d\tTIM: 0x%x\n",
210 "AR5K_BEACON", v, v & AR5K_BEACON_PERIOD, 209 "AR5K_BEACON", v, v & AR5K_BEACON_PERIOD,
211 (v & AR5K_BEACON_TIM) >> AR5K_BEACON_TIM_S); 210 (v & AR5K_BEACON_TIM) >> AR5K_BEACON_TIM_S);
212 211
213 len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n", 212 len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\n",
214 "AR5K_LAST_TSTP", ath5k_hw_reg_read(sc->ah, AR5K_LAST_TSTP)); 213 "AR5K_LAST_TSTP", ath5k_hw_reg_read(ah, AR5K_LAST_TSTP));
215 214
216 len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n\n", 215 len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\n\n",
217 "AR5K_BEACON_CNT", ath5k_hw_reg_read(sc->ah, AR5K_BEACON_CNT)); 216 "AR5K_BEACON_CNT", ath5k_hw_reg_read(ah, AR5K_BEACON_CNT));
218 217
219 v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER0); 218 v = ath5k_hw_reg_read(ah, AR5K_TIMER0);
220 len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n", 219 len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\tTU: %08x\n",
221 "AR5K_TIMER0 (TBTT)", v, v); 220 "AR5K_TIMER0 (TBTT)", v, v);
222 221
223 v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER1); 222 v = ath5k_hw_reg_read(ah, AR5K_TIMER1);
224 len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n", 223 len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\tTU: %08x\n",
225 "AR5K_TIMER1 (DMA)", v, v >> 3); 224 "AR5K_TIMER1 (DMA)", v, v >> 3);
226 225
227 v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER2); 226 v = ath5k_hw_reg_read(ah, AR5K_TIMER2);
228 len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n", 227 len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\tTU: %08x\n",
229 "AR5K_TIMER2 (SWBA)", v, v >> 3); 228 "AR5K_TIMER2 (SWBA)", v, v >> 3);
230 229
231 v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER3); 230 v = ath5k_hw_reg_read(ah, AR5K_TIMER3);
232 len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n", 231 len += snprintf(buf + len, sizeof(buf) - len, "%-24s0x%08x\tTU: %08x\n",
233 "AR5K_TIMER3 (ATIM)", v, v); 232 "AR5K_TIMER3 (ATIM)", v, v);
234 233
235 tsf = ath5k_hw_get_tsf64(sc->ah); 234 tsf = ath5k_hw_get_tsf64(ah);
236 len += snprintf(buf+len, sizeof(buf)-len, 235 len += snprintf(buf + len, sizeof(buf) - len,
237 "TSF\t\t0x%016llx\tTU: %08x\n", 236 "TSF\t\t0x%016llx\tTU: %08x\n",
238 (unsigned long long)tsf, TSF_TO_TU(tsf)); 237 (unsigned long long)tsf, TSF_TO_TU(tsf));
239 238
@@ -247,8 +246,7 @@ static ssize_t write_file_beacon(struct file *file,
247 const char __user *userbuf, 246 const char __user *userbuf,
248 size_t count, loff_t *ppos) 247 size_t count, loff_t *ppos)
249{ 248{
250 struct ath5k_softc *sc = file->private_data; 249 struct ath5k_hw *ah = file->private_data;
251 struct ath5k_hw *ah = sc->ah;
252 char buf[20]; 250 char buf[20];
253 251
254 if (copy_from_user(buf, userbuf, min(count, sizeof(buf)))) 252 if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
@@ -279,9 +277,9 @@ static ssize_t write_file_reset(struct file *file,
279 const char __user *userbuf, 277 const char __user *userbuf,
280 size_t count, loff_t *ppos) 278 size_t count, loff_t *ppos)
281{ 279{
282 struct ath5k_softc *sc = file->private_data; 280 struct ath5k_hw *ah = file->private_data;
283 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "debug file triggered reset\n"); 281 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "debug file triggered reset\n");
284 ieee80211_queue_work(sc->hw, &sc->reset_work); 282 ieee80211_queue_work(ah->hw, &ah->reset_work);
285 return count; 283 return count;
286} 284}
287 285
@@ -318,23 +316,23 @@ static const struct {
318static ssize_t read_file_debug(struct file *file, char __user *user_buf, 316static ssize_t read_file_debug(struct file *file, char __user *user_buf,
319 size_t count, loff_t *ppos) 317 size_t count, loff_t *ppos)
320{ 318{
321 struct ath5k_softc *sc = file->private_data; 319 struct ath5k_hw *ah = file->private_data;
322 char buf[700]; 320 char buf[700];
323 unsigned int len = 0; 321 unsigned int len = 0;
324 unsigned int i; 322 unsigned int i;
325 323
326 len += snprintf(buf+len, sizeof(buf)-len, 324 len += snprintf(buf + len, sizeof(buf) - len,
327 "DEBUG LEVEL: 0x%08x\n\n", sc->debug.level); 325 "DEBUG LEVEL: 0x%08x\n\n", ah->debug.level);
328 326
329 for (i = 0; i < ARRAY_SIZE(dbg_info) - 1; i++) { 327 for (i = 0; i < ARRAY_SIZE(dbg_info) - 1; i++) {
330 len += snprintf(buf+len, sizeof(buf)-len, 328 len += snprintf(buf + len, sizeof(buf) - len,
331 "%10s %c 0x%08x - %s\n", dbg_info[i].name, 329 "%10s %c 0x%08x - %s\n", dbg_info[i].name,
332 sc->debug.level & dbg_info[i].level ? '+' : ' ', 330 ah->debug.level & dbg_info[i].level ? '+' : ' ',
333 dbg_info[i].level, dbg_info[i].desc); 331 dbg_info[i].level, dbg_info[i].desc);
334 } 332 }
335 len += snprintf(buf+len, sizeof(buf)-len, 333 len += snprintf(buf + len, sizeof(buf) - len,
336 "%10s %c 0x%08x - %s\n", dbg_info[i].name, 334 "%10s %c 0x%08x - %s\n", dbg_info[i].name,
337 sc->debug.level == dbg_info[i].level ? '+' : ' ', 335 ah->debug.level == dbg_info[i].level ? '+' : ' ',
338 dbg_info[i].level, dbg_info[i].desc); 336 dbg_info[i].level, dbg_info[i].desc);
339 337
340 if (len > sizeof(buf)) 338 if (len > sizeof(buf))
@@ -347,7 +345,7 @@ static ssize_t write_file_debug(struct file *file,
347 const char __user *userbuf, 345 const char __user *userbuf,
348 size_t count, loff_t *ppos) 346 size_t count, loff_t *ppos)
349{ 347{
350 struct ath5k_softc *sc = file->private_data; 348 struct ath5k_hw *ah = file->private_data;
351 unsigned int i; 349 unsigned int i;
352 char buf[20]; 350 char buf[20];
353 351
@@ -357,7 +355,7 @@ static ssize_t write_file_debug(struct file *file,
357 for (i = 0; i < ARRAY_SIZE(dbg_info); i++) { 355 for (i = 0; i < ARRAY_SIZE(dbg_info); i++) {
358 if (strncmp(buf, dbg_info[i].name, 356 if (strncmp(buf, dbg_info[i].name,
359 strlen(dbg_info[i].name)) == 0) { 357 strlen(dbg_info[i].name)) == 0) {
360 sc->debug.level ^= dbg_info[i].level; /* toggle bit */ 358 ah->debug.level ^= dbg_info[i].level; /* toggle bit */
361 break; 359 break;
362 } 360 }
363 } 361 }
@@ -378,66 +376,66 @@ static const struct file_operations fops_debug = {
378static ssize_t read_file_antenna(struct file *file, char __user *user_buf, 376static ssize_t read_file_antenna(struct file *file, char __user *user_buf,
379 size_t count, loff_t *ppos) 377 size_t count, loff_t *ppos)
380{ 378{
381 struct ath5k_softc *sc = file->private_data; 379 struct ath5k_hw *ah = file->private_data;
382 char buf[700]; 380 char buf[700];
383 unsigned int len = 0; 381 unsigned int len = 0;
384 unsigned int i; 382 unsigned int i;
385 unsigned int v; 383 unsigned int v;
386 384
387 len += snprintf(buf+len, sizeof(buf)-len, "antenna mode\t%d\n", 385 len += snprintf(buf + len, sizeof(buf) - len, "antenna mode\t%d\n",
388 sc->ah->ah_ant_mode); 386 ah->ah_ant_mode);
389 len += snprintf(buf+len, sizeof(buf)-len, "default antenna\t%d\n", 387 len += snprintf(buf + len, sizeof(buf) - len, "default antenna\t%d\n",
390 sc->ah->ah_def_ant); 388 ah->ah_def_ant);
391 len += snprintf(buf+len, sizeof(buf)-len, "tx antenna\t%d\n", 389 len += snprintf(buf + len, sizeof(buf) - len, "tx antenna\t%d\n",
392 sc->ah->ah_tx_ant); 390 ah->ah_tx_ant);
393 391
394 len += snprintf(buf+len, sizeof(buf)-len, "\nANTENNA\t\tRX\tTX\n"); 392 len += snprintf(buf + len, sizeof(buf) - len, "\nANTENNA\t\tRX\tTX\n");
395 for (i = 1; i < ARRAY_SIZE(sc->stats.antenna_rx); i++) { 393 for (i = 1; i < ARRAY_SIZE(ah->stats.antenna_rx); i++) {
396 len += snprintf(buf+len, sizeof(buf)-len, 394 len += snprintf(buf + len, sizeof(buf) - len,
397 "[antenna %d]\t%d\t%d\n", 395 "[antenna %d]\t%d\t%d\n",
398 i, sc->stats.antenna_rx[i], sc->stats.antenna_tx[i]); 396 i, ah->stats.antenna_rx[i], ah->stats.antenna_tx[i]);
399 } 397 }
400 len += snprintf(buf+len, sizeof(buf)-len, "[invalid]\t%d\t%d\n", 398 len += snprintf(buf + len, sizeof(buf) - len, "[invalid]\t%d\t%d\n",
401 sc->stats.antenna_rx[0], sc->stats.antenna_tx[0]); 399 ah->stats.antenna_rx[0], ah->stats.antenna_tx[0]);
402 400
403 v = ath5k_hw_reg_read(sc->ah, AR5K_DEFAULT_ANTENNA); 401 v = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
404 len += snprintf(buf+len, sizeof(buf)-len, 402 len += snprintf(buf + len, sizeof(buf) - len,
405 "\nAR5K_DEFAULT_ANTENNA\t0x%08x\n", v); 403 "\nAR5K_DEFAULT_ANTENNA\t0x%08x\n", v);
406 404
407 v = ath5k_hw_reg_read(sc->ah, AR5K_STA_ID1); 405 v = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
408 len += snprintf(buf+len, sizeof(buf)-len, 406 len += snprintf(buf + len, sizeof(buf) - len,
409 "AR5K_STA_ID1_DEFAULT_ANTENNA\t%d\n", 407 "AR5K_STA_ID1_DEFAULT_ANTENNA\t%d\n",
410 (v & AR5K_STA_ID1_DEFAULT_ANTENNA) != 0); 408 (v & AR5K_STA_ID1_DEFAULT_ANTENNA) != 0);
411 len += snprintf(buf+len, sizeof(buf)-len, 409 len += snprintf(buf + len, sizeof(buf) - len,
412 "AR5K_STA_ID1_DESC_ANTENNA\t%d\n", 410 "AR5K_STA_ID1_DESC_ANTENNA\t%d\n",
413 (v & AR5K_STA_ID1_DESC_ANTENNA) != 0); 411 (v & AR5K_STA_ID1_DESC_ANTENNA) != 0);
414 len += snprintf(buf+len, sizeof(buf)-len, 412 len += snprintf(buf + len, sizeof(buf) - len,
415 "AR5K_STA_ID1_RTS_DEF_ANTENNA\t%d\n", 413 "AR5K_STA_ID1_RTS_DEF_ANTENNA\t%d\n",
416 (v & AR5K_STA_ID1_RTS_DEF_ANTENNA) != 0); 414 (v & AR5K_STA_ID1_RTS_DEF_ANTENNA) != 0);
417 len += snprintf(buf+len, sizeof(buf)-len, 415 len += snprintf(buf + len, sizeof(buf) - len,
418 "AR5K_STA_ID1_SELFGEN_DEF_ANT\t%d\n", 416 "AR5K_STA_ID1_SELFGEN_DEF_ANT\t%d\n",
419 (v & AR5K_STA_ID1_SELFGEN_DEF_ANT) != 0); 417 (v & AR5K_STA_ID1_SELFGEN_DEF_ANT) != 0);
420 418
421 v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_AGCCTL); 419 v = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL);
422 len += snprintf(buf+len, sizeof(buf)-len, 420 len += snprintf(buf + len, sizeof(buf) - len,
423 "\nAR5K_PHY_AGCCTL_OFDM_DIV_DIS\t%d\n", 421 "\nAR5K_PHY_AGCCTL_OFDM_DIV_DIS\t%d\n",
424 (v & AR5K_PHY_AGCCTL_OFDM_DIV_DIS) != 0); 422 (v & AR5K_PHY_AGCCTL_OFDM_DIV_DIS) != 0);
425 423
426 v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_RESTART); 424 v = ath5k_hw_reg_read(ah, AR5K_PHY_RESTART);
427 len += snprintf(buf+len, sizeof(buf)-len, 425 len += snprintf(buf + len, sizeof(buf) - len,
428 "AR5K_PHY_RESTART_DIV_GC\t\t%x\n", 426 "AR5K_PHY_RESTART_DIV_GC\t\t%x\n",
429 (v & AR5K_PHY_RESTART_DIV_GC) >> AR5K_PHY_RESTART_DIV_GC_S); 427 (v & AR5K_PHY_RESTART_DIV_GC) >> AR5K_PHY_RESTART_DIV_GC_S);
430 428
431 v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_FAST_ANT_DIV); 429 v = ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ANT_DIV);
432 len += snprintf(buf+len, sizeof(buf)-len, 430 len += snprintf(buf + len, sizeof(buf) - len,
433 "AR5K_PHY_FAST_ANT_DIV_EN\t%d\n", 431 "AR5K_PHY_FAST_ANT_DIV_EN\t%d\n",
434 (v & AR5K_PHY_FAST_ANT_DIV_EN) != 0); 432 (v & AR5K_PHY_FAST_ANT_DIV_EN) != 0);
435 433
436 v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_ANT_SWITCH_TABLE_0); 434 v = ath5k_hw_reg_read(ah, AR5K_PHY_ANT_SWITCH_TABLE_0);
437 len += snprintf(buf+len, sizeof(buf)-len, 435 len += snprintf(buf + len, sizeof(buf) - len,
438 "\nAR5K_PHY_ANT_SWITCH_TABLE_0\t0x%08x\n", v); 436 "\nAR5K_PHY_ANT_SWITCH_TABLE_0\t0x%08x\n", v);
439 v = ath5k_hw_reg_read(sc->ah, AR5K_PHY_ANT_SWITCH_TABLE_1); 437 v = ath5k_hw_reg_read(ah, AR5K_PHY_ANT_SWITCH_TABLE_1);
440 len += snprintf(buf+len, sizeof(buf)-len, 438 len += snprintf(buf + len, sizeof(buf) - len,
441 "AR5K_PHY_ANT_SWITCH_TABLE_1\t0x%08x\n", v); 439 "AR5K_PHY_ANT_SWITCH_TABLE_1\t0x%08x\n", v);
442 440
443 if (len > sizeof(buf)) 441 if (len > sizeof(buf))
@@ -450,7 +448,7 @@ static ssize_t write_file_antenna(struct file *file,
450 const char __user *userbuf, 448 const char __user *userbuf,
451 size_t count, loff_t *ppos) 449 size_t count, loff_t *ppos)
452{ 450{
453 struct ath5k_softc *sc = file->private_data; 451 struct ath5k_hw *ah = file->private_data;
454 unsigned int i; 452 unsigned int i;
455 char buf[20]; 453 char buf[20];
456 454
@@ -458,18 +456,18 @@ static ssize_t write_file_antenna(struct file *file,
458 return -EFAULT; 456 return -EFAULT;
459 457
460 if (strncmp(buf, "diversity", 9) == 0) { 458 if (strncmp(buf, "diversity", 9) == 0) {
461 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT); 459 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
462 printk(KERN_INFO "ath5k debug: enable diversity\n"); 460 printk(KERN_INFO "ath5k debug: enable diversity\n");
463 } else if (strncmp(buf, "fixed-a", 7) == 0) { 461 } else if (strncmp(buf, "fixed-a", 7) == 0) {
464 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A); 462 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_FIXED_A);
465 printk(KERN_INFO "ath5k debugfs: fixed antenna A\n"); 463 printk(KERN_INFO "ath5k debugfs: fixed antenna A\n");
466 } else if (strncmp(buf, "fixed-b", 7) == 0) { 464 } else if (strncmp(buf, "fixed-b", 7) == 0) {
467 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B); 465 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_FIXED_B);
468 printk(KERN_INFO "ath5k debug: fixed antenna B\n"); 466 printk(KERN_INFO "ath5k debug: fixed antenna B\n");
469 } else if (strncmp(buf, "clear", 5) == 0) { 467 } else if (strncmp(buf, "clear", 5) == 0) {
470 for (i = 0; i < ARRAY_SIZE(sc->stats.antenna_rx); i++) { 468 for (i = 0; i < ARRAY_SIZE(ah->stats.antenna_rx); i++) {
471 sc->stats.antenna_rx[i] = 0; 469 ah->stats.antenna_rx[i] = 0;
472 sc->stats.antenna_tx[i] = 0; 470 ah->stats.antenna_tx[i] = 0;
473 } 471 }
474 printk(KERN_INFO "ath5k debug: cleared antenna stats\n"); 472 printk(KERN_INFO "ath5k debug: cleared antenna stats\n");
475 } 473 }
@@ -489,42 +487,42 @@ static const struct file_operations fops_antenna = {
489static ssize_t read_file_misc(struct file *file, char __user *user_buf, 487static ssize_t read_file_misc(struct file *file, char __user *user_buf,
490 size_t count, loff_t *ppos) 488 size_t count, loff_t *ppos)
491{ 489{
492 struct ath5k_softc *sc = file->private_data; 490 struct ath5k_hw *ah = file->private_data;
493 char buf[700]; 491 char buf[700];
494 unsigned int len = 0; 492 unsigned int len = 0;
495 u32 filt = ath5k_hw_get_rx_filter(sc->ah); 493 u32 filt = ath5k_hw_get_rx_filter(ah);
496 494
497 len += snprintf(buf+len, sizeof(buf)-len, "bssid-mask: %pM\n", 495 len += snprintf(buf + len, sizeof(buf) - len, "bssid-mask: %pM\n",
498 sc->bssidmask); 496 ah->bssidmask);
499 len += snprintf(buf+len, sizeof(buf)-len, "filter-flags: 0x%x ", 497 len += snprintf(buf + len, sizeof(buf) - len, "filter-flags: 0x%x ",
500 filt); 498 filt);
501 if (filt & AR5K_RX_FILTER_UCAST) 499 if (filt & AR5K_RX_FILTER_UCAST)
502 len += snprintf(buf+len, sizeof(buf)-len, " UCAST"); 500 len += snprintf(buf + len, sizeof(buf) - len, " UCAST");
503 if (filt & AR5K_RX_FILTER_MCAST) 501 if (filt & AR5K_RX_FILTER_MCAST)
504 len += snprintf(buf+len, sizeof(buf)-len, " MCAST"); 502 len += snprintf(buf + len, sizeof(buf) - len, " MCAST");
505 if (filt & AR5K_RX_FILTER_BCAST) 503 if (filt & AR5K_RX_FILTER_BCAST)
506 len += snprintf(buf+len, sizeof(buf)-len, " BCAST"); 504 len += snprintf(buf + len, sizeof(buf) - len, " BCAST");
507 if (filt & AR5K_RX_FILTER_CONTROL) 505 if (filt & AR5K_RX_FILTER_CONTROL)
508 len += snprintf(buf+len, sizeof(buf)-len, " CONTROL"); 506 len += snprintf(buf + len, sizeof(buf) - len, " CONTROL");
509 if (filt & AR5K_RX_FILTER_BEACON) 507 if (filt & AR5K_RX_FILTER_BEACON)
510 len += snprintf(buf+len, sizeof(buf)-len, " BEACON"); 508 len += snprintf(buf + len, sizeof(buf) - len, " BEACON");
511 if (filt & AR5K_RX_FILTER_PROM) 509 if (filt & AR5K_RX_FILTER_PROM)
512 len += snprintf(buf+len, sizeof(buf)-len, " PROM"); 510 len += snprintf(buf + len, sizeof(buf) - len, " PROM");
513 if (filt & AR5K_RX_FILTER_XRPOLL) 511 if (filt & AR5K_RX_FILTER_XRPOLL)
514 len += snprintf(buf+len, sizeof(buf)-len, " XRPOLL"); 512 len += snprintf(buf + len, sizeof(buf) - len, " XRPOLL");
515 if (filt & AR5K_RX_FILTER_PROBEREQ) 513 if (filt & AR5K_RX_FILTER_PROBEREQ)
516 len += snprintf(buf+len, sizeof(buf)-len, " PROBEREQ"); 514 len += snprintf(buf + len, sizeof(buf) - len, " PROBEREQ");
517 if (filt & AR5K_RX_FILTER_PHYERR_5212) 515 if (filt & AR5K_RX_FILTER_PHYERR_5212)
518 len += snprintf(buf+len, sizeof(buf)-len, " PHYERR-5212"); 516 len += snprintf(buf + len, sizeof(buf) - len, " PHYERR-5212");
519 if (filt & AR5K_RX_FILTER_RADARERR_5212) 517 if (filt & AR5K_RX_FILTER_RADARERR_5212)
520 len += snprintf(buf+len, sizeof(buf)-len, " RADARERR-5212"); 518 len += snprintf(buf + len, sizeof(buf) - len, " RADARERR-5212");
521 if (filt & AR5K_RX_FILTER_PHYERR_5211) 519 if (filt & AR5K_RX_FILTER_PHYERR_5211)
522 snprintf(buf+len, sizeof(buf)-len, " PHYERR-5211"); 520 snprintf(buf + len, sizeof(buf) - len, " PHYERR-5211");
523 if (filt & AR5K_RX_FILTER_RADARERR_5211) 521 if (filt & AR5K_RX_FILTER_RADARERR_5211)
524 len += snprintf(buf+len, sizeof(buf)-len, " RADARERR-5211"); 522 len += snprintf(buf + len, sizeof(buf) - len, " RADARERR-5211");
525 523
526 len += snprintf(buf+len, sizeof(buf)-len, "\nopmode: %s (%d)\n", 524 len += snprintf(buf + len, sizeof(buf) - len, "\nopmode: %s (%d)\n",
527 ath_opmode_to_string(sc->opmode), sc->opmode); 525 ath_opmode_to_string(ah->opmode), ah->opmode);
528 526
529 if (len > sizeof(buf)) 527 if (len > sizeof(buf))
530 len = sizeof(buf); 528 len = sizeof(buf);
@@ -544,71 +542,71 @@ static const struct file_operations fops_misc = {
544static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf, 542static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf,
545 size_t count, loff_t *ppos) 543 size_t count, loff_t *ppos)
546{ 544{
547 struct ath5k_softc *sc = file->private_data; 545 struct ath5k_hw *ah = file->private_data;
548 struct ath5k_statistics *st = &sc->stats; 546 struct ath5k_statistics *st = &ah->stats;
549 char buf[700]; 547 char buf[700];
550 unsigned int len = 0; 548 unsigned int len = 0;
551 int i; 549 int i;
552 550
553 len += snprintf(buf+len, sizeof(buf)-len, 551 len += snprintf(buf + len, sizeof(buf) - len,
554 "RX\n---------------------\n"); 552 "RX\n---------------------\n");
555 len += snprintf(buf+len, sizeof(buf)-len, "CRC\t%u\t(%u%%)\n", 553 len += snprintf(buf + len, sizeof(buf) - len, "CRC\t%u\t(%u%%)\n",
556 st->rxerr_crc, 554 st->rxerr_crc,
557 st->rx_all_count > 0 ? 555 st->rx_all_count > 0 ?
558 st->rxerr_crc*100/st->rx_all_count : 0); 556 st->rxerr_crc * 100 / st->rx_all_count : 0);
559 len += snprintf(buf+len, sizeof(buf)-len, "PHY\t%u\t(%u%%)\n", 557 len += snprintf(buf + len, sizeof(buf) - len, "PHY\t%u\t(%u%%)\n",
560 st->rxerr_phy, 558 st->rxerr_phy,
561 st->rx_all_count > 0 ? 559 st->rx_all_count > 0 ?
562 st->rxerr_phy*100/st->rx_all_count : 0); 560 st->rxerr_phy * 100 / st->rx_all_count : 0);
563 for (i = 0; i < 32; i++) { 561 for (i = 0; i < 32; i++) {
564 if (st->rxerr_phy_code[i]) 562 if (st->rxerr_phy_code[i])
565 len += snprintf(buf+len, sizeof(buf)-len, 563 len += snprintf(buf + len, sizeof(buf) - len,
566 " phy_err[%u]\t%u\n", 564 " phy_err[%u]\t%u\n",
567 i, st->rxerr_phy_code[i]); 565 i, st->rxerr_phy_code[i]);
568 } 566 }
569 567
570 len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%u\t(%u%%)\n", 568 len += snprintf(buf + len, sizeof(buf) - len, "FIFO\t%u\t(%u%%)\n",
571 st->rxerr_fifo, 569 st->rxerr_fifo,
572 st->rx_all_count > 0 ? 570 st->rx_all_count > 0 ?
573 st->rxerr_fifo*100/st->rx_all_count : 0); 571 st->rxerr_fifo * 100 / st->rx_all_count : 0);
574 len += snprintf(buf+len, sizeof(buf)-len, "decrypt\t%u\t(%u%%)\n", 572 len += snprintf(buf + len, sizeof(buf) - len, "decrypt\t%u\t(%u%%)\n",
575 st->rxerr_decrypt, 573 st->rxerr_decrypt,
576 st->rx_all_count > 0 ? 574 st->rx_all_count > 0 ?
577 st->rxerr_decrypt*100/st->rx_all_count : 0); 575 st->rxerr_decrypt * 100 / st->rx_all_count : 0);
578 len += snprintf(buf+len, sizeof(buf)-len, "MIC\t%u\t(%u%%)\n", 576 len += snprintf(buf + len, sizeof(buf) - len, "MIC\t%u\t(%u%%)\n",
579 st->rxerr_mic, 577 st->rxerr_mic,
580 st->rx_all_count > 0 ? 578 st->rx_all_count > 0 ?
581 st->rxerr_mic*100/st->rx_all_count : 0); 579 st->rxerr_mic * 100 / st->rx_all_count : 0);
582 len += snprintf(buf+len, sizeof(buf)-len, "process\t%u\t(%u%%)\n", 580 len += snprintf(buf + len, sizeof(buf) - len, "process\t%u\t(%u%%)\n",
583 st->rxerr_proc, 581 st->rxerr_proc,
584 st->rx_all_count > 0 ? 582 st->rx_all_count > 0 ?
585 st->rxerr_proc*100/st->rx_all_count : 0); 583 st->rxerr_proc * 100 / st->rx_all_count : 0);
586 len += snprintf(buf+len, sizeof(buf)-len, "jumbo\t%u\t(%u%%)\n", 584 len += snprintf(buf + len, sizeof(buf) - len, "jumbo\t%u\t(%u%%)\n",
587 st->rxerr_jumbo, 585 st->rxerr_jumbo,
588 st->rx_all_count > 0 ? 586 st->rx_all_count > 0 ?
589 st->rxerr_jumbo*100/st->rx_all_count : 0); 587 st->rxerr_jumbo * 100 / st->rx_all_count : 0);
590 len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%u]\n", 588 len += snprintf(buf + len, sizeof(buf) - len, "[RX all\t%u]\n",
591 st->rx_all_count); 589 st->rx_all_count);
592 len += snprintf(buf+len, sizeof(buf)-len, "RX-all-bytes\t%u\n", 590 len += snprintf(buf + len, sizeof(buf) - len, "RX-all-bytes\t%u\n",
593 st->rx_bytes_count); 591 st->rx_bytes_count);
594 592
595 len += snprintf(buf+len, sizeof(buf)-len, 593 len += snprintf(buf + len, sizeof(buf) - len,
596 "\nTX\n---------------------\n"); 594 "\nTX\n---------------------\n");
597 len += snprintf(buf+len, sizeof(buf)-len, "retry\t%u\t(%u%%)\n", 595 len += snprintf(buf + len, sizeof(buf) - len, "retry\t%u\t(%u%%)\n",
598 st->txerr_retry, 596 st->txerr_retry,
599 st->tx_all_count > 0 ? 597 st->tx_all_count > 0 ?
600 st->txerr_retry*100/st->tx_all_count : 0); 598 st->txerr_retry * 100 / st->tx_all_count : 0);
601 len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%u\t(%u%%)\n", 599 len += snprintf(buf + len, sizeof(buf) - len, "FIFO\t%u\t(%u%%)\n",
602 st->txerr_fifo, 600 st->txerr_fifo,
603 st->tx_all_count > 0 ? 601 st->tx_all_count > 0 ?
604 st->txerr_fifo*100/st->tx_all_count : 0); 602 st->txerr_fifo * 100 / st->tx_all_count : 0);
605 len += snprintf(buf+len, sizeof(buf)-len, "filter\t%u\t(%u%%)\n", 603 len += snprintf(buf + len, sizeof(buf) - len, "filter\t%u\t(%u%%)\n",
606 st->txerr_filt, 604 st->txerr_filt,
607 st->tx_all_count > 0 ? 605 st->tx_all_count > 0 ?
608 st->txerr_filt*100/st->tx_all_count : 0); 606 st->txerr_filt * 100 / st->tx_all_count : 0);
609 len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%u]\n", 607 len += snprintf(buf + len, sizeof(buf) - len, "[TX all\t%u]\n",
610 st->tx_all_count); 608 st->tx_all_count);
611 len += snprintf(buf+len, sizeof(buf)-len, "TX-all-bytes\t%u\n", 609 len += snprintf(buf + len, sizeof(buf) - len, "TX-all-bytes\t%u\n",
612 st->tx_bytes_count); 610 st->tx_bytes_count);
613 611
614 if (len > sizeof(buf)) 612 if (len > sizeof(buf))
@@ -621,8 +619,8 @@ static ssize_t write_file_frameerrors(struct file *file,
621 const char __user *userbuf, 619 const char __user *userbuf,
622 size_t count, loff_t *ppos) 620 size_t count, loff_t *ppos)
623{ 621{
624 struct ath5k_softc *sc = file->private_data; 622 struct ath5k_hw *ah = file->private_data;
625 struct ath5k_statistics *st = &sc->stats; 623 struct ath5k_statistics *st = &ah->stats;
626 char buf[20]; 624 char buf[20];
627 625
628 if (copy_from_user(buf, userbuf, min(count, sizeof(buf)))) 626 if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
@@ -660,100 +658,104 @@ static const struct file_operations fops_frameerrors = {
660static ssize_t read_file_ani(struct file *file, char __user *user_buf, 658static ssize_t read_file_ani(struct file *file, char __user *user_buf,
661 size_t count, loff_t *ppos) 659 size_t count, loff_t *ppos)
662{ 660{
663 struct ath5k_softc *sc = file->private_data; 661 struct ath5k_hw *ah = file->private_data;
664 struct ath5k_statistics *st = &sc->stats; 662 struct ath5k_statistics *st = &ah->stats;
665 struct ath5k_ani_state *as = &sc->ani_state; 663 struct ath5k_ani_state *as = &ah->ani_state;
666 664
667 char buf[700]; 665 char buf[700];
668 unsigned int len = 0; 666 unsigned int len = 0;
669 667
670 len += snprintf(buf+len, sizeof(buf)-len, 668 len += snprintf(buf + len, sizeof(buf) - len,
671 "HW has PHY error counters:\t%s\n", 669 "HW has PHY error counters:\t%s\n",
672 sc->ah->ah_capabilities.cap_has_phyerr_counters ? 670 ah->ah_capabilities.cap_has_phyerr_counters ?
673 "yes" : "no"); 671 "yes" : "no");
674 len += snprintf(buf+len, sizeof(buf)-len, 672 len += snprintf(buf + len, sizeof(buf) - len,
675 "HW max spur immunity level:\t%d\n", 673 "HW max spur immunity level:\t%d\n",
676 as->max_spur_level); 674 as->max_spur_level);
677 len += snprintf(buf+len, sizeof(buf)-len, 675 len += snprintf(buf + len, sizeof(buf) - len,
678 "\nANI state\n--------------------------------------------\n"); 676 "\nANI state\n--------------------------------------------\n");
679 len += snprintf(buf+len, sizeof(buf)-len, "operating mode:\t\t\t"); 677 len += snprintf(buf + len, sizeof(buf) - len, "operating mode:\t\t\t");
680 switch (as->ani_mode) { 678 switch (as->ani_mode) {
681 case ATH5K_ANI_MODE_OFF: 679 case ATH5K_ANI_MODE_OFF:
682 len += snprintf(buf+len, sizeof(buf)-len, "OFF\n"); 680 len += snprintf(buf + len, sizeof(buf) - len, "OFF\n");
683 break; 681 break;
684 case ATH5K_ANI_MODE_MANUAL_LOW: 682 case ATH5K_ANI_MODE_MANUAL_LOW:
685 len += snprintf(buf+len, sizeof(buf)-len, 683 len += snprintf(buf + len, sizeof(buf) - len,
686 "MANUAL LOW\n"); 684 "MANUAL LOW\n");
687 break; 685 break;
688 case ATH5K_ANI_MODE_MANUAL_HIGH: 686 case ATH5K_ANI_MODE_MANUAL_HIGH:
689 len += snprintf(buf+len, sizeof(buf)-len, 687 len += snprintf(buf + len, sizeof(buf) - len,
690 "MANUAL HIGH\n"); 688 "MANUAL HIGH\n");
691 break; 689 break;
692 case ATH5K_ANI_MODE_AUTO: 690 case ATH5K_ANI_MODE_AUTO:
693 len += snprintf(buf+len, sizeof(buf)-len, "AUTO\n"); 691 len += snprintf(buf + len, sizeof(buf) - len, "AUTO\n");
694 break; 692 break;
695 default: 693 default:
696 len += snprintf(buf+len, sizeof(buf)-len, 694 len += snprintf(buf + len, sizeof(buf) - len,
697 "??? (not good)\n"); 695 "??? (not good)\n");
698 break; 696 break;
699 } 697 }
700 len += snprintf(buf+len, sizeof(buf)-len, 698 len += snprintf(buf + len, sizeof(buf) - len,
701 "noise immunity level:\t\t%d\n", 699 "noise immunity level:\t\t%d\n",
702 as->noise_imm_level); 700 as->noise_imm_level);
703 len += snprintf(buf+len, sizeof(buf)-len, 701 len += snprintf(buf + len, sizeof(buf) - len,
704 "spur immunity level:\t\t%d\n", 702 "spur immunity level:\t\t%d\n",
705 as->spur_level); 703 as->spur_level);
706 len += snprintf(buf+len, sizeof(buf)-len, "firstep level:\t\t\t%d\n", 704 len += snprintf(buf + len, sizeof(buf) - len,
705 "firstep level:\t\t\t%d\n",
707 as->firstep_level); 706 as->firstep_level);
708 len += snprintf(buf+len, sizeof(buf)-len, 707 len += snprintf(buf + len, sizeof(buf) - len,
709 "OFDM weak signal detection:\t%s\n", 708 "OFDM weak signal detection:\t%s\n",
710 as->ofdm_weak_sig ? "on" : "off"); 709 as->ofdm_weak_sig ? "on" : "off");
711 len += snprintf(buf+len, sizeof(buf)-len, 710 len += snprintf(buf + len, sizeof(buf) - len,
712 "CCK weak signal detection:\t%s\n", 711 "CCK weak signal detection:\t%s\n",
713 as->cck_weak_sig ? "on" : "off"); 712 as->cck_weak_sig ? "on" : "off");
714 713
715 len += snprintf(buf+len, sizeof(buf)-len, 714 len += snprintf(buf + len, sizeof(buf) - len,
716 "\nMIB INTERRUPTS:\t\t%u\n", 715 "\nMIB INTERRUPTS:\t\t%u\n",
717 st->mib_intr); 716 st->mib_intr);
718 len += snprintf(buf+len, sizeof(buf)-len, 717 len += snprintf(buf + len, sizeof(buf) - len,
719 "beacon RSSI average:\t%d\n", 718 "beacon RSSI average:\t%d\n",
720 (int)ewma_read(&sc->ah->ah_beacon_rssi_avg)); 719 (int)ewma_read(&ah->ah_beacon_rssi_avg));
721 720
722#define CC_PRINT(_struct, _field) \ 721#define CC_PRINT(_struct, _field) \
723 _struct._field, \ 722 _struct._field, \
724 _struct.cycles > 0 ? \ 723 _struct.cycles > 0 ? \
725 _struct._field*100/_struct.cycles : 0 724 _struct._field * 100 / _struct.cycles : 0
726 725
727 len += snprintf(buf+len, sizeof(buf)-len, "profcnt tx\t\t%u\t(%d%%)\n", 726 len += snprintf(buf + len, sizeof(buf) - len,
727 "profcnt tx\t\t%u\t(%d%%)\n",
728 CC_PRINT(as->last_cc, tx_frame)); 728 CC_PRINT(as->last_cc, tx_frame));
729 len += snprintf(buf+len, sizeof(buf)-len, "profcnt rx\t\t%u\t(%d%%)\n", 729 len += snprintf(buf + len, sizeof(buf) - len,
730 "profcnt rx\t\t%u\t(%d%%)\n",
730 CC_PRINT(as->last_cc, rx_frame)); 731 CC_PRINT(as->last_cc, rx_frame));
731 len += snprintf(buf+len, sizeof(buf)-len, "profcnt busy\t\t%u\t(%d%%)\n", 732 len += snprintf(buf + len, sizeof(buf) - len,
733 "profcnt busy\t\t%u\t(%d%%)\n",
732 CC_PRINT(as->last_cc, rx_busy)); 734 CC_PRINT(as->last_cc, rx_busy));
733#undef CC_PRINT 735#undef CC_PRINT
734 len += snprintf(buf+len, sizeof(buf)-len, "profcnt cycles\t\t%u\n", 736 len += snprintf(buf + len, sizeof(buf) - len, "profcnt cycles\t\t%u\n",
735 as->last_cc.cycles); 737 as->last_cc.cycles);
736 len += snprintf(buf+len, sizeof(buf)-len, 738 len += snprintf(buf + len, sizeof(buf) - len,
737 "listen time\t\t%d\tlast: %d\n", 739 "listen time\t\t%d\tlast: %d\n",
738 as->listen_time, as->last_listen); 740 as->listen_time, as->last_listen);
739 len += snprintf(buf+len, sizeof(buf)-len, 741 len += snprintf(buf + len, sizeof(buf) - len,
740 "OFDM errors\t\t%u\tlast: %u\tsum: %u\n", 742 "OFDM errors\t\t%u\tlast: %u\tsum: %u\n",
741 as->ofdm_errors, as->last_ofdm_errors, 743 as->ofdm_errors, as->last_ofdm_errors,
742 as->sum_ofdm_errors); 744 as->sum_ofdm_errors);
743 len += snprintf(buf+len, sizeof(buf)-len, 745 len += snprintf(buf + len, sizeof(buf) - len,
744 "CCK errors\t\t%u\tlast: %u\tsum: %u\n", 746 "CCK errors\t\t%u\tlast: %u\tsum: %u\n",
745 as->cck_errors, as->last_cck_errors, 747 as->cck_errors, as->last_cck_errors,
746 as->sum_cck_errors); 748 as->sum_cck_errors);
747 len += snprintf(buf+len, sizeof(buf)-len, 749 len += snprintf(buf + len, sizeof(buf) - len,
748 "AR5K_PHYERR_CNT1\t%x\t(=%d)\n", 750 "AR5K_PHYERR_CNT1\t%x\t(=%d)\n",
749 ath5k_hw_reg_read(sc->ah, AR5K_PHYERR_CNT1), 751 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1),
750 ATH5K_ANI_OFDM_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX - 752 ATH5K_ANI_OFDM_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX -
751 ath5k_hw_reg_read(sc->ah, AR5K_PHYERR_CNT1))); 753 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1)));
752 len += snprintf(buf+len, sizeof(buf)-len, 754 len += snprintf(buf + len, sizeof(buf) - len,
753 "AR5K_PHYERR_CNT2\t%x\t(=%d)\n", 755 "AR5K_PHYERR_CNT2\t%x\t(=%d)\n",
754 ath5k_hw_reg_read(sc->ah, AR5K_PHYERR_CNT2), 756 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2),
755 ATH5K_ANI_CCK_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX - 757 ATH5K_ANI_CCK_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX -
756 ath5k_hw_reg_read(sc->ah, AR5K_PHYERR_CNT2))); 758 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2)));
757 759
758 if (len > sizeof(buf)) 760 if (len > sizeof(buf))
759 len = sizeof(buf); 761 len = sizeof(buf);
@@ -765,42 +767,42 @@ static ssize_t write_file_ani(struct file *file,
765 const char __user *userbuf, 767 const char __user *userbuf,
766 size_t count, loff_t *ppos) 768 size_t count, loff_t *ppos)
767{ 769{
768 struct ath5k_softc *sc = file->private_data; 770 struct ath5k_hw *ah = file->private_data;
769 char buf[20]; 771 char buf[20];
770 772
771 if (copy_from_user(buf, userbuf, min(count, sizeof(buf)))) 773 if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
772 return -EFAULT; 774 return -EFAULT;
773 775
774 if (strncmp(buf, "sens-low", 8) == 0) { 776 if (strncmp(buf, "sens-low", 8) == 0) {
775 ath5k_ani_init(sc->ah, ATH5K_ANI_MODE_MANUAL_HIGH); 777 ath5k_ani_init(ah, ATH5K_ANI_MODE_MANUAL_HIGH);
776 } else if (strncmp(buf, "sens-high", 9) == 0) { 778 } else if (strncmp(buf, "sens-high", 9) == 0) {
777 ath5k_ani_init(sc->ah, ATH5K_ANI_MODE_MANUAL_LOW); 779 ath5k_ani_init(ah, ATH5K_ANI_MODE_MANUAL_LOW);
778 } else if (strncmp(buf, "ani-off", 7) == 0) { 780 } else if (strncmp(buf, "ani-off", 7) == 0) {
779 ath5k_ani_init(sc->ah, ATH5K_ANI_MODE_OFF); 781 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
780 } else if (strncmp(buf, "ani-on", 6) == 0) { 782 } else if (strncmp(buf, "ani-on", 6) == 0) {
781 ath5k_ani_init(sc->ah, ATH5K_ANI_MODE_AUTO); 783 ath5k_ani_init(ah, ATH5K_ANI_MODE_AUTO);
782 } else if (strncmp(buf, "noise-low", 9) == 0) { 784 } else if (strncmp(buf, "noise-low", 9) == 0) {
783 ath5k_ani_set_noise_immunity_level(sc->ah, 0); 785 ath5k_ani_set_noise_immunity_level(ah, 0);
784 } else if (strncmp(buf, "noise-high", 10) == 0) { 786 } else if (strncmp(buf, "noise-high", 10) == 0) {
785 ath5k_ani_set_noise_immunity_level(sc->ah, 787 ath5k_ani_set_noise_immunity_level(ah,
786 ATH5K_ANI_MAX_NOISE_IMM_LVL); 788 ATH5K_ANI_MAX_NOISE_IMM_LVL);
787 } else if (strncmp(buf, "spur-low", 8) == 0) { 789 } else if (strncmp(buf, "spur-low", 8) == 0) {
788 ath5k_ani_set_spur_immunity_level(sc->ah, 0); 790 ath5k_ani_set_spur_immunity_level(ah, 0);
789 } else if (strncmp(buf, "spur-high", 9) == 0) { 791 } else if (strncmp(buf, "spur-high", 9) == 0) {
790 ath5k_ani_set_spur_immunity_level(sc->ah, 792 ath5k_ani_set_spur_immunity_level(ah,
791 sc->ani_state.max_spur_level); 793 ah->ani_state.max_spur_level);
792 } else if (strncmp(buf, "fir-low", 7) == 0) { 794 } else if (strncmp(buf, "fir-low", 7) == 0) {
793 ath5k_ani_set_firstep_level(sc->ah, 0); 795 ath5k_ani_set_firstep_level(ah, 0);
794 } else if (strncmp(buf, "fir-high", 8) == 0) { 796 } else if (strncmp(buf, "fir-high", 8) == 0) {
795 ath5k_ani_set_firstep_level(sc->ah, ATH5K_ANI_MAX_FIRSTEP_LVL); 797 ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL);
796 } else if (strncmp(buf, "ofdm-off", 8) == 0) { 798 } else if (strncmp(buf, "ofdm-off", 8) == 0) {
797 ath5k_ani_set_ofdm_weak_signal_detection(sc->ah, false); 799 ath5k_ani_set_ofdm_weak_signal_detection(ah, false);
798 } else if (strncmp(buf, "ofdm-on", 7) == 0) { 800 } else if (strncmp(buf, "ofdm-on", 7) == 0) {
799 ath5k_ani_set_ofdm_weak_signal_detection(sc->ah, true); 801 ath5k_ani_set_ofdm_weak_signal_detection(ah, true);
800 } else if (strncmp(buf, "cck-off", 7) == 0) { 802 } else if (strncmp(buf, "cck-off", 7) == 0) {
801 ath5k_ani_set_cck_weak_signal_detection(sc->ah, false); 803 ath5k_ani_set_cck_weak_signal_detection(ah, false);
802 } else if (strncmp(buf, "cck-on", 6) == 0) { 804 } else if (strncmp(buf, "cck-on", 6) == 0) {
803 ath5k_ani_set_cck_weak_signal_detection(sc->ah, true); 805 ath5k_ani_set_cck_weak_signal_detection(ah, true);
804 } 806 }
805 return count; 807 return count;
806} 808}
@@ -819,7 +821,7 @@ static const struct file_operations fops_ani = {
819static ssize_t read_file_queue(struct file *file, char __user *user_buf, 821static ssize_t read_file_queue(struct file *file, char __user *user_buf,
820 size_t count, loff_t *ppos) 822 size_t count, loff_t *ppos)
821{ 823{
822 struct ath5k_softc *sc = file->private_data; 824 struct ath5k_hw *ah = file->private_data;
823 char buf[700]; 825 char buf[700];
824 unsigned int len = 0; 826 unsigned int len = 0;
825 827
@@ -827,13 +829,13 @@ static ssize_t read_file_queue(struct file *file, char __user *user_buf,
827 struct ath5k_buf *bf, *bf0; 829 struct ath5k_buf *bf, *bf0;
828 int i, n; 830 int i, n;
829 831
830 len += snprintf(buf+len, sizeof(buf)-len, 832 len += snprintf(buf + len, sizeof(buf) - len,
831 "available txbuffers: %d\n", sc->txbuf_len); 833 "available txbuffers: %d\n", ah->txbuf_len);
832 834
833 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 835 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
834 txq = &sc->txqs[i]; 836 txq = &ah->txqs[i];
835 837
836 len += snprintf(buf+len, sizeof(buf)-len, 838 len += snprintf(buf + len, sizeof(buf) - len,
837 "%02d: %ssetup\n", i, txq->setup ? "" : "not "); 839 "%02d: %ssetup\n", i, txq->setup ? "" : "not ");
838 840
839 if (!txq->setup) 841 if (!txq->setup)
@@ -845,9 +847,9 @@ static ssize_t read_file_queue(struct file *file, char __user *user_buf,
845 n++; 847 n++;
846 spin_unlock_bh(&txq->lock); 848 spin_unlock_bh(&txq->lock);
847 849
848 len += snprintf(buf+len, sizeof(buf)-len, 850 len += snprintf(buf + len, sizeof(buf) - len,
849 " len: %d bufs: %d\n", txq->txq_len, n); 851 " len: %d bufs: %d\n", txq->txq_len, n);
850 len += snprintf(buf+len, sizeof(buf)-len, 852 len += snprintf(buf + len, sizeof(buf) - len,
851 " stuck: %d\n", txq->txq_stuck); 853 " stuck: %d\n", txq->txq_stuck);
852 } 854 }
853 855
@@ -861,16 +863,16 @@ static ssize_t write_file_queue(struct file *file,
861 const char __user *userbuf, 863 const char __user *userbuf,
862 size_t count, loff_t *ppos) 864 size_t count, loff_t *ppos)
863{ 865{
864 struct ath5k_softc *sc = file->private_data; 866 struct ath5k_hw *ah = file->private_data;
865 char buf[20]; 867 char buf[20];
866 868
867 if (copy_from_user(buf, userbuf, min(count, sizeof(buf)))) 869 if (copy_from_user(buf, userbuf, min(count, sizeof(buf))))
868 return -EFAULT; 870 return -EFAULT;
869 871
870 if (strncmp(buf, "start", 5) == 0) 872 if (strncmp(buf, "start", 5) == 0)
871 ieee80211_wake_queues(sc->hw); 873 ieee80211_wake_queues(ah->hw);
872 else if (strncmp(buf, "stop", 4) == 0) 874 else if (strncmp(buf, "stop", 4) == 0)
873 ieee80211_stop_queues(sc->hw); 875 ieee80211_stop_queues(ah->hw);
874 876
875 return count; 877 return count;
876} 878}
@@ -886,54 +888,57 @@ static const struct file_operations fops_queue = {
886 888
887 889
888void 890void
889ath5k_debug_init_device(struct ath5k_softc *sc) 891ath5k_debug_init_device(struct ath5k_hw *ah)
890{ 892{
891 struct dentry *phydir; 893 struct dentry *phydir;
892 894
893 sc->debug.level = ath5k_debug; 895 ah->debug.level = ath5k_debug;
894 896
895 phydir = debugfs_create_dir("ath5k", sc->hw->wiphy->debugfsdir); 897 phydir = debugfs_create_dir("ath5k", ah->hw->wiphy->debugfsdir);
896 if (!phydir) 898 if (!phydir)
897 return; 899 return;
898 900
899 debugfs_create_file("debug", S_IWUSR | S_IRUSR, phydir, sc, 901 debugfs_create_file("debug", S_IWUSR | S_IRUSR, phydir, ah,
900 &fops_debug); 902 &fops_debug);
901 903
902 debugfs_create_file("registers", S_IRUSR, phydir, sc, &fops_registers); 904 debugfs_create_file("registers", S_IRUSR, phydir, ah, &fops_registers);
903 905
904 debugfs_create_file("beacon", S_IWUSR | S_IRUSR, phydir, sc, 906 debugfs_create_file("beacon", S_IWUSR | S_IRUSR, phydir, ah,
905 &fops_beacon); 907 &fops_beacon);
906 908
907 debugfs_create_file("reset", S_IWUSR, phydir, sc, &fops_reset); 909 debugfs_create_file("reset", S_IWUSR, phydir, ah, &fops_reset);
908 910
909 debugfs_create_file("antenna", S_IWUSR | S_IRUSR, phydir, sc, 911 debugfs_create_file("antenna", S_IWUSR | S_IRUSR, phydir, ah,
910 &fops_antenna); 912 &fops_antenna);
911 913
912 debugfs_create_file("misc", S_IRUSR, phydir, sc, &fops_misc); 914 debugfs_create_file("misc", S_IRUSR, phydir, ah, &fops_misc);
913 915
914 debugfs_create_file("frameerrors", S_IWUSR | S_IRUSR, phydir, sc, 916 debugfs_create_file("frameerrors", S_IWUSR | S_IRUSR, phydir, ah,
915 &fops_frameerrors); 917 &fops_frameerrors);
916 918
917 debugfs_create_file("ani", S_IWUSR | S_IRUSR, phydir, sc, &fops_ani); 919 debugfs_create_file("ani", S_IWUSR | S_IRUSR, phydir, ah, &fops_ani);
918 920
919 debugfs_create_file("queue", S_IWUSR | S_IRUSR, phydir, sc, 921 debugfs_create_file("queue", S_IWUSR | S_IRUSR, phydir, ah,
920 &fops_queue); 922 &fops_queue);
923
924 debugfs_create_bool("32khz_clock", S_IWUSR | S_IRUSR, phydir,
925 &ah->ah_use_32khz_clock);
921} 926}
922 927
923/* functions used in other places */ 928/* functions used in other places */
924 929
925void 930void
926ath5k_debug_dump_bands(struct ath5k_softc *sc) 931ath5k_debug_dump_bands(struct ath5k_hw *ah)
927{ 932{
928 unsigned int b, i; 933 unsigned int b, i;
929 934
930 if (likely(!(sc->debug.level & ATH5K_DEBUG_DUMPBANDS))) 935 if (likely(!(ah->debug.level & ATH5K_DEBUG_DUMPBANDS)))
931 return; 936 return;
932 937
933 BUG_ON(!sc->sbands); 938 BUG_ON(!ah->sbands);
934 939
935 for (b = 0; b < IEEE80211_NUM_BANDS; b++) { 940 for (b = 0; b < IEEE80211_NUM_BANDS; b++) {
936 struct ieee80211_supported_band *band = &sc->sbands[b]; 941 struct ieee80211_supported_band *band = &ah->sbands[b];
937 char bname[6]; 942 char bname[6];
938 switch (band->band) { 943 switch (band->band) {
939 case IEEE80211_BAND_2GHZ: 944 case IEEE80211_BAND_2GHZ:
@@ -983,41 +988,41 @@ ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done,
983} 988}
984 989
985void 990void
986ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah) 991ath5k_debug_printrxbuffs(struct ath5k_hw *ah)
987{ 992{
988 struct ath5k_desc *ds; 993 struct ath5k_desc *ds;
989 struct ath5k_buf *bf; 994 struct ath5k_buf *bf;
990 struct ath5k_rx_status rs = {}; 995 struct ath5k_rx_status rs = {};
991 int status; 996 int status;
992 997
993 if (likely(!(sc->debug.level & ATH5K_DEBUG_DESC))) 998 if (likely(!(ah->debug.level & ATH5K_DEBUG_DESC)))
994 return; 999 return;
995 1000
996 printk(KERN_DEBUG "rxdp %x, rxlink %p\n", 1001 printk(KERN_DEBUG "rxdp %x, rxlink %p\n",
997 ath5k_hw_get_rxdp(ah), sc->rxlink); 1002 ath5k_hw_get_rxdp(ah), ah->rxlink);
998 1003
999 spin_lock_bh(&sc->rxbuflock); 1004 spin_lock_bh(&ah->rxbuflock);
1000 list_for_each_entry(bf, &sc->rxbuf, list) { 1005 list_for_each_entry(bf, &ah->rxbuf, list) {
1001 ds = bf->desc; 1006 ds = bf->desc;
1002 status = ah->ah_proc_rx_desc(ah, ds, &rs); 1007 status = ah->ah_proc_rx_desc(ah, ds, &rs);
1003 if (!status) 1008 if (!status)
1004 ath5k_debug_printrxbuf(bf, status == 0, &rs); 1009 ath5k_debug_printrxbuf(bf, status == 0, &rs);
1005 } 1010 }
1006 spin_unlock_bh(&sc->rxbuflock); 1011 spin_unlock_bh(&ah->rxbuflock);
1007} 1012}
1008 1013
1009void 1014void
1010ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf) 1015ath5k_debug_printtxbuf(struct ath5k_hw *ah, struct ath5k_buf *bf)
1011{ 1016{
1012 struct ath5k_desc *ds = bf->desc; 1017 struct ath5k_desc *ds = bf->desc;
1013 struct ath5k_hw_5212_tx_desc *td = &ds->ud.ds_tx5212; 1018 struct ath5k_hw_5212_tx_desc *td = &ds->ud.ds_tx5212;
1014 struct ath5k_tx_status ts = {}; 1019 struct ath5k_tx_status ts = {};
1015 int done; 1020 int done;
1016 1021
1017 if (likely(!(sc->debug.level & ATH5K_DEBUG_DESC))) 1022 if (likely(!(ah->debug.level & ATH5K_DEBUG_DESC)))
1018 return; 1023 return;
1019 1024
1020 done = sc->ah->ah_proc_tx_desc(sc->ah, bf->desc, &ts); 1025 done = ah->ah_proc_tx_desc(ah, bf->desc, &ts);
1021 1026
1022 printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x " 1027 printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x "
1023 "%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link, 1028 "%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link,
diff --git a/drivers/net/wireless/ath/ath5k/debug.h b/drivers/net/wireless/ath/ath5k/debug.h
index 193dd2d4ea3c..7f37df3125fd 100644
--- a/drivers/net/wireless/ath/ath5k/debug.h
+++ b/drivers/net/wireless/ath/ath5k/debug.h
@@ -61,7 +61,6 @@
61#ifndef _ATH5K_DEBUG_H 61#ifndef _ATH5K_DEBUG_H
62#define _ATH5K_DEBUG_H 62#define _ATH5K_DEBUG_H
63 63
64struct ath5k_softc;
65struct ath5k_hw; 64struct ath5k_hw;
66struct sk_buff; 65struct sk_buff;
67struct ath5k_buf; 66struct ath5k_buf;
@@ -127,39 +126,39 @@ enum ath5k_debug_level {
127 } while (0) 126 } while (0)
128 127
129void 128void
130ath5k_debug_init_device(struct ath5k_softc *sc); 129ath5k_debug_init_device(struct ath5k_hw *ah);
131 130
132void 131void
133ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah); 132ath5k_debug_printrxbuffs(struct ath5k_hw *ah);
134 133
135void 134void
136ath5k_debug_dump_bands(struct ath5k_softc *sc); 135ath5k_debug_dump_bands(struct ath5k_hw *ah);
137 136
138void 137void
139ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf); 138ath5k_debug_printtxbuf(struct ath5k_hw *ah, struct ath5k_buf *bf);
140 139
141#else /* no debugging */ 140#else /* no debugging */
142 141
143#include <linux/compiler.h> 142#include <linux/compiler.h>
144 143
145static inline void __attribute__ ((format (printf, 3, 4))) 144static inline void __attribute__ ((format (printf, 3, 4)))
146ATH5K_DBG(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...) {} 145ATH5K_DBG(struct ath5k_hw *ah, unsigned int m, const char *fmt, ...) {}
147 146
148static inline void __attribute__ ((format (printf, 3, 4))) 147static inline void __attribute__ ((format (printf, 3, 4)))
149ATH5K_DBG_UNLIMIT(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...) 148ATH5K_DBG_UNLIMIT(struct ath5k_hw *ah, unsigned int m, const char *fmt, ...)
150{} 149{}
151 150
152static inline void 151static inline void
153ath5k_debug_init_device(struct ath5k_softc *sc) {} 152ath5k_debug_init_device(struct ath5k_hw *ah) {}
154 153
155static inline void 154static inline void
156ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah) {} 155ath5k_debug_printrxbuffs(struct ath5k_hw *ah) {}
157 156
158static inline void 157static inline void
159ath5k_debug_dump_bands(struct ath5k_softc *sc) {} 158ath5k_debug_dump_bands(struct ath5k_hw *ah) {}
160 159
161static inline void 160static inline void
162ath5k_debug_printtxbuf(struct ath5k_softc *sc, struct ath5k_buf *bf) {} 161ath5k_debug_printtxbuf(struct ath5k_hw *ah, struct ath5k_buf *bf) {}
163 162
164#endif /* ifdef CONFIG_ATH5K_DEBUG */ 163#endif /* ifdef CONFIG_ATH5K_DEBUG */
165 164
diff --git a/drivers/net/wireless/ath/ath5k/desc.c b/drivers/net/wireless/ath/ath5k/desc.c
index f82383b3ed30..846535f59efc 100644
--- a/drivers/net/wireless/ath/ath5k/desc.c
+++ b/drivers/net/wireless/ath/ath5k/desc.c
@@ -55,12 +55,12 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
55 * noise on the channel, so it is important to avoid this. 55 * noise on the channel, so it is important to avoid this.
56 */ 56 */
57 if (unlikely(tx_tries0 == 0)) { 57 if (unlikely(tx_tries0 == 0)) {
58 ATH5K_ERR(ah->ah_sc, "zero retries\n"); 58 ATH5K_ERR(ah, "zero retries\n");
59 WARN_ON(1); 59 WARN_ON(1);
60 return -EINVAL; 60 return -EINVAL;
61 } 61 }
62 if (unlikely(tx_rate0 == 0)) { 62 if (unlikely(tx_rate0 == 0)) {
63 ATH5K_ERR(ah->ah_sc, "zero rate\n"); 63 ATH5K_ERR(ah, "zero rate\n");
64 WARN_ON(1); 64 WARN_ON(1);
65 return -EINVAL; 65 return -EINVAL;
66 } 66 }
@@ -203,12 +203,12 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
203 * noise on the channel, so it is important to avoid this. 203 * noise on the channel, so it is important to avoid this.
204 */ 204 */
205 if (unlikely(tx_tries0 == 0)) { 205 if (unlikely(tx_tries0 == 0)) {
206 ATH5K_ERR(ah->ah_sc, "zero retries\n"); 206 ATH5K_ERR(ah, "zero retries\n");
207 WARN_ON(1); 207 WARN_ON(1);
208 return -EINVAL; 208 return -EINVAL;
209 } 209 }
210 if (unlikely(tx_rate0 == 0)) { 210 if (unlikely(tx_rate0 == 0)) {
211 ATH5K_ERR(ah->ah_sc, "zero rate\n"); 211 ATH5K_ERR(ah, "zero rate\n");
212 WARN_ON(1); 212 WARN_ON(1);
213 return -EINVAL; 213 return -EINVAL;
214 } 214 }
@@ -316,7 +316,7 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
316 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) || 316 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
317 (tx_rate2 == 0 && tx_tries2 != 0) || 317 (tx_rate2 == 0 && tx_tries2 != 0) ||
318 (tx_rate3 == 0 && tx_tries3 != 0))) { 318 (tx_rate3 == 0 && tx_tries3 != 0))) {
319 ATH5K_ERR(ah->ah_sc, "zero rate\n"); 319 ATH5K_ERR(ah, "zero rate\n");
320 WARN_ON(1); 320 WARN_ON(1);
321 return -EINVAL; 321 return -EINVAL;
322 } 322 }
diff --git a/drivers/net/wireless/ath/ath5k/desc.h b/drivers/net/wireless/ath/ath5k/desc.h
index 2509d0bf037d..cfd529b548f3 100644
--- a/drivers/net/wireless/ath/ath5k/desc.h
+++ b/drivers/net/wireless/ath/ath5k/desc.h
@@ -58,11 +58,11 @@ struct ath5k_hw_rx_status {
58#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 /* reception success */ 58#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 /* reception success */
59#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004 /* CRC error */ 59#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004 /* CRC error */
60#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210 0x00000008 /* [5210] FIFO overrun */ 60#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210 0x00000008 /* [5210] FIFO overrun */
61#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 /* decyption CRC failure */ 61#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 /* decryption CRC failure */
62#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 /* PHY error */ 62#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 /* PHY error */
63#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5 63#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5
64#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 /* key index valid */ 64#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 /* key index valid */
65#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 /* decyption key index */ 65#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 /* decryption key index */
66#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9 66#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9
67#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 /* 13 bit of TSF */ 67#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 /* 13 bit of TSF */
68#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 68#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15
diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index 21091c26a9a5..0d5d4033f12a 100644
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -25,7 +25,7 @@
25 * 25 *
26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and 26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
27 * handle queue setup for 5210 chipset (rest are handled on qcu.c). 27 * handle queue setup for 5210 chipset (rest are handled on qcu.c).
28 * Also we setup interrupt mask register (IMR) and read the various iterrupt 28 * Also we setup interrupt mask register (IMR) and read the various interrupt
29 * status registers (ISR). 29 * status registers (ISR).
30 * 30 *
31 * TODO: Handle SISR on 5211+ and introduce a function to return the queue 31 * TODO: Handle SISR on 5211+ and introduce a function to return the queue
@@ -73,7 +73,7 @@ static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
73 udelay(100); 73 udelay(100);
74 74
75 if (!i) 75 if (!i)
76 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA, 76 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
77 "failed to stop RX DMA !\n"); 77 "failed to stop RX DMA !\n");
78 78
79 return i ? 0 : -EBUSY; 79 return i ? 0 : -EBUSY;
@@ -100,7 +100,7 @@ u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
100int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) 100int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
101{ 101{
102 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) { 102 if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
103 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA, 103 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
104 "tried to set RXDP while rx was active !\n"); 104 "tried to set RXDP while rx was active !\n");
105 return -EIO; 105 return -EIO;
106 } 106 }
@@ -243,7 +243,7 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
243 udelay(100); 243 udelay(100);
244 244
245 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) 245 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
246 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA, 246 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
247 "queue %i didn't stop !\n", queue); 247 "queue %i didn't stop !\n", queue);
248 248
249 /* Check for pending frames */ 249 /* Check for pending frames */
@@ -258,7 +258,7 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
258 /* For 2413+ order PCU to drop packets using 258 /* For 2413+ order PCU to drop packets using
259 * QUIET mechanism */ 259 * QUIET mechanism */
260 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && 260 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) &&
261 pending){ 261 pending) {
262 /* Set periodicity and duration */ 262 /* Set periodicity and duration */
263 ath5k_hw_reg_write(ah, 263 ath5k_hw_reg_write(ah,
264 AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)| 264 AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)|
@@ -295,7 +295,7 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
295 AR5K_DIAG_SW_CHANNEL_IDLE_HIGH); 295 AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
296 296
297 if (pending) 297 if (pending)
298 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA, 298 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
299 "quiet mechanism didn't work q:%i !\n", 299 "quiet mechanism didn't work q:%i !\n",
300 queue); 300 queue);
301 } 301 }
@@ -309,7 +309,7 @@ static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
309 /* Clear register */ 309 /* Clear register */
310 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD); 310 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
311 if (pending) { 311 if (pending) {
312 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA, 312 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
313 "tx dma didn't stop (q:%i, frm:%i) !\n", 313 "tx dma didn't stop (q:%i, frm:%i) !\n",
314 queue, pending); 314 queue, pending);
315 return -EBUSY; 315 return -EBUSY;
@@ -333,7 +333,7 @@ int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
333 int ret; 333 int ret;
334 ret = ath5k_hw_stop_tx_dma(ah, queue); 334 ret = ath5k_hw_stop_tx_dma(ah, queue);
335 if (ret) { 335 if (ret) {
336 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA, 336 ATH5K_DBG(ah, ATH5K_DEBUG_DMA,
337 "beacon queue didn't stop !\n"); 337 "beacon queue didn't stop !\n");
338 return -EIO; 338 return -EIO;
339 } 339 }
@@ -726,7 +726,7 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
726 int_mask |= AR5K_IMR_RXDOPPLER; 726 int_mask |= AR5K_IMR_RXDOPPLER;
727 727
728 /* Note: Per queue interrupt masks 728 /* Note: Per queue interrupt masks
729 * are set via reset_tx_queue (qcu.c) */ 729 * are set via ath5k_hw_reset_tx_queue() (qcu.c) */
730 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); 730 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
731 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2); 731 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2);
732 732
@@ -783,7 +783,7 @@ void ath5k_hw_dma_init(struct ath5k_hw *ah)
783 * for all PCI-E cards to be safe). 783 * for all PCI-E cards to be safe).
784 * 784 *
785 * XXX: need to check 5210 for this 785 * XXX: need to check 5210 for this
786 * TODO: Check out tx triger level, it's always 64 on dumps but I 786 * TODO: Check out tx trigger level, it's always 64 on dumps but I
787 * guess we can tweak it and see how it goes ;-) 787 * guess we can tweak it and see how it goes ;-)
788 */ 788 */
789 if (ah->ah_version != AR5K_AR5210) { 789 if (ah->ah_version != AR5K_AR5210) {
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c
index 392771f93759..9068b9165265 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.c
+++ b/drivers/net/wireless/ath/ath5k/eeprom.c
@@ -105,7 +105,7 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
105 * big still, waiting on a better value. 105 * big still, waiting on a better value.
106 */ 106 */
107 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) { 107 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
108 ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: " 108 ATH5K_ERR(ah, "Invalid max custom EEPROM size: "
109 "%d (0x%04x) max expected: %d (0x%04x)\n", 109 "%d (0x%04x) max expected: %d (0x%04x)\n",
110 eep_max, eep_max, 110 eep_max, eep_max,
111 3 * AR5K_EEPROM_INFO_MAX, 111 3 * AR5K_EEPROM_INFO_MAX,
@@ -119,7 +119,7 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
119 cksum ^= val; 119 cksum ^= val;
120 } 120 }
121 if (cksum != AR5K_EEPROM_INFO_CKSUM) { 121 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
122 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM " 122 ATH5K_ERR(ah, "Invalid EEPROM "
123 "checksum: 0x%04x eep_max: 0x%04x (%s)\n", 123 "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
124 cksum, eep_max, 124 cksum, eep_max,
125 eep_max == AR5K_EEPROM_INFO_MAX ? 125 eep_max == AR5K_EEPROM_INFO_MAX ?
@@ -223,14 +223,14 @@ static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
223 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] = 223 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
224 (ee->ee_ant_control[mode][0] << 4); 224 (ee->ee_ant_control[mode][0] << 4);
225 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] = 225 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
226 ee->ee_ant_control[mode][1] | 226 ee->ee_ant_control[mode][1] |
227 (ee->ee_ant_control[mode][2] << 6) | 227 (ee->ee_ant_control[mode][2] << 6) |
228 (ee->ee_ant_control[mode][3] << 12) | 228 (ee->ee_ant_control[mode][3] << 12) |
229 (ee->ee_ant_control[mode][4] << 18) | 229 (ee->ee_ant_control[mode][4] << 18) |
230 (ee->ee_ant_control[mode][5] << 24); 230 (ee->ee_ant_control[mode][5] << 24);
231 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] = 231 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
232 ee->ee_ant_control[mode][6] | 232 ee->ee_ant_control[mode][6] |
233 (ee->ee_ant_control[mode][7] << 6) | 233 (ee->ee_ant_control[mode][7] << 6) |
234 (ee->ee_ant_control[mode][8] << 12) | 234 (ee->ee_ant_control[mode][8] << 12) |
235 (ee->ee_ant_control[mode][9] << 18) | 235 (ee->ee_ant_control[mode][9] << 18) |
236 (ee->ee_ant_control[mode][10] << 24); 236 (ee->ee_ant_control[mode][10] << 24);
@@ -255,7 +255,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
255 ee->ee_n_piers[mode] = 0; 255 ee->ee_n_piers[mode] = 0;
256 AR5K_EEPROM_READ(o++, val); 256 AR5K_EEPROM_READ(o++, val);
257 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); 257 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
258 switch(mode) { 258 switch (mode) {
259 case AR5K_EEPROM_MODE_11A: 259 case AR5K_EEPROM_MODE_11A:
260 ee->ee_ob[mode][3] = (val >> 5) & 0x7; 260 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
261 ee->ee_db[mode][3] = (val >> 2) & 0x7; 261 ee->ee_db[mode][3] = (val >> 2) & 0x7;
@@ -349,7 +349,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
349 /* Note: >= v5 have bg freq piers on another location 349 /* Note: >= v5 have bg freq piers on another location
350 * so these freq piers are ignored for >= v5 (should be 0xff 350 * so these freq piers are ignored for >= v5 (should be 0xff
351 * anyway) */ 351 * anyway) */
352 switch(mode) { 352 switch (mode) {
353 case AR5K_EEPROM_MODE_11A: 353 case AR5K_EEPROM_MODE_11A:
354 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1) 354 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
355 break; 355 break;
@@ -422,7 +422,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
422 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0) 422 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
423 goto done; 423 goto done;
424 424
425 switch (mode){ 425 switch (mode) {
426 case AR5K_EEPROM_MODE_11A: 426 case AR5K_EEPROM_MODE_11A:
427 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f; 427 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
428 428
@@ -436,7 +436,7 @@ static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
436 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7; 436 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
437 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff; 437 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
438 438
439 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2) 439 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >= 2)
440 ee->ee_pd_gain_overlap = (val >> 9) & 0xf; 440 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
441 break; 441 break;
442 case AR5K_EEPROM_MODE_11G: 442 case AR5K_EEPROM_MODE_11G:
@@ -516,7 +516,7 @@ ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
516 u16 val; 516 u16 val;
517 517
518 ee->ee_n_piers[mode] = 0; 518 ee->ee_n_piers[mode] = 0;
519 while(i < max) { 519 while (i < max) {
520 AR5K_EEPROM_READ(o++, val); 520 AR5K_EEPROM_READ(o++, val);
521 521
522 freq1 = val & 0xff; 522 freq1 = val & 0xff;
@@ -602,7 +602,7 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
602 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 602 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
603 struct ath5k_chan_pcal_info *pcal; 603 struct ath5k_chan_pcal_info *pcal;
604 604
605 switch(mode) { 605 switch (mode) {
606 case AR5K_EEPROM_MODE_11B: 606 case AR5K_EEPROM_MODE_11B:
607 pcal = ee->ee_pwr_cal_b; 607 pcal = ee->ee_pwr_cal_b;
608 break; 608 break;
@@ -634,7 +634,7 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
634/* Used to match PCDAC steps with power values on RF5111 chips 634/* Used to match PCDAC steps with power values on RF5111 chips
635 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC 635 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
636 * steps that match with the power values we read from eeprom. On 636 * steps that match with the power values we read from eeprom. On
637 * older eeprom versions (< 3.2) these steps are equaly spaced at 637 * older eeprom versions (< 3.2) these steps are equally spaced at
638 * 10% of the pcdac curve -until the curve reaches its maximum- 638 * 10% of the pcdac curve -until the curve reaches its maximum-
639 * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2) 639 * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
640 * these 11 steps are spaced in a different way. This function returns 640 * these 11 steps are spaced in a different way. This function returns
@@ -644,10 +644,12 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
644static inline void 644static inline void
645ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp) 645ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
646{ 646{
647 static const u16 intercepts3[] = 647 static const u16 intercepts3[] = {
648 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 }; 648 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100
649 static const u16 intercepts3_2[] = 649 };
650 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 }; 650 static const u16 intercepts3_2[] = {
651 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100
652 };
651 const u16 *ip; 653 const u16 *ip;
652 int i; 654 int i;
653 655
@@ -762,7 +764,7 @@ ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
762 764
763 /* Fill raw dataset 765 /* Fill raw dataset
764 * (convert power to 0.25dB units 766 * (convert power to 0.25dB units
765 * for RF5112 combatibility) */ 767 * for RF5112 compatibility) */
766 for (point = 0; point < pd->pd_points; point++) { 768 for (point = 0; point < pd->pd_points; point++) {
767 769
768 /* Absolute values */ 770 /* Absolute values */
@@ -796,7 +798,7 @@ ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
796 u16 val; 798 u16 val;
797 799
798 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); 800 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
799 switch(mode) { 801 switch (mode) {
800 case AR5K_EEPROM_MODE_11A: 802 case AR5K_EEPROM_MODE_11A:
801 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) 803 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
802 return 0; 804 return 0;
@@ -882,7 +884,7 @@ ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
882 * Read power calibration for RF5112 chips 884 * Read power calibration for RF5112 chips
883 * 885 *
884 * For RF5112 we have 4 XPD -eXternal Power Detector- curves 886 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
885 * for each calibrated channel on 0, -6, -12 and -18dbm but we only 887 * for each calibrated channel on 0, -6, -12 and -18dBm but we only
886 * use the higher (3) and the lower (0) curves. Each curve has 0.5dB 888 * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
887 * power steps on x axis and PCDAC steps on y axis and looks like a 889 * power steps on x axis and PCDAC steps on y axis and looks like a
888 * linear function. To recreate the curve and pass the power values 890 * linear function. To recreate the curve and pass the power values
@@ -1163,7 +1165,7 @@ ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1163{ 1165{
1164 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4); 1166 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1165 1167
1166 switch(mode) { 1168 switch (mode) {
1167 case AR5K_EEPROM_MODE_11G: 1169 case AR5K_EEPROM_MODE_11G:
1168 if (AR5K_EEPROM_HDR_11B(ee->ee_header)) 1170 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1169 offset += ath5k_pdgains_size_2413(ee, 1171 offset += ath5k_pdgains_size_2413(ee,
@@ -1239,7 +1241,7 @@ ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1239 1241
1240 /* Fill raw dataset 1242 /* Fill raw dataset
1241 * convert all pwr levels to 1243 * convert all pwr levels to
1242 * quarter dB for RF5112 combatibility */ 1244 * quarter dB for RF5112 compatibility */
1243 pd->pd_step[0] = pcinfo->pddac_i[pdg]; 1245 pd->pd_step[0] = pcinfo->pddac_i[pdg];
1244 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg]; 1246 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1245 1247
@@ -1620,8 +1622,8 @@ ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1620 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version); 1622 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1621 1623
1622 rep = ee->ee_ctl_pwr; 1624 rep = ee->ee_ctl_pwr;
1623 for(i = 0; i < ee->ee_ctls; i++) { 1625 for (i = 0; i < ee->ee_ctls; i++) {
1624 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) { 1626 switch (ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1625 case AR5K_CTL_11A: 1627 case AR5K_CTL_11A:
1626 case AR5K_CTL_TURBO: 1628 case AR5K_CTL_TURBO:
1627 ctl_mode = AR5K_EEPROM_MODE_11A; 1629 ctl_mode = AR5K_EEPROM_MODE_11A;
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h
index 6511c27d938e..dc2bcfeadeb4 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.h
+++ b/drivers/net/wireless/ath/ath5k/eeprom.h
@@ -50,7 +50,7 @@
50 50
51#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */ 51#define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) /* EEPROM Version */
52#define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */ 52#define AR5K_EEPROM_VERSION_3_0 0x3000 /* No idea what's going on before this version */
53#define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2Ghz (ar5211_rfregs) */ 53#define AR5K_EEPROM_VERSION_3_1 0x3001 /* ob/db values for 2GHz (ar5211_rfregs) */
54#define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */ 54#define AR5K_EEPROM_VERSION_3_2 0x3002 /* different frequency representation (eeprom_bin2freq) */
55#define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */ 55#define AR5K_EEPROM_VERSION_3_3 0x3003 /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
56#define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */ 56#define AR5K_EEPROM_VERSION_3_4 0x3004 /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
@@ -75,11 +75,11 @@
75#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1) 75#define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
76#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1) 76#define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
77#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1) 77#define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
78#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2Ghz */ 78#define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1) /* Disable turbo for 2GHz */
79#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for < 2W power consumption */ 79#define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f) /* Max turbo power for < 2W power consumption */
80#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI, 4 AP) */ 80#define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7) /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI, 4 AP) */
81#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */ 81#define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1) /* Device has RFKill support */
82#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5Ghz */ 82#define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1) /* Disable turbo for 5GHz */
83 83
84/* Newer EEPROMs are using a different offset */ 84/* Newer EEPROMs are using a different offset */
85#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \ 85#define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
@@ -120,7 +120,7 @@
120#define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) /* disable fast frames */ 120#define AR5K_EEPROM_FF_DIS(_v) (((_v) >> 2) & 0x1) /* disable fast frames */
121#define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) /* disable bursting */ 121#define AR5K_EEPROM_BURST_DIS(_v) (((_v) >> 3) & 0x1) /* disable bursting */
122#define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) /* max number of QCUs. defaults to 10 */ 122#define AR5K_EEPROM_MAX_QCU(_v) (((_v) >> 4) & 0xf) /* max number of QCUs. defaults to 10 */
123#define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) /* enable heayy clipping */ 123#define AR5K_EEPROM_HEAVY_CLIP_EN(_v) (((_v) >> 8) & 0x1) /* enable heavy clipping */
124#define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) /* key cache size. defaults to 128 */ 124#define AR5K_EEPROM_KEY_CACHE_SIZE(_v) (((_v) >> 12) & 0xf) /* key cache size. defaults to 128 */
125 125
126#define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) 126#define AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10)
@@ -223,7 +223,7 @@
223#define AR5K_EEPROM_CCK_OFDM_DELTA 15 223#define AR5K_EEPROM_CCK_OFDM_DELTA 15
224#define AR5K_EEPROM_N_IQ_CAL 2 224#define AR5K_EEPROM_N_IQ_CAL 2
225/* 5GHz/2GHz */ 225/* 5GHz/2GHz */
226enum ath5k_eeprom_freq_bands{ 226enum ath5k_eeprom_freq_bands {
227 AR5K_EEPROM_BAND_5GHZ = 0, 227 AR5K_EEPROM_BAND_5GHZ = 0,
228 AR5K_EEPROM_BAND_2GHZ = 1, 228 AR5K_EEPROM_BAND_2GHZ = 1,
229 AR5K_EEPROM_N_FREQ_BANDS, 229 AR5K_EEPROM_N_FREQ_BANDS,
@@ -270,7 +270,7 @@ enum ath5k_ctl_mode {
270 270
271/* Per channel calibration data, used for power table setup */ 271/* Per channel calibration data, used for power table setup */
272struct ath5k_chan_pcal_info_rf5111 { 272struct ath5k_chan_pcal_info_rf5111 {
273 /* Power levels in half dbm units 273 /* Power levels in half dBm units
274 * for one power curve. */ 274 * for one power curve. */
275 u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111]; 275 u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
276 /* PCDAC table steps 276 /* PCDAC table steps
diff --git a/drivers/net/wireless/ath/ath5k/initvals.c b/drivers/net/wireless/ath/ath5k/initvals.c
index e49340d18df4..5ab607f40e0e 100644
--- a/drivers/net/wireless/ath/ath5k/initvals.c
+++ b/drivers/net/wireless/ath/ath5k/initvals.c
@@ -113,8 +113,8 @@ static const struct ath5k_ini ar5210_ini[] = {
113 { AR5K_PHY(28), 0x0000000f }, 113 { AR5K_PHY(28), 0x0000000f },
114 { AR5K_PHY(29), 0x00000080 }, 114 { AR5K_PHY(29), 0x00000080 },
115 { AR5K_PHY(30), 0x00000004 }, 115 { AR5K_PHY(30), 0x00000004 },
116 { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ 116 { AR5K_PHY(31), 0x00000018 }, /* 0x987c */
117 { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ 117 { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */
118 { AR5K_PHY(65), 0x00000000 }, 118 { AR5K_PHY(65), 0x00000000 },
119 { AR5K_PHY(66), 0x00000000 }, 119 { AR5K_PHY(66), 0x00000000 },
120 { AR5K_PHY(67), 0x00800000 }, 120 { AR5K_PHY(67), 0x00800000 },
@@ -549,7 +549,7 @@ static const struct ath5k_ini ar5212_ini_common_start[] = {
549 { AR5K_DIAG_SW_5211, 0x00000000 }, 549 { AR5K_DIAG_SW_5211, 0x00000000 },
550 { AR5K_ADDAC_TEST, 0x00000000 }, 550 { AR5K_ADDAC_TEST, 0x00000000 },
551 { AR5K_DEFAULT_ANTENNA, 0x00000000 }, 551 { AR5K_DEFAULT_ANTENNA, 0x00000000 },
552 { AR5K_FRAME_CTL_QOSM, 0x000fc78f }, 552 { AR5K_FRAME_CTL_QOSM, 0x000fc78f },
553 { AR5K_XRMODE, 0x2a82301a }, 553 { AR5K_XRMODE, 0x2a82301a },
554 { AR5K_XRDELAY, 0x05dc01e0 }, 554 { AR5K_XRDELAY, 0x05dc01e0 },
555 { AR5K_XRTIMEOUT, 0x1f402710 }, 555 { AR5K_XRTIMEOUT, 0x1f402710 },
@@ -760,9 +760,9 @@ static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
760 760
761static const struct ath5k_ini rf5111_ini_common_end[] = { 761static const struct ath5k_ini rf5111_ini_common_end[] = {
762 { AR5K_DCU_FP, 0x00000000 }, 762 { AR5K_DCU_FP, 0x00000000 },
763 { AR5K_PHY_AGC, 0x00000000 }, 763 { AR5K_PHY_AGC, 0x00000000 },
764 { AR5K_PHY_ADC_CTL, 0x00022ffe }, 764 { AR5K_PHY_ADC_CTL, 0x00022ffe },
765 { 0x983c, 0x00020100 }, 765 { 0x983c, 0x00020100 },
766 { AR5K_PHY_GAIN_OFFSET, 0x1284613c }, 766 { AR5K_PHY_GAIN_OFFSET, 0x1284613c },
767 { AR5K_PHY_PAPD_PROBE, 0x00004883 }, 767 { AR5K_PHY_PAPD_PROBE, 0x00004883 },
768 { 0x9940, 0x00000004 }, 768 { 0x9940, 0x00000004 },
@@ -1409,7 +1409,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
1409 * Write initial register settings 1409 * Write initial register settings
1410 */ 1410 */
1411 1411
1412 /* For AR5212 and combatible */ 1412 /* For AR5212 and compatible */
1413 if (ah->ah_version == AR5K_AR5212) { 1413 if (ah->ah_version == AR5K_AR5212) {
1414 1414
1415 /* First set of mode-specific settings */ 1415 /* First set of mode-specific settings */
@@ -1542,7 +1542,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
1542 1542
1543 /* AR5K_MODE_11B */ 1543 /* AR5K_MODE_11B */
1544 if (mode > 2) { 1544 if (mode > 2) {
1545 ATH5K_ERR(ah->ah_sc, 1545 ATH5K_ERR(ah,
1546 "unsupported channel mode: %d\n", mode); 1546 "unsupported channel mode: %d\n", mode);
1547 return -EINVAL; 1547 return -EINVAL;
1548 } 1548 }
diff --git a/drivers/net/wireless/ath/ath5k/led.c b/drivers/net/wireless/ath/ath5k/led.c
index 576edf2965dc..8c17a00f7dad 100644
--- a/drivers/net/wireless/ath/ath5k/led.c
+++ b/drivers/net/wireless/ath/ath5k/led.c
@@ -43,16 +43,16 @@
43#include "ath5k.h" 43#include "ath5k.h"
44#include "base.h" 44#include "base.h"
45 45
46#define ATH_SDEVICE(subv,subd) \ 46#define ATH_SDEVICE(subv, subd) \
47 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 47 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
48 .subvendor = (subv), .subdevice = (subd) 48 .subvendor = (subv), .subdevice = (subd)
49 49
50#define ATH_LED(pin,polarity) .driver_data = (((pin) << 8) | (polarity)) 50#define ATH_LED(pin, polarity) .driver_data = (((pin) << 8) | (polarity))
51#define ATH_PIN(data) ((data) >> 8) 51#define ATH_PIN(data) ((data) >> 8)
52#define ATH_POLARITY(data) ((data) & 0xff) 52#define ATH_POLARITY(data) ((data) & 0xff)
53 53
54/* Devices we match on for LED config info (typically laptops) */ 54/* Devices we match on for LED config info (typically laptops) */
55static const struct pci_device_id ath5k_led_devices[] = { 55static DEFINE_PCI_DEVICE_TABLE(ath5k_led_devices) = {
56 /* AR5211 */ 56 /* AR5211 */
57 { PCI_VDEVICE(ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211), ATH_LED(0, 0) }, 57 { PCI_VDEVICE(ATHEROS, PCI_DEVICE_ID_ATHEROS_AR5211), ATH_LED(0, 0) },
58 /* HP Compaq nc6xx, nc4000, nx6000 */ 58 /* HP Compaq nc6xx, nc4000, nx6000 */
@@ -86,26 +86,26 @@ static const struct pci_device_id ath5k_led_devices[] = {
86 { } 86 { }
87}; 87};
88 88
89void ath5k_led_enable(struct ath5k_softc *sc) 89void ath5k_led_enable(struct ath5k_hw *ah)
90{ 90{
91 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) { 91 if (test_bit(ATH_STAT_LEDSOFT, ah->status)) {
92 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin); 92 ath5k_hw_set_gpio_output(ah, ah->led_pin);
93 ath5k_led_off(sc); 93 ath5k_led_off(ah);
94 } 94 }
95} 95}
96 96
97static void ath5k_led_on(struct ath5k_softc *sc) 97static void ath5k_led_on(struct ath5k_hw *ah)
98{ 98{
99 if (!test_bit(ATH_STAT_LEDSOFT, sc->status)) 99 if (!test_bit(ATH_STAT_LEDSOFT, ah->status))
100 return; 100 return;
101 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on); 101 ath5k_hw_set_gpio(ah, ah->led_pin, ah->led_on);
102} 102}
103 103
104void ath5k_led_off(struct ath5k_softc *sc) 104void ath5k_led_off(struct ath5k_hw *ah)
105{ 105{
106 if (!test_bit(ATH_STAT_LEDSOFT, sc->status)) 106 if (!test_bit(ATH_STAT_LEDSOFT, ah->status))
107 return; 107 return;
108 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on); 108 ath5k_hw_set_gpio(ah, ah->led_pin, !ah->led_on);
109} 109}
110 110
111static void 111static void
@@ -116,27 +116,27 @@ ath5k_led_brightness_set(struct led_classdev *led_dev,
116 led_dev); 116 led_dev);
117 117
118 if (brightness == LED_OFF) 118 if (brightness == LED_OFF)
119 ath5k_led_off(led->sc); 119 ath5k_led_off(led->ah);
120 else 120 else
121 ath5k_led_on(led->sc); 121 ath5k_led_on(led->ah);
122} 122}
123 123
124static int 124static int
125ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led, 125ath5k_register_led(struct ath5k_hw *ah, struct ath5k_led *led,
126 const char *name, char *trigger) 126 const char *name, char *trigger)
127{ 127{
128 int err; 128 int err;
129 129
130 led->sc = sc; 130 led->ah = ah;
131 strncpy(led->name, name, sizeof(led->name)); 131 strncpy(led->name, name, sizeof(led->name));
132 led->led_dev.name = led->name; 132 led->led_dev.name = led->name;
133 led->led_dev.default_trigger = trigger; 133 led->led_dev.default_trigger = trigger;
134 led->led_dev.brightness_set = ath5k_led_brightness_set; 134 led->led_dev.brightness_set = ath5k_led_brightness_set;
135 135
136 err = led_classdev_register(sc->dev, &led->led_dev); 136 err = led_classdev_register(ah->dev, &led->led_dev);
137 if (err) { 137 if (err) {
138 ATH5K_WARN(sc, "could not register LED %s\n", name); 138 ATH5K_WARN(ah, "could not register LED %s\n", name);
139 led->sc = NULL; 139 led->ah = NULL;
140 } 140 }
141 return err; 141 return err;
142} 142}
@@ -144,30 +144,30 @@ ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
144static void 144static void
145ath5k_unregister_led(struct ath5k_led *led) 145ath5k_unregister_led(struct ath5k_led *led)
146{ 146{
147 if (!led->sc) 147 if (!led->ah)
148 return; 148 return;
149 led_classdev_unregister(&led->led_dev); 149 led_classdev_unregister(&led->led_dev);
150 ath5k_led_off(led->sc); 150 ath5k_led_off(led->ah);
151 led->sc = NULL; 151 led->ah = NULL;
152} 152}
153 153
154void ath5k_unregister_leds(struct ath5k_softc *sc) 154void ath5k_unregister_leds(struct ath5k_hw *ah)
155{ 155{
156 ath5k_unregister_led(&sc->rx_led); 156 ath5k_unregister_led(&ah->rx_led);
157 ath5k_unregister_led(&sc->tx_led); 157 ath5k_unregister_led(&ah->tx_led);
158} 158}
159 159
160int ath5k_init_leds(struct ath5k_softc *sc) 160int __devinit ath5k_init_leds(struct ath5k_hw *ah)
161{ 161{
162 int ret = 0; 162 int ret = 0;
163 struct ieee80211_hw *hw = sc->hw; 163 struct ieee80211_hw *hw = ah->hw;
164#ifndef CONFIG_ATHEROS_AR231X 164#ifndef CONFIG_ATHEROS_AR231X
165 struct pci_dev *pdev = sc->pdev; 165 struct pci_dev *pdev = ah->pdev;
166#endif 166#endif
167 char name[ATH5K_LED_MAX_NAME_LEN + 1]; 167 char name[ATH5K_LED_MAX_NAME_LEN + 1];
168 const struct pci_device_id *match; 168 const struct pci_device_id *match;
169 169
170 if (!sc->pdev) 170 if (!ah->pdev)
171 return 0; 171 return 0;
172 172
173#ifdef CONFIG_ATHEROS_AR231X 173#ifdef CONFIG_ATHEROS_AR231X
@@ -176,24 +176,24 @@ int ath5k_init_leds(struct ath5k_softc *sc)
176 match = pci_match_id(&ath5k_led_devices[0], pdev); 176 match = pci_match_id(&ath5k_led_devices[0], pdev);
177#endif 177#endif
178 if (match) { 178 if (match) {
179 __set_bit(ATH_STAT_LEDSOFT, sc->status); 179 __set_bit(ATH_STAT_LEDSOFT, ah->status);
180 sc->led_pin = ATH_PIN(match->driver_data); 180 ah->led_pin = ATH_PIN(match->driver_data);
181 sc->led_on = ATH_POLARITY(match->driver_data); 181 ah->led_on = ATH_POLARITY(match->driver_data);
182 } 182 }
183 183
184 if (!test_bit(ATH_STAT_LEDSOFT, sc->status)) 184 if (!test_bit(ATH_STAT_LEDSOFT, ah->status))
185 goto out; 185 goto out;
186 186
187 ath5k_led_enable(sc); 187 ath5k_led_enable(ah);
188 188
189 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy)); 189 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
190 ret = ath5k_register_led(sc, &sc->rx_led, name, 190 ret = ath5k_register_led(ah, &ah->rx_led, name,
191 ieee80211_get_rx_led_name(hw)); 191 ieee80211_get_rx_led_name(hw));
192 if (ret) 192 if (ret)
193 goto out; 193 goto out;
194 194
195 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy)); 195 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
196 ret = ath5k_register_led(sc, &sc->tx_led, name, 196 ret = ath5k_register_led(ah, &ah->tx_led, name,
197 ieee80211_get_tx_led_name(hw)); 197 ieee80211_get_tx_led_name(hw));
198out: 198out:
199 return ret; 199 return ret;
diff --git a/drivers/net/wireless/ath/ath5k/mac80211-ops.c b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
index 807bd6440169..2a715ca0c5e4 100644
--- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c
+++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
@@ -46,8 +46,6 @@
46#include "base.h" 46#include "base.h"
47#include "reg.h" 47#include "reg.h"
48 48
49extern int ath5k_modparam_nohwcrypt;
50
51/********************\ 49/********************\
52* Mac80211 functions * 50* Mac80211 functions *
53\********************/ 51\********************/
@@ -55,44 +53,30 @@ extern int ath5k_modparam_nohwcrypt;
55static void 53static void
56ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 54ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
57{ 55{
58 struct ath5k_softc *sc = hw->priv; 56 struct ath5k_hw *ah = hw->priv;
59 u16 qnum = skb_get_queue_mapping(skb); 57 u16 qnum = skb_get_queue_mapping(skb);
60 58
61 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) { 59 if (WARN_ON(qnum >= ah->ah_capabilities.cap_queues.q_tx_num)) {
62 dev_kfree_skb_any(skb); 60 dev_kfree_skb_any(skb);
63 return; 61 return;
64 } 62 }
65 63
66 ath5k_tx_queue(hw, skb, &sc->txqs[qnum]); 64 ath5k_tx_queue(hw, skb, &ah->txqs[qnum]);
67}
68
69
70static int
71ath5k_start(struct ieee80211_hw *hw)
72{
73 return ath5k_init_hw(hw->priv);
74}
75
76
77static void
78ath5k_stop(struct ieee80211_hw *hw)
79{
80 ath5k_stop_hw(hw->priv);
81} 65}
82 66
83 67
84static int 68static int
85ath5k_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 69ath5k_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
86{ 70{
87 struct ath5k_softc *sc = hw->priv; 71 struct ath5k_hw *ah = hw->priv;
88 int ret; 72 int ret;
89 struct ath5k_vif *avf = (void *)vif->drv_priv; 73 struct ath5k_vif *avf = (void *)vif->drv_priv;
90 74
91 mutex_lock(&sc->lock); 75 mutex_lock(&ah->lock);
92 76
93 if ((vif->type == NL80211_IFTYPE_AP || 77 if ((vif->type == NL80211_IFTYPE_AP ||
94 vif->type == NL80211_IFTYPE_ADHOC) 78 vif->type == NL80211_IFTYPE_ADHOC)
95 && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) { 79 && (ah->num_ap_vifs + ah->num_adhoc_vifs) >= ATH_BCBUF) {
96 ret = -ELNRNG; 80 ret = -ELNRNG;
97 goto end; 81 goto end;
98 } 82 }
@@ -102,9 +86,9 @@ ath5k_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
102 * We would need to operate the HW in ad-hoc mode to allow TSF updates 86 * We would need to operate the HW in ad-hoc mode to allow TSF updates
103 * for the IBSS, but this breaks with additional AP or STA interfaces 87 * for the IBSS, but this breaks with additional AP or STA interfaces
104 * at the moment. */ 88 * at the moment. */
105 if (sc->num_adhoc_vifs || 89 if (ah->num_adhoc_vifs ||
106 (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) { 90 (ah->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
107 ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n"); 91 ATH5K_ERR(ah, "Only one single ad-hoc interface is allowed.\n");
108 ret = -ELNRNG; 92 ret = -ELNRNG;
109 goto end; 93 goto end;
110 } 94 }
@@ -121,8 +105,8 @@ ath5k_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
121 goto end; 105 goto end;
122 } 106 }
123 107
124 sc->nvifs++; 108 ah->nvifs++;
125 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode); 109 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
126 110
127 /* Assign the vap/adhoc to a beacon xmit slot. */ 111 /* Assign the vap/adhoc to a beacon xmit slot. */
128 if ((avf->opmode == NL80211_IFTYPE_AP) || 112 if ((avf->opmode == NL80211_IFTYPE_AP) ||
@@ -130,38 +114,38 @@ ath5k_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
130 (avf->opmode == NL80211_IFTYPE_MESH_POINT)) { 114 (avf->opmode == NL80211_IFTYPE_MESH_POINT)) {
131 int slot; 115 int slot;
132 116
133 WARN_ON(list_empty(&sc->bcbuf)); 117 WARN_ON(list_empty(&ah->bcbuf));
134 avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf, 118 avf->bbuf = list_first_entry(&ah->bcbuf, struct ath5k_buf,
135 list); 119 list);
136 list_del(&avf->bbuf->list); 120 list_del(&avf->bbuf->list);
137 121
138 avf->bslot = 0; 122 avf->bslot = 0;
139 for (slot = 0; slot < ATH_BCBUF; slot++) { 123 for (slot = 0; slot < ATH_BCBUF; slot++) {
140 if (!sc->bslot[slot]) { 124 if (!ah->bslot[slot]) {
141 avf->bslot = slot; 125 avf->bslot = slot;
142 break; 126 break;
143 } 127 }
144 } 128 }
145 BUG_ON(sc->bslot[avf->bslot] != NULL); 129 BUG_ON(ah->bslot[avf->bslot] != NULL);
146 sc->bslot[avf->bslot] = vif; 130 ah->bslot[avf->bslot] = vif;
147 if (avf->opmode == NL80211_IFTYPE_AP) 131 if (avf->opmode == NL80211_IFTYPE_AP)
148 sc->num_ap_vifs++; 132 ah->num_ap_vifs++;
149 else if (avf->opmode == NL80211_IFTYPE_ADHOC) 133 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
150 sc->num_adhoc_vifs++; 134 ah->num_adhoc_vifs++;
151 } 135 }
152 136
153 /* Any MAC address is fine, all others are included through the 137 /* Any MAC address is fine, all others are included through the
154 * filter. 138 * filter.
155 */ 139 */
156 memcpy(&sc->lladdr, vif->addr, ETH_ALEN); 140 memcpy(&ah->lladdr, vif->addr, ETH_ALEN);
157 ath5k_hw_set_lladdr(sc->ah, vif->addr); 141 ath5k_hw_set_lladdr(ah, vif->addr);
158 142
159 memcpy(&avf->lladdr, vif->addr, ETH_ALEN); 143 memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
160 144
161 ath5k_update_bssid_mask_and_opmode(sc, vif); 145 ath5k_update_bssid_mask_and_opmode(ah, vif);
162 ret = 0; 146 ret = 0;
163end: 147end:
164 mutex_unlock(&sc->lock); 148 mutex_unlock(&ah->lock);
165 return ret; 149 return ret;
166} 150}
167 151
@@ -170,31 +154,31 @@ static void
170ath5k_remove_interface(struct ieee80211_hw *hw, 154ath5k_remove_interface(struct ieee80211_hw *hw,
171 struct ieee80211_vif *vif) 155 struct ieee80211_vif *vif)
172{ 156{
173 struct ath5k_softc *sc = hw->priv; 157 struct ath5k_hw *ah = hw->priv;
174 struct ath5k_vif *avf = (void *)vif->drv_priv; 158 struct ath5k_vif *avf = (void *)vif->drv_priv;
175 unsigned int i; 159 unsigned int i;
176 160
177 mutex_lock(&sc->lock); 161 mutex_lock(&ah->lock);
178 sc->nvifs--; 162 ah->nvifs--;
179 163
180 if (avf->bbuf) { 164 if (avf->bbuf) {
181 ath5k_txbuf_free_skb(sc, avf->bbuf); 165 ath5k_txbuf_free_skb(ah, avf->bbuf);
182 list_add_tail(&avf->bbuf->list, &sc->bcbuf); 166 list_add_tail(&avf->bbuf->list, &ah->bcbuf);
183 for (i = 0; i < ATH_BCBUF; i++) { 167 for (i = 0; i < ATH_BCBUF; i++) {
184 if (sc->bslot[i] == vif) { 168 if (ah->bslot[i] == vif) {
185 sc->bslot[i] = NULL; 169 ah->bslot[i] = NULL;
186 break; 170 break;
187 } 171 }
188 } 172 }
189 avf->bbuf = NULL; 173 avf->bbuf = NULL;
190 } 174 }
191 if (avf->opmode == NL80211_IFTYPE_AP) 175 if (avf->opmode == NL80211_IFTYPE_AP)
192 sc->num_ap_vifs--; 176 ah->num_ap_vifs--;
193 else if (avf->opmode == NL80211_IFTYPE_ADHOC) 177 else if (avf->opmode == NL80211_IFTYPE_ADHOC)
194 sc->num_adhoc_vifs--; 178 ah->num_adhoc_vifs--;
195 179
196 ath5k_update_bssid_mask_and_opmode(sc, NULL); 180 ath5k_update_bssid_mask_and_opmode(ah, NULL);
197 mutex_unlock(&sc->lock); 181 mutex_unlock(&ah->lock);
198} 182}
199 183
200 184
@@ -204,23 +188,22 @@ ath5k_remove_interface(struct ieee80211_hw *hw,
204static int 188static int
205ath5k_config(struct ieee80211_hw *hw, u32 changed) 189ath5k_config(struct ieee80211_hw *hw, u32 changed)
206{ 190{
207 struct ath5k_softc *sc = hw->priv; 191 struct ath5k_hw *ah = hw->priv;
208 struct ath5k_hw *ah = sc->ah;
209 struct ieee80211_conf *conf = &hw->conf; 192 struct ieee80211_conf *conf = &hw->conf;
210 int ret = 0; 193 int ret = 0;
211 int i; 194 int i;
212 195
213 mutex_lock(&sc->lock); 196 mutex_lock(&ah->lock);
214 197
215 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 198 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
216 ret = ath5k_chan_set(sc, conf->channel); 199 ret = ath5k_chan_set(ah, conf->channel);
217 if (ret < 0) 200 if (ret < 0)
218 goto unlock; 201 goto unlock;
219 } 202 }
220 203
221 if ((changed & IEEE80211_CONF_CHANGE_POWER) && 204 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
222 (sc->power_level != conf->power_level)) { 205 (ah->power_level != conf->power_level)) {
223 sc->power_level = conf->power_level; 206 ah->power_level = conf->power_level;
224 207
225 /* Half dB steps */ 208 /* Half dB steps */
226 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2)); 209 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
@@ -254,7 +237,7 @@ ath5k_config(struct ieee80211_hw *hw, u32 changed)
254 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); 237 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
255 238
256unlock: 239unlock:
257 mutex_unlock(&sc->lock); 240 mutex_unlock(&ah->lock);
258 return ret; 241 return ret;
259} 242}
260 243
@@ -264,12 +247,11 @@ ath5k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
264 struct ieee80211_bss_conf *bss_conf, u32 changes) 247 struct ieee80211_bss_conf *bss_conf, u32 changes)
265{ 248{
266 struct ath5k_vif *avf = (void *)vif->drv_priv; 249 struct ath5k_vif *avf = (void *)vif->drv_priv;
267 struct ath5k_softc *sc = hw->priv; 250 struct ath5k_hw *ah = hw->priv;
268 struct ath5k_hw *ah = sc->ah;
269 struct ath_common *common = ath5k_hw_common(ah); 251 struct ath_common *common = ath5k_hw_common(ah);
270 unsigned long flags; 252 unsigned long flags;
271 253
272 mutex_lock(&sc->lock); 254 mutex_lock(&ah->lock);
273 255
274 if (changes & BSS_CHANGED_BSSID) { 256 if (changes & BSS_CHANGED_BSSID) {
275 /* Cache for later use during resets */ 257 /* Cache for later use during resets */
@@ -280,7 +262,7 @@ ath5k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
280 } 262 }
281 263
282 if (changes & BSS_CHANGED_BEACON_INT) 264 if (changes & BSS_CHANGED_BEACON_INT)
283 sc->bintval = bss_conf->beacon_int; 265 ah->bintval = bss_conf->beacon_int;
284 266
285 if (changes & BSS_CHANGED_ERP_SLOT) { 267 if (changes & BSS_CHANGED_ERP_SLOT) {
286 int slot_time; 268 int slot_time;
@@ -294,16 +276,16 @@ ath5k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
294 if (changes & BSS_CHANGED_ASSOC) { 276 if (changes & BSS_CHANGED_ASSOC) {
295 avf->assoc = bss_conf->assoc; 277 avf->assoc = bss_conf->assoc;
296 if (bss_conf->assoc) 278 if (bss_conf->assoc)
297 sc->assoc = bss_conf->assoc; 279 ah->assoc = bss_conf->assoc;
298 else 280 else
299 sc->assoc = ath_any_vif_assoc(sc); 281 ah->assoc = ath5k_any_vif_assoc(ah);
300 282
301 if (sc->opmode == NL80211_IFTYPE_STATION) 283 if (ah->opmode == NL80211_IFTYPE_STATION)
302 set_beacon_filter(hw, sc->assoc); 284 ath5k_set_beacon_filter(hw, ah->assoc);
303 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 285 ath5k_hw_set_ledstate(ah, ah->assoc ?
304 AR5K_LED_ASSOC : AR5K_LED_INIT); 286 AR5K_LED_ASSOC : AR5K_LED_INIT);
305 if (bss_conf->assoc) { 287 if (bss_conf->assoc) {
306 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, 288 ATH5K_DBG(ah, ATH5K_DEBUG_ANY,
307 "Bss Info ASSOC %d, bssid: %pM\n", 289 "Bss Info ASSOC %d, bssid: %pM\n",
308 bss_conf->aid, common->curbssid); 290 bss_conf->aid, common->curbssid);
309 common->curaid = bss_conf->aid; 291 common->curaid = bss_conf->aid;
@@ -313,19 +295,19 @@ ath5k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
313 } 295 }
314 296
315 if (changes & BSS_CHANGED_BEACON) { 297 if (changes & BSS_CHANGED_BEACON) {
316 spin_lock_irqsave(&sc->block, flags); 298 spin_lock_irqsave(&ah->block, flags);
317 ath5k_beacon_update(hw, vif); 299 ath5k_beacon_update(hw, vif);
318 spin_unlock_irqrestore(&sc->block, flags); 300 spin_unlock_irqrestore(&ah->block, flags);
319 } 301 }
320 302
321 if (changes & BSS_CHANGED_BEACON_ENABLED) 303 if (changes & BSS_CHANGED_BEACON_ENABLED)
322 sc->enable_beacon = bss_conf->enable_beacon; 304 ah->enable_beacon = bss_conf->enable_beacon;
323 305
324 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED | 306 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
325 BSS_CHANGED_BEACON_INT)) 307 BSS_CHANGED_BEACON_INT))
326 ath5k_beacon_config(sc); 308 ath5k_beacon_config(ah);
327 309
328 mutex_unlock(&sc->lock); 310 mutex_unlock(&ah->lock);
329} 311}
330 312
331 313
@@ -350,7 +332,7 @@ ath5k_prepare_multicast(struct ieee80211_hw *hw,
350 mfilt[pos / 32] |= (1 << (pos % 32)); 332 mfilt[pos / 32] |= (1 << (pos % 32));
351 /* XXX: we might be able to just do this instead, 333 /* XXX: we might be able to just do this instead,
352 * but not sure, needs testing, if we do use this we'd 334 * but not sure, needs testing, if we do use this we'd
353 * neet to inform below to not reset the mcast */ 335 * need to inform below not to reset the mcast */
354 /* ath5k_hw_set_mcast_filterindex(ah, 336 /* ath5k_hw_set_mcast_filterindex(ah,
355 * ha->addr[5]); */ 337 * ha->addr[5]); */
356 } 338 }
@@ -386,12 +368,11 @@ ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
386 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ 368 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
387 FIF_BCN_PRBRESP_PROMISC) 369 FIF_BCN_PRBRESP_PROMISC)
388 370
389 struct ath5k_softc *sc = hw->priv; 371 struct ath5k_hw *ah = hw->priv;
390 struct ath5k_hw *ah = sc->ah;
391 u32 mfilt[2], rfilt; 372 u32 mfilt[2], rfilt;
392 struct ath5k_vif_iter_data iter_data; /* to count STA interfaces */ 373 struct ath5k_vif_iter_data iter_data; /* to count STA interfaces */
393 374
394 mutex_lock(&sc->lock); 375 mutex_lock(&ah->lock);
395 376
396 mfilt[0] = multicast; 377 mfilt[0] = multicast;
397 mfilt[1] = multicast >> 32; 378 mfilt[1] = multicast >> 32;
@@ -409,12 +390,12 @@ ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
409 390
410 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) { 391 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
411 if (*new_flags & FIF_PROMISC_IN_BSS) 392 if (*new_flags & FIF_PROMISC_IN_BSS)
412 __set_bit(ATH_STAT_PROMISC, sc->status); 393 __set_bit(ATH_STAT_PROMISC, ah->status);
413 else 394 else
414 __clear_bit(ATH_STAT_PROMISC, sc->status); 395 __clear_bit(ATH_STAT_PROMISC, ah->status);
415 } 396 }
416 397
417 if (test_bit(ATH_STAT_PROMISC, sc->status)) 398 if (test_bit(ATH_STAT_PROMISC, ah->status))
418 rfilt |= AR5K_RX_FILTER_PROM; 399 rfilt |= AR5K_RX_FILTER_PROM;
419 400
420 /* Note, AR5K_RX_FILTER_MCAST is already enabled */ 401 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
@@ -429,7 +410,7 @@ ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
429 410
430 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons 411 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
431 * and probes for any BSSID */ 412 * and probes for any BSSID */
432 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1)) 413 if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (ah->nvifs > 1))
433 rfilt |= AR5K_RX_FILTER_BEACON; 414 rfilt |= AR5K_RX_FILTER_BEACON;
434 415
435 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not 416 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
@@ -444,7 +425,7 @@ ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
444 425
445 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */ 426 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
446 427
447 switch (sc->opmode) { 428 switch (ah->opmode) {
448 case NL80211_IFTYPE_MESH_POINT: 429 case NL80211_IFTYPE_MESH_POINT:
449 rfilt |= AR5K_RX_FILTER_CONTROL | 430 rfilt |= AR5K_RX_FILTER_CONTROL |
450 AR5K_RX_FILTER_BEACON | 431 AR5K_RX_FILTER_BEACON |
@@ -457,7 +438,7 @@ ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
457 AR5K_RX_FILTER_BEACON; 438 AR5K_RX_FILTER_BEACON;
458 break; 439 break;
459 case NL80211_IFTYPE_STATION: 440 case NL80211_IFTYPE_STATION:
460 if (sc->assoc) 441 if (ah->assoc)
461 rfilt |= AR5K_RX_FILTER_BEACON; 442 rfilt |= AR5K_RX_FILTER_BEACON;
462 default: 443 default:
463 break; 444 break;
@@ -466,14 +447,14 @@ ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
466 iter_data.hw_macaddr = NULL; 447 iter_data.hw_macaddr = NULL;
467 iter_data.n_stas = 0; 448 iter_data.n_stas = 0;
468 iter_data.need_set_hw_addr = false; 449 iter_data.need_set_hw_addr = false;
469 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 450 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
470 &iter_data); 451 &iter_data);
471 452
472 /* Set up RX Filter */ 453 /* Set up RX Filter */
473 if (iter_data.n_stas > 1) { 454 if (iter_data.n_stas > 1) {
474 /* If you have multiple STA interfaces connected to 455 /* If you have multiple STA interfaces connected to
475 * different APs, ARPs are not received (most of the time?) 456 * different APs, ARPs are not received (most of the time?)
476 * Enabling PROMISC appears to fix that probem. 457 * Enabling PROMISC appears to fix that problem.
477 */ 458 */
478 rfilt |= AR5K_RX_FILTER_PROM; 459 rfilt |= AR5K_RX_FILTER_PROM;
479 } 460 }
@@ -485,9 +466,9 @@ ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
485 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); 466 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
486 /* Set the cached hw filter flags, this will later actually 467 /* Set the cached hw filter flags, this will later actually
487 * be set in HW */ 468 * be set in HW */
488 sc->filter_flags = rfilt; 469 ah->filter_flags = rfilt;
489 470
490 mutex_unlock(&sc->lock); 471 mutex_unlock(&ah->lock);
491} 472}
492 473
493 474
@@ -496,8 +477,7 @@ ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
496 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 477 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
497 struct ieee80211_key_conf *key) 478 struct ieee80211_key_conf *key)
498{ 479{
499 struct ath5k_softc *sc = hw->priv; 480 struct ath5k_hw *ah = hw->priv;
500 struct ath5k_hw *ah = sc->ah;
501 struct ath_common *common = ath5k_hw_common(ah); 481 struct ath_common *common = ath5k_hw_common(ah);
502 int ret = 0; 482 int ret = 0;
503 483
@@ -518,7 +498,7 @@ ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
518 return -EINVAL; 498 return -EINVAL;
519 } 499 }
520 500
521 mutex_lock(&sc->lock); 501 mutex_lock(&ah->lock);
522 502
523 switch (cmd) { 503 switch (cmd) {
524 case SET_KEY: 504 case SET_KEY:
@@ -542,7 +522,7 @@ ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
542 } 522 }
543 523
544 mmiowb(); 524 mmiowb();
545 mutex_unlock(&sc->lock); 525 mutex_unlock(&ah->lock);
546 return ret; 526 return ret;
547} 527}
548 528
@@ -550,17 +530,17 @@ ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
550static void 530static void
551ath5k_sw_scan_start(struct ieee80211_hw *hw) 531ath5k_sw_scan_start(struct ieee80211_hw *hw)
552{ 532{
553 struct ath5k_softc *sc = hw->priv; 533 struct ath5k_hw *ah = hw->priv;
554 if (!sc->assoc) 534 if (!ah->assoc)
555 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN); 535 ath5k_hw_set_ledstate(ah, AR5K_LED_SCAN);
556} 536}
557 537
558 538
559static void 539static void
560ath5k_sw_scan_complete(struct ieee80211_hw *hw) 540ath5k_sw_scan_complete(struct ieee80211_hw *hw)
561{ 541{
562 struct ath5k_softc *sc = hw->priv; 542 struct ath5k_hw *ah = hw->priv;
563 ath5k_hw_set_ledstate(sc->ah, sc->assoc ? 543 ath5k_hw_set_ledstate(ah, ah->assoc ?
564 AR5K_LED_ASSOC : AR5K_LED_INIT); 544 AR5K_LED_ASSOC : AR5K_LED_INIT);
565} 545}
566 546
@@ -569,15 +549,15 @@ static int
569ath5k_get_stats(struct ieee80211_hw *hw, 549ath5k_get_stats(struct ieee80211_hw *hw,
570 struct ieee80211_low_level_stats *stats) 550 struct ieee80211_low_level_stats *stats)
571{ 551{
572 struct ath5k_softc *sc = hw->priv; 552 struct ath5k_hw *ah = hw->priv;
573 553
574 /* Force update */ 554 /* Force update */
575 ath5k_hw_update_mib_counters(sc->ah); 555 ath5k_hw_update_mib_counters(ah);
576 556
577 stats->dot11ACKFailureCount = sc->stats.ack_fail; 557 stats->dot11ACKFailureCount = ah->stats.ack_fail;
578 stats->dot11RTSFailureCount = sc->stats.rts_fail; 558 stats->dot11RTSFailureCount = ah->stats.rts_fail;
579 stats->dot11RTSSuccessCount = sc->stats.rts_ok; 559 stats->dot11RTSSuccessCount = ah->stats.rts_ok;
580 stats->dot11FCSErrorCount = sc->stats.fcs_error; 560 stats->dot11FCSErrorCount = ah->stats.fcs_error;
581 561
582 return 0; 562 return 0;
583} 563}
@@ -587,15 +567,14 @@ static int
587ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue, 567ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
588 const struct ieee80211_tx_queue_params *params) 568 const struct ieee80211_tx_queue_params *params)
589{ 569{
590 struct ath5k_softc *sc = hw->priv; 570 struct ath5k_hw *ah = hw->priv;
591 struct ath5k_hw *ah = sc->ah;
592 struct ath5k_txq_info qi; 571 struct ath5k_txq_info qi;
593 int ret = 0; 572 int ret = 0;
594 573
595 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num) 574 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
596 return 0; 575 return 0;
597 576
598 mutex_lock(&sc->lock); 577 mutex_lock(&ah->lock);
599 578
600 ath5k_hw_get_tx_queueprops(ah, queue, &qi); 579 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
601 580
@@ -604,20 +583,20 @@ ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
604 qi.tqi_cw_max = params->cw_max; 583 qi.tqi_cw_max = params->cw_max;
605 qi.tqi_burst_time = params->txop; 584 qi.tqi_burst_time = params->txop;
606 585
607 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, 586 ATH5K_DBG(ah, ATH5K_DEBUG_ANY,
608 "Configure tx [queue %d], " 587 "Configure tx [queue %d], "
609 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 588 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
610 queue, params->aifs, params->cw_min, 589 queue, params->aifs, params->cw_min,
611 params->cw_max, params->txop); 590 params->cw_max, params->txop);
612 591
613 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) { 592 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
614 ATH5K_ERR(sc, 593 ATH5K_ERR(ah,
615 "Unable to update hardware queue %u!\n", queue); 594 "Unable to update hardware queue %u!\n", queue);
616 ret = -EIO; 595 ret = -EIO;
617 } else 596 } else
618 ath5k_hw_reset_tx_queue(ah, queue); 597 ath5k_hw_reset_tx_queue(ah, queue);
619 598
620 mutex_unlock(&sc->lock); 599 mutex_unlock(&ah->lock);
621 600
622 return ret; 601 return ret;
623} 602}
@@ -626,43 +605,43 @@ ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
626static u64 605static u64
627ath5k_get_tsf(struct ieee80211_hw *hw) 606ath5k_get_tsf(struct ieee80211_hw *hw)
628{ 607{
629 struct ath5k_softc *sc = hw->priv; 608 struct ath5k_hw *ah = hw->priv;
630 609
631 return ath5k_hw_get_tsf64(sc->ah); 610 return ath5k_hw_get_tsf64(ah);
632} 611}
633 612
634 613
635static void 614static void
636ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf) 615ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
637{ 616{
638 struct ath5k_softc *sc = hw->priv; 617 struct ath5k_hw *ah = hw->priv;
639 618
640 ath5k_hw_set_tsf64(sc->ah, tsf); 619 ath5k_hw_set_tsf64(ah, tsf);
641} 620}
642 621
643 622
644static void 623static void
645ath5k_reset_tsf(struct ieee80211_hw *hw) 624ath5k_reset_tsf(struct ieee80211_hw *hw)
646{ 625{
647 struct ath5k_softc *sc = hw->priv; 626 struct ath5k_hw *ah = hw->priv;
648 627
649 /* 628 /*
650 * in IBSS mode we need to update the beacon timers too. 629 * in IBSS mode we need to update the beacon timers too.
651 * this will also reset the TSF if we call it with 0 630 * this will also reset the TSF if we call it with 0
652 */ 631 */
653 if (sc->opmode == NL80211_IFTYPE_ADHOC) 632 if (ah->opmode == NL80211_IFTYPE_ADHOC)
654 ath5k_beacon_update_timers(sc, 0); 633 ath5k_beacon_update_timers(ah, 0);
655 else 634 else
656 ath5k_hw_reset_tsf(sc->ah); 635 ath5k_hw_reset_tsf(ah);
657} 636}
658 637
659 638
660static int 639static int
661ath5k_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey) 640ath5k_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey)
662{ 641{
663 struct ath5k_softc *sc = hw->priv; 642 struct ath5k_hw *ah = hw->priv;
664 struct ieee80211_conf *conf = &hw->conf; 643 struct ieee80211_conf *conf = &hw->conf;
665 struct ath_common *common = ath5k_hw_common(sc->ah); 644 struct ath_common *common = ath5k_hw_common(ah);
666 struct ath_cycle_counters *cc = &common->cc_survey; 645 struct ath_cycle_counters *cc = &common->cc_survey;
667 unsigned int div = common->clockrate * 1000; 646 unsigned int div = common->clockrate * 1000;
668 647
@@ -672,18 +651,18 @@ ath5k_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey)
672 spin_lock_bh(&common->cc_lock); 651 spin_lock_bh(&common->cc_lock);
673 ath_hw_cycle_counters_update(common); 652 ath_hw_cycle_counters_update(common);
674 if (cc->cycles > 0) { 653 if (cc->cycles > 0) {
675 sc->survey.channel_time += cc->cycles / div; 654 ah->survey.channel_time += cc->cycles / div;
676 sc->survey.channel_time_busy += cc->rx_busy / div; 655 ah->survey.channel_time_busy += cc->rx_busy / div;
677 sc->survey.channel_time_rx += cc->rx_frame / div; 656 ah->survey.channel_time_rx += cc->rx_frame / div;
678 sc->survey.channel_time_tx += cc->tx_frame / div; 657 ah->survey.channel_time_tx += cc->tx_frame / div;
679 } 658 }
680 memset(cc, 0, sizeof(*cc)); 659 memset(cc, 0, sizeof(*cc));
681 spin_unlock_bh(&common->cc_lock); 660 spin_unlock_bh(&common->cc_lock);
682 661
683 memcpy(survey, &sc->survey, sizeof(*survey)); 662 memcpy(survey, &ah->survey, sizeof(*survey));
684 663
685 survey->channel = conf->channel; 664 survey->channel = conf->channel;
686 survey->noise = sc->ah->ah_noise_floor; 665 survey->noise = ah->ah_noise_floor;
687 survey->filled = SURVEY_INFO_NOISE_DBM | 666 survey->filled = SURVEY_INFO_NOISE_DBM |
688 SURVEY_INFO_CHANNEL_TIME | 667 SURVEY_INFO_CHANNEL_TIME |
689 SURVEY_INFO_CHANNEL_TIME_BUSY | 668 SURVEY_INFO_CHANNEL_TIME_BUSY |
@@ -707,25 +686,25 @@ ath5k_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey)
707static void 686static void
708ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) 687ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
709{ 688{
710 struct ath5k_softc *sc = hw->priv; 689 struct ath5k_hw *ah = hw->priv;
711 690
712 mutex_lock(&sc->lock); 691 mutex_lock(&ah->lock);
713 ath5k_hw_set_coverage_class(sc->ah, coverage_class); 692 ath5k_hw_set_coverage_class(ah, coverage_class);
714 mutex_unlock(&sc->lock); 693 mutex_unlock(&ah->lock);
715} 694}
716 695
717 696
718static int 697static int
719ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) 698ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
720{ 699{
721 struct ath5k_softc *sc = hw->priv; 700 struct ath5k_hw *ah = hw->priv;
722 701
723 if (tx_ant == 1 && rx_ant == 1) 702 if (tx_ant == 1 && rx_ant == 1)
724 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A); 703 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_FIXED_A);
725 else if (tx_ant == 2 && rx_ant == 2) 704 else if (tx_ant == 2 && rx_ant == 2)
726 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B); 705 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_FIXED_B);
727 else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3) 706 else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
728 ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT); 707 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
729 else 708 else
730 return -EINVAL; 709 return -EINVAL;
731 return 0; 710 return 0;
@@ -735,9 +714,9 @@ ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
735static int 714static int
736ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) 715ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
737{ 716{
738 struct ath5k_softc *sc = hw->priv; 717 struct ath5k_hw *ah = hw->priv;
739 718
740 switch (sc->ah->ah_ant_mode) { 719 switch (ah->ah_ant_mode) {
741 case AR5K_ANTMODE_FIXED_A: 720 case AR5K_ANTMODE_FIXED_A:
742 *tx_ant = 1; *rx_ant = 1; break; 721 *tx_ant = 1; *rx_ant = 1; break;
743 case AR5K_ANTMODE_FIXED_B: 722 case AR5K_ANTMODE_FIXED_B:
@@ -752,9 +731,9 @@ ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
752static void ath5k_get_ringparam(struct ieee80211_hw *hw, 731static void ath5k_get_ringparam(struct ieee80211_hw *hw,
753 u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max) 732 u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max)
754{ 733{
755 struct ath5k_softc *sc = hw->priv; 734 struct ath5k_hw *ah = hw->priv;
756 735
757 *tx = sc->txqs[AR5K_TX_QUEUE_ID_DATA_MIN].txq_max; 736 *tx = ah->txqs[AR5K_TX_QUEUE_ID_DATA_MIN].txq_max;
758 737
759 *tx_max = ATH5K_TXQ_LEN_MAX; 738 *tx_max = ATH5K_TXQ_LEN_MAX;
760 *rx = *rx_max = ATH_RXBUF; 739 *rx = *rx_max = ATH_RXBUF;
@@ -763,7 +742,7 @@ static void ath5k_get_ringparam(struct ieee80211_hw *hw,
763 742
764static int ath5k_set_ringparam(struct ieee80211_hw *hw, u32 tx, u32 rx) 743static int ath5k_set_ringparam(struct ieee80211_hw *hw, u32 tx, u32 rx)
765{ 744{
766 struct ath5k_softc *sc = hw->priv; 745 struct ath5k_hw *ah = hw->priv;
767 u16 qnum; 746 u16 qnum;
768 747
769 /* only support setting tx ring size for now */ 748 /* only support setting tx ring size for now */
@@ -774,16 +753,16 @@ static int ath5k_set_ringparam(struct ieee80211_hw *hw, u32 tx, u32 rx)
774 if (!tx || tx > ATH5K_TXQ_LEN_MAX) 753 if (!tx || tx > ATH5K_TXQ_LEN_MAX)
775 return -EINVAL; 754 return -EINVAL;
776 755
777 for (qnum = 0; qnum < ARRAY_SIZE(sc->txqs); qnum++) { 756 for (qnum = 0; qnum < ARRAY_SIZE(ah->txqs); qnum++) {
778 if (!sc->txqs[qnum].setup) 757 if (!ah->txqs[qnum].setup)
779 continue; 758 continue;
780 if (sc->txqs[qnum].qnum < AR5K_TX_QUEUE_ID_DATA_MIN || 759 if (ah->txqs[qnum].qnum < AR5K_TX_QUEUE_ID_DATA_MIN ||
781 sc->txqs[qnum].qnum > AR5K_TX_QUEUE_ID_DATA_MAX) 760 ah->txqs[qnum].qnum > AR5K_TX_QUEUE_ID_DATA_MAX)
782 continue; 761 continue;
783 762
784 sc->txqs[qnum].txq_max = tx; 763 ah->txqs[qnum].txq_max = tx;
785 if (sc->txqs[qnum].txq_len >= sc->txqs[qnum].txq_max) 764 if (ah->txqs[qnum].txq_len >= ah->txqs[qnum].txq_max)
786 ieee80211_stop_queue(hw, sc->txqs[qnum].qnum); 765 ieee80211_stop_queue(hw, ah->txqs[qnum].qnum);
787 } 766 }
788 767
789 return 0; 768 return 0;
diff --git a/drivers/net/wireless/ath/ath5k/pci.c b/drivers/net/wireless/ath/ath5k/pci.c
index 296c316a8341..eaf79b49341e 100644
--- a/drivers/net/wireless/ath/ath5k/pci.c
+++ b/drivers/net/wireless/ath/ath5k/pci.c
@@ -34,12 +34,12 @@ static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
34 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ 34 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
35 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ 35 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
36 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ 36 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
37 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ 37 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 compatible */
38 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ 38 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 compatible */
39 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ 39 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 compatible */
40 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ 40 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 compatible */
41 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ 41 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 compatible */
42 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ 42 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 compatible */
43 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ 43 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
44 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ 44 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
45 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ 45 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
@@ -51,10 +51,10 @@ MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
51/* return bus cachesize in 4B word units */ 51/* return bus cachesize in 4B word units */
52static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) 52static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
53{ 53{
54 struct ath5k_softc *sc = (struct ath5k_softc *) common->priv; 54 struct ath5k_hw *ah = (struct ath5k_hw *) common->priv;
55 u8 u8tmp; 55 u8 u8tmp;
56 56
57 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp); 57 pci_read_config_byte(ah->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
58 *csz = (int)u8tmp; 58 *csz = (int)u8tmp;
59 59
60 /* 60 /*
@@ -156,7 +156,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
156 const struct pci_device_id *id) 156 const struct pci_device_id *id)
157{ 157{
158 void __iomem *mem; 158 void __iomem *mem;
159 struct ath5k_softc *sc; 159 struct ath5k_hw *ah;
160 struct ieee80211_hw *hw; 160 struct ieee80211_hw *hw;
161 int ret; 161 int ret;
162 u8 csz; 162 u8 csz;
@@ -234,7 +234,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
234 234
235 mem = pci_iomap(pdev, 0, 0); 235 mem = pci_iomap(pdev, 0, 0);
236 if (!mem) { 236 if (!mem) {
237 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; 237 dev_err(&pdev->dev, "cannot remap PCI memory region\n");
238 ret = -EIO; 238 ret = -EIO;
239 goto err_reg; 239 goto err_reg;
240 } 240 }
@@ -243,7 +243,7 @@ ath5k_pci_probe(struct pci_dev *pdev,
243 * Allocate hw (mac80211 main struct) 243 * Allocate hw (mac80211 main struct)
244 * and hw->priv (driver private data) 244 * and hw->priv (driver private data)
245 */ 245 */
246 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); 246 hw = ieee80211_alloc_hw(sizeof(*ah), &ath5k_hw_ops);
247 if (hw == NULL) { 247 if (hw == NULL) {
248 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); 248 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
249 ret = -ENOMEM; 249 ret = -ENOMEM;
@@ -252,16 +252,16 @@ ath5k_pci_probe(struct pci_dev *pdev,
252 252
253 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); 253 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
254 254
255 sc = hw->priv; 255 ah = hw->priv;
256 sc->hw = hw; 256 ah->hw = hw;
257 sc->pdev = pdev; 257 ah->pdev = pdev;
258 sc->dev = &pdev->dev; 258 ah->dev = &pdev->dev;
259 sc->irq = pdev->irq; 259 ah->irq = pdev->irq;
260 sc->devid = id->device; 260 ah->devid = id->device;
261 sc->iobase = mem; /* So we can unmap it on detach */ 261 ah->iobase = mem; /* So we can unmap it on detach */
262 262
263 /* Initialize */ 263 /* Initialize */
264 ret = ath5k_init_softc(sc, &ath_pci_bus_ops); 264 ret = ath5k_init_softc(ah, &ath_pci_bus_ops);
265 if (ret) 265 if (ret)
266 goto err_free; 266 goto err_free;
267 267
@@ -285,10 +285,10 @@ static void __devexit
285ath5k_pci_remove(struct pci_dev *pdev) 285ath5k_pci_remove(struct pci_dev *pdev)
286{ 286{
287 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 287 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
288 struct ath5k_softc *sc = hw->priv; 288 struct ath5k_hw *ah = hw->priv;
289 289
290 ath5k_deinit_softc(sc); 290 ath5k_deinit_softc(ah);
291 pci_iounmap(pdev, sc->iobase); 291 pci_iounmap(pdev, ah->iobase);
292 pci_release_region(pdev, 0); 292 pci_release_region(pdev, 0);
293 pci_disable_device(pdev); 293 pci_disable_device(pdev);
294 ieee80211_free_hw(hw); 294 ieee80211_free_hw(hw);
@@ -297,16 +297,19 @@ ath5k_pci_remove(struct pci_dev *pdev)
297#ifdef CONFIG_PM_SLEEP 297#ifdef CONFIG_PM_SLEEP
298static int ath5k_pci_suspend(struct device *dev) 298static int ath5k_pci_suspend(struct device *dev)
299{ 299{
300 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev)); 300 struct pci_dev *pdev = to_pci_dev(dev);
301 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
302 struct ath5k_hw *ah = hw->priv;
301 303
302 ath5k_led_off(sc); 304 ath5k_led_off(ah);
303 return 0; 305 return 0;
304} 306}
305 307
306static int ath5k_pci_resume(struct device *dev) 308static int ath5k_pci_resume(struct device *dev)
307{ 309{
308 struct pci_dev *pdev = to_pci_dev(dev); 310 struct pci_dev *pdev = to_pci_dev(dev);
309 struct ath5k_softc *sc = pci_get_drvdata(pdev); 311 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
312 struct ath5k_hw *ah = hw->priv;
310 313
311 /* 314 /*
312 * Suspend/Resume resets the PCI configuration space, so we have to 315 * Suspend/Resume resets the PCI configuration space, so we have to
@@ -315,7 +318,7 @@ static int ath5k_pci_resume(struct device *dev)
315 */ 318 */
316 pci_write_config_byte(pdev, 0x41, 0); 319 pci_write_config_byte(pdev, 0x41, 0);
317 320
318 ath5k_led_enable(sc); 321 ath5k_led_enable(ah);
319 return 0; 322 return 0;
320} 323}
321 324
diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c
index 712a9ac4000e..067313845060 100644
--- a/drivers/net/wireless/ath/ath5k/pcu.c
+++ b/drivers/net/wireless/ath/ath5k/pcu.c
@@ -32,7 +32,7 @@
32#include "base.h" 32#include "base.h"
33 33
34/* 34/*
35 * AR5212+ can use higher rates for ack transmition 35 * AR5212+ can use higher rates for ack transmission
36 * based on current tx rate instead of the base rate. 36 * based on current tx rate instead of the base rate.
37 * It does this to better utilize channel usage. 37 * It does this to better utilize channel usage.
38 * This is a mapping between G rates (that cover both 38 * This is a mapping between G rates (that cover both
@@ -77,14 +77,13 @@ static const unsigned int ack_rates_high[] =
77int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 77int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
78 int len, struct ieee80211_rate *rate, bool shortpre) 78 int len, struct ieee80211_rate *rate, bool shortpre)
79{ 79{
80 struct ath5k_softc *sc = ah->ah_sc;
81 int sifs, preamble, plcp_bits, sym_time; 80 int sifs, preamble, plcp_bits, sym_time;
82 int bitrate, bits, symbols, symbol_bits; 81 int bitrate, bits, symbols, symbol_bits;
83 int dur; 82 int dur;
84 83
85 /* Fallback */ 84 /* Fallback */
86 if (!ah->ah_bwmode) { 85 if (!ah->ah_bwmode) {
87 __le16 raw_dur = ieee80211_generic_frame_duration(sc->hw, 86 __le16 raw_dur = ieee80211_generic_frame_duration(ah->hw,
88 NULL, len, rate); 87 NULL, len, rate);
89 88
90 /* subtract difference between long and short preamble */ 89 /* subtract difference between long and short preamble */
@@ -205,7 +204,7 @@ unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
205 */ 204 */
206void ath5k_hw_update_mib_counters(struct ath5k_hw *ah) 205void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
207{ 206{
208 struct ath5k_statistics *stats = &ah->ah_sc->stats; 207 struct ath5k_statistics *stats = &ah->stats;
209 208
210 /* Read-And-Clear */ 209 /* Read-And-Clear */
211 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL); 210 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
@@ -240,25 +239,24 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
240 */ 239 */
241static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah) 240static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
242{ 241{
243 struct ath5k_softc *sc = ah->ah_sc;
244 struct ieee80211_rate *rate; 242 struct ieee80211_rate *rate;
245 unsigned int i; 243 unsigned int i;
246 /* 802.11g covers both OFDM and CCK */ 244 /* 802.11g covers both OFDM and CCK */
247 u8 band = IEEE80211_BAND_2GHZ; 245 u8 band = IEEE80211_BAND_2GHZ;
248 246
249 /* Write rate duration table */ 247 /* Write rate duration table */
250 for (i = 0; i < sc->sbands[band].n_bitrates; i++) { 248 for (i = 0; i < ah->sbands[band].n_bitrates; i++) {
251 u32 reg; 249 u32 reg;
252 u16 tx_time; 250 u16 tx_time;
253 251
254 if (ah->ah_ack_bitrate_high) 252 if (ah->ah_ack_bitrate_high)
255 rate = &sc->sbands[band].bitrates[ack_rates_high[i]]; 253 rate = &ah->sbands[band].bitrates[ack_rates_high[i]];
256 /* CCK -> 1Mb */ 254 /* CCK -> 1Mb */
257 else if (i < 4) 255 else if (i < 4)
258 rate = &sc->sbands[band].bitrates[0]; 256 rate = &ah->sbands[band].bitrates[0];
259 /* OFDM -> 6Mb */ 257 /* OFDM -> 6Mb */
260 else 258 else
261 rate = &sc->sbands[band].bitrates[4]; 259 rate = &ah->sbands[band].bitrates[4];
262 260
263 /* Set ACK timeout */ 261 /* Set ACK timeout */
264 reg = AR5K_RATE_DUR(rate->hw_value); 262 reg = AR5K_RATE_DUR(rate->hw_value);
@@ -534,9 +532,9 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
534 532
535 local_irq_restore(flags); 533 local_irq_restore(flags);
536 534
537 WARN_ON( i == ATH5K_MAX_TSF_READ ); 535 WARN_ON(i == ATH5K_MAX_TSF_READ);
538 536
539 return (((u64)tsf_upper1 << 32) | tsf_lower); 537 return ((u64)tsf_upper1 << 32) | tsf_lower;
540} 538}
541 539
542/** 540/**
@@ -586,7 +584,7 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
586 /* 584 /*
587 * Set the additional timers by mode 585 * Set the additional timers by mode
588 */ 586 */
589 switch (ah->ah_sc->opmode) { 587 switch (ah->opmode) {
590 case NL80211_IFTYPE_MONITOR: 588 case NL80211_IFTYPE_MONITOR:
591 case NL80211_IFTYPE_STATION: 589 case NL80211_IFTYPE_STATION:
592 /* In STA mode timer1 is used as next wakeup 590 /* In STA mode timer1 is used as next wakeup
@@ -623,8 +621,8 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
623 * Set the beacon register and enable all timers. 621 * Set the beacon register and enable all timers.
624 */ 622 */
625 /* When in AP or Mesh Point mode zero timer0 to start TSF */ 623 /* When in AP or Mesh Point mode zero timer0 to start TSF */
626 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP || 624 if (ah->opmode == NL80211_IFTYPE_AP ||
627 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT) 625 ah->opmode == NL80211_IFTYPE_MESH_POINT)
628 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0); 626 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
629 627
630 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0); 628 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
@@ -643,14 +641,14 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
643 /* Flush any pending BMISS interrupts on ISR by 641 /* Flush any pending BMISS interrupts on ISR by
644 * performing a clear-on-write operation on PISR 642 * performing a clear-on-write operation on PISR
645 * register for the BMISS bit (writing a bit on 643 * register for the BMISS bit (writing a bit on
646 * ISR togles a reset for that bit and leaves 644 * ISR toggles a reset for that bit and leaves
647 * the rest bits intact) */ 645 * the remaining bits intact) */
648 if (ah->ah_version == AR5K_AR5210) 646 if (ah->ah_version == AR5K_AR5210)
649 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR); 647 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
650 else 648 else
651 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR); 649 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
652 650
653 /* TODO: Set enchanced sleep registers on AR5212 651 /* TODO: Set enhanced sleep registers on AR5212
654 * based on vif->bss_conf params, until then 652 * based on vif->bss_conf params, until then
655 * disable power save reporting.*/ 653 * disable power save reporting.*/
656 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV); 654 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
@@ -738,7 +736,7 @@ ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
738 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3; 736 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;
739 737
740 /* NOTE: SWBA is different. Having a wrong window there does not 738 /* NOTE: SWBA is different. Having a wrong window there does not
741 * stop us from sending data and this condition is catched thru 739 * stop us from sending data and this condition is caught by
742 * other means (SWBA interrupt) */ 740 * other means (SWBA interrupt) */
743 741
744 if (ath5k_check_timer_win(nbtt, atim, 1, intval) && 742 if (ath5k_check_timer_win(nbtt, atim, 1, intval) &&
@@ -814,7 +812,7 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
814 struct ath_common *common = ath5k_hw_common(ah); 812 struct ath_common *common = ath5k_hw_common(ah);
815 u32 pcu_reg, beacon_reg, low_id, high_id; 813 u32 pcu_reg, beacon_reg, low_id, high_id;
816 814
817 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode); 815 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
818 816
819 /* Preserve rest settings */ 817 /* Preserve rest settings */
820 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 818 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
@@ -890,13 +888,13 @@ void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
890 * XXX: rethink this after new mode changes to 888 * XXX: rethink this after new mode changes to
891 * mac80211 are integrated */ 889 * mac80211 are integrated */
892 if (ah->ah_version == AR5K_AR5212 && 890 if (ah->ah_version == AR5K_AR5212 &&
893 ah->ah_sc->nvifs) 891 ah->nvifs)
894 ath5k_hw_write_rate_duration(ah); 892 ath5k_hw_write_rate_duration(ah);
895 893
896 /* Set RSSI/BRSSI thresholds 894 /* Set RSSI/BRSSI thresholds
897 * 895 *
898 * Note: If we decide to set this value 896 * Note: If we decide to set this value
899 * dynamicaly, have in mind that when AR5K_RSSI_THR 897 * dynamically, have in mind that when AR5K_RSSI_THR
900 * register is read it might return 0x40 if we haven't 898 * register is read it might return 0x40 if we haven't
901 * wrote anything to it plus BMISS RSSI threshold is zeroed. 899 * wrote anything to it plus BMISS RSSI threshold is zeroed.
902 * So doing a save/restore procedure here isn't the right 900 * So doing a save/restore procedure here isn't the right
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index 55441913344d..81e465e70175 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -22,6 +22,7 @@
22 22
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/slab.h> 24#include <linux/slab.h>
25#include <asm/unaligned.h>
25 26
26#include "ath5k.h" 27#include "ath5k.h"
27#include "reg.h" 28#include "reg.h"
@@ -105,6 +106,7 @@ bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
105 106
106 if ((ah->ah_radio == AR5K_RF5112) || 107 if ((ah->ah_radio == AR5K_RF5112) ||
107 (ah->ah_radio == AR5K_RF5413) || 108 (ah->ah_radio == AR5K_RF5413) ||
109 (ah->ah_radio == AR5K_RF2413) ||
108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) 110 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
109 refclk_freq = 40; 111 refclk_freq = 40;
110 else 112 else
@@ -173,7 +175,7 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
173 data = ath5k_hw_bitswap(val, num_bits); 175 data = ath5k_hw_bitswap(val, num_bits);
174 176
175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0; 177 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
176 position = 0, entry++) { 178 position = 0, entry++) {
177 179
178 last_bit = (position + bits_left > 8) ? 8 : 180 last_bit = (position + bits_left > 8) ? 8 :
179 position + bits_left; 181 position + bits_left;
@@ -363,7 +365,7 @@ int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
363 return 0; 365 return 0;
364} 366}
365 367
366/* Schedule a gain probe check on the next transmited packet. 368/* Schedule a gain probe check on the next transmitted packet.
367 * That means our next packet is going to be sent with lower 369 * That means our next packet is going to be sent with lower
368 * tx power and a Peak to Average Power Detector (PAPD) will try 370 * tx power and a Peak to Average Power Detector (PAPD) will try
369 * to measure the gain. 371 * to measure the gain.
@@ -472,7 +474,7 @@ static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
472 level[0] = 0; 474 level[0] = 0;
473 level[1] = (step == 63) ? 50 : step + 4; 475 level[1] = (step == 63) ? 50 : step + 4;
474 level[2] = (step != 63) ? 64 : level[0]; 476 level[2] = (step != 63) ? 64 : level[0];
475 level[3] = level[2] + 50 ; 477 level[3] = level[2] + 50;
476 478
477 ah->ah_gain.g_high = level[3] - 479 ah->ah_gain.g_high = level[3] -
478 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5); 480 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
@@ -549,7 +551,7 @@ static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
549 551
550 for (ah->ah_gain.g_target = ah->ah_gain.g_current; 552 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
551 ah->ah_gain.g_target <= ah->ah_gain.g_low && 553 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
552 ah->ah_gain.g_step_idx < go->go_steps_count-1; 554 ah->ah_gain.g_step_idx < go->go_steps_count - 1;
553 g_step = &go->go_step[ah->ah_gain.g_step_idx]) 555 g_step = &go->go_step[ah->ah_gain.g_step_idx])
554 ah->ah_gain.g_target -= 2 * 556 ah->ah_gain.g_target -= 2 *
555 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - 557 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
@@ -560,7 +562,7 @@ static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
560 } 562 }
561 563
562done: 564done:
563 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 565 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
564 "ret %d, gain step %u, current gain %u, target gain %u\n", 566 "ret %d, gain step %u, current gain %u, target gain %u\n",
565 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, 567 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
566 ah->ah_gain.g_target); 568 ah->ah_gain.g_target);
@@ -614,13 +616,13 @@ enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
614 ath5k_hw_rf_gainf_corr(ah); 616 ath5k_hw_rf_gainf_corr(ah);
615 ah->ah_gain.g_current = 617 ah->ah_gain.g_current =
616 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 618 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
617 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 619 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) :
618 0; 620 0;
619 } 621 }
620 622
621 /* Check if measurement is ok and if we need 623 /* Check if measurement is ok and if we need
622 * to adjust gain, schedule a gain adjustment, 624 * to adjust gain, schedule a gain adjustment,
623 * else switch back to the acive state */ 625 * else switch back to the active state */
624 if (ath5k_hw_rf_check_gainf_readback(ah) && 626 if (ath5k_hw_rf_check_gainf_readback(ah) &&
625 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 627 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
626 ath5k_hw_rf_gainf_adjust(ah)) { 628 ath5k_hw_rf_gainf_adjust(ah)) {
@@ -772,7 +774,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
772 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, 774 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
773 GFP_KERNEL); 775 GFP_KERNEL);
774 if (ah->ah_rf_banks == NULL) { 776 if (ah->ah_rf_banks == NULL) {
775 ATH5K_ERR(ah->ah_sc, "out of memory\n"); 777 ATH5K_ERR(ah, "out of memory\n");
776 return -ENOMEM; 778 return -ENOMEM;
777 } 779 }
778 } 780 }
@@ -782,7 +784,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
782 784
783 for (i = 0; i < ah->ah_rf_banks_size; i++) { 785 for (i = 0; i < ah->ah_rf_banks_size; i++) {
784 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 786 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
785 ATH5K_ERR(ah->ah_sc, "invalid bank\n"); 787 ATH5K_ERR(ah, "invalid bank\n");
786 return -EINVAL; 788 return -EINVAL;
787 } 789 }
788 790
@@ -807,7 +809,7 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
807 * use b_OB and b_DB parameters stored 809 * use b_OB and b_DB parameters stored
808 * in eeprom on ee->ee_ob[ee_mode][0] 810 * in eeprom on ee->ee_ob[ee_mode][0]
809 * 811 *
810 * For all other chips we use OB/DB for 2Ghz 812 * For all other chips we use OB/DB for 2GHz
811 * stored in the b/g modal section just like 813 * stored in the b/g modal section just like
812 * 802.11a on ee->ee_ob[ee_mode][1] */ 814 * 802.11a on ee->ee_ob[ee_mode][1] */
813 if ((ah->ah_radio == AR5K_RF5111) || 815 if ((ah->ah_radio == AR5K_RF5111) ||
@@ -970,17 +972,20 @@ static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
970 } 972 }
971 973
972 /* Lower synth voltage on Rev 2 */ 974 /* Lower synth voltage on Rev 2 */
973 ath5k_hw_rfb_op(ah, rf_regs, 2, 975 if (ah->ah_radio == AR5K_RF5112 &&
974 AR5K_RF_HIGH_VC_CP, true); 976 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) {
977 ath5k_hw_rfb_op(ah, rf_regs, 2,
978 AR5K_RF_HIGH_VC_CP, true);
975 979
976 ath5k_hw_rfb_op(ah, rf_regs, 2, 980 ath5k_hw_rfb_op(ah, rf_regs, 2,
977 AR5K_RF_MID_VC_CP, true); 981 AR5K_RF_MID_VC_CP, true);
978 982
979 ath5k_hw_rfb_op(ah, rf_regs, 2, 983 ath5k_hw_rfb_op(ah, rf_regs, 2,
980 AR5K_RF_LOW_VC_CP, true); 984 AR5K_RF_LOW_VC_CP, true);
981 985
982 ath5k_hw_rfb_op(ah, rf_regs, 2, 986 ath5k_hw_rfb_op(ah, rf_regs, 2,
983 AR5K_RF_PUSH_UP, true); 987 AR5K_RF_PUSH_UP, true);
988 }
984 989
985 /* Decrease power consumption on 5213+ BaseBand */ 990 /* Decrease power consumption on 5213+ BaseBand */
986 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 991 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
@@ -1259,12 +1264,12 @@ static int ath5k_hw_channel(struct ath5k_hw *ah,
1259{ 1264{
1260 int ret; 1265 int ret;
1261 /* 1266 /*
1262 * Check bounds supported by the PHY (we don't care about regultory 1267 * Check bounds supported by the PHY (we don't care about regulatory
1263 * restrictions at this point). Note: hw_value already has the band 1268 * restrictions at this point). Note: hw_value already has the band
1264 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 1269 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1265 * of the band by that */ 1270 * of the band by that */
1266 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 1271 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1267 ATH5K_ERR(ah->ah_sc, 1272 ATH5K_ERR(ah,
1268 "channel frequency (%u MHz) out of supported " 1273 "channel frequency (%u MHz) out of supported "
1269 "band range\n", 1274 "band range\n",
1270 channel->center_freq); 1275 channel->center_freq);
@@ -1331,7 +1336,7 @@ void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1331static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) 1336static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1332{ 1337{
1333 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; 1338 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1334 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1); 1339 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1);
1335 hist->nfval[hist->index] = noise_floor; 1340 hist->nfval[hist->index] = noise_floor;
1336} 1341}
1337 1342
@@ -1344,18 +1349,18 @@ static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1344 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); 1349 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1345 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) { 1350 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1346 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) { 1351 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1347 if (sort[j] > sort[j-1]) { 1352 if (sort[j] > sort[j - 1]) {
1348 tmp = sort[j]; 1353 tmp = sort[j];
1349 sort[j] = sort[j-1]; 1354 sort[j] = sort[j - 1];
1350 sort[j-1] = tmp; 1355 sort[j - 1] = tmp;
1351 } 1356 }
1352 } 1357 }
1353 } 1358 }
1354 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) { 1359 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1355 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1360 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1356 "cal %d:%d\n", i, sort[i]); 1361 "cal %d:%d\n", i, sort[i]);
1357 } 1362 }
1358 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2]; 1363 return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
1359} 1364}
1360 1365
1361/* 1366/*
@@ -1378,7 +1383,7 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1378 1383
1379 /* keep last value if calibration hasn't completed */ 1384 /* keep last value if calibration hasn't completed */
1380 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { 1385 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1381 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1386 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1382 "NF did not complete in calibration window\n"); 1387 "NF did not complete in calibration window\n");
1383 1388
1384 return; 1389 return;
@@ -1391,7 +1396,7 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1391 threshold = ee->ee_noise_floor_thr[ee_mode]; 1396 threshold = ee->ee_noise_floor_thr[ee_mode];
1392 1397
1393 if (nf > threshold) { 1398 if (nf > threshold) {
1394 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1399 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1395 "noise floor failure detected; " 1400 "noise floor failure detected; "
1396 "read %d, threshold %d\n", 1401 "read %d, threshold %d\n",
1397 nf, threshold); 1402 nf, threshold);
@@ -1428,7 +1433,7 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1428 1433
1429 ah->ah_noise_floor = nf; 1434 ah->ah_noise_floor = nf;
1430 1435
1431 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1436 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
1432 "noise floor calibrated: %d\n", nf); 1437 "noise floor calibrated: %d\n", nf);
1433} 1438}
1434 1439
@@ -1516,7 +1521,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1516 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); 1521 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1517 1522
1518 if (ret) { 1523 if (ret) {
1519 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", 1524 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n",
1520 channel->center_freq); 1525 channel->center_freq);
1521 return ret; 1526 return ret;
1522 } 1527 }
@@ -1551,7 +1556,7 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1551 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); 1556 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1552 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); 1557 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1553 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); 1558 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1554 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1559 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
1555 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr); 1560 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1556 if (i_pwr && q_pwr) 1561 if (i_pwr && q_pwr)
1557 break; 1562 break;
@@ -1577,7 +1582,7 @@ ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1577 q_coff = (i_pwr / q_coffd) - 128; 1582 q_coff = (i_pwr / q_coffd) - 128;
1578 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */ 1583 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1579 1584
1580 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE, 1585 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
1581 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)", 1586 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1582 i_coff, q_coff, i_coffd, q_coffd); 1587 i_coff, q_coff, i_coffd, q_coffd);
1583 1588
@@ -1604,11 +1609,13 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1604 int ret; 1609 int ret;
1605 1610
1606 if (ah->ah_radio == AR5K_RF5110) 1611 if (ah->ah_radio == AR5K_RF5110)
1607 ret = ath5k_hw_rf5110_calibrate(ah, channel); 1612 return ath5k_hw_rf5110_calibrate(ah, channel);
1608 else { 1613
1609 ret = ath5k_hw_rf511x_iq_calibrate(ah); 1614 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1615
1616 if ((ah->ah_radio == AR5K_RF5111 || ah->ah_radio == AR5K_RF5112) &&
1617 (channel->hw_value & CHANNEL_OFDM))
1610 ath5k_hw_request_rfgain_probe(ah); 1618 ath5k_hw_request_rfgain_probe(ah);
1611 }
1612 1619
1613 return ret; 1620 return ret;
1614} 1621}
@@ -1815,7 +1822,7 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1815 1822
1816 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & 1823 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1817 AR5K_PHY_IQ_SPUR_FILT_EN) { 1824 AR5K_PHY_IQ_SPUR_FILT_EN) {
1818 /* Clean up spur mitigation settings and disable fliter */ 1825 /* Clean up spur mitigation settings and disable filter */
1819 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, 1826 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1820 AR5K_PHY_BIN_MASK_CTL_RATE, 0); 1827 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1821 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, 1828 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
@@ -1960,7 +1967,7 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1960 1967
1961 ee_mode = ath5k_eeprom_mode_from_channel(channel); 1968 ee_mode = ath5k_eeprom_mode_from_channel(channel);
1962 if (ee_mode < 0) { 1969 if (ee_mode < 0) {
1963 ATH5K_ERR(ah->ah_sc, 1970 ATH5K_ERR(ah,
1964 "invalid channel: %d\n", channel->center_freq); 1971 "invalid channel: %d\n", channel->center_freq);
1965 return; 1972 return;
1966 } 1973 }
@@ -2080,7 +2087,7 @@ ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2080 * always 1 instead of 1.25, 1.75 etc). We scale up by 100 2087 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2081 * to have some accuracy both for 0.5 and 0.25 steps. 2088 * to have some accuracy both for 0.5 and 0.25 steps.
2082 */ 2089 */
2083 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left)); 2090 ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left));
2084 2091
2085 /* Now scale down to be in range */ 2092 /* Now scale down to be in range */
2086 result = y_left + (ratio * (target - x_left) / 100); 2093 result = y_left + (ratio * (target - x_left) / 100);
@@ -2159,7 +2166,7 @@ ath5k_create_power_curve(s16 pmin, s16 pmax,
2159 u8 *vpd_table, u8 type) 2166 u8 *vpd_table, u8 type)
2160{ 2167{
2161 u8 idx[2] = { 0, 1 }; 2168 u8 idx[2] = { 0, 1 };
2162 s16 pwr_i = 2*pmin; 2169 s16 pwr_i = 2 * pmin;
2163 int i; 2170 int i;
2164 2171
2165 if (num_points < 2) 2172 if (num_points < 2)
@@ -2437,7 +2444,7 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2437 } 2444 }
2438 2445
2439 if (edge_pwr) 2446 if (edge_pwr)
2440 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr); 2447 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr);
2441} 2448}
2442 2449
2443 2450
@@ -2456,7 +2463,7 @@ static void
2456ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, 2463ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2457 s16 *table_max) 2464 s16 *table_max)
2458{ 2465{
2459 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2466 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2460 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; 2467 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2461 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i; 2468 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2462 s16 min_pwr, max_pwr; 2469 s16 min_pwr, max_pwr;
@@ -2475,8 +2482,8 @@ ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2475 2482
2476 /* Copy values from pcdac_tmp */ 2483 /* Copy values from pcdac_tmp */
2477 pwr_idx = min_pwr; 2484 pwr_idx = min_pwr;
2478 for (i = 0 ; pwr_idx <= max_pwr && 2485 for (i = 0; pwr_idx <= max_pwr &&
2479 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) { 2486 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2480 pcdac_out[pcdac_i++] = pcdac_tmp[i]; 2487 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2481 pwr_idx++; 2488 pwr_idx++;
2482 } 2489 }
@@ -2502,7 +2509,7 @@ static void
2502ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, 2509ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2503 s16 *table_max, u8 pdcurves) 2510 s16 *table_max, u8 pdcurves)
2504{ 2511{
2505 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2512 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2506 u8 *pcdac_low_pwr; 2513 u8 *pcdac_low_pwr;
2507 u8 *pcdac_high_pwr; 2514 u8 *pcdac_high_pwr;
2508 u8 *pcdac_tmp; 2515 u8 *pcdac_tmp;
@@ -2510,8 +2517,8 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2510 s16 max_pwr_idx; 2517 s16 max_pwr_idx;
2511 s16 min_pwr_idx; 2518 s16 min_pwr_idx;
2512 s16 mid_pwr_idx = 0; 2519 s16 mid_pwr_idx = 0;
2513 /* Edge flag turs on the 7nth bit on the PCDAC 2520 /* Edge flag turns on the 7nth bit on the PCDAC
2514 * to delcare the higher power curve (force values 2521 * to declare the higher power curve (force values
2515 * to be greater than 64). If we only have one curve 2522 * to be greater than 64). If we only have one curve
2516 * we don't need to set this, if we have 2 curves and 2523 * we don't need to set this, if we have 2 curves and
2517 * fill the table backwards this can also be used to 2524 * fill the table backwards this can also be used to
@@ -2552,7 +2559,7 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2552 } 2559 }
2553 2560
2554 /* This is used when setting tx power*/ 2561 /* This is used when setting tx power*/
2555 ah->ah_txpower.txp_min_idx = min_pwr_idx/2; 2562 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2;
2556 2563
2557 /* Fill Power to PCDAC table backwards */ 2564 /* Fill Power to PCDAC table backwards */
2558 pwr = max_pwr_idx; 2565 pwr = max_pwr_idx;
@@ -2561,14 +2568,14 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2561 * edge flag and set pcdac_tmp to lower 2568 * edge flag and set pcdac_tmp to lower
2562 * power curve.*/ 2569 * power curve.*/
2563 if (edge_flag == 0x40 && 2570 if (edge_flag == 0x40 &&
2564 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) { 2571 (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2565 edge_flag = 0x00; 2572 edge_flag = 0x00;
2566 pcdac_tmp = pcdac_low_pwr; 2573 pcdac_tmp = pcdac_low_pwr;
2567 pwr = mid_pwr_idx/2; 2574 pwr = mid_pwr_idx / 2;
2568 } 2575 }
2569 2576
2570 /* Don't go below 1, extrapolate below if we have 2577 /* Don't go below 1, extrapolate below if we have
2571 * already swithced to the lower power curve -or 2578 * already switched to the lower power curve -or
2572 * we only have one curve and edge_flag is zero 2579 * we only have one curve and edge_flag is zero
2573 * anyway */ 2580 * anyway */
2574 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) { 2581 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
@@ -2596,7 +2603,7 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2596static void 2603static void
2597ath5k_write_pcdac_table(struct ath5k_hw *ah) 2604ath5k_write_pcdac_table(struct ath5k_hw *ah)
2598{ 2605{
2599 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; 2606 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2600 int i; 2607 int i;
2601 2608
2602 /* 2609 /*
@@ -2604,8 +2611,8 @@ ath5k_write_pcdac_table(struct ath5k_hw *ah)
2604 */ 2611 */
2605 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2612 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2606 ath5k_hw_reg_write(ah, 2613 ath5k_hw_reg_write(ah,
2607 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) | 2614 (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) |
2608 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16), 2615 (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16),
2609 AR5K_PHY_PCDAC_TXPOWER(i)); 2616 AR5K_PHY_PCDAC_TXPOWER(i));
2610 } 2617 }
2611} 2618}
@@ -2788,12 +2795,8 @@ ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2788 * Write TX power values 2795 * Write TX power values
2789 */ 2796 */
2790 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) { 2797 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2791 ath5k_hw_reg_write(ah, 2798 u32 val = get_unaligned_le32(&pdadc_out[4 * i]);
2792 ((pdadc_out[4*i + 0] & 0xff) << 0) | 2799 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i));
2793 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2794 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2795 ((pdadc_out[4*i + 3] & 0xff) << 24),
2796 AR5K_PHY_PDADC_TXPOWER(i));
2797 } 2800 }
2798} 2801}
2799 2802
@@ -2805,7 +2808,7 @@ ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
2805/* 2808/*
2806 * This is the main function that uses all of the above 2809 * This is the main function that uses all of the above
2807 * to set PCDAC/PDADC table on hw for the current channel. 2810 * to set PCDAC/PDADC table on hw for the current channel.
2808 * This table is used for tx power calibration on the basband, 2811 * This table is used for tx power calibration on the baseband,
2809 * without it we get weird tx power levels and in some cases 2812 * without it we get weird tx power levels and in some cases
2810 * distorted spectral mask 2813 * distorted spectral mask
2811 */ 2814 */
@@ -3116,13 +3119,13 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3116 int ret; 3119 int ret;
3117 3120
3118 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 3121 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3119 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower); 3122 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower);
3120 return -EINVAL; 3123 return -EINVAL;
3121 } 3124 }
3122 3125
3123 ee_mode = ath5k_eeprom_mode_from_channel(channel); 3126 ee_mode = ath5k_eeprom_mode_from_channel(channel);
3124 if (ee_mode < 0) { 3127 if (ee_mode < 0) {
3125 ATH5K_ERR(ah->ah_sc, 3128 ATH5K_ERR(ah,
3126 "invalid channel: %d\n", channel->center_freq); 3129 "invalid channel: %d\n", channel->center_freq);
3127 return -EINVAL; 3130 return -EINVAL;
3128 } 3131 }
@@ -3223,7 +3226,7 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3223 3226
3224int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) 3227int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3225{ 3228{
3226 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER, 3229 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER,
3227 "changing txpower to %d\n", txpower); 3230 "changing txpower to %d\n", txpower);
3228 3231
3229 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); 3232 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
@@ -3434,7 +3437,7 @@ int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3434 * during ath5k_phy_calibrate) */ 3437 * during ath5k_phy_calibrate) */
3435 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 3438 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3436 AR5K_PHY_AGCCTL_CAL, 0, false)) { 3439 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3437 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", 3440 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n",
3438 channel->center_freq); 3441 channel->center_freq);
3439 } 3442 }
3440 3443
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index b18c5021aac3..65f10398999e 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -187,7 +187,7 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
187 break; 187 break;
188 case AR5K_TX_QUEUE_XR_DATA: 188 case AR5K_TX_QUEUE_XR_DATA:
189 if (ah->ah_version != AR5K_AR5212) 189 if (ah->ah_version != AR5K_AR5212)
190 ATH5K_ERR(ah->ah_sc, 190 ATH5K_ERR(ah,
191 "XR data queues only supported in" 191 "XR data queues only supported in"
192 " 5212!\n"); 192 " 5212!\n");
193 queue = AR5K_TX_QUEUE_ID_XR_DATA; 193 queue = AR5K_TX_QUEUE_ID_XR_DATA;
@@ -510,7 +510,6 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
510int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time) 510int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time)
511{ 511{
512 struct ieee80211_channel *channel = ah->ah_current_channel; 512 struct ieee80211_channel *channel = ah->ah_current_channel;
513 struct ath5k_softc *sc = ah->ah_sc;
514 struct ieee80211_rate *rate; 513 struct ieee80211_rate *rate;
515 u32 ack_tx_time, eifs, eifs_clock, sifs, sifs_clock; 514 u32 ack_tx_time, eifs, eifs_clock, sifs, sifs_clock;
516 u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time); 515 u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time);
@@ -546,9 +545,9 @@ int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time)
546 * Also we have different lowest rate for 802.11a 545 * Also we have different lowest rate for 802.11a
547 */ 546 */
548 if (channel->hw_value & CHANNEL_5GHZ) 547 if (channel->hw_value & CHANNEL_5GHZ)
549 rate = &sc->sbands[IEEE80211_BAND_5GHZ].bitrates[0]; 548 rate = &ah->sbands[IEEE80211_BAND_5GHZ].bitrates[0];
550 else 549 else
551 rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[0]; 550 rate = &ah->sbands[IEEE80211_BAND_2GHZ].bitrates[0];
552 551
553 ack_tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false); 552 ack_tx_time = ath5k_hw_get_frame_duration(ah, 10, rate, false);
554 553
@@ -622,7 +621,7 @@ int ath5k_hw_init_queues(struct ath5k_hw *ah)
622 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) { 621 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
623 ret = ath5k_hw_reset_tx_queue(ah, i); 622 ret = ath5k_hw_reset_tx_queue(ah, i);
624 if (ret) { 623 if (ret) {
625 ATH5K_ERR(ah->ah_sc, 624 ATH5K_ERR(ah,
626 "failed to reset TX queue #%d\n", i); 625 "failed to reset TX queue #%d\n", i);
627 return ret; 626 return ret;
628 } 627 }
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index d12b827033c1..f5c1000045d3 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -72,7 +72,7 @@
72#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ 72#define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
73#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */ 73#define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
74#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */ 74#define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
75#define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */ 75#define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */
76#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ 76#define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */
77#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ 77#define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */
78#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */ 78#define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */
@@ -170,7 +170,7 @@
170#define AR5K_TXCFG_SDMAMR_S 0 170#define AR5K_TXCFG_SDMAMR_S 0
171#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ 171#define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */
172#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ 172#define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */
173#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ 173#define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Trigger level mask */
174#define AR5K_TXCFG_TXFULL_S 4 174#define AR5K_TXCFG_TXFULL_S 4
175#define AR5K_TXCFG_TXFULL_0B 0x00000000 175#define AR5K_TXCFG_TXFULL_0B 0x00000000
176#define AR5K_TXCFG_TXFULL_64B 0x00000010 176#define AR5K_TXCFG_TXFULL_64B 0x00000010
@@ -283,16 +283,16 @@
283 */ 283 */
284#define AR5K_ISR 0x001c /* Register Address [5210] */ 284#define AR5K_ISR 0x001c /* Register Address [5210] */
285#define AR5K_PISR 0x0080 /* Register Address [5211+] */ 285#define AR5K_PISR 0x0080 /* Register Address [5211+] */
286#define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly received */ 286#define AR5K_ISR_RXOK 0x00000001 /* Frame successfully received */
287#define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ 287#define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */
288#define AR5K_ISR_RXERR 0x00000004 /* Receive error */ 288#define AR5K_ISR_RXERR 0x00000004 /* Receive error */
289#define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ 289#define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */
290#define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ 290#define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */
291#define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ 291#define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */
292#define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ 292#define AR5K_ISR_TXOK 0x00000040 /* Frame successfully transmitted */
293#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ 293#define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */
294#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ 294#define AR5K_ISR_TXERR 0x00000100 /* Transmit error */
295#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ 295#define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout) */
296#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ 296#define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */
297#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ 297#define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */
298#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ 298#define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */
@@ -303,7 +303,7 @@
303#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ 303#define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
304#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ 304#define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */
305#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 305#define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
306#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ 306#define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */
307#define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ 307#define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
308#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ 308#define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */
309#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ 309#define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */
@@ -377,16 +377,16 @@
377 */ 377 */
378#define AR5K_IMR 0x0020 /* Register Address [5210] */ 378#define AR5K_IMR 0x0020 /* Register Address [5210] */
379#define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ 379#define AR5K_PIMR 0x00a0 /* Register Address [5211+] */
380#define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly received*/ 380#define AR5K_IMR_RXOK 0x00000001 /* Frame successfully received*/
381#define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ 381#define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/
382#define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ 382#define AR5K_IMR_RXERR 0x00000004 /* Receive error*/
383#define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ 383#define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/
384#define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ 384#define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/
385#define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ 385#define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/
386#define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ 386#define AR5K_IMR_TXOK 0x00000040 /* Frame successfully transmitted*/
387#define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ 387#define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/
388#define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ 388#define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/
389#define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ 389#define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmitted (transmit timeout)*/
390#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ 390#define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/
391#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ 391#define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/
392#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ 392#define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/
@@ -397,7 +397,7 @@
397#define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ 397#define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */
398#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ 398#define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/
399#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ 399#define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */
400#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ 400#define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */
401#define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ 401#define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */
402#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ 402#define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/
403#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ 403#define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */
@@ -601,7 +601,7 @@
601 * QCU misc registers 601 * QCU misc registers
602 */ 602 */
603#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ 603#define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
604#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ 604#define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame scheduling mask */
605#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ 605#define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */
606#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ 606#define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */
607#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */ 607#define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */
@@ -653,13 +653,13 @@
653 * registers [5211+] 653 * registers [5211+]
654 * 654 *
655 * These registers control the various characteristics of each queue 655 * These registers control the various characteristics of each queue
656 * for 802.11e (WME) combatibility so they go together with 656 * for 802.11e (WME) compatibility so they go together with
657 * QCU registers in pairs. For each queue we have a QCU mask register, 657 * QCU registers in pairs. For each queue we have a QCU mask register,
658 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), 658 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
659 * a retry limit register (0x1080 - 0x10ac), a channel time register 659 * a retry limit register (0x1080 - 0x10ac), a channel time register
660 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and 660 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
661 * a sequence number register (0x1140 - 0x116c). It seems that "global" 661 * a sequence number register (0x1140 - 0x116c). It seems that "global"
662 * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). 662 * registers here affect all queues (see use of DCU_GBL_IFS_SLOT in ar5k).
663 * We use the same macros here for easier register access. 663 * We use the same macros here for easier register access.
664 * 664 *
665 */ 665 */
@@ -779,7 +779,7 @@
779 * and it's used for generating pseudo-random 779 * and it's used for generating pseudo-random
780 * number sequences. 780 * number sequences.
781 * 781 *
782 * (If i understand corectly, random numbers are 782 * (If i understand correctly, random numbers are
783 * used for idle sensing -multiplied with cwmin/max etc-) 783 * used for idle sensing -multiplied with cwmin/max etc-)
784 */ 784 */
785#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ 785#define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */
@@ -1007,7 +1007,7 @@
1007#define AR5K_PCIE_WAEN 0x407c 1007#define AR5K_PCIE_WAEN 0x407c
1008 1008
1009/* 1009/*
1010 * PCI-E Serializer/Desirializer 1010 * PCI-E Serializer/Deserializer
1011 * registers 1011 * registers
1012 */ 1012 */
1013#define AR5K_PCIE_SERDES 0x4080 1013#define AR5K_PCIE_SERDES 0x4080
@@ -1227,7 +1227,7 @@
1227 AR5K_USEC_5210 : AR5K_USEC_5211) 1227 AR5K_USEC_5210 : AR5K_USEC_5211)
1228#define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */ 1228#define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */
1229#define AR5K_USEC_1_S 0 1229#define AR5K_USEC_1_S 0
1230#define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32Mhz clock */ 1230#define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32MHz clock */
1231#define AR5K_USEC_32_S 7 1231#define AR5K_USEC_32_S 7
1232#define AR5K_USEC_TX_LATENCY_5211 0x007fc000 1232#define AR5K_USEC_TX_LATENCY_5211 0x007fc000
1233#define AR5K_USEC_TX_LATENCY_5211_S 14 1233#define AR5K_USEC_TX_LATENCY_5211_S 14
@@ -1328,16 +1328,16 @@
1328#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ 1328#define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */
1329#define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ 1329#define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \
1330 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) 1330 AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)
1331#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ 1331#define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */
1332#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ 1332#define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */
1333#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ 1333#define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */
1334#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ 1334#define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */
1335#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ 1335#define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */
1336#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ 1336#define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */
1337#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ 1337#define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */
1338#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ 1338#define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */
1339#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ 1339#define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */
1340#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ 1340#define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */
1341#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ 1341#define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */
1342#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ 1342#define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */
1343#define AR5K_RX_FILTER_PHYERR \ 1343#define AR5K_RX_FILTER_PHYERR \
@@ -1461,7 +1461,7 @@
1461 * ADDAC test register [5211+] 1461 * ADDAC test register [5211+]
1462 */ 1462 */
1463#define AR5K_ADDAC_TEST 0x8054 /* Register Address */ 1463#define AR5K_ADDAC_TEST 0x8054 /* Register Address */
1464#define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */ 1464#define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */
1465#define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */ 1465#define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */
1466#define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */ 1466#define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */
1467#define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */ 1467#define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */
@@ -1632,7 +1632,7 @@
1632#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */ 1632#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */
1633#define AR5K_SLEEP0_NEXT_DTIM_S 0 1633#define AR5K_SLEEP0_NEXT_DTIM_S 0
1634#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */ 1634#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */
1635#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enchanced sleep control */ 1635#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enhanced sleep control */
1636#define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */ 1636#define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */
1637#define AR5K_SLEEP0_CABTO_S 24 1637#define AR5K_SLEEP0_CABTO_S 24
1638 1638
@@ -1657,7 +1657,7 @@
1657/* 1657/*
1658 * TX power control (TPC) register 1658 * TX power control (TPC) register
1659 * 1659 *
1660 * XXX: PCDAC steps (0.5dbm) or DBM ? 1660 * XXX: PCDAC steps (0.5dBm) or dBm ?
1661 * 1661 *
1662 */ 1662 */
1663#define AR5K_TXPC 0x80e8 /* Register Address */ 1663#define AR5K_TXPC 0x80e8 /* Register Address */
@@ -1673,7 +1673,7 @@
1673/* 1673/*
1674 * Profile count registers 1674 * Profile count registers
1675 * 1675 *
1676 * These registers can be cleared and freezed with ATH5K_MIBC, but they do not 1676 * These registers can be cleared and frozen with ATH5K_MIBC, but they do not
1677 * generate a MIB interrupt. 1677 * generate a MIB interrupt.
1678 * Instead of overflowing, they shift by one bit to the right. All registers 1678 * Instead of overflowing, they shift by one bit to the right. All registers
1679 * shift together, i.e. when one reaches the max, all shift at the same time by 1679 * shift together, i.e. when one reaches the max, all shift at the same time by
@@ -1838,7 +1838,7 @@
1838#define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/ 1838#define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/
1839#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */ 1839#define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */
1840#define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */ 1840#define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */
1841#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */ 1841#define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32kHz external) */
1842#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */ 1842#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */
1843#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */ 1843#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */
1844#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */ 1844#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */
@@ -2002,7 +2002,7 @@
2002#define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008 /* Disable antenna diversity on OFDM modes */ 2002#define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008 /* Disable antenna diversity on OFDM modes */
2003#define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */ 2003#define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */
2004#define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000 /* Allow filter calibration (?) */ 2004#define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000 /* Allow filter calibration (?) */
2005#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automaticaly */ 2005#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automatically */
2006 2006
2007/* 2007/*
2008 * PHY noise floor status register (CCA = Clear Channel Assessment) 2008 * PHY noise floor status register (CCA = Clear Channel Assessment)
@@ -2038,7 +2038,7 @@
2038#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24 2038#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24
2039 2039
2040/* Low thresholds */ 2040/* Low thresholds */
2041#define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c 2041#define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c
2042#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001 2042#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001
2043#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00 2043#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00
2044#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8 2044#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8
@@ -2089,7 +2089,7 @@
2089 * 2089 *
2090 * It's obvious from the code that 0x989c is the buffer register but 2090 * It's obvious from the code that 0x989c is the buffer register but
2091 * for the other special registers that we write to after sending each 2091 * for the other special registers that we write to after sending each
2092 * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers 2092 * packet, i have no idea. So I'll name them BUFFER_CONTROL_X registers
2093 * for now. It's interesting that they are also used for some other operations. 2093 * for now. It's interesting that they are also used for some other operations.
2094 */ 2094 */
2095 2095
@@ -2259,12 +2259,13 @@
2259#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */ 2259#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */
2260#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 2260#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000
2261#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */ 2261#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */
2262#define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ 2262#define AR5K_PHY_FRAME_CTL_INI \
2263 AR5K_PHY_FRAME_CTL_TXURN_ERR | \ 2263 (AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
2264 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ 2264 AR5K_PHY_FRAME_CTL_TXURN_ERR | \
2265 AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ 2265 AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
2266 AR5K_PHY_FRAME_CTL_PARITY_ERR | \ 2266 AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
2267 AR5K_PHY_FRAME_CTL_TIMING_ERR 2267 AR5K_PHY_FRAME_CTL_PARITY_ERR | \
2268 AR5K_PHY_FRAME_CTL_TIMING_ERR)
2268 2269
2269/* 2270/*
2270 * PHY Tx Power adjustment register [5212A+] 2271 * PHY Tx Power adjustment register [5212A+]
@@ -2281,22 +2282,22 @@
2281#define AR5K_PHY_RADAR 0x9954 2282#define AR5K_PHY_RADAR 0x9954
2282#define AR5K_PHY_RADAR_ENABLE 0x00000001 2283#define AR5K_PHY_RADAR_ENABLE 0x00000001
2283#define AR5K_PHY_RADAR_DISABLE 0x00000000 2284#define AR5K_PHY_RADAR_DISABLE 0x00000000
2284#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold 2285#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold
2285 5-bits, units unknown {0..31} 2286 5-bits, units unknown {0..31}
2286 (? MHz ?) */ 2287 (? MHz ?) */
2287#define AR5K_PHY_RADAR_INBANDTHR_S 1 2288#define AR5K_PHY_RADAR_INBANDTHR_S 1
2288 2289
2289#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold 2290#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold
2290 6-bits, dBm range {0..63} 2291 6-bits, dBm range {0..63}
2291 in dBm units. */ 2292 in dBm units. */
2292#define AR5K_PHY_RADAR_PRSSI_THR_S 6 2293#define AR5K_PHY_RADAR_PRSSI_THR_S 6
2293 2294
2294#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold 2295#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold
2295 6-bits, dBm range {0..63} 2296 6-bits, dBm range {0..63}
2296 in dBm units. */ 2297 in dBm units. */
2297#define AR5K_PHY_RADAR_PHEIGHT_THR_S 12 2298#define AR5K_PHY_RADAR_PHEIGHT_THR_S 12
2298 2299
2299#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold. 2300#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold.
2300 6-bits, dBm range {0..63} 2301 6-bits, dBm range {0..63}
2301 in dBm units. */ 2302 in dBm units. */
2302#define AR5K_PHY_RADAR_RSSI_THR_S 18 2303#define AR5K_PHY_RADAR_RSSI_THR_S 18
@@ -2339,7 +2340,7 @@
2339#define AR5K_PHY_RESTART_DIV_GC_S 18 2340#define AR5K_PHY_RESTART_DIV_GC_S 18
2340 2341
2341/* 2342/*
2342 * RF Bus access request register (for synth-oly channel switching) 2343 * RF Bus access request register (for synth-only channel switching)
2343 */ 2344 */
2344#define AR5K_PHY_RFBUS_REQ 0x997C 2345#define AR5K_PHY_RFBUS_REQ 0x997C
2345#define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001 2346#define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001
@@ -2381,7 +2382,7 @@
2381 */ 2382 */
2382#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ 2383#define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */
2383#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) 2384#define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2))
2384#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ 2385#define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplifier Gain table base address */
2385#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) 2386#define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2))
2386 2387
2387/* 2388/*
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index 126a4eab35f3..0686c5d8d56e 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -25,7 +25,7 @@
25 25
26#include <asm/unaligned.h> 26#include <asm/unaligned.h>
27 27
28#include <linux/pci.h> /* To determine if a card is pci-e */ 28#include <linux/pci.h> /* To determine if a card is pci-e */
29#include <linux/log2.h> 29#include <linux/log2.h>
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include "ath5k.h" 31#include "ath5k.h"
@@ -142,10 +142,11 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
142 142
143 /* Set 32MHz USEC counter */ 143 /* Set 32MHz USEC counter */
144 if ((ah->ah_radio == AR5K_RF5112) || 144 if ((ah->ah_radio == AR5K_RF5112) ||
145 (ah->ah_radio == AR5K_RF5413) || 145 (ah->ah_radio == AR5K_RF2413) ||
146 (ah->ah_radio == AR5K_RF2316) || 146 (ah->ah_radio == AR5K_RF5413) ||
147 (ah->ah_radio == AR5K_RF2317)) 147 (ah->ah_radio == AR5K_RF2316) ||
148 /* Remain on 40MHz clock ? */ 148 (ah->ah_radio == AR5K_RF2317))
149 /* Remain on 40MHz clock ? */
149 sclock = 40 - 1; 150 sclock = 40 - 1;
150 else 151 else
151 sclock = 32 - 1; 152 sclock = 32 - 1;
@@ -213,7 +214,7 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
213 usec_reg = (usec | sclock | txlat | rxlat); 214 usec_reg = (usec | sclock | txlat | rxlat);
214 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC); 215 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
215 216
216 /* On 5112 set tx frane to tx data start delay */ 217 /* On 5112 set tx frame to tx data start delay */
217 if (ah->ah_radio == AR5K_RF5112) { 218 if (ah->ah_radio == AR5K_RF5112) {
218 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2, 219 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
219 AR5K_PHY_RF_CTL2_TXF2TXD_START, 220 AR5K_PHY_RF_CTL2_TXF2TXD_START,
@@ -233,7 +234,7 @@ static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
233static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable) 234static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
234{ 235{
235 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 236 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
236 u32 scal, spending; 237 u32 scal, spending, sclock;
237 238
238 /* Only set 32KHz settings if we have an external 239 /* Only set 32KHz settings if we have an external
239 * 32KHz crystal present */ 240 * 32KHz crystal present */
@@ -317,6 +318,15 @@ static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
317 318
318 /* Set up tsf increment on each cycle */ 319 /* Set up tsf increment on each cycle */
319 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1); 320 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
321
322 if ((ah->ah_radio == AR5K_RF5112) ||
323 (ah->ah_radio == AR5K_RF5413) ||
324 (ah->ah_radio == AR5K_RF2316) ||
325 (ah->ah_radio == AR5K_RF2317))
326 sclock = 40 - 1;
327 else
328 sclock = 32 - 1;
329 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);
320 } 330 }
321} 331}
322 332
@@ -375,20 +385,20 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
375static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags) 385static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
376{ 386{
377 u32 mask = flags ? flags : ~0U; 387 u32 mask = flags ? flags : ~0U;
378 volatile u32 *reg; 388 u32 __iomem *reg;
379 u32 regval; 389 u32 regval;
380 u32 val = 0; 390 u32 val = 0;
381 391
382 /* ah->ah_mac_srev is not available at this point yet */ 392 /* ah->ah_mac_srev is not available at this point yet */
383 if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) { 393 if (ah->devid >= AR5K_SREV_AR2315_R6) {
384 reg = (u32 *) AR5K_AR2315_RESET; 394 reg = (u32 __iomem *) AR5K_AR2315_RESET;
385 if (mask & AR5K_RESET_CTL_PCU) 395 if (mask & AR5K_RESET_CTL_PCU)
386 val |= AR5K_AR2315_RESET_WMAC; 396 val |= AR5K_AR2315_RESET_WMAC;
387 if (mask & AR5K_RESET_CTL_BASEBAND) 397 if (mask & AR5K_RESET_CTL_BASEBAND)
388 val |= AR5K_AR2315_RESET_BB_WARM; 398 val |= AR5K_AR2315_RESET_BB_WARM;
389 } else { 399 } else {
390 reg = (u32 *) AR5K_AR5312_RESET; 400 reg = (u32 __iomem *) AR5K_AR5312_RESET;
391 if (to_platform_device(ah->ah_sc->dev)->id == 0) { 401 if (to_platform_device(ah->dev)->id == 0) {
392 if (mask & AR5K_RESET_CTL_PCU) 402 if (mask & AR5K_RESET_CTL_PCU)
393 val |= AR5K_AR5312_RESET_WMAC0; 403 val |= AR5K_AR5312_RESET_WMAC0;
394 if (mask & AR5K_RESET_CTL_BASEBAND) 404 if (mask & AR5K_RESET_CTL_BASEBAND)
@@ -520,7 +530,7 @@ commit:
520 */ 530 */
521int ath5k_hw_on_hold(struct ath5k_hw *ah) 531int ath5k_hw_on_hold(struct ath5k_hw *ah)
522{ 532{
523 struct pci_dev *pdev = ah->ah_sc->pdev; 533 struct pci_dev *pdev = ah->pdev;
524 u32 bus_flags; 534 u32 bus_flags;
525 int ret; 535 int ret;
526 536
@@ -530,7 +540,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
530 /* Make sure device is awake */ 540 /* Make sure device is awake */
531 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 541 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
532 if (ret) { 542 if (ret) {
533 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 543 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
534 return ret; 544 return ret;
535 } 545 }
536 546
@@ -539,7 +549,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
539 * 549 *
540 * Note: putting PCI core on warm reset on PCI-E cards 550 * Note: putting PCI core on warm reset on PCI-E cards
541 * results card to hang and always return 0xffff... so 551 * results card to hang and always return 0xffff... so
542 * we ingore that flag for PCI-E cards. On PCI cards 552 * we ignore that flag for PCI-E cards. On PCI cards
543 * this flag gets cleared after 64 PCI clocks. 553 * this flag gets cleared after 64 PCI clocks.
544 */ 554 */
545 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI; 555 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
@@ -555,14 +565,14 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
555 } 565 }
556 566
557 if (ret) { 567 if (ret) {
558 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n"); 568 ATH5K_ERR(ah, "failed to put device on warm reset\n");
559 return -EIO; 569 return -EIO;
560 } 570 }
561 571
562 /* ...wakeup again!*/ 572 /* ...wakeup again!*/
563 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 573 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
564 if (ret) { 574 if (ret) {
565 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n"); 575 ATH5K_ERR(ah, "failed to put device on hold\n");
566 return ret; 576 return ret;
567 } 577 }
568 578
@@ -574,7 +584,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
574 */ 584 */
575int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial) 585int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
576{ 586{
577 struct pci_dev *pdev = ah->ah_sc->pdev; 587 struct pci_dev *pdev = ah->pdev;
578 u32 turbo, mode, clock, bus_flags; 588 u32 turbo, mode, clock, bus_flags;
579 int ret; 589 int ret;
580 590
@@ -586,7 +596,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
586 /* Wakeup the device */ 596 /* Wakeup the device */
587 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 597 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
588 if (ret) { 598 if (ret) {
589 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n"); 599 ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");
590 return ret; 600 return ret;
591 } 601 }
592 } 602 }
@@ -596,7 +606,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
596 * 606 *
597 * Note: putting PCI core on warm reset on PCI-E cards 607 * Note: putting PCI core on warm reset on PCI-E cards
598 * results card to hang and always return 0xffff... so 608 * results card to hang and always return 0xffff... so
599 * we ingore that flag for PCI-E cards. On PCI cards 609 * we ignore that flag for PCI-E cards. On PCI cards
600 * this flag gets cleared after 64 PCI clocks. 610 * this flag gets cleared after 64 PCI clocks.
601 */ 611 */
602 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI; 612 bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
@@ -616,18 +626,18 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
616 } 626 }
617 627
618 if (ret) { 628 if (ret) {
619 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n"); 629 ATH5K_ERR(ah, "failed to reset the MAC Chip\n");
620 return -EIO; 630 return -EIO;
621 } 631 }
622 632
623 /* ...wakeup again!...*/ 633 /* ...wakeup again!...*/
624 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); 634 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
625 if (ret) { 635 if (ret) {
626 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n"); 636 ATH5K_ERR(ah, "failed to resume the MAC Chip\n");
627 return ret; 637 return ret;
628 } 638 }
629 639
630 /* ...reset configuration regiter on Wisoc ... 640 /* ...reset configuration register on Wisoc ...
631 * ...clear reset control register and pull device out of 641 * ...clear reset control register and pull device out of
632 * warm reset on others */ 642 * warm reset on others */
633 if (ath5k_get_bus_type(ah) == ATH_AHB) 643 if (ath5k_get_bus_type(ah) == ATH_AHB)
@@ -636,7 +646,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
636 ret = ath5k_hw_nic_reset(ah, 0); 646 ret = ath5k_hw_nic_reset(ah, 0);
637 647
638 if (ret) { 648 if (ret) {
639 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n"); 649 ATH5K_ERR(ah, "failed to warm reset the MAC Chip\n");
640 return -EIO; 650 return -EIO;
641 } 651 }
642 652
@@ -677,7 +687,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
677 else 687 else
678 mode |= AR5K_PHY_MODE_MOD_DYN; 688 mode |= AR5K_PHY_MODE_MOD_DYN;
679 } else { 689 } else {
680 ATH5K_ERR(ah->ah_sc, 690 ATH5K_ERR(ah,
681 "invalid radio modulation mode\n"); 691 "invalid radio modulation mode\n");
682 return -EINVAL; 692 return -EINVAL;
683 } 693 }
@@ -693,18 +703,18 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
693 if (flags & CHANNEL_OFDM) 703 if (flags & CHANNEL_OFDM)
694 mode |= AR5K_PHY_MODE_MOD_OFDM; 704 mode |= AR5K_PHY_MODE_MOD_OFDM;
695 else { 705 else {
696 ATH5K_ERR(ah->ah_sc, 706 ATH5K_ERR(ah,
697 "invalid radio modulation mode\n"); 707 "invalid radio modulation mode\n");
698 return -EINVAL; 708 return -EINVAL;
699 } 709 }
700 } else { 710 } else {
701 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n"); 711 ATH5K_ERR(ah, "invalid radio frequency mode\n");
702 return -EINVAL; 712 return -EINVAL;
703 } 713 }
704 714
705 /*XXX: Can bwmode be used with dynamic mode ? 715 /*XXX: Can bwmode be used with dynamic mode ?
706 * (I don't think it supports 44MHz) */ 716 * (I don't think it supports 44MHz) */
707 /* On 2425 initvals TURBO_SHORT is not pressent */ 717 /* On 2425 initvals TURBO_SHORT is not present */
708 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) { 718 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
709 turbo = AR5K_PHY_TURBO_MODE | 719 turbo = AR5K_PHY_TURBO_MODE |
710 (ah->ah_radio == AR5K_RF2425) ? 0 : 720 (ah->ah_radio == AR5K_RF2425) ? 0 :
@@ -1066,7 +1076,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1066 /* RF Bus grant won't work if we have pending 1076 /* RF Bus grant won't work if we have pending
1067 * frames */ 1077 * frames */
1068 if (ret && fast) { 1078 if (ret && fast) {
1069 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET, 1079 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1070 "DMA didn't stop, falling back to normal reset\n"); 1080 "DMA didn't stop, falling back to normal reset\n");
1071 fast = 0; 1081 fast = 0;
1072 /* Non fatal, just continue with 1082 /* Non fatal, just continue with
@@ -1081,7 +1091,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1081 case CHANNEL_G: 1091 case CHANNEL_G:
1082 1092
1083 if (ah->ah_version <= AR5K_AR5211) { 1093 if (ah->ah_version <= AR5K_AR5211) {
1084 ATH5K_ERR(ah->ah_sc, 1094 ATH5K_ERR(ah,
1085 "G mode not available on 5210/5211"); 1095 "G mode not available on 5210/5211");
1086 return -EINVAL; 1096 return -EINVAL;
1087 } 1097 }
@@ -1091,7 +1101,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1091 case CHANNEL_B: 1101 case CHANNEL_B:
1092 1102
1093 if (ah->ah_version < AR5K_AR5211) { 1103 if (ah->ah_version < AR5K_AR5211) {
1094 ATH5K_ERR(ah->ah_sc, 1104 ATH5K_ERR(ah,
1095 "B mode not available on 5210"); 1105 "B mode not available on 5210");
1096 return -EINVAL; 1106 return -EINVAL;
1097 } 1107 }
@@ -1100,14 +1110,14 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1100 break; 1110 break;
1101 case CHANNEL_XR: 1111 case CHANNEL_XR:
1102 if (ah->ah_version == AR5K_AR5211) { 1112 if (ah->ah_version == AR5K_AR5211) {
1103 ATH5K_ERR(ah->ah_sc, 1113 ATH5K_ERR(ah,
1104 "XR mode not available on 5211"); 1114 "XR mode not available on 5211");
1105 return -EINVAL; 1115 return -EINVAL;
1106 } 1116 }
1107 mode = AR5K_MODE_XR; 1117 mode = AR5K_MODE_XR;
1108 break; 1118 break;
1109 default: 1119 default:
1110 ATH5K_ERR(ah->ah_sc, 1120 ATH5K_ERR(ah,
1111 "invalid channel: %d\n", channel->center_freq); 1121 "invalid channel: %d\n", channel->center_freq);
1112 return -EINVAL; 1122 return -EINVAL;
1113 } 1123 }
@@ -1119,13 +1129,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1119 if (fast) { 1129 if (fast) {
1120 ret = ath5k_hw_phy_init(ah, channel, mode, true); 1130 ret = ath5k_hw_phy_init(ah, channel, mode, true);
1121 if (ret) { 1131 if (ret) {
1122 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET, 1132 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1123 "fast chan change failed, falling back to normal reset\n"); 1133 "fast chan change failed, falling back to normal reset\n");
1124 /* Non fatal, can happen eg. 1134 /* Non fatal, can happen eg.
1125 * on mode change */ 1135 * on mode change */
1126 ret = 0; 1136 ret = 0;
1127 } else { 1137 } else {
1128 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET, 1138 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
1129 "fast chan change successful\n"); 1139 "fast chan change successful\n");
1130 return 0; 1140 return 0;
1131 } 1141 }
@@ -1258,7 +1268,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1258 */ 1268 */
1259 ret = ath5k_hw_phy_init(ah, channel, mode, false); 1269 ret = ath5k_hw_phy_init(ah, channel, mode, false);
1260 if (ret) { 1270 if (ret) {
1261 ATH5K_ERR(ah->ah_sc, 1271 ATH5K_ERR(ah,
1262 "failed to initialize PHY (%i) !\n", ret); 1272 "failed to initialize PHY (%i) !\n", ret);
1263 return ret; 1273 return ret;
1264 } 1274 }
@@ -1277,11 +1287,16 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1277 ath5k_hw_dma_init(ah); 1287 ath5k_hw_dma_init(ah);
1278 1288
1279 1289
1280 /* Enable 32KHz clock function for AR5212+ chips 1290 /*
1291 * Enable 32KHz clock function for AR5212+ chips
1281 * Set clocks to 32KHz operation and use an 1292 * Set clocks to 32KHz operation and use an
1282 * external 32KHz crystal when sleeping if one 1293 * external 32KHz crystal when sleeping if one
1283 * exists */ 1294 * exists.
1284 if (ah->ah_version == AR5K_AR5212 && 1295 * Disabled by default because it is also disabled in
1296 * other drivers and it is known to cause stability
1297 * issues on some devices
1298 */
1299 if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
1285 op_mode != NL80211_IFTYPE_AP) 1300 op_mode != NL80211_IFTYPE_AP)
1286 ath5k_hw_set_sleep_clock(ah, true); 1301 ath5k_hw_set_sleep_clock(ah, true);
1287 1302
diff --git a/drivers/net/wireless/ath/ath5k/rfbuffer.h b/drivers/net/wireless/ath/ath5k/rfbuffer.h
index 16b67e84906d..5d11c23b4297 100644
--- a/drivers/net/wireless/ath/ath5k/rfbuffer.h
+++ b/drivers/net/wireless/ath/ath5k/rfbuffer.h
@@ -254,7 +254,7 @@ static const struct ath5k_ini_rfbuffer rfb_5111[] = {
254 254
255/* RFX112 (Derby 1) */ 255/* RFX112 (Derby 1) */
256 256
257/* BANK 6 len pos col */ 257/* BANK 6 len pos col */
258#define AR5K_RF5112_OB_2GHZ { 3, 269, 0 } 258#define AR5K_RF5112_OB_2GHZ { 3, 269, 0 }
259#define AR5K_RF5112_DB_2GHZ { 3, 272, 0 } 259#define AR5K_RF5112_DB_2GHZ { 3, 272, 0 }
260 260
@@ -495,7 +495,7 @@ static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
495/* BANK 2 len pos col */ 495/* BANK 2 len pos col */
496#define AR5K_RF2413_RF_TURBO { 1, 1, 2 } 496#define AR5K_RF2413_RF_TURBO { 1, 1, 2 }
497 497
498/* BANK 6 len pos col */ 498/* BANK 6 len pos col */
499#define AR5K_RF2413_OB_2GHZ { 3, 168, 0 } 499#define AR5K_RF2413_OB_2GHZ { 3, 168, 0 }
500#define AR5K_RF2413_DB_2GHZ { 3, 165, 0 } 500#define AR5K_RF2413_DB_2GHZ { 3, 165, 0 }
501 501
diff --git a/drivers/net/wireless/ath/ath5k/rfgain.h b/drivers/net/wireless/ath/ath5k/rfgain.h
index 1354d8c392c8..ebfae052d89e 100644
--- a/drivers/net/wireless/ath/ath5k/rfgain.h
+++ b/drivers/net/wireless/ath/ath5k/rfgain.h
@@ -30,7 +30,7 @@ struct ath5k_ini_rfgain {
30 30
31/* Initial RF Gain settings for RF5111 */ 31/* Initial RF Gain settings for RF5111 */
32static const struct ath5k_ini_rfgain rfgain_5111[] = { 32static const struct ath5k_ini_rfgain rfgain_5111[] = {
33 /* 5Ghz 2Ghz */ 33 /* 5GHz 2GHz */
34 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } }, 34 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
35 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } }, 35 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
36 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } }, 36 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
@@ -99,7 +99,7 @@ static const struct ath5k_ini_rfgain rfgain_5111[] = {
99 99
100/* Initial RF Gain settings for RF5112 */ 100/* Initial RF Gain settings for RF5112 */
101static const struct ath5k_ini_rfgain rfgain_5112[] = { 101static const struct ath5k_ini_rfgain rfgain_5112[] = {
102 /* 5Ghz 2Ghz */ 102 /* 5GHz 2GHz */
103 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } }, 103 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
104 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } }, 104 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
105 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } }, 105 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
@@ -305,7 +305,7 @@ static const struct ath5k_ini_rfgain rfgain_2316[] = {
305 305
306/* Initial RF Gain settings for RF5413 */ 306/* Initial RF Gain settings for RF5413 */
307static const struct ath5k_ini_rfgain rfgain_5413[] = { 307static const struct ath5k_ini_rfgain rfgain_5413[] = {
308 /* 5Ghz 2Ghz */ 308 /* 5GHz 2GHz */
309 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } }, 309 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
310 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } }, 310 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
311 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } }, 311 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
@@ -452,7 +452,7 @@ static const struct ath5k_ini_rfgain rfgain_2425[] = {
452 452
453/* Check if our current measurement is inside our 453/* Check if our current measurement is inside our
454 * current variable attenuation window */ 454 * current variable attenuation window */
455#define AR5K_GAIN_CHECK_ADJUST(_g) \ 455#define AR5K_GAIN_CHECK_ADJUST(_g) \
456 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high) 456 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
457 457
458struct ath5k_gain_opt_step { 458struct ath5k_gain_opt_step {
diff --git a/drivers/net/wireless/ath/ath5k/rfkill.c b/drivers/net/wireless/ath/ath5k/rfkill.c
index 41a877b73fce..945fc9f21e76 100644
--- a/drivers/net/wireless/ath/ath5k/rfkill.c
+++ b/drivers/net/wireless/ath/ath5k/rfkill.c
@@ -36,86 +36,81 @@
36#include "base.h" 36#include "base.h"
37 37
38 38
39static inline void ath5k_rfkill_disable(struct ath5k_softc *sc) 39static inline void ath5k_rfkill_disable(struct ath5k_hw *ah)
40{ 40{
41 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "rfkill disable (gpio:%d polarity:%d)\n", 41 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "rfkill disable (gpio:%d polarity:%d)\n",
42 sc->rf_kill.gpio, sc->rf_kill.polarity); 42 ah->rf_kill.gpio, ah->rf_kill.polarity);
43 ath5k_hw_set_gpio_output(sc->ah, sc->rf_kill.gpio); 43 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio);
44 ath5k_hw_set_gpio(sc->ah, sc->rf_kill.gpio, !sc->rf_kill.polarity); 44 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, !ah->rf_kill.polarity);
45} 45}
46 46
47 47
48static inline void ath5k_rfkill_enable(struct ath5k_softc *sc) 48static inline void ath5k_rfkill_enable(struct ath5k_hw *ah)
49{ 49{
50 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "rfkill enable (gpio:%d polarity:%d)\n", 50 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "rfkill enable (gpio:%d polarity:%d)\n",
51 sc->rf_kill.gpio, sc->rf_kill.polarity); 51 ah->rf_kill.gpio, ah->rf_kill.polarity);
52 ath5k_hw_set_gpio_output(sc->ah, sc->rf_kill.gpio); 52 ath5k_hw_set_gpio_output(ah, ah->rf_kill.gpio);
53 ath5k_hw_set_gpio(sc->ah, sc->rf_kill.gpio, sc->rf_kill.polarity); 53 ath5k_hw_set_gpio(ah, ah->rf_kill.gpio, ah->rf_kill.polarity);
54} 54}
55 55
56static inline void ath5k_rfkill_set_intr(struct ath5k_softc *sc, bool enable) 56static inline void ath5k_rfkill_set_intr(struct ath5k_hw *ah, bool enable)
57{ 57{
58 struct ath5k_hw *ah = sc->ah;
59 u32 curval; 58 u32 curval;
60 59
61 ath5k_hw_set_gpio_input(ah, sc->rf_kill.gpio); 60 ath5k_hw_set_gpio_input(ah, ah->rf_kill.gpio);
62 curval = ath5k_hw_get_gpio(ah, sc->rf_kill.gpio); 61 curval = ath5k_hw_get_gpio(ah, ah->rf_kill.gpio);
63 ath5k_hw_set_gpio_intr(ah, sc->rf_kill.gpio, enable ? 62 ath5k_hw_set_gpio_intr(ah, ah->rf_kill.gpio, enable ?
64 !!curval : !curval); 63 !!curval : !curval);
65} 64}
66 65
67static bool 66static bool
68ath5k_is_rfkill_set(struct ath5k_softc *sc) 67ath5k_is_rfkill_set(struct ath5k_hw *ah)
69{ 68{
70 /* configuring GPIO for input for some reason disables rfkill */ 69 /* configuring GPIO for input for some reason disables rfkill */
71 /*ath5k_hw_set_gpio_input(sc->ah, sc->rf_kill.gpio);*/ 70 /*ath5k_hw_set_gpio_input(ah, ah->rf_kill.gpio);*/
72 return ath5k_hw_get_gpio(sc->ah, sc->rf_kill.gpio) == 71 return ath5k_hw_get_gpio(ah, ah->rf_kill.gpio) ==
73 sc->rf_kill.polarity; 72 ah->rf_kill.polarity;
74} 73}
75 74
76static void 75static void
77ath5k_tasklet_rfkill_toggle(unsigned long data) 76ath5k_tasklet_rfkill_toggle(unsigned long data)
78{ 77{
79 struct ath5k_softc *sc = (void *)data; 78 struct ath5k_hw *ah = (void *)data;
80 bool blocked; 79 bool blocked;
81 80
82 blocked = ath5k_is_rfkill_set(sc); 81 blocked = ath5k_is_rfkill_set(ah);
83 wiphy_rfkill_set_hw_state(sc->hw->wiphy, blocked); 82 wiphy_rfkill_set_hw_state(ah->hw->wiphy, blocked);
84} 83}
85 84
86 85
87void 86void
88ath5k_rfkill_hw_start(struct ath5k_hw *ah) 87ath5k_rfkill_hw_start(struct ath5k_hw *ah)
89{ 88{
90 struct ath5k_softc *sc = ah->ah_sc;
91
92 /* read rfkill GPIO configuration from EEPROM header */ 89 /* read rfkill GPIO configuration from EEPROM header */
93 sc->rf_kill.gpio = ah->ah_capabilities.cap_eeprom.ee_rfkill_pin; 90 ah->rf_kill.gpio = ah->ah_capabilities.cap_eeprom.ee_rfkill_pin;
94 sc->rf_kill.polarity = ah->ah_capabilities.cap_eeprom.ee_rfkill_pol; 91 ah->rf_kill.polarity = ah->ah_capabilities.cap_eeprom.ee_rfkill_pol;
95 92
96 tasklet_init(&sc->rf_kill.toggleq, ath5k_tasklet_rfkill_toggle, 93 tasklet_init(&ah->rf_kill.toggleq, ath5k_tasklet_rfkill_toggle,
97 (unsigned long)sc); 94 (unsigned long)ah);
98 95
99 ath5k_rfkill_disable(sc); 96 ath5k_rfkill_disable(ah);
100 97
101 /* enable interrupt for rfkill switch */ 98 /* enable interrupt for rfkill switch */
102 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) 99 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header))
103 ath5k_rfkill_set_intr(sc, true); 100 ath5k_rfkill_set_intr(ah, true);
104} 101}
105 102
106 103
107void 104void
108ath5k_rfkill_hw_stop(struct ath5k_hw *ah) 105ath5k_rfkill_hw_stop(struct ath5k_hw *ah)
109{ 106{
110 struct ath5k_softc *sc = ah->ah_sc;
111
112 /* disable interrupt for rfkill switch */ 107 /* disable interrupt for rfkill switch */
113 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) 108 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header))
114 ath5k_rfkill_set_intr(sc, false); 109 ath5k_rfkill_set_intr(ah, false);
115 110
116 tasklet_kill(&sc->rf_kill.toggleq); 111 tasklet_kill(&ah->rf_kill.toggleq);
117 112
118 /* enable RFKILL when stopping HW so Wifi LED is turned off */ 113 /* enable RFKILL when stopping HW so Wifi LED is turned off */
119 ath5k_rfkill_enable(sc); 114 ath5k_rfkill_enable(ah);
120} 115}
121 116
diff --git a/drivers/net/wireless/ath/ath5k/sysfs.c b/drivers/net/wireless/ath/ath5k/sysfs.c
index 929c68cdf8ab..0244a36ba958 100644
--- a/drivers/net/wireless/ath/ath5k/sysfs.c
+++ b/drivers/net/wireless/ath/ath5k/sysfs.c
@@ -10,19 +10,23 @@ static ssize_t ath5k_attr_show_##name(struct device *dev, \
10 struct device_attribute *attr, \ 10 struct device_attribute *attr, \
11 char *buf) \ 11 char *buf) \
12{ \ 12{ \
13 struct ath5k_softc *sc = dev_get_drvdata(dev); \ 13 struct ieee80211_hw *hw = dev_get_drvdata(dev); \
14 return snprintf(buf, PAGE_SIZE, "%d\n", get); \ 14 struct ath5k_hw *ah = hw->priv; \
15 return snprintf(buf, PAGE_SIZE, "%d\n", get); \
15} \ 16} \
16 \ 17 \
17static ssize_t ath5k_attr_store_##name(struct device *dev, \ 18static ssize_t ath5k_attr_store_##name(struct device *dev, \
18 struct device_attribute *attr, \ 19 struct device_attribute *attr, \
19 const char *buf, size_t count) \ 20 const char *buf, size_t count) \
20{ \ 21{ \
21 struct ath5k_softc *sc = dev_get_drvdata(dev); \ 22 struct ieee80211_hw *hw = dev_get_drvdata(dev); \
22 int val; \ 23 struct ath5k_hw *ah = hw->priv; \
24 int val, ret; \
23 \ 25 \
24 val = (int)simple_strtoul(buf, NULL, 10); \ 26 ret = kstrtoint(buf, 10, &val); \
25 set(sc->ah, val); \ 27 if (ret < 0) \
28 return ret; \
29 set(ah, val); \
26 return count; \ 30 return count; \
27} \ 31} \
28static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, \ 32static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, \
@@ -33,25 +37,26 @@ static ssize_t ath5k_attr_show_##name(struct device *dev, \
33 struct device_attribute *attr, \ 37 struct device_attribute *attr, \
34 char *buf) \ 38 char *buf) \
35{ \ 39{ \
36 struct ath5k_softc *sc = dev_get_drvdata(dev); \ 40 struct ieee80211_hw *hw = dev_get_drvdata(dev); \
37 return snprintf(buf, PAGE_SIZE, "%d\n", get); \ 41 struct ath5k_hw *ah = hw->priv; \
42 return snprintf(buf, PAGE_SIZE, "%d\n", get); \
38} \ 43} \
39static DEVICE_ATTR(name, S_IRUGO, ath5k_attr_show_##name, NULL) 44static DEVICE_ATTR(name, S_IRUGO, ath5k_attr_show_##name, NULL)
40 45
41/*** ANI ***/ 46/*** ANI ***/
42 47
43SIMPLE_SHOW_STORE(ani_mode, sc->ani_state.ani_mode, ath5k_ani_init); 48SIMPLE_SHOW_STORE(ani_mode, ah->ani_state.ani_mode, ath5k_ani_init);
44SIMPLE_SHOW_STORE(noise_immunity_level, sc->ani_state.noise_imm_level, 49SIMPLE_SHOW_STORE(noise_immunity_level, ah->ani_state.noise_imm_level,
45 ath5k_ani_set_noise_immunity_level); 50 ath5k_ani_set_noise_immunity_level);
46SIMPLE_SHOW_STORE(spur_level, sc->ani_state.spur_level, 51SIMPLE_SHOW_STORE(spur_level, ah->ani_state.spur_level,
47 ath5k_ani_set_spur_immunity_level); 52 ath5k_ani_set_spur_immunity_level);
48SIMPLE_SHOW_STORE(firstep_level, sc->ani_state.firstep_level, 53SIMPLE_SHOW_STORE(firstep_level, ah->ani_state.firstep_level,
49 ath5k_ani_set_firstep_level); 54 ath5k_ani_set_firstep_level);
50SIMPLE_SHOW_STORE(ofdm_weak_signal_detection, sc->ani_state.ofdm_weak_sig, 55SIMPLE_SHOW_STORE(ofdm_weak_signal_detection, ah->ani_state.ofdm_weak_sig,
51 ath5k_ani_set_ofdm_weak_signal_detection); 56 ath5k_ani_set_ofdm_weak_signal_detection);
52SIMPLE_SHOW_STORE(cck_weak_signal_detection, sc->ani_state.cck_weak_sig, 57SIMPLE_SHOW_STORE(cck_weak_signal_detection, ah->ani_state.cck_weak_sig,
53 ath5k_ani_set_cck_weak_signal_detection); 58 ath5k_ani_set_cck_weak_signal_detection);
54SIMPLE_SHOW(spur_level_max, sc->ani_state.max_spur_level); 59SIMPLE_SHOW(spur_level_max, ah->ani_state.max_spur_level);
55 60
56static ssize_t ath5k_attr_show_noise_immunity_level_max(struct device *dev, 61static ssize_t ath5k_attr_show_noise_immunity_level_max(struct device *dev,
57 struct device_attribute *attr, 62 struct device_attribute *attr,
@@ -93,14 +98,14 @@ static struct attribute_group ath5k_attribute_group_ani = {
93/*** register / unregister ***/ 98/*** register / unregister ***/
94 99
95int 100int
96ath5k_sysfs_register(struct ath5k_softc *sc) 101ath5k_sysfs_register(struct ath5k_hw *ah)
97{ 102{
98 struct device *dev = sc->dev; 103 struct device *dev = ah->dev;
99 int err; 104 int err;
100 105
101 err = sysfs_create_group(&dev->kobj, &ath5k_attribute_group_ani); 106 err = sysfs_create_group(&dev->kobj, &ath5k_attribute_group_ani);
102 if (err) { 107 if (err) {
103 ATH5K_ERR(sc, "failed to create sysfs group\n"); 108 ATH5K_ERR(ah, "failed to create sysfs group\n");
104 return err; 109 return err;
105 } 110 }
106 111
@@ -108,9 +113,9 @@ ath5k_sysfs_register(struct ath5k_softc *sc)
108} 113}
109 114
110void 115void
111ath5k_sysfs_unregister(struct ath5k_softc *sc) 116ath5k_sysfs_unregister(struct ath5k_hw *ah)
112{ 117{
113 struct device *dev = sc->dev; 118 struct device *dev = ah->dev;
114 119
115 sysfs_remove_group(&dev->kobj, &ath5k_attribute_group_ani); 120 sysfs_remove_group(&dev->kobj, &ath5k_attribute_group_ani);
116} 121}
diff --git a/drivers/net/wireless/ath/ath5k/trace.h b/drivers/net/wireless/ath/ath5k/trace.h
index 2de68adb6240..c741c871f4e9 100644
--- a/drivers/net/wireless/ath/ath5k/trace.h
+++ b/drivers/net/wireless/ath/ath5k/trace.h
@@ -12,22 +12,19 @@ static inline void trace_ ## name(proto) {}
12 12
13struct sk_buff; 13struct sk_buff;
14 14
15#define PRIV_ENTRY __field(struct ath5k_softc *, priv)
16#define PRIV_ASSIGN __entry->priv = priv
17
18#undef TRACE_SYSTEM 15#undef TRACE_SYSTEM
19#define TRACE_SYSTEM ath5k 16#define TRACE_SYSTEM ath5k
20 17
21TRACE_EVENT(ath5k_rx, 18TRACE_EVENT(ath5k_rx,
22 TP_PROTO(struct ath5k_softc *priv, struct sk_buff *skb), 19 TP_PROTO(struct ath5k_hw *priv, struct sk_buff *skb),
23 TP_ARGS(priv, skb), 20 TP_ARGS(priv, skb),
24 TP_STRUCT__entry( 21 TP_STRUCT__entry(
25 PRIV_ENTRY 22 __field(struct ath5k_hw *, priv)
26 __field(unsigned long, skbaddr) 23 __field(unsigned long, skbaddr)
27 __dynamic_array(u8, frame, skb->len) 24 __dynamic_array(u8, frame, skb->len)
28 ), 25 ),
29 TP_fast_assign( 26 TP_fast_assign(
30 PRIV_ASSIGN; 27 __entry->priv = priv;
31 __entry->skbaddr = (unsigned long) skb; 28 __entry->skbaddr = (unsigned long) skb;
32 memcpy(__get_dynamic_array(frame), skb->data, skb->len); 29 memcpy(__get_dynamic_array(frame), skb->data, skb->len);
33 ), 30 ),
@@ -37,20 +34,20 @@ TRACE_EVENT(ath5k_rx,
37); 34);
38 35
39TRACE_EVENT(ath5k_tx, 36TRACE_EVENT(ath5k_tx,
40 TP_PROTO(struct ath5k_softc *priv, struct sk_buff *skb, 37 TP_PROTO(struct ath5k_hw *priv, struct sk_buff *skb,
41 struct ath5k_txq *q), 38 struct ath5k_txq *q),
42 39
43 TP_ARGS(priv, skb, q), 40 TP_ARGS(priv, skb, q),
44 41
45 TP_STRUCT__entry( 42 TP_STRUCT__entry(
46 PRIV_ENTRY 43 __field(struct ath5k_hw *, priv)
47 __field(unsigned long, skbaddr) 44 __field(unsigned long, skbaddr)
48 __field(u8, qnum) 45 __field(u8, qnum)
49 __dynamic_array(u8, frame, skb->len) 46 __dynamic_array(u8, frame, skb->len)
50 ), 47 ),
51 48
52 TP_fast_assign( 49 TP_fast_assign(
53 PRIV_ASSIGN; 50 __entry->priv = priv;
54 __entry->skbaddr = (unsigned long) skb; 51 __entry->skbaddr = (unsigned long) skb;
55 __entry->qnum = (u8) q->qnum; 52 __entry->qnum = (u8) q->qnum;
56 memcpy(__get_dynamic_array(frame), skb->data, skb->len); 53 memcpy(__get_dynamic_array(frame), skb->data, skb->len);
@@ -63,13 +60,13 @@ TRACE_EVENT(ath5k_tx,
63); 60);
64 61
65TRACE_EVENT(ath5k_tx_complete, 62TRACE_EVENT(ath5k_tx_complete,
66 TP_PROTO(struct ath5k_softc *priv, struct sk_buff *skb, 63 TP_PROTO(struct ath5k_hw *priv, struct sk_buff *skb,
67 struct ath5k_txq *q, struct ath5k_tx_status *ts), 64 struct ath5k_txq *q, struct ath5k_tx_status *ts),
68 65
69 TP_ARGS(priv, skb, q, ts), 66 TP_ARGS(priv, skb, q, ts),
70 67
71 TP_STRUCT__entry( 68 TP_STRUCT__entry(
72 PRIV_ENTRY 69 __field(struct ath5k_hw *, priv)
73 __field(unsigned long, skbaddr) 70 __field(unsigned long, skbaddr)
74 __field(u8, qnum) 71 __field(u8, qnum)
75 __field(u8, ts_status) 72 __field(u8, ts_status)
@@ -78,7 +75,7 @@ TRACE_EVENT(ath5k_tx_complete,
78 ), 75 ),
79 76
80 TP_fast_assign( 77 TP_fast_assign(
81 PRIV_ASSIGN; 78 __entry->priv = priv;
82 __entry->skbaddr = (unsigned long) skb; 79 __entry->skbaddr = (unsigned long) skb;
83 __entry->qnum = (u8) q->qnum; 80 __entry->qnum = (u8) q->qnum;
84 __entry->ts_status = ts->ts_status; 81 __entry->ts_status = ts->ts_status;
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 5b49cd03bfdf..0b36fcf8a280 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -27,6 +27,10 @@ static const struct platform_device_id ath9k_platform_id_table[] = {
27 .driver_data = AR5416_AR9100_DEVID, 27 .driver_data = AR5416_AR9100_DEVID,
28 }, 28 },
29 { 29 {
30 .name = "ar933x_wmac",
31 .driver_data = AR9300_DEVID_AR9330,
32 },
33 {
30 .name = "ar934x_wmac", 34 .name = "ar934x_wmac",
31 .driver_data = AR9300_DEVID_AR9340, 35 .driver_data = AR9300_DEVID_AR9340,
32 }, 36 },
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index 441bb33f17ad..fac2c6da6ca4 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -627,6 +627,11 @@ static void ar5008_hw_init_bb(struct ath_hw *ah,
627 else 627 else
628 synthDelay /= 10; 628 synthDelay /= 10;
629 629
630 if (IS_CHAN_HALF_RATE(chan))
631 synthDelay *= 2;
632 else if (IS_CHAN_QUARTER_RATE(chan))
633 synthDelay *= 4;
634
630 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 635 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
631 636
632 udelay(synthDelay + BASE_ACTIVATE_DELAY); 637 udelay(synthDelay + BASE_ACTIVATE_DELAY);
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index f344cc2b3d59..9ff7c30573b8 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -499,45 +499,6 @@ void ar9002_hw_enable_async_fifo(struct ath_hw *ah)
499 } 499 }
500} 500}
501 501
502/*
503 * If Async FIFO is enabled, the following counters change as MAC now runs
504 * at 117 Mhz instead of 88/44MHz when async FIFO is disabled.
505 *
506 * The values below tested for ht40 2 chain.
507 * Overwrite the delay/timeouts initialized in process ini.
508 */
509void ar9002_hw_update_async_fifo(struct ath_hw *ah)
510{
511 if (AR_SREV_9287_13_OR_LATER(ah)) {
512 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
513 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
514 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
515 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
516 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
517 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
518
519 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
520 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
521
522 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
523 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
524 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
525 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
526 }
527}
528
529/*
530 * We don't enable WEP aggregation on mac80211 but we keep this
531 * around for HAL unification purposes.
532 */
533void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah)
534{
535 if (AR_SREV_9287_13_OR_LATER(ah)) {
536 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
537 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
538 }
539}
540
541/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ 502/* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */
542void ar9002_hw_attach_ops(struct ath_hw *ah) 503void ar9002_hw_attach_ops(struct ath_hw *ah)
543{ 504{
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
index 077e8a6983fa..45b262fe2c25 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -28,11 +28,6 @@ static void ar9002_hw_set_desc_link(void *ds, u32 ds_link)
28 ((struct ath_desc*) ds)->ds_link = ds_link; 28 ((struct ath_desc*) ds)->ds_link = ds_link;
29} 29}
30 30
31static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
32{
33 *ds_link = &((struct ath_desc *)ds)->ds_link;
34}
35
36static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 31static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
37{ 32{
38 u32 isr = 0; 33 u32 isr = 0;
@@ -437,7 +432,6 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
437 432
438 ops->rx_enable = ar9002_hw_rx_enable; 433 ops->rx_enable = ar9002_hw_rx_enable;
439 ops->set_desc_link = ar9002_hw_set_desc_link; 434 ops->set_desc_link = ar9002_hw_set_desc_link;
440 ops->get_desc_link = ar9002_hw_get_desc_link;
441 ops->get_isr = ar9002_hw_get_isr; 435 ops->get_isr = ar9002_hw_get_isr;
442 ops->fill_txdesc = ar9002_hw_fill_txdesc; 436 ops->fill_txdesc = ar9002_hw_fill_txdesc;
443 ops->proc_txdesc = ar9002_hw_proc_txdesc; 437 ops->proc_txdesc = ar9002_hw_proc_txdesc;
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
index 2fe0a34cbabc..3cbbb033fcea 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -111,7 +111,9 @@ static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
111 111
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { 112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
113 case 0: 113 case 0:
114 if ((freq % 20) == 0) 114 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
115 aModeRefSel = 0;
116 else if ((freq % 20) == 0)
115 aModeRefSel = 3; 117 aModeRefSel = 3;
116 else if ((freq % 10) == 0) 118 else if ((freq % 10) == 0)
117 aModeRefSel = 2; 119 aModeRefSel = 2;
@@ -129,8 +131,9 @@ static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
129 channelSel = CHANSEL_5G(freq); 131 channelSel = CHANSEL_5G(freq);
130 132
131 /* RefDivA setting */ 133 /* RefDivA setting */
132 REG_RMW_FIELD(ah, AR_AN_SYNTH9, 134 ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9,
133 AR_AN_SYNTH9_REFDIVA, refDivA); 135 AR_AN_SYNTH9_REFDIVA,
136 AR_AN_SYNTH9_REFDIVA_S, refDivA);
134 137
135 } 138 }
136 139
@@ -447,26 +450,27 @@ static void ar9002_olc_init(struct ath_hw *ah)
447static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah, 450static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
448 struct ath9k_channel *chan) 451 struct ath9k_channel *chan)
449{ 452{
453 int ref_div = 5;
454 int pll_div = 0x2c;
450 u32 pll; 455 u32 pll;
451 456
452 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); 457 if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) {
458 if (AR_SREV_9280_20(ah)) {
459 ref_div = 10;
460 pll_div = 0x50;
461 } else {
462 pll_div = 0x28;
463 }
464 }
465
466 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV);
467 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV);
453 468
454 if (chan && IS_CHAN_HALF_RATE(chan)) 469 if (chan && IS_CHAN_HALF_RATE(chan))
455 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); 470 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
456 else if (chan && IS_CHAN_QUARTER_RATE(chan)) 471 else if (chan && IS_CHAN_QUARTER_RATE(chan))
457 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); 472 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
458 473
459 if (chan && IS_CHAN_5GHZ(chan)) {
460 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
461 pll = 0x142c;
462 else if (AR_SREV_9280_20(ah))
463 pll = 0x2850;
464 else
465 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
466 } else {
467 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
468 }
469
470 return pll; 474 return pll;
471} 475}
472 476
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index e8ac70da5ac7..2339728a7306 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -653,8 +653,8 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
653 {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110}, 653 {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
654 {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, 654 {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
655 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18}, 655 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
656 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982}, 656 {0x0000a2d0, 0x00041981, 0x00041981, 0x00041981, 0x00041982},
657 {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a}, 657 {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
658 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, 658 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
659 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, 659 {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
660 {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000}, 660 {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
@@ -761,7 +761,7 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
761 {0x0000a3ec, 0x20202020}, 761 {0x0000a3ec, 0x20202020},
762 {0x0000a3f0, 0x00000000}, 762 {0x0000a3f0, 0x00000000},
763 {0x0000a3f4, 0x00000246}, 763 {0x0000a3f4, 0x00000246},
764 {0x0000a3f8, 0x0cdbd380}, 764 {0x0000a3f8, 0x0c9bd380},
765 {0x0000a3fc, 0x000f0f01}, 765 {0x0000a3fc, 0x000f0f01},
766 {0x0000a400, 0x8fa91f01}, 766 {0x0000a400, 0x8fa91f01},
767 {0x0000a404, 0x00000000}, 767 {0x0000a404, 0x00000000},
@@ -780,7 +780,7 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
780 {0x0000a43c, 0x00100000}, 780 {0x0000a43c, 0x00100000},
781 {0x0000a440, 0x00000000}, 781 {0x0000a440, 0x00000000},
782 {0x0000a444, 0x00000000}, 782 {0x0000a444, 0x00000000},
783 {0x0000a448, 0x06000080}, 783 {0x0000a448, 0x05000080},
784 {0x0000a44c, 0x00000001}, 784 {0x0000a44c, 0x00000001},
785 {0x0000a450, 0x00010000}, 785 {0x0000a450, 0x00010000},
786 {0x0000a458, 0x00000000}, 786 {0x0000a458, 0x00000000},
@@ -1500,8 +1500,6 @@ static const u32 ar9300_2p2_mac_core[][2] = {
1500 {0x0000816c, 0x00000000}, 1500 {0x0000816c, 0x00000000},
1501 {0x000081c0, 0x00000000}, 1501 {0x000081c0, 0x00000000},
1502 {0x000081c4, 0x33332210}, 1502 {0x000081c4, 0x33332210},
1503 {0x000081c8, 0x00000000},
1504 {0x000081cc, 0x00000000},
1505 {0x000081ec, 0x00000000}, 1503 {0x000081ec, 0x00000000},
1506 {0x000081f0, 0x00000000}, 1504 {0x000081f0, 0x00000000},
1507 {0x000081f4, 0x00000000}, 1505 {0x000081f4, 0x00000000},
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index ff8150e46f0e..d109c25417f4 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <asm/unaligned.h>
17#include "hw.h" 18#include "hw.h"
18#include "ar9003_phy.h" 19#include "ar9003_phy.h"
19#include "ar9003_eeprom.h" 20#include "ar9003_eeprom.h"
@@ -1461,7 +1462,7 @@ static const struct ar9300_eeprom ar9300_h112 = {
1461 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1462 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1462 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 1463 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1463 1464
1464 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, 1465 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1465 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1466 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1466 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 1467 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1467 1468
@@ -2616,7 +2617,7 @@ static const struct ar9300_eeprom ar9300_h116 = {
2616 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2617 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2617 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } }, 2618 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2618 2619
2619 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } }, 2620 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2620 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2621 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2621 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } }, 2622 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2622 2623
@@ -3006,11 +3007,11 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3006 3007
3007 switch (param) { 3008 switch (param) {
3008 case EEP_MAC_LSW: 3009 case EEP_MAC_LSW:
3009 return eep->macAddr[0] << 8 | eep->macAddr[1]; 3010 return get_unaligned_be16(eep->macAddr);
3010 case EEP_MAC_MID: 3011 case EEP_MAC_MID:
3011 return eep->macAddr[2] << 8 | eep->macAddr[3]; 3012 return get_unaligned_be16(eep->macAddr + 2);
3012 case EEP_MAC_MSW: 3013 case EEP_MAC_MSW:
3013 return eep->macAddr[4] << 8 | eep->macAddr[5]; 3014 return get_unaligned_be16(eep->macAddr + 4);
3014 case EEP_REG_0: 3015 case EEP_REG_0:
3015 return le16_to_cpu(pBase->regDmn[0]); 3016 return le16_to_cpu(pBase->regDmn[0]);
3016 case EEP_REG_1: 3017 case EEP_REG_1:
@@ -3038,7 +3039,7 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3038 case EEP_CHAIN_MASK_REDUCE: 3039 case EEP_CHAIN_MASK_REDUCE:
3039 return (pBase->miscConfiguration >> 0x3) & 0x1; 3040 return (pBase->miscConfiguration >> 0x3) & 0x1;
3040 case EEP_ANT_DIV_CTL1: 3041 case EEP_ANT_DIV_CTL1:
3041 return le32_to_cpu(eep->base_ext1.ant_div_control); 3042 return eep->base_ext1.ant_div_control;
3042 default: 3043 default:
3043 return 0; 3044 return 0;
3044 } 3045 }
@@ -3324,6 +3325,8 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3324 read = ar9300_read_eeprom; 3325 read = ar9300_read_eeprom;
3325 if (AR_SREV_9485(ah)) 3326 if (AR_SREV_9485(ah))
3326 cptr = AR9300_BASE_ADDR_4K; 3327 cptr = AR9300_BASE_ADDR_4K;
3328 else if (AR_SREV_9330(ah))
3329 cptr = AR9300_BASE_ADDR_512;
3327 else 3330 else
3328 cptr = AR9300_BASE_ADDR; 3331 cptr = AR9300_BASE_ADDR;
3329 ath_dbg(common, ATH_DBG_EEPROM, 3332 ath_dbg(common, ATH_DBG_EEPROM,
@@ -3378,8 +3381,7 @@ found:
3378 osize = length; 3381 osize = length;
3379 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); 3382 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3380 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length); 3383 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3381 mchecksum = word[COMP_HDR_LEN + osize] | 3384 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3382 (word[COMP_HDR_LEN + osize + 1] << 8);
3383 ath_dbg(common, ATH_DBG_EEPROM, 3385 ath_dbg(common, ATH_DBG_EEPROM,
3384 "checksum %x %x\n", checksum, mchecksum); 3386 "checksum %x %x\n", checksum, mchecksum);
3385 if (checksum == mchecksum) { 3387 if (checksum == mchecksum) {
@@ -3442,7 +3444,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3442{ 3444{
3443 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz); 3445 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3444 3446
3445 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) 3447 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3446 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); 3448 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3447 else { 3449 else {
3448 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); 3450 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
@@ -3523,7 +3525,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3523 } 3525 }
3524 } 3526 }
3525 3527
3526 if (AR_SREV_9485(ah)) { 3528 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3527 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); 3529 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3528 /* 3530 /*
3529 * main_lnaconf, alt_lnaconf, main_tb, alt_tb 3531 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
@@ -3710,7 +3712,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3710 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR); 3712 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3711 3713
3712 if (internal_regulator) { 3714 if (internal_regulator) {
3713 if (AR_SREV_9485(ah)) { 3715 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3714 int reg_pmu_set; 3716 int reg_pmu_set;
3715 3717
3716 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; 3718 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
@@ -3718,9 +3720,24 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3718 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) 3720 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3719 return; 3721 return;
3720 3722
3721 reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) | 3723 if (AR_SREV_9330(ah)) {
3722 (2 << 14) | (6 << 17) | (1 << 20) | 3724 if (ah->is_clk_25mhz) {
3723 (3 << 24) | (1 << 28); 3725 reg_pmu_set = (3 << 1) | (8 << 4) |
3726 (3 << 8) | (1 << 14) |
3727 (6 << 17) | (1 << 20) |
3728 (3 << 24);
3729 } else {
3730 reg_pmu_set = (4 << 1) | (7 << 4) |
3731 (3 << 8) | (1 << 14) |
3732 (6 << 17) | (1 << 20) |
3733 (3 << 24);
3734 }
3735 } else {
3736 reg_pmu_set = (5 << 1) | (7 << 4) |
3737 (1 << 8) | (2 << 14) |
3738 (6 << 17) | (1 << 20) |
3739 (3 << 24) | (1 << 28);
3740 }
3724 3741
3725 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set); 3742 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3726 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set)) 3743 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
@@ -3751,7 +3768,7 @@ static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3751 AR_RTC_REG_CONTROL1_SWREG_PROGRAM); 3768 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3752 } 3769 }
3753 } else { 3770 } else {
3754 if (AR_SREV_9485(ah)) { 3771 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3755 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0); 3772 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3756 while (REG_READ_FIELD(ah, AR_PHY_PMU2, 3773 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3757 AR_PHY_PMU2_PGM)) 3774 AR_PHY_PMU2_PGM))
@@ -3795,9 +3812,9 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3795 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan)); 3812 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3796 ar9003_hw_drive_strength_apply(ah); 3813 ar9003_hw_drive_strength_apply(ah);
3797 ar9003_hw_atten_apply(ah, chan); 3814 ar9003_hw_atten_apply(ah, chan);
3798 if (!AR_SREV_9340(ah)) 3815 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
3799 ar9003_hw_internal_regulator_apply(ah); 3816 ar9003_hw_internal_regulator_apply(ah);
3800 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) 3817 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3801 ar9003_hw_apply_tuning_caps(ah); 3818 ar9003_hw_apply_tuning_caps(ah);
3802} 3819}
3803 3820
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 392bf0f8ff16..8efdec247c02 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -19,6 +19,8 @@
19#include "ar9003_2p2_initvals.h" 19#include "ar9003_2p2_initvals.h"
20#include "ar9485_initvals.h" 20#include "ar9485_initvals.h"
21#include "ar9340_initvals.h" 21#include "ar9340_initvals.h"
22#include "ar9330_1p1_initvals.h"
23#include "ar9330_1p2_initvals.h"
22 24
23/* General hardware code for the AR9003 hadware family */ 25/* General hardware code for the AR9003 hadware family */
24 26
@@ -29,7 +31,113 @@
29 */ 31 */
30static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 32static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
31{ 33{
32 if (AR_SREV_9340(ah)) { 34 if (AR_SREV_9330_11(ah)) {
35 /* mac */
36 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
37 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
38 ar9331_1p1_mac_core,
39 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
40 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
41 ar9331_1p1_mac_postamble,
42 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
43
44 /* bb */
45 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
46 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
47 ar9331_1p1_baseband_core,
48 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
49 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
50 ar9331_1p1_baseband_postamble,
51 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
52
53 /* radio */
54 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
55 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
56 ar9331_1p1_radio_core,
57 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
58 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
59
60 /* soc */
61 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
62 ar9331_1p1_soc_preamble,
63 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
64 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
65 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
66 ar9331_1p1_soc_postamble,
67 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
68
69 /* rx/tx gain */
70 INIT_INI_ARRAY(&ah->iniModesRxGain,
71 ar9331_common_rx_gain_1p1,
72 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
73 INIT_INI_ARRAY(&ah->iniModesTxGain,
74 ar9331_modes_lowest_ob_db_tx_gain_1p1,
75 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
76 5);
77
78 /* additional clock settings */
79 if (ah->is_clk_25mhz)
80 INIT_INI_ARRAY(&ah->iniModesAdditional,
81 ar9331_1p1_xtal_25M,
82 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
83 else
84 INIT_INI_ARRAY(&ah->iniModesAdditional,
85 ar9331_1p1_xtal_40M,
86 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
87 } else if (AR_SREV_9330_12(ah)) {
88 /* mac */
89 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
90 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
91 ar9331_1p2_mac_core,
92 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
93 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
94 ar9331_1p2_mac_postamble,
95 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
96
97 /* bb */
98 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
99 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
100 ar9331_1p2_baseband_core,
101 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
102 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
103 ar9331_1p2_baseband_postamble,
104 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
105
106 /* radio */
107 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
108 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
109 ar9331_1p2_radio_core,
110 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
111 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
112
113 /* soc */
114 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
115 ar9331_1p2_soc_preamble,
116 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
117 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
118 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
119 ar9331_1p2_soc_postamble,
120 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
121
122 /* rx/tx gain */
123 INIT_INI_ARRAY(&ah->iniModesRxGain,
124 ar9331_common_rx_gain_1p2,
125 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
126 INIT_INI_ARRAY(&ah->iniModesTxGain,
127 ar9331_modes_lowest_ob_db_tx_gain_1p2,
128 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
129 5);
130
131 /* additional clock settings */
132 if (ah->is_clk_25mhz)
133 INIT_INI_ARRAY(&ah->iniModesAdditional,
134 ar9331_1p2_xtal_25M,
135 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
136 else
137 INIT_INI_ARRAY(&ah->iniModesAdditional,
138 ar9331_1p2_xtal_40M,
139 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
140 } else if (AR_SREV_9340(ah)) {
33 /* mac */ 141 /* mac */
34 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 142 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
35 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 143 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
@@ -220,7 +328,17 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
220 switch (ar9003_hw_get_tx_gain_idx(ah)) { 328 switch (ar9003_hw_get_tx_gain_idx(ah)) {
221 case 0: 329 case 0:
222 default: 330 default:
223 if (AR_SREV_9340(ah)) 331 if (AR_SREV_9330_12(ah))
332 INIT_INI_ARRAY(&ah->iniModesTxGain,
333 ar9331_modes_lowest_ob_db_tx_gain_1p2,
334 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
335 5);
336 else if (AR_SREV_9330_11(ah))
337 INIT_INI_ARRAY(&ah->iniModesTxGain,
338 ar9331_modes_lowest_ob_db_tx_gain_1p1,
339 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
340 5);
341 else if (AR_SREV_9340(ah))
224 INIT_INI_ARRAY(&ah->iniModesTxGain, 342 INIT_INI_ARRAY(&ah->iniModesTxGain,
225 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 343 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
226 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), 344 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
@@ -237,7 +355,17 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
237 5); 355 5);
238 break; 356 break;
239 case 1: 357 case 1:
240 if (AR_SREV_9340(ah)) 358 if (AR_SREV_9330_12(ah))
359 INIT_INI_ARRAY(&ah->iniModesTxGain,
360 ar9331_modes_high_ob_db_tx_gain_1p2,
361 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
362 5);
363 else if (AR_SREV_9330_11(ah))
364 INIT_INI_ARRAY(&ah->iniModesTxGain,
365 ar9331_modes_high_ob_db_tx_gain_1p1,
366 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
367 5);
368 else if (AR_SREV_9340(ah))
241 INIT_INI_ARRAY(&ah->iniModesTxGain, 369 INIT_INI_ARRAY(&ah->iniModesTxGain,
242 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 370 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
243 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), 371 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
@@ -254,7 +382,17 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
254 5); 382 5);
255 break; 383 break;
256 case 2: 384 case 2:
257 if (AR_SREV_9340(ah)) 385 if (AR_SREV_9330_12(ah))
386 INIT_INI_ARRAY(&ah->iniModesTxGain,
387 ar9331_modes_low_ob_db_tx_gain_1p2,
388 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
389 5);
390 else if (AR_SREV_9330_11(ah))
391 INIT_INI_ARRAY(&ah->iniModesTxGain,
392 ar9331_modes_low_ob_db_tx_gain_1p1,
393 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
394 5);
395 else if (AR_SREV_9340(ah))
258 INIT_INI_ARRAY(&ah->iniModesTxGain, 396 INIT_INI_ARRAY(&ah->iniModesTxGain,
259 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 397 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
260 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), 398 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
@@ -271,7 +409,17 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
271 5); 409 5);
272 break; 410 break;
273 case 3: 411 case 3:
274 if (AR_SREV_9340(ah)) 412 if (AR_SREV_9330_12(ah))
413 INIT_INI_ARRAY(&ah->iniModesTxGain,
414 ar9331_modes_high_power_tx_gain_1p2,
415 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
416 5);
417 else if (AR_SREV_9330_11(ah))
418 INIT_INI_ARRAY(&ah->iniModesTxGain,
419 ar9331_modes_high_power_tx_gain_1p1,
420 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
421 5);
422 else if (AR_SREV_9340(ah))
275 INIT_INI_ARRAY(&ah->iniModesTxGain, 423 INIT_INI_ARRAY(&ah->iniModesTxGain,
276 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 424 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
277 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0), 425 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
@@ -295,7 +443,17 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
295 switch (ar9003_hw_get_rx_gain_idx(ah)) { 443 switch (ar9003_hw_get_rx_gain_idx(ah)) {
296 case 0: 444 case 0:
297 default: 445 default:
298 if (AR_SREV_9340(ah)) 446 if (AR_SREV_9330_12(ah))
447 INIT_INI_ARRAY(&ah->iniModesRxGain,
448 ar9331_common_rx_gain_1p2,
449 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
450 2);
451 else if (AR_SREV_9330_11(ah))
452 INIT_INI_ARRAY(&ah->iniModesRxGain,
453 ar9331_common_rx_gain_1p1,
454 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
455 2);
456 else if (AR_SREV_9340(ah))
299 INIT_INI_ARRAY(&ah->iniModesRxGain, 457 INIT_INI_ARRAY(&ah->iniModesRxGain,
300 ar9340Common_rx_gain_table_1p0, 458 ar9340Common_rx_gain_table_1p0,
301 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0), 459 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
@@ -312,7 +470,17 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
312 2); 470 2);
313 break; 471 break;
314 case 1: 472 case 1:
315 if (AR_SREV_9340(ah)) 473 if (AR_SREV_9330_12(ah))
474 INIT_INI_ARRAY(&ah->iniModesRxGain,
475 ar9331_common_wo_xlna_rx_gain_1p2,
476 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
477 2);
478 else if (AR_SREV_9330_11(ah))
479 INIT_INI_ARRAY(&ah->iniModesRxGain,
480 ar9331_common_wo_xlna_rx_gain_1p1,
481 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
482 2);
483 else if (AR_SREV_9340(ah))
316 INIT_INI_ARRAY(&ah->iniModesRxGain, 484 INIT_INI_ARRAY(&ah->iniModesRxGain,
317 ar9340Common_wo_xlna_rx_gain_table_1p0, 485 ar9340Common_wo_xlna_rx_gain_table_1p0,
318 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0), 486 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 10d71f7d3fc2..8ff0b88a29b9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -43,13 +43,6 @@ static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
43 ads->ctl10 |= ar9003_calc_ptr_chksum(ads); 43 ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
44} 44}
45 45
46static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
47{
48 struct ar9003_txc *ads = ds;
49
50 *ds_link = &ads->link;
51}
52
53static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked) 46static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
54{ 47{
55 u32 isr = 0; 48 u32 isr = 0;
@@ -236,6 +229,7 @@ static void ar9003_hw_fill_txdesc(struct ath_hw *ah, void *ds, u32 seglen,
236static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, 229static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
237 struct ath_tx_status *ts) 230 struct ath_tx_status *ts)
238{ 231{
232 struct ar9003_txc *txc = (struct ar9003_txc *) ds;
239 struct ar9003_txs *ads; 233 struct ar9003_txs *ads;
240 u32 status; 234 u32 status;
241 235
@@ -245,7 +239,11 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
245 if ((status & AR_TxDone) == 0) 239 if ((status & AR_TxDone) == 0)
246 return -EINPROGRESS; 240 return -EINPROGRESS;
247 241
248 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size; 242 ts->qid = MS(ads->ds_info, AR_TxQcuNum);
243 if (!txc || (MS(txc->info, AR_TxQcuNum) == ts->qid))
244 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
245 else
246 return -ENOENT;
249 247
250 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || 248 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
251 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { 249 (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
@@ -261,7 +259,6 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
261 ts->ts_seqnum = MS(status, AR_SeqNum); 259 ts->ts_seqnum = MS(status, AR_SeqNum);
262 ts->tid = MS(status, AR_TxTid); 260 ts->tid = MS(status, AR_TxTid);
263 261
264 ts->qid = MS(ads->ds_info, AR_TxQcuNum);
265 ts->desc_id = MS(ads->status1, AR_TxDescId); 262 ts->desc_id = MS(ads->status1, AR_TxDescId);
266 ts->ts_tstamp = ads->status4; 263 ts->ts_tstamp = ads->status4;
267 ts->ts_status = 0; 264 ts->ts_status = 0;
@@ -498,7 +495,6 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
498 495
499 ops->rx_enable = ar9003_hw_rx_enable; 496 ops->rx_enable = ar9003_hw_rx_enable;
500 ops->set_desc_link = ar9003_hw_set_desc_link; 497 ops->set_desc_link = ar9003_hw_set_desc_link;
501 ops->get_desc_link = ar9003_hw_get_desc_link;
502 ops->get_isr = ar9003_hw_get_isr; 498 ops->get_isr = ar9003_hw_get_isr;
503 ops->fill_txdesc = ar9003_hw_fill_txdesc; 499 ops->fill_txdesc = ar9003_hw_fill_txdesc;
504 ops->proc_txdesc = ar9003_hw_proc_txdesc; 500 ops->proc_txdesc = ar9003_hw_proc_txdesc;
@@ -629,8 +625,7 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
629 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 625 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
630 else if (rxsp->status11 & AR_MichaelErr) 626 else if (rxsp->status11 & AR_MichaelErr)
631 rxs->rs_status |= ATH9K_RXERR_MIC; 627 rxs->rs_status |= ATH9K_RXERR_MIC;
632 628 else if (rxsp->status11 & AR_KeyMiss)
633 if (rxsp->status11 & AR_KeyMiss)
634 rxs->rs_status |= ATH9K_RXERR_DECRYPT; 629 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
635 } 630 }
636 631
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index e4d6a87ec538..f80d1d633980 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -21,6 +21,36 @@ void ar9003_paprd_enable(struct ath_hw *ah, bool val)
21{ 21{
22 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 22 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
23 struct ath9k_channel *chan = ah->curchan; 23 struct ath9k_channel *chan = ah->curchan;
24 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
25
26 /*
27 * 3 bits for modalHeader5G.papdRateMaskHt20
28 * is used for sub-band disabling of PAPRD.
29 * 5G band is divided into 3 sub-bands -- upper,
30 * middle, lower.
31 * if bit 30 of modalHeader5G.papdRateMaskHt20 is set
32 * -- disable PAPRD for upper band 5GHz
33 * if bit 29 of modalHeader5G.papdRateMaskHt20 is set
34 * -- disable PAPRD for middle band 5GHz
35 * if bit 28 of modalHeader5G.papdRateMaskHt20 is set
36 * -- disable PAPRD for lower band 5GHz
37 */
38
39 if (IS_CHAN_5GHZ(chan)) {
40 if (chan->channel >= UPPER_5G_SUB_BAND_START) {
41 if (le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20)
42 & BIT(30))
43 val = false;
44 } else if (chan->channel >= MID_5G_SUB_BAND_START) {
45 if (le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20)
46 & BIT(29))
47 val = false;
48 } else {
49 if (le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20)
50 & BIT(28))
51 val = false;
52 }
53 }
24 54
25 if (val) { 55 if (val) {
26 ah->paprd_table_write_done = true; 56 ah->paprd_table_write_done = true;
@@ -46,11 +76,10 @@ EXPORT_SYMBOL(ar9003_paprd_enable);
46 76
47static int ar9003_get_training_power_2g(struct ath_hw *ah) 77static int ar9003_get_training_power_2g(struct ath_hw *ah)
48{ 78{
49 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; 79 struct ath9k_channel *chan = ah->curchan;
50 struct ar9300_modal_eep_header *hdr = &eep->modalHeader2G;
51 unsigned int power, scale, delta; 80 unsigned int power, scale, delta;
52 81
53 scale = MS(le32_to_cpu(hdr->papdRateMaskHt20), AR9300_PAPRD_SCALE_1); 82 scale = ar9003_get_paprd_scale_factor(ah, chan);
54 power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5, 83 power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
55 AR_PHY_POWERTX_RATE5_POWERTXHT20_0); 84 AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
56 85
@@ -67,20 +96,10 @@ static int ar9003_get_training_power_2g(struct ath_hw *ah)
67static int ar9003_get_training_power_5g(struct ath_hw *ah) 96static int ar9003_get_training_power_5g(struct ath_hw *ah)
68{ 97{
69 struct ath_common *common = ath9k_hw_common(ah); 98 struct ath_common *common = ath9k_hw_common(ah);
70 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
71 struct ar9300_modal_eep_header *hdr = &eep->modalHeader5G;
72 struct ath9k_channel *chan = ah->curchan; 99 struct ath9k_channel *chan = ah->curchan;
73 unsigned int power, scale, delta; 100 unsigned int power, scale, delta;
74 101
75 if (chan->channel >= 5700) 102 scale = ar9003_get_paprd_scale_factor(ah, chan);
76 scale = MS(le32_to_cpu(hdr->papdRateMaskHt20),
77 AR9300_PAPRD_SCALE_1);
78 else if (chan->channel >= 5400)
79 scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
80 AR9300_PAPRD_SCALE_2);
81 else
82 scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
83 AR9300_PAPRD_SCALE_1);
84 103
85 if (IS_CHAN_HT40(chan)) 104 if (IS_CHAN_HT40(chan))
86 power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE8, 105 power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE8,
@@ -94,7 +113,23 @@ static int ar9003_get_training_power_5g(struct ath_hw *ah)
94 if (delta > scale) 113 if (delta > scale)
95 return -1; 114 return -1;
96 115
97 power += 2 * get_streams(common->tx_chainmask); 116 switch (get_streams(common->tx_chainmask)) {
117 case 1:
118 delta = 6;
119 break;
120 case 2:
121 delta = 4;
122 break;
123 case 3:
124 delta = 2;
125 break;
126 default:
127 delta = 0;
128 ath_dbg(common, ATH_DBG_CALIBRATE,
129 "Invalid tx-chainmask: %u\n", common->tx_chainmask);
130 }
131
132 power += delta;
98 return power; 133 return power;
99} 134}
100 135
@@ -119,15 +154,16 @@ static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
119 else 154 else
120 training_power = ar9003_get_training_power_5g(ah); 155 training_power = ar9003_get_training_power_5g(ah);
121 156
157 ath_dbg(common, ATH_DBG_CALIBRATE,
158 "Training power: %d, Target power: %d\n",
159 training_power, ah->paprd_target_power);
160
122 if (training_power < 0) { 161 if (training_power < 0) {
123 ath_dbg(common, ATH_DBG_CALIBRATE, 162 ath_dbg(common, ATH_DBG_CALIBRATE,
124 "PAPRD target power delta out of range"); 163 "PAPRD target power delta out of range");
125 return -ERANGE; 164 return -ERANGE;
126 } 165 }
127 ah->paprd_training_power = training_power; 166 ah->paprd_training_power = training_power;
128 ath_dbg(common, ATH_DBG_CALIBRATE,
129 "Training power: %d, Target power: %d\n",
130 ah->paprd_training_power, ah->paprd_target_power);
131 167
132 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, 168 REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
133 ah->paprd_ratemask); 169 ah->paprd_ratemask);
@@ -230,7 +266,7 @@ static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
230 memset(entry, 0, sizeof(ah->paprd_gain_table_entries)); 266 memset(entry, 0, sizeof(ah->paprd_gain_table_entries));
231 memset(index, 0, sizeof(ah->paprd_gain_table_index)); 267 memset(index, 0, sizeof(ah->paprd_gain_table_index));
232 268
233 for (i = 0; i < 32; i++) { 269 for (i = 0; i < PAPRD_GAIN_TABLE_ENTRIES; i++) {
234 entry[i] = REG_READ(ah, reg); 270 entry[i] = REG_READ(ah, reg);
235 index[i] = (entry[i] >> 24) & 0xff; 271 index[i] = (entry[i] >> 24) & 0xff;
236 reg += 4; 272 reg += 4;
@@ -240,13 +276,13 @@ static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
240static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain, 276static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
241 int target_power) 277 int target_power)
242{ 278{
243 int olpc_gain_delta = 0; 279 int olpc_gain_delta = 0, cl_gain_mod;
244 int alpha_therm, alpha_volt; 280 int alpha_therm, alpha_volt;
245 int therm_cal_value, volt_cal_value; 281 int therm_cal_value, volt_cal_value;
246 int therm_value, volt_value; 282 int therm_value, volt_value;
247 int thermal_gain_corr, voltage_gain_corr; 283 int thermal_gain_corr, voltage_gain_corr;
248 int desired_scale, desired_gain = 0; 284 int desired_scale, desired_gain = 0;
249 u32 reg; 285 u32 reg_olpc = 0, reg_cl_gain = 0;
250 286
251 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1, 287 REG_CLR_BIT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
252 AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE); 288 AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
@@ -265,15 +301,29 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
265 volt_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4, 301 volt_value = REG_READ_FIELD(ah, AR_PHY_BB_THERM_ADC_4,
266 AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE); 302 AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE);
267 303
268 if (chain == 0) 304 switch (chain) {
269 reg = AR_PHY_TPC_11_B0; 305 case 0:
270 else if (chain == 1) 306 reg_olpc = AR_PHY_TPC_11_B0;
271 reg = AR_PHY_TPC_11_B1; 307 reg_cl_gain = AR_PHY_CL_TAB_0;
272 else 308 break;
273 reg = AR_PHY_TPC_11_B2; 309 case 1:
310 reg_olpc = AR_PHY_TPC_11_B1;
311 reg_cl_gain = AR_PHY_CL_TAB_1;
312 break;
313 case 2:
314 reg_olpc = AR_PHY_TPC_11_B2;
315 reg_cl_gain = AR_PHY_CL_TAB_2;
316 break;
317 default:
318 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
319 "Invalid chainmask: %d\n", chain);
320 break;
321 }
274 322
275 olpc_gain_delta = REG_READ_FIELD(ah, reg, 323 olpc_gain_delta = REG_READ_FIELD(ah, reg_olpc,
276 AR_PHY_TPC_11_OLPC_GAIN_DELTA); 324 AR_PHY_TPC_11_OLPC_GAIN_DELTA);
325 cl_gain_mod = REG_READ_FIELD(ah, reg_cl_gain,
326 AR_PHY_CL_TAB_CL_GAIN_MOD);
277 327
278 if (olpc_gain_delta >= 128) 328 if (olpc_gain_delta >= 128)
279 olpc_gain_delta = olpc_gain_delta - 256; 329 olpc_gain_delta = olpc_gain_delta - 256;
@@ -283,7 +333,7 @@ static unsigned int ar9003_get_desired_gain(struct ath_hw *ah, int chain,
283 voltage_gain_corr = (alpha_volt * (volt_value - volt_cal_value) + 333 voltage_gain_corr = (alpha_volt * (volt_value - volt_cal_value) +
284 (128 / 2)) / 128; 334 (128 / 2)) / 128;
285 desired_gain = target_power - olpc_gain_delta - thermal_gain_corr - 335 desired_gain = target_power - olpc_gain_delta - thermal_gain_corr -
286 voltage_gain_corr + desired_scale; 336 voltage_gain_corr + desired_scale + cl_gain_mod;
287 337
288 return desired_gain; 338 return desired_gain;
289} 339}
@@ -721,7 +771,7 @@ int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
721 desired_gain = ar9003_get_desired_gain(ah, chain, train_power); 771 desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
722 772
723 gain_index = 0; 773 gain_index = 0;
724 for (i = 0; i < 32; i++) { 774 for (i = 0; i < PAPRD_GAIN_TABLE_ENTRIES; i++) {
725 if (ah->paprd_gain_table_index[i] >= desired_gain) 775 if (ah->paprd_gain_table_index[i] >= desired_gain)
726 break; 776 break;
727 gain_index++; 777 gain_index++;
@@ -795,7 +845,26 @@ EXPORT_SYMBOL(ar9003_paprd_init_table);
795 845
796bool ar9003_paprd_is_done(struct ath_hw *ah) 846bool ar9003_paprd_is_done(struct ath_hw *ah)
797{ 847{
798 return !!REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1, 848 int paprd_done, agc2_pwr;
849 paprd_done = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,
799 AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE); 850 AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);
851
852 if (paprd_done == 0x1) {
853 agc2_pwr = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,
854 AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR);
855
856 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
857 "AGC2_PWR = 0x%x training done = 0x%x\n",
858 agc2_pwr, paprd_done);
859 /*
860 * agc2_pwr range should not be less than 'IDEAL_AGC2_PWR_CHANGE'
861 * when the training is completely done, otherwise retraining is
862 * done to make sure the value is in ideal range
863 */
864 if (agc2_pwr <= PAPRD_IDEAL_AGC2_PWR_RANGE)
865 paprd_done = 0;
866 }
867
868 return !!paprd_done;
800} 869}
801EXPORT_SYMBOL(ar9003_paprd_is_done); 870EXPORT_SYMBOL(ar9003_paprd_is_done);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 892c48b15434..1baca8e4715d 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -75,7 +75,19 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
75 freq = centers.synth_center; 75 freq = centers.synth_center;
76 76
77 if (freq < 4800) { /* 2 GHz, fractional mode */ 77 if (freq < 4800) { /* 2 GHz, fractional mode */
78 if (AR_SREV_9485(ah)) { 78 if (AR_SREV_9330(ah)) {
79 u32 chan_frac;
80 u32 div;
81
82 if (ah->is_clk_25mhz)
83 div = 75;
84 else
85 div = 120;
86
87 channelSel = (freq * 4) / div;
88 chan_frac = (((freq * 4) % div) * 0x20000) / div;
89 channelSel = (channelSel << 17) | chan_frac;
90 } else if (AR_SREV_9485(ah)) {
79 u32 chan_frac; 91 u32 chan_frac;
80 92
81 /* 93 /*
@@ -104,7 +116,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
104 u32 chan_frac; 116 u32 chan_frac;
105 117
106 channelSel = (freq * 2) / 75; 118 channelSel = (freq * 2) / 75;
107 chan_frac = ((freq % 75) * 0x20000) / 75; 119 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
108 channelSel = (channelSel << 17) | chan_frac; 120 channelSel = (channelSel << 17) | chan_frac;
109 } else { 121 } else {
110 channelSel = CHANSEL_5G(freq); 122 channelSel = CHANSEL_5G(freq);
@@ -168,7 +180,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
168 * is out-of-band and can be ignored. 180 * is out-of-band and can be ignored.
169 */ 181 */
170 182
171 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) { 183 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) {
172 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, 184 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
173 IS_CHAN_2GHZ(chan)); 185 IS_CHAN_2GHZ(chan));
174 if (spur_fbin_ptr[0] == 0) /* No spur */ 186 if (spur_fbin_ptr[0] == 0) /* No spur */
@@ -193,7 +205,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
193 205
194 for (i = 0; i < max_spur_cnts; i++) { 206 for (i = 0; i < max_spur_cnts; i++) {
195 negative = 0; 207 negative = 0;
196 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) 208 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
197 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i], 209 cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
198 IS_CHAN_2GHZ(chan)) - synth_freq; 210 IS_CHAN_2GHZ(chan)) - synth_freq;
199 else 211 else
@@ -659,6 +671,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
659 REG_WRITE_ARRAY(&ah->iniModesAdditional, 671 REG_WRITE_ARRAY(&ah->iniModesAdditional,
660 modesIndex, regWrites); 672 modesIndex, regWrites);
661 673
674 if (AR_SREV_9300(ah))
675 REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites);
676
662 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) 677 if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
663 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites); 678 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
664 679
@@ -1074,7 +1089,10 @@ static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1074{ 1089{
1075 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; 1090 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1076 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; 1091 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1077 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; 1092 if (AR_SREV_9330(ah))
1093 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1094 else
1095 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1078 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; 1096 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1079 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; 1097 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1080 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; 1098 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
@@ -1196,8 +1214,17 @@ static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1196 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S; 1214 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1197 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >> 1215 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1198 AR_PHY_9485_ANT_FAST_DIV_BIAS_S; 1216 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
1199 antconf->lna1_lna2_delta = -9; 1217
1200 antconf->div_group = 2; 1218 if (AR_SREV_9330_11(ah)) {
1219 antconf->lna1_lna2_delta = -9;
1220 antconf->div_group = 1;
1221 } else if (AR_SREV_9485(ah)) {
1222 antconf->lna1_lna2_delta = -9;
1223 antconf->div_group = 2;
1224 } else {
1225 antconf->lna1_lna2_delta = -3;
1226 antconf->div_group = 0;
1227 }
1201} 1228}
1202 1229
1203static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 1230static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 443090d278e3..6de3f0bc18e6 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -332,6 +332,8 @@
332#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95 332#define AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ -95
333#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100 333#define AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ -100
334 334
335#define AR_PHY_CCA_NOM_VAL_9330_2GHZ -118
336
335/* 337/*
336 * AGC Field Definitions 338 * AGC Field Definitions
337 */ 339 */
@@ -623,11 +625,11 @@
623#define AR_PHY_65NM_CH2_RXTX1 0x16900 625#define AR_PHY_65NM_CH2_RXTX1 0x16900
624#define AR_PHY_65NM_CH2_RXTX2 0x16904 626#define AR_PHY_65NM_CH2_RXTX2 0x16904
625 627
626#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c) 628#define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : 0x16284)
627#define AR_CH0_TOP2_XPABIASLVL 0xf000 629#define AR_CH0_TOP2_XPABIASLVL 0xf000
628#define AR_CH0_TOP2_XPABIASLVL_S 12 630#define AR_CH0_TOP2_XPABIASLVL_S 12
629 631
630#define AR_CH0_XTAL (AR_SREV_9485(ah) ? 0x16290 : 0x16294) 632#define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : 0x16290)
631#define AR_CH0_XTAL_CAPINDAC 0x7f000000 633#define AR_CH0_XTAL_CAPINDAC 0x7f000000
632#define AR_CH0_XTAL_CAPINDAC_S 24 634#define AR_CH0_XTAL_CAPINDAC_S 24
633#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 635#define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
@@ -1119,6 +1121,9 @@
1119#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00 1121#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00
1120#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8 1122#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S 8
1121 1123
1124#define AR_PHY_CL_TAB_CL_GAIN_MOD 0x1f
1125#define AR_PHY_CL_TAB_CL_GAIN_MOD_S 0
1126
1122void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); 1127void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1123 1128
1124#endif /* AR9003_PHY_H */ 1129#endif /* AR9003_PHY_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
new file mode 100644
index 000000000000..f11d9b2677fd
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9330_1p1_initvals.h
@@ -0,0 +1,1147 @@
1/*
2 * Copyright (c) 2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef INITVALS_9330_1P1_H
18#define INITVALS_9330_1P1_H
19
20static const u32 ar9331_1p1_baseband_postamble[][5] = {
21 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
22 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
23 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
24 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
25 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
26 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
27 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
28 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
29 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
30 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
31 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
32 {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
33 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
34 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
35 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
36 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
37 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
38 {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
39 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
40 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
41 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
42 {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
43 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
44 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
45 {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
46 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
47 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
48 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
49 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
50 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
51 {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
52 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
53 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
54 {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
55 {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
56 {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
57 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
58 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
59 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
60 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
61 {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
62 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
63};
64
65static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p1[][5] = {
66 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
67 {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
68 {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
69 {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
70 {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
71 {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
72 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
73 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
74 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
75 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
76 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
77 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
78 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
79 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
80 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
81 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
82 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
83 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
84 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
85 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
86 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
87 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
88 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
89 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
90 {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
91 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
92 {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
93 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
94 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
95 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
96 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
97 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
98 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
99 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
100 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
101 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
102 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
103 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
104 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
105 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
106 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
107 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
108 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
109 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
110 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
111 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
112 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
113 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
114 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
115 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
116 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
117 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
118 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
119 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
120 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
121 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
122 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
123 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
124 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
125 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
126 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
127 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
128 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
129 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
130 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
131 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
132 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
133 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
134 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
135 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
136 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
137 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
138 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
139 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
140 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
141 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
142 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
143 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
144 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
145 {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
146 {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
147 {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
148 {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
149 {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
150 {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
151 {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
152 {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
153 {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
154 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
155};
156
157static const u32 ar9331_modes_high_ob_db_tx_gain_1p1[][5] = {
158 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
159 {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
160 {0x0000a2dc, 0xffaa9a52, 0xffaa9a52, 0xffaa9a52, 0xffaa9a52},
161 {0x0000a2e0, 0xffb31c84, 0xffb31c84, 0xffb31c84, 0xffb31c84},
162 {0x0000a2e4, 0xff43e000, 0xff43e000, 0xff43e000, 0xff43e000},
163 {0x0000a2e8, 0xfffc0000, 0xfffc0000, 0xfffc0000, 0xfffc0000},
164 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
165 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
166 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
167 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
168 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
169 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
170 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
171 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
172 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
173 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
174 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
175 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
176 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3d001620, 0x3d001620},
177 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x3f001621, 0x3f001621},
178 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x42001640, 0x42001640},
179 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x44001641, 0x44001641},
180 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x46001642, 0x46001642},
181 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x49001644, 0x49001644},
182 {0x0000a544, 0x6502feca, 0x6502feca, 0x4c001a81, 0x4c001a81},
183 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x4f001a83, 0x4f001a83},
184 {0x0000a54c, 0x7203feca, 0x7203feca, 0x52001c84, 0x52001c84},
185 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x55001ce3, 0x55001ce3},
186 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x59001ce5, 0x59001ce5},
187 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5d001ce9, 0x5d001ce9},
188 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x64001eec, 0x64001eec},
189 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x64001eec, 0x64001eec},
190 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x64001eec, 0x64001eec},
191 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
192 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
193 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
194 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
195 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
196 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x64001eec, 0x64001eec},
197 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
198 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
199 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
200 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
201 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
202 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
203 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
204 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
205 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
206 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
207 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
208 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
209 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
210 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
211 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
212 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
213 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
214 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
215 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
216 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
217 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
218 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
219 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
220 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
221 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
222 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
223 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
224 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
225 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
226 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
227 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
228 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
229 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
230 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
231 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
232 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
233 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
234 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
235 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
236 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
237 {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
238 {0x0000a624, 0x0280ca03, 0x0280ca03, 0x0280ca03, 0x0280ca03},
239 {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
240 {0x0000a62c, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
241 {0x0000a630, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
242 {0x0000a634, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
243 {0x0000a638, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
244 {0x0000a63c, 0x04015005, 0x04015005, 0x04015005, 0x04015005},
245};
246
247static const u32 ar9331_modes_low_ob_db_tx_gain_1p1[][5] = {
248 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
249 {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
250 {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
251 {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
252 {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
253 {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
254 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
255 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
256 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
257 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
258 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
259 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
260 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
261 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
262 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
263 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
264 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
265 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
266 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
267 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
268 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
269 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
270 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
271 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
272 {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
273 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
274 {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
275 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
276 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
277 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
278 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
279 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
280 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
281 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
282 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
283 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
284 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
285 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
286 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
287 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
288 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
289 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
290 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
291 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
292 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
293 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
294 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
295 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
296 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
297 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
298 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
299 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
300 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
301 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
302 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
303 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
304 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
305 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
306 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
307 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
308 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
309 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
310 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
311 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
312 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
313 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
314 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
315 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
316 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
317 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
318 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
319 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
320 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
321 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
322 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
323 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
324 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
325 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
326 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
327 {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
328 {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
329 {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
330 {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
331 {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
332 {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
333 {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
334 {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
335 {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
336 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
337};
338
339static const u32 ar9331_1p1_baseband_core_txfir_coeff_japan_2484[][2] = {
340 /* Addr allmodes */
341 {0x0000a398, 0x00000000},
342 {0x0000a39c, 0x6f7f0301},
343 {0x0000a3a0, 0xca9228ee},
344};
345
346static const u32 ar9331_1p1_xtal_25M[][2] = {
347 /* Addr allmodes */
348 {0x00007038, 0x000002f8},
349 {0x00008244, 0x0010f3d7},
350 {0x0000824c, 0x0001e7ae},
351 {0x0001609c, 0x0f508f29},
352};
353
354static const u32 ar9331_1p1_radio_core[][2] = {
355 /* Addr allmodes */
356 {0x00016000, 0x36db6db6},
357 {0x00016004, 0x6db6db40},
358 {0x00016008, 0x73800000},
359 {0x0001600c, 0x00000000},
360 {0x00016040, 0x7f80fff8},
361 {0x00016044, 0x03db62db},
362 {0x00016048, 0x6c924268},
363 {0x0001604c, 0x000f0278},
364 {0x00016050, 0x4db6db8c},
365 {0x00016054, 0x6db60000},
366 {0x00016080, 0x00080000},
367 {0x00016084, 0x0e48048c},
368 {0x00016088, 0x14214514},
369 {0x0001608c, 0x119f081c},
370 {0x00016090, 0x24926490},
371 {0x00016098, 0xd411eb84},
372 {0x000160a0, 0xc2108ffe},
373 {0x000160a4, 0x812fc370},
374 {0x000160a8, 0x423c8000},
375 {0x000160ac, 0x24651800},
376 {0x000160b0, 0x03284f3e},
377 {0x000160b4, 0x92480040},
378 {0x000160c0, 0x006db6db},
379 {0x000160c4, 0x0186db60},
380 {0x000160c8, 0x6db6db6c},
381 {0x000160cc, 0x6de6c300},
382 {0x000160d0, 0x14500820},
383 {0x00016100, 0x04cb0001},
384 {0x00016104, 0xfff80015},
385 {0x00016108, 0x00080010},
386 {0x0001610c, 0x00170000},
387 {0x00016140, 0x10804000},
388 {0x00016144, 0x01884080},
389 {0x00016148, 0x000080c0},
390 {0x00016280, 0x01000015},
391 {0x00016284, 0x14d20000},
392 {0x00016288, 0x00318000},
393 {0x0001628c, 0x50000000},
394 {0x00016290, 0x4b96210f},
395 {0x00016380, 0x00000000},
396 {0x00016384, 0x00000000},
397 {0x00016388, 0x00800700},
398 {0x0001638c, 0x00800700},
399 {0x00016390, 0x00800700},
400 {0x00016394, 0x00000000},
401 {0x00016398, 0x00000000},
402 {0x0001639c, 0x00000000},
403 {0x000163a0, 0x00000001},
404 {0x000163a4, 0x00000001},
405 {0x000163a8, 0x00000000},
406 {0x000163ac, 0x00000000},
407 {0x000163b0, 0x00000000},
408 {0x000163b4, 0x00000000},
409 {0x000163b8, 0x00000000},
410 {0x000163bc, 0x00000000},
411 {0x000163c0, 0x000000a0},
412 {0x000163c4, 0x000c0000},
413 {0x000163c8, 0x14021402},
414 {0x000163cc, 0x00001402},
415 {0x000163d0, 0x00000000},
416 {0x000163d4, 0x00000000},
417};
418
419static const u32 ar9331_1p1_soc_postamble[][5] = {
420 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
421 {0x00007010, 0x00000022, 0x00000022, 0x00000022, 0x00000022},
422};
423
424static const u32 ar9331_common_wo_xlna_rx_gain_1p1[][2] = {
425 /* Addr allmodes */
426 {0x0000a000, 0x00060005},
427 {0x0000a004, 0x00810080},
428 {0x0000a008, 0x00830082},
429 {0x0000a00c, 0x00850084},
430 {0x0000a010, 0x01820181},
431 {0x0000a014, 0x01840183},
432 {0x0000a018, 0x01880185},
433 {0x0000a01c, 0x018a0189},
434 {0x0000a020, 0x02850284},
435 {0x0000a024, 0x02890288},
436 {0x0000a028, 0x028b028a},
437 {0x0000a02c, 0x03850384},
438 {0x0000a030, 0x03890388},
439 {0x0000a034, 0x038b038a},
440 {0x0000a038, 0x038d038c},
441 {0x0000a03c, 0x03910390},
442 {0x0000a040, 0x03930392},
443 {0x0000a044, 0x03950394},
444 {0x0000a048, 0x00000396},
445 {0x0000a04c, 0x00000000},
446 {0x0000a050, 0x00000000},
447 {0x0000a054, 0x00000000},
448 {0x0000a058, 0x00000000},
449 {0x0000a05c, 0x00000000},
450 {0x0000a060, 0x00000000},
451 {0x0000a064, 0x00000000},
452 {0x0000a068, 0x00000000},
453 {0x0000a06c, 0x00000000},
454 {0x0000a070, 0x00000000},
455 {0x0000a074, 0x00000000},
456 {0x0000a078, 0x00000000},
457 {0x0000a07c, 0x00000000},
458 {0x0000a080, 0x28282828},
459 {0x0000a084, 0x28282828},
460 {0x0000a088, 0x28282828},
461 {0x0000a08c, 0x28282828},
462 {0x0000a090, 0x28282828},
463 {0x0000a094, 0x24242428},
464 {0x0000a098, 0x171e1e1e},
465 {0x0000a09c, 0x02020b0b},
466 {0x0000a0a0, 0x02020202},
467 {0x0000a0a4, 0x00000000},
468 {0x0000a0a8, 0x00000000},
469 {0x0000a0ac, 0x00000000},
470 {0x0000a0b0, 0x00000000},
471 {0x0000a0b4, 0x00000000},
472 {0x0000a0b8, 0x00000000},
473 {0x0000a0bc, 0x00000000},
474 {0x0000a0c0, 0x22072208},
475 {0x0000a0c4, 0x22052206},
476 {0x0000a0c8, 0x22032204},
477 {0x0000a0cc, 0x22012202},
478 {0x0000a0d0, 0x221f2200},
479 {0x0000a0d4, 0x221d221e},
480 {0x0000a0d8, 0x33023303},
481 {0x0000a0dc, 0x33003301},
482 {0x0000a0e0, 0x331e331f},
483 {0x0000a0e4, 0x4402331d},
484 {0x0000a0e8, 0x44004401},
485 {0x0000a0ec, 0x441e441f},
486 {0x0000a0f0, 0x55025503},
487 {0x0000a0f4, 0x55005501},
488 {0x0000a0f8, 0x551e551f},
489 {0x0000a0fc, 0x6602551d},
490 {0x0000a100, 0x66006601},
491 {0x0000a104, 0x661e661f},
492 {0x0000a108, 0x7703661d},
493 {0x0000a10c, 0x77017702},
494 {0x0000a110, 0x00007700},
495 {0x0000a114, 0x00000000},
496 {0x0000a118, 0x00000000},
497 {0x0000a11c, 0x00000000},
498 {0x0000a120, 0x00000000},
499 {0x0000a124, 0x00000000},
500 {0x0000a128, 0x00000000},
501 {0x0000a12c, 0x00000000},
502 {0x0000a130, 0x00000000},
503 {0x0000a134, 0x00000000},
504 {0x0000a138, 0x00000000},
505 {0x0000a13c, 0x00000000},
506 {0x0000a140, 0x001f0000},
507 {0x0000a144, 0x111f1100},
508 {0x0000a148, 0x111d111e},
509 {0x0000a14c, 0x111b111c},
510 {0x0000a150, 0x22032204},
511 {0x0000a154, 0x22012202},
512 {0x0000a158, 0x221f2200},
513 {0x0000a15c, 0x221d221e},
514 {0x0000a160, 0x33013302},
515 {0x0000a164, 0x331f3300},
516 {0x0000a168, 0x4402331e},
517 {0x0000a16c, 0x44004401},
518 {0x0000a170, 0x441e441f},
519 {0x0000a174, 0x55015502},
520 {0x0000a178, 0x551f5500},
521 {0x0000a17c, 0x6602551e},
522 {0x0000a180, 0x66006601},
523 {0x0000a184, 0x661e661f},
524 {0x0000a188, 0x7703661d},
525 {0x0000a18c, 0x77017702},
526 {0x0000a190, 0x00007700},
527 {0x0000a194, 0x00000000},
528 {0x0000a198, 0x00000000},
529 {0x0000a19c, 0x00000000},
530 {0x0000a1a0, 0x00000000},
531 {0x0000a1a4, 0x00000000},
532 {0x0000a1a8, 0x00000000},
533 {0x0000a1ac, 0x00000000},
534 {0x0000a1b0, 0x00000000},
535 {0x0000a1b4, 0x00000000},
536 {0x0000a1b8, 0x00000000},
537 {0x0000a1bc, 0x00000000},
538 {0x0000a1c0, 0x00000000},
539 {0x0000a1c4, 0x00000000},
540 {0x0000a1c8, 0x00000000},
541 {0x0000a1cc, 0x00000000},
542 {0x0000a1d0, 0x00000000},
543 {0x0000a1d4, 0x00000000},
544 {0x0000a1d8, 0x00000000},
545 {0x0000a1dc, 0x00000000},
546 {0x0000a1e0, 0x00000000},
547 {0x0000a1e4, 0x00000000},
548 {0x0000a1e8, 0x00000000},
549 {0x0000a1ec, 0x00000000},
550 {0x0000a1f0, 0x00000396},
551 {0x0000a1f4, 0x00000396},
552 {0x0000a1f8, 0x00000396},
553 {0x0000a1fc, 0x00000296},
554};
555
556static const u32 ar9331_1p1_baseband_core[][2] = {
557 /* Addr allmodes */
558 {0x00009800, 0xafe68e30},
559 {0x00009804, 0xfd14e000},
560 {0x00009808, 0x9c0a8f6b},
561 {0x0000980c, 0x04800000},
562 {0x00009814, 0x9280c00a},
563 {0x00009818, 0x00000000},
564 {0x0000981c, 0x00020028},
565 {0x00009834, 0x5f3ca3de},
566 {0x00009838, 0x0108ecff},
567 {0x0000983c, 0x14750600},
568 {0x00009880, 0x201fff00},
569 {0x00009884, 0x00001042},
570 {0x000098a4, 0x00200400},
571 {0x000098b0, 0x32840bbe},
572 {0x000098d0, 0x004b6a8e},
573 {0x000098d4, 0x00000820},
574 {0x000098dc, 0x00000000},
575 {0x000098f0, 0x00000000},
576 {0x000098f4, 0x00000000},
577 {0x00009c04, 0x00000000},
578 {0x00009c08, 0x03200000},
579 {0x00009c0c, 0x00000000},
580 {0x00009c10, 0x00000000},
581 {0x00009c14, 0x00046384},
582 {0x00009c18, 0x05b6b440},
583 {0x00009c1c, 0x00b6b440},
584 {0x00009d00, 0xc080a333},
585 {0x00009d04, 0x40206c10},
586 {0x00009d08, 0x009c4060},
587 {0x00009d0c, 0x1883800a},
588 {0x00009d10, 0x01834061},
589 {0x00009d14, 0x00c00400},
590 {0x00009d18, 0x00000000},
591 {0x00009e08, 0x0038233c},
592 {0x00009e24, 0x9927b515},
593 {0x00009e28, 0x12ef0200},
594 {0x00009e30, 0x06336f77},
595 {0x00009e34, 0x6af6532f},
596 {0x00009e38, 0x0cc80c00},
597 {0x00009e40, 0x0d261820},
598 {0x00009e4c, 0x00001004},
599 {0x00009e50, 0x00ff03f1},
600 {0x00009fc0, 0x803e4788},
601 {0x00009fc4, 0x0001efb5},
602 {0x00009fcc, 0x40000014},
603 {0x0000a20c, 0x00000000},
604 {0x0000a220, 0x00000000},
605 {0x0000a224, 0x00000000},
606 {0x0000a228, 0x10002310},
607 {0x0000a23c, 0x00000000},
608 {0x0000a244, 0x0c000000},
609 {0x0000a2a0, 0x00000001},
610 {0x0000a2c0, 0x00000001},
611 {0x0000a2c8, 0x00000000},
612 {0x0000a2cc, 0x18c43433},
613 {0x0000a2d4, 0x00000000},
614 {0x0000a2dc, 0x00000000},
615 {0x0000a2e0, 0x00000000},
616 {0x0000a2e4, 0x00000000},
617 {0x0000a2e8, 0x00000000},
618 {0x0000a2ec, 0x00000000},
619 {0x0000a2f0, 0x00000000},
620 {0x0000a2f4, 0x00000000},
621 {0x0000a2f8, 0x00000000},
622 {0x0000a344, 0x00000000},
623 {0x0000a34c, 0x00000000},
624 {0x0000a350, 0x0000a000},
625 {0x0000a364, 0x00000000},
626 {0x0000a370, 0x00000000},
627 {0x0000a390, 0x00000001},
628 {0x0000a394, 0x00000444},
629 {0x0000a398, 0x001f0e0f},
630 {0x0000a39c, 0x0075393f},
631 {0x0000a3a0, 0xb79f6427},
632 {0x0000a3a4, 0x00000000},
633 {0x0000a3a8, 0xaaaaaaaa},
634 {0x0000a3ac, 0x3c466478},
635 {0x0000a3c0, 0x20202020},
636 {0x0000a3c4, 0x22222220},
637 {0x0000a3c8, 0x20200020},
638 {0x0000a3cc, 0x20202020},
639 {0x0000a3d0, 0x20202020},
640 {0x0000a3d4, 0x20202020},
641 {0x0000a3d8, 0x20202020},
642 {0x0000a3dc, 0x20202020},
643 {0x0000a3e0, 0x20202020},
644 {0x0000a3e4, 0x20202020},
645 {0x0000a3e8, 0x20202020},
646 {0x0000a3ec, 0x20202020},
647 {0x0000a3f0, 0x00000000},
648 {0x0000a3f4, 0x00000006},
649 {0x0000a3f8, 0x0cdbd380},
650 {0x0000a3fc, 0x000f0f01},
651 {0x0000a400, 0x8fa91f01},
652 {0x0000a404, 0x00000000},
653 {0x0000a408, 0x0e79e5c6},
654 {0x0000a40c, 0x00820820},
655 {0x0000a414, 0x1ce739ce},
656 {0x0000a418, 0x2d001dce},
657 {0x0000a41c, 0x1ce739ce},
658 {0x0000a420, 0x000001ce},
659 {0x0000a424, 0x1ce739ce},
660 {0x0000a428, 0x000001ce},
661 {0x0000a42c, 0x1ce739ce},
662 {0x0000a430, 0x1ce739ce},
663 {0x0000a434, 0x00000000},
664 {0x0000a438, 0x00001801},
665 {0x0000a43c, 0x00000000},
666 {0x0000a440, 0x00000000},
667 {0x0000a444, 0x00000000},
668 {0x0000a448, 0x04000000},
669 {0x0000a44c, 0x00000001},
670 {0x0000a450, 0x00010000},
671 {0x0000a458, 0x00000000},
672 {0x0000a640, 0x00000000},
673 {0x0000a644, 0x3fad9d74},
674 {0x0000a648, 0x0048060a},
675 {0x0000a64c, 0x00003c37},
676 {0x0000a670, 0x03020100},
677 {0x0000a674, 0x09080504},
678 {0x0000a678, 0x0d0c0b0a},
679 {0x0000a67c, 0x13121110},
680 {0x0000a680, 0x31301514},
681 {0x0000a684, 0x35343332},
682 {0x0000a688, 0x00000036},
683 {0x0000a690, 0x00000838},
684 {0x0000a7c0, 0x00000000},
685 {0x0000a7c4, 0xfffffffc},
686 {0x0000a7c8, 0x00000000},
687 {0x0000a7cc, 0x00000000},
688 {0x0000a7d0, 0x00000000},
689 {0x0000a7d4, 0x00000004},
690 {0x0000a7dc, 0x00000001},
691};
692
693static const u32 ar9331_modes_high_power_tx_gain_1p1[][5] = {
694 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
695 {0x0000a2d8, 0x7999a83a, 0x7999a83a, 0x7999a83a, 0x7999a83a},
696 {0x0000a2dc, 0xffff2a52, 0xffff2a52, 0xffff2a52, 0xffff2a52},
697 {0x0000a2e0, 0xffffcc84, 0xffffcc84, 0xffffcc84, 0xffffcc84},
698 {0x0000a2e4, 0xfffff000, 0xfffff000, 0xfffff000, 0xfffff000},
699 {0x0000a2e8, 0xfffe0000, 0xfffe0000, 0xfffe0000, 0xfffe0000},
700 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d0, 0x000050d0},
701 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
702 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
703 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
704 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
705 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
706 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
707 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
708 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
709 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
710 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
711 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
712 {0x0000a52c, 0x41023e85, 0x41023e85, 0x2d000a20, 0x2d000a20},
713 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x31000a22, 0x31000a22},
714 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x35000a24, 0x35000a24},
715 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000a43, 0x38000a43},
716 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3b000e42, 0x3b000e42},
717 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x3f000e44, 0x3f000e44},
718 {0x0000a544, 0x6502feca, 0x6502feca, 0x42000e64, 0x42000e64},
719 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46000e66, 0x46000e66},
720 {0x0000a54c, 0x7203feca, 0x7203feca, 0x4a000ea6, 0x4a000ea6},
721 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4a000ea6, 0x4a000ea6},
722 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4a000ea6, 0x4a000ea6},
723 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x4a000ea6, 0x4a000ea6},
724 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x4a000ea6, 0x4a000ea6},
725 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x4a000ea6, 0x4a000ea6},
726 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x4a000ea6, 0x4a000ea6},
727 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
728 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
729 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
730 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
731 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
732 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x4a000ea6, 0x4a000ea6},
733 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
734 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
735 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
736 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
737 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
738 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
739 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
740 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
741 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
742 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
743 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
744 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
745 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
746 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
747 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
748 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
749 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
750 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
751 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
752 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
753 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
754 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
755 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
756 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
757 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
758 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
759 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
760 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
761 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
762 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
763 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
764 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
765 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
766 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
767 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
768 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
769 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
770 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
771 {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
772 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
773 {0x0000a620, 0x0280c802, 0x0280c802, 0x0280c802, 0x0280c802},
774 {0x0000a624, 0x03010a03, 0x03010a03, 0x03010a03, 0x03010a03},
775 {0x0000a628, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
776 {0x0000a62c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
777 {0x0000a630, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
778 {0x0000a634, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
779 {0x0000a638, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
780 {0x0000a63c, 0x03010c04, 0x03010c04, 0x03010c04, 0x03010c04},
781 {0x00016044, 0x034922db, 0x034922db, 0x034922db, 0x034922db},
782 {0x00016284, 0x14d3f000, 0x14d3f000, 0x14d3f000, 0x14d3f000},
783};
784
785static const u32 ar9331_1p1_mac_postamble[][5] = {
786 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
787 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
788 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
789 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
790 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
791 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
792 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
793 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
794 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
795};
796
797static const u32 ar9331_1p1_soc_preamble[][2] = {
798 /* Addr allmodes */
799 {0x00007020, 0x00000000},
800 {0x00007034, 0x00000002},
801 {0x00007038, 0x000002f8},
802};
803
804static const u32 ar9331_1p1_xtal_40M[][2] = {
805 /* Addr allmodes */
806 {0x00007038, 0x000004c2},
807 {0x00008244, 0x0010f400},
808 {0x0000824c, 0x0001e800},
809 {0x0001609c, 0x0b283f31},
810};
811
812static const u32 ar9331_1p1_mac_core[][2] = {
813 /* Addr allmodes */
814 {0x00000008, 0x00000000},
815 {0x00000030, 0x00020085},
816 {0x00000034, 0x00000005},
817 {0x00000040, 0x00000000},
818 {0x00000044, 0x00000000},
819 {0x00000048, 0x00000008},
820 {0x0000004c, 0x00000010},
821 {0x00000050, 0x00000000},
822 {0x00001040, 0x002ffc0f},
823 {0x00001044, 0x002ffc0f},
824 {0x00001048, 0x002ffc0f},
825 {0x0000104c, 0x002ffc0f},
826 {0x00001050, 0x002ffc0f},
827 {0x00001054, 0x002ffc0f},
828 {0x00001058, 0x002ffc0f},
829 {0x0000105c, 0x002ffc0f},
830 {0x00001060, 0x002ffc0f},
831 {0x00001064, 0x002ffc0f},
832 {0x000010f0, 0x00000100},
833 {0x00001270, 0x00000000},
834 {0x000012b0, 0x00000000},
835 {0x000012f0, 0x00000000},
836 {0x0000143c, 0x00000000},
837 {0x0000147c, 0x00000000},
838 {0x00008000, 0x00000000},
839 {0x00008004, 0x00000000},
840 {0x00008008, 0x00000000},
841 {0x0000800c, 0x00000000},
842 {0x00008018, 0x00000000},
843 {0x00008020, 0x00000000},
844 {0x00008038, 0x00000000},
845 {0x0000803c, 0x00000000},
846 {0x00008040, 0x00000000},
847 {0x00008044, 0x00000000},
848 {0x00008048, 0x00000000},
849 {0x0000804c, 0xffffffff},
850 {0x00008054, 0x00000000},
851 {0x00008058, 0x00000000},
852 {0x0000805c, 0x000fc78f},
853 {0x00008060, 0x0000000f},
854 {0x00008064, 0x00000000},
855 {0x00008070, 0x00000310},
856 {0x00008074, 0x00000020},
857 {0x00008078, 0x00000000},
858 {0x0000809c, 0x0000000f},
859 {0x000080a0, 0x00000000},
860 {0x000080a4, 0x02ff0000},
861 {0x000080a8, 0x0e070605},
862 {0x000080ac, 0x0000000d},
863 {0x000080b0, 0x00000000},
864 {0x000080b4, 0x00000000},
865 {0x000080b8, 0x00000000},
866 {0x000080bc, 0x00000000},
867 {0x000080c0, 0x2a800000},
868 {0x000080c4, 0x06900168},
869 {0x000080c8, 0x13881c20},
870 {0x000080cc, 0x01f40000},
871 {0x000080d0, 0x00252500},
872 {0x000080d4, 0x00a00000},
873 {0x000080d8, 0x00400000},
874 {0x000080dc, 0x00000000},
875 {0x000080e0, 0xffffffff},
876 {0x000080e4, 0x0000ffff},
877 {0x000080e8, 0x3f3f3f3f},
878 {0x000080ec, 0x00000000},
879 {0x000080f0, 0x00000000},
880 {0x000080f4, 0x00000000},
881 {0x000080fc, 0x00020000},
882 {0x00008100, 0x00000000},
883 {0x00008108, 0x00000052},
884 {0x0000810c, 0x00000000},
885 {0x00008110, 0x00000000},
886 {0x00008114, 0x000007ff},
887 {0x00008118, 0x000000aa},
888 {0x0000811c, 0x00003210},
889 {0x00008124, 0x00000000},
890 {0x00008128, 0x00000000},
891 {0x0000812c, 0x00000000},
892 {0x00008130, 0x00000000},
893 {0x00008134, 0x00000000},
894 {0x00008138, 0x00000000},
895 {0x0000813c, 0x0000ffff},
896 {0x00008144, 0xffffffff},
897 {0x00008168, 0x00000000},
898 {0x0000816c, 0x00000000},
899 {0x00008170, 0x18486200},
900 {0x00008174, 0x33332210},
901 {0x00008178, 0x00000000},
902 {0x0000817c, 0x00020000},
903 {0x000081c0, 0x00000000},
904 {0x000081c4, 0x33332210},
905 {0x000081c8, 0x00000000},
906 {0x000081cc, 0x00000000},
907 {0x000081d4, 0x00000000},
908 {0x000081ec, 0x00000000},
909 {0x000081f0, 0x00000000},
910 {0x000081f4, 0x00000000},
911 {0x000081f8, 0x00000000},
912 {0x000081fc, 0x00000000},
913 {0x00008240, 0x00100000},
914 {0x00008248, 0x00000800},
915 {0x00008250, 0x00000000},
916 {0x00008254, 0x00000000},
917 {0x00008258, 0x00000000},
918 {0x0000825c, 0x40000000},
919 {0x00008260, 0x00080922},
920 {0x00008264, 0x9d400010},
921 {0x00008268, 0xffffffff},
922 {0x0000826c, 0x0000ffff},
923 {0x00008270, 0x00000000},
924 {0x00008274, 0x40000000},
925 {0x00008278, 0x003e4180},
926 {0x0000827c, 0x00000004},
927 {0x00008284, 0x0000002c},
928 {0x00008288, 0x0000002c},
929 {0x0000828c, 0x000000ff},
930 {0x00008294, 0x00000000},
931 {0x00008298, 0x00000000},
932 {0x0000829c, 0x00000000},
933 {0x00008300, 0x00000140},
934 {0x00008314, 0x00000000},
935 {0x0000831c, 0x0000010d},
936 {0x00008328, 0x00000000},
937 {0x0000832c, 0x00000007},
938 {0x00008330, 0x00000302},
939 {0x00008334, 0x00000700},
940 {0x00008338, 0x00ff0000},
941 {0x0000833c, 0x02400000},
942 {0x00008340, 0x000107ff},
943 {0x00008344, 0xaa48105b},
944 {0x00008348, 0x008f0000},
945 {0x0000835c, 0x00000000},
946 {0x00008360, 0xffffffff},
947 {0x00008364, 0xffffffff},
948 {0x00008368, 0x00000000},
949 {0x00008370, 0x00000000},
950 {0x00008374, 0x000000ff},
951 {0x00008378, 0x00000000},
952 {0x0000837c, 0x00000000},
953 {0x00008380, 0xffffffff},
954 {0x00008384, 0xffffffff},
955 {0x00008390, 0xffffffff},
956 {0x00008394, 0xffffffff},
957 {0x00008398, 0x00000000},
958 {0x0000839c, 0x00000000},
959 {0x000083a0, 0x00000000},
960 {0x000083a4, 0x0000fa14},
961 {0x000083a8, 0x000f0c00},
962 {0x000083ac, 0x33332210},
963 {0x000083b0, 0x33332210},
964 {0x000083b4, 0x33332210},
965 {0x000083b8, 0x33332210},
966 {0x000083bc, 0x00000000},
967 {0x000083c0, 0x00000000},
968 {0x000083c4, 0x00000000},
969 {0x000083c8, 0x00000000},
970 {0x000083cc, 0x00000200},
971 {0x000083d0, 0x000301ff},
972};
973
974static const u32 ar9331_common_rx_gain_1p1[][2] = {
975 /* Addr allmodes */
976 {0x0000a000, 0x00010000},
977 {0x0000a004, 0x00030002},
978 {0x0000a008, 0x00050004},
979 {0x0000a00c, 0x00810080},
980 {0x0000a010, 0x00830082},
981 {0x0000a014, 0x01810180},
982 {0x0000a018, 0x01830182},
983 {0x0000a01c, 0x01850184},
984 {0x0000a020, 0x01890188},
985 {0x0000a024, 0x018b018a},
986 {0x0000a028, 0x018d018c},
987 {0x0000a02c, 0x01910190},
988 {0x0000a030, 0x01930192},
989 {0x0000a034, 0x01950194},
990 {0x0000a038, 0x038a0196},
991 {0x0000a03c, 0x038c038b},
992 {0x0000a040, 0x0390038d},
993 {0x0000a044, 0x03920391},
994 {0x0000a048, 0x03940393},
995 {0x0000a04c, 0x03960395},
996 {0x0000a050, 0x00000000},
997 {0x0000a054, 0x00000000},
998 {0x0000a058, 0x00000000},
999 {0x0000a05c, 0x00000000},
1000 {0x0000a060, 0x00000000},
1001 {0x0000a064, 0x00000000},
1002 {0x0000a068, 0x00000000},
1003 {0x0000a06c, 0x00000000},
1004 {0x0000a070, 0x00000000},
1005 {0x0000a074, 0x00000000},
1006 {0x0000a078, 0x00000000},
1007 {0x0000a07c, 0x00000000},
1008 {0x0000a080, 0x22222229},
1009 {0x0000a084, 0x1d1d1d1d},
1010 {0x0000a088, 0x1d1d1d1d},
1011 {0x0000a08c, 0x1d1d1d1d},
1012 {0x0000a090, 0x171d1d1d},
1013 {0x0000a094, 0x11111717},
1014 {0x0000a098, 0x00030311},
1015 {0x0000a09c, 0x00000000},
1016 {0x0000a0a0, 0x00000000},
1017 {0x0000a0a4, 0x00000000},
1018 {0x0000a0a8, 0x00000000},
1019 {0x0000a0ac, 0x00000000},
1020 {0x0000a0b0, 0x00000000},
1021 {0x0000a0b4, 0x00000000},
1022 {0x0000a0b8, 0x00000000},
1023 {0x0000a0bc, 0x00000000},
1024 {0x0000a0c0, 0x001f0000},
1025 {0x0000a0c4, 0x01000101},
1026 {0x0000a0c8, 0x011e011f},
1027 {0x0000a0cc, 0x011c011d},
1028 {0x0000a0d0, 0x02030204},
1029 {0x0000a0d4, 0x02010202},
1030 {0x0000a0d8, 0x021f0200},
1031 {0x0000a0dc, 0x0302021e},
1032 {0x0000a0e0, 0x03000301},
1033 {0x0000a0e4, 0x031e031f},
1034 {0x0000a0e8, 0x0402031d},
1035 {0x0000a0ec, 0x04000401},
1036 {0x0000a0f0, 0x041e041f},
1037 {0x0000a0f4, 0x0502041d},
1038 {0x0000a0f8, 0x05000501},
1039 {0x0000a0fc, 0x051e051f},
1040 {0x0000a100, 0x06010602},
1041 {0x0000a104, 0x061f0600},
1042 {0x0000a108, 0x061d061e},
1043 {0x0000a10c, 0x07020703},
1044 {0x0000a110, 0x07000701},
1045 {0x0000a114, 0x00000000},
1046 {0x0000a118, 0x00000000},
1047 {0x0000a11c, 0x00000000},
1048 {0x0000a120, 0x00000000},
1049 {0x0000a124, 0x00000000},
1050 {0x0000a128, 0x00000000},
1051 {0x0000a12c, 0x00000000},
1052 {0x0000a130, 0x00000000},
1053 {0x0000a134, 0x00000000},
1054 {0x0000a138, 0x00000000},
1055 {0x0000a13c, 0x00000000},
1056 {0x0000a140, 0x001f0000},
1057 {0x0000a144, 0x01000101},
1058 {0x0000a148, 0x011e011f},
1059 {0x0000a14c, 0x011c011d},
1060 {0x0000a150, 0x02030204},
1061 {0x0000a154, 0x02010202},
1062 {0x0000a158, 0x021f0200},
1063 {0x0000a15c, 0x0302021e},
1064 {0x0000a160, 0x03000301},
1065 {0x0000a164, 0x031e031f},
1066 {0x0000a168, 0x0402031d},
1067 {0x0000a16c, 0x04000401},
1068 {0x0000a170, 0x041e041f},
1069 {0x0000a174, 0x0502041d},
1070 {0x0000a178, 0x05000501},
1071 {0x0000a17c, 0x051e051f},
1072 {0x0000a180, 0x06010602},
1073 {0x0000a184, 0x061f0600},
1074 {0x0000a188, 0x061d061e},
1075 {0x0000a18c, 0x07020703},
1076 {0x0000a190, 0x07000701},
1077 {0x0000a194, 0x00000000},
1078 {0x0000a198, 0x00000000},
1079 {0x0000a19c, 0x00000000},
1080 {0x0000a1a0, 0x00000000},
1081 {0x0000a1a4, 0x00000000},
1082 {0x0000a1a8, 0x00000000},
1083 {0x0000a1ac, 0x00000000},
1084 {0x0000a1b0, 0x00000000},
1085 {0x0000a1b4, 0x00000000},
1086 {0x0000a1b8, 0x00000000},
1087 {0x0000a1bc, 0x00000000},
1088 {0x0000a1c0, 0x00000000},
1089 {0x0000a1c4, 0x00000000},
1090 {0x0000a1c8, 0x00000000},
1091 {0x0000a1cc, 0x00000000},
1092 {0x0000a1d0, 0x00000000},
1093 {0x0000a1d4, 0x00000000},
1094 {0x0000a1d8, 0x00000000},
1095 {0x0000a1dc, 0x00000000},
1096 {0x0000a1e0, 0x00000000},
1097 {0x0000a1e4, 0x00000000},
1098 {0x0000a1e8, 0x00000000},
1099 {0x0000a1ec, 0x00000000},
1100 {0x0000a1f0, 0x00000396},
1101 {0x0000a1f4, 0x00000396},
1102 {0x0000a1f8, 0x00000396},
1103 {0x0000a1fc, 0x00000196},
1104};
1105
1106static const u32 ar9331_common_tx_gain_offset1_1[][1] = {
1107 {0},
1108 {3},
1109 {0},
1110 {0},
1111};
1112
1113static const u32 ar9331_1p1_chansel_xtal_25M[] = {
1114 0x0101479e,
1115 0x0101d027,
1116 0x010258af,
1117 0x0102e138,
1118 0x010369c0,
1119 0x0103f249,
1120 0x01047ad1,
1121 0x0105035a,
1122 0x01058be2,
1123 0x0106146b,
1124 0x01069cf3,
1125 0x0107257c,
1126 0x0107ae04,
1127 0x0108f5b2,
1128};
1129
1130static const u32 ar9331_1p1_chansel_xtal_40M[] = {
1131 0x00a0ccbe,
1132 0x00a12213,
1133 0x00a17769,
1134 0x00a1ccbe,
1135 0x00a22213,
1136 0x00a27769,
1137 0x00a2ccbe,
1138 0x00a32213,
1139 0x00a37769,
1140 0x00a3ccbe,
1141 0x00a42213,
1142 0x00a47769,
1143 0x00a4ccbe,
1144 0x00a5998b,
1145};
1146
1147#endif /* INITVALS_9330_1P1_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
new file mode 100644
index 000000000000..0e6ca0834b34
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9330_1p2_initvals.h
@@ -0,0 +1,1080 @@
1/*
2 * Copyright (c) 2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef INITVALS_9330_1P2_H
18#define INITVALS_9330_1P2_H
19
20static const u32 ar9331_modes_lowest_ob_db_tx_gain_1p2[][5] = {
21 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
22 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
23 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
24 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
25 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
26 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
27 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
28 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
29 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
30 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
31 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
32 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
33 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
34 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
35 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
36 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
37 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
38 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
39 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
40 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
41 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
42 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
43 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
44 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
45 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
46 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
47 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
48 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
49 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
50 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
51 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
52 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
53 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
54 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
55 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
56 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
57 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
58 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
59 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
60 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
61 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
62 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
63 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
64 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
65 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
66 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
67 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
68 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
69 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
70 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
71 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
72 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
73 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
74 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
75 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
76 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
77 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
78 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
79 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
80 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
81 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
82 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
83 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
84 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
85 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
86 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
87 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
88 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
89 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
90 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
91 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
92 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
93 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
94 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
95 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
96 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
97 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
98 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
99 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
100 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
101 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
102 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
103};
104
105static const u32 ar9331_1p2_baseband_postamble[][5] = {
106 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
107 {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
108 {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
109 {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
110 {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
111 {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
112 {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
113 {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
114 {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a4, 0x037216a4},
115 {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
116 {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
117 {0x00009e10, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e},
118 {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
119 {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
120 {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
121 {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
122 {0x00009e2c, 0x0000001c, 0x0000001c, 0x00003221, 0x00003221},
123 {0x00009e3c, 0xcf946222, 0xcf946222, 0xcf946222, 0xcf946222},
124 {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
125 {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
126 {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
127 {0x0000a204, 0x00003fc0, 0x00003fc4, 0x00003fc4, 0x00003fc0},
128 {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
129 {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
130 {0x0000a234, 0x00000fff, 0x00000fff, 0x10000fff, 0x00000fff},
131 {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
132 {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
133 {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
134 {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
135 {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
136 {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
137 {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
138 {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
139 {0x0000a284, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
140 {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
141 {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
142 {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
143 {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071981},
144 {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
145 {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
146 {0x0000ae04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
147 {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
148};
149
150static const u32 ar9331_modes_high_ob_db_tx_gain_1p2[][5] = {
151 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
152 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
153 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
154 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
155 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
156 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
157 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
158 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
159 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
160 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
161 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
162 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
163 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
164 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
165 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
166 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
167 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
168 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
169 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
170 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
171 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
172 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
173 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
174 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
175 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
176 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
177 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
178 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
179 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
180 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
181 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
182 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
183 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
184 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
185 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
186 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
187 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
188 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
189 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
190 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
191 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
192 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
193 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
194 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
195 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
196 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
197 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
198 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
199 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
200 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
201 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
202 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
203 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
204 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
205 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
206 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
207 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
208 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
209 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
210 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
211 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
212 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
213 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
214 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
215 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
216 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
217 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
218 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
219 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
220 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
221 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
222 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
223 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
224 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
225 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
226 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
227 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
228 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
229 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
230 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
231 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
232 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
233};
234
235static const u32 ar9331_modes_low_ob_db_tx_gain_1p2[][5] = {
236 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
237 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
238 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
239 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
240 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
241 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
242 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
243 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
244 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
245 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
246 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
247 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
248 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
249 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
250 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
251 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
252 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
253 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
254 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
255 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
256 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
257 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
258 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
259 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
260 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
261 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
262 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
263 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
264 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
265 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
266 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
267 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
268 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
269 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
270 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
271 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
272 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
273 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
274 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
275 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
276 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
277 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
278 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
279 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
280 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
281 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
282 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
283 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
284 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
285 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
286 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
287 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
288 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
289 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
290 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
291 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
292 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
293 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
294 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
295 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
296 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
297 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
298 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
299 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
300 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
301 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
302 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
303 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
304 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
305 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
306 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
307 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
308 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
309 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
310 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
311 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
312 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
313 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
314 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
315 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
316 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
317 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
318};
319
320static const u32 ar9331_1p2_baseband_core_txfir_coeff_japan_2484[][2] = {
321 /* Addr allmodes */
322 {0x0000a398, 0x00000000},
323 {0x0000a39c, 0x6f7f0301},
324 {0x0000a3a0, 0xca9228ee},
325};
326
327static const u32 ar9331_1p2_xtal_25M[][2] = {
328 /* Addr allmodes */
329 {0x00007038, 0x000002f8},
330 {0x00008244, 0x0010f3d7},
331 {0x0000824c, 0x0001e7ae},
332 {0x0001609c, 0x0f508f29},
333};
334
335static const u32 ar9331_1p2_radio_core[][2] = {
336 /* Addr allmodes */
337 {0x00016000, 0x36db6db6},
338 {0x00016004, 0x6db6db40},
339 {0x00016008, 0x73800000},
340 {0x0001600c, 0x00000000},
341 {0x00016040, 0x7f80fff8},
342 {0x00016044, 0x03d6d2db},
343 {0x00016048, 0x6c924268},
344 {0x0001604c, 0x000f0278},
345 {0x00016050, 0x4db6db8c},
346 {0x00016054, 0x6db60000},
347 {0x00016080, 0x00080000},
348 {0x00016084, 0x0e48048c},
349 {0x00016088, 0x14214514},
350 {0x0001608c, 0x119f081c},
351 {0x00016090, 0x24926490},
352 {0x00016098, 0xd411eb84},
353 {0x000160a0, 0xc2108ffe},
354 {0x000160a4, 0x812fc370},
355 {0x000160a8, 0x423c8000},
356 {0x000160ac, 0x24651800},
357 {0x000160b0, 0x03284f3e},
358 {0x000160b4, 0x92480040},
359 {0x000160c0, 0x006db6db},
360 {0x000160c4, 0x0186db60},
361 {0x000160c8, 0x6db6db6c},
362 {0x000160cc, 0x6de6c300},
363 {0x000160d0, 0x14500820},
364 {0x00016100, 0x04cb0001},
365 {0x00016104, 0xfff80015},
366 {0x00016108, 0x00080010},
367 {0x0001610c, 0x00170000},
368 {0x00016140, 0x10804000},
369 {0x00016144, 0x01884080},
370 {0x00016148, 0x000080c0},
371 {0x00016280, 0x01000015},
372 {0x00016284, 0x14d20000},
373 {0x00016288, 0x00318000},
374 {0x0001628c, 0x50000000},
375 {0x00016290, 0x4b96210f},
376 {0x00016380, 0x00000000},
377 {0x00016384, 0x00000000},
378 {0x00016388, 0x00800700},
379 {0x0001638c, 0x00800700},
380 {0x00016390, 0x00800700},
381 {0x00016394, 0x00000000},
382 {0x00016398, 0x00000000},
383 {0x0001639c, 0x00000000},
384 {0x000163a0, 0x00000001},
385 {0x000163a4, 0x00000001},
386 {0x000163a8, 0x00000000},
387 {0x000163ac, 0x00000000},
388 {0x000163b0, 0x00000000},
389 {0x000163b4, 0x00000000},
390 {0x000163b8, 0x00000000},
391 {0x000163bc, 0x00000000},
392 {0x000163c0, 0x000000a0},
393 {0x000163c4, 0x000c0000},
394 {0x000163c8, 0x14021402},
395 {0x000163cc, 0x00001402},
396 {0x000163d0, 0x00000000},
397 {0x000163d4, 0x00000000},
398};
399
400static const u32 ar9331_1p2_soc_postamble[][5] = {
401 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
402 {0x00007010, 0x00000022, 0x00000022, 0x00000022, 0x00000022},
403};
404
405static const u32 ar9331_common_wo_xlna_rx_gain_1p2[][2] = {
406 /* Addr allmodes */
407 {0x0000a000, 0x00060005},
408 {0x0000a004, 0x00810080},
409 {0x0000a008, 0x00830082},
410 {0x0000a00c, 0x00850084},
411 {0x0000a010, 0x01820181},
412 {0x0000a014, 0x01840183},
413 {0x0000a018, 0x01880185},
414 {0x0000a01c, 0x018a0189},
415 {0x0000a020, 0x02850284},
416 {0x0000a024, 0x02890288},
417 {0x0000a028, 0x028b028a},
418 {0x0000a02c, 0x03850384},
419 {0x0000a030, 0x03890388},
420 {0x0000a034, 0x038b038a},
421 {0x0000a038, 0x038d038c},
422 {0x0000a03c, 0x03910390},
423 {0x0000a040, 0x03930392},
424 {0x0000a044, 0x03950394},
425 {0x0000a048, 0x00000396},
426 {0x0000a04c, 0x00000000},
427 {0x0000a050, 0x00000000},
428 {0x0000a054, 0x00000000},
429 {0x0000a058, 0x00000000},
430 {0x0000a05c, 0x00000000},
431 {0x0000a060, 0x00000000},
432 {0x0000a064, 0x00000000},
433 {0x0000a068, 0x00000000},
434 {0x0000a06c, 0x00000000},
435 {0x0000a070, 0x00000000},
436 {0x0000a074, 0x00000000},
437 {0x0000a078, 0x00000000},
438 {0x0000a07c, 0x00000000},
439 {0x0000a080, 0x28282828},
440 {0x0000a084, 0x28282828},
441 {0x0000a088, 0x28282828},
442 {0x0000a08c, 0x28282828},
443 {0x0000a090, 0x28282828},
444 {0x0000a094, 0x24242428},
445 {0x0000a098, 0x171e1e1e},
446 {0x0000a09c, 0x02020b0b},
447 {0x0000a0a0, 0x02020202},
448 {0x0000a0a4, 0x00000000},
449 {0x0000a0a8, 0x00000000},
450 {0x0000a0ac, 0x00000000},
451 {0x0000a0b0, 0x00000000},
452 {0x0000a0b4, 0x00000000},
453 {0x0000a0b8, 0x00000000},
454 {0x0000a0bc, 0x00000000},
455 {0x0000a0c0, 0x22072208},
456 {0x0000a0c4, 0x22052206},
457 {0x0000a0c8, 0x22032204},
458 {0x0000a0cc, 0x22012202},
459 {0x0000a0d0, 0x221f2200},
460 {0x0000a0d4, 0x221d221e},
461 {0x0000a0d8, 0x33023303},
462 {0x0000a0dc, 0x33003301},
463 {0x0000a0e0, 0x331e331f},
464 {0x0000a0e4, 0x4402331d},
465 {0x0000a0e8, 0x44004401},
466 {0x0000a0ec, 0x441e441f},
467 {0x0000a0f0, 0x55025503},
468 {0x0000a0f4, 0x55005501},
469 {0x0000a0f8, 0x551e551f},
470 {0x0000a0fc, 0x6602551d},
471 {0x0000a100, 0x66006601},
472 {0x0000a104, 0x661e661f},
473 {0x0000a108, 0x7703661d},
474 {0x0000a10c, 0x77017702},
475 {0x0000a110, 0x00007700},
476 {0x0000a114, 0x00000000},
477 {0x0000a118, 0x00000000},
478 {0x0000a11c, 0x00000000},
479 {0x0000a120, 0x00000000},
480 {0x0000a124, 0x00000000},
481 {0x0000a128, 0x00000000},
482 {0x0000a12c, 0x00000000},
483 {0x0000a130, 0x00000000},
484 {0x0000a134, 0x00000000},
485 {0x0000a138, 0x00000000},
486 {0x0000a13c, 0x00000000},
487 {0x0000a140, 0x001f0000},
488 {0x0000a144, 0x111f1100},
489 {0x0000a148, 0x111d111e},
490 {0x0000a14c, 0x111b111c},
491 {0x0000a150, 0x22032204},
492 {0x0000a154, 0x22012202},
493 {0x0000a158, 0x221f2200},
494 {0x0000a15c, 0x221d221e},
495 {0x0000a160, 0x33013302},
496 {0x0000a164, 0x331f3300},
497 {0x0000a168, 0x4402331e},
498 {0x0000a16c, 0x44004401},
499 {0x0000a170, 0x441e441f},
500 {0x0000a174, 0x55015502},
501 {0x0000a178, 0x551f5500},
502 {0x0000a17c, 0x6602551e},
503 {0x0000a180, 0x66006601},
504 {0x0000a184, 0x661e661f},
505 {0x0000a188, 0x7703661d},
506 {0x0000a18c, 0x77017702},
507 {0x0000a190, 0x00007700},
508 {0x0000a194, 0x00000000},
509 {0x0000a198, 0x00000000},
510 {0x0000a19c, 0x00000000},
511 {0x0000a1a0, 0x00000000},
512 {0x0000a1a4, 0x00000000},
513 {0x0000a1a8, 0x00000000},
514 {0x0000a1ac, 0x00000000},
515 {0x0000a1b0, 0x00000000},
516 {0x0000a1b4, 0x00000000},
517 {0x0000a1b8, 0x00000000},
518 {0x0000a1bc, 0x00000000},
519 {0x0000a1c0, 0x00000000},
520 {0x0000a1c4, 0x00000000},
521 {0x0000a1c8, 0x00000000},
522 {0x0000a1cc, 0x00000000},
523 {0x0000a1d0, 0x00000000},
524 {0x0000a1d4, 0x00000000},
525 {0x0000a1d8, 0x00000000},
526 {0x0000a1dc, 0x00000000},
527 {0x0000a1e0, 0x00000000},
528 {0x0000a1e4, 0x00000000},
529 {0x0000a1e8, 0x00000000},
530 {0x0000a1ec, 0x00000000},
531 {0x0000a1f0, 0x00000396},
532 {0x0000a1f4, 0x00000396},
533 {0x0000a1f8, 0x00000396},
534 {0x0000a1fc, 0x00000296},
535};
536
537static const u32 ar9331_1p2_baseband_core[][2] = {
538 /* Addr allmodes */
539 {0x00009800, 0xafe68e30},
540 {0x00009804, 0xfd14e000},
541 {0x00009808, 0x9c0a8f6b},
542 {0x0000980c, 0x04800000},
543 {0x00009814, 0x9280c00a},
544 {0x00009818, 0x00000000},
545 {0x0000981c, 0x00020028},
546 {0x00009834, 0x5f3ca3de},
547 {0x00009838, 0x0108ecff},
548 {0x0000983c, 0x14750600},
549 {0x00009880, 0x201fff00},
550 {0x00009884, 0x00001042},
551 {0x000098a4, 0x00200400},
552 {0x000098b0, 0x32840bbe},
553 {0x000098d0, 0x004b6a8e},
554 {0x000098d4, 0x00000820},
555 {0x000098dc, 0x00000000},
556 {0x000098f0, 0x00000000},
557 {0x000098f4, 0x00000000},
558 {0x00009c04, 0x00000000},
559 {0x00009c08, 0x03200000},
560 {0x00009c0c, 0x00000000},
561 {0x00009c10, 0x00000000},
562 {0x00009c14, 0x00046384},
563 {0x00009c18, 0x05b6b440},
564 {0x00009c1c, 0x00b6b440},
565 {0x00009d00, 0xc080a333},
566 {0x00009d04, 0x40206c10},
567 {0x00009d08, 0x009c4060},
568 {0x00009d0c, 0x1883800a},
569 {0x00009d10, 0x01834061},
570 {0x00009d14, 0x00c00400},
571 {0x00009d18, 0x00000000},
572 {0x00009e08, 0x0038233c},
573 {0x00009e24, 0x9927b515},
574 {0x00009e28, 0x12ef0200},
575 {0x00009e30, 0x06336f77},
576 {0x00009e34, 0x6af6532f},
577 {0x00009e38, 0x0cc80c00},
578 {0x00009e40, 0x0d261820},
579 {0x00009e4c, 0x00001004},
580 {0x00009e50, 0x00ff03f1},
581 {0x00009fc0, 0x803e4788},
582 {0x00009fc4, 0x0001efb5},
583 {0x00009fcc, 0x40000014},
584 {0x0000a20c, 0x00000000},
585 {0x0000a220, 0x00000000},
586 {0x0000a224, 0x00000000},
587 {0x0000a228, 0x10002310},
588 {0x0000a23c, 0x00000000},
589 {0x0000a244, 0x0c000000},
590 {0x0000a2a0, 0x00000001},
591 {0x0000a2c0, 0x00000001},
592 {0x0000a2c8, 0x00000000},
593 {0x0000a2cc, 0x18c43433},
594 {0x0000a2d4, 0x00000000},
595 {0x0000a2dc, 0x00000000},
596 {0x0000a2e0, 0x00000000},
597 {0x0000a2e4, 0x00000000},
598 {0x0000a2e8, 0x00000000},
599 {0x0000a2ec, 0x00000000},
600 {0x0000a2f0, 0x00000000},
601 {0x0000a2f4, 0x00000000},
602 {0x0000a2f8, 0x00000000},
603 {0x0000a344, 0x00000000},
604 {0x0000a34c, 0x00000000},
605 {0x0000a350, 0x0000a000},
606 {0x0000a364, 0x00000000},
607 {0x0000a370, 0x00000000},
608 {0x0000a390, 0x00000001},
609 {0x0000a394, 0x00000444},
610 {0x0000a398, 0x001f0e0f},
611 {0x0000a39c, 0x0075393f},
612 {0x0000a3a0, 0xb79f6427},
613 {0x0000a3a4, 0x00000000},
614 {0x0000a3a8, 0xaaaaaaaa},
615 {0x0000a3ac, 0x3c466478},
616 {0x0000a3c0, 0x20202020},
617 {0x0000a3c4, 0x22222220},
618 {0x0000a3c8, 0x20200020},
619 {0x0000a3cc, 0x20202020},
620 {0x0000a3d0, 0x20202020},
621 {0x0000a3d4, 0x20202020},
622 {0x0000a3d8, 0x20202020},
623 {0x0000a3dc, 0x20202020},
624 {0x0000a3e0, 0x20202020},
625 {0x0000a3e4, 0x20202020},
626 {0x0000a3e8, 0x20202020},
627 {0x0000a3ec, 0x20202020},
628 {0x0000a3f0, 0x00000000},
629 {0x0000a3f4, 0x00000006},
630 {0x0000a3f8, 0x0cdbd380},
631 {0x0000a3fc, 0x000f0f01},
632 {0x0000a400, 0x8fa91f01},
633 {0x0000a404, 0x00000000},
634 {0x0000a408, 0x0e79e5c6},
635 {0x0000a40c, 0x00820820},
636 {0x0000a414, 0x1ce739ce},
637 {0x0000a418, 0x2d001dce},
638 {0x0000a41c, 0x1ce739ce},
639 {0x0000a420, 0x000001ce},
640 {0x0000a424, 0x1ce739ce},
641 {0x0000a428, 0x000001ce},
642 {0x0000a42c, 0x1ce739ce},
643 {0x0000a430, 0x1ce739ce},
644 {0x0000a434, 0x00000000},
645 {0x0000a438, 0x00001801},
646 {0x0000a43c, 0x00000000},
647 {0x0000a440, 0x00000000},
648 {0x0000a444, 0x00000000},
649 {0x0000a448, 0x04000000},
650 {0x0000a44c, 0x00000001},
651 {0x0000a450, 0x00010000},
652 {0x0000a458, 0x00000000},
653 {0x0000a640, 0x00000000},
654 {0x0000a644, 0x3fad9d74},
655 {0x0000a648, 0x0048060a},
656 {0x0000a64c, 0x00003c37},
657 {0x0000a670, 0x03020100},
658 {0x0000a674, 0x09080504},
659 {0x0000a678, 0x0d0c0b0a},
660 {0x0000a67c, 0x13121110},
661 {0x0000a680, 0x31301514},
662 {0x0000a684, 0x35343332},
663 {0x0000a688, 0x00000036},
664 {0x0000a690, 0x00000838},
665 {0x0000a7c0, 0x00000000},
666 {0x0000a7c4, 0xfffffffc},
667 {0x0000a7c8, 0x00000000},
668 {0x0000a7cc, 0x00000000},
669 {0x0000a7d0, 0x00000000},
670 {0x0000a7d4, 0x00000004},
671 {0x0000a7dc, 0x00000001},
672};
673
674static const u32 ar9331_modes_high_power_tx_gain_1p2[][5] = {
675 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
676 {0x0000a410, 0x000050d7, 0x000050d7, 0x000050d7, 0x000050d7},
677 {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
678 {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
679 {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
680 {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
681 {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
682 {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
683 {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
684 {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
685 {0x0000a520, 0x2f001f04, 0x2f001f04, 0x23000a00, 0x23000a00},
686 {0x0000a524, 0x35001fc4, 0x35001fc4, 0x27000a02, 0x27000a02},
687 {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2b000a04, 0x2b000a04},
688 {0x0000a52c, 0x41023e85, 0x41023e85, 0x3f001620, 0x3f001620},
689 {0x0000a530, 0x48023ec6, 0x48023ec6, 0x41001621, 0x41001621},
690 {0x0000a534, 0x4d023f01, 0x4d023f01, 0x44001640, 0x44001640},
691 {0x0000a538, 0x53023f4b, 0x53023f4b, 0x46001641, 0x46001641},
692 {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x48001642, 0x48001642},
693 {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x4b001644, 0x4b001644},
694 {0x0000a544, 0x6502feca, 0x6502feca, 0x4e001a81, 0x4e001a81},
695 {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x51001a83, 0x51001a83},
696 {0x0000a54c, 0x7203feca, 0x7203feca, 0x54001c84, 0x54001c84},
697 {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x57001ce3, 0x57001ce3},
698 {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x5b001ce5, 0x5b001ce5},
699 {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x5f001ce9, 0x5f001ce9},
700 {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x66001eec, 0x66001eec},
701 {0x0000a560, 0x900fff0b, 0x900fff0b, 0x66001eec, 0x66001eec},
702 {0x0000a564, 0x960fffcb, 0x960fffcb, 0x66001eec, 0x66001eec},
703 {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
704 {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
705 {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
706 {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
707 {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
708 {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x66001eec, 0x66001eec},
709 {0x0000a580, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
710 {0x0000a584, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
711 {0x0000a588, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
712 {0x0000a58c, 0x11062202, 0x11062202, 0x0b000200, 0x0b000200},
713 {0x0000a590, 0x17022e00, 0x17022e00, 0x0f000202, 0x0f000202},
714 {0x0000a594, 0x1d000ec2, 0x1d000ec2, 0x11000400, 0x11000400},
715 {0x0000a598, 0x25020ec0, 0x25020ec0, 0x15000402, 0x15000402},
716 {0x0000a59c, 0x2b020ec3, 0x2b020ec3, 0x19000404, 0x19000404},
717 {0x0000a5a0, 0x2f001f04, 0x2f001f04, 0x1b000603, 0x1b000603},
718 {0x0000a5a4, 0x35001fc4, 0x35001fc4, 0x1f000a02, 0x1f000a02},
719 {0x0000a5a8, 0x3c022f04, 0x3c022f04, 0x23000a04, 0x23000a04},
720 {0x0000a5ac, 0x41023e85, 0x41023e85, 0x26000a20, 0x26000a20},
721 {0x0000a5b0, 0x48023ec6, 0x48023ec6, 0x2a000e20, 0x2a000e20},
722 {0x0000a5b4, 0x4d023f01, 0x4d023f01, 0x2e000e22, 0x2e000e22},
723 {0x0000a5b8, 0x53023f4b, 0x53023f4b, 0x31000e24, 0x31000e24},
724 {0x0000a5bc, 0x5a027f09, 0x5a027f09, 0x34001640, 0x34001640},
725 {0x0000a5c0, 0x5f027fc9, 0x5f027fc9, 0x38001660, 0x38001660},
726 {0x0000a5c4, 0x6502feca, 0x6502feca, 0x3b001861, 0x3b001861},
727 {0x0000a5c8, 0x6b02ff4a, 0x6b02ff4a, 0x3e001a81, 0x3e001a81},
728 {0x0000a5cc, 0x7203feca, 0x7203feca, 0x42001a83, 0x42001a83},
729 {0x0000a5d0, 0x7703ff0b, 0x7703ff0b, 0x44001c84, 0x44001c84},
730 {0x0000a5d4, 0x7d06ffcb, 0x7d06ffcb, 0x48001ce3, 0x48001ce3},
731 {0x0000a5d8, 0x8407ff0b, 0x8407ff0b, 0x4c001ce5, 0x4c001ce5},
732 {0x0000a5dc, 0x8907ffcb, 0x8907ffcb, 0x50001ce9, 0x50001ce9},
733 {0x0000a5e0, 0x900fff0b, 0x900fff0b, 0x54001ceb, 0x54001ceb},
734 {0x0000a5e4, 0x960fffcb, 0x960fffcb, 0x56001eec, 0x56001eec},
735 {0x0000a5e8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
736 {0x0000a5ec, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
737 {0x0000a5f0, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
738 {0x0000a5f4, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
739 {0x0000a5f8, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
740 {0x0000a5fc, 0x9c1fff0b, 0x9c1fff0b, 0x56001eec, 0x56001eec},
741 {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
742 {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
743 {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
744 {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
745 {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
746 {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
747 {0x0000a618, 0x02008501, 0x02008501, 0x02008501, 0x02008501},
748 {0x0000a61c, 0x02008802, 0x02008802, 0x02008802, 0x02008802},
749 {0x0000a620, 0x0300c802, 0x0300c802, 0x0300c802, 0x0300c802},
750 {0x0000a624, 0x0300cc03, 0x0300cc03, 0x0300cc03, 0x0300cc03},
751 {0x0000a628, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
752 {0x0000a62c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
753 {0x0000a630, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
754 {0x0000a634, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
755 {0x0000a638, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
756 {0x0000a63c, 0x04011004, 0x04011004, 0x04011004, 0x04011004},
757};
758
759static const u32 ar9331_1p2_mac_postamble[][5] = {
760 /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
761 {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
762 {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
763 {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
764 {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
765 {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
766 {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
767 {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
768 {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
769};
770
771static const u32 ar9331_1p2_soc_preamble[][2] = {
772 /* Addr allmodes */
773 {0x00007020, 0x00000000},
774 {0x00007034, 0x00000002},
775 {0x00007038, 0x000002f8},
776};
777
778static const u32 ar9331_1p2_xtal_40M[][2] = {
779 /* Addr allmodes */
780 {0x00007038, 0x000004c2},
781 {0x00008244, 0x0010f400},
782 {0x0000824c, 0x0001e800},
783 {0x0001609c, 0x0b283f31},
784};
785
786static const u32 ar9331_1p2_mac_core[][2] = {
787 /* Addr allmodes */
788 {0x00000008, 0x00000000},
789 {0x00000030, 0x00020085},
790 {0x00000034, 0x00000005},
791 {0x00000040, 0x00000000},
792 {0x00000044, 0x00000000},
793 {0x00000048, 0x00000008},
794 {0x0000004c, 0x00000010},
795 {0x00000050, 0x00000000},
796 {0x00001040, 0x002ffc0f},
797 {0x00001044, 0x002ffc0f},
798 {0x00001048, 0x002ffc0f},
799 {0x0000104c, 0x002ffc0f},
800 {0x00001050, 0x002ffc0f},
801 {0x00001054, 0x002ffc0f},
802 {0x00001058, 0x002ffc0f},
803 {0x0000105c, 0x002ffc0f},
804 {0x00001060, 0x002ffc0f},
805 {0x00001064, 0x002ffc0f},
806 {0x000010f0, 0x00000100},
807 {0x00001270, 0x00000000},
808 {0x000012b0, 0x00000000},
809 {0x000012f0, 0x00000000},
810 {0x0000143c, 0x00000000},
811 {0x0000147c, 0x00000000},
812 {0x00008000, 0x00000000},
813 {0x00008004, 0x00000000},
814 {0x00008008, 0x00000000},
815 {0x0000800c, 0x00000000},
816 {0x00008018, 0x00000000},
817 {0x00008020, 0x00000000},
818 {0x00008038, 0x00000000},
819 {0x0000803c, 0x00000000},
820 {0x00008040, 0x00000000},
821 {0x00008044, 0x00000000},
822 {0x00008048, 0x00000000},
823 {0x0000804c, 0xffffffff},
824 {0x00008054, 0x00000000},
825 {0x00008058, 0x00000000},
826 {0x0000805c, 0x000fc78f},
827 {0x00008060, 0x0000000f},
828 {0x00008064, 0x00000000},
829 {0x00008070, 0x00000310},
830 {0x00008074, 0x00000020},
831 {0x00008078, 0x00000000},
832 {0x0000809c, 0x0000000f},
833 {0x000080a0, 0x00000000},
834 {0x000080a4, 0x02ff0000},
835 {0x000080a8, 0x0e070605},
836 {0x000080ac, 0x0000000d},
837 {0x000080b0, 0x00000000},
838 {0x000080b4, 0x00000000},
839 {0x000080b8, 0x00000000},
840 {0x000080bc, 0x00000000},
841 {0x000080c0, 0x2a800000},
842 {0x000080c4, 0x06900168},
843 {0x000080c8, 0x13881c20},
844 {0x000080cc, 0x01f40000},
845 {0x000080d0, 0x00252500},
846 {0x000080d4, 0x00a00000},
847 {0x000080d8, 0x00400000},
848 {0x000080dc, 0x00000000},
849 {0x000080e0, 0xffffffff},
850 {0x000080e4, 0x0000ffff},
851 {0x000080e8, 0x3f3f3f3f},
852 {0x000080ec, 0x00000000},
853 {0x000080f0, 0x00000000},
854 {0x000080f4, 0x00000000},
855 {0x000080fc, 0x00020000},
856 {0x00008100, 0x00000000},
857 {0x00008108, 0x00000052},
858 {0x0000810c, 0x00000000},
859 {0x00008110, 0x00000000},
860 {0x00008114, 0x000007ff},
861 {0x00008118, 0x000000aa},
862 {0x0000811c, 0x00003210},
863 {0x00008124, 0x00000000},
864 {0x00008128, 0x00000000},
865 {0x0000812c, 0x00000000},
866 {0x00008130, 0x00000000},
867 {0x00008134, 0x00000000},
868 {0x00008138, 0x00000000},
869 {0x0000813c, 0x0000ffff},
870 {0x00008144, 0xffffffff},
871 {0x00008168, 0x00000000},
872 {0x0000816c, 0x00000000},
873 {0x00008170, 0x18486200},
874 {0x00008174, 0x33332210},
875 {0x00008178, 0x00000000},
876 {0x0000817c, 0x00020000},
877 {0x000081c0, 0x00000000},
878 {0x000081c4, 0x33332210},
879 {0x000081c8, 0x00000000},
880 {0x000081cc, 0x00000000},
881 {0x000081d4, 0x00000000},
882 {0x000081ec, 0x00000000},
883 {0x000081f0, 0x00000000},
884 {0x000081f4, 0x00000000},
885 {0x000081f8, 0x00000000},
886 {0x000081fc, 0x00000000},
887 {0x00008240, 0x00100000},
888 {0x00008248, 0x00000800},
889 {0x00008250, 0x00000000},
890 {0x00008254, 0x00000000},
891 {0x00008258, 0x00000000},
892 {0x0000825c, 0x40000000},
893 {0x00008260, 0x00080922},
894 {0x00008264, 0x9d400010},
895 {0x00008268, 0xffffffff},
896 {0x0000826c, 0x0000ffff},
897 {0x00008270, 0x00000000},
898 {0x00008274, 0x40000000},
899 {0x00008278, 0x003e4180},
900 {0x0000827c, 0x00000004},
901 {0x00008284, 0x0000002c},
902 {0x00008288, 0x0000002c},
903 {0x0000828c, 0x000000ff},
904 {0x00008294, 0x00000000},
905 {0x00008298, 0x00000000},
906 {0x0000829c, 0x00000000},
907 {0x00008300, 0x00000140},
908 {0x00008314, 0x00000000},
909 {0x0000831c, 0x0000010d},
910 {0x00008328, 0x00000000},
911 {0x0000832c, 0x00000007},
912 {0x00008330, 0x00000302},
913 {0x00008334, 0x00000700},
914 {0x00008338, 0x00ff0000},
915 {0x0000833c, 0x02400000},
916 {0x00008340, 0x000107ff},
917 {0x00008344, 0xaa48105b},
918 {0x00008348, 0x008f0000},
919 {0x0000835c, 0x00000000},
920 {0x00008360, 0xffffffff},
921 {0x00008364, 0xffffffff},
922 {0x00008368, 0x00000000},
923 {0x00008370, 0x00000000},
924 {0x00008374, 0x000000ff},
925 {0x00008378, 0x00000000},
926 {0x0000837c, 0x00000000},
927 {0x00008380, 0xffffffff},
928 {0x00008384, 0xffffffff},
929 {0x00008390, 0xffffffff},
930 {0x00008394, 0xffffffff},
931 {0x00008398, 0x00000000},
932 {0x0000839c, 0x00000000},
933 {0x000083a0, 0x00000000},
934 {0x000083a4, 0x0000fa14},
935 {0x000083a8, 0x000f0c00},
936 {0x000083ac, 0x33332210},
937 {0x000083b0, 0x33332210},
938 {0x000083b4, 0x33332210},
939 {0x000083b8, 0x33332210},
940 {0x000083bc, 0x00000000},
941 {0x000083c0, 0x00000000},
942 {0x000083c4, 0x00000000},
943 {0x000083c8, 0x00000000},
944 {0x000083cc, 0x00000200},
945 {0x000083d0, 0x000301ff},
946};
947
948static const u32 ar9331_common_rx_gain_1p2[][2] = {
949 /* Addr allmodes */
950 {0x0000a000, 0x00010000},
951 {0x0000a004, 0x00030002},
952 {0x0000a008, 0x00050004},
953 {0x0000a00c, 0x00810080},
954 {0x0000a010, 0x01800082},
955 {0x0000a014, 0x01820181},
956 {0x0000a018, 0x01840183},
957 {0x0000a01c, 0x01880185},
958 {0x0000a020, 0x018a0189},
959 {0x0000a024, 0x02850284},
960 {0x0000a028, 0x02890288},
961 {0x0000a02c, 0x03850384},
962 {0x0000a030, 0x03890388},
963 {0x0000a034, 0x038b038a},
964 {0x0000a038, 0x038d038c},
965 {0x0000a03c, 0x03910390},
966 {0x0000a040, 0x03930392},
967 {0x0000a044, 0x03950394},
968 {0x0000a048, 0x00000396},
969 {0x0000a04c, 0x00000000},
970 {0x0000a050, 0x00000000},
971 {0x0000a054, 0x00000000},
972 {0x0000a058, 0x00000000},
973 {0x0000a05c, 0x00000000},
974 {0x0000a060, 0x00000000},
975 {0x0000a064, 0x00000000},
976 {0x0000a068, 0x00000000},
977 {0x0000a06c, 0x00000000},
978 {0x0000a070, 0x00000000},
979 {0x0000a074, 0x00000000},
980 {0x0000a078, 0x00000000},
981 {0x0000a07c, 0x00000000},
982 {0x0000a080, 0x28282828},
983 {0x0000a084, 0x28282828},
984 {0x0000a088, 0x28282828},
985 {0x0000a08c, 0x28282828},
986 {0x0000a090, 0x28282828},
987 {0x0000a094, 0x21212128},
988 {0x0000a098, 0x171c1c1c},
989 {0x0000a09c, 0x02020212},
990 {0x0000a0a0, 0x00000202},
991 {0x0000a0a4, 0x00000000},
992 {0x0000a0a8, 0x00000000},
993 {0x0000a0ac, 0x00000000},
994 {0x0000a0b0, 0x00000000},
995 {0x0000a0b4, 0x00000000},
996 {0x0000a0b8, 0x00000000},
997 {0x0000a0bc, 0x00000000},
998 {0x0000a0c0, 0x001f0000},
999 {0x0000a0c4, 0x111f1100},
1000 {0x0000a0c8, 0x111d111e},
1001 {0x0000a0cc, 0x111b111c},
1002 {0x0000a0d0, 0x22032204},
1003 {0x0000a0d4, 0x22012202},
1004 {0x0000a0d8, 0x221f2200},
1005 {0x0000a0dc, 0x221d221e},
1006 {0x0000a0e0, 0x33013302},
1007 {0x0000a0e4, 0x331f3300},
1008 {0x0000a0e8, 0x4402331e},
1009 {0x0000a0ec, 0x44004401},
1010 {0x0000a0f0, 0x441e441f},
1011 {0x0000a0f4, 0x55015502},
1012 {0x0000a0f8, 0x551f5500},
1013 {0x0000a0fc, 0x6602551e},
1014 {0x0000a100, 0x66006601},
1015 {0x0000a104, 0x661e661f},
1016 {0x0000a108, 0x7703661d},
1017 {0x0000a10c, 0x77017702},
1018 {0x0000a110, 0x00007700},
1019 {0x0000a114, 0x00000000},
1020 {0x0000a118, 0x00000000},
1021 {0x0000a11c, 0x00000000},
1022 {0x0000a120, 0x00000000},
1023 {0x0000a124, 0x00000000},
1024 {0x0000a128, 0x00000000},
1025 {0x0000a12c, 0x00000000},
1026 {0x0000a130, 0x00000000},
1027 {0x0000a134, 0x00000000},
1028 {0x0000a138, 0x00000000},
1029 {0x0000a13c, 0x00000000},
1030 {0x0000a140, 0x001f0000},
1031 {0x0000a144, 0x111f1100},
1032 {0x0000a148, 0x111d111e},
1033 {0x0000a14c, 0x111b111c},
1034 {0x0000a150, 0x22032204},
1035 {0x0000a154, 0x22012202},
1036 {0x0000a158, 0x221f2200},
1037 {0x0000a15c, 0x221d221e},
1038 {0x0000a160, 0x33013302},
1039 {0x0000a164, 0x331f3300},
1040 {0x0000a168, 0x4402331e},
1041 {0x0000a16c, 0x44004401},
1042 {0x0000a170, 0x441e441f},
1043 {0x0000a174, 0x55015502},
1044 {0x0000a178, 0x551f5500},
1045 {0x0000a17c, 0x6602551e},
1046 {0x0000a180, 0x66006601},
1047 {0x0000a184, 0x661e661f},
1048 {0x0000a188, 0x7703661d},
1049 {0x0000a18c, 0x77017702},
1050 {0x0000a190, 0x00007700},
1051 {0x0000a194, 0x00000000},
1052 {0x0000a198, 0x00000000},
1053 {0x0000a19c, 0x00000000},
1054 {0x0000a1a0, 0x00000000},
1055 {0x0000a1a4, 0x00000000},
1056 {0x0000a1a8, 0x00000000},
1057 {0x0000a1ac, 0x00000000},
1058 {0x0000a1b0, 0x00000000},
1059 {0x0000a1b4, 0x00000000},
1060 {0x0000a1b8, 0x00000000},
1061 {0x0000a1bc, 0x00000000},
1062 {0x0000a1c0, 0x00000000},
1063 {0x0000a1c4, 0x00000000},
1064 {0x0000a1c8, 0x00000000},
1065 {0x0000a1cc, 0x00000000},
1066 {0x0000a1d0, 0x00000000},
1067 {0x0000a1d4, 0x00000000},
1068 {0x0000a1d8, 0x00000000},
1069 {0x0000a1dc, 0x00000000},
1070 {0x0000a1e0, 0x00000000},
1071 {0x0000a1e4, 0x00000000},
1072 {0x0000a1e8, 0x00000000},
1073 {0x0000a1ec, 0x00000000},
1074 {0x0000a1f0, 0x00000396},
1075 {0x0000a1f4, 0x00000396},
1076 {0x0000a1f8, 0x00000396},
1077 {0x0000a1fc, 0x00000296},
1078};
1079
1080#endif /* INITVALS_9330_1P2_H */
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index f75068b4b310..46393f90f16c 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -19,6 +19,7 @@
19 19
20#include <linux/etherdevice.h> 20#include <linux/etherdevice.h>
21#include <linux/device.h> 21#include <linux/device.h>
22#include <linux/interrupt.h>
22#include <linux/leds.h> 23#include <linux/leds.h>
23#include <linux/completion.h> 24#include <linux/completion.h>
24 25
@@ -54,8 +55,6 @@ struct ath_node;
54 (_l) &= ((_sz) - 1); \ 55 (_l) &= ((_sz) - 1); \
55 } while (0) 56 } while (0)
56 57
57#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
58
59#define TSF_TO_TU(_h,_l) \ 58#define TSF_TO_TU(_h,_l) \
60 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) 59 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
61 60
@@ -102,6 +101,11 @@ enum buffer_type {
102 101
103#define ATH_TXSTATUS_RING_SIZE 64 102#define ATH_TXSTATUS_RING_SIZE 64
104 103
104#define DS2PHYS(_dd, _ds) \
105 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
106#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
107#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
108
105struct ath_descdma { 109struct ath_descdma {
106 void *dd_desc; 110 void *dd_desc;
107 dma_addr_t dd_desc_paddr; 111 dma_addr_t dd_desc_paddr;
@@ -179,7 +183,7 @@ enum ATH_AGGR_STATUS {
179struct ath_txq { 183struct ath_txq {
180 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ 184 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
181 u32 axq_qnum; /* ath9k hardware queue number */ 185 u32 axq_qnum; /* ath9k hardware queue number */
182 u32 *axq_link; 186 void *axq_link;
183 struct list_head axq_q; 187 struct list_head axq_q;
184 spinlock_t axq_lock; 188 spinlock_t axq_lock;
185 u32 axq_depth; 189 u32 axq_depth;
@@ -188,7 +192,6 @@ struct ath_txq {
188 bool axq_tx_inprogress; 192 bool axq_tx_inprogress;
189 struct list_head axq_acq; 193 struct list_head axq_acq;
190 struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; 194 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
191 struct list_head txq_fifo_pending;
192 u8 txq_headidx; 195 u8 txq_headidx;
193 u8 txq_tailidx; 196 u8 txq_tailidx;
194 int pending_frames; 197 int pending_frames;
@@ -428,6 +431,7 @@ void ath_hw_check(struct work_struct *work);
428void ath_hw_pll_work(struct work_struct *work); 431void ath_hw_pll_work(struct work_struct *work);
429void ath_paprd_calibrate(struct work_struct *work); 432void ath_paprd_calibrate(struct work_struct *work);
430void ath_ani_calibrate(unsigned long data); 433void ath_ani_calibrate(unsigned long data);
434void ath_start_ani(struct ath_common *common);
431 435
432/**********/ 436/**********/
433/* BTCOEX */ 437/* BTCOEX */
@@ -579,7 +583,7 @@ struct ath9k_vif_iter_data {
579 int naps; /* number of AP vifs */ 583 int naps; /* number of AP vifs */
580 int nmeshes; /* number of mesh vifs */ 584 int nmeshes; /* number of mesh vifs */
581 int nstations; /* number of station vifs */ 585 int nstations; /* number of station vifs */
582 int nwds; /* number of nwd vifs */ 586 int nwds; /* number of WDS vifs */
583 int nadhocs; /* number of adhoc vifs */ 587 int nadhocs; /* number of adhoc vifs */
584 int nothers; /* number of vifs not specified above. */ 588 int nothers; /* number of vifs not specified above. */
585}; 589};
@@ -669,12 +673,8 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
669 const struct ath_bus_ops *bus_ops); 673 const struct ath_bus_ops *bus_ops);
670void ath9k_deinit_device(struct ath_softc *sc); 674void ath9k_deinit_device(struct ath_softc *sc);
671void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); 675void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
672int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
673 struct ath9k_channel *hchan);
674 676
675void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
676void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); 677void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
677bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode);
678bool ath9k_uses_beacons(int type); 678bool ath9k_uses_beacons(int type);
679 679
680#ifdef CONFIG_ATH9K_PCI 680#ifdef CONFIG_ATH9K_PCI
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index d4d8ceced89b..0d13ff74a68b 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <linux/dma-mapping.h>
17#include "ath9k.h" 18#include "ath9k.h"
18 19
19#define FUDGE 2 20#define FUDGE 2
@@ -360,6 +361,7 @@ void ath_beacon_tasklet(unsigned long data)
360 struct ath_common *common = ath9k_hw_common(ah); 361 struct ath_common *common = ath9k_hw_common(ah);
361 struct ath_buf *bf = NULL; 362 struct ath_buf *bf = NULL;
362 struct ieee80211_vif *vif; 363 struct ieee80211_vif *vif;
364 struct ath_tx_status ts;
363 int slot; 365 int slot;
364 u32 bfaddr, bc = 0; 366 u32 bfaddr, bc = 0;
365 367
@@ -384,7 +386,9 @@ void ath_beacon_tasklet(unsigned long data)
384 ath_dbg(common, ATH_DBG_BSTUCK, 386 ath_dbg(common, ATH_DBG_BSTUCK,
385 "beacon is officially stuck\n"); 387 "beacon is officially stuck\n");
386 sc->sc_flags |= SC_OP_TSF_RESET; 388 sc->sc_flags |= SC_OP_TSF_RESET;
389 spin_lock(&sc->sc_pcu_lock);
387 ath_reset(sc, true); 390 ath_reset(sc, true);
391 spin_unlock(&sc->sc_pcu_lock);
388 } 392 }
389 393
390 return; 394 return;
@@ -464,6 +468,11 @@ void ath_beacon_tasklet(unsigned long data)
464 ath9k_hw_txstart(ah, sc->beacon.beaconq); 468 ath9k_hw_txstart(ah, sc->beacon.beaconq);
465 469
466 sc->beacon.ast_be_xmit += bc; /* XXX per-vif? */ 470 sc->beacon.ast_be_xmit += bc; /* XXX per-vif? */
471 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
472 spin_lock_bh(&sc->sc_pcu_lock);
473 ath9k_hw_txprocdesc(ah, bf->bf_desc, (void *)&ts);
474 spin_unlock_bh(&sc->sc_pcu_lock);
475 }
467 } 476 }
468} 477}
469 478
@@ -496,7 +505,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
496 u32 nexttbtt, intval; 505 u32 nexttbtt, intval;
497 506
498 /* NB: the beacon interval is kept internally in TU's */ 507 /* NB: the beacon interval is kept internally in TU's */
499 intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD); 508 intval = TU_TO_USEC(conf->beacon_interval);
500 intval /= ATH_BCBUF; /* for staggered beacons */ 509 intval /= ATH_BCBUF; /* for staggered beacons */
501 nexttbtt = intval; 510 nexttbtt = intval;
502 511
@@ -543,7 +552,7 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
543 } 552 }
544 553
545 memset(&bs, 0, sizeof(bs)); 554 memset(&bs, 0, sizeof(bs));
546 intval = conf->beacon_interval & ATH9K_BEACON_PERIOD; 555 intval = conf->beacon_interval;
547 556
548 /* 557 /*
549 * Setup dtim and cfp parameters according to 558 * Setup dtim and cfp parameters according to
@@ -652,22 +661,13 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
652{ 661{
653 struct ath_hw *ah = sc->sc_ah; 662 struct ath_hw *ah = sc->sc_ah;
654 struct ath_common *common = ath9k_hw_common(ah); 663 struct ath_common *common = ath9k_hw_common(ah);
655 u32 tsf, delta, intval, nexttbtt; 664 u32 tsf, intval, nexttbtt;
656 665
657 ath9k_reset_beacon_status(sc); 666 ath9k_reset_beacon_status(sc);
658 667
659 tsf = ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE); 668 intval = TU_TO_USEC(conf->beacon_interval);
660 intval = TU_TO_USEC(conf->beacon_interval & ATH9K_BEACON_PERIOD); 669 tsf = roundup(ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE), intval);
661 670 nexttbtt = tsf + intval;
662 if (!sc->beacon.bc_tstamp)
663 nexttbtt = tsf + intval;
664 else {
665 if (tsf > sc->beacon.bc_tstamp)
666 delta = (tsf - sc->beacon.bc_tstamp);
667 else
668 delta = (tsf + 1 + (~0U - sc->beacon.bc_tstamp));
669 nexttbtt = tsf + intval - (delta % intval);
670 }
671 671
672 ath_dbg(common, ATH_DBG_BEACON, 672 ath_dbg(common, ATH_DBG_BEACON,
673 "IBSS nexttbtt %u intval %u (%u)\n", 673 "IBSS nexttbtt %u intval %u (%u)\n",
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index 41ce0b139886..6635c377dc00 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -50,7 +50,7 @@ void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
50 .bt_first_slot_time = 5, 50 .bt_first_slot_time = 5,
51 .bt_hold_rx_clear = true, 51 .bt_hold_rx_clear = true,
52 }; 52 };
53 u32 i; 53 u32 i, idx;
54 bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity; 54 bool rxclear_polarity = ath_bt_config.bt_rxclear_polarity;
55 55
56 if (AR_SREV_9300_20_OR_LATER(ah)) 56 if (AR_SREV_9300_20_OR_LATER(ah))
@@ -73,8 +73,10 @@ void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
73 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) | 73 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
74 AR_BT_DISABLE_BT_ANT; 74 AR_BT_DISABLE_BT_ANT;
75 75
76 for (i = 0; i < 32; i++) 76 for (i = 0; i < 32; i++) {
77 ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i; 77 idx = (debruijn32 << i) >> 27;
78 ah->hw_gen_timers.gen_timer_index[idx] = i;
79 }
78} 80}
79EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw); 81EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
80 82
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index d55ffd7d4bd2..d1eb89611ff7 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -176,6 +176,56 @@ static const struct file_operations fops_rx_chainmask = {
176 .llseek = default_llseek, 176 .llseek = default_llseek,
177}; 177};
178 178
179static ssize_t read_file_disable_ani(struct file *file, char __user *user_buf,
180 size_t count, loff_t *ppos)
181{
182 struct ath_softc *sc = file->private_data;
183 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
184 char buf[32];
185 unsigned int len;
186
187 len = sprintf(buf, "%d\n", common->disable_ani);
188 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
189}
190
191static ssize_t write_file_disable_ani(struct file *file,
192 const char __user *user_buf,
193 size_t count, loff_t *ppos)
194{
195 struct ath_softc *sc = file->private_data;
196 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
197 unsigned long disable_ani;
198 char buf[32];
199 ssize_t len;
200
201 len = min(count, sizeof(buf) - 1);
202 if (copy_from_user(buf, user_buf, len))
203 return -EFAULT;
204
205 buf[len] = '\0';
206 if (strict_strtoul(buf, 0, &disable_ani))
207 return -EINVAL;
208
209 common->disable_ani = !!disable_ani;
210
211 if (disable_ani) {
212 sc->sc_flags &= ~SC_OP_ANI_RUN;
213 del_timer_sync(&common->ani.timer);
214 } else {
215 sc->sc_flags |= SC_OP_ANI_RUN;
216 ath_start_ani(common);
217 }
218
219 return count;
220}
221
222static const struct file_operations fops_disable_ani = {
223 .read = read_file_disable_ani,
224 .write = write_file_disable_ani,
225 .open = ath9k_debugfs_open,
226 .owner = THIS_MODULE,
227 .llseek = default_llseek,
228};
179 229
180static ssize_t read_file_dma(struct file *file, char __user *user_buf, 230static ssize_t read_file_dma(struct file *file, char __user *user_buf,
181 size_t count, loff_t *ppos) 231 size_t count, loff_t *ppos)
@@ -550,6 +600,7 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
550 600
551 PR("MPDUs Queued: ", queued); 601 PR("MPDUs Queued: ", queued);
552 PR("MPDUs Completed: ", completed); 602 PR("MPDUs Completed: ", completed);
603 PR("MPDUs XRetried: ", xretries);
553 PR("Aggregates: ", a_aggr); 604 PR("Aggregates: ", a_aggr);
554 PR("AMPDUs Queued HW:", a_queued_hw); 605 PR("AMPDUs Queued HW:", a_queued_hw);
555 PR("AMPDUs Queued SW:", a_queued_sw); 606 PR("AMPDUs Queued SW:", a_queued_sw);
@@ -587,7 +638,6 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
587 638
588 PRQLE("axq_q empty: ", axq_q); 639 PRQLE("axq_q empty: ", axq_q);
589 PRQLE("axq_acq empty: ", axq_acq); 640 PRQLE("axq_acq empty: ", axq_acq);
590 PRQLE("txq_fifo_pending: ", txq_fifo_pending);
591 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) { 641 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) {
592 snprintf(tmp, sizeof(tmp) - 1, "txq_fifo[%i] empty: ", i); 642 snprintf(tmp, sizeof(tmp) - 1, "txq_fifo[%i] empty: ", i);
593 PRQLE(tmp, txq_fifo[i]); 643 PRQLE(tmp, txq_fifo[i]);
@@ -699,7 +749,6 @@ static ssize_t read_file_misc(struct file *file, char __user *user_buf,
699 char *buf; 749 char *buf;
700 unsigned int len = 0, size = 8000; 750 unsigned int len = 0, size = 8000;
701 ssize_t retval = 0; 751 ssize_t retval = 0;
702 const char *tmp;
703 unsigned int reg; 752 unsigned int reg;
704 struct ath9k_vif_iter_data iter_data; 753 struct ath9k_vif_iter_data iter_data;
705 754
@@ -709,31 +758,14 @@ static ssize_t read_file_misc(struct file *file, char __user *user_buf,
709 if (buf == NULL) 758 if (buf == NULL)
710 return -ENOMEM; 759 return -ENOMEM;
711 760
712 switch (sc->sc_ah->opmode) {
713 case NL80211_IFTYPE_ADHOC:
714 tmp = "ADHOC";
715 break;
716 case NL80211_IFTYPE_MESH_POINT:
717 tmp = "MESH";
718 break;
719 case NL80211_IFTYPE_AP:
720 tmp = "AP";
721 break;
722 case NL80211_IFTYPE_STATION:
723 tmp = "STATION";
724 break;
725 default:
726 tmp = "???";
727 break;
728 }
729
730 ath9k_ps_wakeup(sc); 761 ath9k_ps_wakeup(sc);
731 len += snprintf(buf + len, size - len, 762 len += snprintf(buf + len, size - len,
732 "curbssid: %pM\n" 763 "curbssid: %pM\n"
733 "OP-Mode: %s(%i)\n" 764 "OP-Mode: %s(%i)\n"
734 "Beacon-Timer-Register: 0x%x\n", 765 "Beacon-Timer-Register: 0x%x\n",
735 common->curbssid, 766 common->curbssid,
736 tmp, (int)(sc->sc_ah->opmode), 767 ath_opmode_to_string(sc->sc_ah->opmode),
768 (int)(sc->sc_ah->opmode),
737 REG_READ(ah, AR_BEACON_PERIOD)); 769 REG_READ(ah, AR_BEACON_PERIOD));
738 770
739 reg = REG_READ(ah, AR_TIMER_MODE); 771 reg = REG_READ(ah, AR_TIMER_MODE);
@@ -807,7 +839,10 @@ void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
807 else 839 else
808 TX_STAT_INC(qnum, a_completed); 840 TX_STAT_INC(qnum, a_completed);
809 } else { 841 } else {
810 TX_STAT_INC(qnum, completed); 842 if (bf_isxretried(bf))
843 TX_STAT_INC(qnum, xretries);
844 else
845 TX_STAT_INC(qnum, completed);
811 } 846 }
812 847
813 if (ts->ts_status & ATH9K_TXERR_FIFO) 848 if (ts->ts_status & ATH9K_TXERR_FIFO)
@@ -1160,6 +1195,8 @@ int ath9k_init_debug(struct ath_hw *ah)
1160 sc->debug.debugfs_phy, sc, &fops_rx_chainmask); 1195 sc->debug.debugfs_phy, sc, &fops_rx_chainmask);
1161 debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR, 1196 debugfs_create_file("tx_chainmask", S_IRUSR | S_IWUSR,
1162 sc->debug.debugfs_phy, sc, &fops_tx_chainmask); 1197 sc->debug.debugfs_phy, sc, &fops_tx_chainmask);
1198 debugfs_create_file("disable_ani", S_IRUSR | S_IWUSR,
1199 sc->debug.debugfs_phy, sc, &fops_disable_ani);
1163 debugfs_create_file("regidx", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy, 1200 debugfs_create_file("regidx", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
1164 sc, &fops_regidx); 1201 sc, &fops_regidx);
1165 debugfs_create_file("regval", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy, 1202 debugfs_create_file("regval", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index 8ce6ad80f4e2..4a04510e1111 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -116,6 +116,7 @@ struct ath_tx_stats {
116 u32 tx_bytes_all; 116 u32 tx_bytes_all;
117 u32 queued; 117 u32 queued;
118 u32 completed; 118 u32 completed;
119 u32 xretries;
119 u32 a_aggr; 120 u32 a_aggr;
120 u32 a_queued_hw; 121 u32 a_queued_hw;
121 u32 a_queued_sw; 122 u32 a_queued_sw;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 5b1e894f3d67..47cc95086e6e 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <asm/unaligned.h>
17#include "hw.h" 18#include "hw.h"
18#include "ar9002_phy.h" 19#include "ar9002_phy.h"
19 20
@@ -203,11 +204,11 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
203 case EEP_NFTHRESH_2: 204 case EEP_NFTHRESH_2:
204 return pModal->noiseFloorThreshCh[0]; 205 return pModal->noiseFloorThreshCh[0];
205 case EEP_MAC_LSW: 206 case EEP_MAC_LSW:
206 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 207 return get_unaligned_be16(pBase->macAddr);
207 case EEP_MAC_MID: 208 case EEP_MAC_MID:
208 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 209 return get_unaligned_be16(pBase->macAddr + 2);
209 case EEP_MAC_MSW: 210 case EEP_MAC_MSW:
210 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 211 return get_unaligned_be16(pBase->macAddr + 4);
211 case EEP_REG_0: 212 case EEP_REG_0:
212 return pBase->regDmn[0]; 213 return pBase->regDmn[0];
213 case EEP_REG_1: 214 case EEP_REG_1:
@@ -331,10 +332,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
331 332
332 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 333 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
333 for (j = 0; j < 32; j++) { 334 for (j = 0; j < 32; j++) {
334 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | 335 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
335 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
336 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
337 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
338 REG_WRITE(ah, regOffset, reg32); 336 REG_WRITE(ah, regOffset, reg32);
339 337
340 ath_dbg(common, ATH_DBG_EEPROM, 338 ath_dbg(common, ATH_DBG_EEPROM,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index 343fc9f946db..d6f6b192f450 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <asm/unaligned.h>
17#include "hw.h" 18#include "hw.h"
18#include "ar9002_phy.h" 19#include "ar9002_phy.h"
19 20
@@ -195,11 +196,11 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
195 case EEP_NFTHRESH_2: 196 case EEP_NFTHRESH_2:
196 return pModal->noiseFloorThreshCh[0]; 197 return pModal->noiseFloorThreshCh[0];
197 case EEP_MAC_LSW: 198 case EEP_MAC_LSW:
198 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 199 return get_unaligned_be16(pBase->macAddr);
199 case EEP_MAC_MID: 200 case EEP_MAC_MID:
200 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 201 return get_unaligned_be16(pBase->macAddr + 2);
201 case EEP_MAC_MSW: 202 case EEP_MAC_MSW:
202 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 203 return get_unaligned_be16(pBase->macAddr + 4);
203 case EEP_REG_0: 204 case EEP_REG_0:
204 return pBase->regDmn[0]; 205 return pBase->regDmn[0];
205 case EEP_REG_1: 206 case EEP_REG_1:
@@ -434,10 +435,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
434 (672 << 2) + regChainOffset; 435 (672 << 2) + regChainOffset;
435 436
436 for (j = 0; j < 32; j++) { 437 for (j = 0; j < 32; j++) {
437 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) 438 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
438 | ((pdadcValues[4*j + 1] & 0xFF) << 8)
439 | ((pdadcValues[4*j + 2] & 0xFF) << 16)
440 | ((pdadcValues[4*j + 3] & 0xFF) << 24);
441 439
442 REG_WRITE(ah, regOffset, reg32); 440 REG_WRITE(ah, regOffset, reg32);
443 regOffset += 4; 441 regOffset += 4;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 17f0a6806207..b9540a992616 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <asm/unaligned.h>
17#include "hw.h" 18#include "hw.h"
18#include "ar9002_phy.h" 19#include "ar9002_phy.h"
19 20
@@ -276,11 +277,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
276 case EEP_NFTHRESH_2: 277 case EEP_NFTHRESH_2:
277 return pModal[1].noiseFloorThreshCh[0]; 278 return pModal[1].noiseFloorThreshCh[0];
278 case EEP_MAC_LSW: 279 case EEP_MAC_LSW:
279 return pBase->macAddr[0] << 8 | pBase->macAddr[1]; 280 return get_unaligned_be16(pBase->macAddr);
280 case EEP_MAC_MID: 281 case EEP_MAC_MID:
281 return pBase->macAddr[2] << 8 | pBase->macAddr[3]; 282 return get_unaligned_be16(pBase->macAddr + 2);
282 case EEP_MAC_MSW: 283 case EEP_MAC_MSW:
283 return pBase->macAddr[4] << 8 | pBase->macAddr[5]; 284 return get_unaligned_be16(pBase->macAddr + 4);
284 case EEP_REG_0: 285 case EEP_REG_0:
285 return pBase->regDmn[0]; 286 return pBase->regDmn[0];
286 case EEP_REG_1: 287 case EEP_REG_1:
@@ -831,10 +832,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
831 832
832 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 833 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
833 for (j = 0; j < 32; j++) { 834 for (j = 0; j < 32; j++) {
834 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | 835 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
835 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
836 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
837 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
838 REG_WRITE(ah, regOffset, reg32); 836 REG_WRITE(ah, regOffset, reg32);
839 837
840 ath_dbg(common, ATH_DBG_EEPROM, 838 ath_dbg(common, ATH_DBG_EEPROM,
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index 260f1f37a60e..d3f4a59cd456 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <asm/unaligned.h>
17#include "htc.h" 18#include "htc.h"
18 19
19/* identify firmware images */ 20/* identify firmware images */
@@ -49,6 +50,8 @@ static struct usb_device_id ath9k_hif_usb_ids[] = {
49 .driver_info = AR9280_USB }, /* Netgear WNDA3200 */ 50 .driver_info = AR9280_USB }, /* Netgear WNDA3200 */
50 { USB_DEVICE(0x083A, 0xA704), 51 { USB_DEVICE(0x083A, 0xA704),
51 .driver_info = AR9280_USB }, /* SMC Networks */ 52 .driver_info = AR9280_USB }, /* SMC Networks */
53 { USB_DEVICE(0x0411, 0x017f),
54 .driver_info = AR9280_USB }, /* Sony UWA-BR100 */
52 55
53 { USB_DEVICE(0x0cf3, 0x20ff), 56 { USB_DEVICE(0x0cf3, 0x20ff),
54 .driver_info = STORAGE_DEVICE }, 57 .driver_info = STORAGE_DEVICE },
@@ -127,12 +130,14 @@ static int hif_usb_send_regout(struct hif_device_usb *hif_dev,
127static void hif_usb_mgmt_cb(struct urb *urb) 130static void hif_usb_mgmt_cb(struct urb *urb)
128{ 131{
129 struct cmd_buf *cmd = (struct cmd_buf *)urb->context; 132 struct cmd_buf *cmd = (struct cmd_buf *)urb->context;
130 struct hif_device_usb *hif_dev = cmd->hif_dev; 133 struct hif_device_usb *hif_dev;
131 bool txok = true; 134 bool txok = true;
132 135
133 if (!cmd || !cmd->skb || !cmd->hif_dev) 136 if (!cmd || !cmd->skb || !cmd->hif_dev)
134 return; 137 return;
135 138
139 hif_dev = cmd->hif_dev;
140
136 switch (urb->status) { 141 switch (urb->status) {
137 case 0: 142 case 0:
138 break; 143 break;
@@ -555,8 +560,8 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev,
555 560
556 ptr = (u8 *) skb->data; 561 ptr = (u8 *) skb->data;
557 562
558 pkt_len = ptr[index] + (ptr[index+1] << 8); 563 pkt_len = get_unaligned_le16(ptr + index);
559 pkt_tag = ptr[index+2] + (ptr[index+3] << 8); 564 pkt_tag = get_unaligned_le16(ptr + index + 2);
560 565
561 if (pkt_tag != ATH_USB_RX_STREAM_MODE_TAG) { 566 if (pkt_tag != ATH_USB_RX_STREAM_MODE_TAG) {
562 RX_STAT_INC(skb_dropped); 567 RX_STAT_INC(skb_dropped);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index aa6a73118706..57fe22b24247 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -79,7 +79,7 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
79 79
80 memset(&bs, 0, sizeof(bs)); 80 memset(&bs, 0, sizeof(bs));
81 81
82 intval = bss_conf->beacon_interval & ATH9K_BEACON_PERIOD; 82 intval = bss_conf->beacon_interval;
83 bmiss_timeout = (ATH_DEFAULT_BMISS_LIMIT * bss_conf->beacon_interval); 83 bmiss_timeout = (ATH_DEFAULT_BMISS_LIMIT * bss_conf->beacon_interval);
84 84
85 /* 85 /*
@@ -194,7 +194,7 @@ static void ath9k_htc_beacon_config_ap(struct ath9k_htc_priv *priv,
194 u8 cmd_rsp; 194 u8 cmd_rsp;
195 u64 tsf; 195 u64 tsf;
196 196
197 intval = bss_conf->beacon_interval & ATH9K_BEACON_PERIOD; 197 intval = bss_conf->beacon_interval;
198 intval /= ATH9K_HTC_MAX_BCN_VIF; 198 intval /= ATH9K_HTC_MAX_BCN_VIF;
199 nexttbtt = intval; 199 nexttbtt = intval;
200 200
@@ -250,7 +250,7 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
250 u8 cmd_rsp; 250 u8 cmd_rsp;
251 u64 tsf; 251 u64 tsf;
252 252
253 intval = bss_conf->beacon_interval & ATH9K_BEACON_PERIOD; 253 intval = bss_conf->beacon_interval;
254 nexttbtt = intval; 254 nexttbtt = intval;
255 255
256 /* 256 /*
@@ -427,7 +427,7 @@ static int ath9k_htc_choose_bslot(struct ath9k_htc_priv *priv,
427 u16 intval; 427 u16 intval;
428 int slot; 428 int slot;
429 429
430 intval = priv->cur_beacon_conf.beacon_interval & ATH9K_BEACON_PERIOD; 430 intval = priv->cur_beacon_conf.beacon_interval;
431 431
432 tsf = be64_to_cpu(swba->tsf); 432 tsf = be64_to_cpu(swba->tsf);
433 tsftu = TSF_TO_TU(tsf >> 32, tsf); 433 tsftu = TSF_TO_TU(tsf >> 32, tsf);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
index aa48b3abbc48..d3ff33c71aa5 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c
@@ -623,11 +623,8 @@ static ssize_t read_file_base_eeprom(struct file *file, char __user *user_buf,
623 pBase9287->openLoopPwrCntl); 623 pBase9287->openLoopPwrCntl);
624 } 624 }
625 625
626 len += snprintf(buf + len, size - len, 626 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
627 "%20s : %02X:%02X:%02X:%02X:%02X:%02X\n", 627 pBase->macAddr);
628 "MacAddress",
629 pBase->macAddr[0], pBase->macAddr[1], pBase->macAddr[2],
630 pBase->macAddr[3], pBase->macAddr[4], pBase->macAddr[5]);
631 if (len > size) 628 if (len > size)
632 len = size; 629 len = size;
633 630
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index 61e6d3950718..3bea7ea86f0a 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -754,6 +754,7 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
754 IEEE80211_HW_RX_INCLUDES_FCS | 754 IEEE80211_HW_RX_INCLUDES_FCS |
755 IEEE80211_HW_SUPPORTS_PS | 755 IEEE80211_HW_SUPPORTS_PS |
756 IEEE80211_HW_PS_NULLFUNC_STACK | 756 IEEE80211_HW_PS_NULLFUNC_STACK |
757 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
757 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; 758 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
758 759
759 hw->wiphy->interface_modes = 760 hw->wiphy->interface_modes =
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 7b7796895432..7212acb2bd6c 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -1294,11 +1294,16 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
1294 u32 rfilt; 1294 u32 rfilt;
1295 1295
1296 mutex_lock(&priv->mutex); 1296 mutex_lock(&priv->mutex);
1297 ath9k_htc_ps_wakeup(priv);
1298
1299 changed_flags &= SUPPORTED_FILTERS; 1297 changed_flags &= SUPPORTED_FILTERS;
1300 *total_flags &= SUPPORTED_FILTERS; 1298 *total_flags &= SUPPORTED_FILTERS;
1301 1299
1300 if (priv->op_flags & OP_INVALID) {
1301 ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_ANY,
1302 "Unable to configure filter on invalid state\n");
1303 return;
1304 }
1305 ath9k_htc_ps_wakeup(priv);
1306
1302 priv->rxfilter = *total_flags; 1307 priv->rxfilter = *total_flags;
1303 rfilt = ath9k_htc_calcrxfilter(priv); 1308 rfilt = ath9k_htc_calcrxfilter(priv);
1304 ath9k_hw_setrxfilter(priv->ah, rfilt); 1309 ath9k_hw_setrxfilter(priv->ah, rfilt);
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index 2f3e07263fcb..cb29e8875386 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -39,11 +39,6 @@ static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
39 ath9k_hw_ops(ah)->set_desc_link(ds, link); 39 ath9k_hw_ops(ah)->set_desc_link(ds, link);
40} 40}
41 41
42static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
43 u32 **link)
44{
45 ath9k_hw_ops(ah)->get_desc_link(ds, link);
46}
47static inline bool ath9k_hw_calibrate(struct ath_hw *ah, 42static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
48 struct ath9k_channel *chan, 43 struct ath9k_channel *chan,
49 u8 rxchainmask, 44 u8 rxchainmask,
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 1be7c8bbef84..8006ce0c7357 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -87,7 +87,10 @@ static void ath9k_hw_set_clockrate(struct ath_hw *ah)
87 struct ath_common *common = ath9k_hw_common(ah); 87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate; 88 unsigned int clockrate;
89 89
90 if (!ah->curchan) /* should really check for CCK instead */ 90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
92 clockrate = 117;
93 else if (!ah->curchan) /* should really check for CCK instead */
91 clockrate = ATH9K_CLOCK_RATE_CCK; 94 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ) 95 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; 96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
@@ -99,6 +102,13 @@ static void ath9k_hw_set_clockrate(struct ath_hw *ah)
99 if (conf_is_ht40(conf)) 102 if (conf_is_ht40(conf))
100 clockrate *= 2; 103 clockrate *= 2;
101 104
105 if (ah->curchan) {
106 if (IS_CHAN_HALF_RATE(ah->curchan))
107 clockrate /= 2;
108 if (IS_CHAN_QUARTER_RATE(ah->curchan))
109 clockrate /= 4;
110 }
111
102 common->clockrate = clockrate; 112 common->clockrate = clockrate;
103} 113}
104 114
@@ -251,6 +261,15 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
251 case AR5416_AR9100_DEVID: 261 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100; 262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
253 break; 263 break;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (ah->get_mac_revision) {
267 ah->hw_version.macRev = ah->get_mac_revision();
268 } else {
269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
271 }
272 return;
254 case AR9300_DEVID_AR9340: 273 case AR9300_DEVID_AR9340:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9340; 274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
256 val = REG_READ(ah, AR_SREV); 275 val = REG_READ(ah, AR_SREV);
@@ -551,6 +570,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
551 case AR_SREV_VERSION_9287: 570 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271: 571 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300: 572 case AR_SREV_VERSION_9300:
573 case AR_SREV_VERSION_9330:
554 case AR_SREV_VERSION_9485: 574 case AR_SREV_VERSION_9485:
555 case AR_SREV_VERSION_9340: 575 case AR_SREV_VERSION_9340:
556 break; 576 break;
@@ -561,7 +581,8 @@ static int __ath9k_hw_init(struct ath_hw *ah)
561 return -EOPNOTSUPP; 581 return -EOPNOTSUPP;
562 } 582 }
563 583
564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah)) 584 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
585 AR_SREV_9330(ah))
565 ah->is_pciexpress = false; 586 ah->is_pciexpress = false;
566 587
567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 588 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
@@ -604,7 +625,10 @@ static int __ath9k_hw_init(struct ath_hw *ah)
604 else 625 else
605 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); 626 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
606 627
607 ah->bb_watchdog_timeout_ms = 25; 628 if (AR_SREV_9330(ah))
629 ah->bb_watchdog_timeout_ms = 85;
630 else
631 ah->bb_watchdog_timeout_ms = 25;
608 632
609 common->state = ATH_HW_INITIALIZED; 633 common->state = ATH_HW_INITIALIZED;
610 634
@@ -630,6 +654,7 @@ int ath9k_hw_init(struct ath_hw *ah)
630 case AR2427_DEVID_PCIE: 654 case AR2427_DEVID_PCIE:
631 case AR9300_DEVID_PCIE: 655 case AR9300_DEVID_PCIE:
632 case AR9300_DEVID_AR9485_PCIE: 656 case AR9300_DEVID_AR9485_PCIE:
657 case AR9300_DEVID_AR9330:
633 case AR9300_DEVID_AR9340: 658 case AR9300_DEVID_AR9340:
634 break; 659 break;
635 default: 660 default:
@@ -722,6 +747,39 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, 747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
723 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); 748 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
724 udelay(1000); 749 udelay(1000);
750 } else if (AR_SREV_9330(ah)) {
751 u32 ddr_dpll2, pll_control2, kd;
752
753 if (ah->is_clk_25mhz) {
754 ddr_dpll2 = 0x18e82f01;
755 pll_control2 = 0xe04a3d;
756 kd = 0x1d;
757 } else {
758 ddr_dpll2 = 0x19e82f01;
759 pll_control2 = 0x886666;
760 kd = 0x3d;
761 }
762
763 /* program DDR PLL ki and kd value */
764 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
765
766 /* program DDR PLL phase_shift */
767 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
768 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
769
770 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
771 udelay(1000);
772
773 /* program refdiv, nint, frac to RTC register */
774 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
775
776 /* program BB PLL kd and ki value */
777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
778 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
779
780 /* program BB PLL phase_shift */
781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
782 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
725 } else if (AR_SREV_9340(ah)) { 783 } else if (AR_SREV_9340(ah)) {
726 u32 regval, pll2_divint, pll2_divfrac, refdiv; 784 u32 regval, pll2_divint, pll2_divfrac, refdiv;
727 785
@@ -763,7 +821,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
763 821
764 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 822 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
765 823
766 if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) 824 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
767 udelay(1000); 825 udelay(1000);
768 826
769 /* Switch the core clock for ar9271 to 117Mhz */ 827 /* Switch the core clock for ar9271 to 117Mhz */
@@ -847,6 +905,13 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
847 } 905 }
848} 906}
849 907
908static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
909{
910 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
911 val = min(val, (u32) 0xFFFF);
912 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
913}
914
850static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 915static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
851{ 916{
852 u32 val = ath9k_hw_mac_to_clks(ah, us); 917 u32 val = ath9k_hw_mac_to_clks(ah, us);
@@ -884,25 +949,60 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
884 949
885void ath9k_hw_init_global_settings(struct ath_hw *ah) 950void ath9k_hw_init_global_settings(struct ath_hw *ah)
886{ 951{
887 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; 952 struct ath_common *common = ath9k_hw_common(ah);
953 struct ieee80211_conf *conf = &common->hw->conf;
954 const struct ath9k_channel *chan = ah->curchan;
888 int acktimeout; 955 int acktimeout;
889 int slottime; 956 int slottime;
890 int sifstime; 957 int sifstime;
958 int rx_lat = 0, tx_lat = 0, eifs = 0;
959 u32 reg;
891 960
892 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 961 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
893 ah->misc_mode); 962 ah->misc_mode);
894 963
964 if (!chan)
965 return;
966
895 if (ah->misc_mode != 0) 967 if (ah->misc_mode != 0)
896 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); 968 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
897 969
898 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) 970 rx_lat = 37;
899 sifstime = 16; 971 tx_lat = 54;
900 else 972
901 sifstime = 10; 973 if (IS_CHAN_HALF_RATE(chan)) {
974 eifs = 175;
975 rx_lat *= 2;
976 tx_lat *= 2;
977 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
978 tx_lat += 11;
979
980 slottime = 13;
981 sifstime = 32;
982 } else if (IS_CHAN_QUARTER_RATE(chan)) {
983 eifs = 340;
984 rx_lat *= 4;
985 tx_lat *= 4;
986 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
987 tx_lat += 22;
988
989 slottime = 21;
990 sifstime = 64;
991 } else {
992 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS);
993 reg = REG_READ(ah, AR_USEC);
994 rx_lat = MS(reg, AR_USEC_RX_LAT);
995 tx_lat = MS(reg, AR_USEC_TX_LAT);
996
997 slottime = ah->slottime;
998 if (IS_CHAN_5GHZ(chan))
999 sifstime = 16;
1000 else
1001 sifstime = 10;
1002 }
902 1003
903 /* As defined by IEEE 802.11-2007 17.3.8.6 */ 1004 /* As defined by IEEE 802.11-2007 17.3.8.6 */
904 slottime = ah->slottime + 3 * ah->coverage_class; 1005 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
905 acktimeout = slottime + sifstime;
906 1006
907 /* 1007 /*
908 * Workaround for early ACK timeouts, add an offset to match the 1008 * Workaround for early ACK timeouts, add an offset to match the
@@ -914,11 +1014,20 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
914 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) 1014 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
915 acktimeout += 64 - sifstime - ah->slottime; 1015 acktimeout += 64 - sifstime - ah->slottime;
916 1016
917 ath9k_hw_setslottime(ah, ah->slottime); 1017 ath9k_hw_set_sifs_time(ah, sifstime);
1018 ath9k_hw_setslottime(ah, slottime);
918 ath9k_hw_set_ack_timeout(ah, acktimeout); 1019 ath9k_hw_set_ack_timeout(ah, acktimeout);
919 ath9k_hw_set_cts_timeout(ah, acktimeout); 1020 ath9k_hw_set_cts_timeout(ah, acktimeout);
920 if (ah->globaltxtimeout != (u32) -1) 1021 if (ah->globaltxtimeout != (u32) -1)
921 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); 1022 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1023
1024 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1025 REG_RMW(ah, AR_USEC,
1026 (common->clockrate - 1) |
1027 SM(rx_lat, AR_USEC_RX_LAT) |
1028 SM(tx_lat, AR_USEC_TX_LAT),
1029 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1030
922} 1031}
923EXPORT_SYMBOL(ath9k_hw_init_global_settings); 1032EXPORT_SYMBOL(ath9k_hw_init_global_settings);
924 1033
@@ -1114,6 +1223,41 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1114 rst_flags |= AR_RTC_RC_MAC_COLD; 1223 rst_flags |= AR_RTC_RC_MAC_COLD;
1115 } 1224 }
1116 1225
1226 if (AR_SREV_9330(ah)) {
1227 int npend = 0;
1228 int i;
1229
1230 /* AR9330 WAR:
1231 * call external reset function to reset WMAC if:
1232 * - doing a cold reset
1233 * - we have pending frames in the TX queues
1234 */
1235
1236 for (i = 0; i < AR_NUM_QCU; i++) {
1237 npend = ath9k_hw_numtxpending(ah, i);
1238 if (npend)
1239 break;
1240 }
1241
1242 if (ah->external_reset &&
1243 (npend || type == ATH9K_RESET_COLD)) {
1244 int reset_err = 0;
1245
1246 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1247 "reset MAC via external reset\n");
1248
1249 reset_err = ah->external_reset();
1250 if (reset_err) {
1251 ath_err(ath9k_hw_common(ah),
1252 "External reset failed, err=%d\n",
1253 reset_err);
1254 return false;
1255 }
1256
1257 REG_WRITE(ah, AR_RTC_RESET, 1);
1258 }
1259 }
1260
1117 REG_WRITE(ah, AR_RTC_RC, rst_flags); 1261 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1118 1262
1119 REGWRITE_BUFFER_FLUSH(ah); 1263 REGWRITE_BUFFER_FLUSH(ah);
@@ -1487,9 +1631,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1487 1631
1488 ath9k_hw_init_global_settings(ah); 1632 ath9k_hw_init_global_settings(ah);
1489 1633
1490 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1634 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1491 ar9002_hw_update_async_fifo(ah); 1635 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1492 ar9002_hw_enable_wep_aggregation(ah); 1636 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1637 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1638 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1639 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1640 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1493 } 1641 }
1494 1642
1495 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); 1643 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
@@ -1545,7 +1693,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1545 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1693 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1546 } 1694 }
1547#ifdef __BIG_ENDIAN 1695#ifdef __BIG_ENDIAN
1548 else if (AR_SREV_9340(ah)) 1696 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1549 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); 1697 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1550 else 1698 else
1551 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); 1699 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
@@ -1785,16 +1933,16 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1785 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); 1933 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1786 1934
1787 REG_WRITE(ah, AR_BEACON_PERIOD, 1935 REG_WRITE(ah, AR_BEACON_PERIOD,
1788 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1936 TU_TO_USEC(bs->bs_intval));
1789 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, 1937 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1790 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); 1938 TU_TO_USEC(bs->bs_intval));
1791 1939
1792 REGWRITE_BUFFER_FLUSH(ah); 1940 REGWRITE_BUFFER_FLUSH(ah);
1793 1941
1794 REG_RMW_FIELD(ah, AR_RSSI_THR, 1942 REG_RMW_FIELD(ah, AR_RSSI_THR,
1795 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); 1943 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1796 1944
1797 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; 1945 beaconintval = bs->bs_intval;
1798 1946
1799 if (bs->bs_sleepduration > beaconintval) 1947 if (bs->bs_sleepduration > beaconintval)
1800 beaconintval = bs->bs_sleepduration; 1948 beaconintval = bs->bs_sleepduration;
@@ -1849,12 +1997,22 @@ EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1849/* HW Capabilities */ 1997/* HW Capabilities */
1850/*******************/ 1998/*******************/
1851 1999
2000static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2001{
2002 eeprom_chainmask &= chip_chainmask;
2003 if (eeprom_chainmask)
2004 return eeprom_chainmask;
2005 else
2006 return chip_chainmask;
2007}
2008
1852int ath9k_hw_fill_cap_info(struct ath_hw *ah) 2009int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1853{ 2010{
1854 struct ath9k_hw_capabilities *pCap = &ah->caps; 2011 struct ath9k_hw_capabilities *pCap = &ah->caps;
1855 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 2012 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1856 struct ath_common *common = ath9k_hw_common(ah); 2013 struct ath_common *common = ath9k_hw_common(ah);
1857 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 2014 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2015 unsigned int chip_chainmask;
1858 2016
1859 u16 eeval; 2017 u16 eeval;
1860 u8 ant_div_ctl1, tx_chainmask, rx_chainmask; 2018 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
@@ -1891,6 +2049,15 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1891 if (eeval & AR5416_OPFLAGS_11G) 2049 if (eeval & AR5416_OPFLAGS_11G)
1892 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; 2050 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1893 2051
2052 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2053 chip_chainmask = 1;
2054 else if (!AR_SREV_9280_20_OR_LATER(ah))
2055 chip_chainmask = 7;
2056 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2057 chip_chainmask = 3;
2058 else
2059 chip_chainmask = 7;
2060
1894 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); 2061 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1895 /* 2062 /*
1896 * For AR9271 we will temporarilly uses the rx chainmax as read from 2063 * For AR9271 we will temporarilly uses the rx chainmax as read from
@@ -1907,6 +2074,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1907 /* Use rx_chainmask from EEPROM. */ 2074 /* Use rx_chainmask from EEPROM. */
1908 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); 2075 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1909 2076
2077 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2078 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2079
1910 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 2080 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1911 2081
1912 /* enable key search for every frame in an aggregate */ 2082 /* enable key search for every frame in an aggregate */
@@ -1983,7 +2153,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1983 2153
1984 if (AR_SREV_9300_20_OR_LATER(ah)) { 2154 if (AR_SREV_9300_20_OR_LATER(ah)) {
1985 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; 2155 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1986 if (!AR_SREV_9485(ah)) 2156 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
1987 pCap->hw_caps |= ATH9K_HW_CAP_LDPC; 2157 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1988 2158
1989 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; 2159 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
@@ -1996,10 +2166,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1996 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; 2166 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1997 } else { 2167 } else {
1998 pCap->tx_desc_len = sizeof(struct ath_desc); 2168 pCap->tx_desc_len = sizeof(struct ath_desc);
1999 if (AR_SREV_9280_20(ah) && 2169 if (AR_SREV_9280_20(ah))
2000 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2001 AR5416_EEP_MINOR_VER_16) ||
2002 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2003 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; 2170 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2004 } 2171 }
2005 2172
@@ -2025,7 +2192,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2025 } 2192 }
2026 2193
2027 2194
2028 if (AR_SREV_9485(ah)) { 2195 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2029 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); 2196 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2030 /* 2197 /*
2031 * enable the diversity-combining algorithm only when 2198 * enable the diversity-combining algorithm only when
@@ -2574,6 +2741,7 @@ static struct {
2574 { AR_SREV_VERSION_9287, "9287" }, 2741 { AR_SREV_VERSION_9287, "9287" },
2575 { AR_SREV_VERSION_9271, "9271" }, 2742 { AR_SREV_VERSION_9271, "9271" },
2576 { AR_SREV_VERSION_9300, "9300" }, 2743 { AR_SREV_VERSION_9300, "9300" },
2744 { AR_SREV_VERSION_9330, "9330" },
2577 { AR_SREV_VERSION_9485, "9485" }, 2745 { AR_SREV_VERSION_9485, "9485" },
2578}; 2746};
2579 2747
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 4b157c53d1a8..6acd0f975ae1 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -45,6 +45,7 @@
45#define AR9300_DEVID_PCIE 0x0030 45#define AR9300_DEVID_PCIE 0x0030
46#define AR9300_DEVID_AR9340 0x0031 46#define AR9300_DEVID_AR9340 0x0031
47#define AR9300_DEVID_AR9485_PCIE 0x0032 47#define AR9300_DEVID_AR9485_PCIE 0x0032
48#define AR9300_DEVID_AR9330 0x0035
48 49
49#define AR5416_AR9100_DEVID 0x000b 50#define AR5416_AR9100_DEVID 0x000b
50 51
@@ -142,6 +143,8 @@
142#define AR_KEYTABLE_SIZE 128 143#define AR_KEYTABLE_SIZE 128
143#define POWER_UP_TIME 10000 144#define POWER_UP_TIME 10000
144#define SPUR_RSSI_THRESH 40 145#define SPUR_RSSI_THRESH 40
146#define UPPER_5G_SUB_BAND_START 5700
147#define MID_5G_SUB_BAND_START 5400
145 148
146#define CAB_TIMEOUT_VAL 10 149#define CAB_TIMEOUT_VAL 10
147#define BEACON_TIMEOUT_VAL 10 150#define BEACON_TIMEOUT_VAL 10
@@ -157,8 +160,9 @@
157#define ATH9K_HW_RX_HP_QDEPTH 16 160#define ATH9K_HW_RX_HP_QDEPTH 16
158#define ATH9K_HW_RX_LP_QDEPTH 128 161#define ATH9K_HW_RX_LP_QDEPTH 128
159 162
160#define PAPRD_GAIN_TABLE_ENTRIES 32 163#define PAPRD_GAIN_TABLE_ENTRIES 32
161#define PAPRD_TABLE_SZ 24 164#define PAPRD_TABLE_SZ 24
165#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
162 166
163enum ath_hw_txq_subtype { 167enum ath_hw_txq_subtype {
164 ATH_TXQ_AC_BE = 0, 168 ATH_TXQ_AC_BE = 0,
@@ -403,7 +407,6 @@ struct ath9k_beacon_state {
403 u32 bs_nexttbtt; 407 u32 bs_nexttbtt;
404 u32 bs_nextdtim; 408 u32 bs_nextdtim;
405 u32 bs_intval; 409 u32 bs_intval;
406#define ATH9K_BEACON_PERIOD 0x0000ffff
407#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ 410#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
408 u32 bs_dtimperiod; 411 u32 bs_dtimperiod;
409 u16 bs_cfpperiod; 412 u16 bs_cfpperiod;
@@ -603,7 +606,6 @@ struct ath_hw_ops {
603 int power_off); 606 int power_off);
604 void (*rx_enable)(struct ath_hw *ah); 607 void (*rx_enable)(struct ath_hw *ah);
605 void (*set_desc_link)(void *ds, u32 link); 608 void (*set_desc_link)(void *ds, u32 link);
606 void (*get_desc_link)(void *ds, u32 **link);
607 bool (*calibrate)(struct ath_hw *ah, 609 bool (*calibrate)(struct ath_hw *ah,
608 struct ath9k_channel *chan, 610 struct ath9k_channel *chan,
609 u8 rxchainmask, 611 u8 rxchainmask,
@@ -862,6 +864,8 @@ struct ath_hw {
862 u32 ent_mode; 864 u32 ent_mode;
863 865
864 bool is_clk_25mhz; 866 bool is_clk_25mhz;
867 int (*get_mac_revision)(void);
868 int (*external_reset)(void);
865}; 869};
866 870
867struct ath_bus_ops { 871struct ath_bus_ops {
@@ -981,8 +985,6 @@ void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
981void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); 985void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
982int ar9002_hw_rf_claim(struct ath_hw *ah); 986int ar9002_hw_rf_claim(struct ath_hw *ah);
983void ar9002_hw_enable_async_fifo(struct ath_hw *ah); 987void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
984void ar9002_hw_update_async_fifo(struct ath_hw *ah);
985void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
986 988
987/* 989/*
988 * Code specific to AR9003, we stuff these here to avoid callbacks 990 * Code specific to AR9003, we stuff these here to avoid callbacks
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 45c585a337e9..ac5107172f94 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <linux/dma-mapping.h>
17#include <linux/slab.h> 18#include <linux/slab.h>
18#include <linux/ath9k_platform.h> 19#include <linux/ath9k_platform.h>
19 20
@@ -196,6 +197,19 @@ static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
196 return val; 197 return val;
197} 198}
198 199
200static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
201 u32 set, u32 clr)
202{
203 u32 val;
204
205 val = ioread32(sc->mem + reg_offset);
206 val &= ~clr;
207 val |= set;
208 iowrite32(val, sc->mem + reg_offset);
209
210 return val;
211}
212
199static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) 213static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
200{ 214{
201 struct ath_hw *ah = (struct ath_hw *) hw_priv; 215 struct ath_hw *ah = (struct ath_hw *) hw_priv;
@@ -204,16 +218,12 @@ static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 cl
204 unsigned long uninitialized_var(flags); 218 unsigned long uninitialized_var(flags);
205 u32 val; 219 u32 val;
206 220
207 if (ah->config.serialize_regmode == SER_REG_MODE_ON) 221 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
208 spin_lock_irqsave(&sc->sc_serial_rw, flags); 222 spin_lock_irqsave(&sc->sc_serial_rw, flags);
209 223 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
210 val = ioread32(sc->mem + reg_offset);
211 val &= ~clr;
212 val |= set;
213 iowrite32(val, sc->mem + reg_offset);
214
215 if (ah->config.serialize_regmode == SER_REG_MODE_ON)
216 spin_unlock_irqrestore(&sc->sc_serial_rw, flags); 224 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
225 } else
226 val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
217 227
218 return val; 228 return val;
219} 229}
@@ -245,7 +255,7 @@ static void setup_ht_cap(struct ath_softc *sc,
245 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 255 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
246 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 256 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
247 257
248 if (AR_SREV_9485(ah)) 258 if (AR_SREV_9330(ah) || AR_SREV_9485(ah))
249 max_streams = 1; 259 max_streams = 1;
250 else if (AR_SREV_9300_20_OR_LATER(ah)) 260 else if (AR_SREV_9300_20_OR_LATER(ah))
251 max_streams = 3; 261 max_streams = 3;
@@ -298,10 +308,6 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
298 struct list_head *head, const char *name, 308 struct list_head *head, const char *name,
299 int nbuf, int ndesc, bool is_tx) 309 int nbuf, int ndesc, bool is_tx)
300{ 310{
301#define DS2PHYS(_dd, _ds) \
302 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
303#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
304#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
305 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 311 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
306 u8 *ds; 312 u8 *ds;
307 struct ath_buf *bf; 313 struct ath_buf *bf;
@@ -396,9 +402,6 @@ fail2:
396fail: 402fail:
397 memset(dd, 0, sizeof(*dd)); 403 memset(dd, 0, sizeof(*dd));
398 return error; 404 return error;
399#undef ATH_DESC_4KB_BOUND_CHECK
400#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
401#undef DS2PHYS
402} 405}
403 406
404void ath9k_init_crypto(struct ath_softc *sc) 407void ath9k_init_crypto(struct ath_softc *sc)
@@ -519,7 +522,6 @@ static void ath9k_init_misc(struct ath_softc *sc)
519{ 522{
520 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 523 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
521 int i = 0; 524 int i = 0;
522
523 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); 525 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
524 526
525 sc->config.txpowlimit = ATH_TXPOWER_MAX; 527 sc->config.txpowlimit = ATH_TXPOWER_MAX;
@@ -575,6 +577,8 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
575 sc->sc_ah->gpio_val = pdata->gpio_val; 577 sc->sc_ah->gpio_val = pdata->gpio_val;
576 sc->sc_ah->led_pin = pdata->led_pin; 578 sc->sc_ah->led_pin = pdata->led_pin;
577 ah->is_clk_25mhz = pdata->is_clk_25mhz; 579 ah->is_clk_25mhz = pdata->is_clk_25mhz;
580 ah->get_mac_revision = pdata->get_mac_revision;
581 ah->external_reset = pdata->external_reset;
578 } 582 }
579 583
580 common = ath9k_hw_common(ah); 584 common = ath9k_hw_common(ah);
@@ -585,6 +589,7 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
585 common->priv = sc; 589 common->priv = sc;
586 common->debug_mask = ath9k_debug; 590 common->debug_mask = ath9k_debug;
587 common->btcoex_enabled = ath9k_btcoex_enable == 1; 591 common->btcoex_enabled = ath9k_btcoex_enable == 1;
592 common->disable_ani = false;
588 spin_lock_init(&common->cc_lock); 593 spin_lock_init(&common->cc_lock);
589 594
590 spin_lock_init(&sc->sc_serial_rw); 595 spin_lock_init(&sc->sc_serial_rw);
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index c2091f1f4096..b6b523a897e5 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -645,8 +645,7 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
645 rs->rs_status |= ATH9K_RXERR_DECRYPT; 645 rs->rs_status |= ATH9K_RXERR_DECRYPT;
646 else if (ads.ds_rxstatus8 & AR_MichaelErr) 646 else if (ads.ds_rxstatus8 & AR_MichaelErr)
647 rs->rs_status |= ATH9K_RXERR_MIC; 647 rs->rs_status |= ATH9K_RXERR_MIC;
648 648 else if (ads.ds_rxstatus8 & AR_KeyMiss)
649 if (ads.ds_rxstatus8 & AR_KeyMiss)
650 rs->rs_status |= ATH9K_RXERR_DECRYPT; 649 rs->rs_status |= ATH9K_RXERR_DECRYPT;
651 } 650 }
652 651
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 2ca351fe6d3c..9098aaad97a9 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -62,14 +62,12 @@ static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
62 62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq)) 63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true; 64 pending = true;
65 else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
66 pending = !list_empty(&txq->txq_fifo_pending);
67 65
68 spin_unlock_bh(&txq->axq_lock); 66 spin_unlock_bh(&txq->axq_lock);
69 return pending; 67 return pending;
70} 68}
71 69
72bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
73{ 71{
74 unsigned long flags; 72 unsigned long flags;
75 bool ret; 73 bool ret;
@@ -136,7 +134,7 @@ void ath9k_ps_restore(struct ath_softc *sc)
136 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 134 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
137} 135}
138 136
139static void ath_start_ani(struct ath_common *common) 137void ath_start_ani(struct ath_common *common)
140{ 138{
141 struct ath_hw *ah = common->ah; 139 struct ath_hw *ah = common->ah;
142 unsigned long timestamp = jiffies_to_msecs(jiffies); 140 unsigned long timestamp = jiffies_to_msecs(jiffies);
@@ -219,7 +217,7 @@ static int ath_update_survey_stats(struct ath_softc *sc)
219 * by reseting the chip. To accomplish this we must first cleanup any pending 217 * by reseting the chip. To accomplish this we must first cleanup any pending
220 * DMA, then restart stuff. 218 * DMA, then restart stuff.
221*/ 219*/
222int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, 220static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
223 struct ath9k_channel *hchan) 221 struct ath9k_channel *hchan)
224{ 222{
225 struct ath_hw *ah = sc->sc_ah; 223 struct ath_hw *ah = sc->sc_ah;
@@ -302,7 +300,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
302 ath_set_beacon(sc); 300 ath_set_beacon(sc);
303 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); 301 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
304 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); 302 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
305 ath_start_ani(common); 303 if (!common->disable_ani)
304 ath_start_ani(common);
306 } 305 }
307 306
308 ps_restore: 307 ps_restore:
@@ -361,7 +360,7 @@ static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int
361 txctl.paprd = BIT(chain); 360 txctl.paprd = BIT(chain);
362 361
363 if (ath_tx_start(hw, skb, &txctl) != 0) { 362 if (ath_tx_start(hw, skb, &txctl) != 0) {
364 ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n"); 363 ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n");
365 dev_kfree_skb_any(skb); 364 dev_kfree_skb_any(skb);
366 return false; 365 return false;
367 } 366 }
@@ -370,7 +369,7 @@ static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int
370 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); 369 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
371 370
372 if (!time_left) 371 if (!time_left)
373 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE, 372 ath_dbg(common, ATH_DBG_CALIBRATE,
374 "Timeout waiting for paprd training on TX chain %d\n", 373 "Timeout waiting for paprd training on TX chain %d\n",
375 chain); 374 chain);
376 375
@@ -394,12 +393,14 @@ void ath_paprd_calibrate(struct work_struct *work)
394 if (!caldata) 393 if (!caldata)
395 return; 394 return;
396 395
396 ath9k_ps_wakeup(sc);
397
397 if (ar9003_paprd_init_table(ah) < 0) 398 if (ar9003_paprd_init_table(ah) < 0)
398 return; 399 goto fail_paprd;
399 400
400 skb = alloc_skb(len, GFP_KERNEL); 401 skb = alloc_skb(len, GFP_KERNEL);
401 if (!skb) 402 if (!skb)
402 return; 403 goto fail_paprd;
403 404
404 skb_put(skb, len); 405 skb_put(skb, len);
405 memset(skb->data, 0, len); 406 memset(skb->data, 0, len);
@@ -411,7 +412,6 @@ void ath_paprd_calibrate(struct work_struct *work)
411 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); 412 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
412 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); 413 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
413 414
414 ath9k_ps_wakeup(sc);
415 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { 415 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
416 if (!(common->tx_chainmask & BIT(chain))) 416 if (!(common->tx_chainmask & BIT(chain)))
417 continue; 417 continue;
@@ -431,11 +431,18 @@ void ath_paprd_calibrate(struct work_struct *work)
431 if (!ath_paprd_send_frame(sc, skb, chain)) 431 if (!ath_paprd_send_frame(sc, skb, chain))
432 goto fail_paprd; 432 goto fail_paprd;
433 433
434 if (!ar9003_paprd_is_done(ah)) 434 if (!ar9003_paprd_is_done(ah)) {
435 ath_dbg(common, ATH_DBG_CALIBRATE,
436 "PAPRD not yet done on chain %d\n", chain);
435 break; 437 break;
438 }
436 439
437 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) 440 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
441 ath_dbg(common, ATH_DBG_CALIBRATE,
442 "PAPRD create curve failed on chain %d\n",
443 chain);
438 break; 444 break;
445 }
439 446
440 chain_ok = 1; 447 chain_ok = 1;
441 } 448 }
@@ -515,24 +522,19 @@ void ath_ani_calibrate(unsigned long data)
515 common->ani.checkani_timer = timestamp; 522 common->ani.checkani_timer = timestamp;
516 } 523 }
517 524
518 /* Skip all processing if there's nothing to do. */ 525 /* Call ANI routine if necessary */
519 if (longcal || shortcal || aniflag) { 526 if (aniflag) {
520 /* Call ANI routine if necessary */ 527 spin_lock_irqsave(&common->cc_lock, flags);
521 if (aniflag) { 528 ath9k_hw_ani_monitor(ah, ah->curchan);
522 spin_lock_irqsave(&common->cc_lock, flags); 529 ath_update_survey_stats(sc);
523 ath9k_hw_ani_monitor(ah, ah->curchan); 530 spin_unlock_irqrestore(&common->cc_lock, flags);
524 ath_update_survey_stats(sc); 531 }
525 spin_unlock_irqrestore(&common->cc_lock, flags);
526 }
527 532
528 /* Perform calibration if necessary */ 533 /* Perform calibration if necessary */
529 if (longcal || shortcal) { 534 if (longcal || shortcal) {
530 common->ani.caldone = 535 common->ani.caldone =
531 ath9k_hw_calibrate(ah, 536 ath9k_hw_calibrate(ah, ah->curchan,
532 ah->curchan, 537 common->rx_chainmask, longcal);
533 common->rx_chainmask,
534 longcal);
535 }
536 } 538 }
537 539
538 ath9k_ps_restore(sc); 540 ath9k_ps_restore(sc);
@@ -615,8 +617,11 @@ void ath_hw_check(struct work_struct *work)
615 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " 617 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
616 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); 618 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
617 if (busy >= 99) { 619 if (busy >= 99) {
618 if (++sc->hw_busy_count >= 3) 620 if (++sc->hw_busy_count >= 3) {
621 spin_lock_bh(&sc->sc_pcu_lock);
619 ath_reset(sc, true); 622 ath_reset(sc, true);
623 spin_unlock_bh(&sc->sc_pcu_lock);
624 }
620 } else if (busy >= 0) 625 } else if (busy >= 0)
621 sc->hw_busy_count = 0; 626 sc->hw_busy_count = 0;
622 627
@@ -635,7 +640,9 @@ static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
635 /* Rx is hung for more than 500ms. Reset it */ 640 /* Rx is hung for more than 500ms. Reset it */
636 ath_dbg(common, ATH_DBG_RESET, 641 ath_dbg(common, ATH_DBG_RESET,
637 "Possible RX hang, resetting"); 642 "Possible RX hang, resetting");
643 spin_lock_bh(&sc->sc_pcu_lock);
638 ath_reset(sc, true); 644 ath_reset(sc, true);
645 spin_unlock_bh(&sc->sc_pcu_lock);
639 count = 0; 646 count = 0;
640 } 647 }
641 } else 648 } else
@@ -672,7 +679,9 @@ void ath9k_tasklet(unsigned long data)
672 679
673 if ((status & ATH9K_INT_FATAL) || 680 if ((status & ATH9K_INT_FATAL) ||
674 (status & ATH9K_INT_BB_WATCHDOG)) { 681 (status & ATH9K_INT_BB_WATCHDOG)) {
682 spin_lock(&sc->sc_pcu_lock);
675 ath_reset(sc, true); 683 ath_reset(sc, true);
684 spin_unlock(&sc->sc_pcu_lock);
676 return; 685 return;
677 } 686 }
678 687
@@ -868,7 +877,7 @@ chip_reset:
868#undef SCHED_INTR 877#undef SCHED_INTR
869} 878}
870 879
871void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) 880static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
872{ 881{
873 struct ath_hw *ah = sc->sc_ah; 882 struct ath_hw *ah = sc->sc_ah;
874 struct ath_common *common = ath9k_hw_common(ah); 883 struct ath_common *common = ath9k_hw_common(ah);
@@ -974,10 +983,10 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
974 sc->hw_busy_count = 0; 983 sc->hw_busy_count = 0;
975 984
976 /* Stop ANI */ 985 /* Stop ANI */
986
977 del_timer_sync(&common->ani.timer); 987 del_timer_sync(&common->ani.timer);
978 988
979 ath9k_ps_wakeup(sc); 989 ath9k_ps_wakeup(sc);
980 spin_lock_bh(&sc->sc_pcu_lock);
981 990
982 ieee80211_stop_queues(hw); 991 ieee80211_stop_queues(hw);
983 992
@@ -1020,10 +1029,11 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1020 } 1029 }
1021 1030
1022 ieee80211_wake_queues(hw); 1031 ieee80211_wake_queues(hw);
1023 spin_unlock_bh(&sc->sc_pcu_lock);
1024 1032
1025 /* Start ANI */ 1033 /* Start ANI */
1026 ath_start_ani(common); 1034 if (!common->disable_ani)
1035 ath_start_ani(common);
1036
1027 ath9k_ps_restore(sc); 1037 ath9k_ps_restore(sc);
1028 1038
1029 return r; 1039 return r;
@@ -1261,7 +1271,6 @@ static void ath9k_stop(struct ieee80211_hw *hw)
1261 1271
1262 /* disable HAL and put h/w to sleep */ 1272 /* disable HAL and put h/w to sleep */
1263 ath9k_hw_disable(ah); 1273 ath9k_hw_disable(ah);
1264 ath9k_hw_configpcipowersave(ah, 1, 1);
1265 1274
1266 spin_unlock_bh(&sc->sc_pcu_lock); 1275 spin_unlock_bh(&sc->sc_pcu_lock);
1267 1276
@@ -1412,10 +1421,14 @@ static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1412 ath9k_hw_set_interrupts(ah, ah->imask); 1421 ath9k_hw_set_interrupts(ah, ah->imask);
1413 1422
1414 /* Set up ANI */ 1423 /* Set up ANI */
1415 if ((iter_data.naps + iter_data.nadhocs) > 0) { 1424 if (iter_data.naps > 0) {
1416 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1425 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1417 sc->sc_flags |= SC_OP_ANI_RUN; 1426
1418 ath_start_ani(common); 1427 if (!common->disable_ani) {
1428 sc->sc_flags |= SC_OP_ANI_RUN;
1429 ath_start_ani(common);
1430 }
1431
1419 } else { 1432 } else {
1420 sc->sc_flags &= ~SC_OP_ANI_RUN; 1433 sc->sc_flags &= ~SC_OP_ANI_RUN;
1421 del_timer_sync(&common->ani.timer); 1434 del_timer_sync(&common->ani.timer);
@@ -1952,50 +1965,38 @@ static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1952 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 1965 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1953 struct ath_vif *avp = (void *)vif->drv_priv; 1966 struct ath_vif *avp = (void *)vif->drv_priv;
1954 1967
1955 switch (sc->sc_ah->opmode) { 1968 /*
1956 case NL80211_IFTYPE_ADHOC: 1969 * Skip iteration if primary station vif's bss info
1957 /* There can be only one vif available */ 1970 * was not changed
1971 */
1972 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1973 return;
1974
1975 if (bss_conf->assoc) {
1976 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1977 avp->primary_sta_vif = true;
1958 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); 1978 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1959 common->curaid = bss_conf->aid; 1979 common->curaid = bss_conf->aid;
1960 ath9k_hw_write_associd(sc->sc_ah); 1980 ath9k_hw_write_associd(sc->sc_ah);
1961 /* configure beacon */ 1981 ath_dbg(common, ATH_DBG_CONFIG,
1962 if (bss_conf->enable_beacon)
1963 ath_beacon_config(sc, vif);
1964 break;
1965 case NL80211_IFTYPE_STATION:
1966 /*
1967 * Skip iteration if primary station vif's bss info
1968 * was not changed
1969 */
1970 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1971 break;
1972
1973 if (bss_conf->assoc) {
1974 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1975 avp->primary_sta_vif = true;
1976 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1977 common->curaid = bss_conf->aid;
1978 ath9k_hw_write_associd(sc->sc_ah);
1979 ath_dbg(common, ATH_DBG_CONFIG,
1980 "Bss Info ASSOC %d, bssid: %pM\n", 1982 "Bss Info ASSOC %d, bssid: %pM\n",
1981 bss_conf->aid, common->curbssid); 1983 bss_conf->aid, common->curbssid);
1982 ath_beacon_config(sc, vif); 1984 ath_beacon_config(sc, vif);
1983 /* 1985 /*
1984 * Request a re-configuration of Beacon related timers 1986 * Request a re-configuration of Beacon related timers
1985 * on the receipt of the first Beacon frame (i.e., 1987 * on the receipt of the first Beacon frame (i.e.,
1986 * after time sync with the AP). 1988 * after time sync with the AP).
1987 */ 1989 */
1988 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; 1990 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1989 /* Reset rssi stats */ 1991 /* Reset rssi stats */
1990 sc->last_rssi = ATH_RSSI_DUMMY_MARKER; 1992 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1991 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; 1993 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1992 1994
1995 if (!common->disable_ani) {
1993 sc->sc_flags |= SC_OP_ANI_RUN; 1996 sc->sc_flags |= SC_OP_ANI_RUN;
1994 ath_start_ani(common); 1997 ath_start_ani(common);
1995 } 1998 }
1996 break; 1999
1997 default:
1998 break;
1999 } 2000 }
2000} 2001}
2001 2002
@@ -2005,6 +2006,9 @@ static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2005 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 2006 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2006 struct ath_vif *avp = (void *)vif->drv_priv; 2007 struct ath_vif *avp = (void *)vif->drv_priv;
2007 2008
2009 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2010 return;
2011
2008 /* Reconfigure bss info */ 2012 /* Reconfigure bss info */
2009 if (avp->primary_sta_vif && !bss_conf->assoc) { 2013 if (avp->primary_sta_vif && !bss_conf->assoc) {
2010 ath_dbg(common, ATH_DBG_CONFIG, 2014 ath_dbg(common, ATH_DBG_CONFIG,
@@ -2023,8 +2027,7 @@ static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2023 * None of station vifs are associated. 2027 * None of station vifs are associated.
2024 * Clear bssid & aid 2028 * Clear bssid & aid
2025 */ 2029 */
2026 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && 2030 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
2027 !(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
2028 ath9k_hw_write_associd(sc->sc_ah); 2031 ath9k_hw_write_associd(sc->sc_ah);
2029 /* Stop ANI */ 2032 /* Stop ANI */
2030 sc->sc_flags &= ~SC_OP_ANI_RUN; 2033 sc->sc_flags &= ~SC_OP_ANI_RUN;
@@ -2054,6 +2057,26 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2054 common->curbssid, common->curaid); 2057 common->curbssid, common->curaid);
2055 } 2058 }
2056 2059
2060 if (changed & BSS_CHANGED_IBSS) {
2061 /* There can be only one vif available */
2062 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2063 common->curaid = bss_conf->aid;
2064 ath9k_hw_write_associd(sc->sc_ah);
2065
2066 if (bss_conf->ibss_joined) {
2067 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
2068
2069 if (!common->disable_ani) {
2070 sc->sc_flags |= SC_OP_ANI_RUN;
2071 ath_start_ani(common);
2072 }
2073
2074 } else {
2075 sc->sc_flags &= ~SC_OP_ANI_RUN;
2076 del_timer_sync(&common->ani.timer);
2077 }
2078 }
2079
2057 /* Enable transmission of beacons (AP, IBSS, MESH) */ 2080 /* Enable transmission of beacons (AP, IBSS, MESH) */
2058 if ((changed & BSS_CHANGED_BEACON) || 2081 if ((changed & BSS_CHANGED_BEACON) ||
2059 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { 2082 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
@@ -2308,9 +2331,9 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2308 ath9k_ps_wakeup(sc); 2331 ath9k_ps_wakeup(sc);
2309 spin_lock_bh(&sc->sc_pcu_lock); 2332 spin_lock_bh(&sc->sc_pcu_lock);
2310 drain_txq = ath_drain_all_txq(sc, false); 2333 drain_txq = ath_drain_all_txq(sc, false);
2311 spin_unlock_bh(&sc->sc_pcu_lock);
2312 if (!drain_txq) 2334 if (!drain_txq)
2313 ath_reset(sc, false); 2335 ath_reset(sc, false);
2336 spin_unlock_bh(&sc->sc_pcu_lock);
2314 ath9k_ps_restore(sc); 2337 ath9k_ps_restore(sc);
2315 ieee80211_wake_queues(hw); 2338 ieee80211_wake_queues(hw);
2316 2339
@@ -2334,7 +2357,7 @@ static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2334 return false; 2357 return false;
2335} 2358}
2336 2359
2337int ath9k_tx_last_beacon(struct ieee80211_hw *hw) 2360static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2338{ 2361{
2339 struct ath_softc *sc = hw->priv; 2362 struct ath_softc *sc = hw->priv;
2340 struct ath_hw *ah = sc->sc_ah; 2363 struct ath_hw *ah = sc->sc_ah;
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index ba7f36ab0a74..c04a6c3cac7f 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -379,7 +379,30 @@ static const struct ath_rate_table ar5416_11g_ratetable = {
379}; 379};
380 380
381static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table, 381static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
382 struct ieee80211_tx_rate *rate); 382 struct ieee80211_tx_rate *rate)
383{
384 int rix = 0, i = 0;
385 static const int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
386
387 if (!(rate->flags & IEEE80211_TX_RC_MCS))
388 return rate->idx;
389
390 while (i < ARRAY_SIZE(mcs_rix_off) && rate->idx > mcs_rix_off[i]) {
391 rix++; i++;
392 }
393
394 rix += rate->idx + rate_table->mcs_start;
395
396 if ((rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) &&
397 (rate->flags & IEEE80211_TX_RC_SHORT_GI))
398 rix = rate_table->info[rix].ht_index;
399 else if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
400 rix = rate_table->info[rix].sgi_index;
401 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
402 rix = rate_table->info[rix].cw40index;
403
404 return rix;
405}
383 406
384static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table, 407static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
385 struct ath_rate_priv *ath_rc_priv) 408 struct ath_rate_priv *ath_rc_priv)
@@ -533,7 +556,7 @@ static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv,
533 [valid_rate_count] = j; 556 [valid_rate_count] = j;
534 ath_rc_priv->valid_phy_ratecnt[phy] += 1; 557 ath_rc_priv->valid_phy_ratecnt[phy] += 1;
535 ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1); 558 ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
536 hi = A_MAX(hi, j); 559 hi = max(hi, j);
537 } 560 }
538 } 561 }
539 } 562 }
@@ -569,7 +592,7 @@ static u8 ath_rc_setvalid_htrates(struct ath_rate_priv *ath_rc_priv,
569 [ath_rc_priv->valid_phy_ratecnt[phy]] = j; 592 [ath_rc_priv->valid_phy_ratecnt[phy]] = j;
570 ath_rc_priv->valid_phy_ratecnt[phy] += 1; 593 ath_rc_priv->valid_phy_ratecnt[phy] += 1;
571 ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1); 594 ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
572 hi = A_MAX(hi, j); 595 hi = max(hi, j);
573 } 596 }
574 } 597 }
575 598
@@ -1080,31 +1103,6 @@ static void ath_rc_update_ht(struct ath_softc *sc,
1080 1103
1081} 1104}
1082 1105
1083static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
1084 struct ieee80211_tx_rate *rate)
1085{
1086 int rix = 0, i = 0;
1087 static const int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
1088
1089 if (!(rate->flags & IEEE80211_TX_RC_MCS))
1090 return rate->idx;
1091
1092 while (i < ARRAY_SIZE(mcs_rix_off) && rate->idx > mcs_rix_off[i]) {
1093 rix++; i++;
1094 }
1095
1096 rix += rate->idx + rate_table->mcs_start;
1097
1098 if ((rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) &&
1099 (rate->flags & IEEE80211_TX_RC_SHORT_GI))
1100 rix = rate_table->info[rix].ht_index;
1101 else if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
1102 rix = rate_table->info[rix].sgi_index;
1103 else if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1104 rix = rate_table->info[rix].cw40index;
1105
1106 return rix;
1107}
1108 1106
1109static void ath_rc_tx_status(struct ath_softc *sc, 1107static void ath_rc_tx_status(struct ath_softc *sc,
1110 struct ath_rate_priv *ath_rc_priv, 1108 struct ath_rate_priv *ath_rc_priv,
@@ -1228,7 +1226,7 @@ static void ath_rc_init(struct ath_softc *sc,
1228 ht_mcs, 1226 ht_mcs,
1229 ath_rc_priv->ht_cap); 1227 ath_rc_priv->ht_cap);
1230 } 1228 }
1231 hi = A_MAX(hi, hthi); 1229 hi = max(hi, hthi);
1232 } 1230 }
1233 1231
1234 ath_rc_priv->rate_table_size = hi + 1; 1232 ath_rc_priv->rate_table_size = hi + 1;
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index 07e35e59c9e3..9a4850154fb2 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <linux/dma-mapping.h>
17#include "ath9k.h" 18#include "ath9k.h"
18#include "ar9003_mac.h" 19#include "ar9003_mac.h"
19 20
@@ -39,6 +40,7 @@ static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
39 result = true; 40 result = true;
40 break; 41 break;
41 case 1: 42 case 1:
43 case 2:
42 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) && 44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
43 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) && 45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
44 (alt_rssi_avg >= (main_rssi_avg - 5))) || 46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
@@ -813,16 +815,19 @@ static bool ath9k_rx_accept(struct ath_common *common,
813 struct ath_rx_status *rx_stats, 815 struct ath_rx_status *rx_stats,
814 bool *decrypt_error) 816 bool *decrypt_error)
815{ 817{
816#define is_mc_or_valid_tkip_keyix ((is_mc || \ 818 bool is_mc, is_valid_tkip, strip_mic, mic_error;
817 (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \
818 test_bit(rx_stats->rs_keyix, common->tkip_keymap))))
819
820 struct ath_hw *ah = common->ah; 819 struct ath_hw *ah = common->ah;
821 __le16 fc; 820 __le16 fc;
822 u8 rx_status_len = ah->caps.rx_status_len; 821 u8 rx_status_len = ah->caps.rx_status_len;
823 822
824 fc = hdr->frame_control; 823 fc = hdr->frame_control;
825 824
825 is_mc = !!is_multicast_ether_addr(hdr->addr1);
826 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
827 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
828 strip_mic = is_valid_tkip && !(rx_stats->rs_status &
829 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC));
830
826 if (!rx_stats->rs_datalen) 831 if (!rx_stats->rs_datalen)
827 return false; 832 return false;
828 /* 833 /*
@@ -837,6 +842,11 @@ static bool ath9k_rx_accept(struct ath_common *common,
837 if (rx_stats->rs_more) 842 if (rx_stats->rs_more)
838 return true; 843 return true;
839 844
845 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
846 !ieee80211_has_morefrags(fc) &&
847 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
848 (rx_stats->rs_status & ATH9K_RXERR_MIC);
849
840 /* 850 /*
841 * The rx_stats->rs_status will not be set until the end of the 851 * The rx_stats->rs_status will not be set until the end of the
842 * chained descriptors so it can be ignored if rs_more is set. The 852 * chained descriptors so it can be ignored if rs_more is set. The
@@ -844,30 +854,18 @@ static bool ath9k_rx_accept(struct ath_common *common,
844 * descriptors. 854 * descriptors.
845 */ 855 */
846 if (rx_stats->rs_status != 0) { 856 if (rx_stats->rs_status != 0) {
847 if (rx_stats->rs_status & ATH9K_RXERR_CRC) 857 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
848 rxs->flag |= RX_FLAG_FAILED_FCS_CRC; 858 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
859 mic_error = false;
860 }
849 if (rx_stats->rs_status & ATH9K_RXERR_PHY) 861 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
850 return false; 862 return false;
851 863
852 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { 864 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
853 *decrypt_error = true; 865 *decrypt_error = true;
854 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { 866 mic_error = false;
855 bool is_mc;
856 /*
857 * The MIC error bit is only valid if the frame
858 * is not a control frame or fragment, and it was
859 * decrypted using a valid TKIP key.
860 */
861 is_mc = !!is_multicast_ether_addr(hdr->addr1);
862
863 if (!ieee80211_is_ctl(fc) &&
864 !ieee80211_has_morefrags(fc) &&
865 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
866 is_mc_or_valid_tkip_keyix)
867 rxs->flag |= RX_FLAG_MMIC_ERROR;
868 else
869 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
870 } 867 }
868
871 /* 869 /*
872 * Reject error frames with the exception of 870 * Reject error frames with the exception of
873 * decryption and MIC failures. For monitor mode, 871 * decryption and MIC failures. For monitor mode,
@@ -885,6 +883,18 @@ static bool ath9k_rx_accept(struct ath_common *common,
885 } 883 }
886 } 884 }
887 } 885 }
886
887 /*
888 * For unicast frames the MIC error bit can have false positives,
889 * so all MIC error reports need to be validated in software.
890 * False negatives are not common, so skip software verification
891 * if the hardware considers the MIC valid.
892 */
893 if (strip_mic)
894 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
895 else if (is_mc && mic_error)
896 rxs->flag |= RX_FLAG_MMIC_ERROR;
897
888 return true; 898 return true;
889} 899}
890 900
@@ -1075,39 +1085,39 @@ static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1075 antcomb->rssi_lna1 = main_rssi_avg; 1085 antcomb->rssi_lna1 = main_rssi_avg;
1076 1086
1077 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) { 1087 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1078 case (0x10): /* LNA2 A-B */ 1088 case 0x10: /* LNA2 A-B */
1079 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1089 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1080 antcomb->first_quick_scan_conf = 1090 antcomb->first_quick_scan_conf =
1081 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1091 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1082 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; 1092 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1083 break; 1093 break;
1084 case (0x20): /* LNA1 A-B */ 1094 case 0x20: /* LNA1 A-B */
1085 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1095 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1086 antcomb->first_quick_scan_conf = 1096 antcomb->first_quick_scan_conf =
1087 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1097 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1088 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; 1098 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1089 break; 1099 break;
1090 case (0x21): /* LNA1 LNA2 */ 1100 case 0x21: /* LNA1 LNA2 */
1091 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2; 1101 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1092 antcomb->first_quick_scan_conf = 1102 antcomb->first_quick_scan_conf =
1093 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1103 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1094 antcomb->second_quick_scan_conf = 1104 antcomb->second_quick_scan_conf =
1095 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1105 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1096 break; 1106 break;
1097 case (0x12): /* LNA2 LNA1 */ 1107 case 0x12: /* LNA2 LNA1 */
1098 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1; 1108 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1099 antcomb->first_quick_scan_conf = 1109 antcomb->first_quick_scan_conf =
1100 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1110 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1101 antcomb->second_quick_scan_conf = 1111 antcomb->second_quick_scan_conf =
1102 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1112 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1103 break; 1113 break;
1104 case (0x13): /* LNA2 A+B */ 1114 case 0x13: /* LNA2 A+B */
1105 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1115 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1106 antcomb->first_quick_scan_conf = 1116 antcomb->first_quick_scan_conf =
1107 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1117 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1108 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; 1118 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1109 break; 1119 break;
1110 case (0x23): /* LNA1 A+B */ 1120 case 0x23: /* LNA1 A+B */
1111 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1121 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1112 antcomb->first_quick_scan_conf = 1122 antcomb->first_quick_scan_conf =
1113 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1123 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
@@ -1324,65 +1334,148 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1324 /* Adjust the fast_div_bias based on main and alt lna conf */ 1334 /* Adjust the fast_div_bias based on main and alt lna conf */
1325 switch ((ant_conf->main_lna_conf << 4) | 1335 switch ((ant_conf->main_lna_conf << 4) |
1326 ant_conf->alt_lna_conf) { 1336 ant_conf->alt_lna_conf) {
1327 case (0x01): /* A-B LNA2 */ 1337 case 0x01: /* A-B LNA2 */
1328 ant_conf->fast_div_bias = 0x3b; 1338 ant_conf->fast_div_bias = 0x3b;
1329 break; 1339 break;
1330 case (0x02): /* A-B LNA1 */ 1340 case 0x02: /* A-B LNA1 */
1331 ant_conf->fast_div_bias = 0x3d; 1341 ant_conf->fast_div_bias = 0x3d;
1332 break; 1342 break;
1333 case (0x03): /* A-B A+B */ 1343 case 0x03: /* A-B A+B */
1334 ant_conf->fast_div_bias = 0x1; 1344 ant_conf->fast_div_bias = 0x1;
1335 break; 1345 break;
1336 case (0x10): /* LNA2 A-B */ 1346 case 0x10: /* LNA2 A-B */
1337 ant_conf->fast_div_bias = 0x7; 1347 ant_conf->fast_div_bias = 0x7;
1338 break; 1348 break;
1339 case (0x12): /* LNA2 LNA1 */ 1349 case 0x12: /* LNA2 LNA1 */
1340 ant_conf->fast_div_bias = 0x2; 1350 ant_conf->fast_div_bias = 0x2;
1341 break; 1351 break;
1342 case (0x13): /* LNA2 A+B */ 1352 case 0x13: /* LNA2 A+B */
1343 ant_conf->fast_div_bias = 0x7; 1353 ant_conf->fast_div_bias = 0x7;
1344 break; 1354 break;
1345 case (0x20): /* LNA1 A-B */ 1355 case 0x20: /* LNA1 A-B */
1346 ant_conf->fast_div_bias = 0x6; 1356 ant_conf->fast_div_bias = 0x6;
1347 break; 1357 break;
1348 case (0x21): /* LNA1 LNA2 */ 1358 case 0x21: /* LNA1 LNA2 */
1349 ant_conf->fast_div_bias = 0x0; 1359 ant_conf->fast_div_bias = 0x0;
1350 break; 1360 break;
1351 case (0x23): /* LNA1 A+B */ 1361 case 0x23: /* LNA1 A+B */
1352 ant_conf->fast_div_bias = 0x6; 1362 ant_conf->fast_div_bias = 0x6;
1353 break; 1363 break;
1354 case (0x30): /* A+B A-B */ 1364 case 0x30: /* A+B A-B */
1355 ant_conf->fast_div_bias = 0x1; 1365 ant_conf->fast_div_bias = 0x1;
1356 break; 1366 break;
1357 case (0x31): /* A+B LNA2 */ 1367 case 0x31: /* A+B LNA2 */
1358 ant_conf->fast_div_bias = 0x3b; 1368 ant_conf->fast_div_bias = 0x3b;
1359 break; 1369 break;
1360 case (0x32): /* A+B LNA1 */ 1370 case 0x32: /* A+B LNA1 */
1361 ant_conf->fast_div_bias = 0x3d; 1371 ant_conf->fast_div_bias = 0x3d;
1362 break; 1372 break;
1363 default: 1373 default:
1364 break; 1374 break;
1365 } 1375 }
1376 } else if (ant_conf->div_group == 1) {
1377 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1378 switch ((ant_conf->main_lna_conf << 4) |
1379 ant_conf->alt_lna_conf) {
1380 case 0x01: /* A-B LNA2 */
1381 ant_conf->fast_div_bias = 0x1;
1382 ant_conf->main_gaintb = 0;
1383 ant_conf->alt_gaintb = 0;
1384 break;
1385 case 0x02: /* A-B LNA1 */
1386 ant_conf->fast_div_bias = 0x1;
1387 ant_conf->main_gaintb = 0;
1388 ant_conf->alt_gaintb = 0;
1389 break;
1390 case 0x03: /* A-B A+B */
1391 ant_conf->fast_div_bias = 0x1;
1392 ant_conf->main_gaintb = 0;
1393 ant_conf->alt_gaintb = 0;
1394 break;
1395 case 0x10: /* LNA2 A-B */
1396 if (!(antcomb->scan) &&
1397 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1398 ant_conf->fast_div_bias = 0x3f;
1399 else
1400 ant_conf->fast_div_bias = 0x1;
1401 ant_conf->main_gaintb = 0;
1402 ant_conf->alt_gaintb = 0;
1403 break;
1404 case 0x12: /* LNA2 LNA1 */
1405 ant_conf->fast_div_bias = 0x1;
1406 ant_conf->main_gaintb = 0;
1407 ant_conf->alt_gaintb = 0;
1408 break;
1409 case 0x13: /* LNA2 A+B */
1410 if (!(antcomb->scan) &&
1411 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1412 ant_conf->fast_div_bias = 0x3f;
1413 else
1414 ant_conf->fast_div_bias = 0x1;
1415 ant_conf->main_gaintb = 0;
1416 ant_conf->alt_gaintb = 0;
1417 break;
1418 case 0x20: /* LNA1 A-B */
1419 if (!(antcomb->scan) &&
1420 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1421 ant_conf->fast_div_bias = 0x3f;
1422 else
1423 ant_conf->fast_div_bias = 0x1;
1424 ant_conf->main_gaintb = 0;
1425 ant_conf->alt_gaintb = 0;
1426 break;
1427 case 0x21: /* LNA1 LNA2 */
1428 ant_conf->fast_div_bias = 0x1;
1429 ant_conf->main_gaintb = 0;
1430 ant_conf->alt_gaintb = 0;
1431 break;
1432 case 0x23: /* LNA1 A+B */
1433 if (!(antcomb->scan) &&
1434 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1435 ant_conf->fast_div_bias = 0x3f;
1436 else
1437 ant_conf->fast_div_bias = 0x1;
1438 ant_conf->main_gaintb = 0;
1439 ant_conf->alt_gaintb = 0;
1440 break;
1441 case 0x30: /* A+B A-B */
1442 ant_conf->fast_div_bias = 0x1;
1443 ant_conf->main_gaintb = 0;
1444 ant_conf->alt_gaintb = 0;
1445 break;
1446 case 0x31: /* A+B LNA2 */
1447 ant_conf->fast_div_bias = 0x1;
1448 ant_conf->main_gaintb = 0;
1449 ant_conf->alt_gaintb = 0;
1450 break;
1451 case 0x32: /* A+B LNA1 */
1452 ant_conf->fast_div_bias = 0x1;
1453 ant_conf->main_gaintb = 0;
1454 ant_conf->alt_gaintb = 0;
1455 break;
1456 default:
1457 break;
1458 }
1366 } else if (ant_conf->div_group == 2) { 1459 } else if (ant_conf->div_group == 2) {
1367 /* Adjust the fast_div_bias based on main and alt_lna_conf */ 1460 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1368 switch ((ant_conf->main_lna_conf << 4) | 1461 switch ((ant_conf->main_lna_conf << 4) |
1369 ant_conf->alt_lna_conf) { 1462 ant_conf->alt_lna_conf) {
1370 case (0x01): /* A-B LNA2 */ 1463 case 0x01: /* A-B LNA2 */
1371 ant_conf->fast_div_bias = 0x1; 1464 ant_conf->fast_div_bias = 0x1;
1372 ant_conf->main_gaintb = 0; 1465 ant_conf->main_gaintb = 0;
1373 ant_conf->alt_gaintb = 0; 1466 ant_conf->alt_gaintb = 0;
1374 break; 1467 break;
1375 case (0x02): /* A-B LNA1 */ 1468 case 0x02: /* A-B LNA1 */
1376 ant_conf->fast_div_bias = 0x1; 1469 ant_conf->fast_div_bias = 0x1;
1377 ant_conf->main_gaintb = 0; 1470 ant_conf->main_gaintb = 0;
1378 ant_conf->alt_gaintb = 0; 1471 ant_conf->alt_gaintb = 0;
1379 break; 1472 break;
1380 case (0x03): /* A-B A+B */ 1473 case 0x03: /* A-B A+B */
1381 ant_conf->fast_div_bias = 0x1; 1474 ant_conf->fast_div_bias = 0x1;
1382 ant_conf->main_gaintb = 0; 1475 ant_conf->main_gaintb = 0;
1383 ant_conf->alt_gaintb = 0; 1476 ant_conf->alt_gaintb = 0;
1384 break; 1477 break;
1385 case (0x10): /* LNA2 A-B */ 1478 case 0x10: /* LNA2 A-B */
1386 if (!(antcomb->scan) && 1479 if (!(antcomb->scan) &&
1387 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)) 1480 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1388 ant_conf->fast_div_bias = 0x1; 1481 ant_conf->fast_div_bias = 0x1;
@@ -1391,12 +1484,12 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1391 ant_conf->main_gaintb = 0; 1484 ant_conf->main_gaintb = 0;
1392 ant_conf->alt_gaintb = 0; 1485 ant_conf->alt_gaintb = 0;
1393 break; 1486 break;
1394 case (0x12): /* LNA2 LNA1 */ 1487 case 0x12: /* LNA2 LNA1 */
1395 ant_conf->fast_div_bias = 0x1; 1488 ant_conf->fast_div_bias = 0x1;
1396 ant_conf->main_gaintb = 0; 1489 ant_conf->main_gaintb = 0;
1397 ant_conf->alt_gaintb = 0; 1490 ant_conf->alt_gaintb = 0;
1398 break; 1491 break;
1399 case (0x13): /* LNA2 A+B */ 1492 case 0x13: /* LNA2 A+B */
1400 if (!(antcomb->scan) && 1493 if (!(antcomb->scan) &&
1401 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)) 1494 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1402 ant_conf->fast_div_bias = 0x1; 1495 ant_conf->fast_div_bias = 0x1;
@@ -1405,7 +1498,7 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1405 ant_conf->main_gaintb = 0; 1498 ant_conf->main_gaintb = 0;
1406 ant_conf->alt_gaintb = 0; 1499 ant_conf->alt_gaintb = 0;
1407 break; 1500 break;
1408 case (0x20): /* LNA1 A-B */ 1501 case 0x20: /* LNA1 A-B */
1409 if (!(antcomb->scan) && 1502 if (!(antcomb->scan) &&
1410 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)) 1503 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1411 ant_conf->fast_div_bias = 0x1; 1504 ant_conf->fast_div_bias = 0x1;
@@ -1414,12 +1507,12 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1414 ant_conf->main_gaintb = 0; 1507 ant_conf->main_gaintb = 0;
1415 ant_conf->alt_gaintb = 0; 1508 ant_conf->alt_gaintb = 0;
1416 break; 1509 break;
1417 case (0x21): /* LNA1 LNA2 */ 1510 case 0x21: /* LNA1 LNA2 */
1418 ant_conf->fast_div_bias = 0x1; 1511 ant_conf->fast_div_bias = 0x1;
1419 ant_conf->main_gaintb = 0; 1512 ant_conf->main_gaintb = 0;
1420 ant_conf->alt_gaintb = 0; 1513 ant_conf->alt_gaintb = 0;
1421 break; 1514 break;
1422 case (0x23): /* LNA1 A+B */ 1515 case 0x23: /* LNA1 A+B */
1423 if (!(antcomb->scan) && 1516 if (!(antcomb->scan) &&
1424 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)) 1517 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1425 ant_conf->fast_div_bias = 0x1; 1518 ant_conf->fast_div_bias = 0x1;
@@ -1428,17 +1521,17 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1428 ant_conf->main_gaintb = 0; 1521 ant_conf->main_gaintb = 0;
1429 ant_conf->alt_gaintb = 0; 1522 ant_conf->alt_gaintb = 0;
1430 break; 1523 break;
1431 case (0x30): /* A+B A-B */ 1524 case 0x30: /* A+B A-B */
1432 ant_conf->fast_div_bias = 0x1; 1525 ant_conf->fast_div_bias = 0x1;
1433 ant_conf->main_gaintb = 0; 1526 ant_conf->main_gaintb = 0;
1434 ant_conf->alt_gaintb = 0; 1527 ant_conf->alt_gaintb = 0;
1435 break; 1528 break;
1436 case (0x31): /* A+B LNA2 */ 1529 case 0x31: /* A+B LNA2 */
1437 ant_conf->fast_div_bias = 0x1; 1530 ant_conf->fast_div_bias = 0x1;
1438 ant_conf->main_gaintb = 0; 1531 ant_conf->main_gaintb = 0;
1439 ant_conf->alt_gaintb = 0; 1532 ant_conf->alt_gaintb = 0;
1440 break; 1533 break;
1441 case (0x32): /* A+B LNA1 */ 1534 case 0x32: /* A+B LNA1 */
1442 ant_conf->fast_div_bias = 0x1; 1535 ant_conf->fast_div_bias = 0x1;
1443 ant_conf->main_gaintb = 0; 1536 ant_conf->main_gaintb = 0;
1444 ant_conf->alt_gaintb = 0; 1537 ant_conf->alt_gaintb = 0;
@@ -1446,9 +1539,7 @@ static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1446 default: 1539 default:
1447 break; 1540 break;
1448 } 1541 }
1449
1450 } 1542 }
1451
1452} 1543}
1453 1544
1454/* Antenna diversity and combining */ 1545/* Antenna diversity and combining */
@@ -1856,6 +1947,9 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1856 sc->rx.rxotherant = 0; 1947 sc->rx.rxotherant = 0;
1857 } 1948 }
1858 1949
1950 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1951 skb_trim(skb, skb->len - 8);
1952
1859 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1953 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1860 1954
1861 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | 1955 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index c18ee9921fb1..fa4c0bbce6b9 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -600,7 +600,6 @@
600 600
601#define AR_D_GBL_IFS_SIFS 0x1030 601#define AR_D_GBL_IFS_SIFS 0x1030
602#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF 602#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF
603#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB
604#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF 603#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF
605 604
606#define AR_D_TXBLK_BASE 0x1038 605#define AR_D_TXBLK_BASE 0x1038
@@ -616,12 +615,10 @@
616#define AR_D_GBL_IFS_SLOT 0x1070 615#define AR_D_GBL_IFS_SLOT 0x1070
617#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF 616#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF
618#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 617#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000
619#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420
620 618
621#define AR_D_GBL_IFS_EIFS 0x10b0 619#define AR_D_GBL_IFS_EIFS 0x10b0
622#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF 620#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF
623#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 621#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000
624#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB
625 622
626#define AR_D_GBL_IFS_MISC 0x10f0 623#define AR_D_GBL_IFS_MISC 0x10f0
627#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 624#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007
@@ -788,6 +785,10 @@
788#define AR_SREV_REVISION_9271_11 1 785#define AR_SREV_REVISION_9271_11 1
789#define AR_SREV_VERSION_9300 0x1c0 786#define AR_SREV_VERSION_9300 0x1c0
790#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ 787#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */
788#define AR_SREV_VERSION_9330 0x200
789#define AR_SREV_REVISION_9330_10 0
790#define AR_SREV_REVISION_9330_11 1
791#define AR_SREV_REVISION_9330_12 2
791#define AR_SREV_VERSION_9485 0x240 792#define AR_SREV_VERSION_9485 0x240
792#define AR_SREV_REVISION_9485_10 0 793#define AR_SREV_REVISION_9485_10 0
793#define AR_SREV_REVISION_9485_11 1 794#define AR_SREV_REVISION_9485_11 1
@@ -862,6 +863,18 @@
862#define AR_SREV_9300_20_OR_LATER(_ah) \ 863#define AR_SREV_9300_20_OR_LATER(_ah) \
863 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300) 864 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300)
864 865
866#define AR_SREV_9330(_ah) \
867 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330))
868#define AR_SREV_9330_10(_ah) \
869 (AR_SREV_9330((_ah)) && \
870 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_10))
871#define AR_SREV_9330_11(_ah) \
872 (AR_SREV_9330((_ah)) && \
873 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11))
874#define AR_SREV_9330_12(_ah) \
875 (AR_SREV_9330((_ah)) && \
876 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_12))
877
865#define AR_SREV_9485(_ah) \ 878#define AR_SREV_9485(_ah) \
866 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485)) 879 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
867#define AR_SREV_9485_10(_ah) \ 880#define AR_SREV_9485_10(_ah) \
@@ -1461,7 +1474,6 @@ enum {
1461#define AR_TIME_OUT_ACK_S 0 1474#define AR_TIME_OUT_ACK_S 0
1462#define AR_TIME_OUT_CTS 0x3FFF0000 1475#define AR_TIME_OUT_CTS 0x3FFF0000
1463#define AR_TIME_OUT_CTS_S 16 1476#define AR_TIME_OUT_CTS_S 16
1464#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56
1465 1477
1466#define AR_RSSI_THR 0x8018 1478#define AR_RSSI_THR 0x8018
1467#define AR_RSSI_THR_MASK 0x000000FF 1479#define AR_RSSI_THR_MASK 0x000000FF
@@ -1477,7 +1489,6 @@ enum {
1477#define AR_USEC_TX_LAT_S 14 1489#define AR_USEC_TX_LAT_S 14
1478#define AR_USEC_RX_LAT 0x1F800000 1490#define AR_USEC_RX_LAT 0x1F800000
1479#define AR_USEC_RX_LAT_S 23 1491#define AR_USEC_RX_LAT_S 23
1480#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074
1481 1492
1482#define AR_RESET_TSF 0x8020 1493#define AR_RESET_TSF 0x8020
1483#define AR_RESET_TSF_ONCE 0x01000000 1494#define AR_RESET_TSF_ONCE 0x01000000
@@ -1862,29 +1873,6 @@ enum {
1862#define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2)) 1873#define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2))
1863 1874
1864 1875
1865#define AR_KEYTABLE_0 0x8800
1866#define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32))
1867#define AR_KEY_CACHE_SIZE 128
1868#define AR_RSVD_KEYTABLE_ENTRIES 4
1869#define AR_KEY_TYPE 0x00000007
1870#define AR_KEYTABLE_TYPE_40 0x00000000
1871#define AR_KEYTABLE_TYPE_104 0x00000001
1872#define AR_KEYTABLE_TYPE_128 0x00000003
1873#define AR_KEYTABLE_TYPE_TKIP 0x00000004
1874#define AR_KEYTABLE_TYPE_AES 0x00000005
1875#define AR_KEYTABLE_TYPE_CCM 0x00000006
1876#define AR_KEYTABLE_TYPE_CLR 0x00000007
1877#define AR_KEYTABLE_ANT 0x00000008
1878#define AR_KEYTABLE_VALID 0x00008000
1879#define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0)
1880#define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4)
1881#define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8)
1882#define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12)
1883#define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16)
1884#define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20)
1885#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24)
1886#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28)
1887
1888#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ 1876#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */
1889#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ 1877#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */
1890 1878
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 3779b8977d47..cc595712f518 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -14,6 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include <linux/dma-mapping.h>
17#include "ath9k.h" 18#include "ath9k.h"
18#include "ar9003_mac.h" 19#include "ar9003_mac.h"
19 20
@@ -53,7 +54,7 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
53 struct ath_txq *txq, struct list_head *bf_q, 54 struct ath_txq *txq, struct list_head *bf_q,
54 struct ath_tx_status *ts, int txok, int sendbar); 55 struct ath_tx_status *ts, int txok, int sendbar);
55static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 56static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
56 struct list_head *head); 57 struct list_head *head, bool internal);
57static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len); 58static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
58static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 59static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
59 struct ath_tx_status *ts, int nframes, int nbad, 60 struct ath_tx_status *ts, int nframes, int nbad,
@@ -377,8 +378,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
377 bf_next = bf->bf_next; 378 bf_next = bf->bf_next;
378 379
379 bf->bf_state.bf_type |= BUF_XRETRY; 380 bf->bf_state.bf_type |= BUF_XRETRY;
380 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) || 381 if (!bf->bf_stale || bf_next != NULL)
381 !bf->bf_stale || bf_next != NULL)
382 list_move_tail(&bf->list, &bf_head); 382 list_move_tail(&bf->list, &bf_head);
383 383
384 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false); 384 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
@@ -463,20 +463,14 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
463 } 463 }
464 } 464 }
465 465
466 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 466 /*
467 bf_next == NULL) { 467 * Make sure the last desc is reclaimed if it
468 /* 468 * not a holding desc.
469 * Make sure the last desc is reclaimed if it 469 */
470 * not a holding desc. 470 if (!bf_last->bf_stale || bf_next != NULL)
471 */
472 if (!bf_last->bf_stale)
473 list_move_tail(&bf->list, &bf_head);
474 else
475 INIT_LIST_HEAD(&bf_head);
476 } else {
477 BUG_ON(list_empty(bf_q));
478 list_move_tail(&bf->list, &bf_head); 471 list_move_tail(&bf->list, &bf_head);
479 } 472 else
473 INIT_LIST_HEAD(&bf_head);
480 474
481 if (!txpending || (tid->state & AGGR_CLEANUP)) { 475 if (!txpending || (tid->state & AGGR_CLEANUP)) {
482 /* 476 /*
@@ -572,11 +566,8 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
572 566
573 rcu_read_unlock(); 567 rcu_read_unlock();
574 568
575 if (needreset) { 569 if (needreset)
576 spin_unlock_bh(&sc->sc_pcu_lock);
577 ath_reset(sc, false); 570 ath_reset(sc, false);
578 spin_lock_bh(&sc->sc_pcu_lock);
579 }
580} 571}
581 572
582static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 573static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
@@ -671,7 +662,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
671 * TODO - this could be improved to be dependent on the rate. 662 * TODO - this could be improved to be dependent on the rate.
672 * The hardware can keep up at lower rates, but not higher rates 663 * The hardware can keep up at lower rates, but not higher rates
673 */ 664 */
674 if (fi->keyix != ATH9K_TXKEYIX_INVALID) 665 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
666 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
675 ndelim += ATH_AGGR_ENCRYPTDELIM; 667 ndelim += ATH_AGGR_ENCRYPTDELIM;
676 668
677 /* 669 /*
@@ -837,7 +829,7 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
837 bf->bf_state.bf_type &= ~BUF_AGGR; 829 bf->bf_state.bf_type &= ~BUF_AGGR;
838 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); 830 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
839 ath_buf_set_rate(sc, bf, fi->framelen); 831 ath_buf_set_rate(sc, bf, fi->framelen);
840 ath_tx_txqaddbuf(sc, txq, &bf_q); 832 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
841 continue; 833 continue;
842 } 834 }
843 835
@@ -849,7 +841,7 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
849 /* anchor last desc of aggregate */ 841 /* anchor last desc of aggregate */
850 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); 842 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
851 843
852 ath_tx_txqaddbuf(sc, txq, &bf_q); 844 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
853 TX_STAT_INC(txq->axq_qnum, a_aggr); 845 TX_STAT_INC(txq->axq_qnum, a_aggr);
854 846
855 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH && 847 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
@@ -1085,7 +1077,6 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1085 txq->txq_headidx = txq->txq_tailidx = 0; 1077 txq->txq_headidx = txq->txq_tailidx = 0;
1086 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1078 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1087 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1079 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1088 INIT_LIST_HEAD(&txq->txq_fifo_pending);
1089 } 1080 }
1090 return &sc->tx.txq[axq_qnum]; 1081 return &sc->tx.txq[axq_qnum];
1091} 1082}
@@ -1155,13 +1146,10 @@ static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1155 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 1146 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1156} 1147}
1157 1148
1158/* 1149static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1159 * Drain a given TX queue (could be Beacon or Data) 1150 struct list_head *list, bool retry_tx)
1160 * 1151 __releases(txq->axq_lock)
1161 * This assumes output has been stopped and 1152 __acquires(txq->axq_lock)
1162 * we do not need to block ath_tx_tasklet.
1163 */
1164void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1165{ 1153{
1166 struct ath_buf *bf, *lastbf; 1154 struct ath_buf *bf, *lastbf;
1167 struct list_head bf_head; 1155 struct list_head bf_head;
@@ -1170,93 +1158,63 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1170 memset(&ts, 0, sizeof(ts)); 1158 memset(&ts, 0, sizeof(ts));
1171 INIT_LIST_HEAD(&bf_head); 1159 INIT_LIST_HEAD(&bf_head);
1172 1160
1173 for (;;) { 1161 while (!list_empty(list)) {
1174 spin_lock_bh(&txq->axq_lock); 1162 bf = list_first_entry(list, struct ath_buf, list);
1175 1163
1176 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1164 if (bf->bf_stale) {
1177 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { 1165 list_del(&bf->list);
1178 txq->txq_headidx = txq->txq_tailidx = 0;
1179 spin_unlock_bh(&txq->axq_lock);
1180 break;
1181 } else {
1182 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1183 struct ath_buf, list);
1184 }
1185 } else {
1186 if (list_empty(&txq->axq_q)) {
1187 txq->axq_link = NULL;
1188 spin_unlock_bh(&txq->axq_lock);
1189 break;
1190 }
1191 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1192 list);
1193
1194 if (bf->bf_stale) {
1195 list_del(&bf->list);
1196 spin_unlock_bh(&txq->axq_lock);
1197 1166
1198 ath_tx_return_buffer(sc, bf); 1167 ath_tx_return_buffer(sc, bf);
1199 continue; 1168 continue;
1200 }
1201 } 1169 }
1202 1170
1203 lastbf = bf->bf_lastbf; 1171 lastbf = bf->bf_lastbf;
1204 1172 list_cut_position(&bf_head, list, &lastbf->list);
1205 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1206 list_cut_position(&bf_head,
1207 &txq->txq_fifo[txq->txq_tailidx],
1208 &lastbf->list);
1209 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1210 } else {
1211 /* remove ath_buf's of the same mpdu from txq */
1212 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1213 }
1214 1173
1215 txq->axq_depth--; 1174 txq->axq_depth--;
1216 if (bf_is_ampdu_not_probing(bf)) 1175 if (bf_is_ampdu_not_probing(bf))
1217 txq->axq_ampdu_depth--; 1176 txq->axq_ampdu_depth--;
1218 spin_unlock_bh(&txq->axq_lock);
1219 1177
1178 spin_unlock_bh(&txq->axq_lock);
1220 if (bf_isampdu(bf)) 1179 if (bf_isampdu(bf))
1221 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0, 1180 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1222 retry_tx); 1181 retry_tx);
1223 else 1182 else
1224 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); 1183 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1184 spin_lock_bh(&txq->axq_lock);
1225 } 1185 }
1186}
1226 1187
1188/*
1189 * Drain a given TX queue (could be Beacon or Data)
1190 *
1191 * This assumes output has been stopped and
1192 * we do not need to block ath_tx_tasklet.
1193 */
1194void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1195{
1227 spin_lock_bh(&txq->axq_lock); 1196 spin_lock_bh(&txq->axq_lock);
1228 txq->axq_tx_inprogress = false;
1229 spin_unlock_bh(&txq->axq_lock);
1230
1231 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1197 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1232 spin_lock_bh(&txq->axq_lock); 1198 int idx = txq->txq_tailidx;
1233 while (!list_empty(&txq->txq_fifo_pending)) {
1234 bf = list_first_entry(&txq->txq_fifo_pending,
1235 struct ath_buf, list);
1236 list_cut_position(&bf_head,
1237 &txq->txq_fifo_pending,
1238 &bf->bf_lastbf->list);
1239 spin_unlock_bh(&txq->axq_lock);
1240 1199
1241 if (bf_isampdu(bf)) 1200 while (!list_empty(&txq->txq_fifo[idx])) {
1242 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 1201 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1243 &ts, 0, retry_tx); 1202 retry_tx);
1244 else 1203
1245 ath_tx_complete_buf(sc, bf, txq, &bf_head, 1204 INCR(idx, ATH_TXFIFO_DEPTH);
1246 &ts, 0, 0);
1247 spin_lock_bh(&txq->axq_lock);
1248 } 1205 }
1249 spin_unlock_bh(&txq->axq_lock); 1206 txq->txq_tailidx = idx;
1250 } 1207 }
1251 1208
1209 txq->axq_link = NULL;
1210 txq->axq_tx_inprogress = false;
1211 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1212
1252 /* flush any pending frames if aggregation is enabled */ 1213 /* flush any pending frames if aggregation is enabled */
1253 if (sc->sc_flags & SC_OP_TXAGGR) { 1214 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1254 if (!retry_tx) { 1215 ath_txq_drain_pending_buffers(sc, txq);
1255 spin_lock_bh(&txq->axq_lock); 1216
1256 ath_txq_drain_pending_buffers(sc, txq); 1217 spin_unlock_bh(&txq->axq_lock);
1257 spin_unlock_bh(&txq->axq_lock);
1258 }
1259 }
1260} 1218}
1261 1219
1262bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1220bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
@@ -1370,11 +1328,13 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1370 * assume the descriptors are already chained together by caller. 1328 * assume the descriptors are already chained together by caller.
1371 */ 1329 */
1372static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 1330static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1373 struct list_head *head) 1331 struct list_head *head, bool internal)
1374{ 1332{
1375 struct ath_hw *ah = sc->sc_ah; 1333 struct ath_hw *ah = sc->sc_ah;
1376 struct ath_common *common = ath9k_hw_common(ah); 1334 struct ath_common *common = ath9k_hw_common(ah);
1377 struct ath_buf *bf; 1335 struct ath_buf *bf, *bf_last;
1336 bool puttxbuf = false;
1337 bool edma;
1378 1338
1379 /* 1339 /*
1380 * Insert the frame on the outbound list and 1340 * Insert the frame on the outbound list and
@@ -1384,51 +1344,49 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1384 if (list_empty(head)) 1344 if (list_empty(head))
1385 return; 1345 return;
1386 1346
1347 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1387 bf = list_first_entry(head, struct ath_buf, list); 1348 bf = list_first_entry(head, struct ath_buf, list);
1349 bf_last = list_entry(head->prev, struct ath_buf, list);
1388 1350
1389 ath_dbg(common, ATH_DBG_QUEUE, 1351 ath_dbg(common, ATH_DBG_QUEUE,
1390 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1352 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1391 1353
1392 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1354 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1393 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) { 1355 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1394 list_splice_tail_init(head, &txq->txq_fifo_pending);
1395 return;
1396 }
1397 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1398 ath_dbg(common, ATH_DBG_XMIT,
1399 "Initializing tx fifo %d which is non-empty\n",
1400 txq->txq_headidx);
1401 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1402 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1403 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 1356 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1404 TX_STAT_INC(txq->axq_qnum, puttxbuf); 1357 puttxbuf = true;
1405 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1406 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1407 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1408 } else { 1358 } else {
1409 list_splice_tail_init(head, &txq->axq_q); 1359 list_splice_tail_init(head, &txq->axq_q);
1410 1360
1411 if (txq->axq_link == NULL) { 1361 if (txq->axq_link) {
1412 TX_STAT_INC(txq->axq_qnum, puttxbuf); 1362 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1413 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1414 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1415 txq->axq_qnum, ito64(bf->bf_daddr),
1416 bf->bf_desc);
1417 } else {
1418 *txq->axq_link = bf->bf_daddr;
1419 ath_dbg(common, ATH_DBG_XMIT, 1363 ath_dbg(common, ATH_DBG_XMIT,
1420 "link[%u] (%p)=%llx (%p)\n", 1364 "link[%u] (%p)=%llx (%p)\n",
1421 txq->axq_qnum, txq->axq_link, 1365 txq->axq_qnum, txq->axq_link,
1422 ito64(bf->bf_daddr), bf->bf_desc); 1366 ito64(bf->bf_daddr), bf->bf_desc);
1423 } 1367 } else if (!edma)
1424 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc, 1368 puttxbuf = true;
1425 &txq->axq_link); 1369
1370 txq->axq_link = bf_last->bf_desc;
1371 }
1372
1373 if (puttxbuf) {
1374 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1375 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1376 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1377 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1378 }
1379
1380 if (!edma) {
1426 TX_STAT_INC(txq->axq_qnum, txstart); 1381 TX_STAT_INC(txq->axq_qnum, txstart);
1427 ath9k_hw_txstart(ah, txq->axq_qnum); 1382 ath9k_hw_txstart(ah, txq->axq_qnum);
1428 } 1383 }
1429 txq->axq_depth++; 1384
1430 if (bf_is_ampdu_not_probing(bf)) 1385 if (!internal) {
1431 txq->axq_ampdu_depth++; 1386 txq->axq_depth++;
1387 if (bf_is_ampdu_not_probing(bf))
1388 txq->axq_ampdu_depth++;
1389 }
1432} 1390}
1433 1391
1434static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1392static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
@@ -1470,7 +1428,7 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1470 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw); 1428 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1471 bf->bf_lastbf = bf; 1429 bf->bf_lastbf = bf;
1472 ath_buf_set_rate(sc, bf, fi->framelen); 1430 ath_buf_set_rate(sc, bf, fi->framelen);
1473 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head); 1431 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1474} 1432}
1475 1433
1476static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 1434static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
@@ -1490,7 +1448,7 @@ static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1490 bf->bf_lastbf = bf; 1448 bf->bf_lastbf = bf;
1491 fi = get_frame_info(bf->bf_mpdu); 1449 fi = get_frame_info(bf->bf_mpdu);
1492 ath_buf_set_rate(sc, bf, fi->framelen); 1450 ath_buf_set_rate(sc, bf, fi->framelen);
1493 ath_tx_txqaddbuf(sc, txq, bf_head); 1451 ath_tx_txqaddbuf(sc, txq, bf_head, false);
1494 TX_STAT_INC(txq->axq_qnum, queued); 1452 TX_STAT_INC(txq->axq_qnum, queued);
1495} 1453}
1496 1454
@@ -2077,6 +2035,40 @@ static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2077 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2035 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2078} 2036}
2079 2037
2038static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2039 struct ath_tx_status *ts, struct ath_buf *bf,
2040 struct list_head *bf_head)
2041 __releases(txq->axq_lock)
2042 __acquires(txq->axq_lock)
2043{
2044 int txok;
2045
2046 txq->axq_depth--;
2047 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2048 txq->axq_tx_inprogress = false;
2049 if (bf_is_ampdu_not_probing(bf))
2050 txq->axq_ampdu_depth--;
2051
2052 spin_unlock_bh(&txq->axq_lock);
2053
2054 if (!bf_isampdu(bf)) {
2055 /*
2056 * This frame is sent out as a single frame.
2057 * Use hardware retry status for this frame.
2058 */
2059 if (ts->ts_status & ATH9K_TXERR_XRETRY)
2060 bf->bf_state.bf_type |= BUF_XRETRY;
2061 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2062 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2063 } else
2064 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2065
2066 spin_lock_bh(&txq->axq_lock);
2067
2068 if (sc->sc_flags & SC_OP_TXAGGR)
2069 ath_txq_schedule(sc, txq);
2070}
2071
2080static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2072static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2081{ 2073{
2082 struct ath_hw *ah = sc->sc_ah; 2074 struct ath_hw *ah = sc->sc_ah;
@@ -2085,20 +2077,18 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2085 struct list_head bf_head; 2077 struct list_head bf_head;
2086 struct ath_desc *ds; 2078 struct ath_desc *ds;
2087 struct ath_tx_status ts; 2079 struct ath_tx_status ts;
2088 int txok;
2089 int status; 2080 int status;
2090 2081
2091 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 2082 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2092 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2083 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2093 txq->axq_link); 2084 txq->axq_link);
2094 2085
2086 spin_lock_bh(&txq->axq_lock);
2095 for (;;) { 2087 for (;;) {
2096 spin_lock_bh(&txq->axq_lock);
2097 if (list_empty(&txq->axq_q)) { 2088 if (list_empty(&txq->axq_q)) {
2098 txq->axq_link = NULL; 2089 txq->axq_link = NULL;
2099 if (sc->sc_flags & SC_OP_TXAGGR) 2090 if (sc->sc_flags & SC_OP_TXAGGR)
2100 ath_txq_schedule(sc, txq); 2091 ath_txq_schedule(sc, txq);
2101 spin_unlock_bh(&txq->axq_lock);
2102 break; 2092 break;
2103 } 2093 }
2104 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2094 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
@@ -2114,13 +2104,11 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2114 bf_held = NULL; 2104 bf_held = NULL;
2115 if (bf->bf_stale) { 2105 if (bf->bf_stale) {
2116 bf_held = bf; 2106 bf_held = bf;
2117 if (list_is_last(&bf_held->list, &txq->axq_q)) { 2107 if (list_is_last(&bf_held->list, &txq->axq_q))
2118 spin_unlock_bh(&txq->axq_lock);
2119 break; 2108 break;
2120 } else { 2109
2121 bf = list_entry(bf_held->list.next, 2110 bf = list_entry(bf_held->list.next, struct ath_buf,
2122 struct ath_buf, list); 2111 list);
2123 }
2124 } 2112 }
2125 2113
2126 lastbf = bf->bf_lastbf; 2114 lastbf = bf->bf_lastbf;
@@ -2128,10 +2116,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2128 2116
2129 memset(&ts, 0, sizeof(ts)); 2117 memset(&ts, 0, sizeof(ts));
2130 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2118 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2131 if (status == -EINPROGRESS) { 2119 if (status == -EINPROGRESS)
2132 spin_unlock_bh(&txq->axq_lock);
2133 break; 2120 break;
2134 } 2121
2135 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2122 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2136 2123
2137 /* 2124 /*
@@ -2145,42 +2132,14 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2145 list_cut_position(&bf_head, 2132 list_cut_position(&bf_head,
2146 &txq->axq_q, lastbf->list.prev); 2133 &txq->axq_q, lastbf->list.prev);
2147 2134
2148 txq->axq_depth--; 2135 if (bf_held) {
2149 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2150 txq->axq_tx_inprogress = false;
2151 if (bf_held)
2152 list_del(&bf_held->list); 2136 list_del(&bf_held->list);
2153
2154 if (bf_is_ampdu_not_probing(bf))
2155 txq->axq_ampdu_depth--;
2156
2157 spin_unlock_bh(&txq->axq_lock);
2158
2159 if (bf_held)
2160 ath_tx_return_buffer(sc, bf_held); 2137 ath_tx_return_buffer(sc, bf_held);
2161
2162 if (!bf_isampdu(bf)) {
2163 /*
2164 * This frame is sent out as a single frame.
2165 * Use hardware retry status for this frame.
2166 */
2167 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2168 bf->bf_state.bf_type |= BUF_XRETRY;
2169 ath_tx_rc_status(sc, bf, &ts, 1, txok ? 0 : 1, txok, true);
2170 } 2138 }
2171 2139
2172 if (bf_isampdu(bf)) 2140 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2173 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
2174 true);
2175 else
2176 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2177
2178 spin_lock_bh(&txq->axq_lock);
2179
2180 if (sc->sc_flags & SC_OP_TXAGGR)
2181 ath_txq_schedule(sc, txq);
2182 spin_unlock_bh(&txq->axq_lock);
2183 } 2141 }
2142 spin_unlock_bh(&txq->axq_lock);
2184} 2143}
2185 2144
2186static void ath_tx_complete_poll_work(struct work_struct *work) 2145static void ath_tx_complete_poll_work(struct work_struct *work)
@@ -2213,7 +2172,9 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2213 if (needreset) { 2172 if (needreset) {
2214 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, 2173 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2215 "tx hung, resetting the chip\n"); 2174 "tx hung, resetting the chip\n");
2175 spin_lock_bh(&sc->sc_pcu_lock);
2216 ath_reset(sc, true); 2176 ath_reset(sc, true);
2177 spin_unlock_bh(&sc->sc_pcu_lock);
2217 } 2178 }
2218 2179
2219 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2180 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
@@ -2237,17 +2198,16 @@ void ath_tx_tasklet(struct ath_softc *sc)
2237 2198
2238void ath_tx_edma_tasklet(struct ath_softc *sc) 2199void ath_tx_edma_tasklet(struct ath_softc *sc)
2239{ 2200{
2240 struct ath_tx_status txs; 2201 struct ath_tx_status ts;
2241 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2202 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2242 struct ath_hw *ah = sc->sc_ah; 2203 struct ath_hw *ah = sc->sc_ah;
2243 struct ath_txq *txq; 2204 struct ath_txq *txq;
2244 struct ath_buf *bf, *lastbf; 2205 struct ath_buf *bf, *lastbf;
2245 struct list_head bf_head; 2206 struct list_head bf_head;
2246 int status; 2207 int status;
2247 int txok;
2248 2208
2249 for (;;) { 2209 for (;;) {
2250 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs); 2210 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2251 if (status == -EINPROGRESS) 2211 if (status == -EINPROGRESS)
2252 break; 2212 break;
2253 if (status == -EIO) { 2213 if (status == -EIO) {
@@ -2257,12 +2217,13 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
2257 } 2217 }
2258 2218
2259 /* Skip beacon completions */ 2219 /* Skip beacon completions */
2260 if (txs.qid == sc->beacon.beaconq) 2220 if (ts.qid == sc->beacon.beaconq)
2261 continue; 2221 continue;
2262 2222
2263 txq = &sc->tx.txq[txs.qid]; 2223 txq = &sc->tx.txq[ts.qid];
2264 2224
2265 spin_lock_bh(&txq->axq_lock); 2225 spin_lock_bh(&txq->axq_lock);
2226
2266 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { 2227 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2267 spin_unlock_bh(&txq->axq_lock); 2228 spin_unlock_bh(&txq->axq_lock);
2268 return; 2229 return;
@@ -2275,41 +2236,21 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
2275 INIT_LIST_HEAD(&bf_head); 2236 INIT_LIST_HEAD(&bf_head);
2276 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx], 2237 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2277 &lastbf->list); 2238 &lastbf->list);
2278 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2279 txq->axq_depth--;
2280 txq->axq_tx_inprogress = false;
2281 if (bf_is_ampdu_not_probing(bf))
2282 txq->axq_ampdu_depth--;
2283 spin_unlock_bh(&txq->axq_lock);
2284 2239
2285 txok = !(txs.ts_status & ATH9K_TXERR_MASK); 2240 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2286 2241 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2287 if (!bf_isampdu(bf)) {
2288 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2289 bf->bf_state.bf_type |= BUF_XRETRY;
2290 ath_tx_rc_status(sc, bf, &txs, 1, txok ? 0 : 1, txok, true);
2291 }
2292
2293 if (bf_isampdu(bf))
2294 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
2295 txok, true);
2296 else
2297 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2298 &txs, txok, 0);
2299 2242
2300 spin_lock_bh(&txq->axq_lock); 2243 if (!list_empty(&txq->axq_q)) {
2244 struct list_head bf_q;
2301 2245
2302 if (!list_empty(&txq->txq_fifo_pending)) { 2246 INIT_LIST_HEAD(&bf_q);
2303 INIT_LIST_HEAD(&bf_head); 2247 txq->axq_link = NULL;
2304 bf = list_first_entry(&txq->txq_fifo_pending, 2248 list_splice_tail_init(&txq->axq_q, &bf_q);
2305 struct ath_buf, list); 2249 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2306 list_cut_position(&bf_head, 2250 }
2307 &txq->txq_fifo_pending, 2251 }
2308 &bf->bf_lastbf->list);
2309 ath_tx_txqaddbuf(sc, txq, &bf_head);
2310 } else if (sc->sc_flags & SC_OP_TXAGGR)
2311 ath_txq_schedule(sc, txq);
2312 2252
2253 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2313 spin_unlock_bh(&txq->axq_lock); 2254 spin_unlock_bh(&txq->axq_lock);
2314 } 2255 }
2315} 2256}
diff --git a/drivers/net/wireless/ath/carl9170/carl9170.h b/drivers/net/wireless/ath/carl9170/carl9170.h
index 4da01a9f5680..c5427a72a1e2 100644
--- a/drivers/net/wireless/ath/carl9170/carl9170.h
+++ b/drivers/net/wireless/ath/carl9170/carl9170.h
@@ -67,6 +67,8 @@
67 67
68#define PAYLOAD_MAX (CARL9170_MAX_CMD_LEN / 4 - 1) 68#define PAYLOAD_MAX (CARL9170_MAX_CMD_LEN / 4 - 1)
69 69
70static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 3, 2, 1, 0 };
71
70enum carl9170_rf_init_mode { 72enum carl9170_rf_init_mode {
71 CARL9170_RFI_NONE, 73 CARL9170_RFI_NONE,
72 CARL9170_RFI_WARM, 74 CARL9170_RFI_WARM,
@@ -175,7 +177,7 @@ struct carl9170_tx_queue_stats {
175 177
176struct carl9170_vif { 178struct carl9170_vif {
177 unsigned int id; 179 unsigned int id;
178 struct ieee80211_vif *vif; 180 struct ieee80211_vif __rcu *vif;
179}; 181};
180 182
181struct carl9170_vif_info { 183struct carl9170_vif_info {
@@ -309,7 +311,7 @@ struct ar9170 {
309 spinlock_t beacon_lock; 311 spinlock_t beacon_lock;
310 unsigned int global_pretbtt; 312 unsigned int global_pretbtt;
311 unsigned int global_beacon_int; 313 unsigned int global_beacon_int;
312 struct carl9170_vif_info *beacon_iter; 314 struct carl9170_vif_info __rcu *beacon_iter;
313 unsigned int beacon_enabled; 315 unsigned int beacon_enabled;
314 316
315 /* cryptographic engine */ 317 /* cryptographic engine */
@@ -387,7 +389,7 @@ struct ar9170 {
387 /* tx ampdu */ 389 /* tx ampdu */
388 struct work_struct ampdu_work; 390 struct work_struct ampdu_work;
389 spinlock_t tx_ampdu_list_lock; 391 spinlock_t tx_ampdu_list_lock;
390 struct carl9170_sta_tid *tx_ampdu_iter; 392 struct carl9170_sta_tid __rcu *tx_ampdu_iter;
391 struct list_head tx_ampdu_list; 393 struct list_head tx_ampdu_list;
392 atomic_t tx_ampdu_upload; 394 atomic_t tx_ampdu_upload;
393 atomic_t tx_ampdu_scheduler; 395 atomic_t tx_ampdu_scheduler;
@@ -440,7 +442,6 @@ struct ar9170 {
440enum carl9170_ps_off_override_reasons { 442enum carl9170_ps_off_override_reasons {
441 PS_OFF_VIF = BIT(0), 443 PS_OFF_VIF = BIT(0),
442 PS_OFF_BCN = BIT(1), 444 PS_OFF_BCN = BIT(1),
443 PS_OFF_5GHZ = BIT(2),
444}; 445};
445 446
446struct carl9170_ba_stats { 447struct carl9170_ba_stats {
@@ -455,7 +456,7 @@ struct carl9170_sta_info {
455 bool sleeping; 456 bool sleeping;
456 atomic_t pending_frames; 457 atomic_t pending_frames;
457 unsigned int ampdu_max_len; 458 unsigned int ampdu_max_len;
458 struct carl9170_sta_tid *agg[CARL9170_NUM_TID]; 459 struct carl9170_sta_tid __rcu *agg[CARL9170_NUM_TID];
459 struct carl9170_ba_stats stats[CARL9170_NUM_TID]; 460 struct carl9170_ba_stats stats[CARL9170_NUM_TID];
460}; 461};
461 462
@@ -531,7 +532,6 @@ int carl9170_set_ampdu_settings(struct ar9170 *ar);
531int carl9170_set_slot_time(struct ar9170 *ar); 532int carl9170_set_slot_time(struct ar9170 *ar);
532int carl9170_set_mac_rates(struct ar9170 *ar); 533int carl9170_set_mac_rates(struct ar9170 *ar);
533int carl9170_set_hwretry_limit(struct ar9170 *ar, const u32 max_retry); 534int carl9170_set_hwretry_limit(struct ar9170 *ar, const u32 max_retry);
534int carl9170_update_beacon(struct ar9170 *ar, const bool submit);
535int carl9170_upload_key(struct ar9170 *ar, const u8 id, const u8 *mac, 535int carl9170_upload_key(struct ar9170 *ar, const u8 id, const u8 *mac,
536 const u8 ktype, const u8 keyidx, const u8 *keydata, const int keylen); 536 const u8 ktype, const u8 keyidx, const u8 *keydata, const int keylen);
537int carl9170_disable_key(struct ar9170 *ar, const u8 id); 537int carl9170_disable_key(struct ar9170 *ar, const u8 id);
@@ -552,6 +552,7 @@ void carl9170_tx_drop(struct ar9170 *ar, struct sk_buff *skb);
552void carl9170_tx_scheduler(struct ar9170 *ar); 552void carl9170_tx_scheduler(struct ar9170 *ar);
553void carl9170_tx_get_skb(struct sk_buff *skb); 553void carl9170_tx_get_skb(struct sk_buff *skb);
554int carl9170_tx_put_skb(struct sk_buff *skb); 554int carl9170_tx_put_skb(struct sk_buff *skb);
555int carl9170_update_beacon(struct ar9170 *ar, const bool submit);
555 556
556/* LEDs */ 557/* LEDs */
557#ifdef CONFIG_CARL9170_LEDS 558#ifdef CONFIG_CARL9170_LEDS
diff --git a/drivers/net/wireless/ath/carl9170/cmd.h b/drivers/net/wireless/ath/carl9170/cmd.h
index 568174c71b94..d5f95bdc75c1 100644
--- a/drivers/net/wireless/ath/carl9170/cmd.h
+++ b/drivers/net/wireless/ath/carl9170/cmd.h
@@ -87,7 +87,7 @@ do { \
87 __ar->cmd_buf[2 * __nreg + 1] = cpu_to_le32(r); \ 87 __ar->cmd_buf[2 * __nreg + 1] = cpu_to_le32(r); \
88 __ar->cmd_buf[2 * __nreg + 2] = cpu_to_le32(v); \ 88 __ar->cmd_buf[2 * __nreg + 2] = cpu_to_le32(v); \
89 __nreg++; \ 89 __nreg++; \
90 if ((__nreg >= PAYLOAD_MAX/2)) { \ 90 if ((__nreg >= PAYLOAD_MAX / 2)) { \
91 if (IS_ACCEPTING_CMD(__ar)) \ 91 if (IS_ACCEPTING_CMD(__ar)) \
92 __err = carl9170_exec_cmd(__ar, \ 92 __err = carl9170_exec_cmd(__ar, \
93 CARL9170_CMD_WREG, 8 * __nreg, \ 93 CARL9170_CMD_WREG, 8 * __nreg, \
@@ -160,7 +160,7 @@ do { \
160} while (0) 160} while (0)
161 161
162#define carl9170_async_regwrite_finish() do { \ 162#define carl9170_async_regwrite_finish() do { \
163__async_regwrite_out : \ 163__async_regwrite_out: \
164 if (__cmd != NULL && __err == 0) \ 164 if (__cmd != NULL && __err == 0) \
165 carl9170_async_regwrite_flush(); \ 165 carl9170_async_regwrite_flush(); \
166 kfree(__cmd); \ 166 kfree(__cmd); \
diff --git a/drivers/net/wireless/ath/carl9170/debug.c b/drivers/net/wireless/ath/carl9170/debug.c
index 0ac1124c2a0b..de57f90e1d5f 100644
--- a/drivers/net/wireless/ath/carl9170/debug.c
+++ b/drivers/net/wireless/ath/carl9170/debug.c
@@ -695,7 +695,7 @@ static char *carl9170_debugfs_bug_read(struct ar9170 *ar, char *buf,
695} 695}
696__DEBUGFS_DECLARE_RW_FILE(bug, 400, CARL9170_STOPPED); 696__DEBUGFS_DECLARE_RW_FILE(bug, 400, CARL9170_STOPPED);
697 697
698static const char *erp_modes[] = { 698static const char *const erp_modes[] = {
699 [CARL9170_ERP_INVALID] = "INVALID", 699 [CARL9170_ERP_INVALID] = "INVALID",
700 [CARL9170_ERP_AUTO] = "Automatic", 700 [CARL9170_ERP_AUTO] = "Automatic",
701 [CARL9170_ERP_MAC80211] = "Set by MAC80211", 701 [CARL9170_ERP_MAC80211] = "Set by MAC80211",
diff --git a/drivers/net/wireless/ath/carl9170/fw.c b/drivers/net/wireless/ath/carl9170/fw.c
index 221957c5d373..39ddea5794f7 100644
--- a/drivers/net/wireless/ath/carl9170/fw.c
+++ b/drivers/net/wireless/ath/carl9170/fw.c
@@ -237,7 +237,7 @@ static int carl9170_fw(struct ar9170 *ar, const __u8 *data, size_t len)
237 ar->disable_offload = true; 237 ar->disable_offload = true;
238 } 238 }
239 239
240 if (SUPP(CARL9170FW_PSM)) 240 if (SUPP(CARL9170FW_PSM) && SUPP(CARL9170FW_FIXED_5GHZ_PSM))
241 ar->hw->flags |= IEEE80211_HW_SUPPORTS_PS; 241 ar->hw->flags |= IEEE80211_HW_SUPPORTS_PS;
242 242
243 if (!SUPP(CARL9170FW_USB_INIT_FIRMWARE)) { 243 if (!SUPP(CARL9170FW_USB_INIT_FIRMWARE)) {
diff --git a/drivers/net/wireless/ath/carl9170/fwcmd.h b/drivers/net/wireless/ath/carl9170/fwcmd.h
index 30449d21b762..0a6dec529b59 100644
--- a/drivers/net/wireless/ath/carl9170/fwcmd.h
+++ b/drivers/net/wireless/ath/carl9170/fwcmd.h
@@ -4,7 +4,7 @@
4 * Firmware command interface definitions 4 * Firmware command interface definitions
5 * 5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> 7 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -54,6 +54,7 @@ enum carl9170_cmd_oids {
54 CARL9170_CMD_BCN_CTRL = 0x05, 54 CARL9170_CMD_BCN_CTRL = 0x05,
55 CARL9170_CMD_READ_TSF = 0x06, 55 CARL9170_CMD_READ_TSF = 0x06,
56 CARL9170_CMD_RX_FILTER = 0x07, 56 CARL9170_CMD_RX_FILTER = 0x07,
57 CARL9170_CMD_WOL = 0x08,
57 58
58 /* CAM */ 59 /* CAM */
59 CARL9170_CMD_EKEY = 0x10, 60 CARL9170_CMD_EKEY = 0x10,
@@ -180,6 +181,21 @@ struct carl9170_bcn_ctrl_cmd {
180#define CARL9170_BCN_CTRL_DRAIN 0 181#define CARL9170_BCN_CTRL_DRAIN 0
181#define CARL9170_BCN_CTRL_CAB_TRIGGER 1 182#define CARL9170_BCN_CTRL_CAB_TRIGGER 1
182 183
184struct carl9170_wol_cmd {
185 __le32 flags;
186 u8 mac[6];
187 u8 bssid[6];
188 __le32 null_interval;
189 __le32 free_for_use2;
190 __le32 mask;
191 u8 pattern[32];
192} __packed;
193
194#define CARL9170_WOL_CMD_SIZE 60
195
196#define CARL9170_WOL_DISCONNECT 1
197#define CARL9170_WOL_MAGIC_PKT 2
198
183struct carl9170_cmd_head { 199struct carl9170_cmd_head {
184 union { 200 union {
185 struct { 201 struct {
@@ -203,6 +219,7 @@ struct carl9170_cmd {
203 struct carl9170_write_reg wreg; 219 struct carl9170_write_reg wreg;
204 struct carl9170_rf_init rf_init; 220 struct carl9170_rf_init rf_init;
205 struct carl9170_psm psm; 221 struct carl9170_psm psm;
222 struct carl9170_wol_cmd wol;
206 struct carl9170_bcn_ctrl_cmd bcn_ctrl; 223 struct carl9170_bcn_ctrl_cmd bcn_ctrl;
207 struct carl9170_rx_filter_cmd rx_filter; 224 struct carl9170_rx_filter_cmd rx_filter;
208 u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN]; 225 u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
diff --git a/drivers/net/wireless/ath/carl9170/fwdesc.h b/drivers/net/wireless/ath/carl9170/fwdesc.h
index 921066822dd5..6d9c0891ce7f 100644
--- a/drivers/net/wireless/ath/carl9170/fwdesc.h
+++ b/drivers/net/wireless/ath/carl9170/fwdesc.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Firmware descriptor format 4 * Firmware descriptor format
5 * 5 *
6 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> 6 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -72,6 +72,12 @@ enum carl9170fw_feature_list {
72 /* Wake up on WLAN */ 72 /* Wake up on WLAN */
73 CARL9170FW_WOL, 73 CARL9170FW_WOL,
74 74
75 /* Firmware supports PSM in the 5GHZ Band */
76 CARL9170FW_FIXED_5GHZ_PSM,
77
78 /* HW (ANI, CCA, MIB) tally counters */
79 CARL9170FW_HW_COUNTERS,
80
75 /* KEEP LAST */ 81 /* KEEP LAST */
76 __CARL9170FW_FEATURE_NUM 82 __CARL9170FW_FEATURE_NUM
77}; 83};
@@ -82,6 +88,7 @@ enum carl9170fw_feature_list {
82#define DBG_MAGIC "DBG\0" 88#define DBG_MAGIC "DBG\0"
83#define CHK_MAGIC "CHK\0" 89#define CHK_MAGIC "CHK\0"
84#define TXSQ_MAGIC "TXSQ" 90#define TXSQ_MAGIC "TXSQ"
91#define WOL_MAGIC "WOL\0"
85#define LAST_MAGIC "LAST" 92#define LAST_MAGIC "LAST"
86 93
87#define CARL9170FW_SET_DAY(d) (((d) - 1) % 31) 94#define CARL9170FW_SET_DAY(d) (((d) - 1) % 31)
@@ -104,7 +111,7 @@ struct carl9170fw_desc_head {
104 (sizeof(struct carl9170fw_desc_head)) 111 (sizeof(struct carl9170fw_desc_head))
105 112
106#define CARL9170FW_OTUS_DESC_MIN_VER 6 113#define CARL9170FW_OTUS_DESC_MIN_VER 6
107#define CARL9170FW_OTUS_DESC_CUR_VER 6 114#define CARL9170FW_OTUS_DESC_CUR_VER 7
108struct carl9170fw_otus_desc { 115struct carl9170fw_otus_desc {
109 struct carl9170fw_desc_head head; 116 struct carl9170fw_desc_head head;
110 __le32 feature_set; 117 __le32 feature_set;
@@ -186,6 +193,16 @@ struct carl9170fw_txsq_desc {
186#define CARL9170FW_TXSQ_DESC_SIZE \ 193#define CARL9170FW_TXSQ_DESC_SIZE \
187 (sizeof(struct carl9170fw_txsq_desc)) 194 (sizeof(struct carl9170fw_txsq_desc))
188 195
196#define CARL9170FW_WOL_DESC_MIN_VER 1
197#define CARL9170FW_WOL_DESC_CUR_VER 1
198struct carl9170fw_wol_desc {
199 struct carl9170fw_desc_head head;
200
201 __le32 supported_triggers; /* CARL9170_WOL_ */
202} __packed;
203#define CARL9170FW_WOL_DESC_SIZE \
204 (sizeof(struct carl9170fw_wol_desc))
205
189#define CARL9170FW_LAST_DESC_MIN_VER 1 206#define CARL9170FW_LAST_DESC_MIN_VER 1
190#define CARL9170FW_LAST_DESC_CUR_VER 2 207#define CARL9170FW_LAST_DESC_CUR_VER 2
191struct carl9170fw_last_desc { 208struct carl9170fw_last_desc {
diff --git a/drivers/net/wireless/ath/carl9170/hw.h b/drivers/net/wireless/ath/carl9170/hw.h
index 4e30762dd903..fa834c1460f0 100644
--- a/drivers/net/wireless/ath/carl9170/hw.h
+++ b/drivers/net/wireless/ath/carl9170/hw.h
@@ -4,7 +4,7 @@
4 * Register map, hardware-specific definitions 4 * Register map, hardware-specific definitions
5 * 5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> 7 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -174,6 +174,7 @@
174#define AR9170_MAC_SNIFFER_ENABLE_PROMISC BIT(0) 174#define AR9170_MAC_SNIFFER_ENABLE_PROMISC BIT(0)
175#define AR9170_MAC_SNIFFER_DEFAULTS 0x02000000 175#define AR9170_MAC_SNIFFER_DEFAULTS 0x02000000
176#define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678) 176#define AR9170_MAC_REG_ENCRYPTION (AR9170_MAC_REG_BASE + 0x678)
177#define AR9170_MAC_ENCRYPTION_MGMT_RX_SOFTWARE BIT(2)
177#define AR9170_MAC_ENCRYPTION_RX_SOFTWARE BIT(3) 178#define AR9170_MAC_ENCRYPTION_RX_SOFTWARE BIT(3)
178#define AR9170_MAC_ENCRYPTION_DEFAULTS 0x70 179#define AR9170_MAC_ENCRYPTION_DEFAULTS 0x70
179 180
@@ -222,6 +223,12 @@
222#define AR9170_MAC_REG_TX_BLOCKACKS (AR9170_MAC_REG_BASE + 0x6c0) 223#define AR9170_MAC_REG_TX_BLOCKACKS (AR9170_MAC_REG_BASE + 0x6c0)
223#define AR9170_MAC_REG_NAV_COUNT (AR9170_MAC_REG_BASE + 0x6c4) 224#define AR9170_MAC_REG_NAV_COUNT (AR9170_MAC_REG_BASE + 0x6c4)
224#define AR9170_MAC_REG_BACKOFF_STATUS (AR9170_MAC_REG_BASE + 0x6c8) 225#define AR9170_MAC_REG_BACKOFF_STATUS (AR9170_MAC_REG_BASE + 0x6c8)
226#define AR9170_MAC_BACKOFF_CCA BIT(24)
227#define AR9170_MAC_BACKOFF_TX_PEX BIT(25)
228#define AR9170_MAC_BACKOFF_RX_PE BIT(26)
229#define AR9170_MAC_BACKOFF_MD_READY BIT(27)
230#define AR9170_MAC_BACKOFF_TX_PE BIT(28)
231
225#define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6cc) 232#define AR9170_MAC_REG_TX_RETRY (AR9170_MAC_REG_BASE + 0x6cc)
226 233
227#define AR9170_MAC_REG_TX_COMPLETE (AR9170_MAC_REG_BASE + 0x6d4) 234#define AR9170_MAC_REG_TX_COMPLETE (AR9170_MAC_REG_BASE + 0x6d4)
@@ -357,7 +364,18 @@
357 364
358#define AR9170_MAC_REG_DMA_WLAN_STATUS (AR9170_MAC_REG_BASE + 0xd38) 365#define AR9170_MAC_REG_DMA_WLAN_STATUS (AR9170_MAC_REG_BASE + 0xd38)
359#define AR9170_MAC_REG_DMA_STATUS (AR9170_MAC_REG_BASE + 0xd3c) 366#define AR9170_MAC_REG_DMA_STATUS (AR9170_MAC_REG_BASE + 0xd3c)
360 367#define AR9170_MAC_REG_DMA_TXQ_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd40)
368#define AR9170_MAC_REG_DMA_TXQ0_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd40)
369#define AR9170_MAC_REG_DMA_TXQ1_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd44)
370#define AR9170_MAC_REG_DMA_TXQ2_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd48)
371#define AR9170_MAC_REG_DMA_TXQ3_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd4c)
372#define AR9170_MAC_REG_DMA_TXQ4_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd50)
373#define AR9170_MAC_REG_DMA_TXQ0Q1_LEN (AR9170_MAC_REG_BASE + 0xd54)
374#define AR9170_MAC_REG_DMA_TXQ2Q3_LEN (AR9170_MAC_REG_BASE + 0xd58)
375#define AR9170_MAC_REG_DMA_TXQ4_LEN (AR9170_MAC_REG_BASE + 0xd5c)
376
377#define AR9170_MAC_REG_DMA_TXQX_LAST_ADDR (AR9170_MAC_REG_BASE + 0xd74)
378#define AR9170_MAC_REG_DMA_TXQX_FAIL_ADDR (AR9170_MAC_REG_BASE + 0xd78)
361#define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xd7c) 379#define AR9170_MAC_REG_TXRX_MPI (AR9170_MAC_REG_BASE + 0xd7c)
362#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f 380#define AR9170_MAC_TXRX_MPI_TX_MPI_MASK 0x0000000f
363#define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0 381#define AR9170_MAC_TXRX_MPI_TX_TO_MASK 0x0000fff0
@@ -377,10 +395,40 @@
377 395
378#define AR9170_MAC_REG_BCN_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd98) 396#define AR9170_MAC_REG_BCN_CURR_ADDR (AR9170_MAC_REG_BASE + 0xd98)
379#define AR9170_MAC_REG_BCN_COUNT (AR9170_MAC_REG_BASE + 0xd9c) 397#define AR9170_MAC_REG_BCN_COUNT (AR9170_MAC_REG_BASE + 0xd9c)
380
381
382#define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xda0) 398#define AR9170_MAC_REG_BCN_HT1 (AR9170_MAC_REG_BASE + 0xda0)
399#define AR9170_MAC_BCN_HT1_HT_EN BIT(0)
400#define AR9170_MAC_BCN_HT1_GF_PMB BIT(1)
401#define AR9170_MAC_BCN_HT1_SP_EXP BIT(2)
402#define AR9170_MAC_BCN_HT1_TX_BF BIT(3)
403#define AR9170_MAC_BCN_HT1_PWR_CTRL_S 4
404#define AR9170_MAC_BCN_HT1_PWR_CTRL 0x70
405#define AR9170_MAC_BCN_HT1_TX_ANT1 BIT(7)
406#define AR9170_MAC_BCN_HT1_TX_ANT0 BIT(8)
407#define AR9170_MAC_BCN_HT1_NUM_LFT_S 9
408#define AR9170_MAC_BCN_HT1_NUM_LFT 0x600
409#define AR9170_MAC_BCN_HT1_BWC_20M_EXT BIT(16)
410#define AR9170_MAC_BCN_HT1_BWC_40M_SHARED BIT(17)
411#define AR9170_MAC_BCN_HT1_BWC_40M_DUP (BIT(16) | BIT(17))
412#define AR9170_MAC_BCN_HT1_BF_MCS_S 18
413#define AR9170_MAC_BCN_HT1_BF_MCS 0x1c0000
414#define AR9170_MAC_BCN_HT1_TPC_S 21
415#define AR9170_MAC_BCN_HT1_TPC 0x7e00000
416#define AR9170_MAC_BCN_HT1_CHAIN_MASK_S 27
417#define AR9170_MAC_BCN_HT1_CHAIN_MASK 0x38000000
418
383#define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xda4) 419#define AR9170_MAC_REG_BCN_HT2 (AR9170_MAC_REG_BASE + 0xda4)
420#define AR9170_MAC_BCN_HT2_MCS_S 0
421#define AR9170_MAC_BCN_HT2_MCS 0x7f
422#define AR9170_MAC_BCN_HT2_BW40 BIT(8)
423#define AR9170_MAC_BCN_HT2_SMOOTHING BIT(9)
424#define AR9170_MAC_BCN_HT2_SS BIT(10)
425#define AR9170_MAC_BCN_HT2_NSS BIT(11)
426#define AR9170_MAC_BCN_HT2_STBC_S 12
427#define AR9170_MAC_BCN_HT2_STBC 0x3000
428#define AR9170_MAC_BCN_HT2_ADV_COD BIT(14)
429#define AR9170_MAC_BCN_HT2_SGI BIT(15)
430#define AR9170_MAC_BCN_HT2_LEN_S 16
431#define AR9170_MAC_BCN_HT2_LEN 0xffff0000
384 432
385#define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR (AR9170_MAC_REG_BASE + 0xdc0) 433#define AR9170_MAC_REG_DMA_TXQX_ADDR_CURR (AR9170_MAC_REG_BASE + 0xdc0)
386 434
diff --git a/drivers/net/wireless/ath/carl9170/led.c b/drivers/net/wireless/ath/carl9170/led.c
index 4bb2cbd8bd9b..78dadc797558 100644
--- a/drivers/net/wireless/ath/carl9170/led.c
+++ b/drivers/net/wireless/ath/carl9170/led.c
@@ -118,7 +118,7 @@ static void carl9170_led_set_brightness(struct led_classdev *led,
118 } 118 }
119 119
120 if (likely(IS_ACCEPTING_CMD(ar) && arl->toggled)) 120 if (likely(IS_ACCEPTING_CMD(ar) && arl->toggled))
121 ieee80211_queue_delayed_work(ar->hw, &ar->led_work, HZ/10); 121 ieee80211_queue_delayed_work(ar->hw, &ar->led_work, HZ / 10);
122} 122}
123 123
124static int carl9170_led_register_led(struct ar9170 *ar, int i, char *name, 124static int carl9170_led_register_led(struct ar9170 *ar, int i, char *name,
diff --git a/drivers/net/wireless/ath/carl9170/mac.c b/drivers/net/wireless/ath/carl9170/mac.c
index 385cf508479b..dfda91970995 100644
--- a/drivers/net/wireless/ath/carl9170/mac.c
+++ b/drivers/net/wireless/ath/carl9170/mac.c
@@ -455,135 +455,6 @@ int carl9170_set_beacon_timers(struct ar9170 *ar)
455 return carl9170_regwrite_result(); 455 return carl9170_regwrite_result();
456} 456}
457 457
458int carl9170_update_beacon(struct ar9170 *ar, const bool submit)
459{
460 struct sk_buff *skb = NULL;
461 struct carl9170_vif_info *cvif;
462 struct ieee80211_tx_info *txinfo;
463 __le32 *data, *old = NULL;
464 u32 word, off, addr, len;
465 int i = 0, err = 0;
466
467 rcu_read_lock();
468 cvif = rcu_dereference(ar->beacon_iter);
469retry:
470 if (ar->vifs == 0 || !cvif)
471 goto out_unlock;
472
473 list_for_each_entry_continue_rcu(cvif, &ar->vif_list, list) {
474 if (cvif->active && cvif->enable_beacon)
475 goto found;
476 }
477
478 if (!ar->beacon_enabled || i++)
479 goto out_unlock;
480
481 goto retry;
482
483found:
484 rcu_assign_pointer(ar->beacon_iter, cvif);
485
486 skb = ieee80211_beacon_get_tim(ar->hw, carl9170_get_vif(cvif),
487 NULL, NULL);
488
489 if (!skb) {
490 err = -ENOMEM;
491 goto err_free;
492 }
493
494 txinfo = IEEE80211_SKB_CB(skb);
495 if (txinfo->control.rates[0].flags & IEEE80211_TX_RC_MCS) {
496 err = -EINVAL;
497 goto err_free;
498 }
499
500 spin_lock_bh(&ar->beacon_lock);
501 data = (__le32 *)skb->data;
502 if (cvif->beacon)
503 old = (__le32 *)cvif->beacon->data;
504
505 off = cvif->id * AR9170_MAC_BCN_LENGTH_MAX;
506 addr = ar->fw.beacon_addr + off;
507 len = roundup(skb->len + FCS_LEN, 4);
508
509 if ((off + len) > ar->fw.beacon_max_len) {
510 if (net_ratelimit()) {
511 wiphy_err(ar->hw->wiphy, "beacon does not "
512 "fit into device memory!\n");
513 }
514 err = -EINVAL;
515 goto err_unlock;
516 }
517
518 if (len > AR9170_MAC_BCN_LENGTH_MAX) {
519 if (net_ratelimit()) {
520 wiphy_err(ar->hw->wiphy, "no support for beacons "
521 "bigger than %d (yours:%d).\n",
522 AR9170_MAC_BCN_LENGTH_MAX, len);
523 }
524
525 err = -EMSGSIZE;
526 goto err_unlock;
527 }
528
529 i = txinfo->control.rates[0].idx;
530 if (txinfo->band != IEEE80211_BAND_2GHZ)
531 i += 4;
532
533 word = __carl9170_ratetable[i].hw_value & 0xf;
534 if (i < 4)
535 word |= ((skb->len + FCS_LEN) << (3 + 16)) + 0x0400;
536 else
537 word |= ((skb->len + FCS_LEN) << 16) + 0x0010;
538
539 carl9170_async_regwrite_begin(ar);
540 carl9170_async_regwrite(AR9170_MAC_REG_BCN_PLCP, word);
541
542 for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
543 /*
544 * XXX: This accesses beyond skb data for up
545 * to the last 3 bytes!!
546 */
547
548 if (old && (data[i] == old[i]))
549 continue;
550
551 word = le32_to_cpu(data[i]);
552 carl9170_async_regwrite(addr + 4 * i, word);
553 }
554 carl9170_async_regwrite_finish();
555
556 dev_kfree_skb_any(cvif->beacon);
557 cvif->beacon = NULL;
558
559 err = carl9170_async_regwrite_result();
560 if (!err)
561 cvif->beacon = skb;
562 spin_unlock_bh(&ar->beacon_lock);
563 if (err)
564 goto err_free;
565
566 if (submit) {
567 err = carl9170_bcn_ctrl(ar, cvif->id,
568 CARL9170_BCN_CTRL_CAB_TRIGGER,
569 addr, skb->len + FCS_LEN);
570
571 if (err)
572 goto err_free;
573 }
574out_unlock:
575 rcu_read_unlock();
576 return 0;
577
578err_unlock:
579 spin_unlock_bh(&ar->beacon_lock);
580
581err_free:
582 rcu_read_unlock();
583 dev_kfree_skb_any(skb);
584 return err;
585}
586
587int carl9170_upload_key(struct ar9170 *ar, const u8 id, const u8 *mac, 458int carl9170_upload_key(struct ar9170 *ar, const u8 id, const u8 *mac,
588 const u8 ktype, const u8 keyidx, const u8 *keydata, 459 const u8 ktype, const u8 keyidx, const u8 *keydata,
589 const int keylen) 460 const int keylen)
diff --git a/drivers/net/wireless/ath/carl9170/main.c b/drivers/net/wireless/ath/carl9170/main.c
index 54d093c2ab44..0122930b14c7 100644
--- a/drivers/net/wireless/ath/carl9170/main.c
+++ b/drivers/net/wireless/ath/carl9170/main.c
@@ -345,11 +345,11 @@ static int carl9170_op_start(struct ieee80211_hw *hw)
345 carl9170_zap_queues(ar); 345 carl9170_zap_queues(ar);
346 346
347 /* reset QoS defaults */ 347 /* reset QoS defaults */
348 CARL9170_FILL_QUEUE(ar->edcf[0], 3, 15, 1023, 0); /* BEST EFFORT */ 348 CARL9170_FILL_QUEUE(ar->edcf[AR9170_TXQ_VO], 2, 3, 7, 47);
349 CARL9170_FILL_QUEUE(ar->edcf[1], 2, 7, 15, 94); /* VIDEO */ 349 CARL9170_FILL_QUEUE(ar->edcf[AR9170_TXQ_VI], 2, 7, 15, 94);
350 CARL9170_FILL_QUEUE(ar->edcf[2], 2, 3, 7, 47); /* VOICE */ 350 CARL9170_FILL_QUEUE(ar->edcf[AR9170_TXQ_BE], 3, 15, 1023, 0);
351 CARL9170_FILL_QUEUE(ar->edcf[3], 7, 15, 1023, 0); /* BACKGROUND */ 351 CARL9170_FILL_QUEUE(ar->edcf[AR9170_TXQ_BK], 7, 15, 1023, 0);
352 CARL9170_FILL_QUEUE(ar->edcf[4], 2, 3, 7, 0); /* SPECIAL */ 352 CARL9170_FILL_QUEUE(ar->edcf[AR9170_TXQ_SPECIAL], 2, 3, 7, 0);
353 353
354 ar->current_factor = ar->current_density = -1; 354 ar->current_factor = ar->current_density = -1;
355 /* "The first key is unique." */ 355 /* "The first key is unique." */
@@ -1484,6 +1484,13 @@ static void carl9170_op_sta_notify(struct ieee80211_hw *hw,
1484 } 1484 }
1485} 1485}
1486 1486
1487static bool carl9170_tx_frames_pending(struct ieee80211_hw *hw)
1488{
1489 struct ar9170 *ar = hw->priv;
1490
1491 return !!atomic_read(&ar->tx_total_queued);
1492}
1493
1487static const struct ieee80211_ops carl9170_ops = { 1494static const struct ieee80211_ops carl9170_ops = {
1488 .start = carl9170_op_start, 1495 .start = carl9170_op_start,
1489 .stop = carl9170_op_stop, 1496 .stop = carl9170_op_stop,
@@ -1504,6 +1511,7 @@ static const struct ieee80211_ops carl9170_ops = {
1504 .get_survey = carl9170_op_get_survey, 1511 .get_survey = carl9170_op_get_survey,
1505 .get_stats = carl9170_op_get_stats, 1512 .get_stats = carl9170_op_get_stats,
1506 .ampdu_action = carl9170_op_ampdu_action, 1513 .ampdu_action = carl9170_op_ampdu_action,
1514 .tx_frames_pending = carl9170_tx_frames_pending,
1507}; 1515};
1508 1516
1509void *carl9170_alloc(size_t priv_size) 1517void *carl9170_alloc(size_t priv_size)
@@ -1577,6 +1585,7 @@ void *carl9170_alloc(size_t priv_size)
1577 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 1585 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
1578 IEEE80211_HW_SUPPORTS_PS | 1586 IEEE80211_HW_SUPPORTS_PS |
1579 IEEE80211_HW_PS_NULLFUNC_STACK | 1587 IEEE80211_HW_PS_NULLFUNC_STACK |
1588 IEEE80211_HW_NEED_DTIM_PERIOD |
1580 IEEE80211_HW_SIGNAL_DBM; 1589 IEEE80211_HW_SIGNAL_DBM;
1581 1590
1582 if (!modparam_noht) { 1591 if (!modparam_noht) {
@@ -1621,7 +1630,7 @@ static int carl9170_read_eeprom(struct ar9170 *ar)
1621 BUILD_BUG_ON(sizeof(ar->eeprom) % RB); 1630 BUILD_BUG_ON(sizeof(ar->eeprom) % RB);
1622#endif 1631#endif
1623 1632
1624 for (i = 0; i < sizeof(ar->eeprom)/RB; i++) { 1633 for (i = 0; i < sizeof(ar->eeprom) / RB; i++) {
1625 for (j = 0; j < RW; j++) 1634 for (j = 0; j < RW; j++)
1626 offsets[j] = cpu_to_le32(AR9170_EEPROM_START + 1635 offsets[j] = cpu_to_le32(AR9170_EEPROM_START +
1627 RB * i + 4 * j); 1636 RB * i + 4 * j);
diff --git a/drivers/net/wireless/ath/carl9170/phy.c b/drivers/net/wireless/ath/carl9170/phy.c
index b6ae0e179c8d..aa147a9120b6 100644
--- a/drivers/net/wireless/ath/carl9170/phy.c
+++ b/drivers/net/wireless/ath/carl9170/phy.c
@@ -1098,7 +1098,7 @@ static u8 carl9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2)
1098 * Isn't it just DIV_ROUND_UP(y, 1<<SHIFT)? 1098 * Isn't it just DIV_ROUND_UP(y, 1<<SHIFT)?
1099 * Can we rely on the compiler to optimise away the div? 1099 * Can we rely on the compiler to optimise away the div?
1100 */ 1100 */
1101 return (y >> SHIFT) + ((y & (1<<(SHIFT-1))) >> (SHIFT - 1)); 1101 return (y >> SHIFT) + ((y & (1 << (SHIFT - 1))) >> (SHIFT - 1));
1102#undef SHIFT 1102#undef SHIFT
1103} 1103}
1104 1104
@@ -1379,7 +1379,7 @@ static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw)
1379 1379
1380 modes[i].max_power = 1380 modes[i].max_power =
1381 carl9170_get_max_edge_power(ar, 1381 carl9170_get_max_edge_power(ar,
1382 freq+f_off, EDGES(ctl_idx, 1)); 1382 freq + f_off, EDGES(ctl_idx, 1));
1383 1383
1384 /* 1384 /*
1385 * TODO: check if the regulatory max. power is 1385 * TODO: check if the regulatory max. power is
@@ -1441,7 +1441,7 @@ static int carl9170_set_power_cal(struct ar9170 *ar, u32 freq,
1441 if (freq < 3000) 1441 if (freq < 3000)
1442 f = freq - 2300; 1442 f = freq - 2300;
1443 else 1443 else
1444 f = (freq - 4800)/5; 1444 f = (freq - 4800) / 5;
1445 1445
1446 /* 1446 /*
1447 * cycle through the various modes 1447 * cycle through the various modes
@@ -1783,12 +1783,6 @@ int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
1783 } 1783 }
1784 } 1784 }
1785 1785
1786 /* FIXME: PSM does not work in 5GHz Band */
1787 if (channel->band == IEEE80211_BAND_5GHZ)
1788 ar->ps.off_override |= PS_OFF_5GHZ;
1789 else
1790 ar->ps.off_override &= ~PS_OFF_5GHZ;
1791
1792 ar->channel = channel; 1786 ar->channel = channel;
1793 ar->ht_settings = new_ht; 1787 ar->ht_settings = new_ht;
1794 return 0; 1788 return 0;
diff --git a/drivers/net/wireless/ath/carl9170/rx.c b/drivers/net/wireless/ath/carl9170/rx.c
index ec21ea9fd8d5..dc99030ea8b6 100644
--- a/drivers/net/wireless/ath/carl9170/rx.c
+++ b/drivers/net/wireless/ath/carl9170/rx.c
@@ -472,7 +472,7 @@ static struct sk_buff *carl9170_rx_copy_data(u8 *buf, int len)
472 u8 *qc = ieee80211_get_qos_ctl(hdr); 472 u8 *qc = ieee80211_get_qos_ctl(hdr);
473 reserved += NET_IP_ALIGN; 473 reserved += NET_IP_ALIGN;
474 474
475 if (*qc & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT) 475 if (*qc & IEEE80211_QOS_CTL_A_MSDU_PRESENT)
476 reserved += NET_IP_ALIGN; 476 reserved += NET_IP_ALIGN;
477 } 477 }
478 478
diff --git a/drivers/net/wireless/ath/carl9170/tx.c b/drivers/net/wireless/ath/carl9170/tx.c
index e94084fcf6f5..d20946939cd8 100644
--- a/drivers/net/wireless/ath/carl9170/tx.c
+++ b/drivers/net/wireless/ath/carl9170/tx.c
@@ -661,11 +661,67 @@ void carl9170_tx_process_status(struct ar9170 *ar,
661 } 661 }
662} 662}
663 663
664static void carl9170_tx_rate_tpc_chains(struct ar9170 *ar,
665 struct ieee80211_tx_info *info, struct ieee80211_tx_rate *txrate,
666 unsigned int *phyrate, unsigned int *tpc, unsigned int *chains)
667{
668 struct ieee80211_rate *rate = NULL;
669 u8 *txpower;
670 unsigned int idx;
671
672 idx = txrate->idx;
673 *tpc = 0;
674 *phyrate = 0;
675
676 if (txrate->flags & IEEE80211_TX_RC_MCS) {
677 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) {
678 /* +1 dBm for HT40 */
679 *tpc += 2;
680
681 if (info->band == IEEE80211_BAND_2GHZ)
682 txpower = ar->power_2G_ht40;
683 else
684 txpower = ar->power_5G_ht40;
685 } else {
686 if (info->band == IEEE80211_BAND_2GHZ)
687 txpower = ar->power_2G_ht20;
688 else
689 txpower = ar->power_5G_ht20;
690 }
691
692 *phyrate = txrate->idx;
693 *tpc += txpower[idx & 7];
694 } else {
695 if (info->band == IEEE80211_BAND_2GHZ) {
696 if (idx < 4)
697 txpower = ar->power_2G_cck;
698 else
699 txpower = ar->power_2G_ofdm;
700 } else {
701 txpower = ar->power_5G_leg;
702 idx += 4;
703 }
704
705 rate = &__carl9170_ratetable[idx];
706 *tpc += txpower[(rate->hw_value & 0x30) >> 4];
707 *phyrate = rate->hw_value & 0xf;
708 }
709
710 if (ar->eeprom.tx_mask == 1) {
711 *chains = AR9170_TX_PHY_TXCHAIN_1;
712 } else {
713 if (!(txrate->flags & IEEE80211_TX_RC_MCS) &&
714 rate && rate->bitrate >= 360)
715 *chains = AR9170_TX_PHY_TXCHAIN_1;
716 else
717 *chains = AR9170_TX_PHY_TXCHAIN_2;
718 }
719}
720
664static __le32 carl9170_tx_physet(struct ar9170 *ar, 721static __le32 carl9170_tx_physet(struct ar9170 *ar,
665 struct ieee80211_tx_info *info, struct ieee80211_tx_rate *txrate) 722 struct ieee80211_tx_info *info, struct ieee80211_tx_rate *txrate)
666{ 723{
667 struct ieee80211_rate *rate = NULL; 724 unsigned int power = 0, chains = 0, phyrate = 0;
668 u32 power, chains;
669 __le32 tmp; 725 __le32 tmp;
670 726
671 tmp = cpu_to_le32(0); 727 tmp = cpu_to_le32(0);
@@ -682,35 +738,12 @@ static __le32 carl9170_tx_physet(struct ar9170 *ar,
682 tmp |= cpu_to_le32(AR9170_TX_PHY_SHORT_GI); 738 tmp |= cpu_to_le32(AR9170_TX_PHY_SHORT_GI);
683 739
684 if (txrate->flags & IEEE80211_TX_RC_MCS) { 740 if (txrate->flags & IEEE80211_TX_RC_MCS) {
685 u32 r = txrate->idx; 741 SET_VAL(AR9170_TX_PHY_MCS, phyrate, txrate->idx);
686 u8 *txpower;
687 742
688 /* heavy clip control */ 743 /* heavy clip control */
689 tmp |= cpu_to_le32((r & 0x7) << 744 tmp |= cpu_to_le32((txrate->idx & 0x7) <<
690 AR9170_TX_PHY_TX_HEAVY_CLIP_S); 745 AR9170_TX_PHY_TX_HEAVY_CLIP_S);
691 746
692 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) {
693 if (info->band == IEEE80211_BAND_5GHZ)
694 txpower = ar->power_5G_ht40;
695 else
696 txpower = ar->power_2G_ht40;
697 } else {
698 if (info->band == IEEE80211_BAND_5GHZ)
699 txpower = ar->power_5G_ht20;
700 else
701 txpower = ar->power_2G_ht20;
702 }
703
704 power = txpower[r & 7];
705
706 /* +1 dBm for HT40 */
707 if (txrate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
708 power += 2;
709
710 r <<= AR9170_TX_PHY_MCS_S;
711 BUG_ON(r & ~AR9170_TX_PHY_MCS);
712
713 tmp |= cpu_to_le32(r & AR9170_TX_PHY_MCS);
714 tmp |= cpu_to_le32(AR9170_TX_PHY_MOD_HT); 747 tmp |= cpu_to_le32(AR9170_TX_PHY_MOD_HT);
715 748
716 /* 749 /*
@@ -720,34 +753,15 @@ static __le32 carl9170_tx_physet(struct ar9170 *ar,
720 * tmp |= cpu_to_le32(AR9170_TX_PHY_GREENFIELD); 753 * tmp |= cpu_to_le32(AR9170_TX_PHY_GREENFIELD);
721 */ 754 */
722 } else { 755 } else {
723 u8 *txpower; 756 if (info->band == IEEE80211_BAND_2GHZ) {
724 u32 mod; 757 if (txrate->idx <= AR9170_TX_PHY_RATE_CCK_11M)
725 u32 phyrate; 758 tmp |= cpu_to_le32(AR9170_TX_PHY_MOD_CCK);
726 u8 idx = txrate->idx; 759 else
727 760 tmp |= cpu_to_le32(AR9170_TX_PHY_MOD_OFDM);
728 if (info->band != IEEE80211_BAND_2GHZ) {
729 idx += 4;
730 txpower = ar->power_5G_leg;
731 mod = AR9170_TX_PHY_MOD_OFDM;
732 } else { 761 } else {
733 if (idx < 4) { 762 tmp |= cpu_to_le32(AR9170_TX_PHY_MOD_OFDM);
734 txpower = ar->power_2G_cck;
735 mod = AR9170_TX_PHY_MOD_CCK;
736 } else {
737 mod = AR9170_TX_PHY_MOD_OFDM;
738 txpower = ar->power_2G_ofdm;
739 }
740 } 763 }
741 764
742 rate = &__carl9170_ratetable[idx];
743
744 phyrate = rate->hw_value & 0xF;
745 power = txpower[(rate->hw_value & 0x30) >> 4];
746 phyrate <<= AR9170_TX_PHY_MCS_S;
747
748 tmp |= cpu_to_le32(mod);
749 tmp |= cpu_to_le32(phyrate);
750
751 /* 765 /*
752 * short preamble seems to be broken too. 766 * short preamble seems to be broken too.
753 * 767 *
@@ -755,23 +769,12 @@ static __le32 carl9170_tx_physet(struct ar9170 *ar,
755 * tmp |= cpu_to_le32(AR9170_TX_PHY_SHORT_PREAMBLE); 769 * tmp |= cpu_to_le32(AR9170_TX_PHY_SHORT_PREAMBLE);
756 */ 770 */
757 } 771 }
758 power <<= AR9170_TX_PHY_TX_PWR_S; 772 carl9170_tx_rate_tpc_chains(ar, info, txrate,
759 power &= AR9170_TX_PHY_TX_PWR; 773 &phyrate, &power, &chains);
760 tmp |= cpu_to_le32(power);
761
762 /* set TX chains */
763 if (ar->eeprom.tx_mask == 1) {
764 chains = AR9170_TX_PHY_TXCHAIN_1;
765 } else {
766 chains = AR9170_TX_PHY_TXCHAIN_2;
767
768 /* >= 36M legacy OFDM - use only one chain */
769 if (rate && rate->bitrate >= 360 &&
770 !(txrate->flags & IEEE80211_TX_RC_MCS))
771 chains = AR9170_TX_PHY_TXCHAIN_1;
772 }
773 tmp |= cpu_to_le32(chains << AR9170_TX_PHY_TXCHAIN_S);
774 774
775 tmp |= cpu_to_le32(SET_CONSTVAL(AR9170_TX_PHY_MCS, phyrate));
776 tmp |= cpu_to_le32(SET_CONSTVAL(AR9170_TX_PHY_TX_PWR, power));
777 tmp |= cpu_to_le32(SET_CONSTVAL(AR9170_TX_PHY_TXCHAIN, chains));
775 return tmp; 778 return tmp;
776} 779}
777 780
@@ -1438,3 +1441,154 @@ void carl9170_tx_scheduler(struct ar9170 *ar)
1438 if (ar->tx_schedule) 1441 if (ar->tx_schedule)
1439 carl9170_tx(ar); 1442 carl9170_tx(ar);
1440} 1443}
1444
1445int carl9170_update_beacon(struct ar9170 *ar, const bool submit)
1446{
1447 struct sk_buff *skb = NULL;
1448 struct carl9170_vif_info *cvif;
1449 struct ieee80211_tx_info *txinfo;
1450 struct ieee80211_tx_rate *rate;
1451 __le32 *data, *old = NULL;
1452 unsigned int plcp, power, chains;
1453 u32 word, ht1, off, addr, len;
1454 int i = 0, err = 0;
1455
1456 rcu_read_lock();
1457 cvif = rcu_dereference(ar->beacon_iter);
1458retry:
1459 if (ar->vifs == 0 || !cvif)
1460 goto out_unlock;
1461
1462 list_for_each_entry_continue_rcu(cvif, &ar->vif_list, list) {
1463 if (cvif->active && cvif->enable_beacon)
1464 goto found;
1465 }
1466
1467 if (!ar->beacon_enabled || i++)
1468 goto out_unlock;
1469
1470 goto retry;
1471
1472found:
1473 rcu_assign_pointer(ar->beacon_iter, cvif);
1474
1475 skb = ieee80211_beacon_get_tim(ar->hw, carl9170_get_vif(cvif),
1476 NULL, NULL);
1477
1478 if (!skb) {
1479 err = -ENOMEM;
1480 goto err_free;
1481 }
1482
1483 txinfo = IEEE80211_SKB_CB(skb);
1484 spin_lock_bh(&ar->beacon_lock);
1485 data = (__le32 *)skb->data;
1486 if (cvif->beacon)
1487 old = (__le32 *)cvif->beacon->data;
1488
1489 off = cvif->id * AR9170_MAC_BCN_LENGTH_MAX;
1490 addr = ar->fw.beacon_addr + off;
1491 len = roundup(skb->len + FCS_LEN, 4);
1492
1493 if ((off + len) > ar->fw.beacon_max_len) {
1494 if (net_ratelimit()) {
1495 wiphy_err(ar->hw->wiphy, "beacon does not "
1496 "fit into device memory!\n");
1497 }
1498 err = -EINVAL;
1499 goto err_unlock;
1500 }
1501
1502 if (len > AR9170_MAC_BCN_LENGTH_MAX) {
1503 if (net_ratelimit()) {
1504 wiphy_err(ar->hw->wiphy, "no support for beacons "
1505 "bigger than %d (yours:%d).\n",
1506 AR9170_MAC_BCN_LENGTH_MAX, len);
1507 }
1508
1509 err = -EMSGSIZE;
1510 goto err_unlock;
1511 }
1512
1513 ht1 = AR9170_MAC_BCN_HT1_TX_ANT0;
1514 rate = &txinfo->control.rates[0];
1515 carl9170_tx_rate_tpc_chains(ar, txinfo, rate, &plcp, &power, &chains);
1516 if (!(txinfo->control.rates[0].flags & IEEE80211_TX_RC_MCS)) {
1517 if (plcp <= AR9170_TX_PHY_RATE_CCK_11M)
1518 plcp |= ((skb->len + FCS_LEN) << (3 + 16)) + 0x0400;
1519 else
1520 plcp |= ((skb->len + FCS_LEN) << 16) + 0x0010;
1521 } else {
1522 ht1 |= AR9170_MAC_BCN_HT1_HT_EN;
1523 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
1524 plcp |= AR9170_MAC_BCN_HT2_SGI;
1525
1526 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) {
1527 ht1 |= AR9170_MAC_BCN_HT1_BWC_40M_SHARED;
1528 plcp |= AR9170_MAC_BCN_HT2_BW40;
1529 }
1530 if (rate->flags & IEEE80211_TX_RC_DUP_DATA) {
1531 ht1 |= AR9170_MAC_BCN_HT1_BWC_40M_DUP;
1532 plcp |= AR9170_MAC_BCN_HT2_BW40;
1533 }
1534
1535 SET_VAL(AR9170_MAC_BCN_HT2_LEN, plcp, skb->len + FCS_LEN);
1536 }
1537
1538 SET_VAL(AR9170_MAC_BCN_HT1_PWR_CTRL, ht1, 7);
1539 SET_VAL(AR9170_MAC_BCN_HT1_TPC, ht1, power);
1540 SET_VAL(AR9170_MAC_BCN_HT1_CHAIN_MASK, ht1, chains);
1541 if (chains == AR9170_TX_PHY_TXCHAIN_2)
1542 ht1 |= AR9170_MAC_BCN_HT1_TX_ANT1;
1543
1544 carl9170_async_regwrite_begin(ar);
1545 carl9170_async_regwrite(AR9170_MAC_REG_BCN_HT1, ht1);
1546 if (!(txinfo->control.rates[0].flags & IEEE80211_TX_RC_MCS))
1547 carl9170_async_regwrite(AR9170_MAC_REG_BCN_PLCP, plcp);
1548 else
1549 carl9170_async_regwrite(AR9170_MAC_REG_BCN_HT2, plcp);
1550
1551 for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
1552 /*
1553 * XXX: This accesses beyond skb data for up
1554 * to the last 3 bytes!!
1555 */
1556
1557 if (old && (data[i] == old[i]))
1558 continue;
1559
1560 word = le32_to_cpu(data[i]);
1561 carl9170_async_regwrite(addr + 4 * i, word);
1562 }
1563 carl9170_async_regwrite_finish();
1564
1565 dev_kfree_skb_any(cvif->beacon);
1566 cvif->beacon = NULL;
1567
1568 err = carl9170_async_regwrite_result();
1569 if (!err)
1570 cvif->beacon = skb;
1571 spin_unlock_bh(&ar->beacon_lock);
1572 if (err)
1573 goto err_free;
1574
1575 if (submit) {
1576 err = carl9170_bcn_ctrl(ar, cvif->id,
1577 CARL9170_BCN_CTRL_CAB_TRIGGER,
1578 addr, skb->len + FCS_LEN);
1579
1580 if (err)
1581 goto err_free;
1582 }
1583out_unlock:
1584 rcu_read_unlock();
1585 return 0;
1586
1587err_unlock:
1588 spin_unlock_bh(&ar->beacon_lock);
1589
1590err_free:
1591 rcu_read_unlock();
1592 dev_kfree_skb_any(skb);
1593 return err;
1594}
diff --git a/drivers/net/wireless/ath/carl9170/usb.c b/drivers/net/wireless/ath/carl9170/usb.c
index 2fb53d067512..333b69ef2ae2 100644
--- a/drivers/net/wireless/ath/carl9170/usb.c
+++ b/drivers/net/wireless/ath/carl9170/usb.c
@@ -112,6 +112,8 @@ static struct usb_device_id carl9170_usb_ids[] = {
112 { USB_DEVICE(0x04bb, 0x093f) }, 112 { USB_DEVICE(0x04bb, 0x093f) },
113 /* NEC WL300NU-G */ 113 /* NEC WL300NU-G */
114 { USB_DEVICE(0x0409, 0x0249) }, 114 { USB_DEVICE(0x0409, 0x0249) },
115 /* NEC WL300NU-AG */
116 { USB_DEVICE(0x0409, 0x02b4) },
115 /* AVM FRITZ!WLAN USB Stick N */ 117 /* AVM FRITZ!WLAN USB Stick N */
116 { USB_DEVICE(0x057c, 0x8401) }, 118 { USB_DEVICE(0x057c, 0x8401) },
117 /* AVM FRITZ!WLAN USB Stick N 2.4 */ 119 /* AVM FRITZ!WLAN USB Stick N 2.4 */
diff --git a/drivers/net/wireless/ath/carl9170/version.h b/drivers/net/wireless/ath/carl9170/version.h
index 15095c035169..64703778cfea 100644
--- a/drivers/net/wireless/ath/carl9170/version.h
+++ b/drivers/net/wireless/ath/carl9170/version.h
@@ -1,7 +1,7 @@
1#ifndef __CARL9170_SHARED_VERSION_H 1#ifndef __CARL9170_SHARED_VERSION_H
2#define __CARL9170_SHARED_VERSION_H 2#define __CARL9170_SHARED_VERSION_H
3#define CARL9170FW_VERSION_YEAR 11 3#define CARL9170FW_VERSION_YEAR 11
4#define CARL9170FW_VERSION_MONTH 1 4#define CARL9170FW_VERSION_MONTH 6
5#define CARL9170FW_VERSION_DAY 22 5#define CARL9170FW_VERSION_DAY 30
6#define CARL9170FW_VERSION_GIT "1.9.2" 6#define CARL9170FW_VERSION_GIT "1.9.4"
7#endif /* __CARL9170_SHARED_VERSION_H */ 7#endif /* __CARL9170_SHARED_VERSION_H */
diff --git a/drivers/net/wireless/ath/carl9170/wlan.h b/drivers/net/wireless/ath/carl9170/wlan.h
index 9e1324b67e08..ea17995b32f4 100644
--- a/drivers/net/wireless/ath/carl9170/wlan.h
+++ b/drivers/net/wireless/ath/carl9170/wlan.h
@@ -4,7 +4,7 @@
4 * RX/TX meta descriptor format 4 * RX/TX meta descriptor format
5 * 5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> 6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com> 7 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -278,7 +278,7 @@ struct ar9170_tx_frame {
278struct carl9170_tx_superframe { 278struct carl9170_tx_superframe {
279 struct carl9170_tx_superdesc s; 279 struct carl9170_tx_superdesc s;
280 struct ar9170_tx_frame f; 280 struct ar9170_tx_frame f;
281} __packed; 281} __packed __aligned(4);
282 282
283#endif /* __CARL9170FW__ */ 283#endif /* __CARL9170FW__ */
284 284
@@ -328,7 +328,7 @@ struct _carl9170_tx_superframe {
328 struct _carl9170_tx_superdesc s; 328 struct _carl9170_tx_superdesc s;
329 struct _ar9170_tx_hwdesc f; 329 struct _ar9170_tx_hwdesc f;
330 u8 frame_data[0]; 330 u8 frame_data[0];
331} __packed; 331} __packed __aligned(4);
332 332
333#define CARL9170_TX_SUPERDESC_LEN 24 333#define CARL9170_TX_SUPERDESC_LEN 24
334#define AR9170_TX_HWDESC_LEN 8 334#define AR9170_TX_HWDESC_LEN 8
@@ -404,16 +404,6 @@ static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
404 (t->DAidx & 0xc0) >> 6; 404 (t->DAidx & 0xc0) >> 6;
405} 405}
406 406
407enum ar9170_txq {
408 AR9170_TXQ_BE,
409
410 AR9170_TXQ_VI,
411 AR9170_TXQ_VO,
412 AR9170_TXQ_BK,
413
414 __AR9170_NUM_TXQ,
415};
416
417/* 407/*
418 * This is an workaround for several undocumented bugs. 408 * This is an workaround for several undocumented bugs.
419 * Don't mess with the QoS/AC <-> HW Queue map, if you don't 409 * Don't mess with the QoS/AC <-> HW Queue map, if you don't
@@ -431,7 +421,14 @@ enum ar9170_txq {
431 * result, this makes the device pretty much useless 421 * result, this makes the device pretty much useless
432 * for any serious 802.11n setup. 422 * for any serious 802.11n setup.
433 */ 423 */
434static const u8 ar9170_qmap[__AR9170_NUM_TXQ] = { 2, 1, 0, 3 }; 424enum ar9170_txq {
425 AR9170_TXQ_BK = 0, /* TXQ0 */
426 AR9170_TXQ_BE, /* TXQ1 */
427 AR9170_TXQ_VI, /* TXQ2 */
428 AR9170_TXQ_VO, /* TXQ3 */
429
430 __AR9170_NUM_TXQ,
431};
435 432
436#define AR9170_TXQ_DEPTH 32 433#define AR9170_TXQ_DEPTH 32
437 434
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c
index a61ef3d6d89c..17b0efd86f9a 100644
--- a/drivers/net/wireless/ath/key.c
+++ b/drivers/net/wireless/ath/key.c
@@ -105,11 +105,8 @@ static bool ath_hw_keysetmac(struct ath_common *common,
105 if (mac[0] & 0x01) 105 if (mac[0] & 0x01)
106 unicast_flag = 0; 106 unicast_flag = 0;
107 107
108 macHi = (mac[5] << 8) | mac[4]; 108 macLo = get_unaligned_le32(mac);
109 macLo = (mac[3] << 24) | 109 macHi = get_unaligned_le16(mac + 4);
110 (mac[2] << 16) |
111 (mac[1] << 8) |
112 mac[0];
113 macLo >>= 1; 110 macLo >>= 1;
114 macLo |= (macHi & 1) << 31; 111 macLo |= (macHi & 1) << 31;
115 macHi >>= 1; 112 macHi >>= 1;
diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c
index 39a11e8af4fa..7e45ca2e78ef 100644
--- a/drivers/net/wireless/atmel.c
+++ b/drivers/net/wireless/atmel.c
@@ -40,6 +40,7 @@
40******************************************************************************/ 40******************************************************************************/
41 41
42#include <linux/init.h> 42#include <linux/init.h>
43#include <linux/interrupt.h>
43 44
44#include <linux/kernel.h> 45#include <linux/kernel.h>
45#include <linux/ptrace.h> 46#include <linux/ptrace.h>
diff --git a/drivers/net/wireless/b43/Kconfig b/drivers/net/wireless/b43/Kconfig
index 480595f04411..d2293dcc117f 100644
--- a/drivers/net/wireless/b43/Kconfig
+++ b/drivers/net/wireless/b43/Kconfig
@@ -26,6 +26,16 @@ config B43
26 This driver can be built as a module (recommended) that will be called "b43". 26 This driver can be built as a module (recommended) that will be called "b43".
27 If unsure, say M. 27 If unsure, say M.
28 28
29config B43_BCMA
30 bool "Support for BCMA bus"
31 depends on B43 && BCMA && BROKEN
32 default y
33
34config B43_SSB
35 bool
36 depends on B43 && SSB
37 default y
38
29# Auto-select SSB PCI-HOST support, if possible 39# Auto-select SSB PCI-HOST support, if possible
30config B43_PCI_AUTOSELECT 40config B43_PCI_AUTOSELECT
31 bool 41 bool
@@ -80,6 +90,12 @@ config B43_SDIO
80 90
81#Data transfers to the device via PIO. We want it as a fallback even 91#Data transfers to the device via PIO. We want it as a fallback even
82# if we can do DMA. 92# if we can do DMA.
93config B43_BCMA_PIO
94 bool
95 depends on B43_BCMA
96 select BCMA_BLOCKIO
97 default y
98
83config B43_PIO 99config B43_PIO
84 bool 100 bool
85 depends on B43 101 depends on B43
@@ -107,6 +123,22 @@ config B43_PHY_LP
107 and embedded devices. It supports 802.11a/g 123 and embedded devices. It supports 802.11a/g
108 (802.11a support is optional, and currently disabled). 124 (802.11a support is optional, and currently disabled).
109 125
126config B43_PHY_HT
127 bool "Support for HT-PHY devices (BROKEN)"
128 depends on B43 && BROKEN
129 ---help---
130 Support for the HT-PHY.
131
132 Say N, this is BROKEN and crashes driver.
133
134config B43_PHY_LCN
135 bool "Support for LCN-PHY devices (BROKEN)"
136 depends on B43 && BROKEN
137 ---help---
138 Support for the LCN-PHY.
139
140 Say N, this is BROKEN and crashes driver.
141
110# This config option automatically enables b43 LEDS support, 142# This config option automatically enables b43 LEDS support,
111# if it's possible. 143# if it's possible.
112config B43_LEDS 144config B43_LEDS
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
index cef334a8c669..4648bbf76abc 100644
--- a/drivers/net/wireless/b43/Makefile
+++ b/drivers/net/wireless/b43/Makefile
@@ -1,4 +1,5 @@
1b43-y += main.o 1b43-y += main.o
2b43-y += bus.o
2b43-y += tables.o 3b43-y += tables.o
3b43-$(CONFIG_B43_PHY_N) += tables_nphy.o 4b43-$(CONFIG_B43_PHY_N) += tables_nphy.o
4b43-$(CONFIG_B43_PHY_N) += radio_2055.o 5b43-$(CONFIG_B43_PHY_N) += radio_2055.o
@@ -9,6 +10,10 @@ b43-y += phy_a.o
9b43-$(CONFIG_B43_PHY_N) += phy_n.o 10b43-$(CONFIG_B43_PHY_N) += phy_n.o
10b43-$(CONFIG_B43_PHY_LP) += phy_lp.o 11b43-$(CONFIG_B43_PHY_LP) += phy_lp.o
11b43-$(CONFIG_B43_PHY_LP) += tables_lpphy.o 12b43-$(CONFIG_B43_PHY_LP) += tables_lpphy.o
13b43-$(CONFIG_B43_PHY_HT) += phy_ht.o
14b43-$(CONFIG_B43_PHY_HT) += tables_phy_ht.o
15b43-$(CONFIG_B43_PHY_HT) += radio_2059.o
16b43-$(CONFIG_B43_PHY_LCN) += phy_lcn.o tables_phy_lcn.o
12b43-y += sysfs.o 17b43-y += sysfs.o
13b43-y += xmit.o 18b43-y += xmit.o
14b43-y += lo.o 19b43-y += lo.o
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 25a78cfb7d15..c818b0bc88ec 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -5,12 +5,14 @@
5#include <linux/spinlock.h> 5#include <linux/spinlock.h>
6#include <linux/interrupt.h> 6#include <linux/interrupt.h>
7#include <linux/hw_random.h> 7#include <linux/hw_random.h>
8#include <linux/bcma/bcma.h>
8#include <linux/ssb/ssb.h> 9#include <linux/ssb/ssb.h>
9#include <net/mac80211.h> 10#include <net/mac80211.h>
10 11
11#include "debugfs.h" 12#include "debugfs.h"
12#include "leds.h" 13#include "leds.h"
13#include "rfkill.h" 14#include "rfkill.h"
15#include "bus.h"
14#include "lo.h" 16#include "lo.h"
15#include "phy_common.h" 17#include "phy_common.h"
16 18
@@ -90,6 +92,8 @@
90#define B43_MMIO_PIO11_BASE4 0x300 92#define B43_MMIO_PIO11_BASE4 0x300
91#define B43_MMIO_PIO11_BASE5 0x340 93#define B43_MMIO_PIO11_BASE5 0x340
92 94
95#define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */
96#define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */
93#define B43_MMIO_PHY_VER 0x3E0 97#define B43_MMIO_PHY_VER 0x3E0
94#define B43_MMIO_PHY_RADIO 0x3E2 98#define B43_MMIO_PHY_RADIO 0x3E2
95#define B43_MMIO_PHY0 0x3E6 99#define B43_MMIO_PHY0 0x3E6
@@ -361,6 +365,10 @@ enum {
361#define B43_PHYTYPE_G 0x02 365#define B43_PHYTYPE_G 0x02
362#define B43_PHYTYPE_N 0x04 366#define B43_PHYTYPE_N 0x04
363#define B43_PHYTYPE_LP 0x05 367#define B43_PHYTYPE_LP 0x05
368#define B43_PHYTYPE_SSLPN 0x06
369#define B43_PHYTYPE_HT 0x07
370#define B43_PHYTYPE_LCN 0x08
371#define B43_PHYTYPE_LCNXN 0x09
364 372
365/* PHYRegisters */ 373/* PHYRegisters */
366#define B43_PHY_ILT_A_CTRL 0x0072 374#define B43_PHY_ILT_A_CTRL 0x0072
@@ -414,6 +422,23 @@ enum {
414#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */ 422#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
415#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */ 423#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
416 424
425/* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */
426#define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */
427#define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */
428#define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */
429#define B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */
430#define B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */
431#define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */
432#define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */
433#define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */
434#define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */
435
436/* BCMA 802.11 core specific IO status (BCMA_IOST) flags */
437#define B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */
438#define B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */
439#define B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */
440#define B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */
441
417/* 802.11 core specific TM State Low (SSB_TMSLOW) flags */ 442/* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
418#define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */ 443#define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
419#define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */ 444#define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */
@@ -569,6 +594,7 @@ struct b43_dma {
569 struct b43_dmaring *rx_ring; 594 struct b43_dmaring *rx_ring;
570 595
571 u32 translation; /* Routing bits */ 596 u32 translation; /* Routing bits */
597 bool parity; /* Check for parity */
572}; 598};
573 599
574struct b43_pio_txqueue; 600struct b43_pio_txqueue;
@@ -707,7 +733,7 @@ enum {
707 733
708/* Data structure for one wireless device (802.11 core) */ 734/* Data structure for one wireless device (802.11 core) */
709struct b43_wldev { 735struct b43_wldev {
710 struct ssb_device *sdev; 736 struct b43_bus_dev *dev;
711 struct b43_wl *wl; 737 struct b43_wl *wl;
712 738
713 /* The device initialization status. 739 /* The device initialization status.
@@ -879,36 +905,59 @@ static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
879 return wl->hw->conf.channel->band; 905 return wl->hw->conf.channel->band;
880} 906}
881 907
908static inline int b43_bus_may_powerdown(struct b43_wldev *wldev)
909{
910 return wldev->dev->bus_may_powerdown(wldev->dev);
911}
912static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl)
913{
914 return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl);
915}
916static inline int b43_device_is_enabled(struct b43_wldev *wldev)
917{
918 return wldev->dev->device_is_enabled(wldev->dev);
919}
920static inline void b43_device_enable(struct b43_wldev *wldev,
921 u32 core_specific_flags)
922{
923 wldev->dev->device_enable(wldev->dev, core_specific_flags);
924}
925static inline void b43_device_disable(struct b43_wldev *wldev,
926 u32 core_specific_flags)
927{
928 wldev->dev->device_disable(wldev->dev, core_specific_flags);
929}
930
882static inline u16 b43_read16(struct b43_wldev *dev, u16 offset) 931static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
883{ 932{
884 return ssb_read16(dev->sdev, offset); 933 return dev->dev->read16(dev->dev, offset);
885} 934}
886 935
887static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value) 936static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
888{ 937{
889 ssb_write16(dev->sdev, offset, value); 938 dev->dev->write16(dev->dev, offset, value);
890} 939}
891 940
892static inline u32 b43_read32(struct b43_wldev *dev, u16 offset) 941static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
893{ 942{
894 return ssb_read32(dev->sdev, offset); 943 return dev->dev->read32(dev->dev, offset);
895} 944}
896 945
897static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value) 946static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
898{ 947{
899 ssb_write32(dev->sdev, offset, value); 948 dev->dev->write32(dev->dev, offset, value);
900} 949}
901 950
902static inline void b43_block_read(struct b43_wldev *dev, void *buffer, 951static inline void b43_block_read(struct b43_wldev *dev, void *buffer,
903 size_t count, u16 offset, u8 reg_width) 952 size_t count, u16 offset, u8 reg_width)
904{ 953{
905 ssb_block_read(dev->sdev, buffer, count, offset, reg_width); 954 dev->dev->block_read(dev->dev, buffer, count, offset, reg_width);
906} 955}
907 956
908static inline void b43_block_write(struct b43_wldev *dev, const void *buffer, 957static inline void b43_block_write(struct b43_wldev *dev, const void *buffer,
909 size_t count, u16 offset, u8 reg_width) 958 size_t count, u16 offset, u8 reg_width)
910{ 959{
911 ssb_block_write(dev->sdev, buffer, count, offset, reg_width); 960 dev->dev->block_write(dev->dev, buffer, count, offset, reg_width);
912} 961}
913 962
914static inline bool b43_using_pio_transfers(struct b43_wldev *dev) 963static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
diff --git a/drivers/net/wireless/b43/bus.c b/drivers/net/wireless/b43/bus.c
new file mode 100644
index 000000000000..64c3f65ff8c0
--- /dev/null
+++ b/drivers/net/wireless/b43/bus.c
@@ -0,0 +1,253 @@
1/*
2
3 Broadcom B43 wireless driver
4 Bus abstraction layer
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
19 Boston, MA 02110-1301, USA.
20
21*/
22
23#include "b43.h"
24#include "bus.h"
25
26/* BCMA */
27#ifdef CONFIG_B43_BCMA
28static int b43_bus_bcma_bus_may_powerdown(struct b43_bus_dev *dev)
29{
30 return 0; /* bcma_bus_may_powerdown(dev->bdev->bus); */
31}
32static int b43_bus_bcma_bus_powerup(struct b43_bus_dev *dev,
33 bool dynamic_pctl)
34{
35 return 0; /* bcma_bus_powerup(dev->sdev->bus, dynamic_pctl); */
36}
37static int b43_bus_bcma_device_is_enabled(struct b43_bus_dev *dev)
38{
39 return bcma_core_is_enabled(dev->bdev);
40}
41static void b43_bus_bcma_device_enable(struct b43_bus_dev *dev,
42 u32 core_specific_flags)
43{
44 bcma_core_enable(dev->bdev, core_specific_flags);
45}
46static void b43_bus_bcma_device_disable(struct b43_bus_dev *dev,
47 u32 core_specific_flags)
48{
49 bcma_core_disable(dev->bdev, core_specific_flags);
50}
51static u16 b43_bus_bcma_read16(struct b43_bus_dev *dev, u16 offset)
52{
53 return bcma_read16(dev->bdev, offset);
54}
55static u32 b43_bus_bcma_read32(struct b43_bus_dev *dev, u16 offset)
56{
57 return bcma_read32(dev->bdev, offset);
58}
59static
60void b43_bus_bcma_write16(struct b43_bus_dev *dev, u16 offset, u16 value)
61{
62 bcma_write16(dev->bdev, offset, value);
63}
64static
65void b43_bus_bcma_write32(struct b43_bus_dev *dev, u16 offset, u32 value)
66{
67 bcma_write32(dev->bdev, offset, value);
68}
69static
70void b43_bus_bcma_block_read(struct b43_bus_dev *dev, void *buffer,
71 size_t count, u16 offset, u8 reg_width)
72{
73 bcma_block_read(dev->bdev, buffer, count, offset, reg_width);
74}
75static
76void b43_bus_bcma_block_write(struct b43_bus_dev *dev, const void *buffer,
77 size_t count, u16 offset, u8 reg_width)
78{
79 bcma_block_write(dev->bdev, buffer, count, offset, reg_width);
80}
81
82struct b43_bus_dev *b43_bus_dev_bcma_init(struct bcma_device *core)
83{
84 struct b43_bus_dev *dev = kzalloc(sizeof(*dev), GFP_KERNEL);
85 if (!dev)
86 return NULL;
87
88 dev->bus_type = B43_BUS_BCMA;
89 dev->bdev = core;
90
91 dev->bus_may_powerdown = b43_bus_bcma_bus_may_powerdown;
92 dev->bus_powerup = b43_bus_bcma_bus_powerup;
93 dev->device_is_enabled = b43_bus_bcma_device_is_enabled;
94 dev->device_enable = b43_bus_bcma_device_enable;
95 dev->device_disable = b43_bus_bcma_device_disable;
96
97 dev->read16 = b43_bus_bcma_read16;
98 dev->read32 = b43_bus_bcma_read32;
99 dev->write16 = b43_bus_bcma_write16;
100 dev->write32 = b43_bus_bcma_write32;
101 dev->block_read = b43_bus_bcma_block_read;
102 dev->block_write = b43_bus_bcma_block_write;
103
104 dev->dev = &core->dev;
105 dev->dma_dev = core->dma_dev;
106 dev->irq = core->irq;
107
108 /*
109 dev->board_vendor = core->bus->boardinfo.vendor;
110 dev->board_type = core->bus->boardinfo.type;
111 dev->board_rev = core->bus->boardinfo.rev;
112 */
113
114 dev->chip_id = core->bus->chipinfo.id;
115 dev->chip_rev = core->bus->chipinfo.rev;
116 dev->chip_pkg = core->bus->chipinfo.pkg;
117
118 dev->bus_sprom = &core->bus->sprom;
119
120 dev->core_id = core->id.id;
121 dev->core_rev = core->id.rev;
122
123 return dev;
124}
125#endif /* CONFIG_B43_BCMA */
126
127/* SSB */
128#ifdef CONFIG_B43_SSB
129static int b43_bus_ssb_bus_may_powerdown(struct b43_bus_dev *dev)
130{
131 return ssb_bus_may_powerdown(dev->sdev->bus);
132}
133static int b43_bus_ssb_bus_powerup(struct b43_bus_dev *dev,
134 bool dynamic_pctl)
135{
136 return ssb_bus_powerup(dev->sdev->bus, dynamic_pctl);
137}
138static int b43_bus_ssb_device_is_enabled(struct b43_bus_dev *dev)
139{
140 return ssb_device_is_enabled(dev->sdev);
141}
142static void b43_bus_ssb_device_enable(struct b43_bus_dev *dev,
143 u32 core_specific_flags)
144{
145 ssb_device_enable(dev->sdev, core_specific_flags);
146}
147static void b43_bus_ssb_device_disable(struct b43_bus_dev *dev,
148 u32 core_specific_flags)
149{
150 ssb_device_disable(dev->sdev, core_specific_flags);
151}
152
153static u16 b43_bus_ssb_read16(struct b43_bus_dev *dev, u16 offset)
154{
155 return ssb_read16(dev->sdev, offset);
156}
157static u32 b43_bus_ssb_read32(struct b43_bus_dev *dev, u16 offset)
158{
159 return ssb_read32(dev->sdev, offset);
160}
161static void b43_bus_ssb_write16(struct b43_bus_dev *dev, u16 offset, u16 value)
162{
163 ssb_write16(dev->sdev, offset, value);
164}
165static void b43_bus_ssb_write32(struct b43_bus_dev *dev, u16 offset, u32 value)
166{
167 ssb_write32(dev->sdev, offset, value);
168}
169static void b43_bus_ssb_block_read(struct b43_bus_dev *dev, void *buffer,
170 size_t count, u16 offset, u8 reg_width)
171{
172 ssb_block_read(dev->sdev, buffer, count, offset, reg_width);
173}
174static
175void b43_bus_ssb_block_write(struct b43_bus_dev *dev, const void *buffer,
176 size_t count, u16 offset, u8 reg_width)
177{
178 ssb_block_write(dev->sdev, buffer, count, offset, reg_width);
179}
180
181struct b43_bus_dev *b43_bus_dev_ssb_init(struct ssb_device *sdev)
182{
183 struct b43_bus_dev *dev;
184
185 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
186 if (!dev)
187 return NULL;
188
189 dev->bus_type = B43_BUS_SSB;
190 dev->sdev = sdev;
191
192 dev->bus_may_powerdown = b43_bus_ssb_bus_may_powerdown;
193 dev->bus_powerup = b43_bus_ssb_bus_powerup;
194 dev->device_is_enabled = b43_bus_ssb_device_is_enabled;
195 dev->device_enable = b43_bus_ssb_device_enable;
196 dev->device_disable = b43_bus_ssb_device_disable;
197
198 dev->read16 = b43_bus_ssb_read16;
199 dev->read32 = b43_bus_ssb_read32;
200 dev->write16 = b43_bus_ssb_write16;
201 dev->write32 = b43_bus_ssb_write32;
202 dev->block_read = b43_bus_ssb_block_read;
203 dev->block_write = b43_bus_ssb_block_write;
204
205 dev->dev = sdev->dev;
206 dev->dma_dev = sdev->dma_dev;
207 dev->irq = sdev->irq;
208
209 dev->board_vendor = sdev->bus->boardinfo.vendor;
210 dev->board_type = sdev->bus->boardinfo.type;
211 dev->board_rev = sdev->bus->boardinfo.rev;
212
213 dev->chip_id = sdev->bus->chip_id;
214 dev->chip_rev = sdev->bus->chip_rev;
215 dev->chip_pkg = sdev->bus->chip_package;
216
217 dev->bus_sprom = &sdev->bus->sprom;
218
219 dev->core_id = sdev->id.coreid;
220 dev->core_rev = sdev->id.revision;
221
222 return dev;
223}
224#endif /* CONFIG_B43_SSB */
225
226void *b43_bus_get_wldev(struct b43_bus_dev *dev)
227{
228 switch (dev->bus_type) {
229#ifdef CONFIG_B43_BCMA
230 case B43_BUS_BCMA:
231 return bcma_get_drvdata(dev->bdev);
232#endif
233#ifdef CONFIG_B43_SSB
234 case B43_BUS_SSB:
235 return ssb_get_drvdata(dev->sdev);
236#endif
237 }
238 return NULL;
239}
240
241void b43_bus_set_wldev(struct b43_bus_dev *dev, void *wldev)
242{
243 switch (dev->bus_type) {
244#ifdef CONFIG_B43_BCMA
245 case B43_BUS_BCMA:
246 bcma_set_drvdata(dev->bdev, wldev);
247#endif
248#ifdef CONFIG_B43_SSB
249 case B43_BUS_SSB:
250 ssb_set_drvdata(dev->sdev, wldev);
251#endif
252 }
253}
diff --git a/drivers/net/wireless/b43/bus.h b/drivers/net/wireless/b43/bus.h
new file mode 100644
index 000000000000..184c95659279
--- /dev/null
+++ b/drivers/net/wireless/b43/bus.h
@@ -0,0 +1,70 @@
1#ifndef B43_BUS_H_
2#define B43_BUS_H_
3
4enum b43_bus_type {
5#ifdef CONFIG_B43_BCMA
6 B43_BUS_BCMA,
7#endif
8 B43_BUS_SSB,
9};
10
11struct b43_bus_dev {
12 enum b43_bus_type bus_type;
13 union {
14 struct bcma_device *bdev;
15 struct ssb_device *sdev;
16 };
17
18 int (*bus_may_powerdown)(struct b43_bus_dev *dev);
19 int (*bus_powerup)(struct b43_bus_dev *dev, bool dynamic_pctl);
20 int (*device_is_enabled)(struct b43_bus_dev *dev);
21 void (*device_enable)(struct b43_bus_dev *dev,
22 u32 core_specific_flags);
23 void (*device_disable)(struct b43_bus_dev *dev,
24 u32 core_specific_flags);
25
26 u16 (*read16)(struct b43_bus_dev *dev, u16 offset);
27 u32 (*read32)(struct b43_bus_dev *dev, u16 offset);
28 void (*write16)(struct b43_bus_dev *dev, u16 offset, u16 value);
29 void (*write32)(struct b43_bus_dev *dev, u16 offset, u32 value);
30 void (*block_read)(struct b43_bus_dev *dev, void *buffer,
31 size_t count, u16 offset, u8 reg_width);
32 void (*block_write)(struct b43_bus_dev *dev, const void *buffer,
33 size_t count, u16 offset, u8 reg_width);
34
35 struct device *dev;
36 struct device *dma_dev;
37 unsigned int irq;
38
39 u16 board_vendor;
40 u16 board_type;
41 u16 board_rev;
42
43 u16 chip_id;
44 u8 chip_rev;
45 u8 chip_pkg;
46
47 struct ssb_sprom *bus_sprom;
48
49 u16 core_id;
50 u8 core_rev;
51};
52
53static inline bool b43_bus_host_is_pcmcia(struct b43_bus_dev *dev)
54{
55 return (dev->bus_type == B43_BUS_SSB &&
56 dev->sdev->bus->bustype == SSB_BUSTYPE_PCMCIA);
57}
58static inline bool b43_bus_host_is_sdio(struct b43_bus_dev *dev)
59{
60 return (dev->bus_type == B43_BUS_SSB &&
61 dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO);
62}
63
64struct b43_bus_dev *b43_bus_dev_bcma_init(struct bcma_device *core);
65struct b43_bus_dev *b43_bus_dev_ssb_init(struct ssb_device *sdev);
66
67void *b43_bus_get_wldev(struct b43_bus_dev *dev);
68void b43_bus_set_wldev(struct b43_bus_dev *dev, void *data);
69
70#endif /* B43_BUS_H_ */
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
index 47d44bcff37d..0953ce1ac1b0 100644
--- a/drivers/net/wireless/b43/dma.c
+++ b/drivers/net/wireless/b43/dma.c
@@ -174,7 +174,7 @@ static void op64_fill_descriptor(struct b43_dmaring *ring,
174 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK); 174 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
175 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK) 175 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
176 >> SSB_DMA_TRANSLATION_SHIFT; 176 >> SSB_DMA_TRANSLATION_SHIFT;
177 addrhi |= (ring->dev->dma.translation << 1); 177 addrhi |= ring->dev->dma.translation;
178 if (slot == ring->nr_slots - 1) 178 if (slot == ring->nr_slots - 1)
179 ctl0 |= B43_DMA64_DCTL0_DTABLEEND; 179 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
180 if (start) 180 if (start)
@@ -333,10 +333,10 @@ static inline
333 dma_addr_t dmaaddr; 333 dma_addr_t dmaaddr;
334 334
335 if (tx) { 335 if (tx) {
336 dmaaddr = dma_map_single(ring->dev->sdev->dma_dev, 336 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
337 buf, len, DMA_TO_DEVICE); 337 buf, len, DMA_TO_DEVICE);
338 } else { 338 } else {
339 dmaaddr = dma_map_single(ring->dev->sdev->dma_dev, 339 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
340 buf, len, DMA_FROM_DEVICE); 340 buf, len, DMA_FROM_DEVICE);
341 } 341 }
342 342
@@ -348,10 +348,10 @@ static inline
348 dma_addr_t addr, size_t len, int tx) 348 dma_addr_t addr, size_t len, int tx)
349{ 349{
350 if (tx) { 350 if (tx) {
351 dma_unmap_single(ring->dev->sdev->dma_dev, 351 dma_unmap_single(ring->dev->dev->dma_dev,
352 addr, len, DMA_TO_DEVICE); 352 addr, len, DMA_TO_DEVICE);
353 } else { 353 } else {
354 dma_unmap_single(ring->dev->sdev->dma_dev, 354 dma_unmap_single(ring->dev->dev->dma_dev,
355 addr, len, DMA_FROM_DEVICE); 355 addr, len, DMA_FROM_DEVICE);
356 } 356 }
357} 357}
@@ -361,7 +361,7 @@ static inline
361 dma_addr_t addr, size_t len) 361 dma_addr_t addr, size_t len)
362{ 362{
363 B43_WARN_ON(ring->tx); 363 B43_WARN_ON(ring->tx);
364 dma_sync_single_for_cpu(ring->dev->sdev->dma_dev, 364 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
365 addr, len, DMA_FROM_DEVICE); 365 addr, len, DMA_FROM_DEVICE);
366} 366}
367 367
@@ -370,7 +370,7 @@ static inline
370 dma_addr_t addr, size_t len) 370 dma_addr_t addr, size_t len)
371{ 371{
372 B43_WARN_ON(ring->tx); 372 B43_WARN_ON(ring->tx);
373 dma_sync_single_for_device(ring->dev->sdev->dma_dev, 373 dma_sync_single_for_device(ring->dev->dev->dma_dev,
374 addr, len, DMA_FROM_DEVICE); 374 addr, len, DMA_FROM_DEVICE);
375} 375}
376 376
@@ -401,7 +401,7 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
401 */ 401 */
402 if (ring->type == B43_DMA_64BIT) 402 if (ring->type == B43_DMA_64BIT)
403 flags |= GFP_DMA; 403 flags |= GFP_DMA;
404 ring->descbase = dma_alloc_coherent(ring->dev->sdev->dma_dev, 404 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
405 B43_DMA_RINGMEMSIZE, 405 B43_DMA_RINGMEMSIZE,
406 &(ring->dmabase), flags); 406 &(ring->dmabase), flags);
407 if (!ring->descbase) { 407 if (!ring->descbase) {
@@ -415,7 +415,7 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
415 415
416static void free_ringmemory(struct b43_dmaring *ring) 416static void free_ringmemory(struct b43_dmaring *ring)
417{ 417{
418 dma_free_coherent(ring->dev->sdev->dma_dev, B43_DMA_RINGMEMSIZE, 418 dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
419 ring->descbase, ring->dmabase); 419 ring->descbase, ring->dmabase);
420} 420}
421 421
@@ -523,7 +523,7 @@ static bool b43_dma_mapping_error(struct b43_dmaring *ring,
523 dma_addr_t addr, 523 dma_addr_t addr,
524 size_t buffersize, bool dma_to_device) 524 size_t buffersize, bool dma_to_device)
525{ 525{
526 if (unlikely(dma_mapping_error(ring->dev->sdev->dma_dev, addr))) 526 if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
527 return 1; 527 return 1;
528 528
529 switch (ring->type) { 529 switch (ring->type) {
@@ -659,6 +659,7 @@ static int dmacontroller_setup(struct b43_dmaring *ring)
659 u32 value; 659 u32 value;
660 u32 addrext; 660 u32 addrext;
661 u32 trans = ring->dev->dma.translation; 661 u32 trans = ring->dev->dma.translation;
662 bool parity = ring->dev->dma.parity;
662 663
663 if (ring->tx) { 664 if (ring->tx) {
664 if (ring->type == B43_DMA_64BIT) { 665 if (ring->type == B43_DMA_64BIT) {
@@ -669,13 +670,15 @@ static int dmacontroller_setup(struct b43_dmaring *ring)
669 value = B43_DMA64_TXENABLE; 670 value = B43_DMA64_TXENABLE;
670 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT) 671 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
671 & B43_DMA64_TXADDREXT_MASK; 672 & B43_DMA64_TXADDREXT_MASK;
673 if (!parity)
674 value |= B43_DMA64_TXPARITYDISABLE;
672 b43_dma_write(ring, B43_DMA64_TXCTL, value); 675 b43_dma_write(ring, B43_DMA64_TXCTL, value);
673 b43_dma_write(ring, B43_DMA64_TXRINGLO, 676 b43_dma_write(ring, B43_DMA64_TXRINGLO,
674 (ringbase & 0xFFFFFFFF)); 677 (ringbase & 0xFFFFFFFF));
675 b43_dma_write(ring, B43_DMA64_TXRINGHI, 678 b43_dma_write(ring, B43_DMA64_TXRINGHI,
676 ((ringbase >> 32) & 679 ((ringbase >> 32) &
677 ~SSB_DMA_TRANSLATION_MASK) 680 ~SSB_DMA_TRANSLATION_MASK)
678 | (trans << 1)); 681 | trans);
679 } else { 682 } else {
680 u32 ringbase = (u32) (ring->dmabase); 683 u32 ringbase = (u32) (ring->dmabase);
681 684
@@ -684,6 +687,8 @@ static int dmacontroller_setup(struct b43_dmaring *ring)
684 value = B43_DMA32_TXENABLE; 687 value = B43_DMA32_TXENABLE;
685 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT) 688 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
686 & B43_DMA32_TXADDREXT_MASK; 689 & B43_DMA32_TXADDREXT_MASK;
690 if (!parity)
691 value |= B43_DMA32_TXPARITYDISABLE;
687 b43_dma_write(ring, B43_DMA32_TXCTL, value); 692 b43_dma_write(ring, B43_DMA32_TXCTL, value);
688 b43_dma_write(ring, B43_DMA32_TXRING, 693 b43_dma_write(ring, B43_DMA32_TXRING,
689 (ringbase & ~SSB_DMA_TRANSLATION_MASK) 694 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
@@ -702,13 +707,15 @@ static int dmacontroller_setup(struct b43_dmaring *ring)
702 value |= B43_DMA64_RXENABLE; 707 value |= B43_DMA64_RXENABLE;
703 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT) 708 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
704 & B43_DMA64_RXADDREXT_MASK; 709 & B43_DMA64_RXADDREXT_MASK;
710 if (!parity)
711 value |= B43_DMA64_RXPARITYDISABLE;
705 b43_dma_write(ring, B43_DMA64_RXCTL, value); 712 b43_dma_write(ring, B43_DMA64_RXCTL, value);
706 b43_dma_write(ring, B43_DMA64_RXRINGLO, 713 b43_dma_write(ring, B43_DMA64_RXRINGLO,
707 (ringbase & 0xFFFFFFFF)); 714 (ringbase & 0xFFFFFFFF));
708 b43_dma_write(ring, B43_DMA64_RXRINGHI, 715 b43_dma_write(ring, B43_DMA64_RXRINGHI,
709 ((ringbase >> 32) & 716 ((ringbase >> 32) &
710 ~SSB_DMA_TRANSLATION_MASK) 717 ~SSB_DMA_TRANSLATION_MASK)
711 | (trans << 1)); 718 | trans);
712 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots * 719 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
713 sizeof(struct b43_dmadesc64)); 720 sizeof(struct b43_dmadesc64));
714 } else { 721 } else {
@@ -720,6 +727,8 @@ static int dmacontroller_setup(struct b43_dmaring *ring)
720 value |= B43_DMA32_RXENABLE; 727 value |= B43_DMA32_RXENABLE;
721 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT) 728 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
722 & B43_DMA32_RXADDREXT_MASK; 729 & B43_DMA32_RXADDREXT_MASK;
730 if (!parity)
731 value |= B43_DMA32_RXPARITYDISABLE;
723 b43_dma_write(ring, B43_DMA32_RXCTL, value); 732 b43_dma_write(ring, B43_DMA32_RXCTL, value);
724 b43_dma_write(ring, B43_DMA32_RXRING, 733 b43_dma_write(ring, B43_DMA32_RXRING,
725 (ringbase & ~SSB_DMA_TRANSLATION_MASK) 734 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
@@ -757,14 +766,14 @@ static void dmacontroller_cleanup(struct b43_dmaring *ring)
757 766
758static void free_all_descbuffers(struct b43_dmaring *ring) 767static void free_all_descbuffers(struct b43_dmaring *ring)
759{ 768{
760 struct b43_dmadesc_generic *desc;
761 struct b43_dmadesc_meta *meta; 769 struct b43_dmadesc_meta *meta;
762 int i; 770 int i;
763 771
764 if (!ring->used_slots) 772 if (!ring->used_slots)
765 return; 773 return;
766 for (i = 0; i < ring->nr_slots; i++) { 774 for (i = 0; i < ring->nr_slots; i++) {
767 desc = ring->ops->idx2desc(ring, i, &meta); 775 /* get meta - ignore returned value */
776 ring->ops->idx2desc(ring, i, &meta);
768 777
769 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) { 778 if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) {
770 B43_WARN_ON(!ring->tx); 779 B43_WARN_ON(!ring->tx);
@@ -869,7 +878,7 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
869 goto err_kfree_meta; 878 goto err_kfree_meta;
870 879
871 /* test for ability to dma to txhdr_cache */ 880 /* test for ability to dma to txhdr_cache */
872 dma_test = dma_map_single(dev->sdev->dma_dev, 881 dma_test = dma_map_single(dev->dev->dma_dev,
873 ring->txhdr_cache, 882 ring->txhdr_cache,
874 b43_txhdr_size(dev), 883 b43_txhdr_size(dev),
875 DMA_TO_DEVICE); 884 DMA_TO_DEVICE);
@@ -884,7 +893,7 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
884 if (!ring->txhdr_cache) 893 if (!ring->txhdr_cache)
885 goto err_kfree_meta; 894 goto err_kfree_meta;
886 895
887 dma_test = dma_map_single(dev->sdev->dma_dev, 896 dma_test = dma_map_single(dev->dev->dma_dev,
888 ring->txhdr_cache, 897 ring->txhdr_cache,
889 b43_txhdr_size(dev), 898 b43_txhdr_size(dev),
890 DMA_TO_DEVICE); 899 DMA_TO_DEVICE);
@@ -898,7 +907,7 @@ struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
898 } 907 }
899 } 908 }
900 909
901 dma_unmap_single(dev->sdev->dma_dev, 910 dma_unmap_single(dev->dev->dma_dev,
902 dma_test, b43_txhdr_size(dev), 911 dma_test, b43_txhdr_size(dev),
903 DMA_TO_DEVICE); 912 DMA_TO_DEVICE);
904 } 913 }
@@ -1013,9 +1022,9 @@ static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
1013 /* Try to set the DMA mask. If it fails, try falling back to a 1022 /* Try to set the DMA mask. If it fails, try falling back to a
1014 * lower mask, as we can always also support a lower one. */ 1023 * lower mask, as we can always also support a lower one. */
1015 while (1) { 1024 while (1) {
1016 err = dma_set_mask(dev->sdev->dma_dev, mask); 1025 err = dma_set_mask(dev->dev->dma_dev, mask);
1017 if (!err) { 1026 if (!err) {
1018 err = dma_set_coherent_mask(dev->sdev->dma_dev, mask); 1027 err = dma_set_coherent_mask(dev->dev->dma_dev, mask);
1019 if (!err) 1028 if (!err)
1020 break; 1029 break;
1021 } 1030 }
@@ -1055,7 +1064,26 @@ int b43_dma_init(struct b43_wldev *dev)
1055 err = b43_dma_set_mask(dev, dmamask); 1064 err = b43_dma_set_mask(dev, dmamask);
1056 if (err) 1065 if (err)
1057 return err; 1066 return err;
1058 dma->translation = ssb_dma_translation(dev->sdev); 1067
1068 switch (dev->dev->bus_type) {
1069#ifdef CONFIG_B43_BCMA
1070 case B43_BUS_BCMA:
1071 dma->translation = bcma_core_dma_translation(dev->dev->bdev);
1072 break;
1073#endif
1074#ifdef CONFIG_B43_SSB
1075 case B43_BUS_SSB:
1076 dma->translation = ssb_dma_translation(dev->dev->sdev);
1077 break;
1078#endif
1079 }
1080
1081 dma->parity = true;
1082#ifdef CONFIG_B43_BCMA
1083 /* TODO: find out which SSB devices need disabling parity */
1084 if (dev->dev->bus_type == B43_BUS_BCMA)
1085 dma->parity = false;
1086#endif
1059 1087
1060 err = -ENOMEM; 1088 err = -ENOMEM;
1061 /* setup TX DMA channels. */ 1089 /* setup TX DMA channels. */
@@ -1085,7 +1113,7 @@ int b43_dma_init(struct b43_wldev *dev)
1085 goto err_destroy_mcast; 1113 goto err_destroy_mcast;
1086 1114
1087 /* No support for the TX status DMA ring. */ 1115 /* No support for the TX status DMA ring. */
1088 B43_WARN_ON(dev->sdev->id.revision < 5); 1116 B43_WARN_ON(dev->dev->core_rev < 5);
1089 1117
1090 b43dbg(dev->wl, "%u-bit DMA initialized\n", 1118 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1091 (unsigned int)type); 1119 (unsigned int)type);
@@ -1388,7 +1416,6 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
1388{ 1416{
1389 const struct b43_dma_ops *ops; 1417 const struct b43_dma_ops *ops;
1390 struct b43_dmaring *ring; 1418 struct b43_dmaring *ring;
1391 struct b43_dmadesc_generic *desc;
1392 struct b43_dmadesc_meta *meta; 1419 struct b43_dmadesc_meta *meta;
1393 int slot, firstused; 1420 int slot, firstused;
1394 bool frame_succeed; 1421 bool frame_succeed;
@@ -1416,7 +1443,8 @@ void b43_dma_handle_txstatus(struct b43_wldev *dev,
1416 ops = ring->ops; 1443 ops = ring->ops;
1417 while (1) { 1444 while (1) {
1418 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots); 1445 B43_WARN_ON(slot < 0 || slot >= ring->nr_slots);
1419 desc = ops->idx2desc(ring, slot, &meta); 1446 /* get meta - ignore returned value */
1447 ops->idx2desc(ring, slot, &meta);
1420 1448
1421 if (b43_dma_ptr_is_poisoned(meta->skb)) { 1449 if (b43_dma_ptr_is_poisoned(meta->skb)) {
1422 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) " 1450 b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) "
@@ -1600,6 +1628,7 @@ void b43_dma_rx(struct b43_dmaring *ring)
1600 dma_rx(ring, &slot); 1628 dma_rx(ring, &slot);
1601 update_max_used_slots(ring, ++used_slots); 1629 update_max_used_slots(ring, ++used_slots);
1602 } 1630 }
1631 wmb();
1603 ops->set_current_rxslot(ring, slot); 1632 ops->set_current_rxslot(ring, slot);
1604 ring->current_slot = slot; 1633 ring->current_slot = slot;
1605} 1634}
diff --git a/drivers/net/wireless/b43/dma.h b/drivers/net/wireless/b43/dma.h
index e8a80a1251bf..cdf87094efe8 100644
--- a/drivers/net/wireless/b43/dma.h
+++ b/drivers/net/wireless/b43/dma.h
@@ -20,6 +20,7 @@
20#define B43_DMA32_TXSUSPEND 0x00000002 20#define B43_DMA32_TXSUSPEND 0x00000002
21#define B43_DMA32_TXLOOPBACK 0x00000004 21#define B43_DMA32_TXLOOPBACK 0x00000004
22#define B43_DMA32_TXFLUSH 0x00000010 22#define B43_DMA32_TXFLUSH 0x00000010
23#define B43_DMA32_TXPARITYDISABLE 0x00000800
23#define B43_DMA32_TXADDREXT_MASK 0x00030000 24#define B43_DMA32_TXADDREXT_MASK 0x00030000
24#define B43_DMA32_TXADDREXT_SHIFT 16 25#define B43_DMA32_TXADDREXT_SHIFT 16
25#define B43_DMA32_TXRING 0x04 26#define B43_DMA32_TXRING 0x04
@@ -44,6 +45,7 @@
44#define B43_DMA32_RXFROFF_MASK 0x000000FE 45#define B43_DMA32_RXFROFF_MASK 0x000000FE
45#define B43_DMA32_RXFROFF_SHIFT 1 46#define B43_DMA32_RXFROFF_SHIFT 1
46#define B43_DMA32_RXDIRECTFIFO 0x00000100 47#define B43_DMA32_RXDIRECTFIFO 0x00000100
48#define B43_DMA32_RXPARITYDISABLE 0x00000800
47#define B43_DMA32_RXADDREXT_MASK 0x00030000 49#define B43_DMA32_RXADDREXT_MASK 0x00030000
48#define B43_DMA32_RXADDREXT_SHIFT 16 50#define B43_DMA32_RXADDREXT_SHIFT 16
49#define B43_DMA32_RXRING 0x14 51#define B43_DMA32_RXRING 0x14
@@ -84,6 +86,7 @@ struct b43_dmadesc32 {
84#define B43_DMA64_TXSUSPEND 0x00000002 86#define B43_DMA64_TXSUSPEND 0x00000002
85#define B43_DMA64_TXLOOPBACK 0x00000004 87#define B43_DMA64_TXLOOPBACK 0x00000004
86#define B43_DMA64_TXFLUSH 0x00000010 88#define B43_DMA64_TXFLUSH 0x00000010
89#define B43_DMA64_TXPARITYDISABLE 0x00000800
87#define B43_DMA64_TXADDREXT_MASK 0x00030000 90#define B43_DMA64_TXADDREXT_MASK 0x00030000
88#define B43_DMA64_TXADDREXT_SHIFT 16 91#define B43_DMA64_TXADDREXT_SHIFT 16
89#define B43_DMA64_TXINDEX 0x04 92#define B43_DMA64_TXINDEX 0x04
@@ -111,6 +114,7 @@ struct b43_dmadesc32 {
111#define B43_DMA64_RXFROFF_MASK 0x000000FE 114#define B43_DMA64_RXFROFF_MASK 0x000000FE
112#define B43_DMA64_RXFROFF_SHIFT 1 115#define B43_DMA64_RXFROFF_SHIFT 1
113#define B43_DMA64_RXDIRECTFIFO 0x00000100 116#define B43_DMA64_RXDIRECTFIFO 0x00000100
117#define B43_DMA64_RXPARITYDISABLE 0x00000800
114#define B43_DMA64_RXADDREXT_MASK 0x00030000 118#define B43_DMA64_RXADDREXT_MASK 0x00030000
115#define B43_DMA64_RXADDREXT_SHIFT 16 119#define B43_DMA64_RXADDREXT_SHIFT 16
116#define B43_DMA64_RXINDEX 0x24 120#define B43_DMA64_RXINDEX 0x24
diff --git a/drivers/net/wireless/b43/leds.c b/drivers/net/wireless/b43/leds.c
index 0cafafe368af..b56ed41fc1bd 100644
--- a/drivers/net/wireless/b43/leds.c
+++ b/drivers/net/wireless/b43/leds.c
@@ -138,7 +138,7 @@ static int b43_register_led(struct b43_wldev *dev, struct b43_led *led,
138 led->led_dev.default_trigger = default_trigger; 138 led->led_dev.default_trigger = default_trigger;
139 led->led_dev.brightness_set = b43_led_brightness_set; 139 led->led_dev.brightness_set = b43_led_brightness_set;
140 140
141 err = led_classdev_register(dev->sdev->dev, &led->led_dev); 141 err = led_classdev_register(dev->dev->dev, &led->led_dev);
142 if (err) { 142 if (err) {
143 b43warn(dev->wl, "LEDs: Failed to register %s\n", name); 143 b43warn(dev->wl, "LEDs: Failed to register %s\n", name);
144 led->wl = NULL; 144 led->wl = NULL;
@@ -215,13 +215,12 @@ static void b43_led_get_sprominfo(struct b43_wldev *dev,
215 enum b43_led_behaviour *behaviour, 215 enum b43_led_behaviour *behaviour,
216 bool *activelow) 216 bool *activelow)
217{ 217{
218 struct ssb_bus *bus = dev->sdev->bus;
219 u8 sprom[4]; 218 u8 sprom[4];
220 219
221 sprom[0] = bus->sprom.gpio0; 220 sprom[0] = dev->dev->bus_sprom->gpio0;
222 sprom[1] = bus->sprom.gpio1; 221 sprom[1] = dev->dev->bus_sprom->gpio1;
223 sprom[2] = bus->sprom.gpio2; 222 sprom[2] = dev->dev->bus_sprom->gpio2;
224 sprom[3] = bus->sprom.gpio3; 223 sprom[3] = dev->dev->bus_sprom->gpio3;
225 224
226 if (sprom[led_index] == 0xFF) { 225 if (sprom[led_index] == 0xFF) {
227 /* There is no LED information in the SPROM 226 /* There is no LED information in the SPROM
@@ -231,12 +230,12 @@ static void b43_led_get_sprominfo(struct b43_wldev *dev,
231 case 0: 230 case 0:
232 *behaviour = B43_LED_ACTIVITY; 231 *behaviour = B43_LED_ACTIVITY;
233 *activelow = 1; 232 *activelow = 1;
234 if (bus->boardinfo.vendor == PCI_VENDOR_ID_COMPAQ) 233 if (dev->dev->board_vendor == PCI_VENDOR_ID_COMPAQ)
235 *behaviour = B43_LED_RADIO_ALL; 234 *behaviour = B43_LED_RADIO_ALL;
236 break; 235 break;
237 case 1: 236 case 1:
238 *behaviour = B43_LED_RADIO_B; 237 *behaviour = B43_LED_RADIO_B;
239 if (bus->boardinfo.vendor == PCI_VENDOR_ID_ASUSTEK) 238 if (dev->dev->board_vendor == PCI_VENDOR_ID_ASUSTEK)
240 *behaviour = B43_LED_ASSOC; 239 *behaviour = B43_LED_ASSOC;
241 break; 240 break;
242 case 2: 241 case 2:
diff --git a/drivers/net/wireless/b43/lo.c b/drivers/net/wireless/b43/lo.c
index 2ef7d4b38540..a3dc8bb8ca95 100644
--- a/drivers/net/wireless/b43/lo.c
+++ b/drivers/net/wireless/b43/lo.c
@@ -98,7 +98,7 @@ static u16 lo_measure_feedthrough(struct b43_wldev *dev,
98 rfover |= pga; 98 rfover |= pga;
99 rfover |= lna; 99 rfover |= lna;
100 rfover |= trsw_rx; 100 rfover |= trsw_rx;
101 if ((dev->sdev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) 101 if ((dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA)
102 && phy->rev > 6) 102 && phy->rev > 6)
103 rfover |= B43_PHY_RFOVERVAL_EXTLNA; 103 rfover |= B43_PHY_RFOVERVAL_EXTLNA;
104 104
@@ -301,14 +301,12 @@ static void lo_measure_gain_values(struct b43_wldev *dev,
301 max_rx_gain = 0; 301 max_rx_gain = 0;
302 302
303 if (has_loopback_gain(phy)) { 303 if (has_loopback_gain(phy)) {
304 int trsw_rx = 0;
305 int trsw_rx_gain; 304 int trsw_rx_gain;
306 305
307 if (use_trsw_rx) { 306 if (use_trsw_rx) {
308 trsw_rx_gain = gphy->trsw_rx_gain / 2; 307 trsw_rx_gain = gphy->trsw_rx_gain / 2;
309 if (max_rx_gain >= trsw_rx_gain) { 308 if (max_rx_gain >= trsw_rx_gain) {
310 trsw_rx_gain = max_rx_gain - trsw_rx_gain; 309 trsw_rx_gain = max_rx_gain - trsw_rx_gain;
311 trsw_rx = 0x20;
312 } 310 }
313 } else 311 } else
314 trsw_rx_gain = max_rx_gain; 312 trsw_rx_gain = max_rx_gain;
@@ -387,7 +385,7 @@ struct lo_g_saved_values {
387static void lo_measure_setup(struct b43_wldev *dev, 385static void lo_measure_setup(struct b43_wldev *dev,
388 struct lo_g_saved_values *sav) 386 struct lo_g_saved_values *sav)
389{ 387{
390 struct ssb_sprom *sprom = &dev->sdev->bus->sprom; 388 struct ssb_sprom *sprom = dev->dev->bus_sprom;
391 struct b43_phy *phy = &dev->phy; 389 struct b43_phy *phy = &dev->phy;
392 struct b43_phy_g *gphy = phy->g; 390 struct b43_phy_g *gphy = phy->g;
393 struct b43_txpower_lo_control *lo = gphy->lo_control; 391 struct b43_txpower_lo_control *lo = gphy->lo_control;
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index eb4159686985..73fbf0358f96 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -113,6 +113,17 @@ static int b43_modparam_pio = B43_PIO_DEFAULT;
113module_param_named(pio, b43_modparam_pio, int, 0644); 113module_param_named(pio, b43_modparam_pio, int, 0644);
114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO"); 114MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
115 115
116#ifdef CONFIG_B43_BCMA
117static const struct bcma_device_id b43_bcma_tbl[] = {
118 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
119 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
120 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
121 BCMA_CORETABLE_END
122};
123MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
124#endif
125
126#ifdef CONFIG_B43_SSB
116static const struct ssb_device_id b43_ssb_tbl[] = { 127static const struct ssb_device_id b43_ssb_tbl[] = {
117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), 128 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), 129 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
@@ -126,8 +137,8 @@ static const struct ssb_device_id b43_ssb_tbl[] = {
126 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16), 137 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
127 SSB_DEVTABLE_END 138 SSB_DEVTABLE_END
128}; 139};
129
130MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); 140MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
141#endif
131 142
132/* Channel and ratetables are shared for all devices. 143/* Channel and ratetables are shared for all devices.
133 * They can't be const, because ieee80211 puts some precalculated 144 * They can't be const, because ieee80211 puts some precalculated
@@ -548,7 +559,7 @@ void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
548{ 559{
549 u32 low, high; 560 u32 low, high;
550 561
551 B43_WARN_ON(dev->sdev->id.revision < 3); 562 B43_WARN_ON(dev->dev->core_rev < 3);
552 563
553 /* The hardware guarantees us an atomic read, if we 564 /* The hardware guarantees us an atomic read, if we
554 * read the low register first. */ 565 * read the low register first. */
@@ -586,7 +597,7 @@ static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
586{ 597{
587 u32 low, high; 598 u32 low, high;
588 599
589 B43_WARN_ON(dev->sdev->id.revision < 3); 600 B43_WARN_ON(dev->dev->core_rev < 3);
590 601
591 low = tsf; 602 low = tsf;
592 high = (tsf >> 32); 603 high = (tsf >> 32);
@@ -714,7 +725,7 @@ void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
714 b43_ram_write(dev, i * 4, buffer[i]); 725 b43_ram_write(dev, i * 4, buffer[i]);
715 726
716 b43_write16(dev, 0x0568, 0x0000); 727 b43_write16(dev, 0x0568, 0x0000);
717 if (dev->sdev->id.revision < 11) 728 if (dev->dev->core_rev < 11)
718 b43_write16(dev, 0x07C0, 0x0000); 729 b43_write16(dev, 0x07C0, 0x0000);
719 else 730 else
720 b43_write16(dev, 0x07C0, 0x0100); 731 b43_write16(dev, 0x07C0, 0x0100);
@@ -1132,7 +1143,7 @@ void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1132 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1143 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1133 /* Commit write */ 1144 /* Commit write */
1134 b43_read32(dev, B43_MMIO_MACCTL); 1145 b43_read32(dev, B43_MMIO_MACCTL);
1135 if (awake && dev->sdev->id.revision >= 5) { 1146 if (awake && dev->dev->core_rev >= 5) {
1136 /* Wait for the microcode to wake up. */ 1147 /* Wait for the microcode to wake up. */
1137 for (i = 0; i < 100; i++) { 1148 for (i = 0; i < 100; i++) {
1138 ucstat = b43_shm_read16(dev, B43_SHM_SHARED, 1149 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
@@ -1144,35 +1155,85 @@ void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1144 } 1155 }
1145} 1156}
1146 1157
1147static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, u32 flags) 1158#ifdef CONFIG_B43_BCMA
1159static void b43_bcma_phy_reset(struct b43_wldev *dev)
1160{
1161 u32 flags;
1162
1163 /* Put PHY into reset */
1164 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1165 flags |= B43_BCMA_IOCTL_PHY_RESET;
1166 flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
1167 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1168 udelay(2);
1169
1170 /* Take PHY out of reset */
1171 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1172 flags &= ~B43_BCMA_IOCTL_PHY_RESET;
1173 flags |= BCMA_IOCTL_FGC;
1174 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1175 udelay(1);
1176
1177 /* Do not force clock anymore */
1178 flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
1179 flags &= ~BCMA_IOCTL_FGC;
1180 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
1181 udelay(1);
1182}
1183
1184static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1185{
1186 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1187 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1188 b43_bcma_phy_reset(dev);
1189 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true);
1190}
1191#endif
1192
1193static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1148{ 1194{
1195 struct ssb_device *sdev = dev->dev->sdev;
1149 u32 tmslow; 1196 u32 tmslow;
1197 u32 flags = 0;
1150 1198
1199 if (gmode)
1200 flags |= B43_TMSLOW_GMODE;
1151 flags |= B43_TMSLOW_PHYCLKEN; 1201 flags |= B43_TMSLOW_PHYCLKEN;
1152 flags |= B43_TMSLOW_PHYRESET; 1202 flags |= B43_TMSLOW_PHYRESET;
1153 if (dev->phy.type == B43_PHYTYPE_N) 1203 if (dev->phy.type == B43_PHYTYPE_N)
1154 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */ 1204 flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
1155 ssb_device_enable(dev->sdev, flags); 1205 b43_device_enable(dev, flags);
1156 msleep(2); /* Wait for the PLL to turn on. */ 1206 msleep(2); /* Wait for the PLL to turn on. */
1157 1207
1158 /* Now take the PHY out of Reset again */ 1208 /* Now take the PHY out of Reset again */
1159 tmslow = ssb_read32(dev->sdev, SSB_TMSLOW); 1209 tmslow = ssb_read32(sdev, SSB_TMSLOW);
1160 tmslow |= SSB_TMSLOW_FGC; 1210 tmslow |= SSB_TMSLOW_FGC;
1161 tmslow &= ~B43_TMSLOW_PHYRESET; 1211 tmslow &= ~B43_TMSLOW_PHYRESET;
1162 ssb_write32(dev->sdev, SSB_TMSLOW, tmslow); 1212 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1163 ssb_read32(dev->sdev, SSB_TMSLOW); /* flush */ 1213 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1164 msleep(1); 1214 msleep(1);
1165 tmslow &= ~SSB_TMSLOW_FGC; 1215 tmslow &= ~SSB_TMSLOW_FGC;
1166 ssb_write32(dev->sdev, SSB_TMSLOW, tmslow); 1216 ssb_write32(sdev, SSB_TMSLOW, tmslow);
1167 ssb_read32(dev->sdev, SSB_TMSLOW); /* flush */ 1217 ssb_read32(sdev, SSB_TMSLOW); /* flush */
1168 msleep(1); 1218 msleep(1);
1169} 1219}
1170 1220
1171void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) 1221void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1172{ 1222{
1173 u32 macctl; 1223 u32 macctl;
1174 1224
1175 b43_ssb_wireless_core_reset(dev, flags); 1225 switch (dev->dev->bus_type) {
1226#ifdef CONFIG_B43_BCMA
1227 case B43_BUS_BCMA:
1228 b43_bcma_wireless_core_reset(dev, gmode);
1229 break;
1230#endif
1231#ifdef CONFIG_B43_SSB
1232 case B43_BUS_SSB:
1233 b43_ssb_wireless_core_reset(dev, gmode);
1234 break;
1235#endif
1236 }
1176 1237
1177 /* Turn Analog ON, but only if we already know the PHY-type. 1238 /* Turn Analog ON, but only if we already know the PHY-type.
1178 * This protects against very early setup where we don't know the 1239 * This protects against very early setup where we don't know the
@@ -1183,7 +1244,7 @@ void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1183 1244
1184 macctl = b43_read32(dev, B43_MMIO_MACCTL); 1245 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1185 macctl &= ~B43_MACCTL_GMODE; 1246 macctl &= ~B43_MACCTL_GMODE;
1186 if (flags & B43_TMSLOW_GMODE) 1247 if (gmode)
1187 macctl |= B43_MACCTL_GMODE; 1248 macctl |= B43_MACCTL_GMODE;
1188 macctl |= B43_MACCTL_IHR_ENABLED; 1249 macctl |= B43_MACCTL_IHR_ENABLED;
1189 b43_write32(dev, B43_MMIO_MACCTL, macctl); 1250 b43_write32(dev, B43_MMIO_MACCTL, macctl);
@@ -1221,7 +1282,7 @@ static void drain_txstatus_queue(struct b43_wldev *dev)
1221{ 1282{
1222 u32 dummy; 1283 u32 dummy;
1223 1284
1224 if (dev->sdev->id.revision < 5) 1285 if (dev->dev->core_rev < 5)
1225 return; 1286 return;
1226 /* Read all entries from the microcode TXstatus FIFO 1287 /* Read all entries from the microcode TXstatus FIFO
1227 * and throw them away. 1288 * and throw them away.
@@ -1427,9 +1488,9 @@ u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1427 1488
1428 /* Get the mask of available antennas. */ 1489 /* Get the mask of available antennas. */
1429 if (dev->phy.gmode) 1490 if (dev->phy.gmode)
1430 antenna_mask = dev->sdev->bus->sprom.ant_available_bg; 1491 antenna_mask = dev->dev->bus_sprom->ant_available_bg;
1431 else 1492 else
1432 antenna_mask = dev->sdev->bus->sprom.ant_available_a; 1493 antenna_mask = dev->dev->bus_sprom->ant_available_a;
1433 1494
1434 if (!(antenna_mask & (1 << (antenna_nr - 1)))) { 1495 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1435 /* This antenna is not available. Fall back to default. */ 1496 /* This antenna is not available. Fall back to default. */
@@ -1644,7 +1705,7 @@ static void b43_beacon_update_trigger_work(struct work_struct *work)
1644 mutex_lock(&wl->mutex); 1705 mutex_lock(&wl->mutex);
1645 dev = wl->current_dev; 1706 dev = wl->current_dev;
1646 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { 1707 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1647 if (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) { 1708 if (b43_bus_host_is_sdio(dev->dev)) {
1648 /* wl->mutex is enough. */ 1709 /* wl->mutex is enough. */
1649 b43_do_beacon_update_trigger_work(dev); 1710 b43_do_beacon_update_trigger_work(dev);
1650 mmiowb(); 1711 mmiowb();
@@ -1689,7 +1750,7 @@ static void b43_update_templates(struct b43_wl *wl)
1689static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) 1750static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1690{ 1751{
1691 b43_time_lock(dev); 1752 b43_time_lock(dev);
1692 if (dev->sdev->id.revision >= 3) { 1753 if (dev->dev->core_rev >= 3) {
1693 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); 1754 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1694 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); 1755 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1695 } else { 1756 } else {
@@ -1923,7 +1984,7 @@ static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1923 return IRQ_NONE; 1984 return IRQ_NONE;
1924 reason &= dev->irq_mask; 1985 reason &= dev->irq_mask;
1925 if (!reason) 1986 if (!reason)
1926 return IRQ_HANDLED; 1987 return IRQ_NONE;
1927 1988
1928 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) 1989 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1929 & 0x0001DC00; 1990 & 0x0001DC00;
@@ -2063,7 +2124,7 @@ int b43_do_request_fw(struct b43_request_fw_context *ctx,
2063 B43_WARN_ON(1); 2124 B43_WARN_ON(1);
2064 return -ENOSYS; 2125 return -ENOSYS;
2065 } 2126 }
2066 err = request_firmware(&blob, ctx->fwname, ctx->dev->sdev->dev); 2127 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2067 if (err == -ENOENT) { 2128 if (err == -ENOENT) {
2068 snprintf(ctx->errors[ctx->req_type], 2129 snprintf(ctx->errors[ctx->req_type],
2069 sizeof(ctx->errors[ctx->req_type]), 2130 sizeof(ctx->errors[ctx->req_type]),
@@ -2113,26 +2174,48 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2113{ 2174{
2114 struct b43_wldev *dev = ctx->dev; 2175 struct b43_wldev *dev = ctx->dev;
2115 struct b43_firmware *fw = &ctx->dev->fw; 2176 struct b43_firmware *fw = &ctx->dev->fw;
2116 const u8 rev = ctx->dev->sdev->id.revision; 2177 const u8 rev = ctx->dev->dev->core_rev;
2117 const char *filename; 2178 const char *filename;
2118 u32 tmshigh; 2179 u32 tmshigh;
2119 int err; 2180 int err;
2120 2181
2182 /* Files for HT and LCN were found by trying one by one */
2183
2121 /* Get microcode */ 2184 /* Get microcode */
2122 if ((rev >= 5) && (rev <= 10)) 2185 if ((rev >= 5) && (rev <= 10)) {
2123 filename = "ucode5"; 2186 filename = "ucode5";
2124 else if ((rev >= 11) && (rev <= 12)) 2187 } else if ((rev >= 11) && (rev <= 12)) {
2125 filename = "ucode11"; 2188 filename = "ucode11";
2126 else if (rev == 13) 2189 } else if (rev == 13) {
2127 filename = "ucode13"; 2190 filename = "ucode13";
2128 else if (rev == 14) 2191 } else if (rev == 14) {
2129 filename = "ucode14"; 2192 filename = "ucode14";
2130 else if (rev == 15) 2193 } else if (rev == 15) {
2131 filename = "ucode15"; 2194 filename = "ucode15";
2132 else if ((rev >= 16) && (rev <= 20)) 2195 } else {
2133 filename = "ucode16_mimo"; 2196 switch (dev->phy.type) {
2134 else 2197 case B43_PHYTYPE_N:
2135 goto err_no_ucode; 2198 if (rev >= 16)
2199 filename = "ucode16_mimo";
2200 else
2201 goto err_no_ucode;
2202 break;
2203 case B43_PHYTYPE_HT:
2204 if (rev == 29)
2205 filename = "ucode29_mimo";
2206 else
2207 goto err_no_ucode;
2208 break;
2209 case B43_PHYTYPE_LCN:
2210 if (rev == 24)
2211 filename = "ucode24_mimo";
2212 else
2213 goto err_no_ucode;
2214 break;
2215 default:
2216 goto err_no_ucode;
2217 }
2218 }
2136 err = b43_do_request_fw(ctx, filename, &fw->ucode); 2219 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2137 if (err) 2220 if (err)
2138 goto err_load; 2221 goto err_load;
@@ -2157,7 +2240,7 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2157 switch (dev->phy.type) { 2240 switch (dev->phy.type) {
2158 case B43_PHYTYPE_A: 2241 case B43_PHYTYPE_A:
2159 if ((rev >= 5) && (rev <= 10)) { 2242 if ((rev >= 5) && (rev <= 10)) {
2160 tmshigh = ssb_read32(dev->sdev, SSB_TMSHIGH); 2243 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2161 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2244 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2162 filename = "a0g1initvals5"; 2245 filename = "a0g1initvals5";
2163 else 2246 else
@@ -2191,6 +2274,18 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2191 else 2274 else
2192 goto err_no_initvals; 2275 goto err_no_initvals;
2193 break; 2276 break;
2277 case B43_PHYTYPE_HT:
2278 if (rev == 29)
2279 filename = "ht0initvals29";
2280 else
2281 goto err_no_initvals;
2282 break;
2283 case B43_PHYTYPE_LCN:
2284 if (rev == 24)
2285 filename = "lcn0initvals24";
2286 else
2287 goto err_no_initvals;
2288 break;
2194 default: 2289 default:
2195 goto err_no_initvals; 2290 goto err_no_initvals;
2196 } 2291 }
@@ -2202,7 +2297,7 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2202 switch (dev->phy.type) { 2297 switch (dev->phy.type) {
2203 case B43_PHYTYPE_A: 2298 case B43_PHYTYPE_A:
2204 if ((rev >= 5) && (rev <= 10)) { 2299 if ((rev >= 5) && (rev <= 10)) {
2205 tmshigh = ssb_read32(dev->sdev, SSB_TMSHIGH); 2300 tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
2206 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) 2301 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2207 filename = "a0g1bsinitvals5"; 2302 filename = "a0g1bsinitvals5";
2208 else 2303 else
@@ -2238,6 +2333,18 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2238 else 2333 else
2239 goto err_no_initvals; 2334 goto err_no_initvals;
2240 break; 2335 break;
2336 case B43_PHYTYPE_HT:
2337 if (rev == 29)
2338 filename = "ht0bsinitvals29";
2339 else
2340 goto err_no_initvals;
2341 break;
2342 case B43_PHYTYPE_LCN:
2343 if (rev == 24)
2344 filename = "lcn0bsinitvals24";
2345 else
2346 goto err_no_initvals;
2347 break;
2241 default: 2348 default:
2242 goto err_no_initvals; 2349 goto err_no_initvals;
2243 } 2350 }
@@ -2448,7 +2555,7 @@ static int b43_upload_microcode(struct b43_wldev *dev)
2448 2555
2449 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u", 2556 snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
2450 dev->fw.rev, dev->fw.patch); 2557 dev->fw.rev, dev->fw.patch);
2451 wiphy->hw_version = dev->sdev->id.coreid; 2558 wiphy->hw_version = dev->dev->core_id;
2452 2559
2453 if (b43_is_old_txhdr_format(dev)) { 2560 if (b43_is_old_txhdr_format(dev)) {
2454 /* We're over the deadline, but we keep support for old fw 2561 /* We're over the deadline, but we keep support for old fw
@@ -2566,7 +2673,7 @@ out:
2566 */ 2673 */
2567static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev) 2674static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
2568{ 2675{
2569 struct ssb_bus *bus = dev->sdev->bus; 2676 struct ssb_bus *bus = dev->dev->sdev->bus;
2570 2677
2571#ifdef CONFIG_SSB_DRIVER_PCICORE 2678#ifdef CONFIG_SSB_DRIVER_PCICORE
2572 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev); 2679 return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
@@ -2588,7 +2695,7 @@ static int b43_gpio_init(struct b43_wldev *dev)
2588 2695
2589 mask = 0x0000001F; 2696 mask = 0x0000001F;
2590 set = 0x0000000F; 2697 set = 0x0000000F;
2591 if (dev->sdev->bus->chip_id == 0x4301) { 2698 if (dev->dev->chip_id == 0x4301) {
2592 mask |= 0x0060; 2699 mask |= 0x0060;
2593 set |= 0x0060; 2700 set |= 0x0060;
2594 } 2701 }
@@ -2599,21 +2706,34 @@ static int b43_gpio_init(struct b43_wldev *dev)
2599 mask |= 0x0180; 2706 mask |= 0x0180;
2600 set |= 0x0180; 2707 set |= 0x0180;
2601 } 2708 }
2602 if (dev->sdev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) { 2709 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
2603 b43_write16(dev, B43_MMIO_GPIO_MASK, 2710 b43_write16(dev, B43_MMIO_GPIO_MASK,
2604 b43_read16(dev, B43_MMIO_GPIO_MASK) 2711 b43_read16(dev, B43_MMIO_GPIO_MASK)
2605 | 0x0200); 2712 | 0x0200);
2606 mask |= 0x0200; 2713 mask |= 0x0200;
2607 set |= 0x0200; 2714 set |= 0x0200;
2608 } 2715 }
2609 if (dev->sdev->id.revision >= 2) 2716 if (dev->dev->core_rev >= 2)
2610 mask |= 0x0010; /* FIXME: This is redundant. */ 2717 mask |= 0x0010; /* FIXME: This is redundant. */
2611 2718
2612 gpiodev = b43_ssb_gpio_dev(dev); 2719 switch (dev->dev->bus_type) {
2613 if (gpiodev) 2720#ifdef CONFIG_B43_BCMA
2614 ssb_write32(gpiodev, B43_GPIO_CONTROL, 2721 case B43_BUS_BCMA:
2615 (ssb_read32(gpiodev, B43_GPIO_CONTROL) 2722 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2616 & mask) | set); 2723 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2724 BCMA_CC_GPIOCTL) & mask) | set);
2725 break;
2726#endif
2727#ifdef CONFIG_B43_SSB
2728 case B43_BUS_SSB:
2729 gpiodev = b43_ssb_gpio_dev(dev);
2730 if (gpiodev)
2731 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2732 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2733 & mask) | set);
2734 break;
2735#endif
2736 }
2617 2737
2618 return 0; 2738 return 0;
2619} 2739}
@@ -2623,9 +2743,21 @@ static void b43_gpio_cleanup(struct b43_wldev *dev)
2623{ 2743{
2624 struct ssb_device *gpiodev; 2744 struct ssb_device *gpiodev;
2625 2745
2626 gpiodev = b43_ssb_gpio_dev(dev); 2746 switch (dev->dev->bus_type) {
2627 if (gpiodev) 2747#ifdef CONFIG_B43_BCMA
2628 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); 2748 case B43_BUS_BCMA:
2749 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL,
2750 0);
2751 break;
2752#endif
2753#ifdef CONFIG_B43_SSB
2754 case B43_BUS_SSB:
2755 gpiodev = b43_ssb_gpio_dev(dev);
2756 if (gpiodev)
2757 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2758 break;
2759#endif
2760 }
2629} 2761}
2630 2762
2631/* http://bcm-specs.sipsolutions.net/EnableMac */ 2763/* http://bcm-specs.sipsolutions.net/EnableMac */
@@ -2697,12 +2829,30 @@ out:
2697/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */ 2829/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
2698void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on) 2830void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
2699{ 2831{
2700 u32 tmslow = ssb_read32(dev->sdev, SSB_TMSLOW); 2832 u32 tmp;
2701 if (on) 2833
2702 tmslow |= B43_TMSLOW_MACPHYCLKEN; 2834 switch (dev->dev->bus_type) {
2703 else 2835#ifdef CONFIG_B43_BCMA
2704 tmslow &= ~B43_TMSLOW_MACPHYCLKEN; 2836 case B43_BUS_BCMA:
2705 ssb_write32(dev->sdev, SSB_TMSLOW, tmslow); 2837 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
2838 if (on)
2839 tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
2840 else
2841 tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
2842 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
2843 break;
2844#endif
2845#ifdef CONFIG_B43_SSB
2846 case B43_BUS_SSB:
2847 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
2848 if (on)
2849 tmp |= B43_TMSLOW_MACPHYCLKEN;
2850 else
2851 tmp &= ~B43_TMSLOW_MACPHYCLKEN;
2852 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
2853 break;
2854#endif
2855 }
2706} 2856}
2707 2857
2708static void b43_adjust_opmode(struct b43_wldev *dev) 2858static void b43_adjust_opmode(struct b43_wldev *dev)
@@ -2741,15 +2891,15 @@ static void b43_adjust_opmode(struct b43_wldev *dev)
2741 /* Workaround: On old hardware the HW-MAC-address-filter 2891 /* Workaround: On old hardware the HW-MAC-address-filter
2742 * doesn't work properly, so always run promisc in filter 2892 * doesn't work properly, so always run promisc in filter
2743 * it in software. */ 2893 * it in software. */
2744 if (dev->sdev->id.revision <= 4) 2894 if (dev->dev->core_rev <= 4)
2745 ctl |= B43_MACCTL_PROMISC; 2895 ctl |= B43_MACCTL_PROMISC;
2746 2896
2747 b43_write32(dev, B43_MMIO_MACCTL, ctl); 2897 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2748 2898
2749 cfp_pretbtt = 2; 2899 cfp_pretbtt = 2;
2750 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { 2900 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2751 if (dev->sdev->bus->chip_id == 0x4306 && 2901 if (dev->dev->chip_id == 0x4306 &&
2752 dev->sdev->bus->chip_rev == 3) 2902 dev->dev->chip_rev == 3)
2753 cfp_pretbtt = 100; 2903 cfp_pretbtt = 100;
2754 else 2904 else
2755 cfp_pretbtt = 50; 2905 cfp_pretbtt = 50;
@@ -2907,7 +3057,7 @@ static int b43_chip_init(struct b43_wldev *dev)
2907 b43_write16(dev, 0x005E, value16); 3057 b43_write16(dev, 0x005E, value16);
2908 } 3058 }
2909 b43_write32(dev, 0x0100, 0x01000000); 3059 b43_write32(dev, 0x0100, 0x01000000);
2910 if (dev->sdev->id.revision < 5) 3060 if (dev->dev->core_rev < 5)
2911 b43_write32(dev, 0x010C, 0x01000000); 3061 b43_write32(dev, 0x010C, 0x01000000);
2912 3062
2913 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) 3063 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
@@ -2922,7 +3072,7 @@ static int b43_chip_init(struct b43_wldev *dev)
2922 /* Initially set the wireless operation mode. */ 3072 /* Initially set the wireless operation mode. */
2923 b43_adjust_opmode(dev); 3073 b43_adjust_opmode(dev);
2924 3074
2925 if (dev->sdev->id.revision < 3) { 3075 if (dev->dev->core_rev < 3) {
2926 b43_write16(dev, 0x060E, 0x0000); 3076 b43_write16(dev, 0x060E, 0x0000);
2927 b43_write16(dev, 0x0610, 0x8000); 3077 b43_write16(dev, 0x0610, 0x8000);
2928 b43_write16(dev, 0x0604, 0x0000); 3078 b43_write16(dev, 0x0604, 0x0000);
@@ -2941,8 +3091,20 @@ static int b43_chip_init(struct b43_wldev *dev)
2941 3091
2942 b43_mac_phy_clock_set(dev, true); 3092 b43_mac_phy_clock_set(dev, true);
2943 3093
2944 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 3094 switch (dev->dev->bus_type) {
2945 dev->sdev->bus->chipco.fast_pwrup_delay); 3095#ifdef CONFIG_B43_BCMA
3096 case B43_BUS_BCMA:
3097 /* FIXME: 0xE74 is quite common, but should be read from CC */
3098 b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
3099 break;
3100#endif
3101#ifdef CONFIG_B43_SSB
3102 case B43_BUS_SSB:
3103 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
3104 dev->dev->sdev->bus->chipco.fast_pwrup_delay);
3105 break;
3106#endif
3107 }
2946 3108
2947 err = 0; 3109 err = 0;
2948 b43dbg(dev->wl, "Chip initialized\n"); 3110 b43dbg(dev->wl, "Chip initialized\n");
@@ -3105,7 +3267,7 @@ static int b43_validate_chipaccess(struct b43_wldev *dev)
3105 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0); 3267 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3106 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4); 3268 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3107 3269
3108 if ((dev->sdev->id.revision >= 3) && (dev->sdev->id.revision <= 10)) { 3270 if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
3109 /* The 32bit register shadows the two 16bit registers 3271 /* The 32bit register shadows the two 16bit registers
3110 * with update sideeffects. Validate this. */ 3272 * with update sideeffects. Validate this. */
3111 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); 3273 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
@@ -3458,21 +3620,33 @@ static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3458 3620
3459static void b43_put_phy_into_reset(struct b43_wldev *dev) 3621static void b43_put_phy_into_reset(struct b43_wldev *dev)
3460{ 3622{
3461 struct ssb_device *sdev = dev->sdev; 3623 u32 tmp;
3462 u32 tmslow;
3463 3624
3464 tmslow = ssb_read32(sdev, SSB_TMSLOW); 3625 switch (dev->dev->bus_type) {
3465 tmslow &= ~B43_TMSLOW_GMODE; 3626#ifdef CONFIG_B43_BCMA
3466 tmslow |= B43_TMSLOW_PHYRESET; 3627 case B43_BUS_BCMA:
3467 tmslow |= SSB_TMSLOW_FGC; 3628 b43err(dev->wl,
3468 ssb_write32(sdev, SSB_TMSLOW, tmslow); 3629 "Putting PHY into reset not supported on BCMA\n");
3469 msleep(1); 3630 break;
3631#endif
3632#ifdef CONFIG_B43_SSB
3633 case B43_BUS_SSB:
3634 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3635 tmp &= ~B43_TMSLOW_GMODE;
3636 tmp |= B43_TMSLOW_PHYRESET;
3637 tmp |= SSB_TMSLOW_FGC;
3638 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3639 msleep(1);
3640
3641 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
3642 tmp &= ~SSB_TMSLOW_FGC;
3643 tmp |= B43_TMSLOW_PHYRESET;
3644 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
3645 msleep(1);
3470 3646
3471 tmslow = ssb_read32(sdev, SSB_TMSLOW); 3647 break;
3472 tmslow &= ~SSB_TMSLOW_FGC; 3648#endif
3473 tmslow |= B43_TMSLOW_PHYRESET; 3649 }
3474 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3475 msleep(1);
3476} 3650}
3477 3651
3478static const char *band_to_string(enum ieee80211_band band) 3652static const char *band_to_string(enum ieee80211_band band)
@@ -3954,7 +4128,7 @@ redo:
3954 4128
3955 /* Disable interrupts on the device. */ 4129 /* Disable interrupts on the device. */
3956 b43_set_status(dev, B43_STAT_INITIALIZED); 4130 b43_set_status(dev, B43_STAT_INITIALIZED);
3957 if (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) { 4131 if (b43_bus_host_is_sdio(dev->dev)) {
3958 /* wl->mutex is locked. That is enough. */ 4132 /* wl->mutex is locked. That is enough. */
3959 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0); 4133 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3960 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */ 4134 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
@@ -3967,11 +4141,11 @@ redo:
3967 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */ 4141 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
3968 orig_dev = dev; 4142 orig_dev = dev;
3969 mutex_unlock(&wl->mutex); 4143 mutex_unlock(&wl->mutex);
3970 if (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) { 4144 if (b43_bus_host_is_sdio(dev->dev)) {
3971 b43_sdio_free_irq(dev); 4145 b43_sdio_free_irq(dev);
3972 } else { 4146 } else {
3973 synchronize_irq(dev->sdev->irq); 4147 synchronize_irq(dev->dev->irq);
3974 free_irq(dev->sdev->irq, dev); 4148 free_irq(dev->dev->irq, dev);
3975 } 4149 }
3976 mutex_lock(&wl->mutex); 4150 mutex_lock(&wl->mutex);
3977 dev = wl->current_dev; 4151 dev = wl->current_dev;
@@ -4004,19 +4178,19 @@ static int b43_wireless_core_start(struct b43_wldev *dev)
4004 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); 4178 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
4005 4179
4006 drain_txstatus_queue(dev); 4180 drain_txstatus_queue(dev);
4007 if (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) { 4181 if (b43_bus_host_is_sdio(dev->dev)) {
4008 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler); 4182 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
4009 if (err) { 4183 if (err) {
4010 b43err(dev->wl, "Cannot request SDIO IRQ\n"); 4184 b43err(dev->wl, "Cannot request SDIO IRQ\n");
4011 goto out; 4185 goto out;
4012 } 4186 }
4013 } else { 4187 } else {
4014 err = request_threaded_irq(dev->sdev->irq, b43_interrupt_handler, 4188 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
4015 b43_interrupt_thread_handler, 4189 b43_interrupt_thread_handler,
4016 IRQF_SHARED, KBUILD_MODNAME, dev); 4190 IRQF_SHARED, KBUILD_MODNAME, dev);
4017 if (err) { 4191 if (err) {
4018 b43err(dev->wl, "Cannot request IRQ-%d\n", 4192 b43err(dev->wl, "Cannot request IRQ-%d\n",
4019 dev->sdev->irq); 4193 dev->dev->irq);
4020 goto out; 4194 goto out;
4021 } 4195 }
4022 } 4196 }
@@ -4083,9 +4257,21 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4083 unsupported = 1; 4257 unsupported = 1;
4084 break; 4258 break;
4085#endif 4259#endif
4260#ifdef CONFIG_B43_PHY_HT
4261 case B43_PHYTYPE_HT:
4262 if (phy_rev > 1)
4263 unsupported = 1;
4264 break;
4265#endif
4266#ifdef CONFIG_B43_PHY_LCN
4267 case B43_PHYTYPE_LCN:
4268 if (phy_rev > 1)
4269 unsupported = 1;
4270 break;
4271#endif
4086 default: 4272 default:
4087 unsupported = 1; 4273 unsupported = 1;
4088 }; 4274 }
4089 if (unsupported) { 4275 if (unsupported) {
4090 b43err(dev->wl, "FOUND UNSUPPORTED PHY " 4276 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4091 "(Analog %u, Type %u, Revision %u)\n", 4277 "(Analog %u, Type %u, Revision %u)\n",
@@ -4096,22 +4282,42 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4096 analog_type, phy_type, phy_rev); 4282 analog_type, phy_type, phy_rev);
4097 4283
4098 /* Get RADIO versioning */ 4284 /* Get RADIO versioning */
4099 if (dev->sdev->bus->chip_id == 0x4317) { 4285 if (dev->dev->core_rev >= 24) {
4100 if (dev->sdev->bus->chip_rev == 0) 4286 u16 radio24[3];
4101 tmp = 0x3205017F; 4287
4102 else if (dev->sdev->bus->chip_rev == 1) 4288 for (tmp = 0; tmp < 3; tmp++) {
4103 tmp = 0x4205017F; 4289 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
4104 else 4290 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4105 tmp = 0x5205017F; 4291 }
4292
4293 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4294 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4295
4296 radio_manuf = 0x17F;
4297 radio_ver = (radio24[2] << 8) | radio24[1];
4298 radio_rev = (radio24[0] & 0xF);
4106 } else { 4299 } else {
4107 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 4300 if (dev->dev->chip_id == 0x4317) {
4108 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 4301 if (dev->dev->chip_rev == 0)
4109 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); 4302 tmp = 0x3205017F;
4110 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; 4303 else if (dev->dev->chip_rev == 1)
4111 } 4304 tmp = 0x4205017F;
4112 radio_manuf = (tmp & 0x00000FFF); 4305 else
4113 radio_ver = (tmp & 0x0FFFF000) >> 12; 4306 tmp = 0x5205017F;
4114 radio_rev = (tmp & 0xF0000000) >> 28; 4307 } else {
4308 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4309 B43_RADIOCTL_ID);
4310 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4311 b43_write16(dev, B43_MMIO_RADIO_CONTROL,
4312 B43_RADIOCTL_ID);
4313 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
4314 << 16;
4315 }
4316 radio_manuf = (tmp & 0x00000FFF);
4317 radio_ver = (tmp & 0x0FFFF000) >> 12;
4318 radio_rev = (tmp & 0xF0000000) >> 28;
4319 }
4320
4115 if (radio_manuf != 0x17F /* Broadcom */) 4321 if (radio_manuf != 0x17F /* Broadcom */)
4116 unsupported = 1; 4322 unsupported = 1;
4117 switch (phy_type) { 4323 switch (phy_type) {
@@ -4139,6 +4345,14 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4139 if (radio_ver != 0x2062 && radio_ver != 0x2063) 4345 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4140 unsupported = 1; 4346 unsupported = 1;
4141 break; 4347 break;
4348 case B43_PHYTYPE_HT:
4349 if (radio_ver != 0x2059)
4350 unsupported = 1;
4351 break;
4352 case B43_PHYTYPE_LCN:
4353 if (radio_ver != 0x2064)
4354 unsupported = 1;
4355 break;
4142 default: 4356 default:
4143 B43_WARN_ON(1); 4357 B43_WARN_ON(1);
4144 } 4358 }
@@ -4204,7 +4418,7 @@ static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4204 4418
4205static void b43_bluetooth_coext_enable(struct b43_wldev *dev) 4419static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4206{ 4420{
4207 struct ssb_sprom *sprom = &dev->sdev->bus->sprom; 4421 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4208 u64 hf; 4422 u64 hf;
4209 4423
4210 if (!modparam_btcoex) 4424 if (!modparam_btcoex)
@@ -4231,16 +4445,21 @@ static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4231 4445
4232static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) 4446static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4233{ 4447{
4234 struct ssb_bus *bus = dev->sdev->bus; 4448 struct ssb_bus *bus;
4235 u32 tmp; 4449 u32 tmp;
4236 4450
4451 if (dev->dev->bus_type != B43_BUS_SSB)
4452 return;
4453
4454 bus = dev->dev->sdev->bus;
4455
4237 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) || 4456 if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
4238 (bus->chip_id == 0x4312)) { 4457 (bus->chip_id == 0x4312)) {
4239 tmp = ssb_read32(dev->sdev, SSB_IMCFGLO); 4458 tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
4240 tmp &= ~SSB_IMCFGLO_REQTO; 4459 tmp &= ~SSB_IMCFGLO_REQTO;
4241 tmp &= ~SSB_IMCFGLO_SERTO; 4460 tmp &= ~SSB_IMCFGLO_SERTO;
4242 tmp |= 0x3; 4461 tmp |= 0x3;
4243 ssb_write32(dev->sdev, SSB_IMCFGLO, tmp); 4462 ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
4244 ssb_commit_settings(bus); 4463 ssb_commit_settings(bus);
4245 } 4464 }
4246} 4465}
@@ -4310,36 +4529,45 @@ static void b43_wireless_core_exit(struct b43_wldev *dev)
4310 dev->wl->current_beacon = NULL; 4529 dev->wl->current_beacon = NULL;
4311 } 4530 }
4312 4531
4313 ssb_device_disable(dev->sdev, 0); 4532 b43_device_disable(dev, 0);
4314 ssb_bus_may_powerdown(dev->sdev->bus); 4533 b43_bus_may_powerdown(dev);
4315} 4534}
4316 4535
4317/* Initialize a wireless core */ 4536/* Initialize a wireless core */
4318static int b43_wireless_core_init(struct b43_wldev *dev) 4537static int b43_wireless_core_init(struct b43_wldev *dev)
4319{ 4538{
4320 struct ssb_bus *bus = dev->sdev->bus; 4539 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4321 struct ssb_sprom *sprom = &bus->sprom;
4322 struct b43_phy *phy = &dev->phy; 4540 struct b43_phy *phy = &dev->phy;
4323 int err; 4541 int err;
4324 u64 hf; 4542 u64 hf;
4325 u32 tmp;
4326 4543
4327 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4544 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4328 4545
4329 err = ssb_bus_powerup(bus, 0); 4546 err = b43_bus_powerup(dev, 0);
4330 if (err) 4547 if (err)
4331 goto out; 4548 goto out;
4332 if (!ssb_device_is_enabled(dev->sdev)) { 4549 if (!b43_device_is_enabled(dev))
4333 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; 4550 b43_wireless_core_reset(dev, phy->gmode);
4334 b43_wireless_core_reset(dev, tmp);
4335 }
4336 4551
4337 /* Reset all data structures. */ 4552 /* Reset all data structures. */
4338 setup_struct_wldev_for_init(dev); 4553 setup_struct_wldev_for_init(dev);
4339 phy->ops->prepare_structs(dev); 4554 phy->ops->prepare_structs(dev);
4340 4555
4341 /* Enable IRQ routing to this device. */ 4556 /* Enable IRQ routing to this device. */
4342 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->sdev); 4557 switch (dev->dev->bus_type) {
4558#ifdef CONFIG_B43_BCMA
4559 case B43_BUS_BCMA:
4560 bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci,
4561 dev->dev->bdev, true);
4562 break;
4563#endif
4564#ifdef CONFIG_B43_SSB
4565 case B43_BUS_SSB:
4566 ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
4567 dev->dev->sdev);
4568 break;
4569#endif
4570 }
4343 4571
4344 b43_imcfglo_timeouts_workaround(dev); 4572 b43_imcfglo_timeouts_workaround(dev);
4345 b43_bluetooth_coext_disable(dev); 4573 b43_bluetooth_coext_disable(dev);
@@ -4352,7 +4580,7 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
4352 if (err) 4580 if (err)
4353 goto err_busdown; 4581 goto err_busdown;
4354 b43_shm_write16(dev, B43_SHM_SHARED, 4582 b43_shm_write16(dev, B43_SHM_SHARED,
4355 B43_SHM_SH_WLCOREREV, dev->sdev->id.revision); 4583 B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
4356 hf = b43_hf_read(dev); 4584 hf = b43_hf_read(dev);
4357 if (phy->type == B43_PHYTYPE_G) { 4585 if (phy->type == B43_PHYTYPE_G) {
4358 hf |= B43_HF_SYMW; 4586 hf |= B43_HF_SYMW;
@@ -4370,8 +4598,9 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
4370 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW) 4598 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4371 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */ 4599 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4372#ifdef CONFIG_SSB_DRIVER_PCICORE 4600#ifdef CONFIG_SSB_DRIVER_PCICORE
4373 if ((bus->bustype == SSB_BUSTYPE_PCI) && 4601 if (dev->dev->bus_type == B43_BUS_SSB &&
4374 (bus->pcicore.dev->id.revision <= 10)) 4602 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
4603 dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
4375 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */ 4604 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4376#endif 4605#endif
4377 hf &= ~B43_HF_SKCFPUP; 4606 hf &= ~B43_HF_SKCFPUP;
@@ -4399,8 +4628,8 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
4399 /* Maximum Contention Window */ 4628 /* Maximum Contention Window */
4400 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); 4629 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4401 4630
4402 if ((dev->sdev->bus->bustype == SSB_BUSTYPE_PCMCIA) || 4631 if (b43_bus_host_is_pcmcia(dev->dev) ||
4403 (dev->sdev->bus->bustype == SSB_BUSTYPE_SDIO) || 4632 b43_bus_host_is_sdio(dev->dev) ||
4404 dev->use_pio) { 4633 dev->use_pio) {
4405 dev->__using_pio_transfers = 1; 4634 dev->__using_pio_transfers = 1;
4406 err = b43_pio_init(dev); 4635 err = b43_pio_init(dev);
@@ -4414,7 +4643,7 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
4414 b43_set_synth_pu_delay(dev, 1); 4643 b43_set_synth_pu_delay(dev, 1);
4415 b43_bluetooth_coext_enable(dev); 4644 b43_bluetooth_coext_enable(dev);
4416 4645
4417 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)); 4646 b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4418 b43_upload_card_macaddress(dev); 4647 b43_upload_card_macaddress(dev);
4419 b43_security_init(dev); 4648 b43_security_init(dev);
4420 4649
@@ -4431,7 +4660,7 @@ out:
4431err_chip_exit: 4660err_chip_exit:
4432 b43_chip_exit(dev); 4661 b43_chip_exit(dev);
4433err_busdown: 4662err_busdown:
4434 ssb_bus_may_powerdown(bus); 4663 b43_bus_may_powerdown(dev);
4435 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); 4664 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4436 return err; 4665 return err;
4437} 4666}
@@ -4737,11 +4966,10 @@ static void b43_wireless_core_detach(struct b43_wldev *dev)
4737static int b43_wireless_core_attach(struct b43_wldev *dev) 4966static int b43_wireless_core_attach(struct b43_wldev *dev)
4738{ 4967{
4739 struct b43_wl *wl = dev->wl; 4968 struct b43_wl *wl = dev->wl;
4740 struct ssb_bus *bus = dev->sdev->bus; 4969 struct pci_dev *pdev = NULL;
4741 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
4742 int err; 4970 int err;
4743 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4744 u32 tmp; 4971 u32 tmp;
4972 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4745 4973
4746 /* Do NOT do any device initialization here. 4974 /* Do NOT do any device initialization here.
4747 * Do it in wireless_core_init() instead. 4975 * Do it in wireless_core_init() instead.
@@ -4750,25 +4978,42 @@ static int b43_wireless_core_attach(struct b43_wldev *dev)
4750 * that in core_init(), too. 4978 * that in core_init(), too.
4751 */ 4979 */
4752 4980
4753 err = ssb_bus_powerup(bus, 0); 4981#ifdef CONFIG_B43_SSB
4982 if (dev->dev->bus_type == B43_BUS_SSB &&
4983 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
4984 pdev = dev->dev->sdev->bus->host_pci;
4985#endif
4986
4987 err = b43_bus_powerup(dev, 0);
4754 if (err) { 4988 if (err) {
4755 b43err(wl, "Bus powerup failed\n"); 4989 b43err(wl, "Bus powerup failed\n");
4756 goto out; 4990 goto out;
4757 } 4991 }
4758 /* Get the PHY type. */
4759 if (dev->sdev->id.revision >= 5) {
4760 u32 tmshigh;
4761 4992
4762 tmshigh = ssb_read32(dev->sdev, SSB_TMSHIGH); 4993 /* Get the PHY type. */
4763 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY); 4994 switch (dev->dev->bus_type) {
4764 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY); 4995#ifdef CONFIG_B43_BCMA
4765 } else 4996 case B43_BUS_BCMA:
4766 B43_WARN_ON(1); 4997 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
4998 have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
4999 have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
5000 break;
5001#endif
5002#ifdef CONFIG_B43_SSB
5003 case B43_BUS_SSB:
5004 if (dev->dev->core_rev >= 5) {
5005 tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
5006 have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
5007 have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
5008 } else
5009 B43_WARN_ON(1);
5010 break;
5011#endif
5012 }
4767 5013
4768 dev->phy.gmode = have_2ghz_phy; 5014 dev->phy.gmode = have_2ghz_phy;
4769 dev->phy.radio_on = 1; 5015 dev->phy.radio_on = 1;
4770 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 5016 b43_wireless_core_reset(dev, dev->phy.gmode);
4771 b43_wireless_core_reset(dev, tmp);
4772 5017
4773 err = b43_phy_versioning(dev); 5018 err = b43_phy_versioning(dev);
4774 if (err) 5019 if (err)
@@ -4790,6 +5035,8 @@ static int b43_wireless_core_attach(struct b43_wldev *dev)
4790#endif 5035#endif
4791 case B43_PHYTYPE_G: 5036 case B43_PHYTYPE_G:
4792 case B43_PHYTYPE_N: 5037 case B43_PHYTYPE_N:
5038 case B43_PHYTYPE_HT:
5039 case B43_PHYTYPE_LCN:
4793 have_2ghz_phy = 1; 5040 have_2ghz_phy = 1;
4794 break; 5041 break;
4795 default: 5042 default:
@@ -4816,8 +5063,7 @@ static int b43_wireless_core_attach(struct b43_wldev *dev)
4816 goto err_powerdown; 5063 goto err_powerdown;
4817 5064
4818 dev->phy.gmode = have_2ghz_phy; 5065 dev->phy.gmode = have_2ghz_phy;
4819 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; 5066 b43_wireless_core_reset(dev, dev->phy.gmode);
4820 b43_wireless_core_reset(dev, tmp);
4821 5067
4822 err = b43_validate_chipaccess(dev); 5068 err = b43_validate_chipaccess(dev);
4823 if (err) 5069 if (err)
@@ -4832,8 +5078,8 @@ static int b43_wireless_core_attach(struct b43_wldev *dev)
4832 INIT_WORK(&dev->restart_work, b43_chip_reset); 5078 INIT_WORK(&dev->restart_work, b43_chip_reset);
4833 5079
4834 dev->phy.ops->switch_analog(dev, 0); 5080 dev->phy.ops->switch_analog(dev, 0);
4835 ssb_device_disable(dev->sdev, 0); 5081 b43_device_disable(dev, 0);
4836 ssb_bus_may_powerdown(bus); 5082 b43_bus_may_powerdown(dev);
4837 5083
4838out: 5084out:
4839 return err; 5085 return err;
@@ -4841,11 +5087,11 @@ out:
4841err_phy_free: 5087err_phy_free:
4842 b43_phy_free(dev); 5088 b43_phy_free(dev);
4843err_powerdown: 5089err_powerdown:
4844 ssb_bus_may_powerdown(bus); 5090 b43_bus_may_powerdown(dev);
4845 return err; 5091 return err;
4846} 5092}
4847 5093
4848static void b43_one_core_detach(struct ssb_device *dev) 5094static void b43_one_core_detach(struct b43_bus_dev *dev)
4849{ 5095{
4850 struct b43_wldev *wldev; 5096 struct b43_wldev *wldev;
4851 struct b43_wl *wl; 5097 struct b43_wl *wl;
@@ -4853,17 +5099,17 @@ static void b43_one_core_detach(struct ssb_device *dev)
4853 /* Do not cancel ieee80211-workqueue based work here. 5099 /* Do not cancel ieee80211-workqueue based work here.
4854 * See comment in b43_remove(). */ 5100 * See comment in b43_remove(). */
4855 5101
4856 wldev = ssb_get_drvdata(dev); 5102 wldev = b43_bus_get_wldev(dev);
4857 wl = wldev->wl; 5103 wl = wldev->wl;
4858 b43_debugfs_remove_device(wldev); 5104 b43_debugfs_remove_device(wldev);
4859 b43_wireless_core_detach(wldev); 5105 b43_wireless_core_detach(wldev);
4860 list_del(&wldev->list); 5106 list_del(&wldev->list);
4861 wl->nr_devs--; 5107 wl->nr_devs--;
4862 ssb_set_drvdata(dev, NULL); 5108 b43_bus_set_wldev(dev, NULL);
4863 kfree(wldev); 5109 kfree(wldev);
4864} 5110}
4865 5111
4866static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) 5112static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
4867{ 5113{
4868 struct b43_wldev *wldev; 5114 struct b43_wldev *wldev;
4869 int err = -ENOMEM; 5115 int err = -ENOMEM;
@@ -4873,7 +5119,7 @@ static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4873 goto out; 5119 goto out;
4874 5120
4875 wldev->use_pio = b43_modparam_pio; 5121 wldev->use_pio = b43_modparam_pio;
4876 wldev->sdev = dev; 5122 wldev->dev = dev;
4877 wldev->wl = wl; 5123 wldev->wl = wl;
4878 b43_set_status(wldev, B43_STAT_UNINIT); 5124 b43_set_status(wldev, B43_STAT_UNINIT);
4879 wldev->bad_frames_preempt = modparam_bad_frames_preempt; 5125 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
@@ -4885,7 +5131,7 @@ static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4885 5131
4886 list_add(&wldev->list, &wl->devlist); 5132 list_add(&wldev->list, &wl->devlist);
4887 wl->nr_devs++; 5133 wl->nr_devs++;
4888 ssb_set_drvdata(dev, wldev); 5134 b43_bus_set_wldev(dev, wldev);
4889 b43_debugfs_add_device(wldev); 5135 b43_debugfs_add_device(wldev);
4890 5136
4891 out: 5137 out:
@@ -4926,19 +5172,20 @@ static void b43_sprom_fixup(struct ssb_bus *bus)
4926 } 5172 }
4927} 5173}
4928 5174
4929static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) 5175static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
4930{ 5176{
4931 struct ieee80211_hw *hw = wl->hw; 5177 struct ieee80211_hw *hw = wl->hw;
4932 5178
4933 ssb_set_devtypedata(dev, NULL); 5179 ssb_set_devtypedata(dev->sdev, NULL);
4934 ieee80211_free_hw(hw); 5180 ieee80211_free_hw(hw);
4935} 5181}
4936 5182
4937static struct b43_wl *b43_wireless_init(struct ssb_device *dev) 5183static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
4938{ 5184{
4939 struct ssb_sprom *sprom = &dev->bus->sprom; 5185 struct ssb_sprom *sprom = dev->bus_sprom;
4940 struct ieee80211_hw *hw; 5186 struct ieee80211_hw *hw;
4941 struct b43_wl *wl; 5187 struct b43_wl *wl;
5188 char chip_name[6];
4942 5189
4943 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); 5190 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4944 if (!hw) { 5191 if (!hw) {
@@ -4977,29 +5224,105 @@ static struct b43_wl *b43_wireless_init(struct ssb_device *dev)
4977 INIT_WORK(&wl->tx_work, b43_tx_work); 5224 INIT_WORK(&wl->tx_work, b43_tx_work);
4978 skb_queue_head_init(&wl->tx_queue); 5225 skb_queue_head_init(&wl->tx_queue);
4979 5226
4980 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n", 5227 snprintf(chip_name, ARRAY_SIZE(chip_name),
4981 dev->bus->chip_id, dev->id.revision); 5228 (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
5229 b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
5230 dev->core_rev);
4982 return wl; 5231 return wl;
4983} 5232}
4984 5233
4985static int b43_ssb_probe(struct ssb_device *dev, const struct ssb_device_id *id) 5234#ifdef CONFIG_B43_BCMA
5235static int b43_bcma_probe(struct bcma_device *core)
4986{ 5236{
5237 struct b43_bus_dev *dev;
5238 struct b43_wl *wl;
5239 int err;
5240
5241 dev = b43_bus_dev_bcma_init(core);
5242 if (!dev)
5243 return -ENODEV;
5244
5245 wl = b43_wireless_init(dev);
5246 if (IS_ERR(wl)) {
5247 err = PTR_ERR(wl);
5248 goto bcma_out;
5249 }
5250
5251 err = b43_one_core_attach(dev, wl);
5252 if (err)
5253 goto bcma_err_wireless_exit;
5254
5255 err = ieee80211_register_hw(wl->hw);
5256 if (err)
5257 goto bcma_err_one_core_detach;
5258 b43_leds_register(wl->current_dev);
5259
5260bcma_out:
5261 return err;
5262
5263bcma_err_one_core_detach:
5264 b43_one_core_detach(dev);
5265bcma_err_wireless_exit:
5266 ieee80211_free_hw(wl->hw);
5267 return err;
5268}
5269
5270static void b43_bcma_remove(struct bcma_device *core)
5271{
5272 struct b43_wldev *wldev = bcma_get_drvdata(core);
5273 struct b43_wl *wl = wldev->wl;
5274
5275 /* We must cancel any work here before unregistering from ieee80211,
5276 * as the ieee80211 unreg will destroy the workqueue. */
5277 cancel_work_sync(&wldev->restart_work);
5278
5279 /* Restore the queues count before unregistering, because firmware detect
5280 * might have modified it. Restoring is important, so the networking
5281 * stack can properly free resources. */
5282 wl->hw->queues = wl->mac80211_initially_registered_queues;
5283 b43_leds_stop(wldev);
5284 ieee80211_unregister_hw(wl->hw);
5285
5286 b43_one_core_detach(wldev->dev);
5287
5288 b43_leds_unregister(wl);
5289
5290 ieee80211_free_hw(wl->hw);
5291}
5292
5293static struct bcma_driver b43_bcma_driver = {
5294 .name = KBUILD_MODNAME,
5295 .id_table = b43_bcma_tbl,
5296 .probe = b43_bcma_probe,
5297 .remove = b43_bcma_remove,
5298};
5299#endif
5300
5301#ifdef CONFIG_B43_SSB
5302static
5303int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
5304{
5305 struct b43_bus_dev *dev;
4987 struct b43_wl *wl; 5306 struct b43_wl *wl;
4988 int err; 5307 int err;
4989 int first = 0; 5308 int first = 0;
4990 5309
4991 wl = ssb_get_devtypedata(dev); 5310 dev = b43_bus_dev_ssb_init(sdev);
5311 if (!dev)
5312 return -ENOMEM;
5313
5314 wl = ssb_get_devtypedata(sdev);
4992 if (!wl) { 5315 if (!wl) {
4993 /* Probing the first core. Must setup common struct b43_wl */ 5316 /* Probing the first core. Must setup common struct b43_wl */
4994 first = 1; 5317 first = 1;
4995 b43_sprom_fixup(dev->bus); 5318 b43_sprom_fixup(sdev->bus);
4996 wl = b43_wireless_init(dev); 5319 wl = b43_wireless_init(dev);
4997 if (IS_ERR(wl)) { 5320 if (IS_ERR(wl)) {
4998 err = PTR_ERR(wl); 5321 err = PTR_ERR(wl);
4999 goto out; 5322 goto out;
5000 } 5323 }
5001 ssb_set_devtypedata(dev, wl); 5324 ssb_set_devtypedata(sdev, wl);
5002 B43_WARN_ON(ssb_get_devtypedata(dev) != wl); 5325 B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
5003 } 5326 }
5004 err = b43_one_core_attach(dev, wl); 5327 err = b43_one_core_attach(dev, wl);
5005 if (err) 5328 if (err)
@@ -5023,10 +5346,10 @@ static int b43_ssb_probe(struct ssb_device *dev, const struct ssb_device_id *id)
5023 return err; 5346 return err;
5024} 5347}
5025 5348
5026static void b43_ssb_remove(struct ssb_device *dev) 5349static void b43_ssb_remove(struct ssb_device *sdev)
5027{ 5350{
5028 struct b43_wl *wl = ssb_get_devtypedata(dev); 5351 struct b43_wl *wl = ssb_get_devtypedata(sdev);
5029 struct b43_wldev *wldev = ssb_get_drvdata(dev); 5352 struct b43_wldev *wldev = ssb_get_drvdata(sdev);
5030 5353
5031 /* We must cancel any work here before unregistering from ieee80211, 5354 /* We must cancel any work here before unregistering from ieee80211,
5032 * as the ieee80211 unreg will destroy the workqueue. */ 5355 * as the ieee80211 unreg will destroy the workqueue. */
@@ -5042,17 +5365,25 @@ static void b43_ssb_remove(struct ssb_device *dev)
5042 ieee80211_unregister_hw(wl->hw); 5365 ieee80211_unregister_hw(wl->hw);
5043 } 5366 }
5044 5367
5045 b43_one_core_detach(dev); 5368 b43_one_core_detach(wldev->dev);
5046 5369
5047 if (list_empty(&wl->devlist)) { 5370 if (list_empty(&wl->devlist)) {
5048 b43_leds_unregister(wl); 5371 b43_leds_unregister(wl);
5049 /* Last core on the chip unregistered. 5372 /* Last core on the chip unregistered.
5050 * We can destroy common struct b43_wl. 5373 * We can destroy common struct b43_wl.
5051 */ 5374 */
5052 b43_wireless_exit(dev, wl); 5375 b43_wireless_exit(wldev->dev, wl);
5053 } 5376 }
5054} 5377}
5055 5378
5379static struct ssb_driver b43_ssb_driver = {
5380 .name = KBUILD_MODNAME,
5381 .id_table = b43_ssb_tbl,
5382 .probe = b43_ssb_probe,
5383 .remove = b43_ssb_remove,
5384};
5385#endif /* CONFIG_B43_SSB */
5386
5056/* Perform a hardware reset. This can be called from any context. */ 5387/* Perform a hardware reset. This can be called from any context. */
5057void b43_controller_restart(struct b43_wldev *dev, const char *reason) 5388void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5058{ 5389{
@@ -5063,13 +5394,6 @@ void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5063 ieee80211_queue_work(dev->wl->hw, &dev->restart_work); 5394 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
5064} 5395}
5065 5396
5066static struct ssb_driver b43_ssb_driver = {
5067 .name = KBUILD_MODNAME,
5068 .id_table = b43_ssb_tbl,
5069 .probe = b43_ssb_probe,
5070 .remove = b43_ssb_remove,
5071};
5072
5073static void b43_print_driverinfo(void) 5397static void b43_print_driverinfo(void)
5074{ 5398{
5075 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", 5399 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
@@ -5108,14 +5432,27 @@ static int __init b43_init(void)
5108 err = b43_sdio_init(); 5432 err = b43_sdio_init();
5109 if (err) 5433 if (err)
5110 goto err_pcmcia_exit; 5434 goto err_pcmcia_exit;
5111 err = ssb_driver_register(&b43_ssb_driver); 5435#ifdef CONFIG_B43_BCMA
5436 err = bcma_driver_register(&b43_bcma_driver);
5112 if (err) 5437 if (err)
5113 goto err_sdio_exit; 5438 goto err_sdio_exit;
5439#endif
5440#ifdef CONFIG_B43_SSB
5441 err = ssb_driver_register(&b43_ssb_driver);
5442 if (err)
5443 goto err_bcma_driver_exit;
5444#endif
5114 b43_print_driverinfo(); 5445 b43_print_driverinfo();
5115 5446
5116 return err; 5447 return err;
5117 5448
5449#ifdef CONFIG_B43_SSB
5450err_bcma_driver_exit:
5451#endif
5452#ifdef CONFIG_B43_BCMA
5453 bcma_driver_unregister(&b43_bcma_driver);
5118err_sdio_exit: 5454err_sdio_exit:
5455#endif
5119 b43_sdio_exit(); 5456 b43_sdio_exit();
5120err_pcmcia_exit: 5457err_pcmcia_exit:
5121 b43_pcmcia_exit(); 5458 b43_pcmcia_exit();
@@ -5126,7 +5463,12 @@ err_dfs_exit:
5126 5463
5127static void __exit b43_exit(void) 5464static void __exit b43_exit(void)
5128{ 5465{
5466#ifdef CONFIG_B43_SSB
5129 ssb_driver_unregister(&b43_ssb_driver); 5467 ssb_driver_unregister(&b43_ssb_driver);
5468#endif
5469#ifdef CONFIG_B43_BCMA
5470 bcma_driver_unregister(&b43_bcma_driver);
5471#endif
5130 b43_sdio_exit(); 5472 b43_sdio_exit();
5131 b43_pcmcia_exit(); 5473 b43_pcmcia_exit();
5132 b43_debugfs_exit(); 5474 b43_debugfs_exit();
diff --git a/drivers/net/wireless/b43/main.h b/drivers/net/wireless/b43/main.h
index a0d327f13183..e4ebce9be592 100644
--- a/drivers/net/wireless/b43/main.h
+++ b/drivers/net/wireless/b43/main.h
@@ -121,7 +121,7 @@ void b43_hf_write(struct b43_wldev *dev, u64 value);
121 121
122void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on); 122void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on);
123 123
124void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags); 124void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode);
125 125
126void b43_controller_restart(struct b43_wldev *dev, const char *reason); 126void b43_controller_restart(struct b43_wldev *dev, const char *reason);
127 127
diff --git a/drivers/net/wireless/b43/phy_a.c b/drivers/net/wireless/b43/phy_a.c
index b01c8ced57c3..73ace5552bad 100644
--- a/drivers/net/wireless/b43/phy_a.c
+++ b/drivers/net/wireless/b43/phy_a.c
@@ -265,7 +265,6 @@ static void hardware_pctl_init_aphy(struct b43_wldev *dev)
265 265
266void b43_phy_inita(struct b43_wldev *dev) 266void b43_phy_inita(struct b43_wldev *dev)
267{ 267{
268 struct ssb_bus *bus = dev->sdev->bus;
269 struct b43_phy *phy = &dev->phy; 268 struct b43_phy *phy = &dev->phy;
270 269
271 /* This lowlevel A-PHY init is also called from G-PHY init. 270 /* This lowlevel A-PHY init is also called from G-PHY init.
@@ -296,9 +295,9 @@ void b43_phy_inita(struct b43_wldev *dev)
296 295
297 b43_radio_init2060(dev); 296 b43_radio_init2060(dev);
298 297
299 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) && 298 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
300 ((bus->boardinfo.type == SSB_BOARD_BU4306) || 299 ((dev->dev->board_type == SSB_BOARD_BU4306) ||
301 (bus->boardinfo.type == SSB_BOARD_BU4309))) { 300 (dev->dev->board_type == SSB_BOARD_BU4309))) {
302 ; //TODO: A PHY LO 301 ; //TODO: A PHY LO
303 } 302 }
304 303
@@ -311,7 +310,7 @@ void b43_phy_inita(struct b43_wldev *dev)
311 } 310 }
312 311
313 if ((phy->type == B43_PHYTYPE_G) && 312 if ((phy->type == B43_PHYTYPE_G) &&
314 (dev->sdev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) { 313 (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)) {
315 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF); 314 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF);
316 } 315 }
317} 316}
@@ -323,17 +322,17 @@ static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev)
323 struct b43_phy_a *aphy = phy->a; 322 struct b43_phy_a *aphy = phy->a;
324 s16 pab0, pab1, pab2; 323 s16 pab0, pab1, pab2;
325 324
326 pab0 = (s16) (dev->sdev->bus->sprom.pa1b0); 325 pab0 = (s16) (dev->dev->bus_sprom->pa1b0);
327 pab1 = (s16) (dev->sdev->bus->sprom.pa1b1); 326 pab1 = (s16) (dev->dev->bus_sprom->pa1b1);
328 pab2 = (s16) (dev->sdev->bus->sprom.pa1b2); 327 pab2 = (s16) (dev->dev->bus_sprom->pa1b2);
329 328
330 if (pab0 != 0 && pab1 != 0 && pab2 != 0 && 329 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
331 pab0 != -1 && pab1 != -1 && pab2 != -1) { 330 pab0 != -1 && pab1 != -1 && pab2 != -1) {
332 /* The pabX values are set in SPROM. Use them. */ 331 /* The pabX values are set in SPROM. Use them. */
333 if ((s8) dev->sdev->bus->sprom.itssi_a != 0 && 332 if ((s8) dev->dev->bus_sprom->itssi_a != 0 &&
334 (s8) dev->sdev->bus->sprom.itssi_a != -1) 333 (s8) dev->dev->bus_sprom->itssi_a != -1)
335 aphy->tgt_idle_tssi = 334 aphy->tgt_idle_tssi =
336 (s8) (dev->sdev->bus->sprom.itssi_a); 335 (s8) (dev->dev->bus_sprom->itssi_a);
337 else 336 else
338 aphy->tgt_idle_tssi = 62; 337 aphy->tgt_idle_tssi = 62;
339 aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, 338 aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
diff --git a/drivers/net/wireless/b43/phy_common.c b/drivers/net/wireless/b43/phy_common.c
index e46b2f4f0920..101957512bcc 100644
--- a/drivers/net/wireless/b43/phy_common.c
+++ b/drivers/net/wireless/b43/phy_common.c
@@ -31,6 +31,8 @@
31#include "phy_a.h" 31#include "phy_a.h"
32#include "phy_n.h" 32#include "phy_n.h"
33#include "phy_lp.h" 33#include "phy_lp.h"
34#include "phy_ht.h"
35#include "phy_lcn.h"
34#include "b43.h" 36#include "b43.h"
35#include "main.h" 37#include "main.h"
36 38
@@ -59,6 +61,16 @@ int b43_phy_allocate(struct b43_wldev *dev)
59 phy->ops = &b43_phyops_lp; 61 phy->ops = &b43_phyops_lp;
60#endif 62#endif
61 break; 63 break;
64 case B43_PHYTYPE_HT:
65#ifdef CONFIG_B43_PHY_HT
66 phy->ops = &b43_phyops_ht;
67#endif
68 break;
69 case B43_PHYTYPE_LCN:
70#ifdef CONFIG_B43_PHY_LCN
71 phy->ops = &b43_phyops_lcn;
72#endif
73 break;
62 } 74 }
63 if (B43_WARN_ON(!phy->ops)) 75 if (B43_WARN_ON(!phy->ops))
64 return -ENODEV; 76 return -ENODEV;
@@ -168,7 +180,7 @@ void b43_phy_lock(struct b43_wldev *dev)
168 B43_WARN_ON(dev->phy.phy_locked); 180 B43_WARN_ON(dev->phy.phy_locked);
169 dev->phy.phy_locked = 1; 181 dev->phy.phy_locked = 1;
170#endif 182#endif
171 B43_WARN_ON(dev->sdev->id.revision < 3); 183 B43_WARN_ON(dev->dev->core_rev < 3);
172 184
173 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) 185 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
174 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); 186 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
@@ -180,7 +192,7 @@ void b43_phy_unlock(struct b43_wldev *dev)
180 B43_WARN_ON(!dev->phy.phy_locked); 192 B43_WARN_ON(!dev->phy.phy_locked);
181 dev->phy.phy_locked = 0; 193 dev->phy.phy_locked = 0;
182#endif 194#endif
183 B43_WARN_ON(dev->sdev->id.revision < 3); 195 B43_WARN_ON(dev->dev->core_rev < 3);
184 196
185 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) 197 if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
186 b43_power_saving_ctl_bits(dev, 0); 198 b43_power_saving_ctl_bits(dev, 0);
@@ -368,8 +380,8 @@ void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
368 /* The next check will be needed in two seconds, or later. */ 380 /* The next check will be needed in two seconds, or later. */
369 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2)); 381 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
370 382
371 if ((dev->sdev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) && 383 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
372 (dev->sdev->bus->boardinfo.type == SSB_BOARD_BU4306)) 384 (dev->dev->board_type == SSB_BOARD_BU4306))
373 return; /* No software txpower adjustment needed */ 385 return; /* No software txpower adjustment needed */
374 386
375 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI)); 387 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
diff --git a/drivers/net/wireless/b43/phy_common.h b/drivers/net/wireless/b43/phy_common.h
index 2401bee8b081..aa77ba612a92 100644
--- a/drivers/net/wireless/b43/phy_common.h
+++ b/drivers/net/wireless/b43/phy_common.h
@@ -194,6 +194,8 @@ struct b43_phy_a;
194struct b43_phy_g; 194struct b43_phy_g;
195struct b43_phy_n; 195struct b43_phy_n;
196struct b43_phy_lp; 196struct b43_phy_lp;
197struct b43_phy_ht;
198struct b43_phy_lcn;
197 199
198struct b43_phy { 200struct b43_phy {
199 /* Hardware operation callbacks. */ 201 /* Hardware operation callbacks. */
@@ -216,6 +218,10 @@ struct b43_phy {
216 struct b43_phy_n *n; 218 struct b43_phy_n *n;
217 /* LP-PHY specific information */ 219 /* LP-PHY specific information */
218 struct b43_phy_lp *lp; 220 struct b43_phy_lp *lp;
221 /* HT-PHY specific information */
222 struct b43_phy_ht *ht;
223 /* LCN-PHY specific information */
224 struct b43_phy_lcn *lcn;
219 }; 225 };
220 226
221 /* Band support flags. */ 227 /* Band support flags. */
diff --git a/drivers/net/wireless/b43/phy_g.c b/drivers/net/wireless/b43/phy_g.c
index 1758a282f913..83532d19347f 100644
--- a/drivers/net/wireless/b43/phy_g.c
+++ b/drivers/net/wireless/b43/phy_g.c
@@ -718,7 +718,7 @@ static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
718 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 718 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
719 719
720 if (!phy->gmode || 720 if (!phy->gmode ||
721 !(dev->sdev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) { 721 !(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) {
722 tmp16 = b43_nrssi_hw_read(dev, 0x20); 722 tmp16 = b43_nrssi_hw_read(dev, 0x20);
723 if (tmp16 >= 0x20) 723 if (tmp16 >= 0x20)
724 tmp16 -= 0x40; 724 tmp16 -= 0x40;
@@ -1114,7 +1114,7 @@ static u16 radio2050_rfover_val(struct b43_wldev *dev,
1114{ 1114{
1115 struct b43_phy *phy = &dev->phy; 1115 struct b43_phy *phy = &dev->phy;
1116 struct b43_phy_g *gphy = phy->g; 1116 struct b43_phy_g *gphy = phy->g;
1117 struct ssb_sprom *sprom = &(dev->sdev->bus->sprom); 1117 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1118 1118
1119 if (!phy->gmode) 1119 if (!phy->gmode)
1120 return 0; 1120 return 0;
@@ -1491,7 +1491,6 @@ static u16 b43_radio_init2050(struct b43_wldev *dev)
1491 1491
1492static void b43_phy_initb5(struct b43_wldev *dev) 1492static void b43_phy_initb5(struct b43_wldev *dev)
1493{ 1493{
1494 struct ssb_bus *bus = dev->sdev->bus;
1495 struct b43_phy *phy = &dev->phy; 1494 struct b43_phy *phy = &dev->phy;
1496 struct b43_phy_g *gphy = phy->g; 1495 struct b43_phy_g *gphy = phy->g;
1497 u16 offset, value; 1496 u16 offset, value;
@@ -1500,8 +1499,8 @@ static void b43_phy_initb5(struct b43_wldev *dev)
1500 if (phy->analog == 1) { 1499 if (phy->analog == 1) {
1501 b43_radio_set(dev, 0x007A, 0x0050); 1500 b43_radio_set(dev, 0x007A, 0x0050);
1502 } 1501 }
1503 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) && 1502 if ((dev->dev->board_vendor != SSB_BOARDVENDOR_BCM) &&
1504 (bus->boardinfo.type != SSB_BOARD_BU4306)) { 1503 (dev->dev->board_type != SSB_BOARD_BU4306)) {
1505 value = 0x2120; 1504 value = 0x2120;
1506 for (offset = 0x00A8; offset < 0x00C7; offset++) { 1505 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1507 b43_phy_write(dev, offset, value); 1506 b43_phy_write(dev, offset, value);
@@ -1620,7 +1619,7 @@ static void b43_phy_initb6(struct b43_wldev *dev)
1620 b43_radio_write16(dev, 0x5A, 0x88); 1619 b43_radio_write16(dev, 0x5A, 0x88);
1621 b43_radio_write16(dev, 0x5B, 0x6B); 1620 b43_radio_write16(dev, 0x5B, 0x6B);
1622 b43_radio_write16(dev, 0x5C, 0x0F); 1621 b43_radio_write16(dev, 0x5C, 0x0F);
1623 if (dev->sdev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) { 1622 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_ALTIQ) {
1624 b43_radio_write16(dev, 0x5D, 0xFA); 1623 b43_radio_write16(dev, 0x5D, 0xFA);
1625 b43_radio_write16(dev, 0x5E, 0xD8); 1624 b43_radio_write16(dev, 0x5E, 0xD8);
1626 } else { 1625 } else {
@@ -1787,7 +1786,7 @@ static void b43_calc_loopback_gain(struct b43_wldev *dev)
1787 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100); 1786 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1788 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF); 1787 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
1789 1788
1790 if (dev->sdev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) { 1789 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) {
1791 if (phy->rev >= 7) { 1790 if (phy->rev >= 7) {
1792 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800); 1791 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800);
1793 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000); 1792 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000);
@@ -1922,7 +1921,6 @@ static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
1922/* Initialize B/G PHY power control */ 1921/* Initialize B/G PHY power control */
1923static void b43_phy_init_pctl(struct b43_wldev *dev) 1922static void b43_phy_init_pctl(struct b43_wldev *dev)
1924{ 1923{
1925 struct ssb_bus *bus = dev->sdev->bus;
1926 struct b43_phy *phy = &dev->phy; 1924 struct b43_phy *phy = &dev->phy;
1927 struct b43_phy_g *gphy = phy->g; 1925 struct b43_phy_g *gphy = phy->g;
1928 struct b43_rfatt old_rfatt; 1926 struct b43_rfatt old_rfatt;
@@ -1931,8 +1929,8 @@ static void b43_phy_init_pctl(struct b43_wldev *dev)
1931 1929
1932 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 1930 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
1933 1931
1934 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) && 1932 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) &&
1935 (bus->boardinfo.type == SSB_BOARD_BU4306)) 1933 (dev->dev->board_type == SSB_BOARD_BU4306))
1936 return; 1934 return;
1937 1935
1938 b43_phy_write(dev, 0x0028, 0x8018); 1936 b43_phy_write(dev, 0x0028, 0x8018);
@@ -2053,7 +2051,7 @@ static void b43_phy_initg(struct b43_wldev *dev)
2053 if (phy->rev >= 6) { 2051 if (phy->rev >= 6) {
2054 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12)); 2052 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12));
2055 } 2053 }
2056 if (dev->sdev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) 2054 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)
2057 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075); 2055 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2058 else 2056 else
2059 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F); 2057 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
@@ -2066,7 +2064,7 @@ static void b43_phy_initg(struct b43_wldev *dev)
2066 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); 2064 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2067 } 2065 }
2068 2066
2069 if (!(dev->sdev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) { 2067 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) {
2070 /* The specs state to update the NRSSI LT with 2068 /* The specs state to update the NRSSI LT with
2071 * the value 0x7FFFFFFF here. I think that is some weird 2069 * the value 0x7FFFFFFF here. I think that is some weird
2072 * compiler optimization in the original driver. 2070 * compiler optimization in the original driver.
@@ -2088,8 +2086,8 @@ static void b43_phy_initg(struct b43_wldev *dev)
2088 /* FIXME: The spec says in the following if, the 0 should be replaced 2086 /* FIXME: The spec says in the following if, the 0 should be replaced
2089 'if OFDM may not be used in the current locale' 2087 'if OFDM may not be used in the current locale'
2090 but OFDM is legal everywhere */ 2088 but OFDM is legal everywhere */
2091 if ((dev->sdev->bus->chip_id == 0x4306 2089 if ((dev->dev->chip_id == 0x4306
2092 && dev->sdev->bus->chip_package == 2) || 0) { 2090 && dev->dev->chip_pkg == 2) || 0) {
2093 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF); 2091 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF);
2094 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF); 2092 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF);
2095 } 2093 }
@@ -2105,7 +2103,7 @@ void b43_gphy_channel_switch(struct b43_wldev *dev,
2105 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); 2103 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2106 2104
2107 if (channel == 14) { 2105 if (channel == 14) {
2108 if (dev->sdev->bus->sprom.country_code == 2106 if (dev->dev->bus_sprom->country_code ==
2109 SSB_SPROM1CCODE_JAPAN) 2107 SSB_SPROM1CCODE_JAPAN)
2110 b43_hf_write(dev, 2108 b43_hf_write(dev,
2111 b43_hf_read(dev) & ~B43_HF_ACPR); 2109 b43_hf_read(dev) & ~B43_HF_ACPR);
@@ -2136,17 +2134,17 @@ static void default_baseband_attenuation(struct b43_wldev *dev,
2136static void default_radio_attenuation(struct b43_wldev *dev, 2134static void default_radio_attenuation(struct b43_wldev *dev,
2137 struct b43_rfatt *rf) 2135 struct b43_rfatt *rf)
2138{ 2136{
2139 struct ssb_bus *bus = dev->sdev->bus; 2137 struct b43_bus_dev *bdev = dev->dev;
2140 struct b43_phy *phy = &dev->phy; 2138 struct b43_phy *phy = &dev->phy;
2141 2139
2142 rf->with_padmix = 0; 2140 rf->with_padmix = 0;
2143 2141
2144 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM && 2142 if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM &&
2145 bus->boardinfo.type == SSB_BOARD_BCM4309G) { 2143 dev->dev->board_type == SSB_BOARD_BCM4309G) {
2146 if (bus->boardinfo.rev < 0x43) { 2144 if (dev->dev->board_rev < 0x43) {
2147 rf->att = 2; 2145 rf->att = 2;
2148 return; 2146 return;
2149 } else if (bus->boardinfo.rev < 0x51) { 2147 } else if (dev->dev->board_rev < 0x51) {
2150 rf->att = 3; 2148 rf->att = 3;
2151 return; 2149 return;
2152 } 2150 }
@@ -2172,21 +2170,21 @@ static void default_radio_attenuation(struct b43_wldev *dev,
2172 return; 2170 return;
2173 case 1: 2171 case 1:
2174 if (phy->type == B43_PHYTYPE_G) { 2172 if (phy->type == B43_PHYTYPE_G) {
2175 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM 2173 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM
2176 && bus->boardinfo.type == SSB_BOARD_BCM4309G 2174 && bdev->board_type == SSB_BOARD_BCM4309G
2177 && bus->boardinfo.rev >= 30) 2175 && bdev->board_rev >= 30)
2178 rf->att = 3; 2176 rf->att = 3;
2179 else if (bus->boardinfo.vendor == 2177 else if (bdev->board_vendor ==
2180 SSB_BOARDVENDOR_BCM 2178 SSB_BOARDVENDOR_BCM
2181 && bus->boardinfo.type == 2179 && bdev->board_type ==
2182 SSB_BOARD_BU4306) 2180 SSB_BOARD_BU4306)
2183 rf->att = 3; 2181 rf->att = 3;
2184 else 2182 else
2185 rf->att = 1; 2183 rf->att = 1;
2186 } else { 2184 } else {
2187 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM 2185 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM
2188 && bus->boardinfo.type == SSB_BOARD_BCM4309G 2186 && bdev->board_type == SSB_BOARD_BCM4309G
2189 && bus->boardinfo.rev >= 30) 2187 && bdev->board_rev >= 30)
2190 rf->att = 7; 2188 rf->att = 7;
2191 else 2189 else
2192 rf->att = 6; 2190 rf->att = 6;
@@ -2194,16 +2192,16 @@ static void default_radio_attenuation(struct b43_wldev *dev,
2194 return; 2192 return;
2195 case 2: 2193 case 2:
2196 if (phy->type == B43_PHYTYPE_G) { 2194 if (phy->type == B43_PHYTYPE_G) {
2197 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM 2195 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM
2198 && bus->boardinfo.type == SSB_BOARD_BCM4309G 2196 && bdev->board_type == SSB_BOARD_BCM4309G
2199 && bus->boardinfo.rev >= 30) 2197 && bdev->board_rev >= 30)
2200 rf->att = 3; 2198 rf->att = 3;
2201 else if (bus->boardinfo.vendor == 2199 else if (bdev->board_vendor ==
2202 SSB_BOARDVENDOR_BCM 2200 SSB_BOARDVENDOR_BCM
2203 && bus->boardinfo.type == 2201 && bdev->board_type ==
2204 SSB_BOARD_BU4306) 2202 SSB_BOARD_BU4306)
2205 rf->att = 5; 2203 rf->att = 5;
2206 else if (bus->chip_id == 0x4320) 2204 else if (bdev->chip_id == 0x4320)
2207 rf->att = 4; 2205 rf->att = 4;
2208 else 2206 else
2209 rf->att = 3; 2207 rf->att = 3;
@@ -2384,11 +2382,11 @@ static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2384 struct b43_phy_g *gphy = phy->g; 2382 struct b43_phy_g *gphy = phy->g;
2385 s16 pab0, pab1, pab2; 2383 s16 pab0, pab1, pab2;
2386 2384
2387 pab0 = (s16) (dev->sdev->bus->sprom.pa0b0); 2385 pab0 = (s16) (dev->dev->bus_sprom->pa0b0);
2388 pab1 = (s16) (dev->sdev->bus->sprom.pa0b1); 2386 pab1 = (s16) (dev->dev->bus_sprom->pa0b1);
2389 pab2 = (s16) (dev->sdev->bus->sprom.pa0b2); 2387 pab2 = (s16) (dev->dev->bus_sprom->pa0b2);
2390 2388
2391 B43_WARN_ON((dev->sdev->bus->chip_id == 0x4301) && 2389 B43_WARN_ON((dev->dev->chip_id == 0x4301) &&
2392 (phy->radio_ver != 0x2050)); /* Not supported anymore */ 2390 (phy->radio_ver != 0x2050)); /* Not supported anymore */
2393 2391
2394 gphy->dyn_tssi_tbl = 0; 2392 gphy->dyn_tssi_tbl = 0;
@@ -2396,10 +2394,10 @@ static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2396 if (pab0 != 0 && pab1 != 0 && pab2 != 0 && 2394 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2397 pab0 != -1 && pab1 != -1 && pab2 != -1) { 2395 pab0 != -1 && pab1 != -1 && pab2 != -1) {
2398 /* The pabX values are set in SPROM. Use them. */ 2396 /* The pabX values are set in SPROM. Use them. */
2399 if ((s8) dev->sdev->bus->sprom.itssi_bg != 0 && 2397 if ((s8) dev->dev->bus_sprom->itssi_bg != 0 &&
2400 (s8) dev->sdev->bus->sprom.itssi_bg != -1) { 2398 (s8) dev->dev->bus_sprom->itssi_bg != -1) {
2401 gphy->tgt_idle_tssi = 2399 gphy->tgt_idle_tssi =
2402 (s8) (dev->sdev->bus->sprom.itssi_bg); 2400 (s8) (dev->dev->bus_sprom->itssi_bg);
2403 } else 2401 } else
2404 gphy->tgt_idle_tssi = 62; 2402 gphy->tgt_idle_tssi = 62;
2405 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, 2403 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
@@ -2537,7 +2535,7 @@ static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev)
2537 b43_wireless_core_reset(dev, 0); 2535 b43_wireless_core_reset(dev, 0);
2538 b43_phy_initg(dev); 2536 b43_phy_initg(dev);
2539 phy->gmode = 1; 2537 phy->gmode = 1;
2540 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE); 2538 b43_wireless_core_reset(dev, 1);
2541 } 2539 }
2542 2540
2543 return 0; 2541 return 0;
@@ -2840,7 +2838,7 @@ static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev)
2840 B43_TXCTL_TXMIX; 2838 B43_TXCTL_TXMIX;
2841 rfatt += 2; 2839 rfatt += 2;
2842 bbatt += 2; 2840 bbatt += 2;
2843 } else if (dev->sdev->bus->sprom. 2841 } else if (dev->dev->bus_sprom->
2844 boardflags_lo & 2842 boardflags_lo &
2845 B43_BFL_PACTRL) { 2843 B43_BFL_PACTRL) {
2846 bbatt += 4 * (rfatt - 2); 2844 bbatt += 4 * (rfatt - 2);
@@ -2914,14 +2912,14 @@ static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev,
2914 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi); 2912 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi);
2915 2913
2916 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2914 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2917 max_pwr = dev->sdev->bus->sprom.maxpwr_bg; 2915 max_pwr = dev->dev->bus_sprom->maxpwr_bg;
2918 if (dev->sdev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) 2916 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL)
2919 max_pwr -= 3; /* minus 0.75 */ 2917 max_pwr -= 3; /* minus 0.75 */
2920 if (unlikely(max_pwr >= INT_TO_Q52(30/*dBm*/))) { 2918 if (unlikely(max_pwr >= INT_TO_Q52(30/*dBm*/))) {
2921 b43warn(dev->wl, 2919 b43warn(dev->wl,
2922 "Invalid max-TX-power value in SPROM.\n"); 2920 "Invalid max-TX-power value in SPROM.\n");
2923 max_pwr = INT_TO_Q52(20); /* fake it */ 2921 max_pwr = INT_TO_Q52(20); /* fake it */
2924 dev->sdev->bus->sprom.maxpwr_bg = max_pwr; 2922 dev->dev->bus_sprom->maxpwr_bg = max_pwr;
2925 } 2923 }
2926 2924
2927 /* Get desired power (in Q5.2) */ 2925 /* Get desired power (in Q5.2) */
@@ -3014,7 +3012,7 @@ static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3014{ 3012{
3015 struct b43_phy *phy = &dev->phy; 3013 struct b43_phy *phy = &dev->phy;
3016 3014
3017 if (!(dev->sdev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) 3015 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI))
3018 return; 3016 return;
3019 3017
3020 b43_mac_suspend(dev); 3018 b43_mac_suspend(dev);
diff --git a/drivers/net/wireless/b43/phy_ht.c b/drivers/net/wireless/b43/phy_ht.c
new file mode 100644
index 000000000000..7c40919651a7
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_ht.c
@@ -0,0 +1,413 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n HT-PHY support
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
19 Boston, MA 02110-1301, USA.
20
21*/
22
23#include <linux/slab.h>
24
25#include "b43.h"
26#include "phy_ht.h"
27#include "tables_phy_ht.h"
28#include "radio_2059.h"
29#include "main.h"
30
31/**************************************************
32 * Radio 2059.
33 **************************************************/
34
35static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
36 const struct b43_phy_ht_channeltab_e_radio2059 *e)
37{
38 u8 i;
39 u16 routing;
40
41 b43_radio_write(dev, 0x16, e->radio_syn16);
42 b43_radio_write(dev, 0x17, e->radio_syn17);
43 b43_radio_write(dev, 0x22, e->radio_syn22);
44 b43_radio_write(dev, 0x25, e->radio_syn25);
45 b43_radio_write(dev, 0x27, e->radio_syn27);
46 b43_radio_write(dev, 0x28, e->radio_syn28);
47 b43_radio_write(dev, 0x29, e->radio_syn29);
48 b43_radio_write(dev, 0x2c, e->radio_syn2c);
49 b43_radio_write(dev, 0x2d, e->radio_syn2d);
50 b43_radio_write(dev, 0x37, e->radio_syn37);
51 b43_radio_write(dev, 0x41, e->radio_syn41);
52 b43_radio_write(dev, 0x43, e->radio_syn43);
53 b43_radio_write(dev, 0x47, e->radio_syn47);
54 b43_radio_write(dev, 0x4a, e->radio_syn4a);
55 b43_radio_write(dev, 0x58, e->radio_syn58);
56 b43_radio_write(dev, 0x5a, e->radio_syn5a);
57 b43_radio_write(dev, 0x6a, e->radio_syn6a);
58 b43_radio_write(dev, 0x6d, e->radio_syn6d);
59 b43_radio_write(dev, 0x6e, e->radio_syn6e);
60 b43_radio_write(dev, 0x92, e->radio_syn92);
61 b43_radio_write(dev, 0x98, e->radio_syn98);
62
63 for (i = 0; i < 2; i++) {
64 routing = i ? R2059_RXRX1 : R2059_TXRX0;
65 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
66 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
67 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
68 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
69 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
70 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
71 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
72 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
73 }
74
75 udelay(50);
76
77 /* Calibration */
78 b43_radio_mask(dev, 0x2b, ~0x1);
79 b43_radio_mask(dev, 0x2e, ~0x4);
80 b43_radio_set(dev, 0x2e, 0x4);
81 b43_radio_set(dev, 0x2b, 0x1);
82
83 udelay(300);
84}
85
86static void b43_radio_2059_init(struct b43_wldev *dev)
87{
88 const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
89 const u16 radio_values[3][2] = {
90 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
91 };
92 u16 i, j;
93
94 b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
95 b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
96
97 for (i = 0; i < ARRAY_SIZE(routing); i++)
98 b43_radio_set(dev, routing[i] | 0x146, 0x3);
99
100 b43_radio_set(dev, 0x2e, 0x0078);
101 b43_radio_set(dev, 0xc0, 0x0080);
102 msleep(2);
103 b43_radio_mask(dev, 0x2e, ~0x0078);
104 b43_radio_mask(dev, 0xc0, ~0x0080);
105
106 if (1) { /* FIXME */
107 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
108 udelay(10);
109 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
110 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
111
112 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
113 udelay(100);
114 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
115
116 for (i = 0; i < 10000; i++) {
117 if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
118 i = 0;
119 break;
120 }
121 udelay(100);
122 }
123 if (i)
124 b43err(dev->wl, "radio 0x945 timeout\n");
125
126 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
127 b43_radio_set(dev, 0xa, 0x60);
128
129 for (i = 0; i < 3; i++) {
130 b43_radio_write(dev, 0x17F, radio_values[i][0]);
131 b43_radio_write(dev, 0x13D, 0x6E);
132 b43_radio_write(dev, 0x13E, radio_values[i][1]);
133 b43_radio_write(dev, 0x13C, 0x55);
134
135 for (j = 0; j < 10000; j++) {
136 if (b43_radio_read(dev, 0x140) & 2) {
137 j = 0;
138 break;
139 }
140 udelay(500);
141 }
142 if (j)
143 b43err(dev->wl, "radio 0x140 timeout\n");
144
145 b43_radio_write(dev, 0x13C, 0x15);
146 }
147
148 b43_radio_mask(dev, 0x17F, ~0x1);
149 }
150
151 b43_radio_mask(dev, 0x11, ~0x0008);
152}
153
154/**************************************************
155 * Channel switching ops.
156 **************************************************/
157
158static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
159 const struct b43_phy_ht_channeltab_e_phy *e,
160 struct ieee80211_channel *new_channel)
161{
162 bool old_band_5ghz;
163 u8 i;
164
165 old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
166 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
167 /* TODO */
168 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
169 /* TODO */
170 }
171
172 b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
173 b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
174 b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
175 b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
176 b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
177 b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
178
179 /* TODO: some ops on PHY regs 0x0B0 and 0xC0A */
180
181 /* TODO: separated function? */
182 for (i = 0; i < 3; i++) {
183 u16 mask;
184 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
185
186 if (0) /* FIXME */
187 mask = 0x2 << (i * 4);
188 else
189 mask = 0;
190 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
191
192 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
193 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
194 tmp & 0xFF);
195 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
196 tmp & 0xFF);
197 }
198
199 b43_phy_write(dev, 0x017e, 0x3830);
200}
201
202static int b43_phy_ht_set_channel(struct b43_wldev *dev,
203 struct ieee80211_channel *channel,
204 enum nl80211_channel_type channel_type)
205{
206 struct b43_phy *phy = &dev->phy;
207
208 const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
209
210 if (phy->radio_ver == 0x2059) {
211 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
212 channel->center_freq);
213 if (!chent_r2059)
214 return -ESRCH;
215 } else {
216 return -ESRCH;
217 }
218
219 /* TODO: In case of N-PHY some bandwidth switching goes here */
220
221 if (phy->radio_ver == 0x2059) {
222 b43_radio_2059_channel_setup(dev, chent_r2059);
223 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
224 channel);
225 } else {
226 return -ESRCH;
227 }
228
229 return 0;
230}
231
232/**************************************************
233 * Basic PHY ops.
234 **************************************************/
235
236static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
237{
238 struct b43_phy_ht *phy_ht;
239
240 phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
241 if (!phy_ht)
242 return -ENOMEM;
243 dev->phy.ht = phy_ht;
244
245 return 0;
246}
247
248static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
249{
250 struct b43_phy *phy = &dev->phy;
251 struct b43_phy_ht *phy_ht = phy->ht;
252
253 memset(phy_ht, 0, sizeof(*phy_ht));
254}
255
256static int b43_phy_ht_op_init(struct b43_wldev *dev)
257{
258 b43_phy_ht_tables_init(dev);
259
260 return 0;
261}
262
263static void b43_phy_ht_op_free(struct b43_wldev *dev)
264{
265 struct b43_phy *phy = &dev->phy;
266 struct b43_phy_ht *phy_ht = phy->ht;
267
268 kfree(phy_ht);
269 phy->ht = NULL;
270}
271
272/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
273static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
274 bool blocked)
275{
276 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
277 b43err(dev->wl, "MAC not suspended\n");
278
279 /* In the following PHY ops we copy wl's dummy behaviour.
280 * TODO: Find out if reads (currently hidden in masks/masksets) are
281 * needed and replace following ops with just writes or w&r.
282 * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
283 * cause delayed (!) machine lock up. */
284 if (blocked) {
285 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
286 } else {
287 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
288 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
289 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
290 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
291
292 if (dev->phy.radio_ver == 0x2059)
293 b43_radio_2059_init(dev);
294 else
295 B43_WARN_ON(1);
296
297 b43_switch_channel(dev, dev->phy.channel);
298 }
299}
300
301static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
302{
303 if (on) {
304 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00cd);
305 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x0000);
306 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00cd);
307 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x0000);
308 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00cd);
309 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x0000);
310 } else {
311 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x07ff);
312 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00fd);
313 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x07ff);
314 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00fd);
315 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x07ff);
316 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00fd);
317 }
318}
319
320static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
321 unsigned int new_channel)
322{
323 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
324 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
325
326 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
327 if ((new_channel < 1) || (new_channel > 14))
328 return -EINVAL;
329 } else {
330 return -EINVAL;
331 }
332
333 return b43_phy_ht_set_channel(dev, channel, channel_type);
334}
335
336static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
337{
338 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
339 return 11;
340 return 36;
341}
342
343/**************************************************
344 * R/W ops.
345 **************************************************/
346
347static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
348{
349 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
350 return b43_read16(dev, B43_MMIO_PHY_DATA);
351}
352
353static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
354{
355 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
356 b43_write16(dev, B43_MMIO_PHY_DATA, value);
357}
358
359static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
360 u16 set)
361{
362 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
363 b43_write16(dev, B43_MMIO_PHY_DATA,
364 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
365}
366
367static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
368{
369 /* HT-PHY needs 0x200 for read access */
370 reg |= 0x200;
371
372 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
373 return b43_read16(dev, B43_MMIO_RADIO24_DATA);
374}
375
376static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
377 u16 value)
378{
379 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
380 b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
381}
382
383static enum b43_txpwr_result
384b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
385{
386 return B43_TXPWR_RES_DONE;
387}
388
389static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
390{
391}
392
393/**************************************************
394 * PHY ops struct.
395 **************************************************/
396
397const struct b43_phy_operations b43_phyops_ht = {
398 .allocate = b43_phy_ht_op_allocate,
399 .free = b43_phy_ht_op_free,
400 .prepare_structs = b43_phy_ht_op_prepare_structs,
401 .init = b43_phy_ht_op_init,
402 .phy_read = b43_phy_ht_op_read,
403 .phy_write = b43_phy_ht_op_write,
404 .phy_maskset = b43_phy_ht_op_maskset,
405 .radio_read = b43_phy_ht_op_radio_read,
406 .radio_write = b43_phy_ht_op_radio_write,
407 .software_rfkill = b43_phy_ht_op_software_rfkill,
408 .switch_analog = b43_phy_ht_op_switch_analog,
409 .switch_channel = b43_phy_ht_op_switch_channel,
410 .get_default_chan = b43_phy_ht_op_get_default_chan,
411 .recalc_txpower = b43_phy_ht_op_recalc_txpower,
412 .adjust_txpower = b43_phy_ht_op_adjust_txpower,
413};
diff --git a/drivers/net/wireless/b43/phy_ht.h b/drivers/net/wireless/b43/phy_ht.h
new file mode 100644
index 000000000000..7ad7affc8df0
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_ht.h
@@ -0,0 +1,46 @@
1#ifndef B43_PHY_HT_H_
2#define B43_PHY_HT_H_
3
4#include "phy_common.h"
5
6
7#define B43_PHY_HT_BANDCTL 0x009 /* Band control */
8#define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
9#define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
10#define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
11#define B43_PHY_HT_BW1 0x1CE
12#define B43_PHY_HT_BW2 0x1CF
13#define B43_PHY_HT_BW3 0x1D0
14#define B43_PHY_HT_BW4 0x1D1
15#define B43_PHY_HT_BW5 0x1D2
16#define B43_PHY_HT_BW6 0x1D3
17
18#define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010)
19
20#define B43_PHY_HT_AFE_CTL1 B43_PHY_EXTG(0x110)
21#define B43_PHY_HT_AFE_CTL2 B43_PHY_EXTG(0x111)
22#define B43_PHY_HT_AFE_CTL3 B43_PHY_EXTG(0x114)
23#define B43_PHY_HT_AFE_CTL4 B43_PHY_EXTG(0x115)
24#define B43_PHY_HT_AFE_CTL5 B43_PHY_EXTG(0x118)
25#define B43_PHY_HT_AFE_CTL6 B43_PHY_EXTG(0x119)
26
27
28/* Values for PHY registers used on channel switching */
29struct b43_phy_ht_channeltab_e_phy {
30 u16 bw1;
31 u16 bw2;
32 u16 bw3;
33 u16 bw4;
34 u16 bw5;
35 u16 bw6;
36};
37
38
39struct b43_phy_ht {
40};
41
42
43struct b43_phy_operations;
44extern const struct b43_phy_operations b43_phyops_ht;
45
46#endif /* B43_PHY_HT_H_ */
diff --git a/drivers/net/wireless/b43/phy_lcn.c b/drivers/net/wireless/b43/phy_lcn.c
new file mode 100644
index 000000000000..9f7dbbd5ced6
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_lcn.c
@@ -0,0 +1,52 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n LCN-PHY support
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
19 Boston, MA 02110-1301, USA.
20
21*/
22
23#include <linux/slab.h>
24
25#include "b43.h"
26#include "phy_lcn.h"
27#include "tables_phy_lcn.h"
28#include "main.h"
29
30/**************************************************
31 * PHY ops struct.
32 **************************************************/
33
34const struct b43_phy_operations b43_phyops_lcn = {
35 /*
36 .allocate = b43_phy_lcn_op_allocate,
37 .free = b43_phy_lcn_op_free,
38 .prepare_structs = b43_phy_lcn_op_prepare_structs,
39 .init = b43_phy_lcn_op_init,
40 .phy_read = b43_phy_lcn_op_read,
41 .phy_write = b43_phy_lcn_op_write,
42 .phy_maskset = b43_phy_lcn_op_maskset,
43 .radio_read = b43_phy_lcn_op_radio_read,
44 .radio_write = b43_phy_lcn_op_radio_write,
45 .software_rfkill = b43_phy_lcn_op_software_rfkill,
46 .switch_analog = b43_phy_lcn_op_switch_analog,
47 .switch_channel = b43_phy_lcn_op_switch_channel,
48 .get_default_chan = b43_phy_lcn_op_get_default_chan,
49 .recalc_txpower = b43_phy_lcn_op_recalc_txpower,
50 .adjust_txpower = b43_phy_lcn_op_adjust_txpower,
51 */
52};
diff --git a/drivers/net/wireless/b43/phy_lcn.h b/drivers/net/wireless/b43/phy_lcn.h
new file mode 100644
index 000000000000..c046c2a6cab4
--- /dev/null
+++ b/drivers/net/wireless/b43/phy_lcn.h
@@ -0,0 +1,14 @@
1#ifndef B43_PHY_LCN_H_
2#define B43_PHY_LCN_H_
3
4#include "phy_common.h"
5
6
7struct b43_phy_lcn {
8};
9
10
11struct b43_phy_operations;
12extern const struct b43_phy_operations b43_phyops_lcn;
13
14#endif /* B43_PHY_LCN_H_ */ \ No newline at end of file
diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c
index 012c8da2f944..daec1d9e4a18 100644
--- a/drivers/net/wireless/b43/phy_lp.c
+++ b/drivers/net/wireless/b43/phy_lp.c
@@ -85,39 +85,39 @@ static void b43_lpphy_op_free(struct b43_wldev *dev)
85/* http://bcm-v4.sipsolutions.net/802.11/PHY/LP/ReadBandSrom */ 85/* http://bcm-v4.sipsolutions.net/802.11/PHY/LP/ReadBandSrom */
86static void lpphy_read_band_sprom(struct b43_wldev *dev) 86static void lpphy_read_band_sprom(struct b43_wldev *dev)
87{ 87{
88 struct ssb_sprom *sprom = dev->dev->bus_sprom;
88 struct b43_phy_lp *lpphy = dev->phy.lp; 89 struct b43_phy_lp *lpphy = dev->phy.lp;
89 struct ssb_bus *bus = dev->sdev->bus;
90 u16 cckpo, maxpwr; 90 u16 cckpo, maxpwr;
91 u32 ofdmpo; 91 u32 ofdmpo;
92 int i; 92 int i;
93 93
94 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 94 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
95 lpphy->tx_isolation_med_band = bus->sprom.tri2g; 95 lpphy->tx_isolation_med_band = sprom->tri2g;
96 lpphy->bx_arch = bus->sprom.bxa2g; 96 lpphy->bx_arch = sprom->bxa2g;
97 lpphy->rx_pwr_offset = bus->sprom.rxpo2g; 97 lpphy->rx_pwr_offset = sprom->rxpo2g;
98 lpphy->rssi_vf = bus->sprom.rssismf2g; 98 lpphy->rssi_vf = sprom->rssismf2g;
99 lpphy->rssi_vc = bus->sprom.rssismc2g; 99 lpphy->rssi_vc = sprom->rssismc2g;
100 lpphy->rssi_gs = bus->sprom.rssisav2g; 100 lpphy->rssi_gs = sprom->rssisav2g;
101 lpphy->txpa[0] = bus->sprom.pa0b0; 101 lpphy->txpa[0] = sprom->pa0b0;
102 lpphy->txpa[1] = bus->sprom.pa0b1; 102 lpphy->txpa[1] = sprom->pa0b1;
103 lpphy->txpa[2] = bus->sprom.pa0b2; 103 lpphy->txpa[2] = sprom->pa0b2;
104 maxpwr = bus->sprom.maxpwr_bg; 104 maxpwr = sprom->maxpwr_bg;
105 lpphy->max_tx_pwr_med_band = maxpwr; 105 lpphy->max_tx_pwr_med_band = maxpwr;
106 cckpo = bus->sprom.cck2gpo; 106 cckpo = sprom->cck2gpo;
107 /* 107 /*
108 * We don't read SPROM's opo as specs say. On rev8 SPROMs 108 * We don't read SPROM's opo as specs say. On rev8 SPROMs
109 * opo == ofdm2gpo and we don't know any SSB with LP-PHY 109 * opo == ofdm2gpo and we don't know any SSB with LP-PHY
110 * and SPROM rev below 8. 110 * and SPROM rev below 8.
111 */ 111 */
112 B43_WARN_ON(bus->sprom.revision < 8); 112 B43_WARN_ON(sprom->revision < 8);
113 ofdmpo = bus->sprom.ofdm2gpo; 113 ofdmpo = sprom->ofdm2gpo;
114 if (cckpo) { 114 if (cckpo) {
115 for (i = 0; i < 4; i++) { 115 for (i = 0; i < 4; i++) {
116 lpphy->tx_max_rate[i] = 116 lpphy->tx_max_rate[i] =
117 maxpwr - (ofdmpo & 0xF) * 2; 117 maxpwr - (ofdmpo & 0xF) * 2;
118 ofdmpo >>= 4; 118 ofdmpo >>= 4;
119 } 119 }
120 ofdmpo = bus->sprom.ofdm2gpo; 120 ofdmpo = sprom->ofdm2gpo;
121 for (i = 4; i < 15; i++) { 121 for (i = 4; i < 15; i++) {
122 lpphy->tx_max_rate[i] = 122 lpphy->tx_max_rate[i] =
123 maxpwr - (ofdmpo & 0xF) * 2; 123 maxpwr - (ofdmpo & 0xF) * 2;
@@ -131,39 +131,39 @@ static void lpphy_read_band_sprom(struct b43_wldev *dev)
131 lpphy->tx_max_rate[i] = maxpwr - ofdmpo; 131 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
132 } 132 }
133 } else { /* 5GHz */ 133 } else { /* 5GHz */
134 lpphy->tx_isolation_low_band = bus->sprom.tri5gl; 134 lpphy->tx_isolation_low_band = sprom->tri5gl;
135 lpphy->tx_isolation_med_band = bus->sprom.tri5g; 135 lpphy->tx_isolation_med_band = sprom->tri5g;
136 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh; 136 lpphy->tx_isolation_hi_band = sprom->tri5gh;
137 lpphy->bx_arch = bus->sprom.bxa5g; 137 lpphy->bx_arch = sprom->bxa5g;
138 lpphy->rx_pwr_offset = bus->sprom.rxpo5g; 138 lpphy->rx_pwr_offset = sprom->rxpo5g;
139 lpphy->rssi_vf = bus->sprom.rssismf5g; 139 lpphy->rssi_vf = sprom->rssismf5g;
140 lpphy->rssi_vc = bus->sprom.rssismc5g; 140 lpphy->rssi_vc = sprom->rssismc5g;
141 lpphy->rssi_gs = bus->sprom.rssisav5g; 141 lpphy->rssi_gs = sprom->rssisav5g;
142 lpphy->txpa[0] = bus->sprom.pa1b0; 142 lpphy->txpa[0] = sprom->pa1b0;
143 lpphy->txpa[1] = bus->sprom.pa1b1; 143 lpphy->txpa[1] = sprom->pa1b1;
144 lpphy->txpa[2] = bus->sprom.pa1b2; 144 lpphy->txpa[2] = sprom->pa1b2;
145 lpphy->txpal[0] = bus->sprom.pa1lob0; 145 lpphy->txpal[0] = sprom->pa1lob0;
146 lpphy->txpal[1] = bus->sprom.pa1lob1; 146 lpphy->txpal[1] = sprom->pa1lob1;
147 lpphy->txpal[2] = bus->sprom.pa1lob2; 147 lpphy->txpal[2] = sprom->pa1lob2;
148 lpphy->txpah[0] = bus->sprom.pa1hib0; 148 lpphy->txpah[0] = sprom->pa1hib0;
149 lpphy->txpah[1] = bus->sprom.pa1hib1; 149 lpphy->txpah[1] = sprom->pa1hib1;
150 lpphy->txpah[2] = bus->sprom.pa1hib2; 150 lpphy->txpah[2] = sprom->pa1hib2;
151 maxpwr = bus->sprom.maxpwr_al; 151 maxpwr = sprom->maxpwr_al;
152 ofdmpo = bus->sprom.ofdm5glpo; 152 ofdmpo = sprom->ofdm5glpo;
153 lpphy->max_tx_pwr_low_band = maxpwr; 153 lpphy->max_tx_pwr_low_band = maxpwr;
154 for (i = 4; i < 12; i++) { 154 for (i = 4; i < 12; i++) {
155 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2; 155 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
156 ofdmpo >>= 4; 156 ofdmpo >>= 4;
157 } 157 }
158 maxpwr = bus->sprom.maxpwr_a; 158 maxpwr = sprom->maxpwr_a;
159 ofdmpo = bus->sprom.ofdm5gpo; 159 ofdmpo = sprom->ofdm5gpo;
160 lpphy->max_tx_pwr_med_band = maxpwr; 160 lpphy->max_tx_pwr_med_band = maxpwr;
161 for (i = 4; i < 12; i++) { 161 for (i = 4; i < 12; i++) {
162 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2; 162 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
163 ofdmpo >>= 4; 163 ofdmpo >>= 4;
164 } 164 }
165 maxpwr = bus->sprom.maxpwr_ah; 165 maxpwr = sprom->maxpwr_ah;
166 ofdmpo = bus->sprom.ofdm5ghpo; 166 ofdmpo = sprom->ofdm5ghpo;
167 lpphy->max_tx_pwr_hi_band = maxpwr; 167 lpphy->max_tx_pwr_hi_band = maxpwr;
168 for (i = 4; i < 12; i++) { 168 for (i = 4; i < 12; i++) {
169 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2; 169 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
@@ -214,7 +214,8 @@ static void lpphy_table_init(struct b43_wldev *dev)
214 214
215static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev) 215static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
216{ 216{
217 struct ssb_bus *bus = dev->sdev->bus; 217 struct ssb_bus *bus = dev->dev->sdev->bus;
218 struct ssb_sprom *sprom = dev->dev->bus_sprom;
218 struct b43_phy_lp *lpphy = dev->phy.lp; 219 struct b43_phy_lp *lpphy = dev->phy.lp;
219 u16 tmp, tmp2; 220 u16 tmp, tmp2;
220 221
@@ -242,9 +243,9 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
242 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00); 243 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
243 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 244 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
244 0xFF00, lpphy->rx_pwr_offset); 245 0xFF00, lpphy->rx_pwr_offset);
245 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) && 246 if ((sprom->boardflags_lo & B43_BFL_FEM) &&
246 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || 247 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
247 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) { 248 (sprom->boardflags_hi & B43_BFH_PAREF))) {
248 ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28); 249 ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28);
249 ssb_pmu_set_ldo_paref(&bus->chipco, true); 250 ssb_pmu_set_ldo_paref(&bus->chipco, true);
250 if (dev->phy.rev == 0) { 251 if (dev->phy.rev == 0) {
@@ -260,7 +261,7 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
260 } 261 }
261 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000; 262 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
262 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp); 263 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
263 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV) 264 if (sprom->boardflags_hi & B43_BFH_RSSIINV)
264 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA); 265 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
265 else 266 else
266 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA); 267 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
@@ -268,7 +269,7 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
268 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL, 269 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
269 0xFFF9, (lpphy->bx_arch << 1)); 270 0xFFF9, (lpphy->bx_arch << 1));
270 if (dev->phy.rev == 1 && 271 if (dev->phy.rev == 1 &&
271 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) { 272 (sprom->boardflags_hi & B43_BFH_FEM_BT)) {
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A); 273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900); 274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A); 275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
@@ -286,8 +287,8 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A); 287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00); 288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
288 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ || 289 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
289 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) && 290 (dev->dev->board_type == 0x048A) || ((dev->phy.rev == 0) &&
290 (bus->sprom.boardflags_lo & B43_BFL_FEM))) { 291 (sprom->boardflags_lo & B43_BFL_FEM))) {
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001); 292 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
292 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400); 293 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
293 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001); 294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
@@ -297,7 +298,7 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002); 298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
298 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00); 299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
299 } else if (dev->phy.rev == 1 || 300 } else if (dev->phy.rev == 1 ||
300 (bus->sprom.boardflags_lo & B43_BFL_FEM)) { 301 (sprom->boardflags_lo & B43_BFL_FEM)) {
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004); 302 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
302 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800); 303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004); 304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
@@ -316,15 +317,15 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
316 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006); 317 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
317 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700); 318 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
318 } 319 }
319 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) { 320 if (dev->phy.rev == 1 && (sprom->boardflags_hi & B43_BFH_PAREF)) {
320 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1); 321 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
321 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2); 322 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
322 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3); 323 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
323 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4); 324 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
324 } 325 }
325 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) && 326 if ((sprom->boardflags_hi & B43_BFH_FEM_BT) &&
326 (bus->chip_id == 0x5354) && 327 (dev->dev->chip_id == 0x5354) &&
327 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) { 328 (dev->dev->chip_pkg == SSB_CHIPPACK_BCM4712S)) {
328 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006); 329 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
329 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005); 330 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
330 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF); 331 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
@@ -412,7 +413,6 @@ static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
412 413
413static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev) 414static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
414{ 415{
415 struct ssb_bus *bus = dev->sdev->bus;
416 struct b43_phy_lp *lpphy = dev->phy.lp; 416 struct b43_phy_lp *lpphy = dev->phy.lp;
417 417
418 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50); 418 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
@@ -432,7 +432,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
432 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000); 432 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
433 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000); 433 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
434 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1); 434 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
435 if (bus->boardinfo.rev >= 0x18) { 435 if (dev->dev->board_rev >= 0x18) {
436 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC); 436 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
437 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14); 437 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
438 } else { 438 } else {
@@ -449,7 +449,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
449 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0); 449 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
450 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300); 450 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
451 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00); 451 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
452 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) { 452 if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
453 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100); 453 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
454 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA); 454 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
455 } else { 455 } else {
@@ -467,7 +467,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
467 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12); 467 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
468 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000); 468 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
469 469
470 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) { 470 if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
471 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0); 471 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
472 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40); 472 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
473 } 473 }
@@ -492,7 +492,7 @@ static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
492 0x2000 | ((u16)lpphy->rssi_gs << 10) | 492 0x2000 | ((u16)lpphy->rssi_gs << 10) |
493 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf); 493 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
494 494
495 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) { 495 if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
496 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C); 496 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
497 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800); 497 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
498 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400); 498 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
@@ -519,7 +519,7 @@ struct b2062_freqdata {
519static void lpphy_2062_init(struct b43_wldev *dev) 519static void lpphy_2062_init(struct b43_wldev *dev)
520{ 520{
521 struct b43_phy_lp *lpphy = dev->phy.lp; 521 struct b43_phy_lp *lpphy = dev->phy.lp;
522 struct ssb_bus *bus = dev->sdev->bus; 522 struct ssb_bus *bus = dev->dev->sdev->bus;
523 u32 crystalfreq, tmp, ref; 523 u32 crystalfreq, tmp, ref;
524 unsigned int i; 524 unsigned int i;
525 const struct b2062_freqdata *fd = NULL; 525 const struct b2062_freqdata *fd = NULL;
@@ -697,7 +697,7 @@ static void lpphy_radio_init(struct b43_wldev *dev)
697 lpphy_sync_stx(dev); 697 lpphy_sync_stx(dev);
698 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80); 698 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
699 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0); 699 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
700 if (dev->sdev->bus->chip_id == 0x4325) { 700 if (dev->dev->chip_id == 0x4325) {
701 // TODO SSB PMU recalibration 701 // TODO SSB PMU recalibration
702 } 702 }
703 } 703 }
@@ -1289,7 +1289,7 @@ finish:
1289 1289
1290static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev) 1290static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1291{ 1291{
1292 struct ssb_bus *bus = dev->sdev->bus; 1292 struct ssb_bus *bus = dev->dev->sdev->bus;
1293 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000; 1293 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1294 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF; 1294 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1295 int i; 1295 int i;
@@ -1840,7 +1840,6 @@ static void lpphy_papd_cal(struct b43_wldev *dev, struct lpphy_tx_gains gains,
1840static void lpphy_papd_cal_txpwr(struct b43_wldev *dev) 1840static void lpphy_papd_cal_txpwr(struct b43_wldev *dev)
1841{ 1841{
1842 struct b43_phy_lp *lpphy = dev->phy.lp; 1842 struct b43_phy_lp *lpphy = dev->phy.lp;
1843 struct ssb_bus *bus = dev->sdev->bus;
1844 struct lpphy_tx_gains gains, oldgains; 1843 struct lpphy_tx_gains gains, oldgains;
1845 int old_txpctl, old_afe_ovr, old_rf, old_bbmult; 1844 int old_txpctl, old_afe_ovr, old_rf, old_bbmult;
1846 1845
@@ -1854,7 +1853,7 @@ static void lpphy_papd_cal_txpwr(struct b43_wldev *dev)
1854 1853
1855 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF); 1854 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1856 1855
1857 if (bus->chip_id == 0x4325 && bus->chip_rev == 0) 1856 if (dev->dev->chip_id == 0x4325 && dev->dev->chip_rev == 0)
1858 lpphy_papd_cal(dev, gains, 0, 1, 30); 1857 lpphy_papd_cal(dev, gains, 0, 1, 30);
1859 else 1858 else
1860 lpphy_papd_cal(dev, gains, 0, 1, 65); 1859 lpphy_papd_cal(dev, gains, 0, 1, 65);
@@ -1870,7 +1869,6 @@ static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx,
1870 bool rx, bool pa, struct lpphy_tx_gains *gains) 1869 bool rx, bool pa, struct lpphy_tx_gains *gains)
1871{ 1870{
1872 struct b43_phy_lp *lpphy = dev->phy.lp; 1871 struct b43_phy_lp *lpphy = dev->phy.lp;
1873 struct ssb_bus *bus = dev->sdev->bus;
1874 const struct lpphy_rx_iq_comp *iqcomp = NULL; 1872 const struct lpphy_rx_iq_comp *iqcomp = NULL;
1875 struct lpphy_tx_gains nogains, oldgains; 1873 struct lpphy_tx_gains nogains, oldgains;
1876 u16 tmp; 1874 u16 tmp;
@@ -1879,7 +1877,7 @@ static int lpphy_rx_iq_cal(struct b43_wldev *dev, bool noise, bool tx,
1879 memset(&nogains, 0, sizeof(nogains)); 1877 memset(&nogains, 0, sizeof(nogains));
1880 memset(&oldgains, 0, sizeof(oldgains)); 1878 memset(&oldgains, 0, sizeof(oldgains));
1881 1879
1882 if (bus->chip_id == 0x5354) { 1880 if (dev->dev->chip_id == 0x5354) {
1883 for (i = 0; i < ARRAY_SIZE(lpphy_5354_iq_table); i++) { 1881 for (i = 0; i < ARRAY_SIZE(lpphy_5354_iq_table); i++) {
1884 if (lpphy_5354_iq_table[i].chan == lpphy->channel) { 1882 if (lpphy_5354_iq_table[i].chan == lpphy->channel) {
1885 iqcomp = &lpphy_5354_iq_table[i]; 1883 iqcomp = &lpphy_5354_iq_table[i];
@@ -2408,11 +2406,9 @@ static const struct b206x_channel b2063_chantbl[] = {
2408 2406
2409static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev) 2407static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
2410{ 2408{
2411 struct ssb_bus *bus = dev->sdev->bus;
2412
2413 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF); 2409 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
2414 udelay(20); 2410 udelay(20);
2415 if (bus->chip_id == 0x5354) { 2411 if (dev->dev->chip_id == 0x5354) {
2416 b43_radio_write(dev, B2062_N_COMM1, 4); 2412 b43_radio_write(dev, B2062_N_COMM1, 4);
2417 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4); 2413 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
2418 } else { 2414 } else {
@@ -2432,7 +2428,7 @@ static int lpphy_b2062_tune(struct b43_wldev *dev,
2432 unsigned int channel) 2428 unsigned int channel)
2433{ 2429{
2434 struct b43_phy_lp *lpphy = dev->phy.lp; 2430 struct b43_phy_lp *lpphy = dev->phy.lp;
2435 struct ssb_bus *bus = dev->sdev->bus; 2431 struct ssb_bus *bus = dev->dev->sdev->bus;
2436 const struct b206x_channel *chandata = NULL; 2432 const struct b206x_channel *chandata = NULL;
2437 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000; 2433 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2438 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9; 2434 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
@@ -2522,7 +2518,7 @@ static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
2522static int lpphy_b2063_tune(struct b43_wldev *dev, 2518static int lpphy_b2063_tune(struct b43_wldev *dev,
2523 unsigned int channel) 2519 unsigned int channel)
2524{ 2520{
2525 struct ssb_bus *bus = dev->sdev->bus; 2521 struct ssb_bus *bus = dev->dev->sdev->bus;
2526 2522
2527 static const struct b206x_channel *chandata = NULL; 2523 static const struct b206x_channel *chandata = NULL;
2528 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000; 2524 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
@@ -2670,6 +2666,11 @@ static int b43_lpphy_op_init(struct b43_wldev *dev)
2670{ 2666{
2671 int err; 2667 int err;
2672 2668
2669 if (dev->dev->bus_type != B43_BUS_SSB) {
2670 b43err(dev->wl, "LP-PHY is supported only on SSB!\n");
2671 return -EOPNOTSUPP;
2672 }
2673
2673 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs? 2674 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2674 lpphy_baseband_init(dev); 2675 lpphy_baseband_init(dev);
2675 lpphy_radio_init(dev); 2676 lpphy_radio_init(dev);
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 05960ddde24e..1ae1e84cb4d1 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -299,7 +299,7 @@ static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
299static void b43_nphy_tx_power_fix(struct b43_wldev *dev) 299static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
300{ 300{
301 struct b43_phy_n *nphy = dev->phy.n; 301 struct b43_phy_n *nphy = dev->phy.n;
302 struct ssb_sprom *sprom = &(dev->sdev->bus->sprom); 302 struct ssb_sprom *sprom = dev->dev->bus_sprom;
303 303
304 u8 txpi[2], bbmult, i; 304 u8 txpi[2], bbmult, i;
305 u16 tmp, radio_gain, dac_gain; 305 u16 tmp, radio_gain, dac_gain;
@@ -423,16 +423,15 @@ static void b43_radio_init2055_pre(struct b43_wldev *dev)
423static void b43_radio_init2055_post(struct b43_wldev *dev) 423static void b43_radio_init2055_post(struct b43_wldev *dev)
424{ 424{
425 struct b43_phy_n *nphy = dev->phy.n; 425 struct b43_phy_n *nphy = dev->phy.n;
426 struct ssb_sprom *sprom = &(dev->sdev->bus->sprom); 426 struct ssb_sprom *sprom = dev->dev->bus_sprom;
427 struct ssb_boardinfo *binfo = &(dev->sdev->bus->boardinfo);
428 int i; 427 int i;
429 u16 val; 428 u16 val;
430 bool workaround = false; 429 bool workaround = false;
431 430
432 if (sprom->revision < 4) 431 if (sprom->revision < 4)
433 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM && 432 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
434 binfo->type == 0x46D && 433 && dev->dev->board_type == 0x46D
435 binfo->rev >= 0x41); 434 && dev->dev->board_rev >= 0x41);
436 else 435 else
437 workaround = 436 workaround =
438 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS); 437 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
@@ -604,17 +603,33 @@ static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
604/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ 603/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
605static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force) 604static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
606{ 605{
607 u32 tmslow; 606 u32 tmp;
608 607
609 if (dev->phy.type != B43_PHYTYPE_N) 608 if (dev->phy.type != B43_PHYTYPE_N)
610 return; 609 return;
611 610
612 tmslow = ssb_read32(dev->sdev, SSB_TMSLOW); 611 switch (dev->dev->bus_type) {
613 if (force) 612#ifdef CONFIG_B43_BCMA
614 tmslow |= SSB_TMSLOW_FGC; 613 case B43_BUS_BCMA:
615 else 614 tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
616 tmslow &= ~SSB_TMSLOW_FGC; 615 if (force)
617 ssb_write32(dev->sdev, SSB_TMSLOW, tmslow); 616 tmp |= BCMA_IOCTL_FGC;
617 else
618 tmp &= ~BCMA_IOCTL_FGC;
619 bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
620 break;
621#endif
622#ifdef CONFIG_B43_SSB
623 case B43_BUS_SSB:
624 tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
625 if (force)
626 tmp |= SSB_TMSLOW_FGC;
627 else
628 tmp &= ~SSB_TMSLOW_FGC;
629 ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
630 break;
631#endif
632 }
618} 633}
619 634
620/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ 635/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
@@ -959,8 +974,21 @@ static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
959 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); 974 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
960 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); 975 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
961 976
962 ssb_chipco_gpio_control(&dev->sdev->bus->chipco, 0xFC00, 977 switch (dev->dev->bus_type) {
963 0xFC00); 978#ifdef CONFIG_B43_BCMA
979 case B43_BUS_BCMA:
980 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
981 0xFC00, 0xFC00);
982 break;
983#endif
984#ifdef CONFIG_B43_SSB
985 case B43_BUS_SSB:
986 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
987 0xFC00, 0xFC00);
988 break;
989#endif
990 }
991
964 b43_write32(dev, B43_MMIO_MACCTL, 992 b43_write32(dev, B43_MMIO_MACCTL,
965 b43_read32(dev, B43_MMIO_MACCTL) & 993 b43_read32(dev, B43_MMIO_MACCTL) &
966 ~B43_MACCTL_GPOUTSMSK); 994 ~B43_MACCTL_GPOUTSMSK);
@@ -983,7 +1011,7 @@ static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
983{ 1011{
984 u16 tmp; 1012 u16 tmp;
985 1013
986 if (dev->sdev->id.revision == 16) 1014 if (dev->dev->core_rev == 16)
987 b43_mac_suspend(dev); 1015 b43_mac_suspend(dev);
988 1016
989 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); 1017 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
@@ -993,7 +1021,7 @@ static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
993 tmp |= (val & mask); 1021 tmp |= (val & mask);
994 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); 1022 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
995 1023
996 if (dev->sdev->id.revision == 16) 1024 if (dev->dev->core_rev == 16)
997 b43_mac_enable(dev); 1025 b43_mac_enable(dev);
998 1026
999 return tmp; 1027 return tmp;
@@ -1168,7 +1196,7 @@ static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
1168static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev) 1196static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1169{ 1197{
1170 struct b43_phy_n *nphy = dev->phy.n; 1198 struct b43_phy_n *nphy = dev->phy.n;
1171 struct ssb_sprom *sprom = &(dev->sdev->bus->sprom); 1199 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1172 1200
1173 /* PHY rev 0, 1, 2 */ 1201 /* PHY rev 0, 1, 2 */
1174 u8 i, j; 1202 u8 i, j;
@@ -1373,7 +1401,7 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1373/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ 1401/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1374static void b43_nphy_workarounds(struct b43_wldev *dev) 1402static void b43_nphy_workarounds(struct b43_wldev *dev)
1375{ 1403{
1376 struct ssb_bus *bus = dev->sdev->bus; 1404 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1377 struct b43_phy *phy = &dev->phy; 1405 struct b43_phy *phy = &dev->phy;
1378 struct b43_phy_n *nphy = phy->n; 1406 struct b43_phy_n *nphy = phy->n;
1379 1407
@@ -1443,9 +1471,9 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
1443 1471
1444 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */ 1472 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1445 1473
1446 if ((bus->sprom.boardflags2_lo & B43_BFL2_APLL_WAR && 1474 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1447 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || 1475 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1448 (bus->sprom.boardflags2_lo & B43_BFL2_GPLL_WAR && 1476 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1449 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) 1477 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1450 tmp32 = 0x00088888; 1478 tmp32 = 0x00088888;
1451 else 1479 else
@@ -1503,8 +1531,8 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
1503 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 1531 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1504 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 1532 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1505 1533
1506 if (bus->sprom.boardflags2_lo & 0x100 && 1534 if (sprom->boardflags2_lo & 0x100 &&
1507 bus->boardinfo.type == 0x8B) { 1535 dev->dev->board_type == 0x8B) {
1508 delays1[0] = 0x1; 1536 delays1[0] = 0x1;
1509 delays1[5] = 0x14; 1537 delays1[5] = 0x14;
1510 } 1538 }
@@ -3586,7 +3614,7 @@ static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3586 */ 3614 */
3587int b43_phy_initn(struct b43_wldev *dev) 3615int b43_phy_initn(struct b43_wldev *dev)
3588{ 3616{
3589 struct ssb_bus *bus = dev->sdev->bus; 3617 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3590 struct b43_phy *phy = &dev->phy; 3618 struct b43_phy *phy = &dev->phy;
3591 struct b43_phy_n *nphy = phy->n; 3619 struct b43_phy_n *nphy = phy->n;
3592 u8 tx_pwr_state; 3620 u8 tx_pwr_state;
@@ -3599,9 +3627,22 @@ int b43_phy_initn(struct b43_wldev *dev)
3599 bool do_cal = false; 3627 bool do_cal = false;
3600 3628
3601 if ((dev->phy.rev >= 3) && 3629 if ((dev->phy.rev >= 3) &&
3602 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) && 3630 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
3603 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { 3631 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3604 chipco_set32(&dev->sdev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40); 3632 switch (dev->dev->bus_type) {
3633#ifdef CONFIG_B43_BCMA
3634 case B43_BUS_BCMA:
3635 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
3636 BCMA_CC_CHIPCTL, 0x40);
3637 break;
3638#endif
3639#ifdef CONFIG_B43_SSB
3640 case B43_BUS_SSB:
3641 chipco_set32(&dev->dev->sdev->bus->chipco,
3642 SSB_CHIPCO_CHIPCTL, 0x40);
3643 break;
3644#endif
3645 }
3605 } 3646 }
3606 nphy->deaf_count = 0; 3647 nphy->deaf_count = 0;
3607 b43_nphy_tables_init(dev); 3648 b43_nphy_tables_init(dev);
@@ -3639,9 +3680,9 @@ int b43_phy_initn(struct b43_wldev *dev)
3639 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); 3680 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3640 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); 3681 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3641 3682
3642 if (bus->sprom.boardflags2_lo & 0x100 || 3683 if (sprom->boardflags2_lo & 0x100 ||
3643 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && 3684 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
3644 bus->boardinfo.type == 0x8B)) 3685 dev->dev->board_type == 0x8B))
3645 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); 3686 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3646 else 3687 else
3647 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); 3688 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
@@ -4026,11 +4067,24 @@ static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4026/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */ 4067/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4027static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) 4068static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4028{ 4069{
4029 u16 val = on ? 0 : 0x7FFF; 4070 u16 override = on ? 0x0 : 0x7FFF;
4071 u16 core = on ? 0xD : 0x00FD;
4030 4072
4031 if (dev->phy.rev >= 3) 4073 if (dev->phy.rev >= 3) {
4032 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, val); 4074 if (on) {
4033 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, val); 4075 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4076 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4077 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4078 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4079 } else {
4080 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4081 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4082 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4083 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4084 }
4085 } else {
4086 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4087 }
4034} 4088}
4035 4089
4036static int b43_nphy_op_switch_channel(struct b43_wldev *dev, 4090static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
diff --git a/drivers/net/wireless/b43/pio.c b/drivers/net/wireless/b43/pio.c
index 72ab94df7569..44da620d9cc2 100644
--- a/drivers/net/wireless/b43/pio.c
+++ b/drivers/net/wireless/b43/pio.c
@@ -111,7 +111,7 @@ static u16 index_to_pioqueue_base(struct b43_wldev *dev,
111 B43_MMIO_PIO11_BASE5, 111 B43_MMIO_PIO11_BASE5,
112 }; 112 };
113 113
114 if (dev->sdev->id.revision >= 11) { 114 if (dev->dev->core_rev >= 11) {
115 B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11)); 115 B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
116 return bases_rev11[index]; 116 return bases_rev11[index];
117 } 117 }
@@ -121,14 +121,14 @@ static u16 index_to_pioqueue_base(struct b43_wldev *dev,
121 121
122static u16 pio_txqueue_offset(struct b43_wldev *dev) 122static u16 pio_txqueue_offset(struct b43_wldev *dev)
123{ 123{
124 if (dev->sdev->id.revision >= 11) 124 if (dev->dev->core_rev >= 11)
125 return 0x18; 125 return 0x18;
126 return 0; 126 return 0;
127} 127}
128 128
129static u16 pio_rxqueue_offset(struct b43_wldev *dev) 129static u16 pio_rxqueue_offset(struct b43_wldev *dev)
130{ 130{
131 if (dev->sdev->id.revision >= 11) 131 if (dev->dev->core_rev >= 11)
132 return 0x38; 132 return 0x38;
133 return 8; 133 return 8;
134} 134}
@@ -144,7 +144,7 @@ static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev,
144 if (!q) 144 if (!q)
145 return NULL; 145 return NULL;
146 q->dev = dev; 146 q->dev = dev;
147 q->rev = dev->sdev->id.revision; 147 q->rev = dev->dev->core_rev;
148 q->mmio_base = index_to_pioqueue_base(dev, index) + 148 q->mmio_base = index_to_pioqueue_base(dev, index) +
149 pio_txqueue_offset(dev); 149 pio_txqueue_offset(dev);
150 q->index = index; 150 q->index = index;
@@ -178,7 +178,7 @@ static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev,
178 if (!q) 178 if (!q)
179 return NULL; 179 return NULL;
180 q->dev = dev; 180 q->dev = dev;
181 q->rev = dev->sdev->id.revision; 181 q->rev = dev->dev->core_rev;
182 q->mmio_base = index_to_pioqueue_base(dev, index) + 182 q->mmio_base = index_to_pioqueue_base(dev, index) +
183 pio_rxqueue_offset(dev); 183 pio_rxqueue_offset(dev);
184 184
diff --git a/drivers/net/wireless/b43/radio_2055.h b/drivers/net/wireless/b43/radio_2055.h
index d9bfa0f21b72..67f96122f8d8 100644
--- a/drivers/net/wireless/b43/radio_2055.h
+++ b/drivers/net/wireless/b43/radio_2055.h
@@ -251,4 +251,9 @@ struct b43_nphy_channeltab_entry_rev2 {
251void b2055_upload_inittab(struct b43_wldev *dev, 251void b2055_upload_inittab(struct b43_wldev *dev,
252 bool ghz5, bool ignore_uploadflag); 252 bool ghz5, bool ignore_uploadflag);
253 253
254/* Get the NPHY Channel Switch Table entry for a channel.
255 * Returns NULL on failure to find an entry. */
256const struct b43_nphy_channeltab_entry_rev2 *
257b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel);
258
254#endif /* B43_RADIO_2055_H_ */ 259#endif /* B43_RADIO_2055_H_ */
diff --git a/drivers/net/wireless/b43/radio_2056.h b/drivers/net/wireless/b43/radio_2056.h
index d601f6e7e313..d52df6be705a 100644
--- a/drivers/net/wireless/b43/radio_2056.h
+++ b/drivers/net/wireless/b43/radio_2056.h
@@ -1117,4 +1117,9 @@ struct b43_nphy_channeltab_entry_rev3 {
1117void b2056_upload_inittabs(struct b43_wldev *dev, 1117void b2056_upload_inittabs(struct b43_wldev *dev,
1118 bool ghz5, bool ignore_uploadflag); 1118 bool ghz5, bool ignore_uploadflag);
1119 1119
1120/* Get the NPHY Channel Switch Table entry for a channel.
1121 * Returns NULL on failure to find an entry. */
1122const struct b43_nphy_channeltab_entry_rev3 *
1123b43_nphy_get_chantabent_rev3(struct b43_wldev *dev, u16 freq);
1124
1120#endif /* B43_RADIO_2056_H_ */ 1125#endif /* B43_RADIO_2056_H_ */
diff --git a/drivers/net/wireless/b43/radio_2059.c b/drivers/net/wireless/b43/radio_2059.c
new file mode 100644
index 000000000000..f029f6e1f5d1
--- /dev/null
+++ b/drivers/net/wireless/b43/radio_2059.c
@@ -0,0 +1,174 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n 2059 radio device data tables
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
19 Boston, MA 02110-1301, USA.
20
21*/
22
23#include "b43.h"
24#include "radio_2059.h"
25
26#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
27 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
28 r20, r21, r22, r23, r24, r25, r26, r27, r28) \
29 .radio_syn16 = r00, \
30 .radio_syn17 = r01, \
31 .radio_syn22 = r02, \
32 .radio_syn25 = r03, \
33 .radio_syn27 = r04, \
34 .radio_syn28 = r05, \
35 .radio_syn29 = r06, \
36 .radio_syn2c = r07, \
37 .radio_syn2d = r08, \
38 .radio_syn37 = r09, \
39 .radio_syn41 = r10, \
40 .radio_syn43 = r11, \
41 .radio_syn47 = r12, \
42 .radio_syn4a = r13, \
43 .radio_syn58 = r14, \
44 .radio_syn5a = r15, \
45 .radio_syn6a = r16, \
46 .radio_syn6d = r17, \
47 .radio_syn6e = r18, \
48 .radio_syn92 = r19, \
49 .radio_syn98 = r20, \
50 .radio_rxtx4a = r21, \
51 .radio_rxtx58 = r22, \
52 .radio_rxtx5a = r23, \
53 .radio_rxtx6a = r24, \
54 .radio_rxtx6d = r25, \
55 .radio_rxtx6e = r26, \
56 .radio_rxtx92 = r27, \
57 .radio_rxtx98 = r28
58
59#define PHYREGS(r0, r1, r2, r3, r4, r5) \
60 .phy_regs.bw1 = r0, \
61 .phy_regs.bw2 = r1, \
62 .phy_regs.bw3 = r2, \
63 .phy_regs.bw4 = r3, \
64 .phy_regs.bw5 = r4, \
65 .phy_regs.bw6 = r5
66
67static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radio2059[] = {
68 { .freq = 2412,
69 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
70 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
71 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
72 0x00, 0x00, 0x00, 0xf0, 0x00),
73 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
74 },
75 { .freq = 2417,
76 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
77 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
78 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
79 0x00, 0x00, 0x00, 0xf0, 0x00),
80 PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
81 },
82 { .freq = 2422,
83 RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
84 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
85 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
86 0x00, 0x00, 0x00, 0xf0, 0x00),
87 PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
88 },
89 { .freq = 2427,
90 RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
91 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
92 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
93 0x00, 0x00, 0x00, 0xf0, 0x00),
94 PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
95 },
96 { .freq = 2432,
97 RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
98 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
99 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
100 0x00, 0x00, 0x00, 0xf0, 0x00),
101 PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
102 },
103 { .freq = 2437,
104 RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
105 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
106 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
107 0x00, 0x00, 0x00, 0xf0, 0x00),
108 PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
109 },
110 { .freq = 2442,
111 RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
112 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
113 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
114 0x00, 0x00, 0x00, 0xf0, 0x00),
115 PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
116 },
117 { .freq = 2447,
118 RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
119 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
120 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
121 0x00, 0x00, 0x00, 0xf0, 0x00),
122 PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
123 },
124 { .freq = 2452,
125 RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
126 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
127 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
128 0x00, 0x00, 0x00, 0xf0, 0x00),
129 PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
130 },
131 { .freq = 2457,
132 RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
133 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
134 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
135 0x00, 0x00, 0x00, 0xf0, 0x00),
136 PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
137 },
138 { .freq = 2462,
139 RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
140 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
141 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
142 0x00, 0x00, 0x00, 0xf0, 0x00),
143 PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
144 },
145 { .freq = 2467,
146 RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3,
147 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
148 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
149 0x00, 0x00, 0x00, 0xf0, 0x00),
150 PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
151 },
152 { .freq = 2472,
153 RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8,
154 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
155 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
156 0x00, 0x00, 0x00, 0xf0, 0x00),
157 PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
158 },
159};
160
161const struct b43_phy_ht_channeltab_e_radio2059
162*b43_phy_ht_get_channeltab_e_r2059(struct b43_wldev *dev, u16 freq)
163{
164 const struct b43_phy_ht_channeltab_e_radio2059 *e;
165 unsigned int i;
166
167 e = b43_phy_ht_channeltab_radio2059;
168 for (i = 0; i < ARRAY_SIZE(b43_phy_ht_channeltab_radio2059); i++, e++) {
169 if (e->freq == freq)
170 return e;
171 }
172
173 return NULL;
174}
diff --git a/drivers/net/wireless/b43/radio_2059.h b/drivers/net/wireless/b43/radio_2059.h
new file mode 100644
index 000000000000..e4d69e55e9fe
--- /dev/null
+++ b/drivers/net/wireless/b43/radio_2059.h
@@ -0,0 +1,54 @@
1#ifndef B43_RADIO_2059_H_
2#define B43_RADIO_2059_H_
3
4#include <linux/types.h>
5
6#include "phy_ht.h"
7
8#define R2059_SYN 0x000
9#define R2059_TXRX0 0x400
10#define R2059_RXRX1 0x800
11#define R2059_ALL 0xC00
12
13/* Values for various registers uploaded on channel switching */
14struct b43_phy_ht_channeltab_e_radio2059 {
15 /* The channel frequency in MHz */
16 u16 freq;
17 /* Values for radio registers */
18 u8 radio_syn16;
19 u8 radio_syn17;
20 u8 radio_syn22;
21 u8 radio_syn25;
22 u8 radio_syn27;
23 u8 radio_syn28;
24 u8 radio_syn29;
25 u8 radio_syn2c;
26 u8 radio_syn2d;
27 u8 radio_syn37;
28 u8 radio_syn41;
29 u8 radio_syn43;
30 u8 radio_syn47;
31 u8 radio_syn4a;
32 u8 radio_syn58;
33 u8 radio_syn5a;
34 u8 radio_syn6a;
35 u8 radio_syn6d;
36 u8 radio_syn6e;
37 u8 radio_syn92;
38 u8 radio_syn98;
39 u8 radio_rxtx4a;
40 u8 radio_rxtx58;
41 u8 radio_rxtx5a;
42 u8 radio_rxtx6a;
43 u8 radio_rxtx6d;
44 u8 radio_rxtx6e;
45 u8 radio_rxtx92;
46 u8 radio_rxtx98;
47 /* Values for PHY registers */
48 struct b43_phy_ht_channeltab_e_phy phy_regs;
49};
50
51const struct b43_phy_ht_channeltab_e_radio2059
52*b43_phy_ht_get_channeltab_e_r2059(struct b43_wldev *dev, u16 freq);
53
54#endif /* B43_RADIO_2059_H_ */
diff --git a/drivers/net/wireless/b43/rfkill.c b/drivers/net/wireless/b43/rfkill.c
index a617efe38289..59c3afe047af 100644
--- a/drivers/net/wireless/b43/rfkill.c
+++ b/drivers/net/wireless/b43/rfkill.c
@@ -37,17 +37,16 @@ void b43_rfkill_poll(struct ieee80211_hw *hw)
37{ 37{
38 struct b43_wl *wl = hw_to_b43_wl(hw); 38 struct b43_wl *wl = hw_to_b43_wl(hw);
39 struct b43_wldev *dev = wl->current_dev; 39 struct b43_wldev *dev = wl->current_dev;
40 struct ssb_bus *bus = dev->sdev->bus;
41 bool enabled; 40 bool enabled;
42 bool brought_up = false; 41 bool brought_up = false;
43 42
44 mutex_lock(&wl->mutex); 43 mutex_lock(&wl->mutex);
45 if (unlikely(b43_status(dev) < B43_STAT_INITIALIZED)) { 44 if (unlikely(b43_status(dev) < B43_STAT_INITIALIZED)) {
46 if (ssb_bus_powerup(bus, 0)) { 45 if (b43_bus_powerup(dev, 0)) {
47 mutex_unlock(&wl->mutex); 46 mutex_unlock(&wl->mutex);
48 return; 47 return;
49 } 48 }
50 ssb_device_enable(dev->sdev, 0); 49 b43_device_enable(dev, 0);
51 brought_up = true; 50 brought_up = true;
52 } 51 }
53 52
@@ -63,8 +62,8 @@ void b43_rfkill_poll(struct ieee80211_hw *hw)
63 } 62 }
64 63
65 if (brought_up) { 64 if (brought_up) {
66 ssb_device_disable(dev->sdev, 0); 65 b43_device_disable(dev, 0);
67 ssb_bus_may_powerdown(bus); 66 b43_bus_may_powerdown(dev);
68 } 67 }
69 68
70 mutex_unlock(&wl->mutex); 69 mutex_unlock(&wl->mutex);
diff --git a/drivers/net/wireless/b43/sdio.c b/drivers/net/wireless/b43/sdio.c
index 808e25b79703..4fd6775b8c33 100644
--- a/drivers/net/wireless/b43/sdio.c
+++ b/drivers/net/wireless/b43/sdio.c
@@ -66,7 +66,7 @@ static void b43_sdio_interrupt_dispatcher(struct sdio_func *func)
66int b43_sdio_request_irq(struct b43_wldev *dev, 66int b43_sdio_request_irq(struct b43_wldev *dev,
67 void (*handler)(struct b43_wldev *dev)) 67 void (*handler)(struct b43_wldev *dev))
68{ 68{
69 struct ssb_bus *bus = dev->sdev->bus; 69 struct ssb_bus *bus = dev->dev->sdev->bus;
70 struct sdio_func *func = bus->host_sdio; 70 struct sdio_func *func = bus->host_sdio;
71 struct b43_sdio *sdio = sdio_get_drvdata(func); 71 struct b43_sdio *sdio = sdio_get_drvdata(func);
72 int err; 72 int err;
@@ -82,7 +82,7 @@ int b43_sdio_request_irq(struct b43_wldev *dev,
82 82
83void b43_sdio_free_irq(struct b43_wldev *dev) 83void b43_sdio_free_irq(struct b43_wldev *dev)
84{ 84{
85 struct ssb_bus *bus = dev->sdev->bus; 85 struct ssb_bus *bus = dev->dev->sdev->bus;
86 struct sdio_func *func = bus->host_sdio; 86 struct sdio_func *func = bus->host_sdio;
87 struct b43_sdio *sdio = sdio_get_drvdata(func); 87 struct b43_sdio *sdio = sdio_get_drvdata(func);
88 88
@@ -93,8 +93,8 @@ void b43_sdio_free_irq(struct b43_wldev *dev)
93 sdio->irq_handler = NULL; 93 sdio->irq_handler = NULL;
94} 94}
95 95
96static int b43_sdio_probe(struct sdio_func *func, 96static int __devinit b43_sdio_probe(struct sdio_func *func,
97 const struct sdio_device_id *id) 97 const struct sdio_device_id *id)
98{ 98{
99 struct b43_sdio *sdio; 99 struct b43_sdio *sdio;
100 struct sdio_func_tuple *tuple; 100 struct sdio_func_tuple *tuple;
@@ -171,7 +171,7 @@ out:
171 return error; 171 return error;
172} 172}
173 173
174static void b43_sdio_remove(struct sdio_func *func) 174static void __devexit b43_sdio_remove(struct sdio_func *func)
175{ 175{
176 struct b43_sdio *sdio = sdio_get_drvdata(func); 176 struct b43_sdio *sdio = sdio_get_drvdata(func);
177 177
diff --git a/drivers/net/wireless/b43/sysfs.c b/drivers/net/wireless/b43/sysfs.c
index 57af619725c3..f1ae4e05a32c 100644
--- a/drivers/net/wireless/b43/sysfs.c
+++ b/drivers/net/wireless/b43/sysfs.c
@@ -140,7 +140,7 @@ static DEVICE_ATTR(interference, 0644,
140 140
141int b43_sysfs_register(struct b43_wldev *wldev) 141int b43_sysfs_register(struct b43_wldev *wldev)
142{ 142{
143 struct device *dev = wldev->sdev->dev; 143 struct device *dev = wldev->dev->dev;
144 144
145 B43_WARN_ON(b43_status(wldev) != B43_STAT_INITIALIZED); 145 B43_WARN_ON(b43_status(wldev) != B43_STAT_INITIALIZED);
146 146
@@ -149,7 +149,7 @@ int b43_sysfs_register(struct b43_wldev *wldev)
149 149
150void b43_sysfs_unregister(struct b43_wldev *wldev) 150void b43_sysfs_unregister(struct b43_wldev *wldev)
151{ 151{
152 struct device *dev = wldev->sdev->dev; 152 struct device *dev = wldev->dev->dev;
153 153
154 device_remove_file(dev, &dev_attr_interference); 154 device_remove_file(dev, &dev_attr_interference);
155} 155}
diff --git a/drivers/net/wireless/b43/tables_lpphy.c b/drivers/net/wireless/b43/tables_lpphy.c
index 59df3c64af63..6748c5a196e9 100644
--- a/drivers/net/wireless/b43/tables_lpphy.c
+++ b/drivers/net/wireless/b43/tables_lpphy.c
@@ -2304,7 +2304,6 @@ void lpphy_rev0_1_table_init(struct b43_wldev *dev)
2304 2304
2305void lpphy_rev2plus_table_init(struct b43_wldev *dev) 2305void lpphy_rev2plus_table_init(struct b43_wldev *dev)
2306{ 2306{
2307 struct ssb_bus *bus = dev->sdev->bus;
2308 int i; 2307 int i;
2309 2308
2310 B43_WARN_ON(dev->phy.rev < 2); 2309 B43_WARN_ON(dev->phy.rev < 2);
@@ -2341,7 +2340,7 @@ void lpphy_rev2plus_table_init(struct b43_wldev *dev)
2341 b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0), 2340 b43_lptab_write_bulk(dev, B43_LPTAB32(10, 0),
2342 ARRAY_SIZE(lpphy_papd_mult_table), lpphy_papd_mult_table); 2341 ARRAY_SIZE(lpphy_papd_mult_table), lpphy_papd_mult_table);
2343 2342
2344 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) { 2343 if ((dev->dev->chip_id == 0x4325) && (dev->dev->chip_rev == 0)) {
2345 b43_lptab_write_bulk(dev, B43_LPTAB32(13, 0), 2344 b43_lptab_write_bulk(dev, B43_LPTAB32(13, 0),
2346 ARRAY_SIZE(lpphy_a0_gain_idx_table), lpphy_a0_gain_idx_table); 2345 ARRAY_SIZE(lpphy_a0_gain_idx_table), lpphy_a0_gain_idx_table);
2347 b43_lptab_write_bulk(dev, B43_LPTAB16(14, 0), 2346 b43_lptab_write_bulk(dev, B43_LPTAB16(14, 0),
@@ -2416,12 +2415,12 @@ void lpphy_write_gain_table_bulk(struct b43_wldev *dev, int offset, int count,
2416 2415
2417void lpphy_init_tx_gain_table(struct b43_wldev *dev) 2416void lpphy_init_tx_gain_table(struct b43_wldev *dev)
2418{ 2417{
2419 struct ssb_bus *bus = dev->sdev->bus; 2418 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2420 2419
2421 switch (dev->phy.rev) { 2420 switch (dev->phy.rev) {
2422 case 0: 2421 case 0:
2423 if ((bus->sprom.boardflags_hi & B43_BFH_NOPA) || 2422 if ((sprom->boardflags_hi & B43_BFH_NOPA) ||
2424 (bus->sprom.boardflags_lo & B43_BFL_HGPA)) 2423 (sprom->boardflags_lo & B43_BFL_HGPA))
2425 lpphy_write_gain_table_bulk(dev, 0, 128, 2424 lpphy_write_gain_table_bulk(dev, 0, 128,
2426 lpphy_rev0_nopa_tx_gain_table); 2425 lpphy_rev0_nopa_tx_gain_table);
2427 else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 2426 else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
@@ -2432,8 +2431,8 @@ void lpphy_init_tx_gain_table(struct b43_wldev *dev)
2432 lpphy_rev0_5ghz_tx_gain_table); 2431 lpphy_rev0_5ghz_tx_gain_table);
2433 break; 2432 break;
2434 case 1: 2433 case 1:
2435 if ((bus->sprom.boardflags_hi & B43_BFH_NOPA) || 2434 if ((sprom->boardflags_hi & B43_BFH_NOPA) ||
2436 (bus->sprom.boardflags_lo & B43_BFL_HGPA)) 2435 (sprom->boardflags_lo & B43_BFL_HGPA))
2437 lpphy_write_gain_table_bulk(dev, 0, 128, 2436 lpphy_write_gain_table_bulk(dev, 0, 128,
2438 lpphy_rev1_nopa_tx_gain_table); 2437 lpphy_rev1_nopa_tx_gain_table);
2439 else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 2438 else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
@@ -2444,7 +2443,7 @@ void lpphy_init_tx_gain_table(struct b43_wldev *dev)
2444 lpphy_rev1_5ghz_tx_gain_table); 2443 lpphy_rev1_5ghz_tx_gain_table);
2445 break; 2444 break;
2446 default: 2445 default:
2447 if (bus->sprom.boardflags_hi & B43_BFH_NOPA) 2446 if (sprom->boardflags_hi & B43_BFH_NOPA)
2448 lpphy_write_gain_table_bulk(dev, 0, 128, 2447 lpphy_write_gain_table_bulk(dev, 0, 128,
2449 lpphy_rev2_nopa_tx_gain_table); 2448 lpphy_rev2_nopa_tx_gain_table);
2450 else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 2449 else if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
diff --git a/drivers/net/wireless/b43/tables_nphy.h b/drivers/net/wireless/b43/tables_nphy.h
index 18569367ce43..a81696bff0ed 100644
--- a/drivers/net/wireless/b43/tables_nphy.h
+++ b/drivers/net/wireless/b43/tables_nphy.h
@@ -60,16 +60,8 @@ struct nphy_gain_ctl_workaround_entry {
60struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent( 60struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
61 struct b43_wldev *dev, bool ghz5, bool ext_lna); 61 struct b43_wldev *dev, bool ghz5, bool ext_lna);
62 62
63/* Get the NPHY Channel Switch Table entry for a channel.
64 * Returns NULL on failure to find an entry. */
65const struct b43_nphy_channeltab_entry_rev2 *
66b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel);
67const struct b43_nphy_channeltab_entry_rev3 *
68b43_nphy_get_chantabent_rev3(struct b43_wldev *dev, u16 freq);
69
70 63
71/* The N-PHY tables. */ 64/* The N-PHY tables. */
72
73#define B43_NTAB_TYPEMASK 0xF0000000 65#define B43_NTAB_TYPEMASK 0xF0000000
74#define B43_NTAB_8BIT 0x10000000 66#define B43_NTAB_8BIT 0x10000000
75#define B43_NTAB_16BIT 0x20000000 67#define B43_NTAB_16BIT 0x20000000
diff --git a/drivers/net/wireless/b43/tables_phy_ht.c b/drivers/net/wireless/b43/tables_phy_ht.c
new file mode 100644
index 000000000000..603938657b15
--- /dev/null
+++ b/drivers/net/wireless/b43/tables_phy_ht.c
@@ -0,0 +1,750 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n HT-PHY data tables
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
19 Boston, MA 02110-1301, USA.
20
21*/
22
23#include "b43.h"
24#include "tables_phy_ht.h"
25#include "phy_common.h"
26#include "phy_ht.h"
27
28static const u16 b43_httab_0x12[] = {
29 0x0000, 0x0008, 0x000a, 0x0010, 0x0012, 0x0019,
30 0x001a, 0x001c, 0x0080, 0x0088, 0x008a, 0x0090,
31 0x0092, 0x0099, 0x009a, 0x009c, 0x0100, 0x0108,
32 0x010a, 0x0110, 0x0112, 0x0119, 0x011a, 0x011c,
33 0x0180, 0x0188, 0x018a, 0x0190, 0x0192, 0x0199,
34 0x019a, 0x019c, 0x0000, 0x0098, 0x00a0, 0x00a8,
35 0x009a, 0x00a2, 0x00aa, 0x0120, 0x0128, 0x0128,
36 0x0130, 0x0138, 0x0138, 0x0140, 0x0122, 0x012a,
37 0x012a, 0x0132, 0x013a, 0x013a, 0x0142, 0x01a8,
38 0x01b0, 0x01b8, 0x01b0, 0x01b8, 0x01c0, 0x01c8,
39 0x01c0, 0x01c8, 0x01d0, 0x01d0, 0x01d8, 0x01aa,
40 0x01b2, 0x01ba, 0x01b2, 0x01ba, 0x01c2, 0x01ca,
41 0x01c2, 0x01ca, 0x01d2, 0x01d2, 0x01da, 0x0001,
42 0x0002, 0x0004, 0x0009, 0x000c, 0x0011, 0x0014,
43 0x0018, 0x0020, 0x0021, 0x0022, 0x0024, 0x0081,
44 0x0082, 0x0084, 0x0089, 0x008c, 0x0091, 0x0094,
45 0x0098, 0x00a0, 0x00a1, 0x00a2, 0x00a4, 0x0007,
46 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
47 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
48 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
49 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007,
50 0x0007, 0x0007,
51};
52
53static const u16 b43_httab_0x27[] = {
54 0x0009, 0x000e, 0x0011, 0x0014, 0x0017, 0x001a,
55 0x001d, 0x0020, 0x0009, 0x000e, 0x0011, 0x0014,
56 0x0017, 0x001a, 0x001d, 0x0020, 0x0009, 0x000e,
57 0x0011, 0x0014, 0x0017, 0x001a, 0x001d, 0x0020,
58 0x0009, 0x000e, 0x0011, 0x0014, 0x0017, 0x001a,
59 0x001d, 0x0020,
60};
61
62static const u16 b43_httab_0x26[] = {
63 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
64 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
65 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
66 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
67 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
68 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
69 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
70 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
71 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
72 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
73 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
74 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
75 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
77 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
78 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
79 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
80 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
81 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
82 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
83 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
84 0x0000, 0x0000,
85};
86
87static const u32 b43_httab_0x25[] = {
88 0x00000000, 0x00000000, 0x00000000, 0x00000000,
89 0x00000000, 0x00000000, 0x00000000, 0x00000000,
90 0x00000000, 0x00000000, 0x00000000, 0x00000000,
91 0x00000000, 0x00000000, 0x00000000, 0x00000000,
92 0x00000000, 0x00000000, 0x00000000, 0x00000000,
93 0x00000000, 0x00000000, 0x00000000, 0x00000000,
94 0x00000000, 0x00000000, 0x00000000, 0x00000000,
95 0x00000000, 0x00000000, 0x00000000, 0x00000000,
96 0x00000000, 0x00000000, 0x00000000, 0x00000000,
97 0x00000000, 0x00000000, 0x00000000, 0x00000000,
98 0x00000000, 0x00000000, 0x00000000, 0x00000000,
99 0x00000000, 0x00000000, 0x00000000, 0x00000000,
100 0x00000000, 0x00000000, 0x00000000, 0x00000000,
101 0x00000000, 0x00000000, 0x00000000, 0x00000000,
102 0x00000000, 0x00000000, 0x00000000, 0x00000000,
103 0x00000000, 0x00000000, 0x00000000, 0x00000000,
104 0x00000000, 0x00000000, 0x00000000, 0x00000000,
105 0x00000000, 0x00000000, 0x00000000, 0x00000000,
106 0x00000000, 0x00000000, 0x00000000, 0x00000000,
107 0x00000000, 0x00000000, 0x00000000, 0x00000000,
108 0x00000000, 0x00000000, 0x00000000, 0x00000000,
109 0x00000000, 0x00000000, 0x00000000, 0x00000000,
110 0x00000000, 0x00000000, 0x00000000, 0x00000000,
111 0x00000000, 0x00000000, 0x00000000, 0x00000000,
112 0x00000000, 0x00000000, 0x00000000, 0x00000000,
113 0x00000000, 0x00000000, 0x00000000, 0x00000000,
114 0x00000000, 0x00000000, 0x00000000, 0x00000000,
115 0x00000000, 0x00000000, 0x00000000, 0x00000000,
116 0x00000000, 0x00000000, 0x00000000, 0x00000000,
117 0x00000000, 0x00000000, 0x00000000, 0x00000000,
118 0x00000000, 0x00000000, 0x00000000, 0x00000000,
119 0x00000000, 0x00000000, 0x00000000, 0x00000000,
120};
121
122static const u32 b43_httab_0x2f[] = {
123 0x00035700, 0x0002cc9a, 0x00026666, 0x0001581f,
124 0x0001581f, 0x0001581f, 0x0001581f, 0x0001581f,
125 0x0001581f, 0x0001581f, 0x0001581f, 0x00035700,
126 0x0002cc9a, 0x00026666, 0x0001581f, 0x0001581f,
127 0x0001581f, 0x0001581f, 0x0001581f, 0x0001581f,
128 0x0001581f, 0x0001581f,
129};
130
131static const u16 b43_httab_0x1a[] = {
132 0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052,
133 0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e,
134 0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a,
135 0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046,
136 0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040,
137 0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a,
138 0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033,
139 0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b,
140 0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f,
141 0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e,
142 0x000b, 0x0007, 0x0002, 0x00fd,
143};
144
145static const u16 b43_httab_0x1b[] = {
146 0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052,
147 0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e,
148 0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a,
149 0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046,
150 0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040,
151 0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a,
152 0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033,
153 0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b,
154 0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f,
155 0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e,
156 0x000b, 0x0007, 0x0002, 0x00fd,
157};
158
159static const u16 b43_httab_0x1c[] = {
160 0x0055, 0x0054, 0x0054, 0x0053, 0x0052, 0x0052,
161 0x0051, 0x0051, 0x0050, 0x004f, 0x004f, 0x004e,
162 0x004e, 0x004d, 0x004c, 0x004c, 0x004b, 0x004a,
163 0x0049, 0x0049, 0x0048, 0x0047, 0x0046, 0x0046,
164 0x0045, 0x0044, 0x0043, 0x0042, 0x0041, 0x0040,
165 0x0040, 0x003f, 0x003e, 0x003d, 0x003c, 0x003a,
166 0x0039, 0x0038, 0x0037, 0x0036, 0x0035, 0x0033,
167 0x0032, 0x0031, 0x002f, 0x002e, 0x002c, 0x002b,
168 0x0029, 0x0027, 0x0025, 0x0023, 0x0021, 0x001f,
169 0x001d, 0x001a, 0x0018, 0x0015, 0x0012, 0x000e,
170 0x000b, 0x0007, 0x0002, 0x00fd,
171};
172
173static const u32 b43_httab_0x1a_0xc0[] = {
174 0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e,
175 0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037,
176 0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031,
177 0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040,
178 0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039,
179 0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033,
180 0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e,
181 0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037,
182 0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031,
183 0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c,
184 0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e,
185 0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037,
186 0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031,
187 0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c,
188 0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042,
189 0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b,
190 0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034,
191 0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f,
192 0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e,
193 0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037,
194 0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031,
195 0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c,
196 0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027,
197 0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023,
198 0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e,
199 0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037,
200 0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031,
201 0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c,
202 0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027,
203 0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023,
204 0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f,
205 0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c,
206};
207
208static const u32 b43_httab_0x1a_0x140[] = {
209 0x00000000, 0x00000000, 0x00000000, 0x00000000,
210 0x00000000, 0x00000000, 0x00000000, 0x00000000,
211 0x00000000, 0x00000000, 0x00000000, 0x00000000,
212 0x00000000, 0x00000000, 0x00000000, 0x00000000,
213 0x00000000, 0x00000000, 0x00000000, 0x00000000,
214 0x00000000, 0x00000000, 0x00000000, 0x00000000,
215 0x00000000, 0x00000000, 0x00000000, 0x00000000,
216 0x00000000, 0x00000000, 0x00000000, 0x00000000,
217 0x00000000, 0x00000000, 0x00000000, 0x00000000,
218 0x00000000, 0x00000000, 0x00000000, 0x00000000,
219 0x00000000, 0x00000000, 0x00000000, 0x00000000,
220 0x00000000, 0x00000000, 0x00000000, 0x00000000,
221 0x00000000, 0x00000000, 0x00000000, 0x00000000,
222 0x00000000, 0x00000000, 0x00000000, 0x00000000,
223 0x00000000, 0x00000000, 0x00000000, 0x00000000,
224 0x00000000, 0x00000000, 0x00000000, 0x00000000,
225 0x00000000, 0x00000000, 0x00000000, 0x00000000,
226 0x00000000, 0x00000000, 0x00000000, 0x00000000,
227 0x00000000, 0x00000000, 0x00000000, 0x00000000,
228 0x00000000, 0x00000000, 0x00000000, 0x00000000,
229 0x00000000, 0x00000000, 0x00000000, 0x00000000,
230 0x00000000, 0x00000000, 0x00000000, 0x00000000,
231 0x00000000, 0x00000000, 0x00000000, 0x00000000,
232 0x00000000, 0x00000000, 0x00000000, 0x00000000,
233 0x00000000, 0x00000000, 0x00000000, 0x00000000,
234 0x00000000, 0x00000000, 0x00000000, 0x00000000,
235 0x00000000, 0x00000000, 0x00000000, 0x00000000,
236 0x00000000, 0x00000000, 0x00000000, 0x00000000,
237 0x00000000, 0x00000000, 0x00000000, 0x00000000,
238 0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000,
241};
242
243static const u32 b43_httab_0x1b_0x140[] = {
244 0x00000000, 0x00000000, 0x00000000, 0x00000000,
245 0x00000000, 0x00000000, 0x00000000, 0x00000000,
246 0x00000000, 0x00000000, 0x00000000, 0x00000000,
247 0x00000000, 0x00000000, 0x00000000, 0x00000000,
248 0x00000000, 0x00000000, 0x00000000, 0x00000000,
249 0x00000000, 0x00000000, 0x00000000, 0x00000000,
250 0x00000000, 0x00000000, 0x00000000, 0x00000000,
251 0x00000000, 0x00000000, 0x00000000, 0x00000000,
252 0x00000000, 0x00000000, 0x00000000, 0x00000000,
253 0x00000000, 0x00000000, 0x00000000, 0x00000000,
254 0x00000000, 0x00000000, 0x00000000, 0x00000000,
255 0x00000000, 0x00000000, 0x00000000, 0x00000000,
256 0x00000000, 0x00000000, 0x00000000, 0x00000000,
257 0x00000000, 0x00000000, 0x00000000, 0x00000000,
258 0x00000000, 0x00000000, 0x00000000, 0x00000000,
259 0x00000000, 0x00000000, 0x00000000, 0x00000000,
260 0x00000000, 0x00000000, 0x00000000, 0x00000000,
261 0x00000000, 0x00000000, 0x00000000, 0x00000000,
262 0x00000000, 0x00000000, 0x00000000, 0x00000000,
263 0x00000000, 0x00000000, 0x00000000, 0x00000000,
264 0x00000000, 0x00000000, 0x00000000, 0x00000000,
265 0x00000000, 0x00000000, 0x00000000, 0x00000000,
266 0x00000000, 0x00000000, 0x00000000, 0x00000000,
267 0x00000000, 0x00000000, 0x00000000, 0x00000000,
268 0x00000000, 0x00000000, 0x00000000, 0x00000000,
269 0x00000000, 0x00000000, 0x00000000, 0x00000000,
270 0x00000000, 0x00000000, 0x00000000, 0x00000000,
271 0x00000000, 0x00000000, 0x00000000, 0x00000000,
272 0x00000000, 0x00000000, 0x00000000, 0x00000000,
273 0x00000000, 0x00000000, 0x00000000, 0x00000000,
274 0x00000000, 0x00000000, 0x00000000, 0x00000000,
275 0x00000000, 0x00000000, 0x00000000, 0x00000000,
276};
277
278static const u32 b43_httab_0x1c_0x140[] = {
279 0x00000000, 0x00000000, 0x00000000, 0x00000000,
280 0x00000000, 0x00000000, 0x00000000, 0x00000000,
281 0x00000000, 0x00000000, 0x00000000, 0x00000000,
282 0x00000000, 0x00000000, 0x00000000, 0x00000000,
283 0x00000000, 0x00000000, 0x00000000, 0x00000000,
284 0x00000000, 0x00000000, 0x00000000, 0x00000000,
285 0x00000000, 0x00000000, 0x00000000, 0x00000000,
286 0x00000000, 0x00000000, 0x00000000, 0x00000000,
287 0x00000000, 0x00000000, 0x00000000, 0x00000000,
288 0x00000000, 0x00000000, 0x00000000, 0x00000000,
289 0x00000000, 0x00000000, 0x00000000, 0x00000000,
290 0x00000000, 0x00000000, 0x00000000, 0x00000000,
291 0x00000000, 0x00000000, 0x00000000, 0x00000000,
292 0x00000000, 0x00000000, 0x00000000, 0x00000000,
293 0x00000000, 0x00000000, 0x00000000, 0x00000000,
294 0x00000000, 0x00000000, 0x00000000, 0x00000000,
295 0x00000000, 0x00000000, 0x00000000, 0x00000000,
296 0x00000000, 0x00000000, 0x00000000, 0x00000000,
297 0x00000000, 0x00000000, 0x00000000, 0x00000000,
298 0x00000000, 0x00000000, 0x00000000, 0x00000000,
299 0x00000000, 0x00000000, 0x00000000, 0x00000000,
300 0x00000000, 0x00000000, 0x00000000, 0x00000000,
301 0x00000000, 0x00000000, 0x00000000, 0x00000000,
302 0x00000000, 0x00000000, 0x00000000, 0x00000000,
303 0x00000000, 0x00000000, 0x00000000, 0x00000000,
304 0x00000000, 0x00000000, 0x00000000, 0x00000000,
305 0x00000000, 0x00000000, 0x00000000, 0x00000000,
306 0x00000000, 0x00000000, 0x00000000, 0x00000000,
307 0x00000000, 0x00000000, 0x00000000, 0x00000000,
308 0x00000000, 0x00000000, 0x00000000, 0x00000000,
309 0x00000000, 0x00000000, 0x00000000, 0x00000000,
310 0x00000000, 0x00000000, 0x00000000, 0x00000000,
311};
312
313static const u16 b43_httab_0x1a_0x1c0[] = {
314 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
315 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
316 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
317 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
318 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
319 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
320 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
321 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
322 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
323 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
324 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
325 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
326 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
327 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
328 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
329 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
330 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
331 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
332 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
333 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
334 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
335 0x0000, 0x0000,
336};
337
338static const u16 b43_httab_0x1b_0x1c0[] = {
339 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
340 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
341 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
342 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
343 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
344 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
345 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
346 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
347 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
348 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
349 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
350 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
351 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
352 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
353 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
354 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
355 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
356 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
357 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
358 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
359 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
360 0x0000, 0x0000,
361};
362
363static const u16 b43_httab_0x1c_0x1c0[] = {
364 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
365 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
366 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
367 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
368 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
369 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
370 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
371 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
372 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
373 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
374 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
375 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
376 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
377 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
378 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
379 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
380 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
381 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
382 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
383 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
384 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
385 0x0000, 0x0000,
386};
387
388static const u16 b43_httab_0x1a_0x240[] = {
389 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
390 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
391 0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
392 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
393 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
394 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
395 0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e,
396 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
397 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
398 0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc,
399 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
400 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
401 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
402 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
403 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
404 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
405 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
406 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
407 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
408 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
409 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
410 0x01d6, 0x01d6,
411};
412
413static const u16 b43_httab_0x1b_0x240[] = {
414 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
415 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
416 0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
417 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
418 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
419 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
420 0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e,
421 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
422 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
423 0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc,
424 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
425 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
426 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
427 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
428 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
429 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
430 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
431 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
432 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
433 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
434 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
435 0x01d6, 0x01d6,
436};
437
438static const u16 b43_httab_0x1c_0x240[] = {
439 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
440 0x0036, 0x0036, 0x0036, 0x0036, 0x0036, 0x0036,
441 0x0036, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
442 0x002a, 0x002a, 0x002a, 0x002a, 0x002a, 0x002a,
443 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
444 0x001e, 0x001e, 0x001e, 0x001e, 0x001e, 0x001e,
445 0x001e, 0x001e, 0x001e, 0x001e, 0x000e, 0x000e,
446 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
447 0x000e, 0x000e, 0x000e, 0x000e, 0x000e, 0x000e,
448 0x000e, 0x000e, 0x000e, 0x000e, 0x01fc, 0x01fc,
449 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
450 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc, 0x01fc,
451 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
452 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
453 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
454 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee, 0x01ee,
455 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
456 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
457 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
458 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
459 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6, 0x01d6,
460 0x01d6, 0x01d6,
461};
462
463static const u32 b43_httab_0x1f[] = {
464 0x00000000, 0x00000000, 0x00016023, 0x00006028,
465 0x00034036, 0x0003402e, 0x0007203c, 0x0006e037,
466 0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d,
467 0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9,
468 0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9,
469 0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6,
470 0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c,
471 0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b,
472 0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15,
473 0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9,
474 0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87,
475 0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3,
476 0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa,
477 0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff,
478 0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff,
479 0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff,
480};
481
482static const u32 b43_httab_0x21[] = {
483 0x00000000, 0x00000000, 0x00016023, 0x00006028,
484 0x00034036, 0x0003402e, 0x0007203c, 0x0006e037,
485 0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d,
486 0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9,
487 0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9,
488 0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6,
489 0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c,
490 0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b,
491 0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15,
492 0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9,
493 0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87,
494 0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3,
495 0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa,
496 0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff,
497 0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff,
498 0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff,
499};
500
501static const u32 b43_httab_0x23[] = {
502 0x00000000, 0x00000000, 0x00016023, 0x00006028,
503 0x00034036, 0x0003402e, 0x0007203c, 0x0006e037,
504 0x00070030, 0x0009401f, 0x0009a00f, 0x000b600d,
505 0x000c8007, 0x000ce007, 0x00101fff, 0x00121ff9,
506 0x0012e004, 0x0014dffc, 0x0016dff6, 0x0018dfe9,
507 0x001b3fe5, 0x001c5fd0, 0x001ddfc2, 0x001f1fb6,
508 0x00207fa4, 0x00219f8f, 0x0022ff7d, 0x00247f6c,
509 0x0024df5b, 0x00267f4b, 0x0027df3b, 0x0029bf3b,
510 0x002b5f2f, 0x002d3f2e, 0x002f5f2a, 0x002fff15,
511 0x00315f0b, 0x0032defa, 0x0033beeb, 0x0034fed9,
512 0x00353ec5, 0x00361eb0, 0x00363e9b, 0x0036be87,
513 0x0036be70, 0x0038fe67, 0x0044beb2, 0x00513ef3,
514 0x00595f11, 0x00669f3d, 0x0078dfdf, 0x00a143aa,
515 0x01642fff, 0x0162afff, 0x01620fff, 0x0160cfff,
516 0x015f0fff, 0x015dafff, 0x015bcfff, 0x015bcfff,
517 0x015b4fff, 0x015acfff, 0x01590fff, 0x0156cfff,
518};
519
520static const u32 b43_httab_0x20[] = {
521 0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035,
522 0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043,
523 0x07340047, 0x06d2004b, 0x067a004f, 0x06170054,
524 0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a,
525 0x04910070, 0x044c0077, 0x040f007e, 0x03d90085,
526 0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8,
527 0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3,
528 0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a,
529 0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e,
530 0x01720162, 0x015d0177, 0x0149018e, 0x013701a5,
531 0x012601be, 0x011501d8, 0x010601f4, 0x00f70212,
532 0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b,
533 0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348,
534 0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422,
535 0x00750460, 0x006e04a3, 0x006804e9, 0x00620533,
536 0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c,
537};
538
539static const u32 b43_httab_0x22[] = {
540 0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035,
541 0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043,
542 0x07340047, 0x06d2004b, 0x067a004f, 0x06170054,
543 0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a,
544 0x04910070, 0x044c0077, 0x040f007e, 0x03d90085,
545 0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8,
546 0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3,
547 0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a,
548 0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e,
549 0x01720162, 0x015d0177, 0x0149018e, 0x013701a5,
550 0x012601be, 0x011501d8, 0x010601f4, 0x00f70212,
551 0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b,
552 0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348,
553 0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422,
554 0x00750460, 0x006e04a3, 0x006804e9, 0x00620533,
555 0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c,
556};
557
558static const u32 b43_httab_0x24[] = {
559 0x0b5e002d, 0x0ae2002f, 0x0a3b0032, 0x09a70035,
560 0x09220038, 0x08ab003b, 0x081f003f, 0x07a20043,
561 0x07340047, 0x06d2004b, 0x067a004f, 0x06170054,
562 0x05bf0059, 0x0571005e, 0x051e0064, 0x04d3006a,
563 0x04910070, 0x044c0077, 0x040f007e, 0x03d90085,
564 0x03a1008d, 0x036f0095, 0x033d009e, 0x030b00a8,
565 0x02e000b2, 0x02b900bc, 0x029200c7, 0x026d00d3,
566 0x024900e0, 0x022900ed, 0x020a00fb, 0x01ec010a,
567 0x01d20119, 0x01b7012a, 0x019e013c, 0x0188014e,
568 0x01720162, 0x015d0177, 0x0149018e, 0x013701a5,
569 0x012601be, 0x011501d8, 0x010601f4, 0x00f70212,
570 0x00e90231, 0x00dc0253, 0x00d00276, 0x00c4029b,
571 0x00b902c3, 0x00af02ed, 0x00a50319, 0x009c0348,
572 0x0093037a, 0x008b03af, 0x008303e6, 0x007c0422,
573 0x00750460, 0x006e04a3, 0x006804e9, 0x00620533,
574 0x005d0582, 0x005805d6, 0x0053062e, 0x004e068c,
575};
576
577/**************************************************
578 * R/W ops.
579 **************************************************/
580
581u32 b43_httab_read(struct b43_wldev *dev, u32 offset)
582{
583 u32 type, value;
584
585 type = offset & B43_HTTAB_TYPEMASK;
586 offset &= ~B43_HTTAB_TYPEMASK;
587 B43_WARN_ON(offset > 0xFFFF);
588
589 switch (type) {
590 case B43_HTTAB_8BIT:
591 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
592 value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO) & 0xFF;
593 break;
594 case B43_HTTAB_16BIT:
595 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
596 value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO);
597 break;
598 case B43_HTTAB_32BIT:
599 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
600 value = b43_phy_read(dev, B43_PHY_HT_TABLE_DATAHI);
601 value <<= 16;
602 value |= b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO);
603 break;
604 default:
605 B43_WARN_ON(1);
606 value = 0;
607 }
608
609 return value;
610}
611
612void b43_httab_read_bulk(struct b43_wldev *dev, u32 offset,
613 unsigned int nr_elements, void *_data)
614{
615 u32 type;
616 u8 *data = _data;
617 unsigned int i;
618
619 type = offset & B43_HTTAB_TYPEMASK;
620 offset &= ~B43_HTTAB_TYPEMASK;
621 B43_WARN_ON(offset > 0xFFFF);
622
623 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
624
625 for (i = 0; i < nr_elements; i++) {
626 switch (type) {
627 case B43_HTTAB_8BIT:
628 *data = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO) & 0xFF;
629 data++;
630 break;
631 case B43_HTTAB_16BIT:
632 *((u16 *)data) = b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO);
633 data += 2;
634 break;
635 case B43_HTTAB_32BIT:
636 *((u32 *)data) = b43_phy_read(dev, B43_PHY_HT_TABLE_DATAHI);
637 *((u32 *)data) <<= 16;
638 *((u32 *)data) |= b43_phy_read(dev, B43_PHY_HT_TABLE_DATALO);
639 data += 4;
640 break;
641 default:
642 B43_WARN_ON(1);
643 }
644 }
645}
646
647void b43_httab_write(struct b43_wldev *dev, u32 offset, u32 value)
648{
649 u32 type;
650
651 type = offset & B43_HTTAB_TYPEMASK;
652 offset &= 0xFFFF;
653
654 switch (type) {
655 case B43_HTTAB_8BIT:
656 B43_WARN_ON(value & ~0xFF);
657 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
658 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value);
659 break;
660 case B43_HTTAB_16BIT:
661 B43_WARN_ON(value & ~0xFFFF);
662 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
663 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value);
664 break;
665 case B43_HTTAB_32BIT:
666 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
667 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, value >> 16);
668 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value & 0xFFFF);
669 break;
670 default:
671 B43_WARN_ON(1);
672 }
673
674 return;
675}
676
677void b43_httab_write_bulk(struct b43_wldev *dev, u32 offset,
678 unsigned int nr_elements, const void *_data)
679{
680 u32 type, value;
681 const u8 *data = _data;
682 unsigned int i;
683
684 type = offset & B43_HTTAB_TYPEMASK;
685 offset &= ~B43_HTTAB_TYPEMASK;
686 B43_WARN_ON(offset > 0xFFFF);
687
688 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, offset);
689
690 for (i = 0; i < nr_elements; i++) {
691 switch (type) {
692 case B43_HTTAB_8BIT:
693 value = *data;
694 data++;
695 B43_WARN_ON(value & ~0xFF);
696 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value);
697 break;
698 case B43_HTTAB_16BIT:
699 value = *((u16 *)data);
700 data += 2;
701 B43_WARN_ON(value & ~0xFFFF);
702 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, value);
703 break;
704 case B43_HTTAB_32BIT:
705 value = *((u32 *)data);
706 data += 4;
707 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, value >> 16);
708 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO,
709 value & 0xFFFF);
710 break;
711 default:
712 B43_WARN_ON(1);
713 }
714 }
715}
716
717/**************************************************
718 * Tables ops.
719 **************************************************/
720
721#define httab_upload(dev, offset, data) do { \
722 b43_httab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
723 } while (0)
724void b43_phy_ht_tables_init(struct b43_wldev *dev)
725{
726 httab_upload(dev, B43_HTTAB16(0x12, 0), b43_httab_0x12);
727 httab_upload(dev, B43_HTTAB16(0x27, 0), b43_httab_0x27);
728 httab_upload(dev, B43_HTTAB16(0x26, 0), b43_httab_0x26);
729 httab_upload(dev, B43_HTTAB32(0x25, 0), b43_httab_0x25);
730 httab_upload(dev, B43_HTTAB32(0x2f, 0), b43_httab_0x2f);
731 httab_upload(dev, B43_HTTAB16(0x1a, 0), b43_httab_0x1a);
732 httab_upload(dev, B43_HTTAB16(0x1b, 0), b43_httab_0x1b);
733 httab_upload(dev, B43_HTTAB16(0x1c, 0), b43_httab_0x1c);
734 httab_upload(dev, B43_HTTAB32(0x1a, 0x0c0), b43_httab_0x1a_0xc0);
735 httab_upload(dev, B43_HTTAB32(0x1a, 0x140), b43_httab_0x1a_0x140);
736 httab_upload(dev, B43_HTTAB32(0x1b, 0x140), b43_httab_0x1b_0x140);
737 httab_upload(dev, B43_HTTAB32(0x1c, 0x140), b43_httab_0x1c_0x140);
738 httab_upload(dev, B43_HTTAB16(0x1a, 0x1c0), b43_httab_0x1a_0x1c0);
739 httab_upload(dev, B43_HTTAB16(0x1b, 0x1c0), b43_httab_0x1b_0x1c0);
740 httab_upload(dev, B43_HTTAB16(0x1c, 0x1c0), b43_httab_0x1c_0x1c0);
741 httab_upload(dev, B43_HTTAB16(0x1a, 0x240), b43_httab_0x1a_0x240);
742 httab_upload(dev, B43_HTTAB16(0x1b, 0x240), b43_httab_0x1b_0x240);
743 httab_upload(dev, B43_HTTAB16(0x1c, 0x240), b43_httab_0x1c_0x240);
744 httab_upload(dev, B43_HTTAB32(0x1f, 0), b43_httab_0x1f);
745 httab_upload(dev, B43_HTTAB32(0x21, 0), b43_httab_0x21);
746 httab_upload(dev, B43_HTTAB32(0x23, 0), b43_httab_0x23);
747 httab_upload(dev, B43_HTTAB32(0x20, 0), b43_httab_0x20);
748 httab_upload(dev, B43_HTTAB32(0x22, 0), b43_httab_0x22);
749 httab_upload(dev, B43_HTTAB32(0x24, 0), b43_httab_0x24);
750}
diff --git a/drivers/net/wireless/b43/tables_phy_ht.h b/drivers/net/wireless/b43/tables_phy_ht.h
new file mode 100644
index 000000000000..ea3be382c894
--- /dev/null
+++ b/drivers/net/wireless/b43/tables_phy_ht.h
@@ -0,0 +1,22 @@
1#ifndef B43_TABLES_PHY_HT_H_
2#define B43_TABLES_PHY_HT_H_
3
4/* The HT-PHY tables. */
5#define B43_HTTAB_TYPEMASK 0xF0000000
6#define B43_HTTAB_8BIT 0x10000000
7#define B43_HTTAB_16BIT 0x20000000
8#define B43_HTTAB_32BIT 0x30000000
9#define B43_HTTAB8(table, offset) (((table) << 10) | (offset) | B43_HTTAB_8BIT)
10#define B43_HTTAB16(table, offset) (((table) << 10) | (offset) | B43_HTTAB_16BIT)
11#define B43_HTTAB32(table, offset) (((table) << 10) | (offset) | B43_HTTAB_32BIT)
12
13u32 b43_httab_read(struct b43_wldev *dev, u32 offset);
14void b43_httab_read_bulk(struct b43_wldev *dev, u32 offset,
15 unsigned int nr_elements, void *_data);
16void b43_httab_write(struct b43_wldev *dev, u32 offset, u32 value);
17void b43_httab_write_bulk(struct b43_wldev *dev, u32 offset,
18 unsigned int nr_elements, const void *_data);
19
20void b43_phy_ht_tables_init(struct b43_wldev *dev);
21
22#endif /* B43_TABLES_PHY_HT_H_ */
diff --git a/drivers/net/wireless/b43/tables_phy_lcn.c b/drivers/net/wireless/b43/tables_phy_lcn.c
new file mode 100644
index 000000000000..40c1d0915dd3
--- /dev/null
+++ b/drivers/net/wireless/b43/tables_phy_lcn.c
@@ -0,0 +1,34 @@
1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n LCN-PHY data tables
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; see the file COPYING. If not, write to
18 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
19 Boston, MA 02110-1301, USA.
20
21*/
22
23#include "b43.h"
24#include "tables_phy_lcn.h"
25#include "phy_common.h"
26#include "phy_lcn.h"
27
28/**************************************************
29 * Tables ops.
30 **************************************************/
31
32void b43_phy_lcn_tables_init(struct b43_wldev *dev)
33{
34}
diff --git a/drivers/net/wireless/b43/tables_phy_lcn.h b/drivers/net/wireless/b43/tables_phy_lcn.h
new file mode 100644
index 000000000000..5e31b15b81ec
--- /dev/null
+++ b/drivers/net/wireless/b43/tables_phy_lcn.h
@@ -0,0 +1,6 @@
1#ifndef B43_TABLES_PHY_LCN_H_
2#define B43_TABLES_PHY_LCN_H_
3
4void b43_phy_lcn_tables_init(struct b43_wldev *dev);
5
6#endif /* B43_TABLES_PHY_LCN_H_ */
diff --git a/drivers/net/wireless/b43/wa.c b/drivers/net/wireless/b43/wa.c
index 8f4db448ec33..5d00d0eaf2e7 100644
--- a/drivers/net/wireless/b43/wa.c
+++ b/drivers/net/wireless/b43/wa.c
@@ -458,17 +458,15 @@ static void b43_wa_rssi_adc(struct b43_wldev *dev)
458 458
459static void b43_wa_boards_a(struct b43_wldev *dev) 459static void b43_wa_boards_a(struct b43_wldev *dev)
460{ 460{
461 struct ssb_bus *bus = dev->sdev->bus; 461 if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM &&
462 462 dev->dev->board_type == SSB_BOARD_BU4306 &&
463 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM && 463 dev->dev->board_rev < 0x30) {
464 bus->boardinfo.type == SSB_BOARD_BU4306 &&
465 bus->boardinfo.rev < 0x30) {
466 b43_phy_write(dev, 0x0010, 0xE000); 464 b43_phy_write(dev, 0x0010, 0xE000);
467 b43_phy_write(dev, 0x0013, 0x0140); 465 b43_phy_write(dev, 0x0013, 0x0140);
468 b43_phy_write(dev, 0x0014, 0x0280); 466 b43_phy_write(dev, 0x0014, 0x0280);
469 } else { 467 } else {
470 if (bus->boardinfo.type == SSB_BOARD_MP4318 && 468 if (dev->dev->board_type == SSB_BOARD_MP4318 &&
471 bus->boardinfo.rev < 0x20) { 469 dev->dev->board_rev < 0x20) {
472 b43_phy_write(dev, 0x0013, 0x0210); 470 b43_phy_write(dev, 0x0013, 0x0210);
473 b43_phy_write(dev, 0x0014, 0x0840); 471 b43_phy_write(dev, 0x0014, 0x0840);
474 } else { 472 } else {
@@ -486,19 +484,19 @@ static void b43_wa_boards_a(struct b43_wldev *dev)
486 484
487static void b43_wa_boards_g(struct b43_wldev *dev) 485static void b43_wa_boards_g(struct b43_wldev *dev)
488{ 486{
489 struct ssb_bus *bus = dev->sdev->bus; 487 struct ssb_sprom *sprom = dev->dev->bus_sprom;
490 struct b43_phy *phy = &dev->phy; 488 struct b43_phy *phy = &dev->phy;
491 489
492 if (bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM || 490 if (dev->dev->board_vendor != SSB_BOARDVENDOR_BCM ||
493 bus->boardinfo.type != SSB_BOARD_BU4306 || 491 dev->dev->board_type != SSB_BOARD_BU4306 ||
494 bus->boardinfo.rev != 0x17) { 492 dev->dev->board_rev != 0x17) {
495 if (phy->rev < 2) { 493 if (phy->rev < 2) {
496 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002); 494 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);
497 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001); 495 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);
498 } else { 496 } else {
499 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002); 497 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);
500 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001); 498 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);
501 if ((bus->sprom.boardflags_lo & B43_BFL_EXTLNA) && 499 if ((sprom->boardflags_lo & B43_BFL_EXTLNA) &&
502 (phy->rev >= 7)) { 500 (phy->rev >= 7)) {
503 b43_phy_mask(dev, B43_PHY_EXTG(0x11), 0xF7FF); 501 b43_phy_mask(dev, B43_PHY_EXTG(0x11), 0xF7FF);
504 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001); 502 b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);
@@ -510,7 +508,7 @@ static void b43_wa_boards_g(struct b43_wldev *dev)
510 } 508 }
511 } 509 }
512 } 510 }
513 if (bus->sprom.boardflags_lo & B43_BFL_FEM) { 511 if (sprom->boardflags_lo & B43_BFL_FEM) {
514 b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120); 512 b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);
515 b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480); 513 b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);
516 } 514 }
diff --git a/drivers/net/wireless/b43/xmit.c b/drivers/net/wireless/b43/xmit.c
index c8f99aebe01f..82bcf7595139 100644
--- a/drivers/net/wireless/b43/xmit.c
+++ b/drivers/net/wireless/b43/xmit.c
@@ -323,8 +323,7 @@ int b43_generate_txhdr(struct b43_wldev *dev,
323 /* we give the phase1key and iv16 here, the key is stored in 323 /* we give the phase1key and iv16 here, the key is stored in
324 * shm. With that the hardware can do phase 2 and encryption. 324 * shm. With that the hardware can do phase 2 and encryption.
325 */ 325 */
326 ieee80211_get_tkip_key(info->control.hw_key, skb_frag, 326 ieee80211_get_tkip_p1k(info->control.hw_key, skb_frag, phase1key);
327 IEEE80211_TKIP_P1_KEY, (u8*)phase1key);
328 /* phase1key is in host endian. Copy to little-endian txhdr->iv. */ 327 /* phase1key is in host endian. Copy to little-endian txhdr->iv. */
329 for (i = 0; i < 5; i++) { 328 for (i = 0; i < 5; i++) {
330 txhdr->iv[i * 2 + 0] = phase1key[i]; 329 txhdr->iv[i * 2 + 0] = phase1key[i];
@@ -547,7 +546,7 @@ static s8 b43_rssi_postprocess(struct b43_wldev *dev,
547 else 546 else
548 tmp -= 3; 547 tmp -= 3;
549 } else { 548 } else {
550 if (dev->sdev->bus->sprom. 549 if (dev->dev->bus_sprom->
551 boardflags_lo & B43_BFL_RSSI) { 550 boardflags_lo & B43_BFL_RSSI) {
552 if (in_rssi > 63) 551 if (in_rssi > 63)
553 in_rssi = 63; 552 in_rssi = 63;
diff --git a/drivers/net/wireless/b43legacy/b43legacy.h b/drivers/net/wireless/b43legacy/b43legacy.h
index 23583be1ee0b..17a130d18dc9 100644
--- a/drivers/net/wireless/b43legacy/b43legacy.h
+++ b/drivers/net/wireless/b43legacy/b43legacy.h
@@ -532,6 +532,8 @@ struct b43legacy_dma {
532 532
533 struct b43legacy_dmaring *rx_ring0; 533 struct b43legacy_dmaring *rx_ring0;
534 struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */ 534 struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
535
536 u32 translation; /* Routing bits */
535}; 537};
536 538
537/* Data structures for PIO transmission, per 80211 core. */ 539/* Data structures for PIO transmission, per 80211 core. */
diff --git a/drivers/net/wireless/b43legacy/dma.c b/drivers/net/wireless/b43legacy/dma.c
index e03e01d0bc35..704ee62101bd 100644
--- a/drivers/net/wireless/b43legacy/dma.c
+++ b/drivers/net/wireless/b43legacy/dma.c
@@ -73,7 +73,7 @@ static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
73 addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK); 73 addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
74 addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK) 74 addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
75 >> SSB_DMA_TRANSLATION_SHIFT; 75 >> SSB_DMA_TRANSLATION_SHIFT;
76 addr |= ssb_dma_translation(ring->dev->dev); 76 addr |= ring->dev->dma.translation;
77 ctl = (bufsize - ring->frameoffset) 77 ctl = (bufsize - ring->frameoffset)
78 & B43legacy_DMA32_DCTL_BYTECNT; 78 & B43legacy_DMA32_DCTL_BYTECNT;
79 if (slot == ring->nr_slots - 1) 79 if (slot == ring->nr_slots - 1)
@@ -175,7 +175,7 @@ static void op64_fill_descriptor(struct b43legacy_dmaring *ring,
175 addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK); 175 addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
176 addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK) 176 addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
177 >> SSB_DMA_TRANSLATION_SHIFT; 177 >> SSB_DMA_TRANSLATION_SHIFT;
178 addrhi |= ssb_dma_translation(ring->dev->dev); 178 addrhi |= ring->dev->dma.translation;
179 if (slot == ring->nr_slots - 1) 179 if (slot == ring->nr_slots - 1)
180 ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND; 180 ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND;
181 if (start) 181 if (start)
@@ -709,7 +709,7 @@ static int dmacontroller_setup(struct b43legacy_dmaring *ring)
709 int err = 0; 709 int err = 0;
710 u32 value; 710 u32 value;
711 u32 addrext; 711 u32 addrext;
712 u32 trans = ssb_dma_translation(ring->dev->dev); 712 u32 trans = ring->dev->dma.translation;
713 713
714 if (ring->tx) { 714 if (ring->tx) {
715 if (ring->type == B43legacy_DMA_64BIT) { 715 if (ring->type == B43legacy_DMA_64BIT) {
@@ -817,14 +817,13 @@ static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
817 817
818static void free_all_descbuffers(struct b43legacy_dmaring *ring) 818static void free_all_descbuffers(struct b43legacy_dmaring *ring)
819{ 819{
820 struct b43legacy_dmadesc_generic *desc;
821 struct b43legacy_dmadesc_meta *meta; 820 struct b43legacy_dmadesc_meta *meta;
822 int i; 821 int i;
823 822
824 if (!ring->used_slots) 823 if (!ring->used_slots)
825 return; 824 return;
826 for (i = 0; i < ring->nr_slots; i++) { 825 for (i = 0; i < ring->nr_slots; i++) {
827 desc = ring->ops->idx2desc(ring, i, &meta); 826 ring->ops->idx2desc(ring, i, &meta);
828 827
829 if (!meta->skb) { 828 if (!meta->skb) {
830 B43legacy_WARN_ON(!ring->tx); 829 B43legacy_WARN_ON(!ring->tx);
@@ -1094,6 +1093,7 @@ int b43legacy_dma_init(struct b43legacy_wldev *dev)
1094 return -EOPNOTSUPP; 1093 return -EOPNOTSUPP;
1095#endif 1094#endif
1096 } 1095 }
1096 dma->translation = ssb_dma_translation(dev->dev);
1097 1097
1098 err = -ENOMEM; 1098 err = -ENOMEM;
1099 /* setup TX DMA channels. */ 1099 /* setup TX DMA channels. */
@@ -1371,10 +1371,8 @@ int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1371 struct sk_buff *skb) 1371 struct sk_buff *skb)
1372{ 1372{
1373 struct b43legacy_dmaring *ring; 1373 struct b43legacy_dmaring *ring;
1374 struct ieee80211_hdr *hdr;
1375 int err = 0; 1374 int err = 0;
1376 unsigned long flags; 1375 unsigned long flags;
1377 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1378 1376
1379 ring = priority_to_txring(dev, skb_get_queue_mapping(skb)); 1377 ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1380 spin_lock_irqsave(&ring->lock, flags); 1378 spin_lock_irqsave(&ring->lock, flags);
@@ -1401,8 +1399,6 @@ int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1401 1399
1402 /* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing 1400 /* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing
1403 * into the skb data or cb now. */ 1401 * into the skb data or cb now. */
1404 hdr = NULL;
1405 info = NULL;
1406 err = dma_tx_fragment(ring, &skb); 1402 err = dma_tx_fragment(ring, &skb);
1407 if (unlikely(err == -ENOKEY)) { 1403 if (unlikely(err == -ENOKEY)) {
1408 /* Drop this packet, as we don't have the encryption key 1404 /* Drop this packet, as we don't have the encryption key
@@ -1435,7 +1431,6 @@ void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1435{ 1431{
1436 const struct b43legacy_dma_ops *ops; 1432 const struct b43legacy_dma_ops *ops;
1437 struct b43legacy_dmaring *ring; 1433 struct b43legacy_dmaring *ring;
1438 struct b43legacy_dmadesc_generic *desc;
1439 struct b43legacy_dmadesc_meta *meta; 1434 struct b43legacy_dmadesc_meta *meta;
1440 int retry_limit; 1435 int retry_limit;
1441 int slot; 1436 int slot;
@@ -1450,7 +1445,7 @@ void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1450 ops = ring->ops; 1445 ops = ring->ops;
1451 while (1) { 1446 while (1) {
1452 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); 1447 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1453 desc = ops->idx2desc(ring, slot, &meta); 1448 ops->idx2desc(ring, slot, &meta);
1454 1449
1455 if (meta->skb) 1450 if (meta->skb)
1456 unmap_descbuffer(ring, meta->dmaaddr, 1451 unmap_descbuffer(ring, meta->dmaaddr,
diff --git a/drivers/net/wireless/b43legacy/main.c b/drivers/net/wireless/b43legacy/main.c
index 1ab8861dd43a..d6db6c17da4f 100644
--- a/drivers/net/wireless/b43legacy/main.c
+++ b/drivers/net/wireless/b43legacy/main.c
@@ -1564,10 +1564,10 @@ static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1564 struct b43legacy_firmware *fw = &dev->fw; 1564 struct b43legacy_firmware *fw = &dev->fw;
1565 const u8 rev = dev->dev->id.revision; 1565 const u8 rev = dev->dev->id.revision;
1566 const char *filename; 1566 const char *filename;
1567 u32 tmshigh;
1568 int err; 1567 int err;
1569 1568
1570 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); 1569 /* do dummy read */
1570 ssb_read32(dev->dev, SSB_TMSHIGH);
1571 if (!fw->ucode) { 1571 if (!fw->ucode) {
1572 if (rev == 2) 1572 if (rev == 2)
1573 filename = "ucode2"; 1573 filename = "ucode2";
@@ -2634,11 +2634,9 @@ static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2634 unsigned long flags; 2634 unsigned long flags;
2635 unsigned int new_phymode = 0xFFFF; 2635 unsigned int new_phymode = 0xFFFF;
2636 int antenna_tx; 2636 int antenna_tx;
2637 int antenna_rx;
2638 int err = 0; 2637 int err = 0;
2639 2638
2640 antenna_tx = B43legacy_ANTENNA_DEFAULT; 2639 antenna_tx = B43legacy_ANTENNA_DEFAULT;
2641 antenna_rx = B43legacy_ANTENNA_DEFAULT;
2642 2640
2643 mutex_lock(&wl->mutex); 2641 mutex_lock(&wl->mutex);
2644 dev = wl->current_dev; 2642 dev = wl->current_dev;
@@ -2775,14 +2773,12 @@ static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2775{ 2773{
2776 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw); 2774 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2777 struct b43legacy_wldev *dev; 2775 struct b43legacy_wldev *dev;
2778 struct b43legacy_phy *phy;
2779 unsigned long flags; 2776 unsigned long flags;
2780 2777
2781 mutex_lock(&wl->mutex); 2778 mutex_lock(&wl->mutex);
2782 B43legacy_WARN_ON(wl->vif != vif); 2779 B43legacy_WARN_ON(wl->vif != vif);
2783 2780
2784 dev = wl->current_dev; 2781 dev = wl->current_dev;
2785 phy = &dev->phy;
2786 2782
2787 /* Disable IRQs while reconfiguring the device. 2783 /* Disable IRQs while reconfiguring the device.
2788 * This makes it possible to drop the spinlock throughout 2784 * This makes it possible to drop the spinlock throughout
@@ -2974,7 +2970,7 @@ static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2974 break; 2970 break;
2975 default: 2971 default:
2976 unsupported = 1; 2972 unsupported = 1;
2977 }; 2973 }
2978 if (unsupported) { 2974 if (unsupported) {
2979 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY " 2975 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2980 "(Analog %u, Type %u, Revision %u)\n", 2976 "(Analog %u, Type %u, Revision %u)\n",
diff --git a/drivers/net/wireless/b43legacy/xmit.c b/drivers/net/wireless/b43legacy/xmit.c
index 3a95541708a6..6c174f38ca3c 100644
--- a/drivers/net/wireless/b43legacy/xmit.c
+++ b/drivers/net/wireless/b43legacy/xmit.c
@@ -321,11 +321,9 @@ static int generate_txhdr_fw3(struct b43legacy_wldev *dev,
321 struct ieee80211_hdr *hdr; 321 struct ieee80211_hdr *hdr;
322 int rts_rate; 322 int rts_rate;
323 int rts_rate_fb; 323 int rts_rate_fb;
324 int rts_rate_ofdm;
325 int rts_rate_fb_ofdm; 324 int rts_rate_fb_ofdm;
326 325
327 rts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info)->hw_value; 326 rts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info)->hw_value;
328 rts_rate_ofdm = b43legacy_is_ofdm_rate(rts_rate);
329 rts_rate_fb = b43legacy_calc_fallback_rate(rts_rate); 327 rts_rate_fb = b43legacy_calc_fallback_rate(rts_rate);
330 rts_rate_fb_ofdm = b43legacy_is_ofdm_rate(rts_rate_fb); 328 rts_rate_fb_ofdm = b43legacy_is_ofdm_rate(rts_rate_fb);
331 if (rts_rate_fb_ofdm) 329 if (rts_rate_fb_ofdm)
diff --git a/drivers/net/wireless/hostap/hostap_wlan.h b/drivers/net/wireless/hostap/hostap_wlan.h
index 88dc6a52bdf1..7bb0b4b3f2cb 100644
--- a/drivers/net/wireless/hostap/hostap_wlan.h
+++ b/drivers/net/wireless/hostap/hostap_wlan.h
@@ -1,6 +1,7 @@
1#ifndef HOSTAP_WLAN_H 1#ifndef HOSTAP_WLAN_H
2#define HOSTAP_WLAN_H 2#define HOSTAP_WLAN_H
3 3
4#include <linux/interrupt.h>
4#include <linux/wireless.h> 5#include <linux/wireless.h>
5#include <linux/netdevice.h> 6#include <linux/netdevice.h>
6#include <linux/mutex.h> 7#include <linux/mutex.h>
diff --git a/drivers/net/wireless/ipw2x00/ipw2100.c b/drivers/net/wireless/ipw2x00/ipw2100.c
index 44307753587d..3774dd034746 100644
--- a/drivers/net/wireless/ipw2x00/ipw2100.c
+++ b/drivers/net/wireless/ipw2x00/ipw2100.c
@@ -287,7 +287,7 @@ static const char *command_types[] = {
287 "unused", /* HOST_INTERRUPT_COALESCING */ 287 "unused", /* HOST_INTERRUPT_COALESCING */
288 "undefined", 288 "undefined",
289 "CARD_DISABLE_PHY_OFF", 289 "CARD_DISABLE_PHY_OFF",
290 "MSDU_TX_RATES" "undefined", 290 "MSDU_TX_RATES",
291 "undefined", 291 "undefined",
292 "SET_STATION_STAT_BITS", 292 "SET_STATION_STAT_BITS",
293 "CLEAR_STATIONS_STAT_BITS", 293 "CLEAR_STATIONS_STAT_BITS",
diff --git a/drivers/net/wireless/ipw2x00/ipw2200.h b/drivers/net/wireless/ipw2x00/ipw2200.h
index 91795b5a93c5..ecb561d7a7a0 100644
--- a/drivers/net/wireless/ipw2x00/ipw2200.h
+++ b/drivers/net/wireless/ipw2x00/ipw2200.h
@@ -32,6 +32,7 @@
32#include <linux/module.h> 32#include <linux/module.h>
33#include <linux/moduleparam.h> 33#include <linux/moduleparam.h>
34#include <linux/init.h> 34#include <linux/init.h>
35#include <linux/interrupt.h>
35#include <linux/mutex.h> 36#include <linux/mutex.h>
36 37
37#include <linux/pci.h> 38#include <linux/pci.h>
diff --git a/drivers/net/wireless/ipw2x00/libipw_rx.c b/drivers/net/wireless/ipw2x00/libipw_rx.c
index e5ad76cd77da..32a9966c3bf6 100644
--- a/drivers/net/wireless/ipw2x00/libipw_rx.c
+++ b/drivers/net/wireless/ipw2x00/libipw_rx.c
@@ -442,7 +442,7 @@ int libipw_rx(struct libipw_device *ieee, struct sk_buff *skb,
442 * 802.11, but makes it easier to use different keys with 442 * 802.11, but makes it easier to use different keys with
443 * stations that do not support WEP key mapping). */ 443 * stations that do not support WEP key mapping). */
444 444
445 if (!(hdr->addr1[0] & 0x01) || local->bcrx_sta_key) 445 if (is_unicast_ether_addr(hdr->addr1) || local->bcrx_sta_key)
446 (void)hostap_handle_sta_crypto(local, hdr, &crypt, 446 (void)hostap_handle_sta_crypto(local, hdr, &crypt,
447 &sta); 447 &sta);
448#endif 448#endif
@@ -772,7 +772,7 @@ int libipw_rx(struct libipw_device *ieee, struct sk_buff *skb,
772 772
773#ifdef NOT_YET 773#ifdef NOT_YET
774 if (ieee->iw_mode == IW_MODE_MASTER && !wds && ieee->ap->bridge_packets) { 774 if (ieee->iw_mode == IW_MODE_MASTER && !wds && ieee->ap->bridge_packets) {
775 if (dst[0] & 0x01) { 775 if (is_multicast_ether_addr(dst)) {
776 /* copy multicast frame both to the higher layers and 776 /* copy multicast frame both to the higher layers and
777 * to the wireless media */ 777 * to the wireless media */
778 ieee->ap->bridged_multicast++; 778 ieee->ap->bridged_multicast++;
diff --git a/drivers/net/wireless/ipw2x00/libipw_wx.c b/drivers/net/wireless/ipw2x00/libipw_wx.c
index d7bd6cf00a81..6623e5052254 100644
--- a/drivers/net/wireless/ipw2x00/libipw_wx.c
+++ b/drivers/net/wireless/ipw2x00/libipw_wx.c
@@ -30,6 +30,7 @@
30 30
31******************************************************************************/ 31******************************************************************************/
32 32
33#include <linux/hardirq.h>
33#include <linux/kmod.h> 34#include <linux/kmod.h>
34#include <linux/slab.h> 35#include <linux/slab.h>
35#include <linux/module.h> 36#include <linux/module.h>
diff --git a/drivers/net/wireless/iwlegacy/iwl-3945.c b/drivers/net/wireless/iwlegacy/iwl-3945.c
index d096dc28204d..dab67a12d73b 100644
--- a/drivers/net/wireless/iwlegacy/iwl-3945.c
+++ b/drivers/net/wireless/iwlegacy/iwl-3945.c
@@ -408,7 +408,6 @@ void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
408#ifdef CONFIG_IWLWIFI_LEGACY_DEBUGFS 408#ifdef CONFIG_IWLWIFI_LEGACY_DEBUGFS
409 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw); 409 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
410#endif 410#endif
411 iwl_legacy_recover_from_statistics(priv, pkt);
412 411
413 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics)); 412 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
414} 413}
@@ -2640,7 +2639,6 @@ static struct iwl_lib_ops iwl3945_lib = {
2640 .txq_free_tfd = iwl3945_hw_txq_free_tfd, 2639 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2641 .txq_init = iwl3945_hw_tx_queue_init, 2640 .txq_init = iwl3945_hw_tx_queue_init,
2642 .load_ucode = iwl3945_load_bsm, 2641 .load_ucode = iwl3945_load_bsm,
2643 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2644 .dump_nic_error_log = iwl3945_dump_nic_error_log, 2642 .dump_nic_error_log = iwl3945_dump_nic_error_log,
2645 .apm_ops = { 2643 .apm_ops = {
2646 .init = iwl3945_apm_init, 2644 .init = iwl3945_apm_init,
@@ -2698,9 +2696,7 @@ static struct iwl_base_params iwl3945_base_params = {
2698 .set_l0s = false, 2696 .set_l0s = false,
2699 .use_bsm = true, 2697 .use_bsm = true,
2700 .led_compensation = 64, 2698 .led_compensation = 64,
2701 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
2702 .wd_timeout = IWL_DEF_WD_TIMEOUT, 2699 .wd_timeout = IWL_DEF_WD_TIMEOUT,
2703 .max_event_log_size = 512,
2704}; 2700};
2705 2701
2706static struct iwl_cfg iwl3945_bg_cfg = { 2702static struct iwl_cfg iwl3945_bg_cfg = {
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-lib.c b/drivers/net/wireless/iwlegacy/iwl-4965-lib.c
index a7a4739880dc..2be6d9e3b019 100644
--- a/drivers/net/wireless/iwlegacy/iwl-4965-lib.c
+++ b/drivers/net/wireless/iwlegacy/iwl-4965-lib.c
@@ -694,47 +694,6 @@ void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
694 sizeof(struct iwl_rx_phy_res)); 694 sizeof(struct iwl_rx_phy_res));
695} 695}
696 696
697static int iwl4965_get_single_channel_for_scan(struct iwl_priv *priv,
698 struct ieee80211_vif *vif,
699 enum ieee80211_band band,
700 struct iwl_scan_channel *scan_ch)
701{
702 const struct ieee80211_supported_band *sband;
703 u16 passive_dwell = 0;
704 u16 active_dwell = 0;
705 int added = 0;
706 u16 channel = 0;
707
708 sband = iwl_get_hw_mode(priv, band);
709 if (!sband) {
710 IWL_ERR(priv, "invalid band\n");
711 return added;
712 }
713
714 active_dwell = iwl_legacy_get_active_dwell_time(priv, band, 0);
715 passive_dwell = iwl_legacy_get_passive_dwell_time(priv, band, vif);
716
717 if (passive_dwell <= active_dwell)
718 passive_dwell = active_dwell + 1;
719
720 channel = iwl_legacy_get_single_channel_number(priv, band);
721 if (channel) {
722 scan_ch->channel = cpu_to_le16(channel);
723 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
724 scan_ch->active_dwell = cpu_to_le16(active_dwell);
725 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
726 /* Set txpower levels to defaults */
727 scan_ch->dsp_atten = 110;
728 if (band == IEEE80211_BAND_5GHZ)
729 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
730 else
731 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
732 added++;
733 } else
734 IWL_ERR(priv, "no valid channel found\n");
735 return added;
736}
737
738static int iwl4965_get_channels_for_scan(struct iwl_priv *priv, 697static int iwl4965_get_channels_for_scan(struct iwl_priv *priv,
739 struct ieee80211_vif *vif, 698 struct ieee80211_vif *vif,
740 enum ieee80211_band band, 699 enum ieee80211_band band,
@@ -858,16 +817,13 @@ int iwl4965_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
858 scan->quiet_time = IWL_ACTIVE_QUIET_TIME; 817 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
859 818
860 if (iwl_legacy_is_any_associated(priv)) { 819 if (iwl_legacy_is_any_associated(priv)) {
861 u16 interval = 0; 820 u16 interval;
862 u32 extra; 821 u32 extra;
863 u32 suspend_time = 100; 822 u32 suspend_time = 100;
864 u32 scan_suspend_time = 100; 823 u32 scan_suspend_time = 100;
865 824
866 IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); 825 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
867 if (priv->is_internal_short_scan) 826 interval = vif->bss_conf.beacon_int;
868 interval = 0;
869 else
870 interval = vif->bss_conf.beacon_int;
871 827
872 scan->suspend_time = 0; 828 scan->suspend_time = 0;
873 scan->max_out_time = cpu_to_le32(200 * 1024); 829 scan->max_out_time = cpu_to_le32(200 * 1024);
@@ -882,9 +838,7 @@ int iwl4965_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
882 scan_suspend_time, interval); 838 scan_suspend_time, interval);
883 } 839 }
884 840
885 if (priv->is_internal_short_scan) { 841 if (priv->scan_request->n_ssids) {
886 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
887 } else if (priv->scan_request->n_ssids) {
888 int i, p = 0; 842 int i, p = 0;
889 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); 843 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
890 for (i = 0; i < priv->scan_request->n_ssids; i++) { 844 for (i = 0; i < priv->scan_request->n_ssids; i++) {
@@ -981,38 +935,21 @@ int iwl4965_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
981 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS; 935 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
982 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; 936 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
983 scan->rx_chain = cpu_to_le16(rx_chain); 937 scan->rx_chain = cpu_to_le16(rx_chain);
984 if (!priv->is_internal_short_scan) { 938
985 cmd_len = iwl_legacy_fill_probe_req(priv, 939 cmd_len = iwl_legacy_fill_probe_req(priv,
986 (struct ieee80211_mgmt *)scan->data, 940 (struct ieee80211_mgmt *)scan->data,
987 vif->addr, 941 vif->addr,
988 priv->scan_request->ie, 942 priv->scan_request->ie,
989 priv->scan_request->ie_len, 943 priv->scan_request->ie_len,
990 IWL_MAX_SCAN_SIZE - sizeof(*scan)); 944 IWL_MAX_SCAN_SIZE - sizeof(*scan));
991 } else {
992 /* use bcast addr, will not be transmitted but must be valid */
993 cmd_len = iwl_legacy_fill_probe_req(priv,
994 (struct ieee80211_mgmt *)scan->data,
995 iwlegacy_bcast_addr, NULL, 0,
996 IWL_MAX_SCAN_SIZE - sizeof(*scan));
997
998 }
999 scan->tx_cmd.len = cpu_to_le16(cmd_len); 945 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1000 946
1001 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK | 947 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1002 RXON_FILTER_BCON_AWARE_MSK); 948 RXON_FILTER_BCON_AWARE_MSK);
1003 949
1004 if (priv->is_internal_short_scan) { 950 scan->channel_count = iwl4965_get_channels_for_scan(priv, vif, band,
1005 scan->channel_count = 951 is_active, n_probes,
1006 iwl4965_get_single_channel_for_scan(priv, vif, band, 952 (void *)&scan->data[cmd_len]);
1007 (void *)&scan->data[le16_to_cpu(
1008 scan->tx_cmd.len)]);
1009 } else {
1010 scan->channel_count =
1011 iwl4965_get_channels_for_scan(priv, vif, band,
1012 is_active, n_probes,
1013 (void *)&scan->data[le16_to_cpu(
1014 scan->tx_cmd.len)]);
1015 }
1016 if (scan->channel_count == 0) { 953 if (scan->channel_count == 0) {
1017 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); 954 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1018 return -EIO; 955 return -EIO;
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-rs.c b/drivers/net/wireless/iwlegacy/iwl-4965-rs.c
index 24d149909ba3..9b65153bdd01 100644
--- a/drivers/net/wireless/iwlegacy/iwl-4965-rs.c
+++ b/drivers/net/wireless/iwlegacy/iwl-4965-rs.c
@@ -2275,6 +2275,9 @@ iwl4965_rs_get_rate(void *priv_r, struct ieee80211_sta *sta, void *priv_sta,
2275 if (rate_control_send_low(sta, priv_sta, txrc)) 2275 if (rate_control_send_low(sta, priv_sta, txrc))
2276 return; 2276 return;
2277 2277
2278 if (!lq_sta)
2279 return;
2280
2278 rate_idx = lq_sta->last_txrate_idx; 2281 rate_idx = lq_sta->last_txrate_idx;
2279 2282
2280 if (lq_sta->last_rate_n_flags & RATE_MCS_HT_MSK) { 2283 if (lq_sta->last_rate_n_flags & RATE_MCS_HT_MSK) {
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-rx.c b/drivers/net/wireless/iwlegacy/iwl-4965-rx.c
index b9fa2f6411a7..2b144bbfc3c5 100644
--- a/drivers/net/wireless/iwlegacy/iwl-4965-rx.c
+++ b/drivers/net/wireless/iwlegacy/iwl-4965-rx.c
@@ -151,81 +151,6 @@ static void iwl4965_accumulative_statistics(struct iwl_priv *priv,
151 151
152#define REG_RECALIB_PERIOD (60) 152#define REG_RECALIB_PERIOD (60)
153 153
154/**
155 * iwl4965_good_plcp_health - checks for plcp error.
156 *
157 * When the plcp error is exceeding the thresholds, reset the radio
158 * to improve the throughput.
159 */
160bool iwl4965_good_plcp_health(struct iwl_priv *priv,
161 struct iwl_rx_packet *pkt)
162{
163 bool rc = true;
164 int combined_plcp_delta;
165 unsigned int plcp_msec;
166 unsigned long plcp_received_jiffies;
167
168 if (priv->cfg->base_params->plcp_delta_threshold ==
169 IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
170 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
171 return rc;
172 }
173
174 /*
175 * check for plcp_err and trigger radio reset if it exceeds
176 * the plcp error threshold plcp_delta.
177 */
178 plcp_received_jiffies = jiffies;
179 plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
180 (long) priv->plcp_jiffies);
181 priv->plcp_jiffies = plcp_received_jiffies;
182 /*
183 * check to make sure plcp_msec is not 0 to prevent division
184 * by zero.
185 */
186 if (plcp_msec) {
187 struct statistics_rx_phy *ofdm;
188 struct statistics_rx_ht_phy *ofdm_ht;
189
190 ofdm = &pkt->u.stats.rx.ofdm;
191 ofdm_ht = &pkt->u.stats.rx.ofdm_ht;
192 combined_plcp_delta =
193 (le32_to_cpu(ofdm->plcp_err) -
194 le32_to_cpu(priv->_4965.statistics.
195 rx.ofdm.plcp_err)) +
196 (le32_to_cpu(ofdm_ht->plcp_err) -
197 le32_to_cpu(priv->_4965.statistics.
198 rx.ofdm_ht.plcp_err));
199
200 if ((combined_plcp_delta > 0) &&
201 ((combined_plcp_delta * 100) / plcp_msec) >
202 priv->cfg->base_params->plcp_delta_threshold) {
203 /*
204 * if plcp_err exceed the threshold,
205 * the following data is printed in csv format:
206 * Text: plcp_err exceeded %d,
207 * Received ofdm.plcp_err,
208 * Current ofdm.plcp_err,
209 * Received ofdm_ht.plcp_err,
210 * Current ofdm_ht.plcp_err,
211 * combined_plcp_delta,
212 * plcp_msec
213 */
214 IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
215 "%u, %u, %u, %u, %d, %u mSecs\n",
216 priv->cfg->base_params->plcp_delta_threshold,
217 le32_to_cpu(ofdm->plcp_err),
218 le32_to_cpu(ofdm->plcp_err),
219 le32_to_cpu(ofdm_ht->plcp_err),
220 le32_to_cpu(ofdm_ht->plcp_err),
221 combined_plcp_delta, plcp_msec);
222
223 rc = false;
224 }
225 }
226 return rc;
227}
228
229void iwl4965_rx_statistics(struct iwl_priv *priv, 154void iwl4965_rx_statistics(struct iwl_priv *priv,
230 struct iwl_rx_mem_buffer *rxb) 155 struct iwl_rx_mem_buffer *rxb)
231{ 156{
@@ -248,8 +173,7 @@ void iwl4965_rx_statistics(struct iwl_priv *priv,
248 iwl4965_accumulative_statistics(priv, (__le32 *)&pkt->u.stats); 173 iwl4965_accumulative_statistics(priv, (__le32 *)&pkt->u.stats);
249#endif 174#endif
250 175
251 iwl_legacy_recover_from_statistics(priv, pkt); 176 /* TODO: reading some of statistics is unneeded */
252
253 memcpy(&priv->_4965.statistics, &pkt->u.stats, 177 memcpy(&priv->_4965.statistics, &pkt->u.stats,
254 sizeof(priv->_4965.statistics)); 178 sizeof(priv->_4965.statistics));
255 179
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-tx.c b/drivers/net/wireless/iwlegacy/iwl-4965-tx.c
index 79ac081832fb..ac4f64de1363 100644
--- a/drivers/net/wireless/iwlegacy/iwl-4965-tx.c
+++ b/drivers/net/wireless/iwlegacy/iwl-4965-tx.c
@@ -240,8 +240,7 @@ static void iwl4965_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
240 240
241 case WLAN_CIPHER_SUITE_TKIP: 241 case WLAN_CIPHER_SUITE_TKIP:
242 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; 242 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
243 ieee80211_get_tkip_key(keyconf, skb_frag, 243 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
244 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
245 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); 244 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
246 break; 245 break;
247 246
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965.c b/drivers/net/wireless/iwlegacy/iwl-4965.c
index facc94e74b07..bd4b000733f7 100644
--- a/drivers/net/wireless/iwlegacy/iwl-4965.c
+++ b/drivers/net/wireless/iwlegacy/iwl-4965.c
@@ -496,7 +496,7 @@ static s32 iwl4965_get_tx_atten_grp(u16 channel)
496 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH) 496 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
497 return CALIB_CH_GROUP_4; 497 return CALIB_CH_GROUP_4;
498 498
499 return -1; 499 return -EINVAL;
500} 500}
501 501
502static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel) 502static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
@@ -915,7 +915,7 @@ static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
915 if (txatten_grp < 0) { 915 if (txatten_grp < 0) {
916 IWL_ERR(priv, "Can't find txatten group for channel %d.\n", 916 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
917 channel); 917 channel);
918 return -EINVAL; 918 return txatten_grp;
919 } 919 }
920 920
921 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n", 921 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
@@ -1185,8 +1185,6 @@ static int iwl4965_send_rxon_assoc(struct iwl_priv *priv,
1185 1185
1186 ret = iwl_legacy_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, 1186 ret = iwl_legacy_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1187 sizeof(rxon_assoc), &rxon_assoc, NULL); 1187 sizeof(rxon_assoc), &rxon_assoc, NULL);
1188 if (ret)
1189 return ret;
1190 1188
1191 return ret; 1189 return ret;
1192} 1190}
@@ -2071,7 +2069,6 @@ static struct iwl_lib_ops iwl4965_lib = {
2071 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr, 2069 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2072 .init_alive_start = iwl4965_init_alive_start, 2070 .init_alive_start = iwl4965_init_alive_start,
2073 .load_ucode = iwl4965_load_bsm, 2071 .load_ucode = iwl4965_load_bsm,
2074 .dump_nic_event_log = iwl4965_dump_nic_event_log,
2075 .dump_nic_error_log = iwl4965_dump_nic_error_log, 2072 .dump_nic_error_log = iwl4965_dump_nic_error_log,
2076 .dump_fh = iwl4965_dump_fh, 2073 .dump_fh = iwl4965_dump_fh,
2077 .set_channel_switch = iwl4965_hw_channel_switch, 2074 .set_channel_switch = iwl4965_hw_channel_switch,
@@ -2102,7 +2099,6 @@ static struct iwl_lib_ops iwl4965_lib = {
2102 .tx_stats_read = iwl4965_ucode_tx_stats_read, 2099 .tx_stats_read = iwl4965_ucode_tx_stats_read,
2103 .general_stats_read = iwl4965_ucode_general_stats_read, 2100 .general_stats_read = iwl4965_ucode_general_stats_read,
2104 }, 2101 },
2105 .check_plcp_health = iwl4965_good_plcp_health,
2106}; 2102};
2107 2103
2108static const struct iwl_legacy_ops iwl4965_legacy_ops = { 2104static const struct iwl_legacy_ops iwl4965_legacy_ops = {
@@ -2152,10 +2148,8 @@ static struct iwl_base_params iwl4965_base_params = {
2152 .use_bsm = true, 2148 .use_bsm = true,
2153 .led_compensation = 61, 2149 .led_compensation = 61,
2154 .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS, 2150 .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
2155 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
2156 .wd_timeout = IWL_DEF_WD_TIMEOUT, 2151 .wd_timeout = IWL_DEF_WD_TIMEOUT,
2157 .temperature_kelvin = true, 2152 .temperature_kelvin = true,
2158 .max_event_log_size = 512,
2159 .ucode_tracing = true, 2153 .ucode_tracing = true,
2160 .sensitivity_calib_by_driver = true, 2154 .sensitivity_calib_by_driver = true,
2161 .chain_noise_calib_by_driver = true, 2155 .chain_noise_calib_by_driver = true,
diff --git a/drivers/net/wireless/iwlegacy/iwl-commands.h b/drivers/net/wireless/iwlegacy/iwl-commands.h
index 17a1d504348e..ee21210bea9c 100644
--- a/drivers/net/wireless/iwlegacy/iwl-commands.h
+++ b/drivers/net/wireless/iwlegacy/iwl-commands.h
@@ -2297,14 +2297,7 @@ struct iwl_spectrum_notification {
2297#define IWL_POWER_VEC_SIZE 5 2297#define IWL_POWER_VEC_SIZE 5
2298 2298
2299#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0)) 2299#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2300#define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2301#define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2302#define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2303#define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3)) 2300#define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2304#define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2305#define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2306#define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2307#define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2308 2301
2309struct iwl3945_powertable_cmd { 2302struct iwl3945_powertable_cmd {
2310 __le16 flags; 2303 __le16 flags;
diff --git a/drivers/net/wireless/iwlegacy/iwl-core.c b/drivers/net/wireless/iwlegacy/iwl-core.c
index 3be76bd5499a..35cd2537e7fd 100644
--- a/drivers/net/wireless/iwlegacy/iwl-core.c
+++ b/drivers/net/wireless/iwlegacy/iwl-core.c
@@ -931,7 +931,6 @@ void iwl_legacy_irq_handle_error(struct iwl_priv *priv)
931 priv->cfg->ops->lib->dump_nic_error_log(priv); 931 priv->cfg->ops->lib->dump_nic_error_log(priv);
932 if (priv->cfg->ops->lib->dump_fh) 932 if (priv->cfg->ops->lib->dump_fh)
933 priv->cfg->ops->lib->dump_fh(priv, NULL, false); 933 priv->cfg->ops->lib->dump_fh(priv, NULL, false);
934 priv->cfg->ops->lib->dump_nic_event_log(priv, false, NULL, false);
935#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG 934#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
936 if (iwl_legacy_get_debug_level(priv) & IWL_DL_FW_ERRORS) 935 if (iwl_legacy_get_debug_level(priv) & IWL_DL_FW_ERRORS)
937 iwl_legacy_print_rx_config_cmd(priv, 936 iwl_legacy_print_rx_config_cmd(priv,
@@ -1707,41 +1706,14 @@ iwl_legacy_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
1707EXPORT_SYMBOL(iwl_legacy_update_stats); 1706EXPORT_SYMBOL(iwl_legacy_update_stats);
1708#endif 1707#endif
1709 1708
1710static void _iwl_legacy_force_rf_reset(struct iwl_priv *priv) 1709int iwl_legacy_force_reset(struct iwl_priv *priv, bool external)
1711{
1712 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1713 return;
1714
1715 if (!iwl_legacy_is_any_associated(priv)) {
1716 IWL_DEBUG_SCAN(priv, "force reset rejected: not associated\n");
1717 return;
1718 }
1719 /*
1720 * There is no easy and better way to force reset the radio,
1721 * the only known method is switching channel which will force to
1722 * reset and tune the radio.
1723 * Use internal short scan (single channel) operation to should
1724 * achieve this objective.
1725 * Driver should reset the radio when number of consecutive missed
1726 * beacon, or any other uCode error condition detected.
1727 */
1728 IWL_DEBUG_INFO(priv, "perform radio reset.\n");
1729 iwl_legacy_internal_short_hw_scan(priv);
1730}
1731
1732
1733int iwl_legacy_force_reset(struct iwl_priv *priv, int mode, bool external)
1734{ 1710{
1735 struct iwl_force_reset *force_reset; 1711 struct iwl_force_reset *force_reset;
1736 1712
1737 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 1713 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1738 return -EINVAL; 1714 return -EINVAL;
1739 1715
1740 if (mode >= IWL_MAX_FORCE_RESET) { 1716 force_reset = &priv->force_reset;
1741 IWL_DEBUG_INFO(priv, "invalid reset request.\n");
1742 return -EINVAL;
1743 }
1744 force_reset = &priv->force_reset[mode];
1745 force_reset->reset_request_count++; 1717 force_reset->reset_request_count++;
1746 if (!external) { 1718 if (!external) {
1747 if (force_reset->last_force_reset_jiffies && 1719 if (force_reset->last_force_reset_jiffies &&
@@ -1754,37 +1726,34 @@ int iwl_legacy_force_reset(struct iwl_priv *priv, int mode, bool external)
1754 } 1726 }
1755 force_reset->reset_success_count++; 1727 force_reset->reset_success_count++;
1756 force_reset->last_force_reset_jiffies = jiffies; 1728 force_reset->last_force_reset_jiffies = jiffies;
1757 IWL_DEBUG_INFO(priv, "perform force reset (%d)\n", mode); 1729
1758 switch (mode) { 1730 /*
1759 case IWL_RF_RESET: 1731 * if the request is from external(ex: debugfs),
1760 _iwl_legacy_force_rf_reset(priv); 1732 * then always perform the request in regardless the module
1761 break; 1733 * parameter setting
1762 case IWL_FW_RESET: 1734 * if the request is from internal (uCode error or driver
1763 /* 1735 * detect failure), then fw_restart module parameter
1764 * if the request is from external(ex: debugfs), 1736 * need to be check before performing firmware reload
1765 * then always perform the request in regardless the module 1737 */
1766 * parameter setting 1738
1767 * if the request is from internal (uCode error or driver 1739 if (!external && !priv->cfg->mod_params->restart_fw) {
1768 * detect failure), then fw_restart module parameter 1740 IWL_DEBUG_INFO(priv, "Cancel firmware reload based on "
1769 * need to be check before performing firmware reload 1741 "module parameter setting\n");
1770 */ 1742 return 0;
1771 if (!external && !priv->cfg->mod_params->restart_fw) {
1772 IWL_DEBUG_INFO(priv, "Cancel firmware reload based on "
1773 "module parameter setting\n");
1774 break;
1775 }
1776 IWL_ERR(priv, "On demand firmware reload\n");
1777 /* Set the FW error flag -- cleared on iwl_down */
1778 set_bit(STATUS_FW_ERROR, &priv->status);
1779 wake_up_interruptible(&priv->wait_command_queue);
1780 /*
1781 * Keep the restart process from trying to send host
1782 * commands by clearing the INIT status bit
1783 */
1784 clear_bit(STATUS_READY, &priv->status);
1785 queue_work(priv->workqueue, &priv->restart);
1786 break;
1787 } 1743 }
1744
1745 IWL_ERR(priv, "On demand firmware reload\n");
1746
1747 /* Set the FW error flag -- cleared on iwl_down */
1748 set_bit(STATUS_FW_ERROR, &priv->status);
1749 wake_up_interruptible(&priv->wait_command_queue);
1750 /*
1751 * Keep the restart process from trying to send host
1752 * commands by clearing the INIT status bit
1753 */
1754 clear_bit(STATUS_READY, &priv->status);
1755 queue_work(priv->workqueue, &priv->restart);
1756
1788 return 0; 1757 return 0;
1789} 1758}
1790 1759
@@ -1879,7 +1848,7 @@ static int iwl_legacy_check_stuck_queue(struct iwl_priv *priv, int cnt)
1879 if (time_after(jiffies, timeout)) { 1848 if (time_after(jiffies, timeout)) {
1880 IWL_ERR(priv, "Queue %d stuck for %u ms.\n", 1849 IWL_ERR(priv, "Queue %d stuck for %u ms.\n",
1881 q->id, priv->cfg->base_params->wd_timeout); 1850 q->id, priv->cfg->base_params->wd_timeout);
1882 ret = iwl_legacy_force_reset(priv, IWL_FW_RESET, false); 1851 ret = iwl_legacy_force_reset(priv, false);
1883 return (ret == -EAGAIN) ? 0 : 1; 1852 return (ret == -EAGAIN) ? 0 : 1;
1884 } 1853 }
1885 1854
diff --git a/drivers/net/wireless/iwlegacy/iwl-core.h b/drivers/net/wireless/iwlegacy/iwl-core.h
index c5fbda0760de..84da79376ef8 100644
--- a/drivers/net/wireless/iwlegacy/iwl-core.h
+++ b/drivers/net/wireless/iwlegacy/iwl-core.h
@@ -143,8 +143,7 @@ struct iwl_lib_ops {
143 int (*is_valid_rtc_data_addr)(u32 addr); 143 int (*is_valid_rtc_data_addr)(u32 addr);
144 /* 1st ucode load */ 144 /* 1st ucode load */
145 int (*load_ucode)(struct iwl_priv *priv); 145 int (*load_ucode)(struct iwl_priv *priv);
146 int (*dump_nic_event_log)(struct iwl_priv *priv, 146
147 bool full_log, char **buf, bool display);
148 void (*dump_nic_error_log)(struct iwl_priv *priv); 147 void (*dump_nic_error_log)(struct iwl_priv *priv);
149 int (*dump_fh)(struct iwl_priv *priv, char **buf, bool display); 148 int (*dump_fh)(struct iwl_priv *priv, char **buf, bool display);
150 int (*set_channel_switch)(struct iwl_priv *priv, 149 int (*set_channel_switch)(struct iwl_priv *priv,
@@ -161,9 +160,6 @@ struct iwl_lib_ops {
161 160
162 /* temperature */ 161 /* temperature */
163 struct iwl_temp_ops temp_ops; 162 struct iwl_temp_ops temp_ops;
164 /* check for plcp health */
165 bool (*check_plcp_health)(struct iwl_priv *priv,
166 struct iwl_rx_packet *pkt);
167 163
168 struct iwl_debugfs_ops debugfs_ops; 164 struct iwl_debugfs_ops debugfs_ops;
169 165
@@ -207,11 +203,8 @@ struct iwl_mod_params {
207 * to the deviation to achieve the desired led frequency. 203 * to the deviation to achieve the desired led frequency.
208 * The detail algorithm is described in iwl-led.c 204 * The detail algorithm is described in iwl-led.c
209 * @chain_noise_num_beacons: number of beacons used to compute chain noise 205 * @chain_noise_num_beacons: number of beacons used to compute chain noise
210 * @plcp_delta_threshold: plcp error rate threshold used to trigger
211 * radio tuning when there is a high receiving plcp error rate
212 * @wd_timeout: TX queues watchdog timeout 206 * @wd_timeout: TX queues watchdog timeout
213 * @temperature_kelvin: temperature report by uCode in kelvin 207 * @temperature_kelvin: temperature report by uCode in kelvin
214 * @max_event_log_size: size of event log buffer size for ucode event logging
215 * @ucode_tracing: support ucode continuous tracing 208 * @ucode_tracing: support ucode continuous tracing
216 * @sensitivity_calib_by_driver: driver has the capability to perform 209 * @sensitivity_calib_by_driver: driver has the capability to perform
217 * sensitivity calibration operation 210 * sensitivity calibration operation
@@ -229,10 +222,8 @@ struct iwl_base_params {
229 222
230 u16 led_compensation; 223 u16 led_compensation;
231 int chain_noise_num_beacons; 224 int chain_noise_num_beacons;
232 u8 plcp_delta_threshold;
233 unsigned int wd_timeout; 225 unsigned int wd_timeout;
234 bool temperature_kelvin; 226 bool temperature_kelvin;
235 u32 max_event_log_size;
236 const bool ucode_tracing; 227 const bool ucode_tracing;
237 const bool sensitivity_calib_by_driver; 228 const bool sensitivity_calib_by_driver;
238 const bool chain_noise_calib_by_driver; 229 const bool chain_noise_calib_by_driver;
@@ -441,7 +432,7 @@ int iwl_legacy_mac_hw_scan(struct ieee80211_hw *hw,
441 struct ieee80211_vif *vif, 432 struct ieee80211_vif *vif,
442 struct cfg80211_scan_request *req); 433 struct cfg80211_scan_request *req);
443void iwl_legacy_internal_short_hw_scan(struct iwl_priv *priv); 434void iwl_legacy_internal_short_hw_scan(struct iwl_priv *priv);
444int iwl_legacy_force_reset(struct iwl_priv *priv, int mode, bool external); 435int iwl_legacy_force_reset(struct iwl_priv *priv, bool external);
445u16 iwl_legacy_fill_probe_req(struct iwl_priv *priv, 436u16 iwl_legacy_fill_probe_req(struct iwl_priv *priv,
446 struct ieee80211_mgmt *frame, 437 struct ieee80211_mgmt *frame,
447 const u8 *ta, const u8 *ie, int ie_len, int left); 438 const u8 *ta, const u8 *ie, int ie_len, int left);
@@ -493,7 +484,7 @@ static inline u16 iwl_legacy_pcie_link_ctl(struct iwl_priv *priv)
493{ 484{
494 int pos; 485 int pos;
495 u16 pci_lnk_ctl; 486 u16 pci_lnk_ctl;
496 pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP); 487 pos = pci_pcie_cap(priv->pci_dev);
497 pci_read_config_word(priv->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl); 488 pci_read_config_word(priv->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
498 return pci_lnk_ctl; 489 return pci_lnk_ctl;
499} 490}
@@ -521,8 +512,6 @@ extern const struct dev_pm_ops iwl_legacy_pm_ops;
521* Error Handling Debugging 512* Error Handling Debugging
522******************************************************/ 513******************************************************/
523void iwl4965_dump_nic_error_log(struct iwl_priv *priv); 514void iwl4965_dump_nic_error_log(struct iwl_priv *priv);
524int iwl4965_dump_nic_event_log(struct iwl_priv *priv,
525 bool full_log, char **buf, bool display);
526#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG 515#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
527void iwl_legacy_print_rx_config_cmd(struct iwl_priv *priv, 516void iwl_legacy_print_rx_config_cmd(struct iwl_priv *priv,
528 struct iwl_rxon_context *ctx); 517 struct iwl_rxon_context *ctx);
diff --git a/drivers/net/wireless/iwlegacy/iwl-debugfs.c b/drivers/net/wireless/iwlegacy/iwl-debugfs.c
index 2d32438b4cb8..996996a71657 100644
--- a/drivers/net/wireless/iwlegacy/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlegacy/iwl-debugfs.c
@@ -391,48 +391,6 @@ static ssize_t iwl_legacy_dbgfs_nvm_read(struct file *file,
391 return ret; 391 return ret;
392} 392}
393 393
394static ssize_t iwl_legacy_dbgfs_log_event_read(struct file *file,
395 char __user *user_buf,
396 size_t count, loff_t *ppos)
397{
398 struct iwl_priv *priv = file->private_data;
399 char *buf;
400 int pos = 0;
401 ssize_t ret = -ENOMEM;
402
403 ret = pos = priv->cfg->ops->lib->dump_nic_event_log(
404 priv, true, &buf, true);
405 if (buf) {
406 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
407 kfree(buf);
408 }
409 return ret;
410}
411
412static ssize_t iwl_legacy_dbgfs_log_event_write(struct file *file,
413 const char __user *user_buf,
414 size_t count, loff_t *ppos)
415{
416 struct iwl_priv *priv = file->private_data;
417 u32 event_log_flag;
418 char buf[8];
419 int buf_size;
420
421 memset(buf, 0, sizeof(buf));
422 buf_size = min(count, sizeof(buf) - 1);
423 if (copy_from_user(buf, user_buf, buf_size))
424 return -EFAULT;
425 if (sscanf(buf, "%d", &event_log_flag) != 1)
426 return -EFAULT;
427 if (event_log_flag == 1)
428 priv->cfg->ops->lib->dump_nic_event_log(priv, true,
429 NULL, false);
430
431 return count;
432}
433
434
435
436static ssize_t 394static ssize_t
437iwl_legacy_dbgfs_channels_read(struct file *file, char __user *user_buf, 395iwl_legacy_dbgfs_channels_read(struct file *file, char __user *user_buf,
438 size_t count, loff_t *ppos) 396 size_t count, loff_t *ppos)
@@ -706,7 +664,6 @@ static ssize_t iwl_legacy_dbgfs_disable_ht40_read(struct file *file,
706} 664}
707 665
708DEBUGFS_READ_WRITE_FILE_OPS(sram); 666DEBUGFS_READ_WRITE_FILE_OPS(sram);
709DEBUGFS_READ_WRITE_FILE_OPS(log_event);
710DEBUGFS_READ_FILE_OPS(nvm); 667DEBUGFS_READ_FILE_OPS(nvm);
711DEBUGFS_READ_FILE_OPS(stations); 668DEBUGFS_READ_FILE_OPS(stations);
712DEBUGFS_READ_FILE_OPS(channels); 669DEBUGFS_READ_FILE_OPS(channels);
@@ -1098,56 +1055,6 @@ static ssize_t iwl_legacy_dbgfs_clear_ucode_statistics_write(struct file *file,
1098 return count; 1055 return count;
1099} 1056}
1100 1057
1101static ssize_t iwl_legacy_dbgfs_ucode_tracing_read(struct file *file,
1102 char __user *user_buf,
1103 size_t count, loff_t *ppos) {
1104
1105 struct iwl_priv *priv = file->private_data;
1106 int pos = 0;
1107 char buf[128];
1108 const size_t bufsz = sizeof(buf);
1109
1110 pos += scnprintf(buf + pos, bufsz - pos, "ucode trace timer is %s\n",
1111 priv->event_log.ucode_trace ? "On" : "Off");
1112 pos += scnprintf(buf + pos, bufsz - pos, "non_wraps_count:\t\t %u\n",
1113 priv->event_log.non_wraps_count);
1114 pos += scnprintf(buf + pos, bufsz - pos, "wraps_once_count:\t\t %u\n",
1115 priv->event_log.wraps_once_count);
1116 pos += scnprintf(buf + pos, bufsz - pos, "wraps_more_count:\t\t %u\n",
1117 priv->event_log.wraps_more_count);
1118
1119 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1120}
1121
1122static ssize_t iwl_legacy_dbgfs_ucode_tracing_write(struct file *file,
1123 const char __user *user_buf,
1124 size_t count, loff_t *ppos)
1125{
1126 struct iwl_priv *priv = file->private_data;
1127 char buf[8];
1128 int buf_size;
1129 int trace;
1130
1131 memset(buf, 0, sizeof(buf));
1132 buf_size = min(count, sizeof(buf) - 1);
1133 if (copy_from_user(buf, user_buf, buf_size))
1134 return -EFAULT;
1135 if (sscanf(buf, "%d", &trace) != 1)
1136 return -EFAULT;
1137
1138 if (trace) {
1139 priv->event_log.ucode_trace = true;
1140 /* schedule the ucode timer to occur in UCODE_TRACE_PERIOD */
1141 mod_timer(&priv->ucode_trace,
1142 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
1143 } else {
1144 priv->event_log.ucode_trace = false;
1145 del_timer_sync(&priv->ucode_trace);
1146 }
1147
1148 return count;
1149}
1150
1151static ssize_t iwl_legacy_dbgfs_rxon_flags_read(struct file *file, 1058static ssize_t iwl_legacy_dbgfs_rxon_flags_read(struct file *file,
1152 char __user *user_buf, 1059 char __user *user_buf,
1153 size_t count, loff_t *ppos) { 1060 size_t count, loff_t *ppos) {
@@ -1236,72 +1143,31 @@ static ssize_t iwl_legacy_dbgfs_missed_beacon_write(struct file *file,
1236 return count; 1143 return count;
1237} 1144}
1238 1145
1239static ssize_t iwl_legacy_dbgfs_plcp_delta_read(struct file *file,
1240 char __user *user_buf,
1241 size_t count, loff_t *ppos) {
1242
1243 struct iwl_priv *priv = file->private_data;
1244 int pos = 0;
1245 char buf[12];
1246 const size_t bufsz = sizeof(buf);
1247
1248 pos += scnprintf(buf + pos, bufsz - pos, "%u\n",
1249 priv->cfg->base_params->plcp_delta_threshold);
1250
1251 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1252}
1253
1254static ssize_t iwl_legacy_dbgfs_plcp_delta_write(struct file *file,
1255 const char __user *user_buf,
1256 size_t count, loff_t *ppos) {
1257
1258 struct iwl_priv *priv = file->private_data;
1259 char buf[8];
1260 int buf_size;
1261 int plcp;
1262
1263 memset(buf, 0, sizeof(buf));
1264 buf_size = min(count, sizeof(buf) - 1);
1265 if (copy_from_user(buf, user_buf, buf_size))
1266 return -EFAULT;
1267 if (sscanf(buf, "%d", &plcp) != 1)
1268 return -EINVAL;
1269 if ((plcp < IWL_MAX_PLCP_ERR_THRESHOLD_MIN) ||
1270 (plcp > IWL_MAX_PLCP_ERR_THRESHOLD_MAX))
1271 priv->cfg->base_params->plcp_delta_threshold =
1272 IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE;
1273 else
1274 priv->cfg->base_params->plcp_delta_threshold = plcp;
1275 return count;
1276}
1277
1278static ssize_t iwl_legacy_dbgfs_force_reset_read(struct file *file, 1146static ssize_t iwl_legacy_dbgfs_force_reset_read(struct file *file,
1279 char __user *user_buf, 1147 char __user *user_buf,
1280 size_t count, loff_t *ppos) { 1148 size_t count, loff_t *ppos) {
1281 1149
1282 struct iwl_priv *priv = file->private_data; 1150 struct iwl_priv *priv = file->private_data;
1283 int i, pos = 0; 1151 int pos = 0;
1284 char buf[300]; 1152 char buf[300];
1285 const size_t bufsz = sizeof(buf); 1153 const size_t bufsz = sizeof(buf);
1286 struct iwl_force_reset *force_reset; 1154 struct iwl_force_reset *force_reset;
1287 1155
1288 for (i = 0; i < IWL_MAX_FORCE_RESET; i++) { 1156 force_reset = &priv->force_reset;
1289 force_reset = &priv->force_reset[i]; 1157
1290 pos += scnprintf(buf + pos, bufsz - pos, 1158 pos += scnprintf(buf + pos, bufsz - pos,
1291 "Force reset method %d\n", i); 1159 "\tnumber of reset request: %d\n",
1292 pos += scnprintf(buf + pos, bufsz - pos, 1160 force_reset->reset_request_count);
1293 "\tnumber of reset request: %d\n", 1161 pos += scnprintf(buf + pos, bufsz - pos,
1294 force_reset->reset_request_count); 1162 "\tnumber of reset request success: %d\n",
1295 pos += scnprintf(buf + pos, bufsz - pos, 1163 force_reset->reset_success_count);
1296 "\tnumber of reset request success: %d\n", 1164 pos += scnprintf(buf + pos, bufsz - pos,
1297 force_reset->reset_success_count); 1165 "\tnumber of reset request reject: %d\n",
1298 pos += scnprintf(buf + pos, bufsz - pos, 1166 force_reset->reset_reject_count);
1299 "\tnumber of reset request reject: %d\n", 1167 pos += scnprintf(buf + pos, bufsz - pos,
1300 force_reset->reset_reject_count); 1168 "\treset duration: %lu\n",
1301 pos += scnprintf(buf + pos, bufsz - pos, 1169 force_reset->reset_duration);
1302 "\treset duration: %lu\n", 1170
1303 force_reset->reset_duration);
1304 }
1305 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 1171 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1306} 1172}
1307 1173
@@ -1309,25 +1175,11 @@ static ssize_t iwl_legacy_dbgfs_force_reset_write(struct file *file,
1309 const char __user *user_buf, 1175 const char __user *user_buf,
1310 size_t count, loff_t *ppos) { 1176 size_t count, loff_t *ppos) {
1311 1177
1178 int ret;
1312 struct iwl_priv *priv = file->private_data; 1179 struct iwl_priv *priv = file->private_data;
1313 char buf[8];
1314 int buf_size;
1315 int reset, ret;
1316 1180
1317 memset(buf, 0, sizeof(buf)); 1181 ret = iwl_legacy_force_reset(priv, true);
1318 buf_size = min(count, sizeof(buf) - 1); 1182
1319 if (copy_from_user(buf, user_buf, buf_size))
1320 return -EFAULT;
1321 if (sscanf(buf, "%d", &reset) != 1)
1322 return -EINVAL;
1323 switch (reset) {
1324 case IWL_RF_RESET:
1325 case IWL_FW_RESET:
1326 ret = iwl_legacy_force_reset(priv, reset, true);
1327 break;
1328 default:
1329 return -EINVAL;
1330 }
1331 return ret ? ret : count; 1183 return ret ? ret : count;
1332} 1184}
1333 1185
@@ -1367,10 +1219,8 @@ DEBUGFS_READ_FILE_OPS(chain_noise);
1367DEBUGFS_READ_FILE_OPS(power_save_status); 1219DEBUGFS_READ_FILE_OPS(power_save_status);
1368DEBUGFS_WRITE_FILE_OPS(clear_ucode_statistics); 1220DEBUGFS_WRITE_FILE_OPS(clear_ucode_statistics);
1369DEBUGFS_WRITE_FILE_OPS(clear_traffic_statistics); 1221DEBUGFS_WRITE_FILE_OPS(clear_traffic_statistics);
1370DEBUGFS_READ_WRITE_FILE_OPS(ucode_tracing);
1371DEBUGFS_READ_FILE_OPS(fh_reg); 1222DEBUGFS_READ_FILE_OPS(fh_reg);
1372DEBUGFS_READ_WRITE_FILE_OPS(missed_beacon); 1223DEBUGFS_READ_WRITE_FILE_OPS(missed_beacon);
1373DEBUGFS_READ_WRITE_FILE_OPS(plcp_delta);
1374DEBUGFS_READ_WRITE_FILE_OPS(force_reset); 1224DEBUGFS_READ_WRITE_FILE_OPS(force_reset);
1375DEBUGFS_READ_FILE_OPS(rxon_flags); 1225DEBUGFS_READ_FILE_OPS(rxon_flags);
1376DEBUGFS_READ_FILE_OPS(rxon_filter_flags); 1226DEBUGFS_READ_FILE_OPS(rxon_filter_flags);
@@ -1403,7 +1253,6 @@ int iwl_legacy_dbgfs_register(struct iwl_priv *priv, const char *name)
1403 1253
1404 DEBUGFS_ADD_FILE(nvm, dir_data, S_IRUSR); 1254 DEBUGFS_ADD_FILE(nvm, dir_data, S_IRUSR);
1405 DEBUGFS_ADD_FILE(sram, dir_data, S_IWUSR | S_IRUSR); 1255 DEBUGFS_ADD_FILE(sram, dir_data, S_IWUSR | S_IRUSR);
1406 DEBUGFS_ADD_FILE(log_event, dir_data, S_IWUSR | S_IRUSR);
1407 DEBUGFS_ADD_FILE(stations, dir_data, S_IRUSR); 1256 DEBUGFS_ADD_FILE(stations, dir_data, S_IRUSR);
1408 DEBUGFS_ADD_FILE(channels, dir_data, S_IRUSR); 1257 DEBUGFS_ADD_FILE(channels, dir_data, S_IRUSR);
1409 DEBUGFS_ADD_FILE(status, dir_data, S_IRUSR); 1258 DEBUGFS_ADD_FILE(status, dir_data, S_IRUSR);
@@ -1420,7 +1269,6 @@ int iwl_legacy_dbgfs_register(struct iwl_priv *priv, const char *name)
1420 DEBUGFS_ADD_FILE(clear_traffic_statistics, dir_debug, S_IWUSR); 1269 DEBUGFS_ADD_FILE(clear_traffic_statistics, dir_debug, S_IWUSR);
1421 DEBUGFS_ADD_FILE(fh_reg, dir_debug, S_IRUSR); 1270 DEBUGFS_ADD_FILE(fh_reg, dir_debug, S_IRUSR);
1422 DEBUGFS_ADD_FILE(missed_beacon, dir_debug, S_IWUSR); 1271 DEBUGFS_ADD_FILE(missed_beacon, dir_debug, S_IWUSR);
1423 DEBUGFS_ADD_FILE(plcp_delta, dir_debug, S_IWUSR | S_IRUSR);
1424 DEBUGFS_ADD_FILE(force_reset, dir_debug, S_IWUSR | S_IRUSR); 1272 DEBUGFS_ADD_FILE(force_reset, dir_debug, S_IWUSR | S_IRUSR);
1425 DEBUGFS_ADD_FILE(ucode_rx_stats, dir_debug, S_IRUSR); 1273 DEBUGFS_ADD_FILE(ucode_rx_stats, dir_debug, S_IRUSR);
1426 DEBUGFS_ADD_FILE(ucode_tx_stats, dir_debug, S_IRUSR); 1274 DEBUGFS_ADD_FILE(ucode_tx_stats, dir_debug, S_IRUSR);
@@ -1430,8 +1278,6 @@ int iwl_legacy_dbgfs_register(struct iwl_priv *priv, const char *name)
1430 DEBUGFS_ADD_FILE(sensitivity, dir_debug, S_IRUSR); 1278 DEBUGFS_ADD_FILE(sensitivity, dir_debug, S_IRUSR);
1431 if (priv->cfg->base_params->chain_noise_calib_by_driver) 1279 if (priv->cfg->base_params->chain_noise_calib_by_driver)
1432 DEBUGFS_ADD_FILE(chain_noise, dir_debug, S_IRUSR); 1280 DEBUGFS_ADD_FILE(chain_noise, dir_debug, S_IRUSR);
1433 if (priv->cfg->base_params->ucode_tracing)
1434 DEBUGFS_ADD_FILE(ucode_tracing, dir_debug, S_IWUSR | S_IRUSR);
1435 DEBUGFS_ADD_FILE(rxon_flags, dir_debug, S_IWUSR); 1281 DEBUGFS_ADD_FILE(rxon_flags, dir_debug, S_IWUSR);
1436 DEBUGFS_ADD_FILE(rxon_filter_flags, dir_debug, S_IWUSR); 1282 DEBUGFS_ADD_FILE(rxon_filter_flags, dir_debug, S_IWUSR);
1437 DEBUGFS_ADD_FILE(wd_timeout, dir_debug, S_IWUSR); 1283 DEBUGFS_ADD_FILE(wd_timeout, dir_debug, S_IWUSR);
diff --git a/drivers/net/wireless/iwlegacy/iwl-dev.h b/drivers/net/wireless/iwlegacy/iwl-dev.h
index ea30122669ee..9c786edf56fd 100644
--- a/drivers/net/wireless/iwlegacy/iwl-dev.h
+++ b/drivers/net/wireless/iwlegacy/iwl-dev.h
@@ -32,6 +32,7 @@
32#ifndef __iwl_legacy_dev_h__ 32#ifndef __iwl_legacy_dev_h__
33#define __iwl_legacy_dev_h__ 33#define __iwl_legacy_dev_h__
34 34
35#include <linux/interrupt.h>
35#include <linux/pci.h> /* for struct pci_device_id */ 36#include <linux/pci.h> /* for struct pci_device_id */
36#include <linux/kernel.h> 37#include <linux/kernel.h>
37#include <linux/leds.h> 38#include <linux/leds.h>
@@ -855,32 +856,6 @@ struct traffic_stats {
855}; 856};
856 857
857/* 858/*
858 * schedule the timer to wake up every UCODE_TRACE_PERIOD milliseconds
859 * to perform continuous uCode event logging operation if enabled
860 */
861#define UCODE_TRACE_PERIOD (100)
862
863/*
864 * iwl_event_log: current uCode event log position
865 *
866 * @ucode_trace: enable/disable ucode continuous trace timer
867 * @num_wraps: how many times the event buffer wraps
868 * @next_entry: the entry just before the next one that uCode would fill
869 * @non_wraps_count: counter for no wrap detected when dump ucode events
870 * @wraps_once_count: counter for wrap once detected when dump ucode events
871 * @wraps_more_count: counter for wrap more than once detected
872 * when dump ucode events
873 */
874struct iwl_event_log {
875 bool ucode_trace;
876 u32 num_wraps;
877 u32 next_entry;
878 int non_wraps_count;
879 int wraps_once_count;
880 int wraps_more_count;
881};
882
883/*
884 * host interrupt timeout value 859 * host interrupt timeout value
885 * used with setting interrupt coalescing timer 860 * used with setting interrupt coalescing timer
886 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 861 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
@@ -895,18 +870,6 @@ struct iwl_event_log {
895#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10) 870#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
896#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0) 871#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
897 872
898/*
899 * This is the threshold value of plcp error rate per 100mSecs. It is
900 * used to set and check for the validity of plcp_delta.
901 */
902#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN (1)
903#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF (50)
904#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF (100)
905#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF (200)
906#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX (255)
907#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE (0)
908
909#define IWL_DELAY_NEXT_FORCE_RF_RESET (HZ*3)
910#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5) 873#define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
911 874
912/* TX queue watchdog timeouts in mSecs */ 875/* TX queue watchdog timeouts in mSecs */
@@ -914,12 +877,6 @@ struct iwl_event_log {
914#define IWL_LONG_WD_TIMEOUT (10000) 877#define IWL_LONG_WD_TIMEOUT (10000)
915#define IWL_MAX_WD_TIMEOUT (120000) 878#define IWL_MAX_WD_TIMEOUT (120000)
916 879
917enum iwl_reset {
918 IWL_RF_RESET = 0,
919 IWL_FW_RESET,
920 IWL_MAX_FORCE_RESET,
921};
922
923struct iwl_force_reset { 880struct iwl_force_reset {
924 int reset_request_count; 881 int reset_request_count;
925 int reset_success_count; 882 int reset_success_count;
@@ -1032,11 +989,8 @@ struct iwl_priv {
1032 /* track IBSS manager (last beacon) status */ 989 /* track IBSS manager (last beacon) status */
1033 u32 ibss_manager; 990 u32 ibss_manager;
1034 991
1035 /* storing the jiffies when the plcp error rate is received */
1036 unsigned long plcp_jiffies;
1037
1038 /* force reset */ 992 /* force reset */
1039 struct iwl_force_reset force_reset[IWL_MAX_FORCE_RESET]; 993 struct iwl_force_reset force_reset;
1040 994
1041 /* we allocate array of iwl_channel_info for NIC's valid channels. 995 /* we allocate array of iwl_channel_info for NIC's valid channels.
1042 * Access via channel # using indirect index array */ 996 * Access via channel # using indirect index array */
@@ -1057,7 +1011,6 @@ struct iwl_priv {
1057 enum ieee80211_band scan_band; 1011 enum ieee80211_band scan_band;
1058 struct cfg80211_scan_request *scan_request; 1012 struct cfg80211_scan_request *scan_request;
1059 struct ieee80211_vif *scan_vif; 1013 struct ieee80211_vif *scan_vif;
1060 bool is_internal_short_scan;
1061 u8 scan_tx_ant[IEEE80211_NUM_BANDS]; 1014 u8 scan_tx_ant[IEEE80211_NUM_BANDS];
1062 u8 mgmt_tx_ant; 1015 u8 mgmt_tx_ant;
1063 1016
@@ -1212,12 +1165,6 @@ struct iwl_priv {
1212#endif 1165#endif
1213#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE) 1166#if defined(CONFIG_IWL4965) || defined(CONFIG_IWL4965_MODULE)
1214 struct { 1167 struct {
1215 /*
1216 * reporting the number of tids has AGG on. 0 means
1217 * no AGGREGATION
1218 */
1219 u8 agg_tids_count;
1220
1221 struct iwl_rx_phy_res last_phy_res; 1168 struct iwl_rx_phy_res last_phy_res;
1222 bool last_phy_res_valid; 1169 bool last_phy_res_valid;
1223 1170
@@ -1256,7 +1203,6 @@ struct iwl_priv {
1256 struct iwl_rxon_context *beacon_ctx; 1203 struct iwl_rxon_context *beacon_ctx;
1257 struct sk_buff *beacon_skb; 1204 struct sk_buff *beacon_skb;
1258 1205
1259 struct work_struct start_internal_scan;
1260 struct work_struct tx_flush; 1206 struct work_struct tx_flush;
1261 1207
1262 struct tasklet_struct irq_tasklet; 1208 struct tasklet_struct irq_tasklet;
@@ -1293,12 +1239,9 @@ struct iwl_priv {
1293 u32 disable_tx_power_cal; 1239 u32 disable_tx_power_cal;
1294 struct work_struct run_time_calib_work; 1240 struct work_struct run_time_calib_work;
1295 struct timer_list statistics_periodic; 1241 struct timer_list statistics_periodic;
1296 struct timer_list ucode_trace;
1297 struct timer_list watchdog; 1242 struct timer_list watchdog;
1298 bool hw_ready; 1243 bool hw_ready;
1299 1244
1300 struct iwl_event_log event_log;
1301
1302 struct led_classdev led; 1245 struct led_classdev led;
1303 unsigned long blink_on, blink_off; 1246 unsigned long blink_on, blink_off;
1304 bool led_registered; 1247 bool led_registered;
diff --git a/drivers/net/wireless/iwlegacy/iwl-devtrace.c b/drivers/net/wireless/iwlegacy/iwl-devtrace.c
index 080b852b33bd..acec99197ce0 100644
--- a/drivers/net/wireless/iwlegacy/iwl-devtrace.c
+++ b/drivers/net/wireless/iwlegacy/iwl-devtrace.c
@@ -38,8 +38,5 @@ EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_ioread32);
38EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_iowrite32); 38EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_iowrite32);
39EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_rx); 39EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_rx);
40EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_tx); 40EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_tx);
41EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_ucode_event);
42EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_ucode_error); 41EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_ucode_error);
43EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_ucode_cont_event);
44EXPORT_TRACEPOINT_SYMBOL(iwlwifi_legacy_dev_ucode_wrap_event);
45#endif 42#endif
diff --git a/drivers/net/wireless/iwlegacy/iwl-devtrace.h b/drivers/net/wireless/iwlegacy/iwl-devtrace.h
index 9612aa0f6ec4..a443725ba6be 100644
--- a/drivers/net/wireless/iwlegacy/iwl-devtrace.h
+++ b/drivers/net/wireless/iwlegacy/iwl-devtrace.h
@@ -96,47 +96,6 @@ TRACE_EVENT(iwlwifi_legacy_dev_iowrite32,
96#undef TRACE_SYSTEM 96#undef TRACE_SYSTEM
97#define TRACE_SYSTEM iwlwifi_legacy_ucode 97#define TRACE_SYSTEM iwlwifi_legacy_ucode
98 98
99TRACE_EVENT(iwlwifi_legacy_dev_ucode_cont_event,
100 TP_PROTO(struct iwl_priv *priv, u32 time, u32 data, u32 ev),
101 TP_ARGS(priv, time, data, ev),
102 TP_STRUCT__entry(
103 PRIV_ENTRY
104
105 __field(u32, time)
106 __field(u32, data)
107 __field(u32, ev)
108 ),
109 TP_fast_assign(
110 PRIV_ASSIGN;
111 __entry->time = time;
112 __entry->data = data;
113 __entry->ev = ev;
114 ),
115 TP_printk("[%p] EVT_LOGT:%010u:0x%08x:%04u",
116 __entry->priv, __entry->time, __entry->data, __entry->ev)
117);
118
119TRACE_EVENT(iwlwifi_legacy_dev_ucode_wrap_event,
120 TP_PROTO(struct iwl_priv *priv, u32 wraps, u32 n_entry, u32 p_entry),
121 TP_ARGS(priv, wraps, n_entry, p_entry),
122 TP_STRUCT__entry(
123 PRIV_ENTRY
124
125 __field(u32, wraps)
126 __field(u32, n_entry)
127 __field(u32, p_entry)
128 ),
129 TP_fast_assign(
130 PRIV_ASSIGN;
131 __entry->wraps = wraps;
132 __entry->n_entry = n_entry;
133 __entry->p_entry = p_entry;
134 ),
135 TP_printk("[%p] wraps=#%02d n=0x%X p=0x%X",
136 __entry->priv, __entry->wraps, __entry->n_entry,
137 __entry->p_entry)
138);
139
140#undef TRACE_SYSTEM 99#undef TRACE_SYSTEM
141#define TRACE_SYSTEM iwlwifi 100#define TRACE_SYSTEM iwlwifi
142 101
@@ -242,25 +201,6 @@ TRACE_EVENT(iwlwifi_legacy_dev_ucode_error,
242 __entry->blink2, __entry->ilink1, __entry->ilink2) 201 __entry->blink2, __entry->ilink1, __entry->ilink2)
243); 202);
244 203
245TRACE_EVENT(iwlwifi_legacy_dev_ucode_event,
246 TP_PROTO(struct iwl_priv *priv, u32 time, u32 data, u32 ev),
247 TP_ARGS(priv, time, data, ev),
248 TP_STRUCT__entry(
249 PRIV_ENTRY
250
251 __field(u32, time)
252 __field(u32, data)
253 __field(u32, ev)
254 ),
255 TP_fast_assign(
256 PRIV_ASSIGN;
257 __entry->time = time;
258 __entry->data = data;
259 __entry->ev = ev;
260 ),
261 TP_printk("[%p] EVT_LOGT:%010u:0x%08x:%04u",
262 __entry->priv, __entry->time, __entry->data, __entry->ev)
263);
264#endif /* __IWLWIFI_DEVICE_TRACE */ 204#endif /* __IWLWIFI_DEVICE_TRACE */
265 205
266#undef TRACE_INCLUDE_PATH 206#undef TRACE_INCLUDE_PATH
diff --git a/drivers/net/wireless/iwlegacy/iwl-eeprom.c b/drivers/net/wireless/iwlegacy/iwl-eeprom.c
index cb346d1a9ffa..5bf3f49b74ab 100644
--- a/drivers/net/wireless/iwlegacy/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlegacy/iwl-eeprom.c
@@ -316,7 +316,6 @@ static void iwl_legacy_init_band_reference(const struct iwl_priv *priv,
316 break; 316 break;
317 default: 317 default:
318 BUG(); 318 BUG();
319 return;
320 } 319 }
321} 320}
322 321
diff --git a/drivers/net/wireless/iwlegacy/iwl-helpers.h b/drivers/net/wireless/iwlegacy/iwl-helpers.h
index a6effdae63f9..5cf23eaecbbb 100644
--- a/drivers/net/wireless/iwlegacy/iwl-helpers.h
+++ b/drivers/net/wireless/iwlegacy/iwl-helpers.h
@@ -132,7 +132,16 @@ static inline void iwl_legacy_stop_queue(struct iwl_priv *priv,
132 ieee80211_stop_queue(priv->hw, ac); 132 ieee80211_stop_queue(priv->hw, ac);
133} 133}
134 134
135#ifdef ieee80211_stop_queue
136#undef ieee80211_stop_queue
137#endif
138
135#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue 139#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
140
141#ifdef ieee80211_wake_queue
142#undef ieee80211_wake_queue
143#endif
144
136#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue 145#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
137 146
138static inline void iwl_legacy_disable_interrupts(struct iwl_priv *priv) 147static inline void iwl_legacy_disable_interrupts(struct iwl_priv *priv)
diff --git a/drivers/net/wireless/iwlegacy/iwl-rx.c b/drivers/net/wireless/iwlegacy/iwl-rx.c
index 654cf233a384..9b5d0abe8be9 100644
--- a/drivers/net/wireless/iwlegacy/iwl-rx.c
+++ b/drivers/net/wireless/iwlegacy/iwl-rx.c
@@ -227,27 +227,6 @@ void iwl_legacy_rx_spectrum_measure_notif(struct iwl_priv *priv,
227} 227}
228EXPORT_SYMBOL(iwl_legacy_rx_spectrum_measure_notif); 228EXPORT_SYMBOL(iwl_legacy_rx_spectrum_measure_notif);
229 229
230void iwl_legacy_recover_from_statistics(struct iwl_priv *priv,
231 struct iwl_rx_packet *pkt)
232{
233 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
234 return;
235 if (iwl_legacy_is_any_associated(priv)) {
236 if (priv->cfg->ops->lib->check_plcp_health) {
237 if (!priv->cfg->ops->lib->check_plcp_health(
238 priv, pkt)) {
239 /*
240 * high plcp error detected
241 * reset Radio
242 */
243 iwl_legacy_force_reset(priv,
244 IWL_RF_RESET, false);
245 }
246 }
247 }
248}
249EXPORT_SYMBOL(iwl_legacy_recover_from_statistics);
250
251/* 230/*
252 * returns non-zero if packet should be dropped 231 * returns non-zero if packet should be dropped
253 */ 232 */
diff --git a/drivers/net/wireless/iwlegacy/iwl-scan.c b/drivers/net/wireless/iwlegacy/iwl-scan.c
index 353234a02c6d..a6b5222fc59e 100644
--- a/drivers/net/wireless/iwlegacy/iwl-scan.c
+++ b/drivers/net/wireless/iwlegacy/iwl-scan.c
@@ -101,7 +101,6 @@ static void iwl_legacy_complete_scan(struct iwl_priv *priv, bool aborted)
101 ieee80211_scan_completed(priv->hw, aborted); 101 ieee80211_scan_completed(priv->hw, aborted);
102 } 102 }
103 103
104 priv->is_internal_short_scan = false;
105 priv->scan_vif = NULL; 104 priv->scan_vif = NULL;
106 priv->scan_request = NULL; 105 priv->scan_request = NULL;
107} 106}
@@ -329,10 +328,8 @@ void iwl_legacy_init_scan_params(struct iwl_priv *priv)
329} 328}
330EXPORT_SYMBOL(iwl_legacy_init_scan_params); 329EXPORT_SYMBOL(iwl_legacy_init_scan_params);
331 330
332static int __must_check iwl_legacy_scan_initiate(struct iwl_priv *priv, 331static int iwl_legacy_scan_initiate(struct iwl_priv *priv,
333 struct ieee80211_vif *vif, 332 struct ieee80211_vif *vif)
334 bool internal,
335 enum ieee80211_band band)
336{ 333{
337 int ret; 334 int ret;
338 335
@@ -359,18 +356,14 @@ static int __must_check iwl_legacy_scan_initiate(struct iwl_priv *priv,
359 return -EBUSY; 356 return -EBUSY;
360 } 357 }
361 358
362 IWL_DEBUG_SCAN(priv, "Starting %sscan...\n", 359 IWL_DEBUG_SCAN(priv, "Starting scan...\n");
363 internal ? "internal short " : "");
364 360
365 set_bit(STATUS_SCANNING, &priv->status); 361 set_bit(STATUS_SCANNING, &priv->status);
366 priv->is_internal_short_scan = internal;
367 priv->scan_start = jiffies; 362 priv->scan_start = jiffies;
368 priv->scan_band = band;
369 363
370 ret = priv->cfg->ops->utils->request_scan(priv, vif); 364 ret = priv->cfg->ops->utils->request_scan(priv, vif);
371 if (ret) { 365 if (ret) {
372 clear_bit(STATUS_SCANNING, &priv->status); 366 clear_bit(STATUS_SCANNING, &priv->status);
373 priv->is_internal_short_scan = false;
374 return ret; 367 return ret;
375 } 368 }
376 369
@@ -394,8 +387,7 @@ int iwl_legacy_mac_hw_scan(struct ieee80211_hw *hw,
394 387
395 mutex_lock(&priv->mutex); 388 mutex_lock(&priv->mutex);
396 389
397 if (test_bit(STATUS_SCANNING, &priv->status) && 390 if (test_bit(STATUS_SCANNING, &priv->status)) {
398 !priv->is_internal_short_scan) {
399 IWL_DEBUG_SCAN(priv, "Scan already in progress.\n"); 391 IWL_DEBUG_SCAN(priv, "Scan already in progress.\n");
400 ret = -EAGAIN; 392 ret = -EAGAIN;
401 goto out_unlock; 393 goto out_unlock;
@@ -404,17 +396,9 @@ int iwl_legacy_mac_hw_scan(struct ieee80211_hw *hw,
404 /* mac80211 will only ask for one band at a time */ 396 /* mac80211 will only ask for one band at a time */
405 priv->scan_request = req; 397 priv->scan_request = req;
406 priv->scan_vif = vif; 398 priv->scan_vif = vif;
399 priv->scan_band = req->channels[0]->band;
407 400
408 /* 401 ret = iwl_legacy_scan_initiate(priv, vif);
409 * If an internal scan is in progress, just set
410 * up the scan_request as per above.
411 */
412 if (priv->is_internal_short_scan) {
413 IWL_DEBUG_SCAN(priv, "SCAN request during internal scan\n");
414 ret = 0;
415 } else
416 ret = iwl_legacy_scan_initiate(priv, vif, false,
417 req->channels[0]->band);
418 402
419 IWL_DEBUG_MAC80211(priv, "leave\n"); 403 IWL_DEBUG_MAC80211(priv, "leave\n");
420 404
@@ -425,40 +409,6 @@ out_unlock:
425} 409}
426EXPORT_SYMBOL(iwl_legacy_mac_hw_scan); 410EXPORT_SYMBOL(iwl_legacy_mac_hw_scan);
427 411
428/*
429 * internal short scan, this function should only been called while associated.
430 * It will reset and tune the radio to prevent possible RF related problem
431 */
432void iwl_legacy_internal_short_hw_scan(struct iwl_priv *priv)
433{
434 queue_work(priv->workqueue, &priv->start_internal_scan);
435}
436
437static void iwl_legacy_bg_start_internal_scan(struct work_struct *work)
438{
439 struct iwl_priv *priv =
440 container_of(work, struct iwl_priv, start_internal_scan);
441
442 IWL_DEBUG_SCAN(priv, "Start internal scan\n");
443
444 mutex_lock(&priv->mutex);
445
446 if (priv->is_internal_short_scan == true) {
447 IWL_DEBUG_SCAN(priv, "Internal scan already in progress\n");
448 goto unlock;
449 }
450
451 if (test_bit(STATUS_SCANNING, &priv->status)) {
452 IWL_DEBUG_SCAN(priv, "Scan already in progress.\n");
453 goto unlock;
454 }
455
456 if (iwl_legacy_scan_initiate(priv, NULL, true, priv->band))
457 IWL_DEBUG_SCAN(priv, "failed to start internal short scan\n");
458 unlock:
459 mutex_unlock(&priv->mutex);
460}
461
462static void iwl_legacy_bg_scan_check(struct work_struct *data) 412static void iwl_legacy_bg_scan_check(struct work_struct *data)
463{ 413{
464 struct iwl_priv *priv = 414 struct iwl_priv *priv =
@@ -542,8 +492,7 @@ static void iwl_legacy_bg_scan_completed(struct work_struct *work)
542 container_of(work, struct iwl_priv, scan_completed); 492 container_of(work, struct iwl_priv, scan_completed);
543 bool aborted; 493 bool aborted;
544 494
545 IWL_DEBUG_SCAN(priv, "Completed %sscan.\n", 495 IWL_DEBUG_SCAN(priv, "Completed scan.\n");
546 priv->is_internal_short_scan ? "internal short " : "");
547 496
548 cancel_delayed_work(&priv->scan_check); 497 cancel_delayed_work(&priv->scan_check);
549 498
@@ -558,27 +507,6 @@ static void iwl_legacy_bg_scan_completed(struct work_struct *work)
558 goto out_settings; 507 goto out_settings;
559 } 508 }
560 509
561 if (priv->is_internal_short_scan && !aborted) {
562 int err;
563
564 /* Check if mac80211 requested scan during our internal scan */
565 if (priv->scan_request == NULL)
566 goto out_complete;
567
568 /* If so request a new scan */
569 err = iwl_legacy_scan_initiate(priv, priv->scan_vif, false,
570 priv->scan_request->channels[0]->band);
571 if (err) {
572 IWL_DEBUG_SCAN(priv,
573 "failed to initiate pending scan: %d\n", err);
574 aborted = true;
575 goto out_complete;
576 }
577
578 goto out;
579 }
580
581out_complete:
582 iwl_legacy_complete_scan(priv, aborted); 510 iwl_legacy_complete_scan(priv, aborted);
583 511
584out_settings: 512out_settings:
@@ -590,8 +518,7 @@ out_settings:
590 * We do not commit power settings while scan is pending, 518 * We do not commit power settings while scan is pending,
591 * do it now if the settings changed. 519 * do it now if the settings changed.
592 */ 520 */
593 iwl_legacy_power_set_mode(priv, &priv->power_data.sleep_cmd_next, 521 iwl_legacy_power_set_mode(priv, &priv->power_data.sleep_cmd_next, false);
594 false);
595 iwl_legacy_set_tx_power(priv, priv->tx_power_next, false); 522 iwl_legacy_set_tx_power(priv, priv->tx_power_next, false);
596 523
597 priv->cfg->ops->utils->post_scan(priv); 524 priv->cfg->ops->utils->post_scan(priv);
@@ -604,15 +531,12 @@ void iwl_legacy_setup_scan_deferred_work(struct iwl_priv *priv)
604{ 531{
605 INIT_WORK(&priv->scan_completed, iwl_legacy_bg_scan_completed); 532 INIT_WORK(&priv->scan_completed, iwl_legacy_bg_scan_completed);
606 INIT_WORK(&priv->abort_scan, iwl_legacy_bg_abort_scan); 533 INIT_WORK(&priv->abort_scan, iwl_legacy_bg_abort_scan);
607 INIT_WORK(&priv->start_internal_scan,
608 iwl_legacy_bg_start_internal_scan);
609 INIT_DELAYED_WORK(&priv->scan_check, iwl_legacy_bg_scan_check); 534 INIT_DELAYED_WORK(&priv->scan_check, iwl_legacy_bg_scan_check);
610} 535}
611EXPORT_SYMBOL(iwl_legacy_setup_scan_deferred_work); 536EXPORT_SYMBOL(iwl_legacy_setup_scan_deferred_work);
612 537
613void iwl_legacy_cancel_scan_deferred_work(struct iwl_priv *priv) 538void iwl_legacy_cancel_scan_deferred_work(struct iwl_priv *priv)
614{ 539{
615 cancel_work_sync(&priv->start_internal_scan);
616 cancel_work_sync(&priv->abort_scan); 540 cancel_work_sync(&priv->abort_scan);
617 cancel_work_sync(&priv->scan_completed); 541 cancel_work_sync(&priv->scan_completed);
618 542
diff --git a/drivers/net/wireless/iwlegacy/iwl3945-base.c b/drivers/net/wireless/iwlegacy/iwl3945-base.c
index 0ee6be6a9c5d..795826a014ed 100644
--- a/drivers/net/wireless/iwlegacy/iwl3945-base.c
+++ b/drivers/net/wireless/iwlegacy/iwl3945-base.c
@@ -1409,212 +1409,6 @@ void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
1409 } 1409 }
1410} 1410}
1411 1411
1412#define EVENT_START_OFFSET (6 * sizeof(u32))
1413
1414/**
1415 * iwl3945_print_event_log - Dump error event log to syslog
1416 *
1417 */
1418static int iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
1419 u32 num_events, u32 mode,
1420 int pos, char **buf, size_t bufsz)
1421{
1422 u32 i;
1423 u32 base; /* SRAM byte address of event log header */
1424 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1425 u32 ptr; /* SRAM byte address of log data */
1426 u32 ev, time, data; /* event log data */
1427 unsigned long reg_flags;
1428
1429 if (num_events == 0)
1430 return pos;
1431
1432 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1433
1434 if (mode == 0)
1435 event_size = 2 * sizeof(u32);
1436 else
1437 event_size = 3 * sizeof(u32);
1438
1439 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1440
1441 /* Make sure device is powered up for SRAM reads */
1442 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1443 iwl_grab_nic_access(priv);
1444
1445 /* Set starting address; reads will auto-increment */
1446 _iwl_legacy_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1447 rmb();
1448
1449 /* "time" is actually "data" for mode 0 (no timestamp).
1450 * place event id # at far right for easier visual parsing. */
1451 for (i = 0; i < num_events; i++) {
1452 ev = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1453 time = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1454 if (mode == 0) {
1455 /* data, ev */
1456 if (bufsz) {
1457 pos += scnprintf(*buf + pos, bufsz - pos,
1458 "0x%08x:%04u\n",
1459 time, ev);
1460 } else {
1461 IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
1462 trace_iwlwifi_legacy_dev_ucode_event(priv, 0,
1463 time, ev);
1464 }
1465 } else {
1466 data = _iwl_legacy_read_direct32(priv,
1467 HBUS_TARG_MEM_RDAT);
1468 if (bufsz) {
1469 pos += scnprintf(*buf + pos, bufsz - pos,
1470 "%010u:0x%08x:%04u\n",
1471 time, data, ev);
1472 } else {
1473 IWL_ERR(priv, "%010u\t0x%08x\t%04u\n",
1474 time, data, ev);
1475 trace_iwlwifi_legacy_dev_ucode_event(priv, time,
1476 data, ev);
1477 }
1478 }
1479 }
1480
1481 /* Allow device to power down */
1482 iwl_release_nic_access(priv);
1483 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
1484 return pos;
1485}
1486
1487/**
1488 * iwl3945_print_last_event_logs - Dump the newest # of event log to syslog
1489 */
1490static int iwl3945_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1491 u32 num_wraps, u32 next_entry,
1492 u32 size, u32 mode,
1493 int pos, char **buf, size_t bufsz)
1494{
1495 /*
1496 * display the newest DEFAULT_LOG_ENTRIES entries
1497 * i.e the entries just before the next ont that uCode would fill.
1498 */
1499 if (num_wraps) {
1500 if (next_entry < size) {
1501 pos = iwl3945_print_event_log(priv,
1502 capacity - (size - next_entry),
1503 size - next_entry, mode,
1504 pos, buf, bufsz);
1505 pos = iwl3945_print_event_log(priv, 0,
1506 next_entry, mode,
1507 pos, buf, bufsz);
1508 } else
1509 pos = iwl3945_print_event_log(priv, next_entry - size,
1510 size, mode,
1511 pos, buf, bufsz);
1512 } else {
1513 if (next_entry < size)
1514 pos = iwl3945_print_event_log(priv, 0,
1515 next_entry, mode,
1516 pos, buf, bufsz);
1517 else
1518 pos = iwl3945_print_event_log(priv, next_entry - size,
1519 size, mode,
1520 pos, buf, bufsz);
1521 }
1522 return pos;
1523}
1524
1525#define DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES (20)
1526
1527int iwl3945_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1528 char **buf, bool display)
1529{
1530 u32 base; /* SRAM byte address of event log header */
1531 u32 capacity; /* event log capacity in # entries */
1532 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1533 u32 num_wraps; /* # times uCode wrapped to top of log */
1534 u32 next_entry; /* index of next entry to be written by uCode */
1535 u32 size; /* # entries that we'll print */
1536 int pos = 0;
1537 size_t bufsz = 0;
1538
1539 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1540 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
1541 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1542 return -EINVAL;
1543 }
1544
1545 /* event log header */
1546 capacity = iwl_legacy_read_targ_mem(priv, base);
1547 mode = iwl_legacy_read_targ_mem(priv, base + (1 * sizeof(u32)));
1548 num_wraps = iwl_legacy_read_targ_mem(priv, base + (2 * sizeof(u32)));
1549 next_entry = iwl_legacy_read_targ_mem(priv, base + (3 * sizeof(u32)));
1550
1551 if (capacity > priv->cfg->base_params->max_event_log_size) {
1552 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1553 capacity, priv->cfg->base_params->max_event_log_size);
1554 capacity = priv->cfg->base_params->max_event_log_size;
1555 }
1556
1557 if (next_entry > priv->cfg->base_params->max_event_log_size) {
1558 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1559 next_entry, priv->cfg->base_params->max_event_log_size);
1560 next_entry = priv->cfg->base_params->max_event_log_size;
1561 }
1562
1563 size = num_wraps ? capacity : next_entry;
1564
1565 /* bail out if nothing in log */
1566 if (size == 0) {
1567 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1568 return pos;
1569 }
1570
1571#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
1572 if (!(iwl_legacy_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
1573 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1574 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1575#else
1576 size = (size > DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES)
1577 ? DEFAULT_IWL3945_DUMP_EVENT_LOG_ENTRIES : size;
1578#endif
1579
1580 IWL_ERR(priv, "Start IWL Event Log Dump: display last %d count\n",
1581 size);
1582
1583#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
1584 if (display) {
1585 if (full_log)
1586 bufsz = capacity * 48;
1587 else
1588 bufsz = size * 48;
1589 *buf = kmalloc(bufsz, GFP_KERNEL);
1590 if (!*buf)
1591 return -ENOMEM;
1592 }
1593 if ((iwl_legacy_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1594 /* if uCode has wrapped back to top of log,
1595 * start at the oldest entry,
1596 * i.e the next one that uCode would fill.
1597 */
1598 if (num_wraps)
1599 pos = iwl3945_print_event_log(priv, next_entry,
1600 capacity - next_entry, mode,
1601 pos, buf, bufsz);
1602
1603 /* (then/else) start at top of log */
1604 pos = iwl3945_print_event_log(priv, 0, next_entry, mode,
1605 pos, buf, bufsz);
1606 } else
1607 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1608 next_entry, size, mode,
1609 pos, buf, bufsz);
1610#else
1611 pos = iwl3945_print_last_event_logs(priv, capacity, num_wraps,
1612 next_entry, size, mode,
1613 pos, buf, bufsz);
1614#endif
1615 return pos;
1616}
1617
1618static void iwl3945_irq_tasklet(struct iwl_priv *priv) 1412static void iwl3945_irq_tasklet(struct iwl_priv *priv)
1619{ 1413{
1620 u32 inta, handled = 0; 1414 u32 inta, handled = 0;
@@ -1762,49 +1556,6 @@ static void iwl3945_irq_tasklet(struct iwl_priv *priv)
1762#endif 1556#endif
1763} 1557}
1764 1558
1765static int iwl3945_get_single_channel_for_scan(struct iwl_priv *priv,
1766 struct ieee80211_vif *vif,
1767 enum ieee80211_band band,
1768 struct iwl3945_scan_channel *scan_ch)
1769{
1770 const struct ieee80211_supported_band *sband;
1771 u16 passive_dwell = 0;
1772 u16 active_dwell = 0;
1773 int added = 0;
1774 u8 channel = 0;
1775
1776 sband = iwl_get_hw_mode(priv, band);
1777 if (!sband) {
1778 IWL_ERR(priv, "invalid band\n");
1779 return added;
1780 }
1781
1782 active_dwell = iwl_legacy_get_active_dwell_time(priv, band, 0);
1783 passive_dwell = iwl_legacy_get_passive_dwell_time(priv, band, vif);
1784
1785 if (passive_dwell <= active_dwell)
1786 passive_dwell = active_dwell + 1;
1787
1788
1789 channel = iwl_legacy_get_single_channel_number(priv, band);
1790
1791 if (channel) {
1792 scan_ch->channel = channel;
1793 scan_ch->type = 0; /* passive */
1794 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1795 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1796 /* Set txpower levels to defaults */
1797 scan_ch->tpc.dsp_atten = 110;
1798 if (band == IEEE80211_BAND_5GHZ)
1799 scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
1800 else
1801 scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
1802 added++;
1803 } else
1804 IWL_ERR(priv, "no valid channel found\n");
1805 return added;
1806}
1807
1808static int iwl3945_get_channels_for_scan(struct iwl_priv *priv, 1559static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
1809 enum ieee80211_band band, 1560 enum ieee80211_band band,
1810 u8 is_active, u8 n_probes, 1561 u8 is_active, u8 n_probes,
@@ -2816,6 +2567,7 @@ int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
2816 enum ieee80211_band band; 2567 enum ieee80211_band band;
2817 bool is_active = false; 2568 bool is_active = false;
2818 int ret; 2569 int ret;
2570 u16 len;
2819 2571
2820 lockdep_assert_held(&priv->mutex); 2572 lockdep_assert_held(&priv->mutex);
2821 2573
@@ -2834,17 +2586,14 @@ int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
2834 scan->quiet_time = IWL_ACTIVE_QUIET_TIME; 2586 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
2835 2587
2836 if (iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS)) { 2588 if (iwl_legacy_is_associated(priv, IWL_RXON_CTX_BSS)) {
2837 u16 interval = 0; 2589 u16 interval;
2838 u32 extra; 2590 u32 extra;
2839 u32 suspend_time = 100; 2591 u32 suspend_time = 100;
2840 u32 scan_suspend_time = 100; 2592 u32 scan_suspend_time = 100;
2841 2593
2842 IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); 2594 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
2843 2595
2844 if (priv->is_internal_short_scan) 2596 interval = vif->bss_conf.beacon_int;
2845 interval = 0;
2846 else
2847 interval = vif->bss_conf.beacon_int;
2848 2597
2849 scan->suspend_time = 0; 2598 scan->suspend_time = 0;
2850 scan->max_out_time = cpu_to_le32(200 * 1024); 2599 scan->max_out_time = cpu_to_le32(200 * 1024);
@@ -2866,9 +2615,7 @@ int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
2866 scan_suspend_time, interval); 2615 scan_suspend_time, interval);
2867 } 2616 }
2868 2617
2869 if (priv->is_internal_short_scan) { 2618 if (priv->scan_request->n_ssids) {
2870 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
2871 } else if (priv->scan_request->n_ssids) {
2872 int i, p = 0; 2619 int i, p = 0;
2873 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); 2620 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
2874 for (i = 0; i < priv->scan_request->n_ssids; i++) { 2621 for (i = 0; i < priv->scan_request->n_ssids; i++) {
@@ -2919,36 +2666,17 @@ int iwl3945_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
2919 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT : 2666 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
2920 IWL_GOOD_CRC_TH_DISABLED; 2667 IWL_GOOD_CRC_TH_DISABLED;
2921 2668
2922 if (!priv->is_internal_short_scan) { 2669 len = iwl_legacy_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
2923 scan->tx_cmd.len = cpu_to_le16( 2670 vif->addr, priv->scan_request->ie,
2924 iwl_legacy_fill_probe_req(priv, 2671 priv->scan_request->ie_len,
2925 (struct ieee80211_mgmt *)scan->data, 2672 IWL_MAX_SCAN_SIZE - sizeof(*scan));
2926 vif->addr, 2673 scan->tx_cmd.len = cpu_to_le16(len);
2927 priv->scan_request->ie, 2674
2928 priv->scan_request->ie_len,
2929 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
2930 } else {
2931 /* use bcast addr, will not be transmitted but must be valid */
2932 scan->tx_cmd.len = cpu_to_le16(
2933 iwl_legacy_fill_probe_req(priv,
2934 (struct ieee80211_mgmt *)scan->data,
2935 iwlegacy_bcast_addr, NULL, 0,
2936 IWL_MAX_SCAN_SIZE - sizeof(*scan)));
2937 }
2938 /* select Rx antennas */ 2675 /* select Rx antennas */
2939 scan->flags |= iwl3945_get_antenna_flags(priv); 2676 scan->flags |= iwl3945_get_antenna_flags(priv);
2940 2677
2941 if (priv->is_internal_short_scan) { 2678 scan->channel_count = iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
2942 scan->channel_count = 2679 (void *)&scan->data[len], vif);
2943 iwl3945_get_single_channel_for_scan(priv, vif, band,
2944 (void *)&scan->data[le16_to_cpu(
2945 scan->tx_cmd.len)]);
2946 } else {
2947 scan->channel_count =
2948 iwl3945_get_channels_for_scan(priv, band, is_active, n_probes,
2949 (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)], vif);
2950 }
2951
2952 if (scan->channel_count == 0) { 2680 if (scan->channel_count == 0) {
2953 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); 2681 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
2954 return -EIO; 2682 return -EIO;
@@ -3824,10 +3552,7 @@ static int iwl3945_init_drv(struct iwl_priv *priv)
3824 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; 3552 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3825 3553
3826 /* initialize force reset */ 3554 /* initialize force reset */
3827 priv->force_reset[IWL_RF_RESET].reset_duration = 3555 priv->force_reset.reset_duration = IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3828 IWL_DELAY_NEXT_FORCE_RF_RESET;
3829 priv->force_reset[IWL_FW_RESET].reset_duration =
3830 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3831 3556
3832 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) { 3557 if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
3833 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n", 3558 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
diff --git a/drivers/net/wireless/iwlegacy/iwl4965-base.c b/drivers/net/wireless/iwlegacy/iwl4965-base.c
index 7157ba529680..14334668034e 100644
--- a/drivers/net/wireless/iwlegacy/iwl4965-base.c
+++ b/drivers/net/wireless/iwlegacy/iwl4965-base.c
@@ -488,134 +488,6 @@ static void iwl4965_bg_statistics_periodic(unsigned long data)
488 iwl_legacy_send_statistics_request(priv, CMD_ASYNC, false); 488 iwl_legacy_send_statistics_request(priv, CMD_ASYNC, false);
489} 489}
490 490
491
492static void iwl4965_print_cont_event_trace(struct iwl_priv *priv, u32 base,
493 u32 start_idx, u32 num_events,
494 u32 mode)
495{
496 u32 i;
497 u32 ptr; /* SRAM byte address of log data */
498 u32 ev, time, data; /* event log data */
499 unsigned long reg_flags;
500
501 if (mode == 0)
502 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
503 else
504 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
505
506 /* Make sure device is powered up for SRAM reads */
507 spin_lock_irqsave(&priv->reg_lock, reg_flags);
508 if (iwl_grab_nic_access(priv)) {
509 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
510 return;
511 }
512
513 /* Set starting address; reads will auto-increment */
514 _iwl_legacy_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
515 rmb();
516
517 /*
518 * "time" is actually "data" for mode 0 (no timestamp).
519 * place event id # at far right for easier visual parsing.
520 */
521 for (i = 0; i < num_events; i++) {
522 ev = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
523 time = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
524 if (mode == 0) {
525 trace_iwlwifi_legacy_dev_ucode_cont_event(priv,
526 0, time, ev);
527 } else {
528 data = _iwl_legacy_read_direct32(priv,
529 HBUS_TARG_MEM_RDAT);
530 trace_iwlwifi_legacy_dev_ucode_cont_event(priv,
531 time, data, ev);
532 }
533 }
534 /* Allow device to power down */
535 iwl_release_nic_access(priv);
536 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
537}
538
539static void iwl4965_continuous_event_trace(struct iwl_priv *priv)
540{
541 u32 capacity; /* event log capacity in # entries */
542 u32 base; /* SRAM byte address of event log header */
543 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
544 u32 num_wraps; /* # times uCode wrapped to top of log */
545 u32 next_entry; /* index of next entry to be written by uCode */
546
547 if (priv->ucode_type == UCODE_INIT)
548 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
549 else
550 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
551 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
552 capacity = iwl_legacy_read_targ_mem(priv, base);
553 num_wraps = iwl_legacy_read_targ_mem(priv,
554 base + (2 * sizeof(u32)));
555 mode = iwl_legacy_read_targ_mem(priv, base + (1 * sizeof(u32)));
556 next_entry = iwl_legacy_read_targ_mem(priv,
557 base + (3 * sizeof(u32)));
558 } else
559 return;
560
561 if (num_wraps == priv->event_log.num_wraps) {
562 iwl4965_print_cont_event_trace(priv,
563 base, priv->event_log.next_entry,
564 next_entry - priv->event_log.next_entry,
565 mode);
566 priv->event_log.non_wraps_count++;
567 } else {
568 if ((num_wraps - priv->event_log.num_wraps) > 1)
569 priv->event_log.wraps_more_count++;
570 else
571 priv->event_log.wraps_once_count++;
572 trace_iwlwifi_legacy_dev_ucode_wrap_event(priv,
573 num_wraps - priv->event_log.num_wraps,
574 next_entry, priv->event_log.next_entry);
575 if (next_entry < priv->event_log.next_entry) {
576 iwl4965_print_cont_event_trace(priv, base,
577 priv->event_log.next_entry,
578 capacity - priv->event_log.next_entry,
579 mode);
580
581 iwl4965_print_cont_event_trace(priv, base, 0,
582 next_entry, mode);
583 } else {
584 iwl4965_print_cont_event_trace(priv, base,
585 next_entry, capacity - next_entry,
586 mode);
587
588 iwl4965_print_cont_event_trace(priv, base, 0,
589 next_entry, mode);
590 }
591 }
592 priv->event_log.num_wraps = num_wraps;
593 priv->event_log.next_entry = next_entry;
594}
595
596/**
597 * iwl4965_bg_ucode_trace - Timer callback to log ucode event
598 *
599 * The timer is continually set to execute every
600 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
601 * this function is to perform continuous uCode event logging operation
602 * if enabled
603 */
604static void iwl4965_bg_ucode_trace(unsigned long data)
605{
606 struct iwl_priv *priv = (struct iwl_priv *)data;
607
608 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
609 return;
610
611 if (priv->event_log.ucode_trace) {
612 iwl4965_continuous_event_trace(priv);
613 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
614 mod_timer(&priv->ucode_trace,
615 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
616 }
617}
618
619static void iwl4965_rx_beacon_notif(struct iwl_priv *priv, 491static void iwl4965_rx_beacon_notif(struct iwl_priv *priv,
620 struct iwl_rx_mem_buffer *rxb) 492 struct iwl_rx_mem_buffer *rxb)
621{ 493{
@@ -1612,7 +1484,7 @@ static const char * const desc_lookup_text[] = {
1612 "NMI_INTERRUPT_DATA_ACTION_PT", 1484 "NMI_INTERRUPT_DATA_ACTION_PT",
1613 "NMI_TRM_HW_ER", 1485 "NMI_TRM_HW_ER",
1614 "NMI_INTERRUPT_TRM", 1486 "NMI_INTERRUPT_TRM",
1615 "NMI_INTERRUPT_BREAK_POINT" 1487 "NMI_INTERRUPT_BREAK_POINT",
1616 "DEBUG_0", 1488 "DEBUG_0",
1617 "DEBUG_1", 1489 "DEBUG_1",
1618 "DEBUG_2", 1490 "DEBUG_2",
@@ -1711,209 +1583,6 @@ void iwl4965_dump_nic_error_log(struct iwl_priv *priv)
1711 pc, blink1, blink2, ilink1, ilink2, hcmd); 1583 pc, blink1, blink2, ilink1, ilink2, hcmd);
1712} 1584}
1713 1585
1714#define EVENT_START_OFFSET (4 * sizeof(u32))
1715
1716/**
1717 * iwl4965_print_event_log - Dump error event log to syslog
1718 *
1719 */
1720static int iwl4965_print_event_log(struct iwl_priv *priv, u32 start_idx,
1721 u32 num_events, u32 mode,
1722 int pos, char **buf, size_t bufsz)
1723{
1724 u32 i;
1725 u32 base; /* SRAM byte address of event log header */
1726 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1727 u32 ptr; /* SRAM byte address of log data */
1728 u32 ev, time, data; /* event log data */
1729 unsigned long reg_flags;
1730
1731 if (num_events == 0)
1732 return pos;
1733
1734 if (priv->ucode_type == UCODE_INIT) {
1735 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1736 } else {
1737 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1738 }
1739
1740 if (mode == 0)
1741 event_size = 2 * sizeof(u32);
1742 else
1743 event_size = 3 * sizeof(u32);
1744
1745 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1746
1747 /* Make sure device is powered up for SRAM reads */
1748 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1749 iwl_grab_nic_access(priv);
1750
1751 /* Set starting address; reads will auto-increment */
1752 _iwl_legacy_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1753 rmb();
1754
1755 /* "time" is actually "data" for mode 0 (no timestamp).
1756 * place event id # at far right for easier visual parsing. */
1757 for (i = 0; i < num_events; i++) {
1758 ev = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1759 time = _iwl_legacy_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1760 if (mode == 0) {
1761 /* data, ev */
1762 if (bufsz) {
1763 pos += scnprintf(*buf + pos, bufsz - pos,
1764 "EVT_LOG:0x%08x:%04u\n",
1765 time, ev);
1766 } else {
1767 trace_iwlwifi_legacy_dev_ucode_event(priv, 0,
1768 time, ev);
1769 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1770 time, ev);
1771 }
1772 } else {
1773 data = _iwl_legacy_read_direct32(priv,
1774 HBUS_TARG_MEM_RDAT);
1775 if (bufsz) {
1776 pos += scnprintf(*buf + pos, bufsz - pos,
1777 "EVT_LOGT:%010u:0x%08x:%04u\n",
1778 time, data, ev);
1779 } else {
1780 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1781 time, data, ev);
1782 trace_iwlwifi_legacy_dev_ucode_event(priv, time,
1783 data, ev);
1784 }
1785 }
1786 }
1787
1788 /* Allow device to power down */
1789 iwl_release_nic_access(priv);
1790 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
1791 return pos;
1792}
1793
1794/**
1795 * iwl4965_print_last_event_logs - Dump the newest # of event log to syslog
1796 */
1797static int iwl4965_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1798 u32 num_wraps, u32 next_entry,
1799 u32 size, u32 mode,
1800 int pos, char **buf, size_t bufsz)
1801{
1802 /*
1803 * display the newest DEFAULT_LOG_ENTRIES entries
1804 * i.e the entries just before the next ont that uCode would fill.
1805 */
1806 if (num_wraps) {
1807 if (next_entry < size) {
1808 pos = iwl4965_print_event_log(priv,
1809 capacity - (size - next_entry),
1810 size - next_entry, mode,
1811 pos, buf, bufsz);
1812 pos = iwl4965_print_event_log(priv, 0,
1813 next_entry, mode,
1814 pos, buf, bufsz);
1815 } else
1816 pos = iwl4965_print_event_log(priv, next_entry - size,
1817 size, mode, pos, buf, bufsz);
1818 } else {
1819 if (next_entry < size) {
1820 pos = iwl4965_print_event_log(priv, 0, next_entry,
1821 mode, pos, buf, bufsz);
1822 } else {
1823 pos = iwl4965_print_event_log(priv, next_entry - size,
1824 size, mode, pos, buf, bufsz);
1825 }
1826 }
1827 return pos;
1828}
1829
1830#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
1831
1832int iwl4965_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1833 char **buf, bool display)
1834{
1835 u32 base; /* SRAM byte address of event log header */
1836 u32 capacity; /* event log capacity in # entries */
1837 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1838 u32 num_wraps; /* # times uCode wrapped to top of log */
1839 u32 next_entry; /* index of next entry to be written by uCode */
1840 u32 size; /* # entries that we'll print */
1841 int pos = 0;
1842 size_t bufsz = 0;
1843
1844 if (priv->ucode_type == UCODE_INIT) {
1845 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1846 } else {
1847 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1848 }
1849
1850 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1851 IWL_ERR(priv,
1852 "Invalid event log pointer 0x%08X for %s uCode\n",
1853 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
1854 return -EINVAL;
1855 }
1856
1857 /* event log header */
1858 capacity = iwl_legacy_read_targ_mem(priv, base);
1859 mode = iwl_legacy_read_targ_mem(priv, base + (1 * sizeof(u32)));
1860 num_wraps = iwl_legacy_read_targ_mem(priv, base + (2 * sizeof(u32)));
1861 next_entry = iwl_legacy_read_targ_mem(priv, base + (3 * sizeof(u32)));
1862
1863 size = num_wraps ? capacity : next_entry;
1864
1865 /* bail out if nothing in log */
1866 if (size == 0) {
1867 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1868 return pos;
1869 }
1870
1871#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
1872 if (!(iwl_legacy_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
1873 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1874 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1875#else
1876 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1877 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1878#endif
1879 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
1880 size);
1881
1882#ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
1883 if (display) {
1884 if (full_log)
1885 bufsz = capacity * 48;
1886 else
1887 bufsz = size * 48;
1888 *buf = kmalloc(bufsz, GFP_KERNEL);
1889 if (!*buf)
1890 return -ENOMEM;
1891 }
1892 if ((iwl_legacy_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1893 /*
1894 * if uCode has wrapped back to top of log,
1895 * start at the oldest entry,
1896 * i.e the next one that uCode would fill.
1897 */
1898 if (num_wraps)
1899 pos = iwl4965_print_event_log(priv, next_entry,
1900 capacity - next_entry, mode,
1901 pos, buf, bufsz);
1902 /* (then/else) start at top of log */
1903 pos = iwl4965_print_event_log(priv, 0,
1904 next_entry, mode, pos, buf, bufsz);
1905 } else
1906 pos = iwl4965_print_last_event_logs(priv, capacity, num_wraps,
1907 next_entry, size, mode,
1908 pos, buf, bufsz);
1909#else
1910 pos = iwl4965_print_last_event_logs(priv, capacity, num_wraps,
1911 next_entry, size, mode,
1912 pos, buf, bufsz);
1913#endif
1914 return pos;
1915}
1916
1917static void iwl4965_rf_kill_ct_config(struct iwl_priv *priv) 1586static void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
1918{ 1587{
1919 struct iwl_ct_kill_config cmd; 1588 struct iwl_ct_kill_config cmd;
@@ -2773,20 +2442,10 @@ int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
2773 case IEEE80211_AMPDU_TX_START: 2442 case IEEE80211_AMPDU_TX_START:
2774 IWL_DEBUG_HT(priv, "start Tx\n"); 2443 IWL_DEBUG_HT(priv, "start Tx\n");
2775 ret = iwl4965_tx_agg_start(priv, vif, sta, tid, ssn); 2444 ret = iwl4965_tx_agg_start(priv, vif, sta, tid, ssn);
2776 if (ret == 0) {
2777 priv->_4965.agg_tids_count++;
2778 IWL_DEBUG_HT(priv, "priv->_4965.agg_tids_count = %u\n",
2779 priv->_4965.agg_tids_count);
2780 }
2781 break; 2445 break;
2782 case IEEE80211_AMPDU_TX_STOP: 2446 case IEEE80211_AMPDU_TX_STOP:
2783 IWL_DEBUG_HT(priv, "stop Tx\n"); 2447 IWL_DEBUG_HT(priv, "stop Tx\n");
2784 ret = iwl4965_tx_agg_stop(priv, vif, sta, tid); 2448 ret = iwl4965_tx_agg_stop(priv, vif, sta, tid);
2785 if ((ret == 0) && (priv->_4965.agg_tids_count > 0)) {
2786 priv->_4965.agg_tids_count--;
2787 IWL_DEBUG_HT(priv, "priv->_4965.agg_tids_count = %u\n",
2788 priv->_4965.agg_tids_count);
2789 }
2790 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 2449 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2791 ret = 0; 2450 ret = 0;
2792 break; 2451 break;
@@ -2851,7 +2510,6 @@ void iwl4965_mac_channel_switch(struct ieee80211_hw *hw,
2851 2510
2852 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; 2511 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2853 u16 ch; 2512 u16 ch;
2854 unsigned long flags = 0;
2855 2513
2856 IWL_DEBUG_MAC80211(priv, "enter\n"); 2514 IWL_DEBUG_MAC80211(priv, "enter\n");
2857 2515
@@ -2868,64 +2526,64 @@ void iwl4965_mac_channel_switch(struct ieee80211_hw *hw,
2868 if (!iwl_legacy_is_associated_ctx(ctx)) 2526 if (!iwl_legacy_is_associated_ctx(ctx))
2869 goto out; 2527 goto out;
2870 2528
2871 if (priv->cfg->ops->lib->set_channel_switch) { 2529 if (!priv->cfg->ops->lib->set_channel_switch)
2530 goto out;
2872 2531
2873 ch = channel->hw_value; 2532 ch = channel->hw_value;
2874 if (le16_to_cpu(ctx->active.channel) != ch) { 2533 if (le16_to_cpu(ctx->active.channel) == ch)
2875 ch_info = iwl_legacy_get_channel_info(priv, 2534 goto out;
2876 channel->band, 2535
2877 ch); 2536 ch_info = iwl_legacy_get_channel_info(priv, channel->band, ch);
2878 if (!iwl_legacy_is_channel_valid(ch_info)) { 2537 if (!iwl_legacy_is_channel_valid(ch_info)) {
2879 IWL_DEBUG_MAC80211(priv, "invalid channel\n"); 2538 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
2880 goto out; 2539 goto out;
2881 } 2540 }
2882 spin_lock_irqsave(&priv->lock, flags); 2541
2883 2542 spin_lock_irq(&priv->lock);
2884 priv->current_ht_config.smps = conf->smps_mode; 2543
2885 2544 priv->current_ht_config.smps = conf->smps_mode;
2886 /* Configure HT40 channels */ 2545
2887 ctx->ht.enabled = conf_is_ht(conf); 2546 /* Configure HT40 channels */
2888 if (ctx->ht.enabled) { 2547 ctx->ht.enabled = conf_is_ht(conf);
2889 if (conf_is_ht40_minus(conf)) { 2548 if (ctx->ht.enabled) {
2890 ctx->ht.extension_chan_offset = 2549 if (conf_is_ht40_minus(conf)) {
2891 IEEE80211_HT_PARAM_CHA_SEC_BELOW; 2550 ctx->ht.extension_chan_offset =
2892 ctx->ht.is_40mhz = true; 2551 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2893 } else if (conf_is_ht40_plus(conf)) { 2552 ctx->ht.is_40mhz = true;
2894 ctx->ht.extension_chan_offset = 2553 } else if (conf_is_ht40_plus(conf)) {
2895 IEEE80211_HT_PARAM_CHA_SEC_ABOVE; 2554 ctx->ht.extension_chan_offset =
2896 ctx->ht.is_40mhz = true; 2555 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2897 } else { 2556 ctx->ht.is_40mhz = true;
2898 ctx->ht.extension_chan_offset = 2557 } else {
2899 IEEE80211_HT_PARAM_CHA_SEC_NONE; 2558 ctx->ht.extension_chan_offset =
2900 ctx->ht.is_40mhz = false; 2559 IEEE80211_HT_PARAM_CHA_SEC_NONE;
2901 } 2560 ctx->ht.is_40mhz = false;
2902 } else
2903 ctx->ht.is_40mhz = false;
2904
2905 if ((le16_to_cpu(ctx->staging.channel) != ch))
2906 ctx->staging.flags = 0;
2907
2908 iwl_legacy_set_rxon_channel(priv, channel, ctx);
2909 iwl_legacy_set_rxon_ht(priv, ht_conf);
2910 iwl_legacy_set_flags_for_band(priv, ctx, channel->band,
2911 ctx->vif);
2912 spin_unlock_irqrestore(&priv->lock, flags);
2913
2914 iwl_legacy_set_rate(priv);
2915 /*
2916 * at this point, staging_rxon has the
2917 * configuration for channel switch
2918 */
2919 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
2920 priv->switch_channel = cpu_to_le16(ch);
2921 if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) {
2922 clear_bit(STATUS_CHANNEL_SWITCH_PENDING,
2923 &priv->status);
2924 priv->switch_channel = 0;
2925 ieee80211_chswitch_done(ctx->vif, false);
2926 }
2927 } 2561 }
2562 } else
2563 ctx->ht.is_40mhz = false;
2564
2565 if ((le16_to_cpu(ctx->staging.channel) != ch))
2566 ctx->staging.flags = 0;
2567
2568 iwl_legacy_set_rxon_channel(priv, channel, ctx);
2569 iwl_legacy_set_rxon_ht(priv, ht_conf);
2570 iwl_legacy_set_flags_for_band(priv, ctx, channel->band, ctx->vif);
2571
2572 spin_unlock_irq(&priv->lock);
2573
2574 iwl_legacy_set_rate(priv);
2575 /*
2576 * at this point, staging_rxon has the
2577 * configuration for channel switch
2578 */
2579 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
2580 priv->switch_channel = cpu_to_le16(ch);
2581 if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) {
2582 clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
2583 priv->switch_channel = 0;
2584 ieee80211_chswitch_done(ctx->vif, false);
2928 } 2585 }
2586
2929out: 2587out:
2930 mutex_unlock(&priv->mutex); 2588 mutex_unlock(&priv->mutex);
2931 IWL_DEBUG_MAC80211(priv, "leave\n"); 2589 IWL_DEBUG_MAC80211(priv, "leave\n");
@@ -3034,10 +2692,6 @@ static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
3034 priv->statistics_periodic.data = (unsigned long)priv; 2692 priv->statistics_periodic.data = (unsigned long)priv;
3035 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic; 2693 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
3036 2694
3037 init_timer(&priv->ucode_trace);
3038 priv->ucode_trace.data = (unsigned long)priv;
3039 priv->ucode_trace.function = iwl4965_bg_ucode_trace;
3040
3041 init_timer(&priv->watchdog); 2695 init_timer(&priv->watchdog);
3042 priv->watchdog.data = (unsigned long)priv; 2696 priv->watchdog.data = (unsigned long)priv;
3043 priv->watchdog.function = iwl_legacy_bg_watchdog; 2697 priv->watchdog.function = iwl_legacy_bg_watchdog;
@@ -3056,7 +2710,6 @@ static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
3056 iwl_legacy_cancel_scan_deferred_work(priv); 2710 iwl_legacy_cancel_scan_deferred_work(priv);
3057 2711
3058 del_timer_sync(&priv->statistics_periodic); 2712 del_timer_sync(&priv->statistics_periodic);
3059 del_timer_sync(&priv->ucode_trace);
3060} 2713}
3061 2714
3062static void iwl4965_init_hw_rates(struct iwl_priv *priv, 2715static void iwl4965_init_hw_rates(struct iwl_priv *priv,
@@ -3132,13 +2785,9 @@ static int iwl4965_init_drv(struct iwl_priv *priv)
3132 priv->iw_mode = NL80211_IFTYPE_STATION; 2785 priv->iw_mode = NL80211_IFTYPE_STATION;
3133 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; 2786 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3134 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; 2787 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3135 priv->_4965.agg_tids_count = 0;
3136 2788
3137 /* initialize force reset */ 2789 /* initialize force reset */
3138 priv->force_reset[IWL_RF_RESET].reset_duration = 2790 priv->force_reset.reset_duration = IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3139 IWL_DELAY_NEXT_FORCE_RF_RESET;
3140 priv->force_reset[IWL_FW_RESET].reset_duration =
3141 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3142 2791
3143 /* Choose which receivers/antennas to use */ 2792 /* Choose which receivers/antennas to use */
3144 if (priv->cfg->ops->hcmd->set_rxon_chain) 2793 if (priv->cfg->ops->hcmd->set_rxon_chain)
diff --git a/drivers/net/wireless/iwlwifi/Makefile b/drivers/net/wireless/iwlwifi/Makefile
index 822660483f9f..48ab9142af38 100644
--- a/drivers/net/wireless/iwlwifi/Makefile
+++ b/drivers/net/wireless/iwlwifi/Makefile
@@ -5,14 +5,16 @@ iwlagn-objs += iwl-agn-ucode.o iwl-agn-tx.o
5iwlagn-objs += iwl-agn-lib.o iwl-agn-calib.o iwl-io.o 5iwlagn-objs += iwl-agn-lib.o iwl-agn-calib.o iwl-io.o
6iwlagn-objs += iwl-agn-tt.o iwl-agn-sta.o iwl-agn-eeprom.o 6iwlagn-objs += iwl-agn-tt.o iwl-agn-sta.o iwl-agn-eeprom.o
7 7
8iwlagn-objs += iwl-core.o iwl-eeprom.o iwl-hcmd.o iwl-power.o 8iwlagn-objs += iwl-core.o iwl-eeprom.o iwl-power.o
9iwlagn-objs += iwl-rx.o iwl-tx.o iwl-sta.o 9iwlagn-objs += iwl-rx.o iwl-sta.o
10iwlagn-objs += iwl-scan.o iwl-led.o 10iwlagn-objs += iwl-scan.o iwl-led.o
11iwlagn-objs += iwl-agn-rxon.o iwl-agn-hcmd.o iwl-agn-ict.o 11iwlagn-objs += iwl-agn-rxon.o
12iwlagn-objs += iwl-5000.o 12iwlagn-objs += iwl-5000.o
13iwlagn-objs += iwl-6000.o 13iwlagn-objs += iwl-6000.o
14iwlagn-objs += iwl-1000.o 14iwlagn-objs += iwl-1000.o
15iwlagn-objs += iwl-2000.o 15iwlagn-objs += iwl-2000.o
16iwlagn-objs += iwl-pci.o
17iwlagn-objs += iwl-trans.o iwl-trans-rx-pcie.o iwl-trans-tx-pcie.o
16 18
17iwlagn-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-debugfs.o 19iwlagn-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-debugfs.o
18iwlagn-$(CONFIG_IWLWIFI_DEVICE_TRACING) += iwl-devtrace.o 20iwlagn-$(CONFIG_IWLWIFI_DEVICE_TRACING) += iwl-devtrace.o
diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c
index 2a88e73bb39c..01b49eb8c8ec 100644
--- a/drivers/net/wireless/iwlwifi/iwl-1000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-1000.c
@@ -27,8 +27,6 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h> 30#include <linux/delay.h>
33#include <linux/skbuff.h> 31#include <linux/skbuff.h>
34#include <linux/netdevice.h> 32#include <linux/netdevice.h>
@@ -127,7 +125,6 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv)
127 iwlagn_mod_params.num_of_queues; 125 iwlagn_mod_params.num_of_queues;
128 126
129 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues; 127 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
130 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
131 priv->hw_params.scd_bc_tbls_size = 128 priv->hw_params.scd_bc_tbls_size =
132 priv->cfg->base_params->num_of_queues * 129 priv->cfg->base_params->num_of_queues *
133 sizeof(struct iwlagn_scd_bc_tbl); 130 sizeof(struct iwlagn_scd_bc_tbl);
@@ -140,7 +137,6 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv)
140 137
141 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | 138 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
142 BIT(IEEE80211_BAND_5GHZ); 139 BIT(IEEE80211_BAND_5GHZ);
143 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
144 140
145 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 141 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
146 if (priv->cfg->rx_with_siso_diversity) 142 if (priv->cfg->rx_with_siso_diversity)
@@ -172,15 +168,7 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv)
172 168
173static struct iwl_lib_ops iwl1000_lib = { 169static struct iwl_lib_ops iwl1000_lib = {
174 .set_hw_params = iwl1000_hw_set_hw_params, 170 .set_hw_params = iwl1000_hw_set_hw_params,
175 .rx_handler_setup = iwlagn_rx_handler_setup, 171 .nic_config = iwl1000_nic_config,
176 .setup_deferred_work = iwlagn_setup_deferred_work,
177 .is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
178 .send_tx_power = iwlagn_send_tx_power,
179 .update_chain_flags = iwl_update_chain_flags,
180 .apm_ops = {
181 .init = iwl_apm_init,
182 .config = iwl1000_nic_config,
183 },
184 .eeprom_ops = { 172 .eeprom_ops = {
185 .regulatory_bands = { 173 .regulatory_bands = {
186 EEPROM_REG_BAND_1_CHANNELS, 174 EEPROM_REG_BAND_1_CHANNELS,
@@ -191,19 +179,8 @@ static struct iwl_lib_ops iwl1000_lib = {
191 EEPROM_REG_BAND_24_HT40_CHANNELS, 179 EEPROM_REG_BAND_24_HT40_CHANNELS,
192 EEPROM_REGULATORY_BAND_NO_HT40, 180 EEPROM_REGULATORY_BAND_NO_HT40,
193 }, 181 },
194 .query_addr = iwlagn_eeprom_query_addr,
195 }, 182 },
196 .temp_ops = { 183 .temperature = iwlagn_temperature,
197 .temperature = iwlagn_temperature,
198 },
199 .txfifo_flush = iwlagn_txfifo_flush,
200 .dev_txfifo_flush = iwlagn_dev_txfifo_flush,
201};
202
203static const struct iwl_ops iwl1000_ops = {
204 .lib = &iwl1000_lib,
205 .hcmd = &iwlagn_hcmd,
206 .utils = &iwlagn_hcmd_utils,
207}; 184};
208 185
209static struct iwl_base_params iwl1000_base_params = { 186static struct iwl_base_params iwl1000_base_params = {
@@ -224,6 +201,7 @@ static struct iwl_base_params iwl1000_base_params = {
224static struct iwl_ht_params iwl1000_ht_params = { 201static struct iwl_ht_params iwl1000_ht_params = {
225 .ht_greenfield_support = true, 202 .ht_greenfield_support = true,
226 .use_rts_for_aggregation = true, /* use rts/cts protection */ 203 .use_rts_for_aggregation = true, /* use rts/cts protection */
204 .smps_mode = IEEE80211_SMPS_STATIC,
227}; 205};
228 206
229#define IWL_DEVICE_1000 \ 207#define IWL_DEVICE_1000 \
@@ -232,7 +210,7 @@ static struct iwl_ht_params iwl1000_ht_params = {
232 .ucode_api_min = IWL1000_UCODE_API_MIN, \ 210 .ucode_api_min = IWL1000_UCODE_API_MIN, \
233 .eeprom_ver = EEPROM_1000_EEPROM_VERSION, \ 211 .eeprom_ver = EEPROM_1000_EEPROM_VERSION, \
234 .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION, \ 212 .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION, \
235 .ops = &iwl1000_ops, \ 213 .lib = &iwl1000_lib, \
236 .base_params = &iwl1000_base_params, \ 214 .base_params = &iwl1000_base_params, \
237 .led_mode = IWL_LED_BLINK 215 .led_mode = IWL_LED_BLINK
238 216
@@ -253,7 +231,7 @@ struct iwl_cfg iwl1000_bg_cfg = {
253 .ucode_api_min = IWL100_UCODE_API_MIN, \ 231 .ucode_api_min = IWL100_UCODE_API_MIN, \
254 .eeprom_ver = EEPROM_1000_EEPROM_VERSION, \ 232 .eeprom_ver = EEPROM_1000_EEPROM_VERSION, \
255 .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION, \ 233 .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION, \
256 .ops = &iwl1000_ops, \ 234 .lib = &iwl1000_lib, \
257 .base_params = &iwl1000_base_params, \ 235 .base_params = &iwl1000_base_params, \
258 .led_mode = IWL_LED_RF_STATE, \ 236 .led_mode = IWL_LED_RF_STATE, \
259 .rx_with_siso_diversity = true 237 .rx_with_siso_diversity = true
diff --git a/drivers/net/wireless/iwlwifi/iwl-2000.c b/drivers/net/wireless/iwlwifi/iwl-2000.c
index 3df76f53a41b..0e13f0bb2e17 100644
--- a/drivers/net/wireless/iwlwifi/iwl-2000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-2000.c
@@ -27,8 +27,6 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h> 30#include <linux/delay.h>
33#include <linux/skbuff.h> 31#include <linux/skbuff.h>
34#include <linux/netdevice.h> 32#include <linux/netdevice.h>
@@ -52,11 +50,13 @@
52#define IWL2030_UCODE_API_MAX 5 50#define IWL2030_UCODE_API_MAX 5
53#define IWL2000_UCODE_API_MAX 5 51#define IWL2000_UCODE_API_MAX 5
54#define IWL105_UCODE_API_MAX 5 52#define IWL105_UCODE_API_MAX 5
53#define IWL135_UCODE_API_MAX 5
55 54
56/* Lowest firmware API version supported */ 55/* Lowest firmware API version supported */
57#define IWL2030_UCODE_API_MIN 5 56#define IWL2030_UCODE_API_MIN 5
58#define IWL2000_UCODE_API_MIN 5 57#define IWL2000_UCODE_API_MIN 5
59#define IWL105_UCODE_API_MIN 5 58#define IWL105_UCODE_API_MIN 5
59#define IWL135_UCODE_API_MIN 5
60 60
61#define IWL2030_FW_PRE "iwlwifi-2030-" 61#define IWL2030_FW_PRE "iwlwifi-2030-"
62#define IWL2030_MODULE_FIRMWARE(api) IWL2030_FW_PRE __stringify(api) ".ucode" 62#define IWL2030_MODULE_FIRMWARE(api) IWL2030_FW_PRE __stringify(api) ".ucode"
@@ -67,6 +67,9 @@
67#define IWL105_FW_PRE "iwlwifi-105-" 67#define IWL105_FW_PRE "iwlwifi-105-"
68#define IWL105_MODULE_FIRMWARE(api) IWL105_FW_PRE __stringify(api) ".ucode" 68#define IWL105_MODULE_FIRMWARE(api) IWL105_FW_PRE __stringify(api) ".ucode"
69 69
70#define IWL135_FW_PRE "iwlwifi-135-"
71#define IWL135_MODULE_FIRMWARE(api) IWL135_FW_PRE #api ".ucode"
72
70static void iwl2000_set_ct_threshold(struct iwl_priv *priv) 73static void iwl2000_set_ct_threshold(struct iwl_priv *priv)
71{ 74{
72 /* want Celsius */ 75 /* want Celsius */
@@ -77,28 +80,11 @@ static void iwl2000_set_ct_threshold(struct iwl_priv *priv)
77/* NIC configuration for 2000 series */ 80/* NIC configuration for 2000 series */
78static void iwl2000_nic_config(struct iwl_priv *priv) 81static void iwl2000_nic_config(struct iwl_priv *priv)
79{ 82{
80 u16 radio_cfg; 83 iwl_rf_config(priv);
81
82 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
83
84 /* write radio config values to register */
85 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX)
86 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
87 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
88 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
89 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
90
91 /* set CSR_HW_CONFIG_REG for uCode use */
92 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
93 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
94 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
95 84
96 if (priv->cfg->iq_invert) 85 if (priv->cfg->iq_invert)
97 iwl_set_bit(priv, CSR_GP_DRIVER_REG, 86 iwl_set_bit(priv, CSR_GP_DRIVER_REG,
98 CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER); 87 CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);
99
100 if (priv->cfg->disable_otp_refresh)
101 iwl_write_prph(priv, APMG_ANALOG_SVR_REG, 0x80000010);
102} 88}
103 89
104static struct iwl_sensitivity_ranges iwl2000_sensitivity = { 90static struct iwl_sensitivity_ranges iwl2000_sensitivity = {
@@ -134,7 +120,6 @@ static int iwl2000_hw_set_hw_params(struct iwl_priv *priv)
134 iwlagn_mod_params.num_of_queues; 120 iwlagn_mod_params.num_of_queues;
135 121
136 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues; 122 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
137 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
138 priv->hw_params.scd_bc_tbls_size = 123 priv->hw_params.scd_bc_tbls_size =
139 priv->cfg->base_params->num_of_queues * 124 priv->cfg->base_params->num_of_queues *
140 sizeof(struct iwlagn_scd_bc_tbl); 125 sizeof(struct iwlagn_scd_bc_tbl);
@@ -147,7 +132,6 @@ static int iwl2000_hw_set_hw_params(struct iwl_priv *priv)
147 132
148 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | 133 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
149 BIT(IEEE80211_BAND_5GHZ); 134 BIT(IEEE80211_BAND_5GHZ);
150 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
151 135
152 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 136 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
153 if (priv->cfg->rx_with_siso_diversity) 137 if (priv->cfg->rx_with_siso_diversity)
@@ -169,7 +153,7 @@ static int iwl2000_hw_set_hw_params(struct iwl_priv *priv)
169 BIT(IWL_CALIB_TX_IQ) | 153 BIT(IWL_CALIB_TX_IQ) |
170 BIT(IWL_CALIB_BASE_BAND); 154 BIT(IWL_CALIB_BASE_BAND);
171 if (priv->cfg->need_dc_calib) 155 if (priv->cfg->need_dc_calib)
172 priv->hw_params.calib_rt_cfg |= BIT(IWL_CALIB_CFG_DC_IDX); 156 priv->hw_params.calib_rt_cfg |= IWL_CALIB_CFG_DC_IDX;
173 if (priv->cfg->need_temp_offset_calib) 157 if (priv->cfg->need_temp_offset_calib)
174 priv->hw_params.calib_init_cfg |= BIT(IWL_CALIB_TEMP_OFFSET); 158 priv->hw_params.calib_init_cfg |= BIT(IWL_CALIB_TEMP_OFFSET);
175 159
@@ -180,16 +164,7 @@ static int iwl2000_hw_set_hw_params(struct iwl_priv *priv)
180 164
181static struct iwl_lib_ops iwl2000_lib = { 165static struct iwl_lib_ops iwl2000_lib = {
182 .set_hw_params = iwl2000_hw_set_hw_params, 166 .set_hw_params = iwl2000_hw_set_hw_params,
183 .rx_handler_setup = iwlagn_rx_handler_setup, 167 .nic_config = iwl2000_nic_config,
184 .setup_deferred_work = iwlagn_bt_setup_deferred_work,
185 .cancel_deferred_work = iwlagn_bt_cancel_deferred_work,
186 .is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
187 .send_tx_power = iwlagn_send_tx_power,
188 .update_chain_flags = iwl_update_chain_flags,
189 .apm_ops = {
190 .init = iwl_apm_init,
191 .config = iwl2000_nic_config,
192 },
193 .eeprom_ops = { 168 .eeprom_ops = {
194 .regulatory_bands = { 169 .regulatory_bands = {
195 EEPROM_REG_BAND_1_CHANNELS, 170 EEPROM_REG_BAND_1_CHANNELS,
@@ -200,38 +175,30 @@ static struct iwl_lib_ops iwl2000_lib = {
200 EEPROM_6000_REG_BAND_24_HT40_CHANNELS, 175 EEPROM_6000_REG_BAND_24_HT40_CHANNELS,
201 EEPROM_REGULATORY_BAND_NO_HT40, 176 EEPROM_REGULATORY_BAND_NO_HT40,
202 }, 177 },
203 .query_addr = iwlagn_eeprom_query_addr,
204 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower, 178 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
205 }, 179 },
206 .temp_ops = { 180 .temperature = iwlagn_temperature,
207 .temperature = iwlagn_temperature,
208 },
209 .txfifo_flush = iwlagn_txfifo_flush,
210 .dev_txfifo_flush = iwlagn_dev_txfifo_flush,
211}; 181};
212 182
213static const struct iwl_ops iwl2000_ops = { 183static struct iwl_lib_ops iwl2030_lib = {
214 .lib = &iwl2000_lib, 184 .set_hw_params = iwl2000_hw_set_hw_params,
215 .hcmd = &iwlagn_hcmd, 185 .bt_rx_handler_setup = iwlagn_bt_rx_handler_setup,
216 .utils = &iwlagn_hcmd_utils, 186 .bt_setup_deferred_work = iwlagn_bt_setup_deferred_work,
217}; 187 .cancel_deferred_work = iwlagn_bt_cancel_deferred_work,
218 188 .nic_config = iwl2000_nic_config,
219static const struct iwl_ops iwl2030_ops = { 189 .eeprom_ops = {
220 .lib = &iwl2000_lib, 190 .regulatory_bands = {
221 .hcmd = &iwlagn_bt_hcmd, 191 EEPROM_REG_BAND_1_CHANNELS,
222 .utils = &iwlagn_hcmd_utils, 192 EEPROM_REG_BAND_2_CHANNELS,
223}; 193 EEPROM_REG_BAND_3_CHANNELS,
224 194 EEPROM_REG_BAND_4_CHANNELS,
225static const struct iwl_ops iwl105_ops = { 195 EEPROM_REG_BAND_5_CHANNELS,
226 .lib = &iwl2000_lib, 196 EEPROM_6000_REG_BAND_24_HT40_CHANNELS,
227 .hcmd = &iwlagn_hcmd, 197 EEPROM_REGULATORY_BAND_NO_HT40,
228 .utils = &iwlagn_hcmd_utils, 198 },
229}; 199 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
230 200 },
231static const struct iwl_ops iwl135_ops = { 201 .temperature = iwlagn_temperature,
232 .lib = &iwl2000_lib,
233 .hcmd = &iwlagn_bt_hcmd,
234 .utils = &iwlagn_hcmd_utils,
235}; 202};
236 203
237static struct iwl_base_params iwl2000_base_params = { 204static struct iwl_base_params iwl2000_base_params = {
@@ -292,13 +259,12 @@ static struct iwl_bt_params iwl2030_bt_params = {
292 .ucode_api_min = IWL2000_UCODE_API_MIN, \ 259 .ucode_api_min = IWL2000_UCODE_API_MIN, \
293 .eeprom_ver = EEPROM_2000_EEPROM_VERSION, \ 260 .eeprom_ver = EEPROM_2000_EEPROM_VERSION, \
294 .eeprom_calib_ver = EEPROM_2000_TX_POWER_VERSION, \ 261 .eeprom_calib_ver = EEPROM_2000_TX_POWER_VERSION, \
295 .ops = &iwl2000_ops, \ 262 .lib = &iwl2000_lib, \
296 .base_params = &iwl2000_base_params, \ 263 .base_params = &iwl2000_base_params, \
297 .need_dc_calib = true, \ 264 .need_dc_calib = true, \
298 .need_temp_offset_calib = true, \ 265 .need_temp_offset_calib = true, \
299 .led_mode = IWL_LED_RF_STATE, \ 266 .led_mode = IWL_LED_RF_STATE, \
300 .iq_invert = true, \ 267 .iq_invert = true \
301 .disable_otp_refresh = true \
302 268
303struct iwl_cfg iwl2000_2bgn_cfg = { 269struct iwl_cfg iwl2000_2bgn_cfg = {
304 .name = "2000 Series 2x2 BGN", 270 .name = "2000 Series 2x2 BGN",
@@ -317,7 +283,7 @@ struct iwl_cfg iwl2000_2bg_cfg = {
317 .ucode_api_min = IWL2030_UCODE_API_MIN, \ 283 .ucode_api_min = IWL2030_UCODE_API_MIN, \
318 .eeprom_ver = EEPROM_2000_EEPROM_VERSION, \ 284 .eeprom_ver = EEPROM_2000_EEPROM_VERSION, \
319 .eeprom_calib_ver = EEPROM_2000_TX_POWER_VERSION, \ 285 .eeprom_calib_ver = EEPROM_2000_TX_POWER_VERSION, \
320 .ops = &iwl2030_ops, \ 286 .lib = &iwl2030_lib, \
321 .base_params = &iwl2030_base_params, \ 287 .base_params = &iwl2030_base_params, \
322 .bt_params = &iwl2030_bt_params, \ 288 .bt_params = &iwl2030_bt_params, \
323 .need_dc_calib = true, \ 289 .need_dc_calib = true, \
@@ -343,13 +309,14 @@ struct iwl_cfg iwl2030_2bg_cfg = {
343 .ucode_api_min = IWL105_UCODE_API_MIN, \ 309 .ucode_api_min = IWL105_UCODE_API_MIN, \
344 .eeprom_ver = EEPROM_2000_EEPROM_VERSION, \ 310 .eeprom_ver = EEPROM_2000_EEPROM_VERSION, \
345 .eeprom_calib_ver = EEPROM_2000_TX_POWER_VERSION, \ 311 .eeprom_calib_ver = EEPROM_2000_TX_POWER_VERSION, \
346 .ops = &iwl105_ops, \ 312 .lib = &iwl2000_lib, \
347 .base_params = &iwl2000_base_params, \ 313 .base_params = &iwl2000_base_params, \
348 .need_dc_calib = true, \ 314 .need_dc_calib = true, \
349 .need_temp_offset_calib = true, \ 315 .need_temp_offset_calib = true, \
350 .led_mode = IWL_LED_RF_STATE, \ 316 .led_mode = IWL_LED_RF_STATE, \
351 .adv_pm = true, \ 317 .adv_pm = true, \
352 .rx_with_siso_diversity = true \ 318 .rx_with_siso_diversity = true, \
319 .iq_invert = true \
353 320
354struct iwl_cfg iwl105_bg_cfg = { 321struct iwl_cfg iwl105_bg_cfg = {
355 .name = "105 Series 1x1 BG", 322 .name = "105 Series 1x1 BG",
@@ -363,27 +330,28 @@ struct iwl_cfg iwl105_bgn_cfg = {
363}; 330};
364 331
365#define IWL_DEVICE_135 \ 332#define IWL_DEVICE_135 \
366 .fw_name_pre = IWL105_FW_PRE, \ 333 .fw_name_pre = IWL135_FW_PRE, \
367 .ucode_api_max = IWL105_UCODE_API_MAX, \ 334 .ucode_api_max = IWL135_UCODE_API_MAX, \
368 .ucode_api_min = IWL105_UCODE_API_MIN, \ 335 .ucode_api_min = IWL135_UCODE_API_MIN, \
369 .eeprom_ver = EEPROM_2000_EEPROM_VERSION, \ 336 .eeprom_ver = EEPROM_2000_EEPROM_VERSION, \
370 .eeprom_calib_ver = EEPROM_2000_TX_POWER_VERSION, \ 337 .eeprom_calib_ver = EEPROM_2000_TX_POWER_VERSION, \
371 .ops = &iwl135_ops, \ 338 .lib = &iwl2030_lib, \
372 .base_params = &iwl2030_base_params, \ 339 .base_params = &iwl2030_base_params, \
373 .bt_params = &iwl2030_bt_params, \ 340 .bt_params = &iwl2030_bt_params, \
374 .need_dc_calib = true, \ 341 .need_dc_calib = true, \
375 .need_temp_offset_calib = true, \ 342 .need_temp_offset_calib = true, \
376 .led_mode = IWL_LED_RF_STATE, \ 343 .led_mode = IWL_LED_RF_STATE, \
377 .adv_pm = true, \ 344 .adv_pm = true, \
378 .rx_with_siso_diversity = true \ 345 .rx_with_siso_diversity = true, \
346 .iq_invert = true \
379 347
380struct iwl_cfg iwl135_bg_cfg = { 348struct iwl_cfg iwl135_bg_cfg = {
381 .name = "105 Series 1x1 BG/BT", 349 .name = "135 Series 1x1 BG/BT",
382 IWL_DEVICE_135, 350 IWL_DEVICE_135,
383}; 351};
384 352
385struct iwl_cfg iwl135_bgn_cfg = { 353struct iwl_cfg iwl135_bgn_cfg = {
386 .name = "105 Series 1x1 BGN/BT", 354 .name = "135 Series 1x1 BGN/BT",
387 IWL_DEVICE_135, 355 IWL_DEVICE_135,
388 .ht_params = &iwl2000_ht_params, 356 .ht_params = &iwl2000_ht_params,
389}; 357};
@@ -391,3 +359,4 @@ struct iwl_cfg iwl135_bgn_cfg = {
391MODULE_FIRMWARE(IWL2000_MODULE_FIRMWARE(IWL2000_UCODE_API_MAX)); 359MODULE_FIRMWARE(IWL2000_MODULE_FIRMWARE(IWL2000_UCODE_API_MAX));
392MODULE_FIRMWARE(IWL2030_MODULE_FIRMWARE(IWL2030_UCODE_API_MAX)); 360MODULE_FIRMWARE(IWL2030_MODULE_FIRMWARE(IWL2030_UCODE_API_MAX));
393MODULE_FIRMWARE(IWL105_MODULE_FIRMWARE(IWL105_UCODE_API_MAX)); 361MODULE_FIRMWARE(IWL105_MODULE_FIRMWARE(IWL105_UCODE_API_MAX));
362MODULE_FIRMWARE(IWL135_MODULE_FIRMWARE(IWL135_UCODE_API_MAX));
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000-hw.h b/drivers/net/wireless/iwlwifi/iwl-5000-hw.h
index 05ad47628b63..f9630a3c79fe 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-5000-hw.h
@@ -75,7 +75,7 @@ static inline s32 iwl_temp_calib_to_offset(struct iwl_priv *priv)
75{ 75{
76 u16 temperature, voltage; 76 u16 temperature, voltage;
77 __le16 *temp_calib = 77 __le16 *temp_calib =
78 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_TEMPERATURE); 78 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
79 79
80 temperature = le16_to_cpu(temp_calib[0]); 80 temperature = le16_to_cpu(temp_calib[0]);
81 voltage = le16_to_cpu(temp_calib[1]); 81 voltage = le16_to_cpu(temp_calib[1]);
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index e816c27db794..3eeb12ebe6e9 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -27,8 +27,6 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h> 30#include <linux/delay.h>
33#include <linux/sched.h> 31#include <linux/sched.h>
34#include <linux/skbuff.h> 32#include <linux/skbuff.h>
@@ -48,6 +46,7 @@
48#include "iwl-agn.h" 46#include "iwl-agn.h"
49#include "iwl-agn-hw.h" 47#include "iwl-agn-hw.h"
50#include "iwl-5000-hw.h" 48#include "iwl-5000-hw.h"
49#include "iwl-trans.h"
51 50
52/* Highest firmware API version supported */ 51/* Highest firmware API version supported */
53#define IWL5000_UCODE_API_MAX 5 52#define IWL5000_UCODE_API_MAX 5
@@ -67,23 +66,10 @@
67static void iwl5000_nic_config(struct iwl_priv *priv) 66static void iwl5000_nic_config(struct iwl_priv *priv)
68{ 67{
69 unsigned long flags; 68 unsigned long flags;
70 u16 radio_cfg;
71 69
72 spin_lock_irqsave(&priv->lock, flags); 70 iwl_rf_config(priv);
73
74 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
75
76 /* write radio config values to register */
77 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
78 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
79 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
80 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
81 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
82 71
83 /* set CSR_HW_CONFIG_REG for uCode use */ 72 spin_lock_irqsave(&priv->lock, flags);
84 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
85 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
86 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
87 73
88 /* W/A : NIC is stuck in a reset state after Early PCIe power off 74 /* W/A : NIC is stuck in a reset state after Early PCIe power off
89 * (PCIe power is lost before PERST# is asserted), 75 * (PCIe power is lost before PERST# is asserted),
@@ -171,7 +157,6 @@ static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
171 iwlagn_mod_params.num_of_queues; 157 iwlagn_mod_params.num_of_queues;
172 158
173 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues; 159 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
174 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
175 priv->hw_params.scd_bc_tbls_size = 160 priv->hw_params.scd_bc_tbls_size =
176 priv->cfg->base_params->num_of_queues * 161 priv->cfg->base_params->num_of_queues *
177 sizeof(struct iwlagn_scd_bc_tbl); 162 sizeof(struct iwlagn_scd_bc_tbl);
@@ -184,7 +169,6 @@ static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
184 169
185 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | 170 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
186 BIT(IEEE80211_BAND_5GHZ); 171 BIT(IEEE80211_BAND_5GHZ);
187 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
188 172
189 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 173 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
190 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); 174 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
@@ -216,7 +200,6 @@ static int iwl5150_hw_set_hw_params(struct iwl_priv *priv)
216 iwlagn_mod_params.num_of_queues; 200 iwlagn_mod_params.num_of_queues;
217 201
218 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues; 202 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
219 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
220 priv->hw_params.scd_bc_tbls_size = 203 priv->hw_params.scd_bc_tbls_size =
221 priv->cfg->base_params->num_of_queues * 204 priv->cfg->base_params->num_of_queues *
222 sizeof(struct iwlagn_scd_bc_tbl); 205 sizeof(struct iwlagn_scd_bc_tbl);
@@ -229,7 +212,6 @@ static int iwl5150_hw_set_hw_params(struct iwl_priv *priv)
229 212
230 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | 213 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
231 BIT(IEEE80211_BAND_5GHZ); 214 BIT(IEEE80211_BAND_5GHZ);
232 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
233 215
234 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 216 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
235 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); 217 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
@@ -333,21 +315,13 @@ static int iwl5000_hw_channel_switch(struct iwl_priv *priv,
333 return -EFAULT; 315 return -EFAULT;
334 } 316 }
335 317
336 return iwl_send_cmd_sync(priv, &hcmd); 318 return trans_send_cmd(&priv->trans, &hcmd);
337} 319}
338 320
339static struct iwl_lib_ops iwl5000_lib = { 321static struct iwl_lib_ops iwl5000_lib = {
340 .set_hw_params = iwl5000_hw_set_hw_params, 322 .set_hw_params = iwl5000_hw_set_hw_params,
341 .rx_handler_setup = iwlagn_rx_handler_setup,
342 .setup_deferred_work = iwlagn_setup_deferred_work,
343 .is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
344 .send_tx_power = iwlagn_send_tx_power,
345 .update_chain_flags = iwl_update_chain_flags,
346 .set_channel_switch = iwl5000_hw_channel_switch, 323 .set_channel_switch = iwl5000_hw_channel_switch,
347 .apm_ops = { 324 .nic_config = iwl5000_nic_config,
348 .init = iwl_apm_init,
349 .config = iwl5000_nic_config,
350 },
351 .eeprom_ops = { 325 .eeprom_ops = {
352 .regulatory_bands = { 326 .regulatory_bands = {
353 EEPROM_REG_BAND_1_CHANNELS, 327 EEPROM_REG_BAND_1_CHANNELS,
@@ -358,27 +332,14 @@ static struct iwl_lib_ops iwl5000_lib = {
358 EEPROM_REG_BAND_24_HT40_CHANNELS, 332 EEPROM_REG_BAND_24_HT40_CHANNELS,
359 EEPROM_REG_BAND_52_HT40_CHANNELS 333 EEPROM_REG_BAND_52_HT40_CHANNELS
360 }, 334 },
361 .query_addr = iwlagn_eeprom_query_addr,
362 }, 335 },
363 .temp_ops = { 336 .temperature = iwlagn_temperature,
364 .temperature = iwlagn_temperature,
365 },
366 .txfifo_flush = iwlagn_txfifo_flush,
367 .dev_txfifo_flush = iwlagn_dev_txfifo_flush,
368}; 337};
369 338
370static struct iwl_lib_ops iwl5150_lib = { 339static struct iwl_lib_ops iwl5150_lib = {
371 .set_hw_params = iwl5150_hw_set_hw_params, 340 .set_hw_params = iwl5150_hw_set_hw_params,
372 .rx_handler_setup = iwlagn_rx_handler_setup,
373 .setup_deferred_work = iwlagn_setup_deferred_work,
374 .is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
375 .send_tx_power = iwlagn_send_tx_power,
376 .update_chain_flags = iwl_update_chain_flags,
377 .set_channel_switch = iwl5000_hw_channel_switch, 341 .set_channel_switch = iwl5000_hw_channel_switch,
378 .apm_ops = { 342 .nic_config = iwl5000_nic_config,
379 .init = iwl_apm_init,
380 .config = iwl5000_nic_config,
381 },
382 .eeprom_ops = { 343 .eeprom_ops = {
383 .regulatory_bands = { 344 .regulatory_bands = {
384 EEPROM_REG_BAND_1_CHANNELS, 345 EEPROM_REG_BAND_1_CHANNELS,
@@ -389,25 +350,8 @@ static struct iwl_lib_ops iwl5150_lib = {
389 EEPROM_REG_BAND_24_HT40_CHANNELS, 350 EEPROM_REG_BAND_24_HT40_CHANNELS,
390 EEPROM_REG_BAND_52_HT40_CHANNELS 351 EEPROM_REG_BAND_52_HT40_CHANNELS
391 }, 352 },
392 .query_addr = iwlagn_eeprom_query_addr,
393 }, 353 },
394 .temp_ops = { 354 .temperature = iwl5150_temperature,
395 .temperature = iwl5150_temperature,
396 },
397 .txfifo_flush = iwlagn_txfifo_flush,
398 .dev_txfifo_flush = iwlagn_dev_txfifo_flush,
399};
400
401static const struct iwl_ops iwl5000_ops = {
402 .lib = &iwl5000_lib,
403 .hcmd = &iwlagn_hcmd,
404 .utils = &iwlagn_hcmd_utils,
405};
406
407static const struct iwl_ops iwl5150_ops = {
408 .lib = &iwl5150_lib,
409 .hcmd = &iwlagn_hcmd,
410 .utils = &iwlagn_hcmd_utils,
411}; 355};
412 356
413static struct iwl_base_params iwl5000_base_params = { 357static struct iwl_base_params iwl5000_base_params = {
@@ -432,7 +376,7 @@ static struct iwl_ht_params iwl5000_ht_params = {
432 .ucode_api_min = IWL5000_UCODE_API_MIN, \ 376 .ucode_api_min = IWL5000_UCODE_API_MIN, \
433 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, \ 377 .eeprom_ver = EEPROM_5000_EEPROM_VERSION, \
434 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, \ 378 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, \
435 .ops = &iwl5000_ops, \ 379 .lib = &iwl5000_lib, \
436 .base_params = &iwl5000_base_params, \ 380 .base_params = &iwl5000_base_params, \
437 .led_mode = IWL_LED_BLINK 381 .led_mode = IWL_LED_BLINK
438 382
@@ -475,7 +419,7 @@ struct iwl_cfg iwl5350_agn_cfg = {
475 .ucode_api_min = IWL5000_UCODE_API_MIN, 419 .ucode_api_min = IWL5000_UCODE_API_MIN,
476 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, 420 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
477 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, 421 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
478 .ops = &iwl5000_ops, 422 .lib = &iwl5000_lib,
479 .base_params = &iwl5000_base_params, 423 .base_params = &iwl5000_base_params,
480 .ht_params = &iwl5000_ht_params, 424 .ht_params = &iwl5000_ht_params,
481 .led_mode = IWL_LED_BLINK, 425 .led_mode = IWL_LED_BLINK,
@@ -488,7 +432,7 @@ struct iwl_cfg iwl5350_agn_cfg = {
488 .ucode_api_min = IWL5150_UCODE_API_MIN, \ 432 .ucode_api_min = IWL5150_UCODE_API_MIN, \
489 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, \ 433 .eeprom_ver = EEPROM_5050_EEPROM_VERSION, \
490 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, \ 434 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, \
491 .ops = &iwl5150_ops, \ 435 .lib = &iwl5150_lib, \
492 .base_params = &iwl5000_base_params, \ 436 .base_params = &iwl5000_base_params, \
493 .need_dc_calib = true, \ 437 .need_dc_calib = true, \
494 .led_mode = IWL_LED_BLINK, \ 438 .led_mode = IWL_LED_BLINK, \
diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c
index 5b150bc70b06..973d1972e8cc 100644
--- a/drivers/net/wireless/iwlwifi/iwl-6000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c
@@ -27,8 +27,6 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h> 30#include <linux/delay.h>
33#include <linux/skbuff.h> 31#include <linux/skbuff.h>
34#include <linux/netdevice.h> 32#include <linux/netdevice.h>
@@ -47,6 +45,7 @@
47#include "iwl-helpers.h" 45#include "iwl-helpers.h"
48#include "iwl-agn-hw.h" 46#include "iwl-agn-hw.h"
49#include "iwl-6000-hw.h" 47#include "iwl-6000-hw.h"
48#include "iwl-trans.h"
50 49
51/* Highest firmware API version supported */ 50/* Highest firmware API version supported */
52#define IWL6000_UCODE_API_MAX 4 51#define IWL6000_UCODE_API_MAX 4
@@ -98,21 +97,7 @@ static void iwl6150_additional_nic_config(struct iwl_priv *priv)
98/* NIC configuration for 6000 series */ 97/* NIC configuration for 6000 series */
99static void iwl6000_nic_config(struct iwl_priv *priv) 98static void iwl6000_nic_config(struct iwl_priv *priv)
100{ 99{
101 u16 radio_cfg; 100 iwl_rf_config(priv);
102
103 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
104
105 /* write radio config values to register */
106 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX)
107 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
108 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
109 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
110 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
111
112 /* set CSR_HW_CONFIG_REG for uCode use */
113 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
114 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
115 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
116 101
117 /* no locking required for register write */ 102 /* no locking required for register write */
118 if (priv->cfg->pa_type == IWL_PA_INTERNAL) { 103 if (priv->cfg->pa_type == IWL_PA_INTERNAL) {
@@ -121,10 +106,8 @@ static void iwl6000_nic_config(struct iwl_priv *priv)
121 CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA); 106 CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);
122 } 107 }
123 /* do additional nic configuration if needed */ 108 /* do additional nic configuration if needed */
124 if (priv->cfg->ops->nic && 109 if (priv->cfg->additional_nic_config)
125 priv->cfg->ops->nic->additional_nic_config) { 110 priv->cfg->additional_nic_config(priv);
126 priv->cfg->ops->nic->additional_nic_config(priv);
127 }
128} 111}
129 112
130static struct iwl_sensitivity_ranges iwl6000_sensitivity = { 113static struct iwl_sensitivity_ranges iwl6000_sensitivity = {
@@ -160,7 +143,6 @@ static int iwl6000_hw_set_hw_params(struct iwl_priv *priv)
160 iwlagn_mod_params.num_of_queues; 143 iwlagn_mod_params.num_of_queues;
161 144
162 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues; 145 priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
163 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
164 priv->hw_params.scd_bc_tbls_size = 146 priv->hw_params.scd_bc_tbls_size =
165 priv->cfg->base_params->num_of_queues * 147 priv->cfg->base_params->num_of_queues *
166 sizeof(struct iwlagn_scd_bc_tbl); 148 sizeof(struct iwlagn_scd_bc_tbl);
@@ -173,7 +155,6 @@ static int iwl6000_hw_set_hw_params(struct iwl_priv *priv)
173 155
174 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | 156 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
175 BIT(IEEE80211_BAND_5GHZ); 157 BIT(IEEE80211_BAND_5GHZ);
176 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
177 158
178 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); 159 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
179 if (priv->cfg->rx_with_siso_diversity) 160 if (priv->cfg->rx_with_siso_diversity)
@@ -195,7 +176,7 @@ static int iwl6000_hw_set_hw_params(struct iwl_priv *priv)
195 BIT(IWL_CALIB_TX_IQ) | 176 BIT(IWL_CALIB_TX_IQ) |
196 BIT(IWL_CALIB_BASE_BAND); 177 BIT(IWL_CALIB_BASE_BAND);
197 if (priv->cfg->need_dc_calib) 178 if (priv->cfg->need_dc_calib)
198 priv->hw_params.calib_rt_cfg |= BIT(IWL_CALIB_CFG_DC_IDX); 179 priv->hw_params.calib_rt_cfg |= IWL_CALIB_CFG_DC_IDX;
199 if (priv->cfg->need_temp_offset_calib) 180 if (priv->cfg->need_temp_offset_calib)
200 priv->hw_params.calib_init_cfg |= BIT(IWL_CALIB_TEMP_OFFSET); 181 priv->hw_params.calib_init_cfg |= BIT(IWL_CALIB_TEMP_OFFSET);
201 182
@@ -272,21 +253,13 @@ static int iwl6000_hw_channel_switch(struct iwl_priv *priv,
272 return -EFAULT; 253 return -EFAULT;
273 } 254 }
274 255
275 return iwl_send_cmd_sync(priv, &hcmd); 256 return trans_send_cmd(&priv->trans, &hcmd);
276} 257}
277 258
278static struct iwl_lib_ops iwl6000_lib = { 259static struct iwl_lib_ops iwl6000_lib = {
279 .set_hw_params = iwl6000_hw_set_hw_params, 260 .set_hw_params = iwl6000_hw_set_hw_params,
280 .rx_handler_setup = iwlagn_rx_handler_setup,
281 .setup_deferred_work = iwlagn_setup_deferred_work,
282 .is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
283 .send_tx_power = iwlagn_send_tx_power,
284 .update_chain_flags = iwl_update_chain_flags,
285 .set_channel_switch = iwl6000_hw_channel_switch, 261 .set_channel_switch = iwl6000_hw_channel_switch,
286 .apm_ops = { 262 .nic_config = iwl6000_nic_config,
287 .init = iwl_apm_init,
288 .config = iwl6000_nic_config,
289 },
290 .eeprom_ops = { 263 .eeprom_ops = {
291 .regulatory_bands = { 264 .regulatory_bands = {
292 EEPROM_REG_BAND_1_CHANNELS, 265 EEPROM_REG_BAND_1_CHANNELS,
@@ -297,29 +270,18 @@ static struct iwl_lib_ops iwl6000_lib = {
297 EEPROM_6000_REG_BAND_24_HT40_CHANNELS, 270 EEPROM_6000_REG_BAND_24_HT40_CHANNELS,
298 EEPROM_REG_BAND_52_HT40_CHANNELS 271 EEPROM_REG_BAND_52_HT40_CHANNELS
299 }, 272 },
300 .query_addr = iwlagn_eeprom_query_addr,
301 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower, 273 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
302 }, 274 },
303 .temp_ops = { 275 .temperature = iwlagn_temperature,
304 .temperature = iwlagn_temperature,
305 },
306 .txfifo_flush = iwlagn_txfifo_flush,
307 .dev_txfifo_flush = iwlagn_dev_txfifo_flush,
308}; 276};
309 277
310static struct iwl_lib_ops iwl6030_lib = { 278static struct iwl_lib_ops iwl6030_lib = {
311 .set_hw_params = iwl6000_hw_set_hw_params, 279 .set_hw_params = iwl6000_hw_set_hw_params,
312 .rx_handler_setup = iwlagn_bt_rx_handler_setup, 280 .bt_rx_handler_setup = iwlagn_bt_rx_handler_setup,
313 .setup_deferred_work = iwlagn_bt_setup_deferred_work, 281 .bt_setup_deferred_work = iwlagn_bt_setup_deferred_work,
314 .cancel_deferred_work = iwlagn_bt_cancel_deferred_work, 282 .cancel_deferred_work = iwlagn_bt_cancel_deferred_work,
315 .is_valid_rtc_data_addr = iwlagn_hw_valid_rtc_data_addr,
316 .send_tx_power = iwlagn_send_tx_power,
317 .update_chain_flags = iwl_update_chain_flags,
318 .set_channel_switch = iwl6000_hw_channel_switch, 283 .set_channel_switch = iwl6000_hw_channel_switch,
319 .apm_ops = { 284 .nic_config = iwl6000_nic_config,
320 .init = iwl_apm_init,
321 .config = iwl6000_nic_config,
322 },
323 .eeprom_ops = { 285 .eeprom_ops = {
324 .regulatory_bands = { 286 .regulatory_bands = {
325 EEPROM_REG_BAND_1_CHANNELS, 287 EEPROM_REG_BAND_1_CHANNELS,
@@ -330,48 +292,9 @@ static struct iwl_lib_ops iwl6030_lib = {
330 EEPROM_6000_REG_BAND_24_HT40_CHANNELS, 292 EEPROM_6000_REG_BAND_24_HT40_CHANNELS,
331 EEPROM_REG_BAND_52_HT40_CHANNELS 293 EEPROM_REG_BAND_52_HT40_CHANNELS
332 }, 294 },
333 .query_addr = iwlagn_eeprom_query_addr,
334 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower, 295 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
335 }, 296 },
336 .temp_ops = { 297 .temperature = iwlagn_temperature,
337 .temperature = iwlagn_temperature,
338 },
339 .txfifo_flush = iwlagn_txfifo_flush,
340 .dev_txfifo_flush = iwlagn_dev_txfifo_flush,
341};
342
343static struct iwl_nic_ops iwl6050_nic_ops = {
344 .additional_nic_config = &iwl6050_additional_nic_config,
345};
346
347static struct iwl_nic_ops iwl6150_nic_ops = {
348 .additional_nic_config = &iwl6150_additional_nic_config,
349};
350
351static const struct iwl_ops iwl6000_ops = {
352 .lib = &iwl6000_lib,
353 .hcmd = &iwlagn_hcmd,
354 .utils = &iwlagn_hcmd_utils,
355};
356
357static const struct iwl_ops iwl6050_ops = {
358 .lib = &iwl6000_lib,
359 .hcmd = &iwlagn_hcmd,
360 .utils = &iwlagn_hcmd_utils,
361 .nic = &iwl6050_nic_ops,
362};
363
364static const struct iwl_ops iwl6150_ops = {
365 .lib = &iwl6000_lib,
366 .hcmd = &iwlagn_hcmd,
367 .utils = &iwlagn_hcmd_utils,
368 .nic = &iwl6150_nic_ops,
369};
370
371static const struct iwl_ops iwl6030_ops = {
372 .lib = &iwl6030_lib,
373 .hcmd = &iwlagn_bt_hcmd,
374 .utils = &iwlagn_hcmd_utils,
375}; 298};
376 299
377static struct iwl_base_params iwl6000_base_params = { 300static struct iwl_base_params iwl6000_base_params = {
@@ -447,7 +370,7 @@ static struct iwl_bt_params iwl6000_bt_params = {
447 .ucode_api_min = IWL6000G2_UCODE_API_MIN, \ 370 .ucode_api_min = IWL6000G2_UCODE_API_MIN, \
448 .eeprom_ver = EEPROM_6005_EEPROM_VERSION, \ 371 .eeprom_ver = EEPROM_6005_EEPROM_VERSION, \
449 .eeprom_calib_ver = EEPROM_6005_TX_POWER_VERSION, \ 372 .eeprom_calib_ver = EEPROM_6005_TX_POWER_VERSION, \
450 .ops = &iwl6000_ops, \ 373 .lib = &iwl6000_lib, \
451 .base_params = &iwl6000_g2_base_params, \ 374 .base_params = &iwl6000_g2_base_params, \
452 .need_dc_calib = true, \ 375 .need_dc_calib = true, \
453 .need_temp_offset_calib = true, \ 376 .need_temp_offset_calib = true, \
@@ -475,7 +398,7 @@ struct iwl_cfg iwl6005_2bg_cfg = {
475 .ucode_api_min = IWL6000G2_UCODE_API_MIN, \ 398 .ucode_api_min = IWL6000G2_UCODE_API_MIN, \
476 .eeprom_ver = EEPROM_6030_EEPROM_VERSION, \ 399 .eeprom_ver = EEPROM_6030_EEPROM_VERSION, \
477 .eeprom_calib_ver = EEPROM_6030_TX_POWER_VERSION, \ 400 .eeprom_calib_ver = EEPROM_6030_TX_POWER_VERSION, \
478 .ops = &iwl6030_ops, \ 401 .lib = &iwl6030_lib, \
479 .base_params = &iwl6000_g2_base_params, \ 402 .base_params = &iwl6000_g2_base_params, \
480 .bt_params = &iwl6000_bt_params, \ 403 .bt_params = &iwl6000_bt_params, \
481 .need_dc_calib = true, \ 404 .need_dc_calib = true, \
@@ -556,7 +479,7 @@ struct iwl_cfg iwl130_bg_cfg = {
556 .valid_rx_ant = ANT_BC, /* .cfg overwrite */ \ 479 .valid_rx_ant = ANT_BC, /* .cfg overwrite */ \
557 .eeprom_ver = EEPROM_6000_EEPROM_VERSION, \ 480 .eeprom_ver = EEPROM_6000_EEPROM_VERSION, \
558 .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION, \ 481 .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION, \
559 .ops = &iwl6000_ops, \ 482 .lib = &iwl6000_lib, \
560 .base_params = &iwl6000_base_params, \ 483 .base_params = &iwl6000_base_params, \
561 .pa_type = IWL_PA_INTERNAL, \ 484 .pa_type = IWL_PA_INTERNAL, \
562 .led_mode = IWL_LED_BLINK 485 .led_mode = IWL_LED_BLINK
@@ -583,7 +506,8 @@ struct iwl_cfg iwl6000i_2bg_cfg = {
583 .ucode_api_min = IWL6050_UCODE_API_MIN, \ 506 .ucode_api_min = IWL6050_UCODE_API_MIN, \
584 .valid_tx_ant = ANT_AB, /* .cfg overwrite */ \ 507 .valid_tx_ant = ANT_AB, /* .cfg overwrite */ \
585 .valid_rx_ant = ANT_AB, /* .cfg overwrite */ \ 508 .valid_rx_ant = ANT_AB, /* .cfg overwrite */ \
586 .ops = &iwl6050_ops, \ 509 .lib = &iwl6000_lib, \
510 .additional_nic_config = iwl6050_additional_nic_config, \
587 .eeprom_ver = EEPROM_6050_EEPROM_VERSION, \ 511 .eeprom_ver = EEPROM_6050_EEPROM_VERSION, \
588 .eeprom_calib_ver = EEPROM_6050_TX_POWER_VERSION, \ 512 .eeprom_calib_ver = EEPROM_6050_TX_POWER_VERSION, \
589 .base_params = &iwl6050_base_params, \ 513 .base_params = &iwl6050_base_params, \
@@ -606,7 +530,8 @@ struct iwl_cfg iwl6050_2abg_cfg = {
606 .fw_name_pre = IWL6050_FW_PRE, \ 530 .fw_name_pre = IWL6050_FW_PRE, \
607 .ucode_api_max = IWL6050_UCODE_API_MAX, \ 531 .ucode_api_max = IWL6050_UCODE_API_MAX, \
608 .ucode_api_min = IWL6050_UCODE_API_MIN, \ 532 .ucode_api_min = IWL6050_UCODE_API_MIN, \
609 .ops = &iwl6150_ops, \ 533 .lib = &iwl6000_lib, \
534 .additional_nic_config = iwl6150_additional_nic_config, \
610 .eeprom_ver = EEPROM_6150_EEPROM_VERSION, \ 535 .eeprom_ver = EEPROM_6150_EEPROM_VERSION, \
611 .eeprom_calib_ver = EEPROM_6150_TX_POWER_VERSION, \ 536 .eeprom_calib_ver = EEPROM_6150_TX_POWER_VERSION, \
612 .base_params = &iwl6050_base_params, \ 537 .base_params = &iwl6050_base_params, \
@@ -632,7 +557,7 @@ struct iwl_cfg iwl6000_3agn_cfg = {
632 .ucode_api_min = IWL6000_UCODE_API_MIN, 557 .ucode_api_min = IWL6000_UCODE_API_MIN,
633 .eeprom_ver = EEPROM_6000_EEPROM_VERSION, 558 .eeprom_ver = EEPROM_6000_EEPROM_VERSION,
634 .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION, 559 .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION,
635 .ops = &iwl6000_ops, 560 .lib = &iwl6000_lib,
636 .base_params = &iwl6000_base_params, 561 .base_params = &iwl6000_base_params,
637 .ht_params = &iwl6000_ht_params, 562 .ht_params = &iwl6000_ht_params,
638 .need_dc_calib = true, 563 .need_dc_calib = true,
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-calib.c b/drivers/net/wireless/iwlwifi/iwl-agn-calib.c
index c9255def1080..72d6297602b8 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-calib.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-calib.c
@@ -66,6 +66,8 @@
66#include "iwl-dev.h" 66#include "iwl-dev.h"
67#include "iwl-core.h" 67#include "iwl-core.h"
68#include "iwl-agn-calib.h" 68#include "iwl-agn-calib.h"
69#include "iwl-trans.h"
70#include "iwl-agn.h"
69 71
70/***************************************************************************** 72/*****************************************************************************
71 * INIT calibrations framework 73 * INIT calibrations framework
@@ -87,6 +89,7 @@ int iwl_send_calib_results(struct iwl_priv *priv)
87 89
88 struct iwl_host_cmd hcmd = { 90 struct iwl_host_cmd hcmd = {
89 .id = REPLY_PHY_CALIBRATION_CMD, 91 .id = REPLY_PHY_CALIBRATION_CMD,
92 .flags = CMD_SYNC,
90 }; 93 };
91 94
92 for (i = 0; i < IWL_CALIB_MAX; i++) { 95 for (i = 0; i < IWL_CALIB_MAX; i++) {
@@ -95,7 +98,7 @@ int iwl_send_calib_results(struct iwl_priv *priv)
95 hcmd.len[0] = priv->calib_results[i].buf_len; 98 hcmd.len[0] = priv->calib_results[i].buf_len;
96 hcmd.data[0] = priv->calib_results[i].buf; 99 hcmd.data[0] = priv->calib_results[i].buf;
97 hcmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY; 100 hcmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
98 ret = iwl_send_cmd_sync(priv, &hcmd); 101 ret = trans_send_cmd(&priv->trans, &hcmd);
99 if (ret) { 102 if (ret) {
100 IWL_ERR(priv, "Error %d iteration %d\n", 103 IWL_ERR(priv, "Error %d iteration %d\n",
101 ret, i); 104 ret, i);
@@ -481,7 +484,7 @@ static int iwl_sensitivity_write(struct iwl_priv *priv)
481 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]), 484 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
482 sizeof(u16)*HD_TABLE_SIZE); 485 sizeof(u16)*HD_TABLE_SIZE);
483 486
484 return iwl_send_cmd(priv, &cmd_out); 487 return trans_send_cmd(&priv->trans, &cmd_out);
485} 488}
486 489
487/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */ 490/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
@@ -545,7 +548,7 @@ static int iwl_enhance_sensitivity_write(struct iwl_priv *priv)
545 &(cmd.enhance_table[HD_INA_NON_SQUARE_DET_OFDM_INDEX]), 548 &(cmd.enhance_table[HD_INA_NON_SQUARE_DET_OFDM_INDEX]),
546 sizeof(u16)*ENHANCE_HD_TABLE_ENTRIES); 549 sizeof(u16)*ENHANCE_HD_TABLE_ENTRIES);
547 550
548 return iwl_send_cmd(priv, &cmd_out); 551 return trans_send_cmd(&priv->trans, &cmd_out);
549} 552}
550 553
551void iwl_init_sensitivity(struct iwl_priv *priv) 554void iwl_init_sensitivity(struct iwl_priv *priv)
@@ -837,6 +840,65 @@ static void iwl_find_disconn_antenna(struct iwl_priv *priv, u32* average_sig,
837 active_chains); 840 active_chains);
838} 841}
839 842
843static void iwlagn_gain_computation(struct iwl_priv *priv,
844 u32 average_noise[NUM_RX_CHAINS],
845 u16 min_average_noise_antenna_i,
846 u32 min_average_noise,
847 u8 default_chain)
848{
849 int i;
850 s32 delta_g;
851 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
852
853 /*
854 * Find Gain Code for the chains based on "default chain"
855 */
856 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
857 if ((data->disconn_array[i])) {
858 data->delta_gain_code[i] = 0;
859 continue;
860 }
861
862 delta_g = (priv->cfg->base_params->chain_noise_scale *
863 ((s32)average_noise[default_chain] -
864 (s32)average_noise[i])) / 1500;
865
866 /* bound gain by 2 bits value max, 3rd bit is sign */
867 data->delta_gain_code[i] =
868 min(abs(delta_g),
869 (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
870
871 if (delta_g < 0)
872 /*
873 * set negative sign ...
874 * note to Intel developers: This is uCode API format,
875 * not the format of any internal device registers.
876 * Do not change this format for e.g. 6050 or similar
877 * devices. Change format only if more resolution
878 * (i.e. more than 2 bits magnitude) is needed.
879 */
880 data->delta_gain_code[i] |= (1 << 2);
881 }
882
883 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
884 data->delta_gain_code[1], data->delta_gain_code[2]);
885
886 if (!data->radio_write) {
887 struct iwl_calib_chain_noise_gain_cmd cmd;
888
889 memset(&cmd, 0, sizeof(cmd));
890
891 iwl_set_calib_hdr(&cmd.hdr,
892 priv->phy_calib_chain_noise_gain_cmd);
893 cmd.delta_gain_1 = data->delta_gain_code[1];
894 cmd.delta_gain_2 = data->delta_gain_code[2];
895 trans_send_cmd_pdu(&priv->trans, REPLY_PHY_CALIBRATION_CMD,
896 CMD_ASYNC, sizeof(cmd), &cmd);
897
898 data->radio_write = 1;
899 data->state = IWL_CHAIN_NOISE_CALIBRATED;
900 }
901}
840 902
841/* 903/*
842 * Accumulate 16 beacons of signal and noise statistics for each of 904 * Accumulate 16 beacons of signal and noise statistics for each of
@@ -991,16 +1053,14 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv)
991 IWL_DEBUG_CALIB(priv, "min_average_noise = %d, antenna %d\n", 1053 IWL_DEBUG_CALIB(priv, "min_average_noise = %d, antenna %d\n",
992 min_average_noise, min_average_noise_antenna_i); 1054 min_average_noise, min_average_noise_antenna_i);
993 1055
994 if (priv->cfg->ops->utils->gain_computation) 1056 iwlagn_gain_computation(priv, average_noise,
995 priv->cfg->ops->utils->gain_computation(priv, average_noise,
996 min_average_noise_antenna_i, min_average_noise, 1057 min_average_noise_antenna_i, min_average_noise,
997 find_first_chain(priv->cfg->valid_rx_ant)); 1058 find_first_chain(priv->cfg->valid_rx_ant));
998 1059
999 /* Some power changes may have been made during the calibration. 1060 /* Some power changes may have been made during the calibration.
1000 * Update and commit the RXON 1061 * Update and commit the RXON
1001 */ 1062 */
1002 if (priv->cfg->ops->lib->update_chain_flags) 1063 iwl_update_chain_flags(priv);
1003 priv->cfg->ops->lib->update_chain_flags(priv);
1004 1064
1005 data->state = IWL_CHAIN_NOISE_DONE; 1065 data->state = IWL_CHAIN_NOISE_DONE;
1006 iwl_power_update_mode(priv, false); 1066 iwl_power_update_mode(priv, false);
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-calib.h b/drivers/net/wireless/iwlwifi/iwl-agn-calib.h
index 4ef4dd934254..a869fc9205d2 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-calib.h
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-calib.h
@@ -71,13 +71,6 @@ void iwl_sensitivity_calibration(struct iwl_priv *priv);
71 71
72void iwl_init_sensitivity(struct iwl_priv *priv); 72void iwl_init_sensitivity(struct iwl_priv *priv);
73void iwl_reset_run_time_calib(struct iwl_priv *priv); 73void iwl_reset_run_time_calib(struct iwl_priv *priv);
74static inline void iwl_chain_noise_reset(struct iwl_priv *priv)
75{
76
77 if (!priv->disable_chain_noise_cal &&
78 priv->cfg->ops->utils->chain_noise_reset)
79 priv->cfg->ops->utils->chain_noise_reset(priv);
80}
81 74
82int iwl_send_calib_results(struct iwl_priv *priv); 75int iwl_send_calib_results(struct iwl_priv *priv);
83int iwl_calib_set(struct iwl_calib_result *res, const u8 *buf, int len); 76int iwl_calib_set(struct iwl_calib_result *res, const u8 *buf, int len);
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c
index 2ef9448b1c20..b8347db850e7 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c
@@ -108,18 +108,16 @@ err:
108 108
109int iwl_eeprom_check_sku(struct iwl_priv *priv) 109int iwl_eeprom_check_sku(struct iwl_priv *priv)
110{ 110{
111 u16 eeprom_sku;
112 u16 radio_cfg; 111 u16 radio_cfg;
113 112
114 eeprom_sku = iwl_eeprom_query16(priv, EEPROM_SKU_CAP);
115
116 if (!priv->cfg->sku) { 113 if (!priv->cfg->sku) {
117 /* not using sku overwrite */ 114 /* not using sku overwrite */
118 priv->cfg->sku = 115 priv->cfg->sku = iwl_eeprom_query16(priv, EEPROM_SKU_CAP);
119 ((eeprom_sku & EEPROM_SKU_CAP_BAND_SELECTION) >> 116 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE &&
120 EEPROM_SKU_CAP_BAND_POS); 117 !priv->cfg->ht_params) {
121 if (eeprom_sku & EEPROM_SKU_CAP_11N_ENABLE) 118 IWL_ERR(priv, "Invalid 11n configuration\n");
122 priv->cfg->sku |= IWL_SKU_N; 119 return -EINVAL;
120 }
123 } 121 }
124 if (!priv->cfg->sku) { 122 if (!priv->cfg->sku) {
125 IWL_ERR(priv, "Invalid device sku\n"); 123 IWL_ERR(priv, "Invalid device sku\n");
@@ -152,7 +150,7 @@ int iwl_eeprom_check_sku(struct iwl_priv *priv)
152 150
153void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac) 151void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac)
154{ 152{
155 const u8 *addr = priv->cfg->ops->lib->eeprom_ops.query_addr(priv, 153 const u8 *addr = iwl_eeprom_query_addr(priv,
156 EEPROM_MAC_ADDRESS); 154 EEPROM_MAC_ADDRESS);
157 memcpy(mac, addr, ETH_ALEN); 155 memcpy(mac, addr, ETH_ALEN);
158} 156}
@@ -247,10 +245,10 @@ void iwlcore_eeprom_enhanced_txpower(struct iwl_priv *priv)
247 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8); 245 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8);
248 246
249 /* the length is in 16-bit words, but we want entries */ 247 /* the length is in 16-bit words, but we want entries */
250 txp_len = (__le16 *) iwlagn_eeprom_query_addr(priv, EEPROM_TXP_SZ_OFFS); 248 txp_len = (__le16 *) iwl_eeprom_query_addr(priv, EEPROM_TXP_SZ_OFFS);
251 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN; 249 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN;
252 250
253 txp_array = (void *) iwlagn_eeprom_query_addr(priv, EEPROM_TXP_OFFS); 251 txp_array = (void *) iwl_eeprom_query_addr(priv, EEPROM_TXP_OFFS);
254 252
255 for (idx = 0; idx < entries; idx++) { 253 for (idx = 0; idx < entries; idx++) {
256 txp = &txp_array[idx]; 254 txp = &txp_array[idx];
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c b/drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c
deleted file mode 100644
index 23fa93deae96..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c
+++ /dev/null
@@ -1,328 +0,0 @@
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/sched.h>
34
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-io.h"
38#include "iwl-agn.h"
39
40int iwlagn_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
41{
42 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
43 .valid = cpu_to_le32(valid_tx_ant),
44 };
45
46 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
47 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
48 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
49 sizeof(struct iwl_tx_ant_config_cmd),
50 &tx_ant_cmd);
51 } else {
52 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
53 return -EOPNOTSUPP;
54 }
55}
56
57static u16 iwlagn_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
58{
59 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
60 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
61 memcpy(addsta, cmd, size);
62 /* resrved in 5000 */
63 addsta->rate_n_flags = cpu_to_le16(0);
64 return size;
65}
66
67static void iwlagn_gain_computation(struct iwl_priv *priv,
68 u32 average_noise[NUM_RX_CHAINS],
69 u16 min_average_noise_antenna_i,
70 u32 min_average_noise,
71 u8 default_chain)
72{
73 int i;
74 s32 delta_g;
75 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
76
77 /*
78 * Find Gain Code for the chains based on "default chain"
79 */
80 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
81 if ((data->disconn_array[i])) {
82 data->delta_gain_code[i] = 0;
83 continue;
84 }
85
86 delta_g = (priv->cfg->base_params->chain_noise_scale *
87 ((s32)average_noise[default_chain] -
88 (s32)average_noise[i])) / 1500;
89
90 /* bound gain by 2 bits value max, 3rd bit is sign */
91 data->delta_gain_code[i] =
92 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
93
94 if (delta_g < 0)
95 /*
96 * set negative sign ...
97 * note to Intel developers: This is uCode API format,
98 * not the format of any internal device registers.
99 * Do not change this format for e.g. 6050 or similar
100 * devices. Change format only if more resolution
101 * (i.e. more than 2 bits magnitude) is needed.
102 */
103 data->delta_gain_code[i] |= (1 << 2);
104 }
105
106 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
107 data->delta_gain_code[1], data->delta_gain_code[2]);
108
109 if (!data->radio_write) {
110 struct iwl_calib_chain_noise_gain_cmd cmd;
111
112 memset(&cmd, 0, sizeof(cmd));
113
114 cmd.hdr.op_code = priv->_agn.phy_calib_chain_noise_gain_cmd;
115 cmd.hdr.first_group = 0;
116 cmd.hdr.groups_num = 1;
117 cmd.hdr.data_valid = 1;
118 cmd.delta_gain_1 = data->delta_gain_code[1];
119 cmd.delta_gain_2 = data->delta_gain_code[2];
120 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
121 sizeof(cmd), &cmd, NULL);
122
123 data->radio_write = 1;
124 data->state = IWL_CHAIN_NOISE_CALIBRATED;
125 }
126}
127
128static void iwlagn_chain_noise_reset(struct iwl_priv *priv)
129{
130 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
131 int ret;
132
133 if ((data->state == IWL_CHAIN_NOISE_ALIVE) &&
134 iwl_is_any_associated(priv)) {
135 struct iwl_calib_chain_noise_reset_cmd cmd;
136
137 /* clear data for chain noise calibration algorithm */
138 data->chain_noise_a = 0;
139 data->chain_noise_b = 0;
140 data->chain_noise_c = 0;
141 data->chain_signal_a = 0;
142 data->chain_signal_b = 0;
143 data->chain_signal_c = 0;
144 data->beacon_count = 0;
145
146 memset(&cmd, 0, sizeof(cmd));
147 cmd.hdr.op_code = priv->_agn.phy_calib_chain_noise_reset_cmd;
148 cmd.hdr.first_group = 0;
149 cmd.hdr.groups_num = 1;
150 cmd.hdr.data_valid = 1;
151 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
152 sizeof(cmd), &cmd);
153 if (ret)
154 IWL_ERR(priv,
155 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
156 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
157 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
158 }
159}
160
161static void iwlagn_tx_cmd_protection(struct iwl_priv *priv,
162 struct ieee80211_tx_info *info,
163 __le16 fc, __le32 *tx_flags)
164{
165 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS ||
166 info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT ||
167 info->flags & IEEE80211_TX_CTL_AMPDU)
168 *tx_flags |= TX_CMD_FLG_PROT_REQUIRE_MSK;
169}
170
171/* Calc max signal level (dBm) among 3 possible receivers */
172static int iwlagn_calc_rssi(struct iwl_priv *priv,
173 struct iwl_rx_phy_res *rx_resp)
174{
175 /* data from PHY/DSP regarding signal strength, etc.,
176 * contents are always there, not configurable by host
177 */
178 struct iwlagn_non_cfg_phy *ncphy =
179 (struct iwlagn_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
180 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
181 u8 agc;
182
183 val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_AGC_IDX]);
184 agc = (val & IWLAGN_OFDM_AGC_MSK) >> IWLAGN_OFDM_AGC_BIT_POS;
185
186 /* Find max rssi among 3 possible receivers.
187 * These values are measured by the digital signal processor (DSP).
188 * They should stay fairly constant even as the signal strength varies,
189 * if the radio's automatic gain control (AGC) is working right.
190 * AGC value (see below) will provide the "interesting" info.
191 */
192 val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_RSSI_AB_IDX]);
193 rssi_a = (val & IWLAGN_OFDM_RSSI_INBAND_A_BITMSK) >>
194 IWLAGN_OFDM_RSSI_A_BIT_POS;
195 rssi_b = (val & IWLAGN_OFDM_RSSI_INBAND_B_BITMSK) >>
196 IWLAGN_OFDM_RSSI_B_BIT_POS;
197 val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_RSSI_C_IDX]);
198 rssi_c = (val & IWLAGN_OFDM_RSSI_INBAND_C_BITMSK) >>
199 IWLAGN_OFDM_RSSI_C_BIT_POS;
200
201 max_rssi = max_t(u32, rssi_a, rssi_b);
202 max_rssi = max_t(u32, max_rssi, rssi_c);
203
204 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
205 rssi_a, rssi_b, rssi_c, max_rssi, agc);
206
207 /* dBm = max_rssi dB - agc dB - constant.
208 * Higher AGC (higher radio gain) means lower signal. */
209 return max_rssi - agc - IWLAGN_RSSI_OFFSET;
210}
211
212static int iwlagn_set_pan_params(struct iwl_priv *priv)
213{
214 struct iwl_wipan_params_cmd cmd;
215 struct iwl_rxon_context *ctx_bss, *ctx_pan;
216 int slot0 = 300, slot1 = 0;
217 int ret;
218
219 if (priv->valid_contexts == BIT(IWL_RXON_CTX_BSS))
220 return 0;
221
222 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
223
224 lockdep_assert_held(&priv->mutex);
225
226 ctx_bss = &priv->contexts[IWL_RXON_CTX_BSS];
227 ctx_pan = &priv->contexts[IWL_RXON_CTX_PAN];
228
229 /*
230 * If the PAN context is inactive, then we don't need
231 * to update the PAN parameters, the last thing we'll
232 * have done before it goes inactive is making the PAN
233 * parameters be WLAN-only.
234 */
235 if (!ctx_pan->is_active)
236 return 0;
237
238 memset(&cmd, 0, sizeof(cmd));
239
240 /* only 2 slots are currently allowed */
241 cmd.num_slots = 2;
242
243 cmd.slots[0].type = 0; /* BSS */
244 cmd.slots[1].type = 1; /* PAN */
245
246 if (priv->_agn.hw_roc_channel) {
247 /* both contexts must be used for this to happen */
248 slot1 = priv->_agn.hw_roc_duration;
249 slot0 = IWL_MIN_SLOT_TIME;
250 } else if (ctx_bss->vif && ctx_pan->vif) {
251 int bcnint = ctx_pan->vif->bss_conf.beacon_int;
252 int dtim = ctx_pan->vif->bss_conf.dtim_period ?: 1;
253
254 /* should be set, but seems unused?? */
255 cmd.flags |= cpu_to_le16(IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE);
256
257 if (ctx_pan->vif->type == NL80211_IFTYPE_AP &&
258 bcnint &&
259 bcnint != ctx_bss->vif->bss_conf.beacon_int) {
260 IWL_ERR(priv,
261 "beacon intervals don't match (%d, %d)\n",
262 ctx_bss->vif->bss_conf.beacon_int,
263 ctx_pan->vif->bss_conf.beacon_int);
264 } else
265 bcnint = max_t(int, bcnint,
266 ctx_bss->vif->bss_conf.beacon_int);
267 if (!bcnint)
268 bcnint = DEFAULT_BEACON_INTERVAL;
269 slot0 = bcnint / 2;
270 slot1 = bcnint - slot0;
271
272 if (test_bit(STATUS_SCAN_HW, &priv->status) ||
273 (!ctx_bss->vif->bss_conf.idle &&
274 !ctx_bss->vif->bss_conf.assoc)) {
275 slot0 = dtim * bcnint * 3 - IWL_MIN_SLOT_TIME;
276 slot1 = IWL_MIN_SLOT_TIME;
277 } else if (!ctx_pan->vif->bss_conf.idle &&
278 !ctx_pan->vif->bss_conf.assoc) {
279 slot1 = bcnint * 3 - IWL_MIN_SLOT_TIME;
280 slot0 = IWL_MIN_SLOT_TIME;
281 }
282 } else if (ctx_pan->vif) {
283 slot0 = 0;
284 slot1 = max_t(int, 1, ctx_pan->vif->bss_conf.dtim_period) *
285 ctx_pan->vif->bss_conf.beacon_int;
286 slot1 = max_t(int, DEFAULT_BEACON_INTERVAL, slot1);
287
288 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
289 slot0 = slot1 * 3 - IWL_MIN_SLOT_TIME;
290 slot1 = IWL_MIN_SLOT_TIME;
291 }
292 }
293
294 cmd.slots[0].width = cpu_to_le16(slot0);
295 cmd.slots[1].width = cpu_to_le16(slot1);
296
297 ret = iwl_send_cmd_pdu(priv, REPLY_WIPAN_PARAMS, sizeof(cmd), &cmd);
298 if (ret)
299 IWL_ERR(priv, "Error setting PAN parameters (%d)\n", ret);
300
301 return ret;
302}
303
304struct iwl_hcmd_ops iwlagn_hcmd = {
305 .commit_rxon = iwlagn_commit_rxon,
306 .set_rxon_chain = iwlagn_set_rxon_chain,
307 .set_tx_ant = iwlagn_send_tx_ant_config,
308 .send_bt_config = iwl_send_bt_config,
309 .set_pan_params = iwlagn_set_pan_params,
310};
311
312struct iwl_hcmd_ops iwlagn_bt_hcmd = {
313 .commit_rxon = iwlagn_commit_rxon,
314 .set_rxon_chain = iwlagn_set_rxon_chain,
315 .set_tx_ant = iwlagn_send_tx_ant_config,
316 .send_bt_config = iwlagn_send_advance_bt_config,
317 .set_pan_params = iwlagn_set_pan_params,
318};
319
320struct iwl_hcmd_utils_ops iwlagn_hcmd_utils = {
321 .build_addsta_hcmd = iwlagn_build_addsta_hcmd,
322 .gain_computation = iwlagn_gain_computation,
323 .chain_noise_reset = iwlagn_chain_noise_reset,
324 .tx_cmd_protection = iwlagn_tx_cmd_protection,
325 .calc_rssi = iwlagn_calc_rssi,
326 .request_scan = iwlagn_request_scan,
327 .post_scan = iwlagn_post_scan,
328};
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-hw.h b/drivers/net/wireless/iwlwifi/iwl-agn-hw.h
index 7bd19f4e66de..0e5b842529c4 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-hw.h
@@ -81,13 +81,6 @@
81/* RSSI to dBm */ 81/* RSSI to dBm */
82#define IWLAGN_RSSI_OFFSET 44 82#define IWLAGN_RSSI_OFFSET 44
83 83
84/* PCI registers */
85#define PCI_CFG_RETRY_TIMEOUT 0x041
86
87/* PCI register values */
88#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
89#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
90
91#define IWLAGN_DEFAULT_TX_RETRY 15 84#define IWLAGN_DEFAULT_TX_RETRY 15
92 85
93/* Limit range of txpower output target to be between these values */ 86/* Limit range of txpower output target to be between these values */
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-ict.c b/drivers/net/wireless/iwlwifi/iwl-agn-ict.c
deleted file mode 100644
index 0d5fda44c3a3..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-agn-ict.c
+++ /dev/null
@@ -1,306 +0,0 @@
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/gfp.h>
34#include <net/mac80211.h>
35
36#include "iwl-dev.h"
37#include "iwl-core.h"
38#include "iwl-agn.h"
39#include "iwl-helpers.h"
40
41#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
42
43/* Free dram table */
44void iwl_free_isr_ict(struct iwl_priv *priv)
45{
46 if (priv->_agn.ict_tbl_vir) {
47 dma_free_coherent(&priv->pci_dev->dev,
48 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
49 priv->_agn.ict_tbl_vir,
50 priv->_agn.ict_tbl_dma);
51 priv->_agn.ict_tbl_vir = NULL;
52 }
53}
54
55
56/* allocate dram shared table it is a PAGE_SIZE aligned
57 * also reset all data related to ICT table interrupt.
58 */
59int iwl_alloc_isr_ict(struct iwl_priv *priv)
60{
61
62 /* allocate shrared data table */
63 priv->_agn.ict_tbl_vir =
64 dma_alloc_coherent(&priv->pci_dev->dev,
65 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
66 &priv->_agn.ict_tbl_dma, GFP_KERNEL);
67 if (!priv->_agn.ict_tbl_vir)
68 return -ENOMEM;
69
70 /* align table to PAGE_SIZE boundary */
71 priv->_agn.aligned_ict_tbl_dma = ALIGN(priv->_agn.ict_tbl_dma, PAGE_SIZE);
72
73 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
74 (unsigned long long)priv->_agn.ict_tbl_dma,
75 (unsigned long long)priv->_agn.aligned_ict_tbl_dma,
76 (int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
77
78 priv->_agn.ict_tbl = priv->_agn.ict_tbl_vir +
79 (priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma);
80
81 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
82 priv->_agn.ict_tbl, priv->_agn.ict_tbl_vir,
83 (int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
84
85 /* reset table and index to all 0 */
86 memset(priv->_agn.ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
87 priv->_agn.ict_index = 0;
88
89 /* add periodic RX interrupt */
90 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
91 return 0;
92}
93
94/* Device is going up inform it about using ICT interrupt table,
95 * also we need to tell the driver to start using ICT interrupt.
96 */
97int iwl_reset_ict(struct iwl_priv *priv)
98{
99 u32 val;
100 unsigned long flags;
101
102 if (!priv->_agn.ict_tbl_vir)
103 return 0;
104
105 spin_lock_irqsave(&priv->lock, flags);
106 iwl_disable_interrupts(priv);
107
108 memset(&priv->_agn.ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
109
110 val = priv->_agn.aligned_ict_tbl_dma >> PAGE_SHIFT;
111
112 val |= CSR_DRAM_INT_TBL_ENABLE;
113 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
114
115 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
116 "aligned dma address %Lx\n",
117 val, (unsigned long long)priv->_agn.aligned_ict_tbl_dma);
118
119 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
120 priv->_agn.use_ict = true;
121 priv->_agn.ict_index = 0;
122 iwl_write32(priv, CSR_INT, priv->inta_mask);
123 iwl_enable_interrupts(priv);
124 spin_unlock_irqrestore(&priv->lock, flags);
125
126 return 0;
127}
128
129/* Device is going down disable ict interrupt usage */
130void iwl_disable_ict(struct iwl_priv *priv)
131{
132 unsigned long flags;
133
134 spin_lock_irqsave(&priv->lock, flags);
135 priv->_agn.use_ict = false;
136 spin_unlock_irqrestore(&priv->lock, flags);
137}
138
139static irqreturn_t iwl_isr(int irq, void *data)
140{
141 struct iwl_priv *priv = data;
142 u32 inta, inta_mask;
143 unsigned long flags;
144#ifdef CONFIG_IWLWIFI_DEBUG
145 u32 inta_fh;
146#endif
147 if (!priv)
148 return IRQ_NONE;
149
150 spin_lock_irqsave(&priv->lock, flags);
151
152 /* Disable (but don't clear!) interrupts here to avoid
153 * back-to-back ISRs and sporadic interrupts from our NIC.
154 * If we have something to service, the tasklet will re-enable ints.
155 * If we *don't* have something, we'll re-enable before leaving here. */
156 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
157 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
158
159 /* Discover which interrupts are active/pending */
160 inta = iwl_read32(priv, CSR_INT);
161
162 /* Ignore interrupt if there's nothing in NIC to service.
163 * This may be due to IRQ shared with another device,
164 * or due to sporadic interrupts thrown from our NIC. */
165 if (!inta) {
166 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
167 goto none;
168 }
169
170 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
171 /* Hardware disappeared. It might have already raised
172 * an interrupt */
173 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
174 goto unplugged;
175 }
176
177#ifdef CONFIG_IWLWIFI_DEBUG
178 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
179 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
180 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
181 "fh 0x%08x\n", inta, inta_mask, inta_fh);
182 }
183#endif
184
185 priv->_agn.inta |= inta;
186 /* iwl_irq_tasklet() will service interrupts and re-enable them */
187 if (likely(inta))
188 tasklet_schedule(&priv->irq_tasklet);
189 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
190 iwl_enable_interrupts(priv);
191
192 unplugged:
193 spin_unlock_irqrestore(&priv->lock, flags);
194 return IRQ_HANDLED;
195
196 none:
197 /* re-enable interrupts here since we don't have anything to service. */
198 /* only Re-enable if disabled by irq and no schedules tasklet. */
199 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
200 iwl_enable_interrupts(priv);
201
202 spin_unlock_irqrestore(&priv->lock, flags);
203 return IRQ_NONE;
204}
205
206/* interrupt handler using ict table, with this interrupt driver will
207 * stop using INTA register to get device's interrupt, reading this register
208 * is expensive, device will write interrupts in ICT dram table, increment
209 * index then will fire interrupt to driver, driver will OR all ICT table
210 * entries from current index up to table entry with 0 value. the result is
211 * the interrupt we need to service, driver will set the entries back to 0 and
212 * set index.
213 */
214irqreturn_t iwl_isr_ict(int irq, void *data)
215{
216 struct iwl_priv *priv = data;
217 u32 inta, inta_mask;
218 u32 val = 0;
219 unsigned long flags;
220
221 if (!priv)
222 return IRQ_NONE;
223
224 /* dram interrupt table not set yet,
225 * use legacy interrupt.
226 */
227 if (!priv->_agn.use_ict)
228 return iwl_isr(irq, data);
229
230 spin_lock_irqsave(&priv->lock, flags);
231
232 /* Disable (but don't clear!) interrupts here to avoid
233 * back-to-back ISRs and sporadic interrupts from our NIC.
234 * If we have something to service, the tasklet will re-enable ints.
235 * If we *don't* have something, we'll re-enable before leaving here.
236 */
237 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
238 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
239
240
241 /* Ignore interrupt if there's nothing in NIC to service.
242 * This may be due to IRQ shared with another device,
243 * or due to sporadic interrupts thrown from our NIC. */
244 if (!priv->_agn.ict_tbl[priv->_agn.ict_index]) {
245 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
246 goto none;
247 }
248
249 /* read all entries that not 0 start with ict_index */
250 while (priv->_agn.ict_tbl[priv->_agn.ict_index]) {
251
252 val |= le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]);
253 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
254 priv->_agn.ict_index,
255 le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]));
256 priv->_agn.ict_tbl[priv->_agn.ict_index] = 0;
257 priv->_agn.ict_index = iwl_queue_inc_wrap(priv->_agn.ict_index,
258 ICT_COUNT);
259
260 }
261
262 /* We should not get this value, just ignore it. */
263 if (val == 0xffffffff)
264 val = 0;
265
266 /*
267 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
268 * (bit 15 before shifting it to 31) to clear when using interrupt
269 * coalescing. fortunately, bits 18 and 19 stay set when this happens
270 * so we use them to decide on the real state of the Rx bit.
271 * In order words, bit 15 is set if bit 18 or bit 19 are set.
272 */
273 if (val & 0xC0000)
274 val |= 0x8000;
275
276 inta = (0xff & val) | ((0xff00 & val) << 16);
277 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
278 inta, inta_mask, val);
279
280 inta &= priv->inta_mask;
281 priv->_agn.inta |= inta;
282
283 /* iwl_irq_tasklet() will service interrupts and re-enable them */
284 if (likely(inta))
285 tasklet_schedule(&priv->irq_tasklet);
286 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) {
287 /* Allow interrupt if was disabled by this handler and
288 * no tasklet was schedules, We should not enable interrupt,
289 * tasklet will enable it.
290 */
291 iwl_enable_interrupts(priv);
292 }
293
294 spin_unlock_irqrestore(&priv->lock, flags);
295 return IRQ_HANDLED;
296
297 none:
298 /* re-enable interrupts here since we don't have anything to service.
299 * only Re-enable if disabled by irq.
300 */
301 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
302 iwl_enable_interrupts(priv);
303
304 spin_unlock_irqrestore(&priv->lock, flags);
305 return IRQ_NONE;
306}
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-lib.c b/drivers/net/wireless/iwlwifi/iwl-agn-lib.c
index f803fb62f8bc..3bee0f119bcd 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-lib.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-lib.c
@@ -39,6 +39,7 @@
39#include "iwl-agn-hw.h" 39#include "iwl-agn-hw.h"
40#include "iwl-agn.h" 40#include "iwl-agn.h"
41#include "iwl-sta.h" 41#include "iwl-sta.h"
42#include "iwl-trans.h"
42 43
43static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp) 44static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
44{ 45{
@@ -52,73 +53,73 @@ static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
52 53
53 switch (status) { 54 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY: 55 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++; 56 priv->reply_tx_stats.pp_delay++;
56 break; 57 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES: 58 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++; 59 priv->reply_tx_stats.pp_few_bytes++;
59 break; 60 break;
60 case TX_STATUS_POSTPONE_BT_PRIO: 61 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++; 62 priv->reply_tx_stats.pp_bt_prio++;
62 break; 63 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD: 64 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++; 65 priv->reply_tx_stats.pp_quiet_period++;
65 break; 66 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK: 67 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++; 68 priv->reply_tx_stats.pp_calc_ttak++;
68 break; 69 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY: 70 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++; 71 priv->reply_tx_stats.int_crossed_retry++;
71 break; 72 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT: 73 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++; 74 priv->reply_tx_stats.short_limit++;
74 break; 75 break;
75 case TX_STATUS_FAIL_LONG_LIMIT: 76 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++; 77 priv->reply_tx_stats.long_limit++;
77 break; 78 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN: 79 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++; 80 priv->reply_tx_stats.fifo_underrun++;
80 break; 81 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW: 82 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++; 83 priv->reply_tx_stats.drain_flow++;
83 break; 84 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH: 85 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++; 86 priv->reply_tx_stats.rfkill_flush++;
86 break; 87 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE: 88 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++; 89 priv->reply_tx_stats.life_expire++;
89 break; 90 break;
90 case TX_STATUS_FAIL_DEST_PS: 91 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++; 92 priv->reply_tx_stats.dest_ps++;
92 break; 93 break;
93 case TX_STATUS_FAIL_HOST_ABORTED: 94 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++; 95 priv->reply_tx_stats.host_abort++;
95 break; 96 break;
96 case TX_STATUS_FAIL_BT_RETRY: 97 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++; 98 priv->reply_tx_stats.bt_retry++;
98 break; 99 break;
99 case TX_STATUS_FAIL_STA_INVALID: 100 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++; 101 priv->reply_tx_stats.sta_invalid++;
101 break; 102 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED: 103 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++; 104 priv->reply_tx_stats.frag_drop++;
104 break; 105 break;
105 case TX_STATUS_FAIL_TID_DISABLE: 106 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++; 107 priv->reply_tx_stats.tid_disable++;
107 break; 108 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED: 109 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++; 110 priv->reply_tx_stats.fifo_flush++;
110 break; 111 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL: 112 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++; 113 priv->reply_tx_stats.insuff_cf_poll++;
113 break; 114 break;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX: 115 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++; 116 priv->reply_tx_stats.fail_hw_drop++;
116 break; 117 break;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR: 118 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++; 119 priv->reply_tx_stats.sta_color_mismatch++;
119 break; 120 break;
120 default: 121 default:
121 priv->_agn.reply_tx_stats.unknown++; 122 priv->reply_tx_stats.unknown++;
122 break; 123 break;
123 } 124 }
124} 125}
@@ -129,43 +130,43 @@ static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
129 130
130 switch (status) { 131 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK: 132 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++; 133 priv->reply_agg_tx_stats.underrun++;
133 break; 134 break;
134 case AGG_TX_STATE_BT_PRIO_MSK: 135 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++; 136 priv->reply_agg_tx_stats.bt_prio++;
136 break; 137 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK: 138 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++; 139 priv->reply_agg_tx_stats.few_bytes++;
139 break; 140 break;
140 case AGG_TX_STATE_ABORT_MSK: 141 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++; 142 priv->reply_agg_tx_stats.abort++;
142 break; 143 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK: 144 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++; 145 priv->reply_agg_tx_stats.last_sent_ttl++;
145 break; 146 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK: 147 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++; 148 priv->reply_agg_tx_stats.last_sent_try++;
148 break; 149 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK: 150 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++; 151 priv->reply_agg_tx_stats.last_sent_bt_kill++;
151 break; 152 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK: 153 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++; 154 priv->reply_agg_tx_stats.scd_query++;
154 break; 155 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK: 156 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++; 157 priv->reply_agg_tx_stats.bad_crc32++;
157 break; 158 break;
158 case AGG_TX_STATE_RESPONSE_MSK: 159 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++; 160 priv->reply_agg_tx_stats.response++;
160 break; 161 break;
161 case AGG_TX_STATE_DUMP_TX_MSK: 162 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++; 163 priv->reply_agg_tx_stats.dump_tx++;
163 break; 164 break;
164 case AGG_TX_STATE_DELAY_TX_MSK: 165 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++; 166 priv->reply_agg_tx_stats.delay_tx++;
166 break; 167 break;
167 default: 168 default:
168 priv->_agn.reply_agg_tx_stats.unknown++; 169 priv->reply_agg_tx_stats.unknown++;
169 break; 170 break;
170 } 171 }
171} 172}
@@ -390,8 +391,7 @@ void iwl_check_abort_status(struct iwl_priv *priv,
390 } 391 }
391} 392}
392 393
393static void iwlagn_rx_reply_tx(struct iwl_priv *priv, 394void iwlagn_rx_reply_tx(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
394 struct iwl_rx_mem_buffer *rxb)
395{ 395{
396 struct iwl_rx_packet *pkt = rxb_addr(rxb); 396 struct iwl_rx_packet *pkt = rxb_addr(rxb);
397 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 397 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
@@ -400,6 +400,7 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
400 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 400 struct iwl_tx_queue *txq = &priv->txq[txq_id];
401 struct ieee80211_tx_info *info; 401 struct ieee80211_tx_info *info;
402 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 402 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
403 struct ieee80211_hdr *hdr;
403 struct iwl_tx_info *txb; 404 struct iwl_tx_info *txb;
404 u32 status = le16_to_cpu(tx_resp->status.status); 405 u32 status = le16_to_cpu(tx_resp->status.status);
405 int tid; 406 int tid;
@@ -408,9 +409,9 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
408 unsigned long flags; 409 unsigned long flags;
409 410
410 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 411 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
411 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " 412 IWL_ERR(priv, "%s: Read index for DMA queue txq_id (%d) "
412 "is out of range [0-%d] %d %d\n", txq_id, 413 "index %d is out of range [0-%d] %d %d\n", __func__,
413 index, txq->q.n_bd, txq->q.write_ptr, 414 txq_id, index, txq->q.n_bd, txq->q.write_ptr,
414 txq->q.read_ptr); 415 txq->q.read_ptr);
415 return; 416 return;
416 } 417 }
@@ -426,6 +427,11 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
426 IWLAGN_TX_RES_RA_POS; 427 IWLAGN_TX_RES_RA_POS;
427 428
428 spin_lock_irqsave(&priv->sta_lock, flags); 429 spin_lock_irqsave(&priv->sta_lock, flags);
430
431 hdr = (void *)txb->skb->data;
432 if (!ieee80211_is_data_qos(hdr->frame_control))
433 priv->last_seq_ctl = tx_resp->seq_ctl;
434
429 if (txq->sched_retry) { 435 if (txq->sched_retry) {
430 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp); 436 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
431 struct iwl_ht_agg *agg; 437 struct iwl_ht_agg *agg;
@@ -438,7 +444,7 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
438 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 && 444 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
439 priv->cfg->bt_params && 445 priv->cfg->bt_params &&
440 priv->cfg->bt_params->advanced_bt_coexist) { 446 priv->cfg->bt_params->advanced_bt_coexist) {
441 IWL_WARN(priv, "receive reply tx with bt_kill\n"); 447 IWL_DEBUG_COEX(priv, "receive reply tx with bt_kill\n");
442 } 448 }
443 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 449 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
444 450
@@ -478,27 +484,6 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
478 spin_unlock_irqrestore(&priv->sta_lock, flags); 484 spin_unlock_irqrestore(&priv->sta_lock, flags);
479} 485}
480 486
481void iwlagn_rx_handler_setup(struct iwl_priv *priv)
482{
483 /* init calibration handlers */
484 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
485 iwlagn_rx_calib_result;
486 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
487
488 /* set up notification wait support */
489 spin_lock_init(&priv->_agn.notif_wait_lock);
490 INIT_LIST_HEAD(&priv->_agn.notif_waits);
491 init_waitqueue_head(&priv->_agn.notif_waitq);
492}
493
494void iwlagn_setup_deferred_work(struct iwl_priv *priv)
495{
496 /*
497 * nothing need to be done here anymore
498 * still keep for future use if needed
499 */
500}
501
502int iwlagn_hw_valid_rtc_data_addr(u32 addr) 487int iwlagn_hw_valid_rtc_data_addr(u32 addr)
503{ 488{
504 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) && 489 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
@@ -540,8 +525,8 @@ int iwlagn_send_tx_power(struct iwl_priv *priv)
540 else 525 else
541 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; 526 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
542 527
543 return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd), 528 return trans_send_cmd_pdu(&priv->trans, tx_ant_cfg_cmd, CMD_SYNC,
544 &tx_power_cmd); 529 sizeof(tx_power_cmd), &tx_power_cmd);
545} 530}
546 531
547void iwlagn_temperature(struct iwl_priv *priv) 532void iwlagn_temperature(struct iwl_priv *priv)
@@ -610,8 +595,7 @@ static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
610 return (address & ADDRESS_MSK) + (offset << 1); 595 return (address & ADDRESS_MSK) + (offset << 1);
611} 596}
612 597
613const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv, 598const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
614 size_t offset)
615{ 599{
616 u32 address = eeprom_indirect_address(priv, offset); 600 u32 address = eeprom_indirect_address(priv, offset);
617 BUG_ON(address >= priv->cfg->base_params->eeprom_size); 601 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
@@ -622,367 +606,12 @@ struct iwl_mod_params iwlagn_mod_params = {
622 .amsdu_size_8K = 1, 606 .amsdu_size_8K = 1,
623 .restart_fw = 1, 607 .restart_fw = 1,
624 .plcp_check = true, 608 .plcp_check = true,
609 .bt_coex_active = true,
610 .no_sleep_autoadjust = true,
611 .power_level = IWL_POWER_INDEX_1,
625 /* the rest are 0 by default */ 612 /* the rest are 0 by default */
626}; 613};
627 614
628void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
629{
630 unsigned long flags;
631 int i;
632 spin_lock_irqsave(&rxq->lock, flags);
633 INIT_LIST_HEAD(&rxq->rx_free);
634 INIT_LIST_HEAD(&rxq->rx_used);
635 /* Fill the rx_used queue with _all_ of the Rx buffers */
636 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
637 /* In the reset function, these buffers may have been allocated
638 * to an SKB, so we need to unmap and free potential storage */
639 if (rxq->pool[i].page != NULL) {
640 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
641 PAGE_SIZE << priv->hw_params.rx_page_order,
642 PCI_DMA_FROMDEVICE);
643 __iwl_free_pages(priv, rxq->pool[i].page);
644 rxq->pool[i].page = NULL;
645 }
646 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
647 }
648
649 for (i = 0; i < RX_QUEUE_SIZE; i++)
650 rxq->queue[i] = NULL;
651
652 /* Set us so that we have processed and used all buffers, but have
653 * not restocked the Rx queue with fresh buffers */
654 rxq->read = rxq->write = 0;
655 rxq->write_actual = 0;
656 rxq->free_count = 0;
657 spin_unlock_irqrestore(&rxq->lock, flags);
658}
659
660int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
661{
662 u32 rb_size;
663 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
664 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
665
666 rb_timeout = RX_RB_TIMEOUT;
667
668 if (iwlagn_mod_params.amsdu_size_8K)
669 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
670 else
671 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
672
673 /* Stop Rx DMA */
674 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
675
676 /* Reset driver's Rx queue write index */
677 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
678
679 /* Tell device where to find RBD circular buffer in DRAM */
680 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
681 (u32)(rxq->bd_dma >> 8));
682
683 /* Tell device where in DRAM to update its Rx status */
684 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
685 rxq->rb_stts_dma >> 4);
686
687 /* Enable Rx DMA
688 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
689 * the credit mechanism in 5000 HW RX FIFO
690 * Direct rx interrupts to hosts
691 * Rx buffer size 4 or 8k
692 * RB timeout 0x10
693 * 256 RBDs
694 */
695 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
696 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
697 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
698 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
699 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
700 rb_size|
701 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
702 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
703
704 /* Set interrupt coalescing timer to default (2048 usecs) */
705 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
706
707 return 0;
708}
709
710static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
711{
712/*
713 * (for documentation purposes)
714 * to set power to V_AUX, do:
715
716 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
717 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
718 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
719 ~APMG_PS_CTRL_MSK_PWR_SRC);
720 */
721
722 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
723 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
724 ~APMG_PS_CTRL_MSK_PWR_SRC);
725}
726
727int iwlagn_hw_nic_init(struct iwl_priv *priv)
728{
729 unsigned long flags;
730 struct iwl_rx_queue *rxq = &priv->rxq;
731 int ret;
732
733 /* nic_init */
734 spin_lock_irqsave(&priv->lock, flags);
735 priv->cfg->ops->lib->apm_ops.init(priv);
736
737 /* Set interrupt coalescing calibration timer to default (512 usecs) */
738 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
739
740 spin_unlock_irqrestore(&priv->lock, flags);
741
742 iwlagn_set_pwr_vmain(priv);
743
744 priv->cfg->ops->lib->apm_ops.config(priv);
745
746 /* Allocate the RX queue, or reset if it is already allocated */
747 if (!rxq->bd) {
748 ret = iwl_rx_queue_alloc(priv);
749 if (ret) {
750 IWL_ERR(priv, "Unable to initialize Rx queue\n");
751 return -ENOMEM;
752 }
753 } else
754 iwlagn_rx_queue_reset(priv, rxq);
755
756 iwlagn_rx_replenish(priv);
757
758 iwlagn_rx_init(priv, rxq);
759
760 spin_lock_irqsave(&priv->lock, flags);
761
762 rxq->need_update = 1;
763 iwl_rx_queue_update_write_ptr(priv, rxq);
764
765 spin_unlock_irqrestore(&priv->lock, flags);
766
767 /* Allocate or reset and init all Tx and Command queues */
768 if (!priv->txq) {
769 ret = iwlagn_txq_ctx_alloc(priv);
770 if (ret)
771 return ret;
772 } else
773 iwlagn_txq_ctx_reset(priv);
774
775 if (priv->cfg->base_params->shadow_reg_enable) {
776 /* enable shadow regs in HW */
777 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
778 0x800FFFFF);
779 }
780
781 set_bit(STATUS_INIT, &priv->status);
782
783 return 0;
784}
785
786/**
787 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
788 */
789static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
790 dma_addr_t dma_addr)
791{
792 return cpu_to_le32((u32)(dma_addr >> 8));
793}
794
795/**
796 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
797 *
798 * If there are slots in the RX queue that need to be restocked,
799 * and we have free pre-allocated buffers, fill the ranks as much
800 * as we can, pulling from rx_free.
801 *
802 * This moves the 'write' index forward to catch up with 'processed', and
803 * also updates the memory address in the firmware to reference the new
804 * target buffer.
805 */
806void iwlagn_rx_queue_restock(struct iwl_priv *priv)
807{
808 struct iwl_rx_queue *rxq = &priv->rxq;
809 struct list_head *element;
810 struct iwl_rx_mem_buffer *rxb;
811 unsigned long flags;
812
813 spin_lock_irqsave(&rxq->lock, flags);
814 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
815 /* The overwritten rxb must be a used one */
816 rxb = rxq->queue[rxq->write];
817 BUG_ON(rxb && rxb->page);
818
819 /* Get next free Rx buffer, remove from free list */
820 element = rxq->rx_free.next;
821 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
822 list_del(element);
823
824 /* Point to Rx buffer via next RBD in circular buffer */
825 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
826 rxb->page_dma);
827 rxq->queue[rxq->write] = rxb;
828 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
829 rxq->free_count--;
830 }
831 spin_unlock_irqrestore(&rxq->lock, flags);
832 /* If the pre-allocated buffer pool is dropping low, schedule to
833 * refill it */
834 if (rxq->free_count <= RX_LOW_WATERMARK)
835 queue_work(priv->workqueue, &priv->rx_replenish);
836
837
838 /* If we've added more space for the firmware to place data, tell it.
839 * Increment device's write pointer in multiples of 8. */
840 if (rxq->write_actual != (rxq->write & ~0x7)) {
841 spin_lock_irqsave(&rxq->lock, flags);
842 rxq->need_update = 1;
843 spin_unlock_irqrestore(&rxq->lock, flags);
844 iwl_rx_queue_update_write_ptr(priv, rxq);
845 }
846}
847
848/**
849 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
850 *
851 * When moving to rx_free an SKB is allocated for the slot.
852 *
853 * Also restock the Rx queue via iwl_rx_queue_restock.
854 * This is called as a scheduled work item (except for during initialization)
855 */
856void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
857{
858 struct iwl_rx_queue *rxq = &priv->rxq;
859 struct list_head *element;
860 struct iwl_rx_mem_buffer *rxb;
861 struct page *page;
862 unsigned long flags;
863 gfp_t gfp_mask = priority;
864
865 while (1) {
866 spin_lock_irqsave(&rxq->lock, flags);
867 if (list_empty(&rxq->rx_used)) {
868 spin_unlock_irqrestore(&rxq->lock, flags);
869 return;
870 }
871 spin_unlock_irqrestore(&rxq->lock, flags);
872
873 if (rxq->free_count > RX_LOW_WATERMARK)
874 gfp_mask |= __GFP_NOWARN;
875
876 if (priv->hw_params.rx_page_order > 0)
877 gfp_mask |= __GFP_COMP;
878
879 /* Alloc a new receive buffer */
880 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
881 if (!page) {
882 if (net_ratelimit())
883 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
884 "order: %d\n",
885 priv->hw_params.rx_page_order);
886
887 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
888 net_ratelimit())
889 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
890 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
891 rxq->free_count);
892 /* We don't reschedule replenish work here -- we will
893 * call the restock method and if it still needs
894 * more buffers it will schedule replenish */
895 return;
896 }
897
898 spin_lock_irqsave(&rxq->lock, flags);
899
900 if (list_empty(&rxq->rx_used)) {
901 spin_unlock_irqrestore(&rxq->lock, flags);
902 __free_pages(page, priv->hw_params.rx_page_order);
903 return;
904 }
905 element = rxq->rx_used.next;
906 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
907 list_del(element);
908
909 spin_unlock_irqrestore(&rxq->lock, flags);
910
911 BUG_ON(rxb->page);
912 rxb->page = page;
913 /* Get physical address of the RB */
914 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
915 PAGE_SIZE << priv->hw_params.rx_page_order,
916 PCI_DMA_FROMDEVICE);
917 /* dma address must be no more than 36 bits */
918 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
919 /* and also 256 byte aligned! */
920 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
921
922 spin_lock_irqsave(&rxq->lock, flags);
923
924 list_add_tail(&rxb->list, &rxq->rx_free);
925 rxq->free_count++;
926
927 spin_unlock_irqrestore(&rxq->lock, flags);
928 }
929}
930
931void iwlagn_rx_replenish(struct iwl_priv *priv)
932{
933 unsigned long flags;
934
935 iwlagn_rx_allocate(priv, GFP_KERNEL);
936
937 spin_lock_irqsave(&priv->lock, flags);
938 iwlagn_rx_queue_restock(priv);
939 spin_unlock_irqrestore(&priv->lock, flags);
940}
941
942void iwlagn_rx_replenish_now(struct iwl_priv *priv)
943{
944 iwlagn_rx_allocate(priv, GFP_ATOMIC);
945
946 iwlagn_rx_queue_restock(priv);
947}
948
949/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
950 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
951 * This free routine walks the list of POOL entries and if SKB is set to
952 * non NULL it is unmapped and freed
953 */
954void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
955{
956 int i;
957 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
958 if (rxq->pool[i].page != NULL) {
959 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
960 PAGE_SIZE << priv->hw_params.rx_page_order,
961 PCI_DMA_FROMDEVICE);
962 __iwl_free_pages(priv, rxq->pool[i].page);
963 rxq->pool[i].page = NULL;
964 }
965 }
966
967 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
968 rxq->bd_dma);
969 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
970 rxq->rb_stts, rxq->rb_stts_dma);
971 rxq->bd = NULL;
972 rxq->rb_stts = NULL;
973}
974
975int iwlagn_rxq_stop(struct iwl_priv *priv)
976{
977
978 /* stop Rx DMA */
979 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
980 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
981 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
982
983 return 0;
984}
985
986int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band) 615int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
987{ 616{
988 int idx = 0; 617 int idx = 0;
@@ -1126,7 +755,7 @@ static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1126 755
1127static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen) 756static int iwl_fill_offch_tx(struct iwl_priv *priv, void *data, size_t maxlen)
1128{ 757{
1129 struct sk_buff *skb = priv->_agn.offchan_tx_skb; 758 struct sk_buff *skb = priv->offchan_tx_skb;
1130 759
1131 if (skb->len < maxlen) 760 if (skb->len < maxlen)
1132 maxlen = skb->len; 761 maxlen = skb->len;
@@ -1141,6 +770,7 @@ int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1141 struct iwl_host_cmd cmd = { 770 struct iwl_host_cmd cmd = {
1142 .id = REPLY_SCAN_CMD, 771 .id = REPLY_SCAN_CMD,
1143 .len = { sizeof(struct iwl_scan_cmd), }, 772 .len = { sizeof(struct iwl_scan_cmd), },
773 .flags = CMD_SYNC,
1144 }; 774 };
1145 struct iwl_scan_cmd *scan; 775 struct iwl_scan_cmd *scan;
1146 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; 776 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
@@ -1211,7 +841,7 @@ int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1211 } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) { 841 } else if (priv->scan_type == IWL_SCAN_OFFCH_TX) {
1212 scan->suspend_time = 0; 842 scan->suspend_time = 0;
1213 scan->max_out_time = 843 scan->max_out_time =
1214 cpu_to_le32(1024 * priv->_agn.offchan_tx_timeout); 844 cpu_to_le32(1024 * priv->offchan_tx_timeout);
1215 } 845 }
1216 846
1217 switch (priv->scan_type) { 847 switch (priv->scan_type) {
@@ -1399,9 +1029,9 @@ int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1399 scan_ch = (void *)&scan->data[cmd_len]; 1029 scan_ch = (void *)&scan->data[cmd_len];
1400 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE; 1030 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1401 scan_ch->channel = 1031 scan_ch->channel =
1402 cpu_to_le16(priv->_agn.offchan_tx_chan->hw_value); 1032 cpu_to_le16(priv->offchan_tx_chan->hw_value);
1403 scan_ch->active_dwell = 1033 scan_ch->active_dwell =
1404 cpu_to_le16(priv->_agn.offchan_tx_timeout); 1034 cpu_to_le16(priv->offchan_tx_timeout);
1405 scan_ch->passive_dwell = 0; 1035 scan_ch->passive_dwell = 0;
1406 1036
1407 /* Set txpower levels to defaults */ 1037 /* Set txpower levels to defaults */
@@ -1411,7 +1041,7 @@ int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1411 * power level: 1041 * power level:
1412 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3; 1042 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1413 */ 1043 */
1414 if (priv->_agn.offchan_tx_chan->band == IEEE80211_BAND_5GHZ) 1044 if (priv->offchan_tx_chan->band == IEEE80211_BAND_5GHZ)
1415 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3; 1045 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1416 else 1046 else
1417 scan_ch->tx_gain = ((1 << 5) | (5 << 3)); 1047 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
@@ -1433,17 +1063,14 @@ int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1433 /* set scan bit here for PAN params */ 1063 /* set scan bit here for PAN params */
1434 set_bit(STATUS_SCAN_HW, &priv->status); 1064 set_bit(STATUS_SCAN_HW, &priv->status);
1435 1065
1436 if (priv->cfg->ops->hcmd->set_pan_params) { 1066 ret = iwlagn_set_pan_params(priv);
1437 ret = priv->cfg->ops->hcmd->set_pan_params(priv); 1067 if (ret)
1438 if (ret) 1068 return ret;
1439 return ret;
1440 }
1441 1069
1442 ret = iwl_send_cmd_sync(priv, &cmd); 1070 ret = trans_send_cmd(&priv->trans, &cmd);
1443 if (ret) { 1071 if (ret) {
1444 clear_bit(STATUS_SCAN_HW, &priv->status); 1072 clear_bit(STATUS_SCAN_HW, &priv->status);
1445 if (priv->cfg->ops->hcmd->set_pan_params) 1073 iwlagn_set_pan_params(priv);
1446 priv->cfg->ops->hcmd->set_pan_params(priv);
1447 } 1074 }
1448 1075
1449 return ret; 1076 return ret;
@@ -1528,23 +1155,32 @@ int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1528 might_sleep(); 1155 might_sleep();
1529 1156
1530 memset(&flush_cmd, 0, sizeof(flush_cmd)); 1157 memset(&flush_cmd, 0, sizeof(flush_cmd));
1531 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK | 1158 if (flush_control & BIT(IWL_RXON_CTX_BSS))
1532 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK; 1159 flush_cmd.fifo_control = IWL_SCD_VO_MSK | IWL_SCD_VI_MSK |
1533 if (priv->cfg->sku & IWL_SKU_N) 1160 IWL_SCD_BE_MSK | IWL_SCD_BK_MSK |
1161 IWL_SCD_MGMT_MSK;
1162 if ((flush_control & BIT(IWL_RXON_CTX_PAN)) &&
1163 (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)))
1164 flush_cmd.fifo_control |= IWL_PAN_SCD_VO_MSK |
1165 IWL_PAN_SCD_VI_MSK | IWL_PAN_SCD_BE_MSK |
1166 IWL_PAN_SCD_BK_MSK | IWL_PAN_SCD_MGMT_MSK |
1167 IWL_PAN_SCD_MULTICAST_MSK;
1168
1169 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
1534 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK; 1170 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1535 1171
1536 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n", 1172 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1537 flush_cmd.fifo_control); 1173 flush_cmd.fifo_control);
1538 flush_cmd.flush_control = cpu_to_le16(flush_control); 1174 flush_cmd.flush_control = cpu_to_le16(flush_control);
1539 1175
1540 return iwl_send_cmd(priv, &cmd); 1176 return trans_send_cmd(&priv->trans, &cmd);
1541} 1177}
1542 1178
1543void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control) 1179void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1544{ 1180{
1545 mutex_lock(&priv->mutex); 1181 mutex_lock(&priv->mutex);
1546 ieee80211_stop_queues(priv->hw); 1182 ieee80211_stop_queues(priv->hw);
1547 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) { 1183 if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
1548 IWL_ERR(priv, "flush request fail\n"); 1184 IWL_ERR(priv, "flush request fail\n");
1549 goto done; 1185 goto done;
1550 } 1186 }
@@ -1699,18 +1335,21 @@ void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1699 * (might be in monitor mode), or the interface is in 1335 * (might be in monitor mode), or the interface is in
1700 * IBSS mode (no proper uCode support for coex then). 1336 * IBSS mode (no proper uCode support for coex then).
1701 */ 1337 */
1702 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) { 1338 if (!iwlagn_mod_params.bt_coex_active ||
1339 priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1703 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED; 1340 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1704 } else { 1341 } else {
1705 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W << 1342 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1706 IWLAGN_BT_FLAG_COEX_MODE_SHIFT; 1343 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1707 if (priv->cfg->bt_params && 1344
1708 priv->cfg->bt_params->bt_sco_disable) 1345 if (!priv->bt_enable_pspoll)
1709 basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE; 1346 basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1347 else
1348 basic.flags &= ~IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1710 1349
1711 if (priv->bt_ch_announce) 1350 if (priv->bt_ch_announce)
1712 basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION; 1351 basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1713 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", basic.flags); 1352 IWL_DEBUG_COEX(priv, "BT coex flag: 0X%x\n", basic.flags);
1714 } 1353 }
1715 priv->bt_enable_flag = basic.flags; 1354 priv->bt_enable_flag = basic.flags;
1716 if (priv->bt_full_concurrent) 1355 if (priv->bt_full_concurrent)
@@ -1720,7 +1359,7 @@ void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1720 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup, 1359 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1721 sizeof(iwlagn_def_3w_lookup)); 1360 sizeof(iwlagn_def_3w_lookup));
1722 1361
1723 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n", 1362 IWL_DEBUG_COEX(priv, "BT coex %s in %s mode\n",
1724 basic.flags ? "active" : "disabled", 1363 basic.flags ? "active" : "disabled",
1725 priv->bt_full_concurrent ? 1364 priv->bt_full_concurrent ?
1726 "full concurrency" : "3-wire"); 1365 "full concurrency" : "3-wire");
@@ -1728,19 +1367,97 @@ void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1728 if (priv->cfg->bt_params->bt_session_2) { 1367 if (priv->cfg->bt_params->bt_session_2) {
1729 memcpy(&bt_cmd_2000.basic, &basic, 1368 memcpy(&bt_cmd_2000.basic, &basic,
1730 sizeof(basic)); 1369 sizeof(basic));
1731 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, 1370 ret = trans_send_cmd_pdu(&priv->trans, REPLY_BT_CONFIG,
1732 sizeof(bt_cmd_2000), &bt_cmd_2000); 1371 CMD_SYNC, sizeof(bt_cmd_2000), &bt_cmd_2000);
1733 } else { 1372 } else {
1734 memcpy(&bt_cmd_6000.basic, &basic, 1373 memcpy(&bt_cmd_6000.basic, &basic,
1735 sizeof(basic)); 1374 sizeof(basic));
1736 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, 1375 ret = trans_send_cmd_pdu(&priv->trans, REPLY_BT_CONFIG,
1737 sizeof(bt_cmd_6000), &bt_cmd_6000); 1376 CMD_SYNC, sizeof(bt_cmd_6000), &bt_cmd_6000);
1738 } 1377 }
1739 if (ret) 1378 if (ret)
1740 IWL_ERR(priv, "failed to send BT Coex Config\n"); 1379 IWL_ERR(priv, "failed to send BT Coex Config\n");
1741 1380
1742} 1381}
1743 1382
1383void iwlagn_bt_adjust_rssi_monitor(struct iwl_priv *priv, bool rssi_ena)
1384{
1385 struct iwl_rxon_context *ctx, *found_ctx = NULL;
1386 bool found_ap = false;
1387
1388 lockdep_assert_held(&priv->mutex);
1389
1390 /* Check whether AP or GO mode is active. */
1391 if (rssi_ena) {
1392 for_each_context(priv, ctx) {
1393 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_AP &&
1394 iwl_is_associated_ctx(ctx)) {
1395 found_ap = true;
1396 break;
1397 }
1398 }
1399 }
1400
1401 /*
1402 * If disable was received or If GO/AP mode, disable RSSI
1403 * measurements.
1404 */
1405 if (!rssi_ena || found_ap) {
1406 if (priv->cur_rssi_ctx) {
1407 ctx = priv->cur_rssi_ctx;
1408 ieee80211_disable_rssi_reports(ctx->vif);
1409 priv->cur_rssi_ctx = NULL;
1410 }
1411 return;
1412 }
1413
1414 /*
1415 * If rssi measurements need to be enabled, consider all cases now.
1416 * Figure out how many contexts are active.
1417 */
1418 for_each_context(priv, ctx) {
1419 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION &&
1420 iwl_is_associated_ctx(ctx)) {
1421 found_ctx = ctx;
1422 break;
1423 }
1424 }
1425
1426 /*
1427 * rssi monitor already enabled for the correct interface...nothing
1428 * to do.
1429 */
1430 if (found_ctx == priv->cur_rssi_ctx)
1431 return;
1432
1433 /*
1434 * Figure out if rssi monitor is currently enabled, and needs
1435 * to be changed. If rssi monitor is already enabled, disable
1436 * it first else just enable rssi measurements on the
1437 * interface found above.
1438 */
1439 if (priv->cur_rssi_ctx) {
1440 ctx = priv->cur_rssi_ctx;
1441 if (ctx->vif)
1442 ieee80211_disable_rssi_reports(ctx->vif);
1443 }
1444
1445 priv->cur_rssi_ctx = found_ctx;
1446
1447 if (!found_ctx)
1448 return;
1449
1450 ieee80211_enable_rssi_reports(found_ctx->vif,
1451 IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD,
1452 IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD);
1453}
1454
1455static bool iwlagn_bt_traffic_is_sco(struct iwl_bt_uart_msg *uart_msg)
1456{
1457 return BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3 >>
1458 BT_UART_MSG_FRAME3SCOESCO_POS;
1459}
1460
1744static void iwlagn_bt_traffic_change_work(struct work_struct *work) 1461static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1745{ 1462{
1746 struct iwl_priv *priv = 1463 struct iwl_priv *priv =
@@ -1758,7 +1475,7 @@ static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1758 * coex profile notifications. Ignore that since only bad consequence 1475 * coex profile notifications. Ignore that since only bad consequence
1759 * can be not matching debug print with actual state. 1476 * can be not matching debug print with actual state.
1760 */ 1477 */
1761 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n", 1478 IWL_DEBUG_COEX(priv, "BT traffic load changes: %d\n",
1762 priv->bt_traffic_load); 1479 priv->bt_traffic_load);
1763 1480
1764 switch (priv->bt_traffic_load) { 1481 switch (priv->bt_traffic_load) {
@@ -1793,23 +1510,43 @@ static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1793 if (test_bit(STATUS_SCAN_HW, &priv->status)) 1510 if (test_bit(STATUS_SCAN_HW, &priv->status))
1794 goto out; 1511 goto out;
1795 1512
1796 if (priv->cfg->ops->lib->update_chain_flags) 1513 iwl_update_chain_flags(priv);
1797 priv->cfg->ops->lib->update_chain_flags(priv);
1798 1514
1799 if (smps_request != -1) { 1515 if (smps_request != -1) {
1516 priv->current_ht_config.smps = smps_request;
1800 for_each_context(priv, ctx) { 1517 for_each_context(priv, ctx) {
1801 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION) 1518 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1802 ieee80211_request_smps(ctx->vif, smps_request); 1519 ieee80211_request_smps(ctx->vif, smps_request);
1803 } 1520 }
1804 } 1521 }
1522
1523 /*
1524 * Dynamic PS poll related functionality. Adjust RSSI measurements if
1525 * necessary.
1526 */
1527 iwlagn_bt_coex_rssi_monitor(priv);
1805out: 1528out:
1806 mutex_unlock(&priv->mutex); 1529 mutex_unlock(&priv->mutex);
1807} 1530}
1808 1531
1532/*
1533 * If BT sco traffic, and RSSI monitor is enabled, move measurements to the
1534 * correct interface or disable it if this is the last interface to be
1535 * removed.
1536 */
1537void iwlagn_bt_coex_rssi_monitor(struct iwl_priv *priv)
1538{
1539 if (priv->bt_is_sco &&
1540 priv->bt_traffic_load == IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS)
1541 iwlagn_bt_adjust_rssi_monitor(priv, true);
1542 else
1543 iwlagn_bt_adjust_rssi_monitor(priv, false);
1544}
1545
1809static void iwlagn_print_uartmsg(struct iwl_priv *priv, 1546static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1810 struct iwl_bt_uart_msg *uart_msg) 1547 struct iwl_bt_uart_msg *uart_msg)
1811{ 1548{
1812 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, " 1549 IWL_DEBUG_COEX(priv, "Message Type = 0x%X, SSN = 0x%X, "
1813 "Update Req = 0x%X", 1550 "Update Req = 0x%X",
1814 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >> 1551 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1815 BT_UART_MSG_FRAME1MSGTYPE_POS, 1552 BT_UART_MSG_FRAME1MSGTYPE_POS,
@@ -1818,7 +1555,7 @@ static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1818 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >> 1555 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1819 BT_UART_MSG_FRAME1UPDATEREQ_POS); 1556 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1820 1557
1821 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, " 1558 IWL_DEBUG_COEX(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1822 "Chl_SeqN = 0x%X, In band = 0x%X", 1559 "Chl_SeqN = 0x%X, In band = 0x%X",
1823 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >> 1560 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1824 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS, 1561 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
@@ -1829,7 +1566,7 @@ static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1829 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >> 1566 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1830 BT_UART_MSG_FRAME2INBAND_POS); 1567 BT_UART_MSG_FRAME2INBAND_POS);
1831 1568
1832 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, " 1569 IWL_DEBUG_COEX(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1833 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X", 1570 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1834 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >> 1571 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1835 BT_UART_MSG_FRAME3SCOESCO_POS, 1572 BT_UART_MSG_FRAME3SCOESCO_POS,
@@ -1844,11 +1581,11 @@ static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1844 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >> 1581 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1845 BT_UART_MSG_FRAME3OBEX_POS); 1582 BT_UART_MSG_FRAME3OBEX_POS);
1846 1583
1847 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X", 1584 IWL_DEBUG_COEX(priv, "Idle duration = 0x%X",
1848 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >> 1585 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1849 BT_UART_MSG_FRAME4IDLEDURATION_POS); 1586 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1850 1587
1851 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, " 1588 IWL_DEBUG_COEX(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1852 "eSCO Retransmissions = 0x%X", 1589 "eSCO Retransmissions = 0x%X",
1853 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >> 1590 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1854 BT_UART_MSG_FRAME5TXACTIVITY_POS, 1591 BT_UART_MSG_FRAME5TXACTIVITY_POS,
@@ -1857,13 +1594,13 @@ static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1857 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >> 1594 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1858 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS); 1595 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1859 1596
1860 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X", 1597 IWL_DEBUG_COEX(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1861 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >> 1598 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1862 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS, 1599 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1863 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >> 1600 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1864 BT_UART_MSG_FRAME6DISCOVERABLE_POS); 1601 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1865 1602
1866 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Page = " 1603 IWL_DEBUG_COEX(priv, "Sniff Activity = 0x%X, Page = "
1867 "0x%X, Inquiry = 0x%X, Connectable = 0x%X", 1604 "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1868 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >> 1605 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1869 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS, 1606 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
@@ -1913,14 +1650,16 @@ void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1913 return; 1650 return;
1914 } 1651 }
1915 1652
1916 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n"); 1653 IWL_DEBUG_COEX(priv, "BT Coex notification:\n");
1917 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status); 1654 IWL_DEBUG_COEX(priv, " status: %d\n", coex->bt_status);
1918 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load); 1655 IWL_DEBUG_COEX(priv, " traffic load: %d\n", coex->bt_traffic_load);
1919 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n", 1656 IWL_DEBUG_COEX(priv, " CI compliance: %d\n",
1920 coex->bt_ci_compliance); 1657 coex->bt_ci_compliance);
1921 iwlagn_print_uartmsg(priv, uart_msg); 1658 iwlagn_print_uartmsg(priv, uart_msg);
1922 1659
1923 priv->last_bt_traffic_load = priv->bt_traffic_load; 1660 priv->last_bt_traffic_load = priv->bt_traffic_load;
1661 priv->bt_is_sco = iwlagn_bt_traffic_is_sco(uart_msg);
1662
1924 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) { 1663 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1925 if (priv->bt_status != coex->bt_status || 1664 if (priv->bt_status != coex->bt_status ||
1926 priv->last_bt_traffic_load != coex->bt_traffic_load) { 1665 priv->last_bt_traffic_load != coex->bt_traffic_load) {
@@ -1954,15 +1693,12 @@ void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1954 1693
1955void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv) 1694void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1956{ 1695{
1957 iwlagn_rx_handler_setup(priv);
1958 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] = 1696 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1959 iwlagn_bt_coex_profile_notif; 1697 iwlagn_bt_coex_profile_notif;
1960} 1698}
1961 1699
1962void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv) 1700void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1963{ 1701{
1964 iwlagn_setup_deferred_work(priv);
1965
1966 INIT_WORK(&priv->bt_traffic_change_work, 1702 INIT_WORK(&priv->bt_traffic_change_work,
1967 iwlagn_bt_traffic_change_work); 1703 iwlagn_bt_traffic_change_work);
1968} 1704}
@@ -2274,9 +2010,9 @@ void iwlagn_init_notification_wait(struct iwl_priv *priv,
2274 wait_entry->triggered = false; 2010 wait_entry->triggered = false;
2275 wait_entry->aborted = false; 2011 wait_entry->aborted = false;
2276 2012
2277 spin_lock_bh(&priv->_agn.notif_wait_lock); 2013 spin_lock_bh(&priv->notif_wait_lock);
2278 list_add(&wait_entry->list, &priv->_agn.notif_waits); 2014 list_add(&wait_entry->list, &priv->notif_waits);
2279 spin_unlock_bh(&priv->_agn.notif_wait_lock); 2015 spin_unlock_bh(&priv->notif_wait_lock);
2280} 2016}
2281 2017
2282int iwlagn_wait_notification(struct iwl_priv *priv, 2018int iwlagn_wait_notification(struct iwl_priv *priv,
@@ -2285,13 +2021,13 @@ int iwlagn_wait_notification(struct iwl_priv *priv,
2285{ 2021{
2286 int ret; 2022 int ret;
2287 2023
2288 ret = wait_event_timeout(priv->_agn.notif_waitq, 2024 ret = wait_event_timeout(priv->notif_waitq,
2289 wait_entry->triggered || wait_entry->aborted, 2025 wait_entry->triggered || wait_entry->aborted,
2290 timeout); 2026 timeout);
2291 2027
2292 spin_lock_bh(&priv->_agn.notif_wait_lock); 2028 spin_lock_bh(&priv->notif_wait_lock);
2293 list_del(&wait_entry->list); 2029 list_del(&wait_entry->list);
2294 spin_unlock_bh(&priv->_agn.notif_wait_lock); 2030 spin_unlock_bh(&priv->notif_wait_lock);
2295 2031
2296 if (wait_entry->aborted) 2032 if (wait_entry->aborted)
2297 return -EIO; 2033 return -EIO;
@@ -2305,91 +2041,7 @@ int iwlagn_wait_notification(struct iwl_priv *priv,
2305void iwlagn_remove_notification(struct iwl_priv *priv, 2041void iwlagn_remove_notification(struct iwl_priv *priv,
2306 struct iwl_notification_wait *wait_entry) 2042 struct iwl_notification_wait *wait_entry)
2307{ 2043{
2308 spin_lock_bh(&priv->_agn.notif_wait_lock); 2044 spin_lock_bh(&priv->notif_wait_lock);
2309 list_del(&wait_entry->list); 2045 list_del(&wait_entry->list);
2310 spin_unlock_bh(&priv->_agn.notif_wait_lock); 2046 spin_unlock_bh(&priv->notif_wait_lock);
2311}
2312
2313int iwlagn_start_device(struct iwl_priv *priv)
2314{
2315 int ret;
2316
2317 if (iwl_prepare_card_hw(priv)) {
2318 IWL_WARN(priv, "Exit HW not ready\n");
2319 return -EIO;
2320 }
2321
2322 /* If platform's RF_KILL switch is NOT set to KILL */
2323 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2324 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2325 else
2326 set_bit(STATUS_RF_KILL_HW, &priv->status);
2327
2328 if (iwl_is_rfkill(priv)) {
2329 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2330 iwl_enable_interrupts(priv);
2331 return -ERFKILL;
2332 }
2333
2334 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2335
2336 ret = iwlagn_hw_nic_init(priv);
2337 if (ret) {
2338 IWL_ERR(priv, "Unable to init nic\n");
2339 return ret;
2340 }
2341
2342 /* make sure rfkill handshake bits are cleared */
2343 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2344 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2345 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2346
2347 /* clear (again), then enable host interrupts */
2348 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2349 iwl_enable_interrupts(priv);
2350
2351 /* really make sure rfkill handshake bits are cleared */
2352 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2353 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2354
2355 return 0;
2356}
2357
2358void iwlagn_stop_device(struct iwl_priv *priv)
2359{
2360 unsigned long flags;
2361
2362 /* stop and reset the on-board processor */
2363 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2364
2365 /* tell the device to stop sending interrupts */
2366 spin_lock_irqsave(&priv->lock, flags);
2367 iwl_disable_interrupts(priv);
2368 spin_unlock_irqrestore(&priv->lock, flags);
2369 iwl_synchronize_irq(priv);
2370
2371 /* device going down, Stop using ICT table */
2372 iwl_disable_ict(priv);
2373
2374 /*
2375 * If a HW restart happens during firmware loading,
2376 * then the firmware loading might call this function
2377 * and later it might be called again due to the
2378 * restart. So don't process again if the device is
2379 * already dead.
2380 */
2381 if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
2382 iwlagn_txq_ctx_stop(priv);
2383 iwlagn_rxq_stop(priv);
2384
2385 /* Power-down device's busmaster DMA clocks */
2386 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2387 udelay(5);
2388 }
2389
2390 /* Make sure (redundant) we've released our request to stay awake */
2391 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2392
2393 /* Stop the device, and put it in low power state */
2394 iwl_apm_stop(priv);
2395} 2047}
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rs.c b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
index 592b0cfcf717..3789ff4bf53b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
@@ -336,6 +336,12 @@ static u8 rs_tl_add_packet(struct iwl_lq_sta *lq_data,
336} 336}
337 337
338#ifdef CONFIG_MAC80211_DEBUGFS 338#ifdef CONFIG_MAC80211_DEBUGFS
339/**
340 * Program the device to use fixed rate for frame transmit
341 * This is for debugging/testing only
342 * once the device start use fixed rate, we need to reload the module
343 * to being back the normal operation.
344 */
339static void rs_program_fix_rate(struct iwl_priv *priv, 345static void rs_program_fix_rate(struct iwl_priv *priv,
340 struct iwl_lq_sta *lq_sta) 346 struct iwl_lq_sta *lq_sta)
341{ 347{
@@ -348,13 +354,17 @@ static void rs_program_fix_rate(struct iwl_priv *priv,
348 lq_sta->active_mimo2_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */ 354 lq_sta->active_mimo2_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */
349 lq_sta->active_mimo3_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */ 355 lq_sta->active_mimo3_rate = 0x1FD0; /* 6 - 60 MBits, no 9, no CCK */
350 356
351 lq_sta->dbg_fixed_rate = priv->dbg_fixed_rate; 357#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
358 /* testmode has higher priority to overwirte the fixed rate */
359 if (priv->tm_fixed_rate)
360 lq_sta->dbg_fixed_rate = priv->tm_fixed_rate;
361#endif
352 362
353 IWL_DEBUG_RATE(priv, "sta_id %d rate 0x%X\n", 363 IWL_DEBUG_RATE(priv, "sta_id %d rate 0x%X\n",
354 lq_sta->lq.sta_id, priv->dbg_fixed_rate); 364 lq_sta->lq.sta_id, lq_sta->dbg_fixed_rate);
355 365
356 if (priv->dbg_fixed_rate) { 366 if (lq_sta->dbg_fixed_rate) {
357 rs_fill_link_cmd(NULL, lq_sta, priv->dbg_fixed_rate); 367 rs_fill_link_cmd(NULL, lq_sta, lq_sta->dbg_fixed_rate);
358 iwl_send_lq_cmd(lq_sta->drv, ctx, &lq_sta->lq, CMD_ASYNC, 368 iwl_send_lq_cmd(lq_sta->drv, ctx, &lq_sta->lq, CMD_ASYNC,
359 false); 369 false);
360 } 370 }
@@ -426,7 +436,7 @@ static int rs_tl_turn_on_agg_for_tid(struct iwl_priv *priv,
426 ieee80211_stop_tx_ba_session(sta, tid); 436 ieee80211_stop_tx_ba_session(sta, tid);
427 } 437 }
428 } else { 438 } else {
429 IWL_ERR(priv, "Aggregation not enabled for tid %d " 439 IWL_DEBUG_HT(priv, "Aggregation not enabled for tid %d "
430 "because load = %u\n", tid, load); 440 "because load = %u\n", tid, load);
431 } 441 }
432 return ret; 442 return ret;
@@ -1072,8 +1082,10 @@ done:
1072 /* See if there's a better rate or modulation mode to try. */ 1082 /* See if there's a better rate or modulation mode to try. */
1073 if (sta && sta->supp_rates[sband->band]) 1083 if (sta && sta->supp_rates[sband->band])
1074 rs_rate_scale_perform(priv, skb, sta, lq_sta); 1084 rs_rate_scale_perform(priv, skb, sta, lq_sta);
1075#ifdef CONFIG_MAC80211_DEBUGFS 1085
1076 if (priv->dbg_fixed_rate != lq_sta->dbg_fixed_rate) 1086#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_IWLWIFI_DEVICE_SVTOOL)
1087 if ((priv->tm_fixed_rate) &&
1088 (priv->tm_fixed_rate != lq_sta->dbg_fixed_rate))
1077 rs_program_fix_rate(priv, lq_sta); 1089 rs_program_fix_rate(priv, lq_sta);
1078#endif 1090#endif
1079 if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist) 1091 if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist)
@@ -2895,8 +2907,9 @@ void iwl_rs_rate_init(struct iwl_priv *priv, struct ieee80211_sta *sta, u8 sta_i
2895 if (sband->band == IEEE80211_BAND_5GHZ) 2907 if (sband->band == IEEE80211_BAND_5GHZ)
2896 lq_sta->last_txrate_idx += IWL_FIRST_OFDM_RATE; 2908 lq_sta->last_txrate_idx += IWL_FIRST_OFDM_RATE;
2897 lq_sta->is_agg = 0; 2909 lq_sta->is_agg = 0;
2898 2910#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
2899 priv->dbg_fixed_rate = 0; 2911 priv->tm_fixed_rate = 0;
2912#endif
2900#ifdef CONFIG_MAC80211_DEBUGFS 2913#ifdef CONFIG_MAC80211_DEBUGFS
2901 lq_sta->dbg_fixed_rate = 0; 2914 lq_sta->dbg_fixed_rate = 0;
2902#endif 2915#endif
@@ -3095,7 +3108,6 @@ static void rs_dbgfs_set_mcs(struct iwl_lq_sta *lq_sta,
3095 IWL_DEBUG_RATE(priv, "Fixed rate ON\n"); 3108 IWL_DEBUG_RATE(priv, "Fixed rate ON\n");
3096 } else { 3109 } else {
3097 lq_sta->dbg_fixed_rate = 0; 3110 lq_sta->dbg_fixed_rate = 0;
3098 priv->dbg_fixed_rate = 0;
3099 IWL_ERR(priv, 3111 IWL_ERR(priv,
3100 "Invalid antenna selection 0x%X, Valid is 0x%X\n", 3112 "Invalid antenna selection 0x%X, Valid is 0x%X\n",
3101 ant_sel_tx, valid_tx_ant); 3113 ant_sel_tx, valid_tx_ant);
@@ -3123,9 +3135,9 @@ static ssize_t rs_sta_dbgfs_scale_table_write(struct file *file,
3123 return -EFAULT; 3135 return -EFAULT;
3124 3136
3125 if (sscanf(buf, "%x", &parsed_rate) == 1) 3137 if (sscanf(buf, "%x", &parsed_rate) == 1)
3126 priv->dbg_fixed_rate = lq_sta->dbg_fixed_rate = parsed_rate; 3138 lq_sta->dbg_fixed_rate = parsed_rate;
3127 else 3139 else
3128 priv->dbg_fixed_rate = lq_sta->dbg_fixed_rate = 0; 3140 lq_sta->dbg_fixed_rate = 0;
3129 3141
3130 rs_program_fix_rate(priv, lq_sta); 3142 rs_program_fix_rate(priv, lq_sta);
3131 3143
@@ -3155,7 +3167,7 @@ static ssize_t rs_sta_dbgfs_scale_table_read(struct file *file,
3155 lq_sta->total_failed, lq_sta->total_success, 3167 lq_sta->total_failed, lq_sta->total_success,
3156 lq_sta->active_legacy_rate); 3168 lq_sta->active_legacy_rate);
3157 desc += sprintf(buff+desc, "fixed rate 0x%X\n", 3169 desc += sprintf(buff+desc, "fixed rate 0x%X\n",
3158 priv->dbg_fixed_rate); 3170 lq_sta->dbg_fixed_rate);
3159 desc += sprintf(buff+desc, "valid_tx_ant %s%s%s\n", 3171 desc += sprintf(buff+desc, "valid_tx_ant %s%s%s\n",
3160 (priv->hw_params.valid_tx_ant & ANT_A) ? "ANT_A," : "", 3172 (priv->hw_params.valid_tx_ant & ANT_A) ? "ANT_A," : "",
3161 (priv->hw_params.valid_tx_ant & ANT_B) ? "ANT_B," : "", 3173 (priv->hw_params.valid_tx_ant & ANT_B) ? "ANT_B," : "",
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c b/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
index 09f679d6046f..d42ef1763a71 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
@@ -30,6 +30,7 @@
30#include "iwl-core.h" 30#include "iwl-core.h"
31#include "iwl-agn-calib.h" 31#include "iwl-agn-calib.h"
32#include "iwl-helpers.h" 32#include "iwl-helpers.h"
33#include "iwl-trans.h"
33 34
34static int iwlagn_disable_bss(struct iwl_priv *priv, 35static int iwlagn_disable_bss(struct iwl_priv *priv,
35 struct iwl_rxon_context *ctx, 36 struct iwl_rxon_context *ctx,
@@ -39,7 +40,8 @@ static int iwlagn_disable_bss(struct iwl_priv *priv,
39 int ret; 40 int ret;
40 41
41 send->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 42 send->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
42 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd, sizeof(*send), send); 43 ret = trans_send_cmd_pdu(&priv->trans, ctx->rxon_cmd,
44 CMD_SYNC, sizeof(*send), send);
43 45
44 send->filter_flags = old_filter; 46 send->filter_flags = old_filter;
45 47
@@ -64,7 +66,8 @@ static int iwlagn_disable_pan(struct iwl_priv *priv,
64 66
65 send->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 67 send->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
66 send->dev_type = RXON_DEV_TYPE_P2P; 68 send->dev_type = RXON_DEV_TYPE_P2P;
67 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd, sizeof(*send), send); 69 ret = trans_send_cmd_pdu(&priv->trans, ctx->rxon_cmd,
70 CMD_SYNC, sizeof(*send), send);
68 71
69 send->filter_flags = old_filter; 72 send->filter_flags = old_filter;
70 send->dev_type = old_dev_type; 73 send->dev_type = old_dev_type;
@@ -81,6 +84,22 @@ static int iwlagn_disable_pan(struct iwl_priv *priv,
81 return ret; 84 return ret;
82} 85}
83 86
87static int iwlagn_disconn_pan(struct iwl_priv *priv,
88 struct iwl_rxon_context *ctx,
89 struct iwl_rxon_cmd *send)
90{
91 __le32 old_filter = send->filter_flags;
92 int ret;
93
94 send->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
95 ret = trans_send_cmd_pdu(&priv->trans, ctx->rxon_cmd, CMD_SYNC,
96 sizeof(*send), send);
97
98 send->filter_flags = old_filter;
99
100 return ret;
101}
102
84static void iwlagn_update_qos(struct iwl_priv *priv, 103static void iwlagn_update_qos(struct iwl_priv *priv,
85 struct iwl_rxon_context *ctx) 104 struct iwl_rxon_context *ctx)
86{ 105{
@@ -102,7 +121,7 @@ static void iwlagn_update_qos(struct iwl_priv *priv,
102 ctx->qos_data.qos_active, 121 ctx->qos_data.qos_active,
103 ctx->qos_data.def_qos_parm.qos_flags); 122 ctx->qos_data.def_qos_parm.qos_flags);
104 123
105 ret = iwl_send_cmd_pdu(priv, ctx->qos_cmd, 124 ret = trans_send_cmd_pdu(&priv->trans, ctx->qos_cmd, CMD_SYNC,
106 sizeof(struct iwl_qosparam_cmd), 125 sizeof(struct iwl_qosparam_cmd),
107 &ctx->qos_data.def_qos_parm); 126 &ctx->qos_data.def_qos_parm);
108 if (ret) 127 if (ret)
@@ -161,11 +180,8 @@ static int iwlagn_send_rxon_assoc(struct iwl_priv *priv,
161 ctx->staging.ofdm_ht_triple_stream_basic_rates; 180 ctx->staging.ofdm_ht_triple_stream_basic_rates;
162 rxon_assoc.acquisition_data = ctx->staging.acquisition_data; 181 rxon_assoc.acquisition_data = ctx->staging.acquisition_data;
163 182
164 ret = iwl_send_cmd_pdu_async(priv, ctx->rxon_assoc_cmd, 183 ret = trans_send_cmd_pdu(&priv->trans, ctx->rxon_assoc_cmd,
165 sizeof(rxon_assoc), &rxon_assoc, NULL); 184 CMD_ASYNC, sizeof(rxon_assoc), &rxon_assoc);
166 if (ret)
167 return ret;
168
169 return ret; 185 return ret;
170} 186}
171 187
@@ -175,10 +191,21 @@ static int iwlagn_rxon_disconn(struct iwl_priv *priv,
175 int ret; 191 int ret;
176 struct iwl_rxon_cmd *active = (void *)&ctx->active; 192 struct iwl_rxon_cmd *active = (void *)&ctx->active;
177 193
178 if (ctx->ctxid == IWL_RXON_CTX_BSS) 194 if (ctx->ctxid == IWL_RXON_CTX_BSS) {
179 ret = iwlagn_disable_bss(priv, ctx, &ctx->staging); 195 ret = iwlagn_disable_bss(priv, ctx, &ctx->staging);
180 else 196 } else {
181 ret = iwlagn_disable_pan(priv, ctx, &ctx->staging); 197 ret = iwlagn_disable_pan(priv, ctx, &ctx->staging);
198 if (ret)
199 return ret;
200 if (ctx->vif) {
201 ret = iwl_send_rxon_timing(priv, ctx);
202 if (ret) {
203 IWL_ERR(priv, "Failed to send timing (%d)!\n", ret);
204 return ret;
205 }
206 ret = iwlagn_disconn_pan(priv, ctx, &ctx->staging);
207 }
208 }
182 if (ret) 209 if (ret)
183 return ret; 210 return ret;
184 211
@@ -187,6 +214,8 @@ static int iwlagn_rxon_disconn(struct iwl_priv *priv,
187 * keys, so we have to restore those afterwards. 214 * keys, so we have to restore those afterwards.
188 */ 215 */
189 iwl_clear_ucode_stations(priv, ctx); 216 iwl_clear_ucode_stations(priv, ctx);
217 /* update -- might need P2P now */
218 iwl_update_bcast_station(priv, ctx);
190 iwl_restore_stations(priv, ctx); 219 iwl_restore_stations(priv, ctx);
191 ret = iwl_restore_default_wep_keys(priv, ctx); 220 ret = iwl_restore_default_wep_keys(priv, ctx);
192 if (ret) { 221 if (ret) {
@@ -205,10 +234,12 @@ static int iwlagn_rxon_connect(struct iwl_priv *priv,
205 struct iwl_rxon_cmd *active = (void *)&ctx->active; 234 struct iwl_rxon_cmd *active = (void *)&ctx->active;
206 235
207 /* RXON timing must be before associated RXON */ 236 /* RXON timing must be before associated RXON */
208 ret = iwl_send_rxon_timing(priv, ctx); 237 if (ctx->ctxid == IWL_RXON_CTX_BSS) {
209 if (ret) { 238 ret = iwl_send_rxon_timing(priv, ctx);
210 IWL_ERR(priv, "Failed to send timing (%d)!\n", ret); 239 if (ret) {
211 return ret; 240 IWL_ERR(priv, "Failed to send timing (%d)!\n", ret);
241 return ret;
242 }
212 } 243 }
213 /* QoS info may be cleared by previous un-assoc RXON */ 244 /* QoS info may be cleared by previous un-assoc RXON */
214 iwlagn_update_qos(priv, ctx); 245 iwlagn_update_qos(priv, ctx);
@@ -235,7 +266,7 @@ static int iwlagn_rxon_connect(struct iwl_priv *priv,
235 * Associated RXON doesn't clear the station table in uCode, 266 * Associated RXON doesn't clear the station table in uCode,
236 * so we don't need to restore stations etc. after this. 267 * so we don't need to restore stations etc. after this.
237 */ 268 */
238 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd, 269 ret = trans_send_cmd_pdu(&priv->trans, ctx->rxon_cmd, CMD_SYNC,
239 sizeof(struct iwl_rxon_cmd), &ctx->staging); 270 sizeof(struct iwl_rxon_cmd), &ctx->staging);
240 if (ret) { 271 if (ret) {
241 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); 272 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
@@ -263,9 +294,107 @@ static int iwlagn_rxon_connect(struct iwl_priv *priv,
263 IWL_ERR(priv, "Error sending TX power (%d)\n", ret); 294 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
264 return ret; 295 return ret;
265 } 296 }
297
298 if ((ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION) &&
299 priv->cfg->ht_params->smps_mode)
300 ieee80211_request_smps(ctx->vif,
301 priv->cfg->ht_params->smps_mode);
302
266 return 0; 303 return 0;
267} 304}
268 305
306int iwlagn_set_pan_params(struct iwl_priv *priv)
307{
308 struct iwl_wipan_params_cmd cmd;
309 struct iwl_rxon_context *ctx_bss, *ctx_pan;
310 int slot0 = 300, slot1 = 0;
311 int ret;
312
313 if (priv->valid_contexts == BIT(IWL_RXON_CTX_BSS))
314 return 0;
315
316 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
317
318 lockdep_assert_held(&priv->mutex);
319
320 ctx_bss = &priv->contexts[IWL_RXON_CTX_BSS];
321 ctx_pan = &priv->contexts[IWL_RXON_CTX_PAN];
322
323 /*
324 * If the PAN context is inactive, then we don't need
325 * to update the PAN parameters, the last thing we'll
326 * have done before it goes inactive is making the PAN
327 * parameters be WLAN-only.
328 */
329 if (!ctx_pan->is_active)
330 return 0;
331
332 memset(&cmd, 0, sizeof(cmd));
333
334 /* only 2 slots are currently allowed */
335 cmd.num_slots = 2;
336
337 cmd.slots[0].type = 0; /* BSS */
338 cmd.slots[1].type = 1; /* PAN */
339
340 if (priv->hw_roc_channel) {
341 /* both contexts must be used for this to happen */
342 slot1 = priv->hw_roc_duration;
343 slot0 = IWL_MIN_SLOT_TIME;
344 } else if (ctx_bss->vif && ctx_pan->vif) {
345 int bcnint = ctx_pan->beacon_int;
346 int dtim = ctx_pan->vif->bss_conf.dtim_period ?: 1;
347
348 /* should be set, but seems unused?? */
349 cmd.flags |= cpu_to_le16(IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE);
350
351 if (ctx_pan->vif->type == NL80211_IFTYPE_AP &&
352 bcnint &&
353 bcnint != ctx_bss->beacon_int) {
354 IWL_ERR(priv,
355 "beacon intervals don't match (%d, %d)\n",
356 ctx_bss->beacon_int, ctx_pan->beacon_int);
357 } else
358 bcnint = max_t(int, bcnint,
359 ctx_bss->beacon_int);
360 if (!bcnint)
361 bcnint = DEFAULT_BEACON_INTERVAL;
362 slot0 = bcnint / 2;
363 slot1 = bcnint - slot0;
364
365 if (test_bit(STATUS_SCAN_HW, &priv->status) ||
366 (!ctx_bss->vif->bss_conf.idle &&
367 !ctx_bss->vif->bss_conf.assoc)) {
368 slot0 = dtim * bcnint * 3 - IWL_MIN_SLOT_TIME;
369 slot1 = IWL_MIN_SLOT_TIME;
370 } else if (!ctx_pan->vif->bss_conf.idle &&
371 !ctx_pan->vif->bss_conf.assoc) {
372 slot1 = bcnint * 3 - IWL_MIN_SLOT_TIME;
373 slot0 = IWL_MIN_SLOT_TIME;
374 }
375 } else if (ctx_pan->vif) {
376 slot0 = 0;
377 slot1 = max_t(int, 1, ctx_pan->vif->bss_conf.dtim_period) *
378 ctx_pan->beacon_int;
379 slot1 = max_t(int, DEFAULT_BEACON_INTERVAL, slot1);
380
381 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
382 slot0 = slot1 * 3 - IWL_MIN_SLOT_TIME;
383 slot1 = IWL_MIN_SLOT_TIME;
384 }
385 }
386
387 cmd.slots[0].width = cpu_to_le16(slot0);
388 cmd.slots[1].width = cpu_to_le16(slot1);
389
390 ret = trans_send_cmd_pdu(&priv->trans, REPLY_WIPAN_PARAMS, CMD_SYNC,
391 sizeof(cmd), &cmd);
392 if (ret)
393 IWL_ERR(priv, "Error setting PAN parameters (%d)\n", ret);
394
395 return ret;
396}
397
269/** 398/**
270 * iwlagn_commit_rxon - commit staging_rxon to hardware 399 * iwlagn_commit_rxon - commit staging_rxon to hardware
271 * 400 *
@@ -308,8 +437,8 @@ int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
308 /* always get timestamp with Rx frame */ 437 /* always get timestamp with Rx frame */
309 ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK; 438 ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
310 439
311 if (ctx->ctxid == IWL_RXON_CTX_PAN && priv->_agn.hw_roc_channel) { 440 if (ctx->ctxid == IWL_RXON_CTX_PAN && priv->hw_roc_channel) {
312 struct ieee80211_channel *chan = priv->_agn.hw_roc_channel; 441 struct ieee80211_channel *chan = priv->hw_roc_channel;
313 442
314 iwl_set_rxon_channel(priv, chan, ctx); 443 iwl_set_rxon_channel(priv, chan, ctx);
315 iwl_set_flags_for_band(priv, ctx, chan->band, NULL); 444 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
@@ -375,13 +504,11 @@ int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
375 * do it now if after settings changed. 504 * do it now if after settings changed.
376 */ 505 */
377 iwl_set_tx_power(priv, priv->tx_power_next, false); 506 iwl_set_tx_power(priv, priv->tx_power_next, false);
378 return 0;
379 }
380 507
381 if (priv->cfg->ops->hcmd->set_pan_params) { 508 /* make sure we are in the right PS state */
382 ret = priv->cfg->ops->hcmd->set_pan_params(priv); 509 iwl_power_update_mode(priv, true);
383 if (ret) 510
384 return ret; 511 return 0;
385 } 512 }
386 513
387 iwl_set_rxon_hwcrypto(priv, ctx, !iwlagn_mod_params.sw_crypto); 514 iwl_set_rxon_hwcrypto(priv, ctx, !iwlagn_mod_params.sw_crypto);
@@ -405,6 +532,10 @@ int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
405 if (ret) 532 if (ret)
406 return ret; 533 return ret;
407 534
535 ret = iwlagn_set_pan_params(priv);
536 if (ret)
537 return ret;
538
408 if (new_assoc) 539 if (new_assoc)
409 return iwlagn_rxon_connect(priv, ctx); 540 return iwlagn_rxon_connect(priv, ctx);
410 541
@@ -446,9 +577,8 @@ int iwlagn_mac_config(struct ieee80211_hw *hw, u32 changed)
446 * set up the SM PS mode to OFF if an HT channel is 577 * set up the SM PS mode to OFF if an HT channel is
447 * configured. 578 * configured.
448 */ 579 */
449 if (priv->cfg->ops->hcmd->set_rxon_chain) 580 for_each_context(priv, ctx)
450 for_each_context(priv, ctx) 581 iwlagn_set_rxon_chain(priv, ctx);
451 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
452 } 582 }
453 583
454 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 584 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
@@ -636,6 +766,38 @@ static void iwlagn_check_needed_chains(struct iwl_priv *priv,
636 ht_conf->single_chain_sufficient = !need_multiple; 766 ht_conf->single_chain_sufficient = !need_multiple;
637} 767}
638 768
769static void iwlagn_chain_noise_reset(struct iwl_priv *priv)
770{
771 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
772 int ret;
773
774 if ((data->state == IWL_CHAIN_NOISE_ALIVE) &&
775 iwl_is_any_associated(priv)) {
776 struct iwl_calib_chain_noise_reset_cmd cmd;
777
778 /* clear data for chain noise calibration algorithm */
779 data->chain_noise_a = 0;
780 data->chain_noise_b = 0;
781 data->chain_noise_c = 0;
782 data->chain_signal_a = 0;
783 data->chain_signal_b = 0;
784 data->chain_signal_c = 0;
785 data->beacon_count = 0;
786
787 memset(&cmd, 0, sizeof(cmd));
788 iwl_set_calib_hdr(&cmd.hdr,
789 priv->phy_calib_chain_noise_reset_cmd);
790 ret = trans_send_cmd_pdu(&priv->trans,
791 REPLY_PHY_CALIBRATION_CMD,
792 CMD_SYNC, sizeof(cmd), &cmd);
793 if (ret)
794 IWL_ERR(priv,
795 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
796 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
797 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
798 }
799}
800
639void iwlagn_bss_info_changed(struct ieee80211_hw *hw, 801void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
640 struct ieee80211_vif *vif, 802 struct ieee80211_vif *vif,
641 struct ieee80211_bss_conf *bss_conf, 803 struct ieee80211_bss_conf *bss_conf,
@@ -692,7 +854,12 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
692 iwl_wake_any_queue(priv, ctx); 854 iwl_wake_any_queue(priv, ctx);
693 } 855 }
694 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; 856 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
857
858 if (ctx->ctxid == IWL_RXON_CTX_BSS)
859 priv->have_rekey_data = false;
695 } 860 }
861
862 iwlagn_bt_coex_rssi_monitor(priv);
696 } 863 }
697 864
698 if (ctx->ht.enabled) { 865 if (ctx->ht.enabled) {
@@ -704,8 +871,7 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
704 iwl_set_rxon_ht(priv, &priv->current_ht_config); 871 iwl_set_rxon_ht(priv, &priv->current_ht_config);
705 } 872 }
706 873
707 if (priv->cfg->ops->hcmd->set_rxon_chain) 874 iwlagn_set_rxon_chain(priv, ctx);
708 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
709 875
710 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ)) 876 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
711 ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK; 877 ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
@@ -743,7 +909,8 @@ void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
743 iwl_power_update_mode(priv, false); 909 iwl_power_update_mode(priv, false);
744 910
745 /* Enable RX differential gain and sensitivity calibrations */ 911 /* Enable RX differential gain and sensitivity calibrations */
746 iwl_chain_noise_reset(priv); 912 if (!priv->disable_chain_noise_cal)
913 iwlagn_chain_noise_reset(priv);
747 priv->start_calib = 1; 914 priv->start_calib = 1;
748 } 915 }
749 916
@@ -770,6 +937,13 @@ void iwlagn_post_scan(struct iwl_priv *priv)
770 struct iwl_rxon_context *ctx; 937 struct iwl_rxon_context *ctx;
771 938
772 /* 939 /*
940 * We do not commit power settings while scan is pending,
941 * do it now if the settings changed.
942 */
943 iwl_power_set_mode(priv, &priv->power_data.sleep_cmd_next, false);
944 iwl_set_tx_power(priv, priv->tx_power_next, false);
945
946 /*
773 * Since setting the RXON may have been deferred while 947 * Since setting the RXON may have been deferred while
774 * performing the scan, fire one off if needed 948 * performing the scan, fire one off if needed
775 */ 949 */
@@ -777,6 +951,5 @@ void iwlagn_post_scan(struct iwl_priv *priv)
777 if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging))) 951 if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
778 iwlagn_commit_rxon(priv, ctx); 952 iwlagn_commit_rxon(priv, ctx);
779 953
780 if (priv->cfg->ops->hcmd->set_pan_params) 954 iwlagn_set_pan_params(priv);
781 priv->cfg->ops->hcmd->set_pan_params(priv);
782} 955}
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-sta.c b/drivers/net/wireless/iwlwifi/iwl-agn-sta.c
index 0bd722cee5ae..37e624095e40 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-sta.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-sta.c
@@ -33,9 +33,10 @@
33#include "iwl-core.h" 33#include "iwl-core.h"
34#include "iwl-sta.h" 34#include "iwl-sta.h"
35#include "iwl-agn.h" 35#include "iwl-agn.h"
36#include "iwl-trans.h"
36 37
37static struct iwl_link_quality_cmd * 38static struct iwl_link_quality_cmd *
38iwl_sta_alloc_lq(struct iwl_priv *priv, u8 sta_id) 39iwl_sta_alloc_lq(struct iwl_priv *priv, struct iwl_rxon_context *ctx, u8 sta_id)
39{ 40{
40 int i, r; 41 int i, r;
41 struct iwl_link_quality_cmd *link_cmd; 42 struct iwl_link_quality_cmd *link_cmd;
@@ -47,10 +48,15 @@ iwl_sta_alloc_lq(struct iwl_priv *priv, u8 sta_id)
47 IWL_ERR(priv, "Unable to allocate memory for LQ cmd.\n"); 48 IWL_ERR(priv, "Unable to allocate memory for LQ cmd.\n");
48 return NULL; 49 return NULL;
49 } 50 }
51
52 lockdep_assert_held(&priv->mutex);
53
50 /* Set up the rate scaling to start at selected rate, fall back 54 /* Set up the rate scaling to start at selected rate, fall back
51 * all the way down to 1M in IEEE order, and then spin on 1M */ 55 * all the way down to 1M in IEEE order, and then spin on 1M */
52 if (priv->band == IEEE80211_BAND_5GHZ) 56 if (priv->band == IEEE80211_BAND_5GHZ)
53 r = IWL_RATE_6M_INDEX; 57 r = IWL_RATE_6M_INDEX;
58 else if (ctx && ctx->vif && ctx->vif->p2p)
59 r = IWL_RATE_6M_INDEX;
54 else 60 else
55 r = IWL_RATE_1M_INDEX; 61 r = IWL_RATE_1M_INDEX;
56 62
@@ -115,7 +121,7 @@ int iwlagn_add_bssid_station(struct iwl_priv *priv, struct iwl_rxon_context *ctx
115 spin_unlock_irqrestore(&priv->sta_lock, flags); 121 spin_unlock_irqrestore(&priv->sta_lock, flags);
116 122
117 /* Set up default rate scaling table in device's station table */ 123 /* Set up default rate scaling table in device's station table */
118 link_cmd = iwl_sta_alloc_lq(priv, sta_id); 124 link_cmd = iwl_sta_alloc_lq(priv, ctx, sta_id);
119 if (!link_cmd) { 125 if (!link_cmd) {
120 IWL_ERR(priv, "Unable to initialize rate scaling for station %pM.\n", 126 IWL_ERR(priv, "Unable to initialize rate scaling for station %pM.\n",
121 addr); 127 addr);
@@ -133,6 +139,14 @@ int iwlagn_add_bssid_station(struct iwl_priv *priv, struct iwl_rxon_context *ctx
133 return 0; 139 return 0;
134} 140}
135 141
142/*
143 * static WEP keys
144 *
145 * For each context, the device has a table of 4 static WEP keys
146 * (one for each key index) that is updated with the following
147 * commands.
148 */
149
136static int iwl_send_static_wepkey_cmd(struct iwl_priv *priv, 150static int iwl_send_static_wepkey_cmd(struct iwl_priv *priv,
137 struct iwl_rxon_context *ctx, 151 struct iwl_rxon_context *ctx,
138 bool send_if_empty) 152 bool send_if_empty)
@@ -175,7 +189,7 @@ static int iwl_send_static_wepkey_cmd(struct iwl_priv *priv,
175 cmd.len[0] = cmd_size; 189 cmd.len[0] = cmd_size;
176 190
177 if (not_empty || send_if_empty) 191 if (not_empty || send_if_empty)
178 return iwl_send_cmd(priv, &cmd); 192 return trans_send_cmd(&priv->trans, &cmd);
179 else 193 else
180 return 0; 194 return 0;
181} 195}
@@ -226,9 +240,7 @@ int iwl_set_default_wep_key(struct iwl_priv *priv,
226 return -EINVAL; 240 return -EINVAL;
227 } 241 }
228 242
229 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 243 keyconf->hw_key_idx = IWLAGN_HW_KEY_DEFAULT;
230 keyconf->hw_key_idx = HW_KEY_DEFAULT;
231 priv->stations[ctx->ap_sta_id].keyinfo.cipher = keyconf->cipher;
232 244
233 ctx->wep_keys[keyconf->keyidx].key_size = keyconf->keylen; 245 ctx->wep_keys[keyconf->keyidx].key_size = keyconf->keylen;
234 memcpy(&ctx->wep_keys[keyconf->keyidx].key, &keyconf->key, 246 memcpy(&ctx->wep_keys[keyconf->keyidx].key, &keyconf->key,
@@ -241,166 +253,117 @@ int iwl_set_default_wep_key(struct iwl_priv *priv,
241 return ret; 253 return ret;
242} 254}
243 255
244static int iwl_set_wep_dynamic_key_info(struct iwl_priv *priv, 256/*
245 struct iwl_rxon_context *ctx, 257 * dynamic (per-station) keys
246 struct ieee80211_key_conf *keyconf, 258 *
247 u8 sta_id) 259 * The dynamic keys are a little more complicated. The device has
248{ 260 * a key cache of up to STA_KEY_MAX_NUM/STA_KEY_MAX_NUM_PAN keys.
249 unsigned long flags; 261 * These are linked to stations by a table that contains an index
250 __le16 key_flags = 0; 262 * into the key table for each station/key index/{mcast,unicast},
251 struct iwl_addsta_cmd sta_cmd; 263 * i.e. it's basically an array of pointers like this:
252 264 * key_offset_t key_mapping[NUM_STATIONS][4][2];
253 lockdep_assert_held(&priv->mutex); 265 * (it really works differently, but you can think of it as such)
254 266 *
255 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 267 * The key uploading and linking happens in the same command, the
256 268 * add station command with STA_MODIFY_KEY_MASK.
257 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK); 269 */
258 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
259 key_flags &= ~STA_KEY_FLG_INVALID;
260
261 if (keyconf->keylen == WEP_KEY_LEN_128)
262 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
263
264 if (sta_id == ctx->bcast_sta_id)
265 key_flags |= STA_KEY_MULTICAST_MSK;
266
267 spin_lock_irqsave(&priv->sta_lock, flags);
268
269 priv->stations[sta_id].keyinfo.cipher = keyconf->cipher;
270 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
271 priv->stations[sta_id].keyinfo.keyidx = keyconf->keyidx;
272
273 memcpy(priv->stations[sta_id].keyinfo.key,
274 keyconf->key, keyconf->keylen);
275
276 memcpy(&priv->stations[sta_id].sta.key.key[3],
277 keyconf->key, keyconf->keylen);
278
279 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
280 == STA_KEY_FLG_NO_ENC)
281 priv->stations[sta_id].sta.key.key_offset =
282 iwl_get_free_ucode_key_index(priv);
283 /* else, we are overriding an existing key => no need to allocated room
284 * in uCode. */
285 270
286 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 271static u8 iwlagn_key_sta_id(struct iwl_priv *priv,
287 "no space for a new key"); 272 struct ieee80211_vif *vif,
273 struct ieee80211_sta *sta)
274{
275 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
276 u8 sta_id = IWL_INVALID_STATION;
288 277
289 priv->stations[sta_id].sta.key.key_flags = key_flags; 278 if (sta)
290 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 279 sta_id = iwl_sta_id(sta);
291 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
292 280
293 memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd)); 281 /*
294 spin_unlock_irqrestore(&priv->sta_lock, flags); 282 * The device expects GTKs for station interfaces to be
283 * installed as GTKs for the AP station. If we have no
284 * station ID, then use the ap_sta_id in that case.
285 */
286 if (!sta && vif && vif_priv->ctx) {
287 switch (vif->type) {
288 case NL80211_IFTYPE_STATION:
289 sta_id = vif_priv->ctx->ap_sta_id;
290 break;
291 default:
292 /*
293 * In all other cases, the key will be
294 * used either for TX only or is bound
295 * to a station already.
296 */
297 break;
298 }
299 }
295 300
296 return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC); 301 return sta_id;
297} 302}
298 303
299static int iwl_set_ccmp_dynamic_key_info(struct iwl_priv *priv, 304static int iwlagn_send_sta_key(struct iwl_priv *priv,
300 struct iwl_rxon_context *ctx, 305 struct ieee80211_key_conf *keyconf,
301 struct ieee80211_key_conf *keyconf, 306 u8 sta_id, u32 tkip_iv32, u16 *tkip_p1k,
302 u8 sta_id) 307 u32 cmd_flags)
303{ 308{
304 unsigned long flags; 309 unsigned long flags;
305 __le16 key_flags = 0; 310 __le16 key_flags;
306 struct iwl_addsta_cmd sta_cmd; 311 struct iwl_addsta_cmd sta_cmd;
307 312 int i;
308 lockdep_assert_held(&priv->mutex);
309
310 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK);
311 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
312 key_flags &= ~STA_KEY_FLG_INVALID;
313
314 if (sta_id == ctx->bcast_sta_id)
315 key_flags |= STA_KEY_MULTICAST_MSK;
316
317 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
318 313
319 spin_lock_irqsave(&priv->sta_lock, flags); 314 spin_lock_irqsave(&priv->sta_lock, flags);
320 priv->stations[sta_id].keyinfo.cipher = keyconf->cipher; 315 memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(sta_cmd));
321 priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
322
323 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
324 keyconf->keylen);
325
326 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
327 keyconf->keylen);
328
329 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
330 == STA_KEY_FLG_NO_ENC)
331 priv->stations[sta_id].sta.key.key_offset =
332 iwl_get_free_ucode_key_index(priv);
333 /* else, we are overriding an existing key => no need to allocated room
334 * in uCode. */
335
336 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
337 "no space for a new key");
338
339 priv->stations[sta_id].sta.key.key_flags = key_flags;
340 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
341 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
342
343 memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd));
344 spin_unlock_irqrestore(&priv->sta_lock, flags); 316 spin_unlock_irqrestore(&priv->sta_lock, flags);
345 317
346 return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC); 318 key_flags = cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
347} 319 key_flags |= STA_KEY_FLG_MAP_KEY_MSK;
348 320
349static int iwl_set_tkip_dynamic_key_info(struct iwl_priv *priv, 321 switch (keyconf->cipher) {
350 struct iwl_rxon_context *ctx, 322 case WLAN_CIPHER_SUITE_CCMP:
351 struct ieee80211_key_conf *keyconf, 323 key_flags |= STA_KEY_FLG_CCMP;
352 u8 sta_id) 324 memcpy(sta_cmd.key.key, keyconf->key, keyconf->keylen);
353{ 325 break;
354 unsigned long flags; 326 case WLAN_CIPHER_SUITE_TKIP:
355 int ret = 0; 327 key_flags |= STA_KEY_FLG_TKIP;
356 __le16 key_flags = 0; 328 sta_cmd.key.tkip_rx_tsc_byte2 = tkip_iv32;
357 329 for (i = 0; i < 5; i++)
358 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); 330 sta_cmd.key.tkip_rx_ttak[i] = cpu_to_le16(tkip_p1k[i]);
359 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 331 memcpy(sta_cmd.key.key, keyconf->key, keyconf->keylen);
360 key_flags &= ~STA_KEY_FLG_INVALID; 332 break;
333 case WLAN_CIPHER_SUITE_WEP104:
334 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK;
335 /* fall through */
336 case WLAN_CIPHER_SUITE_WEP40:
337 key_flags |= STA_KEY_FLG_WEP;
338 memcpy(&sta_cmd.key.key[3], keyconf->key, keyconf->keylen);
339 break;
340 default:
341 WARN_ON(1);
342 return -EINVAL;
343 }
361 344
362 if (sta_id == ctx->bcast_sta_id) 345 if (!(keyconf->flags & IEEE80211_KEY_FLAG_PAIRWISE))
363 key_flags |= STA_KEY_MULTICAST_MSK; 346 key_flags |= STA_KEY_MULTICAST_MSK;
364 347
365 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 348 /* key pointer (offset) */
366 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 349 sta_cmd.key.key_offset = keyconf->hw_key_idx;
367
368 spin_lock_irqsave(&priv->sta_lock, flags);
369
370 priv->stations[sta_id].keyinfo.cipher = keyconf->cipher;
371 priv->stations[sta_id].keyinfo.keylen = 16;
372
373 if ((priv->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_ENCRYPT_MSK)
374 == STA_KEY_FLG_NO_ENC)
375 priv->stations[sta_id].sta.key.key_offset =
376 iwl_get_free_ucode_key_index(priv);
377 /* else, we are overriding an existing key => no need to allocated room
378 * in uCode. */
379
380 WARN(priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET,
381 "no space for a new key");
382
383 priv->stations[sta_id].sta.key.key_flags = key_flags;
384
385 350
386 /* This copy is acutally not needed: we get the key with each TX */ 351 sta_cmd.key.key_flags = key_flags;
387 memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key, 16); 352 sta_cmd.mode = STA_CONTROL_MODIFY_MSK;
353 sta_cmd.sta.modify_mask = STA_MODIFY_KEY_MASK;
388 354
389 memcpy(priv->stations[sta_id].sta.key.key, keyconf->key, 16); 355 return iwl_send_add_sta(priv, &sta_cmd, cmd_flags);
390
391 spin_unlock_irqrestore(&priv->sta_lock, flags);
392
393 return ret;
394} 356}
395 357
396void iwl_update_tkip_key(struct iwl_priv *priv, 358void iwl_update_tkip_key(struct iwl_priv *priv,
397 struct iwl_rxon_context *ctx, 359 struct ieee80211_vif *vif,
398 struct ieee80211_key_conf *keyconf, 360 struct ieee80211_key_conf *keyconf,
399 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key) 361 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key)
400{ 362{
401 u8 sta_id; 363 u8 sta_id = iwlagn_key_sta_id(priv, vif, sta);
402 unsigned long flags; 364
403 int i; 365 if (sta_id == IWL_INVALID_STATION)
366 return;
404 367
405 if (iwl_scan_cancel(priv)) { 368 if (iwl_scan_cancel(priv)) {
406 /* cancel scan failed, just live w/ bad key and rely 369 /* cancel scan failed, just live w/ bad key and rely
@@ -408,121 +371,110 @@ void iwl_update_tkip_key(struct iwl_priv *priv,
408 return; 371 return;
409 } 372 }
410 373
411 sta_id = iwl_sta_id_or_broadcast(priv, ctx, sta); 374 iwlagn_send_sta_key(priv, keyconf, sta_id,
412 if (sta_id == IWL_INVALID_STATION) 375 iv32, phase1key, CMD_ASYNC);
413 return;
414
415 spin_lock_irqsave(&priv->sta_lock, flags);
416
417 priv->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32;
418
419 for (i = 0; i < 5; i++)
420 priv->stations[sta_id].sta.key.tkip_rx_ttak[i] =
421 cpu_to_le16(phase1key[i]);
422
423 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
424 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
425
426 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
427
428 spin_unlock_irqrestore(&priv->sta_lock, flags);
429
430} 376}
431 377
432int iwl_remove_dynamic_key(struct iwl_priv *priv, 378int iwl_remove_dynamic_key(struct iwl_priv *priv,
433 struct iwl_rxon_context *ctx, 379 struct iwl_rxon_context *ctx,
434 struct ieee80211_key_conf *keyconf, 380 struct ieee80211_key_conf *keyconf,
435 u8 sta_id) 381 struct ieee80211_sta *sta)
436{ 382{
437 unsigned long flags; 383 unsigned long flags;
438 u16 key_flags;
439 u8 keyidx;
440 struct iwl_addsta_cmd sta_cmd; 384 struct iwl_addsta_cmd sta_cmd;
385 u8 sta_id = iwlagn_key_sta_id(priv, ctx->vif, sta);
386
387 /* if station isn't there, neither is the key */
388 if (sta_id == IWL_INVALID_STATION)
389 return -ENOENT;
390
391 spin_lock_irqsave(&priv->sta_lock, flags);
392 memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(sta_cmd));
393 if (!(priv->stations[sta_id].used & IWL_STA_UCODE_ACTIVE))
394 sta_id = IWL_INVALID_STATION;
395 spin_unlock_irqrestore(&priv->sta_lock, flags);
396
397 if (sta_id == IWL_INVALID_STATION)
398 return 0;
441 399
442 lockdep_assert_held(&priv->mutex); 400 lockdep_assert_held(&priv->mutex);
443 401
444 ctx->key_mapping_keys--; 402 ctx->key_mapping_keys--;
445 403
446 spin_lock_irqsave(&priv->sta_lock, flags);
447 key_flags = le16_to_cpu(priv->stations[sta_id].sta.key.key_flags);
448 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3;
449
450 IWL_DEBUG_WEP(priv, "Remove dynamic key: idx=%d sta=%d\n", 404 IWL_DEBUG_WEP(priv, "Remove dynamic key: idx=%d sta=%d\n",
451 keyconf->keyidx, sta_id); 405 keyconf->keyidx, sta_id);
452 406
453 if (keyconf->keyidx != keyidx) { 407 if (!test_and_clear_bit(keyconf->hw_key_idx, &priv->ucode_key_table))
454 /* We need to remove a key with index different that the one 408 IWL_ERR(priv, "offset %d not used in uCode key table.\n",
455 * in the uCode. This means that the key we need to remove has 409 keyconf->hw_key_idx);
456 * been replaced by another one with different index.
457 * Don't do anything and return ok
458 */
459 spin_unlock_irqrestore(&priv->sta_lock, flags);
460 return 0;
461 }
462
463 if (priv->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) {
464 IWL_WARN(priv, "Removing wrong key %d 0x%x\n",
465 keyconf->keyidx, key_flags);
466 spin_unlock_irqrestore(&priv->sta_lock, flags);
467 return 0;
468 }
469
470 if (!test_and_clear_bit(priv->stations[sta_id].sta.key.key_offset,
471 &priv->ucode_key_table))
472 IWL_ERR(priv, "index %d not used in uCode key table.\n",
473 priv->stations[sta_id].sta.key.key_offset);
474 memset(&priv->stations[sta_id].keyinfo, 0,
475 sizeof(struct iwl_hw_key));
476 memset(&priv->stations[sta_id].sta.key, 0,
477 sizeof(struct iwl_keyinfo));
478 priv->stations[sta_id].sta.key.key_flags =
479 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
480 priv->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET;
481 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
482 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
483 410
484 if (iwl_is_rfkill(priv)) { 411 sta_cmd.key.key_flags = STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID;
485 IWL_DEBUG_WEP(priv, "Not sending REPLY_ADD_STA command because RFKILL enabled.\n"); 412 sta_cmd.key.key_offset = WEP_INVALID_OFFSET;
486 spin_unlock_irqrestore(&priv->sta_lock, flags); 413 sta_cmd.sta.modify_mask = STA_MODIFY_KEY_MASK;
487 return 0; 414 sta_cmd.mode = STA_CONTROL_MODIFY_MSK;
488 }
489 memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(struct iwl_addsta_cmd));
490 spin_unlock_irqrestore(&priv->sta_lock, flags);
491 415
492 return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC); 416 return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
493} 417}
494 418
495int iwl_set_dynamic_key(struct iwl_priv *priv, struct iwl_rxon_context *ctx, 419int iwl_set_dynamic_key(struct iwl_priv *priv,
496 struct ieee80211_key_conf *keyconf, u8 sta_id) 420 struct iwl_rxon_context *ctx,
421 struct ieee80211_key_conf *keyconf,
422 struct ieee80211_sta *sta)
497{ 423{
424 struct ieee80211_key_seq seq;
425 u16 p1k[5];
498 int ret; 426 int ret;
427 u8 sta_id = iwlagn_key_sta_id(priv, ctx->vif, sta);
428 const u8 *addr;
429
430 if (sta_id == IWL_INVALID_STATION)
431 return -EINVAL;
499 432
500 lockdep_assert_held(&priv->mutex); 433 lockdep_assert_held(&priv->mutex);
501 434
435 keyconf->hw_key_idx = iwl_get_free_ucode_key_offset(priv);
436 if (keyconf->hw_key_idx == WEP_INVALID_OFFSET)
437 return -ENOSPC;
438
502 ctx->key_mapping_keys++; 439 ctx->key_mapping_keys++;
503 keyconf->hw_key_idx = HW_KEY_DYNAMIC;
504 440
505 switch (keyconf->cipher) { 441 switch (keyconf->cipher) {
506 case WLAN_CIPHER_SUITE_CCMP:
507 ret = iwl_set_ccmp_dynamic_key_info(priv, ctx, keyconf, sta_id);
508 break;
509 case WLAN_CIPHER_SUITE_TKIP: 442 case WLAN_CIPHER_SUITE_TKIP:
510 ret = iwl_set_tkip_dynamic_key_info(priv, ctx, keyconf, sta_id); 443 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
444 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
445
446 if (sta)
447 addr = sta->addr;
448 else /* station mode case only */
449 addr = ctx->active.bssid_addr;
450
451 /* pre-fill phase 1 key into device cache */
452 ieee80211_get_key_rx_seq(keyconf, 0, &seq);
453 ieee80211_get_tkip_rx_p1k(keyconf, addr, seq.tkip.iv32, p1k);
454 ret = iwlagn_send_sta_key(priv, keyconf, sta_id,
455 seq.tkip.iv32, p1k, CMD_SYNC);
511 break; 456 break;
457 case WLAN_CIPHER_SUITE_CCMP:
458 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
459 /* fall through */
512 case WLAN_CIPHER_SUITE_WEP40: 460 case WLAN_CIPHER_SUITE_WEP40:
513 case WLAN_CIPHER_SUITE_WEP104: 461 case WLAN_CIPHER_SUITE_WEP104:
514 ret = iwl_set_wep_dynamic_key_info(priv, ctx, keyconf, sta_id); 462 ret = iwlagn_send_sta_key(priv, keyconf, sta_id,
463 0, NULL, CMD_SYNC);
515 break; 464 break;
516 default: 465 default:
517 IWL_ERR(priv, 466 IWL_ERR(priv, "Unknown cipher %x\n", keyconf->cipher);
518 "Unknown alg: %s cipher = %x\n", __func__,
519 keyconf->cipher);
520 ret = -EINVAL; 467 ret = -EINVAL;
521 } 468 }
522 469
523 IWL_DEBUG_WEP(priv, "Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n", 470 if (ret) {
471 ctx->key_mapping_keys--;
472 clear_bit(keyconf->hw_key_idx, &priv->ucode_key_table);
473 }
474
475 IWL_DEBUG_WEP(priv, "Set dynamic key: cipher=%x len=%d idx=%d sta=%pM ret=%d\n",
524 keyconf->cipher, keyconf->keylen, keyconf->keyidx, 476 keyconf->cipher, keyconf->keylen, keyconf->keyidx,
525 sta_id, ret); 477 sta ? sta->addr : NULL, ret);
526 478
527 return ret; 479 return ret;
528} 480}
@@ -554,7 +506,7 @@ int iwlagn_alloc_bcast_station(struct iwl_priv *priv,
554 priv->stations[sta_id].used |= IWL_STA_BCAST; 506 priv->stations[sta_id].used |= IWL_STA_BCAST;
555 spin_unlock_irqrestore(&priv->sta_lock, flags); 507 spin_unlock_irqrestore(&priv->sta_lock, flags);
556 508
557 link_cmd = iwl_sta_alloc_lq(priv, sta_id); 509 link_cmd = iwl_sta_alloc_lq(priv, ctx, sta_id);
558 if (!link_cmd) { 510 if (!link_cmd) {
559 IWL_ERR(priv, 511 IWL_ERR(priv,
560 "Unable to initialize rate scaling for bcast station.\n"); 512 "Unable to initialize rate scaling for bcast station.\n");
@@ -574,14 +526,14 @@ int iwlagn_alloc_bcast_station(struct iwl_priv *priv,
574 * Only used by iwlagn. Placed here to have all bcast station management 526 * Only used by iwlagn. Placed here to have all bcast station management
575 * code together. 527 * code together.
576 */ 528 */
577static int iwl_update_bcast_station(struct iwl_priv *priv, 529int iwl_update_bcast_station(struct iwl_priv *priv,
578 struct iwl_rxon_context *ctx) 530 struct iwl_rxon_context *ctx)
579{ 531{
580 unsigned long flags; 532 unsigned long flags;
581 struct iwl_link_quality_cmd *link_cmd; 533 struct iwl_link_quality_cmd *link_cmd;
582 u8 sta_id = ctx->bcast_sta_id; 534 u8 sta_id = ctx->bcast_sta_id;
583 535
584 link_cmd = iwl_sta_alloc_lq(priv, sta_id); 536 link_cmd = iwl_sta_alloc_lq(priv, ctx, sta_id);
585 if (!link_cmd) { 537 if (!link_cmd) {
586 IWL_ERR(priv, "Unable to initialize rate scaling for bcast station.\n"); 538 IWL_ERR(priv, "Unable to initialize rate scaling for bcast station.\n");
587 return -ENOMEM; 539 return -ENOMEM;
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-tt.c b/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
index 348f74f1c8e8..f501d742984c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-tt.c
@@ -198,7 +198,7 @@ static void iwl_tt_check_exit_ct_kill(unsigned long data)
198 /* Reschedule the ct_kill timer to occur in 198 /* Reschedule the ct_kill timer to occur in
199 * CT_KILL_EXIT_DURATION seconds to ensure we get a 199 * CT_KILL_EXIT_DURATION seconds to ensure we get a
200 * thermal update */ 200 * thermal update */
201 IWL_DEBUG_POWER(priv, "schedule ct_kill exit timer\n"); 201 IWL_DEBUG_TEMP(priv, "schedule ct_kill exit timer\n");
202 mod_timer(&priv->thermal_throttle.ct_kill_exit_tm, 202 mod_timer(&priv->thermal_throttle.ct_kill_exit_tm,
203 jiffies + CT_KILL_EXIT_DURATION * HZ); 203 jiffies + CT_KILL_EXIT_DURATION * HZ);
204 } 204 }
@@ -208,15 +208,15 @@ static void iwl_perform_ct_kill_task(struct iwl_priv *priv,
208 bool stop) 208 bool stop)
209{ 209{
210 if (stop) { 210 if (stop) {
211 IWL_DEBUG_POWER(priv, "Stop all queues\n"); 211 IWL_DEBUG_TEMP(priv, "Stop all queues\n");
212 if (priv->mac80211_registered) 212 if (priv->mac80211_registered)
213 ieee80211_stop_queues(priv->hw); 213 ieee80211_stop_queues(priv->hw);
214 IWL_DEBUG_POWER(priv, 214 IWL_DEBUG_TEMP(priv,
215 "Schedule 5 seconds CT_KILL Timer\n"); 215 "Schedule 5 seconds CT_KILL Timer\n");
216 mod_timer(&priv->thermal_throttle.ct_kill_exit_tm, 216 mod_timer(&priv->thermal_throttle.ct_kill_exit_tm,
217 jiffies + CT_KILL_EXIT_DURATION * HZ); 217 jiffies + CT_KILL_EXIT_DURATION * HZ);
218 } else { 218 } else {
219 IWL_DEBUG_POWER(priv, "Wake all queues\n"); 219 IWL_DEBUG_TEMP(priv, "Wake all queues\n");
220 if (priv->mac80211_registered) 220 if (priv->mac80211_registered)
221 ieee80211_wake_queues(priv->hw); 221 ieee80211_wake_queues(priv->hw);
222 } 222 }
@@ -232,7 +232,7 @@ static void iwl_tt_ready_for_ct_kill(unsigned long data)
232 232
233 /* temperature timer expired, ready to go into CT_KILL state */ 233 /* temperature timer expired, ready to go into CT_KILL state */
234 if (tt->state != IWL_TI_CT_KILL) { 234 if (tt->state != IWL_TI_CT_KILL) {
235 IWL_DEBUG_POWER(priv, "entering CT_KILL state when " 235 IWL_DEBUG_TEMP(priv, "entering CT_KILL state when "
236 "temperature timer expired\n"); 236 "temperature timer expired\n");
237 tt->state = IWL_TI_CT_KILL; 237 tt->state = IWL_TI_CT_KILL;
238 set_bit(STATUS_CT_KILL, &priv->status); 238 set_bit(STATUS_CT_KILL, &priv->status);
@@ -242,7 +242,7 @@ static void iwl_tt_ready_for_ct_kill(unsigned long data)
242 242
243static void iwl_prepare_ct_kill_task(struct iwl_priv *priv) 243static void iwl_prepare_ct_kill_task(struct iwl_priv *priv)
244{ 244{
245 IWL_DEBUG_POWER(priv, "Prepare to enter IWL_TI_CT_KILL\n"); 245 IWL_DEBUG_TEMP(priv, "Prepare to enter IWL_TI_CT_KILL\n");
246 /* make request to retrieve statistics information */ 246 /* make request to retrieve statistics information */
247 iwl_send_statistics_request(priv, CMD_SYNC, false); 247 iwl_send_statistics_request(priv, CMD_SYNC, false);
248 /* Reschedule the ct_kill wait timer */ 248 /* Reschedule the ct_kill wait timer */
@@ -273,7 +273,7 @@ static void iwl_legacy_tt_handler(struct iwl_priv *priv, s32 temp, bool force)
273 (temp > tt->tt_previous_temp) && 273 (temp > tt->tt_previous_temp) &&
274 ((temp - tt->tt_previous_temp) > 274 ((temp - tt->tt_previous_temp) >
275 IWL_TT_INCREASE_MARGIN)) { 275 IWL_TT_INCREASE_MARGIN)) {
276 IWL_DEBUG_POWER(priv, 276 IWL_DEBUG_TEMP(priv,
277 "Temperature increase %d degree Celsius\n", 277 "Temperature increase %d degree Celsius\n",
278 (temp - tt->tt_previous_temp)); 278 (temp - tt->tt_previous_temp));
279 } 279 }
@@ -338,9 +338,9 @@ static void iwl_legacy_tt_handler(struct iwl_priv *priv, s32 temp, bool force)
338 } else if (old_state == IWL_TI_CT_KILL && 338 } else if (old_state == IWL_TI_CT_KILL &&
339 tt->state != IWL_TI_CT_KILL) 339 tt->state != IWL_TI_CT_KILL)
340 iwl_perform_ct_kill_task(priv, false); 340 iwl_perform_ct_kill_task(priv, false);
341 IWL_DEBUG_POWER(priv, "Temperature state changed %u\n", 341 IWL_DEBUG_TEMP(priv, "Temperature state changed %u\n",
342 tt->state); 342 tt->state);
343 IWL_DEBUG_POWER(priv, "Power Index change to %u\n", 343 IWL_DEBUG_TEMP(priv, "Power Index change to %u\n",
344 tt->tt_power_mode); 344 tt->tt_power_mode);
345 } 345 }
346 mutex_unlock(&priv->mutex); 346 mutex_unlock(&priv->mutex);
@@ -397,7 +397,7 @@ static void iwl_advance_tt_handler(struct iwl_priv *priv, s32 temp, bool force)
397 (temp > tt->tt_previous_temp) && 397 (temp > tt->tt_previous_temp) &&
398 ((temp - tt->tt_previous_temp) > 398 ((temp - tt->tt_previous_temp) >
399 IWL_TT_INCREASE_MARGIN)) { 399 IWL_TT_INCREASE_MARGIN)) {
400 IWL_DEBUG_POWER(priv, 400 IWL_DEBUG_TEMP(priv,
401 "Temperature increase %d " 401 "Temperature increase %d "
402 "degree Celsius\n", 402 "degree Celsius\n",
403 (temp - tt->tt_previous_temp)); 403 (temp - tt->tt_previous_temp));
@@ -467,13 +467,13 @@ static void iwl_advance_tt_handler(struct iwl_priv *priv, s32 temp, bool force)
467 set_bit(STATUS_CT_KILL, &priv->status); 467 set_bit(STATUS_CT_KILL, &priv->status);
468 tt->state = old_state; 468 tt->state = old_state;
469 } else { 469 } else {
470 IWL_DEBUG_POWER(priv, 470 IWL_DEBUG_TEMP(priv,
471 "Thermal Throttling to new state: %u\n", 471 "Thermal Throttling to new state: %u\n",
472 tt->state); 472 tt->state);
473 if (old_state != IWL_TI_CT_KILL && 473 if (old_state != IWL_TI_CT_KILL &&
474 tt->state == IWL_TI_CT_KILL) { 474 tt->state == IWL_TI_CT_KILL) {
475 if (force) { 475 if (force) {
476 IWL_DEBUG_POWER(priv, 476 IWL_DEBUG_TEMP(priv,
477 "Enter IWL_TI_CT_KILL\n"); 477 "Enter IWL_TI_CT_KILL\n");
478 set_bit(STATUS_CT_KILL, &priv->status); 478 set_bit(STATUS_CT_KILL, &priv->status);
479 iwl_perform_ct_kill_task(priv, true); 479 iwl_perform_ct_kill_task(priv, true);
@@ -483,7 +483,7 @@ static void iwl_advance_tt_handler(struct iwl_priv *priv, s32 temp, bool force)
483 } 483 }
484 } else if (old_state == IWL_TI_CT_KILL && 484 } else if (old_state == IWL_TI_CT_KILL &&
485 tt->state != IWL_TI_CT_KILL) { 485 tt->state != IWL_TI_CT_KILL) {
486 IWL_DEBUG_POWER(priv, "Exit IWL_TI_CT_KILL\n"); 486 IWL_DEBUG_TEMP(priv, "Exit IWL_TI_CT_KILL\n");
487 iwl_perform_ct_kill_task(priv, false); 487 iwl_perform_ct_kill_task(priv, false);
488 } 488 }
489 } 489 }
@@ -568,7 +568,7 @@ void iwl_tt_enter_ct_kill(struct iwl_priv *priv)
568 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 568 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
569 return; 569 return;
570 570
571 IWL_DEBUG_POWER(priv, "Queueing critical temperature enter.\n"); 571 IWL_DEBUG_TEMP(priv, "Queueing critical temperature enter.\n");
572 queue_work(priv->workqueue, &priv->ct_enter); 572 queue_work(priv->workqueue, &priv->ct_enter);
573} 573}
574 574
@@ -577,7 +577,7 @@ void iwl_tt_exit_ct_kill(struct iwl_priv *priv)
577 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 577 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
578 return; 578 return;
579 579
580 IWL_DEBUG_POWER(priv, "Queueing critical temperature exit.\n"); 580 IWL_DEBUG_TEMP(priv, "Queueing critical temperature exit.\n");
581 queue_work(priv->workqueue, &priv->ct_exit); 581 queue_work(priv->workqueue, &priv->ct_exit);
582} 582}
583 583
@@ -603,7 +603,7 @@ void iwl_tt_handler(struct iwl_priv *priv)
603 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 603 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
604 return; 604 return;
605 605
606 IWL_DEBUG_POWER(priv, "Queueing thermal throttling work.\n"); 606 IWL_DEBUG_TEMP(priv, "Queueing thermal throttling work.\n");
607 queue_work(priv->workqueue, &priv->tt_work); 607 queue_work(priv->workqueue, &priv->tt_work);
608} 608}
609 609
@@ -618,7 +618,7 @@ void iwl_tt_initialize(struct iwl_priv *priv)
618 int size = sizeof(struct iwl_tt_trans) * (IWL_TI_STATE_MAX - 1); 618 int size = sizeof(struct iwl_tt_trans) * (IWL_TI_STATE_MAX - 1);
619 struct iwl_tt_trans *transaction; 619 struct iwl_tt_trans *transaction;
620 620
621 IWL_DEBUG_POWER(priv, "Initialize Thermal Throttling\n"); 621 IWL_DEBUG_TEMP(priv, "Initialize Thermal Throttling\n");
622 622
623 memset(tt, 0, sizeof(struct iwl_tt_mgmt)); 623 memset(tt, 0, sizeof(struct iwl_tt_mgmt));
624 624
@@ -638,7 +638,7 @@ void iwl_tt_initialize(struct iwl_priv *priv)
638 INIT_WORK(&priv->ct_exit, iwl_bg_ct_exit); 638 INIT_WORK(&priv->ct_exit, iwl_bg_ct_exit);
639 639
640 if (priv->cfg->base_params->adv_thermal_throttle) { 640 if (priv->cfg->base_params->adv_thermal_throttle) {
641 IWL_DEBUG_POWER(priv, "Advanced Thermal Throttling\n"); 641 IWL_DEBUG_TEMP(priv, "Advanced Thermal Throttling\n");
642 tt->restriction = kzalloc(sizeof(struct iwl_tt_restriction) * 642 tt->restriction = kzalloc(sizeof(struct iwl_tt_restriction) *
643 IWL_TI_STATE_MAX, GFP_KERNEL); 643 IWL_TI_STATE_MAX, GFP_KERNEL);
644 tt->transaction = kzalloc(sizeof(struct iwl_tt_trans) * 644 tt->transaction = kzalloc(sizeof(struct iwl_tt_trans) *
@@ -671,7 +671,7 @@ void iwl_tt_initialize(struct iwl_priv *priv)
671 priv->thermal_throttle.advanced_tt = true; 671 priv->thermal_throttle.advanced_tt = true;
672 } 672 }
673 } else { 673 } else {
674 IWL_DEBUG_POWER(priv, "Legacy Thermal Throttling\n"); 674 IWL_DEBUG_TEMP(priv, "Legacy Thermal Throttling\n");
675 priv->thermal_throttle.advanced_tt = false; 675 priv->thermal_throttle.advanced_tt = false;
676 } 676 }
677} 677}
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-tx.c b/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
index 4974cd7837cb..53bb59ee719d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
@@ -39,6 +39,7 @@
39#include "iwl-helpers.h" 39#include "iwl-helpers.h"
40#include "iwl-agn-hw.h" 40#include "iwl-agn-hw.h"
41#include "iwl-agn.h" 41#include "iwl-agn.h"
42#include "iwl-trans.h"
42 43
43/* 44/*
44 * mac80211 queues, ACs, hardware queues, FIFOs. 45 * mac80211 queues, ACs, hardware queues, FIFOs.
@@ -95,132 +96,8 @@ static inline int get_fifo_from_tid(struct iwl_rxon_context *ctx, u16 tid)
95 return -EINVAL; 96 return -EINVAL;
96} 97}
97 98
98/** 99static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id,
99 * iwlagn_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 100 int tid)
100 */
101static void iwlagn_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
102 struct iwl_tx_queue *txq,
103 u16 byte_cnt)
104{
105 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
106 int write_ptr = txq->q.write_ptr;
107 int txq_id = txq->q.id;
108 u8 sec_ctl = 0;
109 u8 sta_id = 0;
110 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
111 __le16 bc_ent;
112
113 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
114
115 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
116 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
117
118 switch (sec_ctl & TX_CMD_SEC_MSK) {
119 case TX_CMD_SEC_CCM:
120 len += CCMP_MIC_LEN;
121 break;
122 case TX_CMD_SEC_TKIP:
123 len += TKIP_ICV_LEN;
124 break;
125 case TX_CMD_SEC_WEP:
126 len += WEP_IV_LEN + WEP_ICV_LEN;
127 break;
128 }
129
130 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
131
132 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
133
134 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
135 scd_bc_tbl[txq_id].
136 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
137}
138
139static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
140 struct iwl_tx_queue *txq)
141{
142 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
143 int txq_id = txq->q.id;
144 int read_ptr = txq->q.read_ptr;
145 u8 sta_id = 0;
146 __le16 bc_ent;
147
148 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
149
150 if (txq_id != priv->cmd_queue)
151 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
152
153 bc_ent = cpu_to_le16(1 | (sta_id << 12));
154 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
155
156 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
157 scd_bc_tbl[txq_id].
158 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
159}
160
161static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
162 u16 txq_id)
163{
164 u32 tbl_dw_addr;
165 u32 tbl_dw;
166 u16 scd_q2ratid;
167
168 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
169
170 tbl_dw_addr = priv->scd_base_addr +
171 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
172
173 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
174
175 if (txq_id & 0x1)
176 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
177 else
178 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
179
180 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
181
182 return 0;
183}
184
185static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
186{
187 /* Simply stop the queue, but don't change any configuration;
188 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
189 iwl_write_prph(priv,
190 IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
191 (0 << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
192 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
193}
194
195void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
196 int txq_id, u32 index)
197{
198 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
199 (index & 0xff) | (txq_id << 8));
200 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(txq_id), index);
201}
202
203void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
204 struct iwl_tx_queue *txq,
205 int tx_fifo_id, int scd_retry)
206{
207 int txq_id = txq->q.id;
208 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
209
210 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_STATUS_BITS(txq_id),
211 (active << IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
212 (tx_fifo_id << IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF) |
213 (1 << IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL) |
214 IWLAGN_SCD_QUEUE_STTS_REG_MSK);
215
216 txq->sched_retry = scd_retry;
217
218 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
219 active ? "Activate" : "Deactivate",
220 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
221}
222
223static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id, int tid)
224{ 101{
225 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) || 102 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
226 (IWLAGN_FIRST_AMPDU_QUEUE + 103 (IWLAGN_FIRST_AMPDU_QUEUE +
@@ -237,106 +114,14 @@ static int iwlagn_txq_agg_enable(struct iwl_priv *priv, int txq_id, int sta_id,
237 return iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); 114 return iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
238} 115}
239 116
240void iwlagn_txq_agg_queue_setup(struct iwl_priv *priv, 117static void iwlagn_tx_cmd_protection(struct iwl_priv *priv,
241 struct ieee80211_sta *sta, 118 struct ieee80211_tx_info *info,
242 int tid, int frame_limit) 119 __le16 fc, __le32 *tx_flags)
243{ 120{
244 int sta_id, tx_fifo, txq_id, ssn_idx; 121 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS ||
245 u16 ra_tid; 122 info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT ||
246 unsigned long flags; 123 info->flags & IEEE80211_TX_CTL_AMPDU)
247 struct iwl_tid_data *tid_data; 124 *tx_flags |= TX_CMD_FLG_PROT_REQUIRE_MSK;
248
249 sta_id = iwl_sta_id(sta);
250 if (WARN_ON(sta_id == IWL_INVALID_STATION))
251 return;
252 if (WARN_ON(tid >= MAX_TID_COUNT))
253 return;
254
255 spin_lock_irqsave(&priv->sta_lock, flags);
256 tid_data = &priv->stations[sta_id].tid[tid];
257 ssn_idx = SEQ_TO_SN(tid_data->seq_number);
258 txq_id = tid_data->agg.txq_id;
259 tx_fifo = tid_data->agg.tx_fifo;
260 spin_unlock_irqrestore(&priv->sta_lock, flags);
261
262 ra_tid = BUILD_RAxTID(sta_id, tid);
263
264 spin_lock_irqsave(&priv->lock, flags);
265
266 /* Stop this Tx queue before configuring it */
267 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
268
269 /* Map receiver-address / traffic-ID to this queue */
270 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
271
272 /* Set this queue as a chain-building queue */
273 iwl_set_bits_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL, (1<<txq_id));
274
275 /* enable aggregations for the queue */
276 iwl_set_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1<<txq_id));
277
278 /* Place first TFD at index corresponding to start sequence number.
279 * Assumes that ssn_idx is valid (!= 0xFFF) */
280 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
281 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
282 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
283
284 /* Set up Tx window size and frame limit for this queue */
285 iwl_write_targ_mem(priv, priv->scd_base_addr +
286 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
287 sizeof(u32),
288 ((frame_limit <<
289 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
290 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
291 ((frame_limit <<
292 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
293 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
294
295 iwl_set_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
296
297 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
298 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
299
300 spin_unlock_irqrestore(&priv->lock, flags);
301}
302
303static int iwlagn_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
304 u16 ssn_idx, u8 tx_fifo)
305{
306 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
307 (IWLAGN_FIRST_AMPDU_QUEUE +
308 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
309 IWL_ERR(priv,
310 "queue number out of range: %d, must be %d to %d\n",
311 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
312 IWLAGN_FIRST_AMPDU_QUEUE +
313 priv->cfg->base_params->num_of_ampdu_queues - 1);
314 return -EINVAL;
315 }
316
317 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
318
319 iwl_clear_bits_prph(priv, IWLAGN_SCD_AGGR_SEL, (1 << txq_id));
320
321 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
322 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
323 /* supposes that ssn_idx is valid (!= 0xFFF) */
324 iwlagn_set_wr_ptrs(priv, txq_id, ssn_idx);
325
326 iwl_clear_bits_prph(priv, IWLAGN_SCD_INTERRUPT_MASK, (1 << txq_id));
327 iwl_txq_ctx_deactivate(priv, txq_id);
328 iwlagn_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
329
330 return 0;
331}
332
333/*
334 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
335 * must be called under priv->lock and mac access
336 */
337void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask)
338{
339 iwl_write_prph(priv, IWLAGN_SCD_TXFACT, mask);
340} 125}
341 126
342/* 127/*
@@ -353,19 +138,15 @@ static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
353 __le32 tx_flags = tx_cmd->tx_flags; 138 __le32 tx_flags = tx_cmd->tx_flags;
354 139
355 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 140 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
356 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 141
142 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
357 tx_flags |= TX_CMD_FLG_ACK_MSK; 143 tx_flags |= TX_CMD_FLG_ACK_MSK;
358 if (ieee80211_is_mgmt(fc)) 144 else
359 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 145 tx_flags &= ~TX_CMD_FLG_ACK_MSK;
360 if (ieee80211_is_probe_resp(fc) &&
361 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
362 tx_flags |= TX_CMD_FLG_TSF_MSK;
363 } else {
364 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
365 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
366 }
367 146
368 if (ieee80211_is_back_req(fc)) 147 if (ieee80211_is_probe_resp(fc))
148 tx_flags |= TX_CMD_FLG_TSF_MSK;
149 else if (ieee80211_is_back_req(fc))
369 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; 150 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
370 else if (info->band == IEEE80211_BAND_2GHZ && 151 else if (info->band == IEEE80211_BAND_2GHZ &&
371 priv->cfg->bt_params && 152 priv->cfg->bt_params &&
@@ -388,7 +169,7 @@ static void iwlagn_tx_cmd_build_basic(struct iwl_priv *priv,
388 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 169 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
389 } 170 }
390 171
391 priv->cfg->ops->utils->tx_cmd_protection(priv, info, fc, &tx_flags); 172 iwlagn_tx_cmd_protection(priv, info, fc, &tx_flags);
392 173
393 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); 174 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
394 if (ieee80211_is_mgmt(fc)) { 175 if (ieee80211_is_mgmt(fc)) {
@@ -436,6 +217,18 @@ static void iwlagn_tx_cmd_build_rate(struct iwl_priv *priv,
436 if (ieee80211_is_data(fc)) { 217 if (ieee80211_is_data(fc)) {
437 tx_cmd->initial_rate_index = 0; 218 tx_cmd->initial_rate_index = 0;
438 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; 219 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
220#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
221 if (priv->tm_fixed_rate) {
222 /*
223 * rate overwrite by testmode
224 * we not only send lq command to change rate
225 * we also re-enforce per data pkt base.
226 */
227 tx_cmd->tx_flags &= ~TX_CMD_FLG_STA_RATE_MSK;
228 memcpy(&tx_cmd->rate_n_flags, &priv->tm_fixed_rate,
229 sizeof(tx_cmd->rate_n_flags));
230 }
231#endif
439 return; 232 return;
440 } 233 }
441 234
@@ -497,8 +290,7 @@ static void iwlagn_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
497 290
498 case WLAN_CIPHER_SUITE_TKIP: 291 case WLAN_CIPHER_SUITE_TKIP:
499 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; 292 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
500 ieee80211_get_tkip_key(keyconf, skb_frag, 293 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
501 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
502 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n"); 294 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
503 break; 295 break;
504 296
@@ -528,26 +320,17 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
528{ 320{
529 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 321 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
530 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 322 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
531 struct ieee80211_sta *sta = info->control.sta;
532 struct iwl_station_priv *sta_priv = NULL; 323 struct iwl_station_priv *sta_priv = NULL;
533 struct iwl_tx_queue *txq;
534 struct iwl_queue *q;
535 struct iwl_device_cmd *out_cmd;
536 struct iwl_cmd_meta *out_meta;
537 struct iwl_tx_cmd *tx_cmd;
538 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; 324 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
325 struct iwl_tx_cmd *tx_cmd;
539 int txq_id; 326 int txq_id;
540 dma_addr_t phys_addr = 0; 327
541 dma_addr_t txcmd_phys;
542 dma_addr_t scratch_phys;
543 u16 len, firstlen, secondlen;
544 u16 seq_number = 0; 328 u16 seq_number = 0;
545 __le16 fc; 329 __le16 fc;
546 u8 hdr_len; 330 u8 hdr_len;
331 u16 len;
547 u8 sta_id; 332 u8 sta_id;
548 u8 wait_write_ptr = 0;
549 u8 tid = 0; 333 u8 tid = 0;
550 u8 *qc = NULL;
551 unsigned long flags; 334 unsigned long flags;
552 bool is_agg = false; 335 bool is_agg = false;
553 336
@@ -595,8 +378,8 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
595 378
596 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id); 379 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
597 380
598 if (sta) 381 if (info->control.sta)
599 sta_priv = (void *)sta->drv_priv; 382 sta_priv = (void *)info->control.sta->drv_priv;
600 383
601 if (sta_priv && sta_priv->asleep && 384 if (sta_priv && sta_priv->asleep &&
602 (info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)) { 385 (info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)) {
@@ -631,6 +414,7 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
631 spin_lock(&priv->sta_lock); 414 spin_lock(&priv->sta_lock);
632 415
633 if (ieee80211_is_data_qos(fc)) { 416 if (ieee80211_is_data_qos(fc)) {
417 u8 *qc = NULL;
634 qc = ieee80211_get_qos_ctl(hdr); 418 qc = ieee80211_get_qos_ctl(hdr);
635 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 419 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
636 420
@@ -651,38 +435,13 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
651 } 435 }
652 } 436 }
653 437
654 txq = &priv->txq[txq_id]; 438 tx_cmd = trans_get_tx_cmd(&priv->trans, txq_id);
655 q = &txq->q; 439 if (unlikely(!tx_cmd))
656
657 if (unlikely(iwl_queue_space(q) < q->high_mark))
658 goto drop_unlock_sta; 440 goto drop_unlock_sta;
659 441
660 /* Set up driver data for this TFD */
661 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
662 txq->txb[q->write_ptr].skb = skb;
663 txq->txb[q->write_ptr].ctx = ctx;
664
665 /* Set up first empty entry in queue's array of Tx/cmd buffers */
666 out_cmd = txq->cmd[q->write_ptr];
667 out_meta = &txq->meta[q->write_ptr];
668 tx_cmd = &out_cmd->cmd.tx;
669 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
670 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
671
672 /*
673 * Set up the Tx-command (not MAC!) header.
674 * Store the chosen Tx queue and TFD index within the sequence field;
675 * after Tx, uCode's Tx response will return this value so driver can
676 * locate the frame within the tx queue and do post-tx processing.
677 */
678 out_cmd->hdr.cmd = REPLY_TX;
679 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
680 INDEX_TO_SEQ(q->write_ptr)));
681
682 /* Copy MAC header from skb into command buffer */ 442 /* Copy MAC header from skb into command buffer */
683 memcpy(tx_cmd->hdr, hdr, hdr_len); 443 memcpy(tx_cmd->hdr, hdr, hdr_len);
684 444
685
686 /* Total # bytes to be transmitted */ 445 /* Total # bytes to be transmitted */
687 len = (u16)skb->len; 446 len = (u16)skb->len;
688 tx_cmd->len = cpu_to_le16(len); 447 tx_cmd->len = cpu_to_le16(len);
@@ -697,54 +456,9 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
697 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc); 456 iwlagn_tx_cmd_build_rate(priv, tx_cmd, info, fc);
698 457
699 iwl_update_stats(priv, true, fc, len); 458 iwl_update_stats(priv, true, fc, len);
700 /*
701 * Use the first empty entry in this queue's command buffer array
702 * to contain the Tx command and MAC header concatenated together
703 * (payload data will be in another buffer).
704 * Size of this varies, due to varying MAC header length.
705 * If end is not dword aligned, we'll have 2 extra bytes at the end
706 * of the MAC header (device reads on dword boundaries).
707 * We'll tell device about this padding later.
708 */
709 len = sizeof(struct iwl_tx_cmd) +
710 sizeof(struct iwl_cmd_header) + hdr_len;
711 firstlen = (len + 3) & ~3;
712
713 /* Tell NIC about any 2-byte padding after MAC header */
714 if (firstlen != len)
715 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
716
717 /* Physical address of this Tx command's header (not MAC header!),
718 * within command buffer array. */
719 txcmd_phys = pci_map_single(priv->pci_dev,
720 &out_cmd->hdr, firstlen,
721 PCI_DMA_BIDIRECTIONAL);
722 if (unlikely(pci_dma_mapping_error(priv->pci_dev, txcmd_phys)))
723 goto drop_unlock_sta;
724 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
725 dma_unmap_len_set(out_meta, len, firstlen);
726 459
727 if (!ieee80211_has_morefrags(hdr->frame_control)) { 460 if (trans_tx(&priv->trans, skb, tx_cmd, txq_id, fc, is_agg, ctx))
728 txq->need_update = 1; 461 goto drop_unlock_sta;
729 } else {
730 wait_write_ptr = 1;
731 txq->need_update = 0;
732 }
733
734 /* Set up TFD's 2nd entry to point directly to remainder of skb,
735 * if any (802.11 null frames have no payload). */
736 secondlen = skb->len - hdr_len;
737 if (secondlen > 0) {
738 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
739 secondlen, PCI_DMA_TODEVICE);
740 if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) {
741 pci_unmap_single(priv->pci_dev,
742 dma_unmap_addr(out_meta, mapping),
743 dma_unmap_len(out_meta, len),
744 PCI_DMA_BIDIRECTIONAL);
745 goto drop_unlock_sta;
746 }
747 }
748 462
749 if (ieee80211_is_data_qos(fc)) { 463 if (ieee80211_is_data_qos(fc)) {
750 priv->stations[sta_id].tid[tid].tfds_in_queue++; 464 priv->stations[sta_id].tid[tid].tfds_in_queue++;
@@ -753,55 +467,9 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
753 } 467 }
754 468
755 spin_unlock(&priv->sta_lock); 469 spin_unlock(&priv->sta_lock);
756
757 /* Attach buffers to TFD */
758 iwlagn_txq_attach_buf_to_tfd(priv, txq, txcmd_phys, firstlen, 1);
759 if (secondlen > 0)
760 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
761 secondlen, 0);
762
763 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
764 offsetof(struct iwl_tx_cmd, scratch);
765
766 /* take back ownership of DMA buffer to enable update */
767 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
768 firstlen, PCI_DMA_BIDIRECTIONAL);
769 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
770 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
771
772 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
773 le16_to_cpu(out_cmd->hdr.sequence));
774 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
775 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
776 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
777
778 /* Set up entry for this TFD in Tx byte-count array */
779 if (info->flags & IEEE80211_TX_CTL_AMPDU)
780 iwlagn_txq_update_byte_cnt_tbl(priv, txq,
781 le16_to_cpu(tx_cmd->len));
782
783 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
784 firstlen, PCI_DMA_BIDIRECTIONAL);
785
786 trace_iwlwifi_dev_tx(priv,
787 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
788 sizeof(struct iwl_tfd),
789 &out_cmd->hdr, firstlen,
790 skb->data + hdr_len, secondlen);
791
792 /* Tell device the write index *just past* this latest filled TFD */
793 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
794 iwl_txq_update_write_ptr(priv, txq);
795 spin_unlock_irqrestore(&priv->lock, flags); 470 spin_unlock_irqrestore(&priv->lock, flags);
796 471
797 /* 472 /*
798 * At this point the frame is "transmitted" successfully
799 * and we will get a TX status notification eventually,
800 * regardless of the value of ret. "ret" only indicates
801 * whether or not we should update the write pointer.
802 */
803
804 /*
805 * Avoid atomic ops if it isn't an associated client. 473 * Avoid atomic ops if it isn't an associated client.
806 * Also, if this is a packet for aggregation, don't 474 * Also, if this is a packet for aggregation, don't
807 * increase the counter because the ucode will stop 475 * increase the counter because the ucode will stop
@@ -811,17 +479,6 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
811 if (sta_priv && sta_priv->client && !is_agg) 479 if (sta_priv && sta_priv->client && !is_agg)
812 atomic_inc(&sta_priv->pending_frames); 480 atomic_inc(&sta_priv->pending_frames);
813 481
814 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
815 if (wait_write_ptr) {
816 spin_lock_irqsave(&priv->lock, flags);
817 txq->need_update = 1;
818 iwl_txq_update_write_ptr(priv, txq);
819 spin_unlock_irqrestore(&priv->lock, flags);
820 } else {
821 iwl_stop_queue(priv, txq);
822 }
823 }
824
825 return 0; 482 return 0;
826 483
827drop_unlock_sta: 484drop_unlock_sta:
@@ -831,178 +488,6 @@ drop_unlock_priv:
831 return -1; 488 return -1;
832} 489}
833 490
834static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
835 struct iwl_dma_ptr *ptr, size_t size)
836{
837 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
838 GFP_KERNEL);
839 if (!ptr->addr)
840 return -ENOMEM;
841 ptr->size = size;
842 return 0;
843}
844
845static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
846 struct iwl_dma_ptr *ptr)
847{
848 if (unlikely(!ptr->addr))
849 return;
850
851 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
852 memset(ptr, 0, sizeof(*ptr));
853}
854
855/**
856 * iwlagn_hw_txq_ctx_free - Free TXQ Context
857 *
858 * Destroy all TX DMA queues and structures
859 */
860void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv)
861{
862 int txq_id;
863
864 /* Tx queues */
865 if (priv->txq) {
866 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
867 if (txq_id == priv->cmd_queue)
868 iwl_cmd_queue_free(priv);
869 else
870 iwl_tx_queue_free(priv, txq_id);
871 }
872 iwlagn_free_dma_ptr(priv, &priv->kw);
873
874 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
875
876 /* free tx queue structure */
877 iwl_free_txq_mem(priv);
878}
879
880/**
881 * iwlagn_txq_ctx_alloc - allocate TX queue context
882 * Allocate all Tx DMA structures and initialize them
883 *
884 * @param priv
885 * @return error code
886 */
887int iwlagn_txq_ctx_alloc(struct iwl_priv *priv)
888{
889 int ret;
890 int txq_id, slots_num;
891 unsigned long flags;
892
893 /* Free all tx/cmd queues and keep-warm buffer */
894 iwlagn_hw_txq_ctx_free(priv);
895
896 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
897 priv->hw_params.scd_bc_tbls_size);
898 if (ret) {
899 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
900 goto error_bc_tbls;
901 }
902 /* Alloc keep-warm buffer */
903 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
904 if (ret) {
905 IWL_ERR(priv, "Keep Warm allocation failed\n");
906 goto error_kw;
907 }
908
909 /* allocate tx queue structure */
910 ret = iwl_alloc_txq_mem(priv);
911 if (ret)
912 goto error;
913
914 spin_lock_irqsave(&priv->lock, flags);
915
916 /* Turn off all Tx DMA fifos */
917 iwlagn_txq_set_sched(priv, 0);
918
919 /* Tell NIC where to find the "keep warm" buffer */
920 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
921
922 spin_unlock_irqrestore(&priv->lock, flags);
923
924 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
925 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
926 slots_num = (txq_id == priv->cmd_queue) ?
927 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
928 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
929 txq_id);
930 if (ret) {
931 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
932 goto error;
933 }
934 }
935
936 return ret;
937
938 error:
939 iwlagn_hw_txq_ctx_free(priv);
940 iwlagn_free_dma_ptr(priv, &priv->kw);
941 error_kw:
942 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
943 error_bc_tbls:
944 return ret;
945}
946
947void iwlagn_txq_ctx_reset(struct iwl_priv *priv)
948{
949 int txq_id, slots_num;
950 unsigned long flags;
951
952 spin_lock_irqsave(&priv->lock, flags);
953
954 /* Turn off all Tx DMA fifos */
955 iwlagn_txq_set_sched(priv, 0);
956
957 /* Tell NIC where to find the "keep warm" buffer */
958 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
959
960 spin_unlock_irqrestore(&priv->lock, flags);
961
962 /* Alloc and init all Tx queues, including the command queue (#4) */
963 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
964 slots_num = txq_id == priv->cmd_queue ?
965 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
966 iwl_tx_queue_reset(priv, &priv->txq[txq_id], slots_num, txq_id);
967 }
968}
969
970/**
971 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
972 */
973void iwlagn_txq_ctx_stop(struct iwl_priv *priv)
974{
975 int ch, txq_id;
976 unsigned long flags;
977
978 /* Turn off all Tx DMA fifos */
979 spin_lock_irqsave(&priv->lock, flags);
980
981 iwlagn_txq_set_sched(priv, 0);
982
983 /* Stop each Tx DMA channel, and wait for it to be idle */
984 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
985 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
986 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
987 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
988 1000))
989 IWL_ERR(priv, "Failing on timeout while stopping"
990 " DMA channel %d [0x%08x]", ch,
991 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
992 }
993 spin_unlock_irqrestore(&priv->lock, flags);
994
995 if (!priv->txq)
996 return;
997
998 /* Unmap DMA from host system and free skb's */
999 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1000 if (txq_id == priv->cmd_queue)
1001 iwl_cmd_queue_unmap(priv);
1002 else
1003 iwl_tx_queue_unmap(priv, txq_id);
1004}
1005
1006/* 491/*
1007 * Find first available (lowest unused) Tx Queue, mark it "active". 492 * Find first available (lowest unused) Tx Queue, mark it "active".
1008 * Called only when finding queue for aggregation. 493 * Called only when finding queue for aggregation.
@@ -1033,8 +518,8 @@ int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
1033 if (unlikely(tx_fifo < 0)) 518 if (unlikely(tx_fifo < 0))
1034 return tx_fifo; 519 return tx_fifo;
1035 520
1036 IWL_WARN(priv, "%s on ra = %pM tid = %d\n", 521 IWL_DEBUG_HT(priv, "TX AGG request on ra = %pM tid = %d\n",
1037 __func__, sta->addr, tid); 522 sta->addr, tid);
1038 523
1039 sta_id = iwl_sta_id(sta); 524 sta_id = iwl_sta_id(sta);
1040 if (sta_id == IWL_INVALID_STATION) { 525 if (sta_id == IWL_INVALID_STATION) {
@@ -1150,7 +635,7 @@ int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
1150 * to deactivate the uCode queue, just return "success" to allow 635 * to deactivate the uCode queue, just return "success" to allow
1151 * mac80211 to clean up it own data. 636 * mac80211 to clean up it own data.
1152 */ 637 */
1153 iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo_id); 638 trans_txq_agg_disable(&priv->trans, txq_id, ssn, tx_fifo_id);
1154 spin_unlock_irqrestore(&priv->lock, flags); 639 spin_unlock_irqrestore(&priv->lock, flags);
1155 640
1156 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 641 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
@@ -1179,7 +664,8 @@ int iwlagn_txq_check_empty(struct iwl_priv *priv,
1179 u16 ssn = SEQ_TO_SN(tid_data->seq_number); 664 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1180 int tx_fifo = get_fifo_from_tid(ctx, tid); 665 int tx_fifo = get_fifo_from_tid(ctx, tid);
1181 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n"); 666 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1182 iwlagn_txq_agg_disable(priv, txq_id, ssn, tx_fifo); 667 trans_txq_agg_disable(&priv->trans, txq_id,
668 ssn, tx_fifo);
1183 tid_data->agg.state = IWL_AGG_OFF; 669 tid_data->agg.state = IWL_AGG_OFF;
1184 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid); 670 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1185 } 671 }
@@ -1236,9 +722,9 @@ int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1236 struct ieee80211_hdr *hdr; 722 struct ieee80211_hdr *hdr;
1237 723
1238 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { 724 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1239 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " 725 IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), "
1240 "is out of range [0-%d] %d %d.\n", txq_id, 726 "index %d is out of range [0-%d] %d %d.\n", __func__,
1241 index, q->n_bd, q->write_ptr, q->read_ptr); 727 txq_id, index, q->n_bd, q->write_ptr, q->read_ptr);
1242 return 0; 728 return 0;
1243 } 729 }
1244 730
@@ -1261,7 +747,7 @@ int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1261 747
1262 iwlagn_txq_inval_byte_cnt_tbl(priv, txq); 748 iwlagn_txq_inval_byte_cnt_tbl(priv, txq);
1263 749
1264 iwlagn_txq_free_tfd(priv, txq); 750 iwlagn_txq_free_tfd(priv, txq, txq->q.read_ptr);
1265 } 751 }
1266 return nfreed; 752 return nfreed;
1267} 753}
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
index 97de5d9de67b..a895a099d086 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
@@ -39,38 +39,7 @@
39#include "iwl-agn-hw.h" 39#include "iwl-agn-hw.h"
40#include "iwl-agn.h" 40#include "iwl-agn.h"
41#include "iwl-agn-calib.h" 41#include "iwl-agn-calib.h"
42 42#include "iwl-trans.h"
43#define IWL_AC_UNSET -1
44
45struct queue_to_fifo_ac {
46 s8 fifo, ac;
47};
48
49static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
50 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
51 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
52 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
53 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
54 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
55 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
56 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
57 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
58 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
59 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
60};
61
62static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
63 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
64 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
65 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
66 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
67 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
68 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
69 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
70 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
71 { IWL_TX_FIFO_BE_IPAN, 2, },
72 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
73};
74 43
75static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = { 44static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
76 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP, 45 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
@@ -143,7 +112,7 @@ static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
143 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 112 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
144 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 113 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
145 114
146 IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name); 115 IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
147 ret = wait_event_interruptible_timeout(priv->wait_command_queue, 116 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
148 priv->ucode_write_complete, 5 * HZ); 117 priv->ucode_write_complete, 5 * HZ);
149 if (ret == -ERESTARTSYS) { 118 if (ret == -ERESTARTSYS) {
@@ -183,10 +152,7 @@ static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
183 __le16 *xtal_calib = 152 __le16 *xtal_calib =
184 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL); 153 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
185 154
186 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; 155 iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
187 cmd.hdr.first_group = 0;
188 cmd.hdr.groups_num = 1;
189 cmd.hdr.data_valid = 1;
190 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]); 156 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
191 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]); 157 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
192 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], 158 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
@@ -197,17 +163,16 @@ static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
197{ 163{
198 struct iwl_calib_temperature_offset_cmd cmd; 164 struct iwl_calib_temperature_offset_cmd cmd;
199 __le16 *offset_calib = 165 __le16 *offset_calib =
200 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_TEMPERATURE); 166 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
201 cmd.hdr.op_code = IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD; 167
202 cmd.hdr.first_group = 0; 168 memset(&cmd, 0, sizeof(cmd));
203 cmd.hdr.groups_num = 1; 169 iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
204 cmd.hdr.data_valid = 1; 170 memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(offset_calib));
205 cmd.radio_sensor_offset = le16_to_cpu(offset_calib[1]);
206 if (!(cmd.radio_sensor_offset)) 171 if (!(cmd.radio_sensor_offset))
207 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET; 172 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
208 cmd.reserved = 0; 173
209 IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n", 174 IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
210 cmd.radio_sensor_offset); 175 le16_to_cpu(cmd.radio_sensor_offset));
211 return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET], 176 return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
212 (u8 *)&cmd, sizeof(cmd)); 177 (u8 *)&cmd, sizeof(cmd));
213} 178}
@@ -225,9 +190,10 @@ static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
225 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 190 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
226 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; 191 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
227 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; 192 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
228 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; 193 calib_cfg_cmd.ucd_calib_cfg.flags =
194 IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
229 195
230 return iwl_send_cmd(priv, &cmd); 196 return trans_send_cmd(&priv->trans, &cmd);
231} 197}
232 198
233void iwlagn_rx_calib_result(struct iwl_priv *priv, 199void iwlagn_rx_calib_result(struct iwl_priv *priv,
@@ -325,7 +291,8 @@ static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
325 /* coexistence is disabled */ 291 /* coexistence is disabled */
326 memset(&coex_cmd, 0, sizeof(coex_cmd)); 292 memset(&coex_cmd, 0, sizeof(coex_cmd));
327 } 293 }
328 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, 294 return trans_send_cmd_pdu(&priv->trans,
295 COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
329 sizeof(coex_cmd), &coex_cmd); 296 sizeof(coex_cmd), &coex_cmd);
330} 297}
331 298
@@ -357,7 +324,8 @@ void iwlagn_send_prio_tbl(struct iwl_priv *priv)
357 324
358 memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl, 325 memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
359 sizeof(iwlagn_bt_prio_tbl)); 326 sizeof(iwlagn_bt_prio_tbl));
360 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PRIO_TABLE, 327 if (trans_send_cmd_pdu(&priv->trans,
328 REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
361 sizeof(prio_tbl_cmd), &prio_tbl_cmd)) 329 sizeof(prio_tbl_cmd), &prio_tbl_cmd))
362 IWL_ERR(priv, "failed to send BT prio tbl command\n"); 330 IWL_ERR(priv, "failed to send BT prio tbl command\n");
363} 331}
@@ -369,7 +337,8 @@ int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
369 337
370 env_cmd.action = action; 338 env_cmd.action = action;
371 env_cmd.type = type; 339 env_cmd.type = type;
372 ret = iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PROT_ENV, 340 ret = trans_send_cmd_pdu(&priv->trans,
341 REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
373 sizeof(env_cmd), &env_cmd); 342 sizeof(env_cmd), &env_cmd);
374 if (ret) 343 if (ret)
375 IWL_ERR(priv, "failed to send BT env command\n"); 344 IWL_ERR(priv, "failed to send BT env command\n");
@@ -379,109 +348,9 @@ int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
379 348
380static int iwlagn_alive_notify(struct iwl_priv *priv) 349static int iwlagn_alive_notify(struct iwl_priv *priv)
381{ 350{
382 const struct queue_to_fifo_ac *queue_to_fifo;
383 struct iwl_rxon_context *ctx;
384 u32 a;
385 unsigned long flags;
386 int i, chan;
387 u32 reg_val;
388 int ret; 351 int ret;
389 352
390 spin_lock_irqsave(&priv->lock, flags); 353 trans_tx_start(&priv->trans);
391
392 priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
393 a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET;
394 for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET;
395 a += 4)
396 iwl_write_targ_mem(priv, a, 0);
397 for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET;
398 a += 4)
399 iwl_write_targ_mem(priv, a, 0);
400 for (; a < priv->scd_base_addr +
401 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
402 iwl_write_targ_mem(priv, a, 0);
403
404 iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
405 priv->scd_bc_tbls.dma >> 10);
406
407 /* Enable DMA channel */
408 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
409 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
410 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
411 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
412
413 /* Update FH chicken bits */
414 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
415 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
416 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
417
418 iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
419 IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
420 iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
421
422 /* initiate the queues */
423 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
424 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
425 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
426 iwl_write_targ_mem(priv, priv->scd_base_addr +
427 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
428 iwl_write_targ_mem(priv, priv->scd_base_addr +
429 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
430 sizeof(u32),
431 ((SCD_WIN_SIZE <<
432 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
433 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
434 ((SCD_FRAME_LIMIT <<
435 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
436 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
437 }
438
439 iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
440 IWL_MASK(0, priv->hw_params.max_txq_num));
441
442 /* Activate all Tx DMA/FIFO channels */
443 iwlagn_txq_set_sched(priv, IWL_MASK(0, 7));
444
445 /* map queues to FIFOs */
446 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
447 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
448 else
449 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
450
451 iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
452
453 /* make sure all queue are not stopped */
454 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
455 for (i = 0; i < 4; i++)
456 atomic_set(&priv->queue_stop_count[i], 0);
457 for_each_context(priv, ctx)
458 ctx->last_tx_rejected = false;
459
460 /* reset to 0 to enable all the queue first */
461 priv->txq_ctx_active_msk = 0;
462
463 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
464 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
465
466 for (i = 0; i < 10; i++) {
467 int fifo = queue_to_fifo[i].fifo;
468 int ac = queue_to_fifo[i].ac;
469
470 iwl_txq_ctx_activate(priv, i);
471
472 if (fifo == IWL_TX_FIFO_UNUSED)
473 continue;
474
475 if (ac != IWL_AC_UNSET)
476 iwl_set_swq_id(&priv->txq[i], ac, i);
477 iwlagn_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
478 }
479
480 spin_unlock_irqrestore(&priv->lock, flags);
481
482 /* Enable L1-Active */
483 iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
484 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
485 354
486 ret = iwlagn_send_wimax_coex(priv); 355 ret = iwlagn_send_wimax_coex(priv);
487 if (ret) 356 if (ret)
@@ -508,7 +377,7 @@ static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
508 u32 val; 377 u32 val;
509 u32 i; 378 u32 i;
510 379
511 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); 380 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
512 381
513 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { 382 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
514 /* read data comes through single port, auto-incr addr */ 383 /* read data comes through single port, auto-incr addr */
@@ -533,7 +402,7 @@ static void iwl_print_mismatch_inst(struct iwl_priv *priv,
533 u32 offs; 402 u32 offs;
534 int errors = 0; 403 int errors = 0;
535 404
536 IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len); 405 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
537 406
538 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, 407 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
539 IWLAGN_RTC_INST_LOWER_BOUND); 408 IWLAGN_RTC_INST_LOWER_BOUND);
@@ -559,7 +428,7 @@ static void iwl_print_mismatch_inst(struct iwl_priv *priv,
559static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img) 428static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
560{ 429{
561 if (!iwlcore_verify_inst_sparse(priv, &img->code)) { 430 if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
562 IWL_DEBUG_INFO(priv, "uCode is good in inst SRAM\n"); 431 IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
563 return 0; 432 return 0;
564 } 433 }
565 434
@@ -583,7 +452,7 @@ static void iwlagn_alive_fn(struct iwl_priv *priv,
583 452
584 palive = &pkt->u.alive_frame; 453 palive = &pkt->u.alive_frame;
585 454
586 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " 455 IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
587 "0x%01X 0x%01X\n", 456 "0x%01X 0x%01X\n",
588 palive->is_valid, palive->ver_type, 457 palive->is_valid, palive->ver_type,
589 palive->ver_subtype); 458 palive->ver_subtype);
@@ -602,14 +471,14 @@ static void iwlagn_alive_fn(struct iwl_priv *priv,
602 471
603int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv, 472int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
604 struct fw_img *image, 473 struct fw_img *image,
605 int subtype, int alternate_subtype) 474 enum iwlagn_ucode_type ucode_type)
606{ 475{
607 struct iwl_notification_wait alive_wait; 476 struct iwl_notification_wait alive_wait;
608 struct iwlagn_alive_data alive_data; 477 struct iwlagn_alive_data alive_data;
609 int ret; 478 int ret;
610 enum iwlagn_ucode_subtype old_type; 479 enum iwlagn_ucode_type old_type;
611 480
612 ret = iwlagn_start_device(priv); 481 ret = trans_start_device(&priv->trans);
613 if (ret) 482 if (ret)
614 return ret; 483 return ret;
615 484
@@ -617,7 +486,7 @@ int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
617 iwlagn_alive_fn, &alive_data); 486 iwlagn_alive_fn, &alive_data);
618 487
619 old_type = priv->ucode_type; 488 old_type = priv->ucode_type;
620 priv->ucode_type = subtype; 489 priv->ucode_type = ucode_type;
621 490
622 ret = iwlagn_load_given_ucode(priv, image); 491 ret = iwlagn_load_given_ucode(priv, image);
623 if (ret) { 492 if (ret) {
@@ -626,8 +495,7 @@ int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
626 return ret; 495 return ret;
627 } 496 }
628 497
629 /* Remove all resets to allow NIC to operate */ 498 trans_kick_nic(&priv->trans);
630 iwl_write32(priv, CSR_RESET, 0);
631 499
632 /* 500 /*
633 * Some things may run in the background now, but we 501 * Some things may run in the background now, but we
@@ -645,24 +513,22 @@ int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
645 return -EIO; 513 return -EIO;
646 } 514 }
647 515
648 if (alive_data.subtype != subtype && 516 /*
649 alive_data.subtype != alternate_subtype) { 517 * This step takes a long time (60-80ms!!) and
650 IWL_ERR(priv, 518 * WoWLAN image should be loaded quickly, so
651 "Loaded ucode is not expected type (got %d, expected %d)!\n", 519 * skip it for WoWLAN.
652 alive_data.subtype, subtype); 520 */
653 priv->ucode_type = old_type; 521 if (ucode_type != IWL_UCODE_WOWLAN) {
654 return -EIO; 522 ret = iwl_verify_ucode(priv, image);
655 } 523 if (ret) {
524 priv->ucode_type = old_type;
525 return ret;
526 }
656 527
657 ret = iwl_verify_ucode(priv, image); 528 /* delay a bit to give rfkill time to run */
658 if (ret) { 529 msleep(5);
659 priv->ucode_type = old_type;
660 return ret;
661 } 530 }
662 531
663 /* delay a bit to give rfkill time to run */
664 msleep(5);
665
666 ret = iwlagn_alive_notify(priv); 532 ret = iwlagn_alive_notify(priv);
667 if (ret) { 533 if (ret) {
668 IWL_WARN(priv, 534 IWL_WARN(priv,
@@ -685,7 +551,7 @@ int iwlagn_run_init_ucode(struct iwl_priv *priv)
685 if (!priv->ucode_init.code.len) 551 if (!priv->ucode_init.code.len)
686 return 0; 552 return 0;
687 553
688 if (priv->ucode_type != UCODE_SUBTYPE_NONE_LOADED) 554 if (priv->ucode_type != IWL_UCODE_NONE)
689 return 0; 555 return 0;
690 556
691 iwlagn_init_notification_wait(priv, &calib_wait, 557 iwlagn_init_notification_wait(priv, &calib_wait,
@@ -694,7 +560,7 @@ int iwlagn_run_init_ucode(struct iwl_priv *priv)
694 560
695 /* Will also start the device */ 561 /* Will also start the device */
696 ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init, 562 ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
697 UCODE_SUBTYPE_INIT, -1); 563 IWL_UCODE_INIT);
698 if (ret) 564 if (ret)
699 goto error; 565 goto error;
700 566
@@ -714,6 +580,6 @@ int iwlagn_run_init_ucode(struct iwl_priv *priv)
714 iwlagn_remove_notification(priv, &calib_wait); 580 iwlagn_remove_notification(priv, &calib_wait);
715 out: 581 out:
716 /* Whatever happened, stop the device */ 582 /* Whatever happened, stop the device */
717 iwlagn_stop_device(priv); 583 trans_stop_device(&priv->trans);
718 return ret; 584 return ret;
719} 585}
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index 8e1942ebd9a0..b0ae4de7f083 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -26,14 +26,9 @@
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/kernel.h> 29#include <linux/kernel.h>
33#include <linux/module.h> 30#include <linux/module.h>
34#include <linux/init.h> 31#include <linux/init.h>
35#include <linux/pci.h>
36#include <linux/pci-aspm.h>
37#include <linux/slab.h> 32#include <linux/slab.h>
38#include <linux/dma-mapping.h> 33#include <linux/dma-mapping.h>
39#include <linux/delay.h> 34#include <linux/delay.h>
@@ -49,8 +44,6 @@
49 44
50#include <asm/div64.h> 45#include <asm/div64.h>
51 46
52#define DRV_NAME "iwlagn"
53
54#include "iwl-eeprom.h" 47#include "iwl-eeprom.h"
55#include "iwl-dev.h" 48#include "iwl-dev.h"
56#include "iwl-core.h" 49#include "iwl-core.h"
@@ -59,7 +52,8 @@
59#include "iwl-sta.h" 52#include "iwl-sta.h"
60#include "iwl-agn-calib.h" 53#include "iwl-agn-calib.h"
61#include "iwl-agn.h" 54#include "iwl-agn.h"
62 55#include "iwl-bus.h"
56#include "iwl-trans.h"
63 57
64/****************************************************************************** 58/******************************************************************************
65 * 59 *
@@ -93,12 +87,10 @@ void iwl_update_chain_flags(struct iwl_priv *priv)
93{ 87{
94 struct iwl_rxon_context *ctx; 88 struct iwl_rxon_context *ctx;
95 89
96 if (priv->cfg->ops->hcmd->set_rxon_chain) { 90 for_each_context(priv, ctx) {
97 for_each_context(priv, ctx) { 91 iwlagn_set_rxon_chain(priv, ctx);
98 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); 92 if (ctx->active.rx_chain != ctx->staging.rx_chain)
99 if (ctx->active.rx_chain != ctx->staging.rx_chain) 93 iwlagn_commit_rxon(priv, ctx);
100 iwlcore_commit_rxon(priv, ctx);
101 }
102 } 94 }
103} 95}
104 96
@@ -134,7 +126,9 @@ int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
134 struct iwl_tx_beacon_cmd *tx_beacon_cmd; 126 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
135 struct iwl_host_cmd cmd = { 127 struct iwl_host_cmd cmd = {
136 .id = REPLY_TX_BEACON, 128 .id = REPLY_TX_BEACON,
129 .flags = CMD_SYNC,
137 }; 130 };
131 struct ieee80211_tx_info *info;
138 u32 frame_size; 132 u32 frame_size;
139 u32 rate_flags; 133 u32 rate_flags;
140 u32 rate; 134 u32 rate;
@@ -175,14 +169,31 @@ int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
175 frame_size); 169 frame_size);
176 170
177 /* Set up packet rate and flags */ 171 /* Set up packet rate and flags */
178 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx); 172 info = IEEE80211_SKB_CB(priv->beacon_skb);
173
174 /*
175 * Let's set up the rate at least somewhat correctly;
176 * it will currently not actually be used by the uCode,
177 * it uses the broadcast station's rate instead.
178 */
179 if (info->control.rates[0].idx < 0 ||
180 info->control.rates[0].flags & IEEE80211_TX_RC_MCS)
181 rate = 0;
182 else
183 rate = info->control.rates[0].idx;
184
179 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, 185 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
180 priv->hw_params.valid_tx_ant); 186 priv->hw_params.valid_tx_ant);
181 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); 187 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
182 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) 188
189 /* In mac80211, rates for 5 GHz start at 0 */
190 if (info->band == IEEE80211_BAND_5GHZ)
191 rate += IWL_FIRST_OFDM_RATE;
192 else if (rate >= IWL_FIRST_CCK_RATE && rate <= IWL_LAST_CCK_RATE)
183 rate_flags |= RATE_MCS_CCK_MSK; 193 rate_flags |= RATE_MCS_CCK_MSK;
184 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, 194
185 rate_flags); 195 tx_beacon_cmd->tx.rate_n_flags =
196 iwl_hw_set_rate_n_flags(rate, rate_flags);
186 197
187 /* Submit command */ 198 /* Submit command */
188 cmd.len[0] = sizeof(*tx_beacon_cmd); 199 cmd.len[0] = sizeof(*tx_beacon_cmd);
@@ -192,7 +203,7 @@ int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
192 cmd.data[1] = priv->beacon_skb->data; 203 cmd.data[1] = priv->beacon_skb->data;
193 cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY; 204 cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
194 205
195 return iwl_send_cmd_sync(priv, &cmd); 206 return trans_send_cmd(&priv->trans, &cmd);
196} 207}
197 208
198static void iwl_bg_beacon_update(struct work_struct *work) 209static void iwl_bg_beacon_update(struct work_struct *work)
@@ -245,7 +256,7 @@ static void iwl_bg_bt_runtime_config(struct work_struct *work)
245 /* dont send host command if rf-kill is on */ 256 /* dont send host command if rf-kill is on */
246 if (!iwl_is_ready_rf(priv)) 257 if (!iwl_is_ready_rf(priv))
247 return; 258 return;
248 priv->cfg->ops->hcmd->send_bt_config(priv); 259 iwlagn_send_advance_bt_config(priv);
249} 260}
250 261
251static void iwl_bg_bt_full_concurrency(struct work_struct *work) 262static void iwl_bg_bt_full_concurrency(struct work_struct *work)
@@ -272,12 +283,11 @@ static void iwl_bg_bt_full_concurrency(struct work_struct *work)
272 * to avoid 3-wire collisions 283 * to avoid 3-wire collisions
273 */ 284 */
274 for_each_context(priv, ctx) { 285 for_each_context(priv, ctx) {
275 if (priv->cfg->ops->hcmd->set_rxon_chain) 286 iwlagn_set_rxon_chain(priv, ctx);
276 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); 287 iwlagn_commit_rxon(priv, ctx);
277 iwlcore_commit_rxon(priv, ctx);
278 } 288 }
279 289
280 priv->cfg->ops->hcmd->send_bt_config(priv); 290 iwlagn_send_advance_bt_config(priv);
281out: 291out:
282 mutex_unlock(&priv->mutex); 292 mutex_unlock(&priv->mutex);
283} 293}
@@ -362,7 +372,7 @@ static void iwl_continuous_event_trace(struct iwl_priv *priv)
362 u32 next_entry; /* index of next entry to be written by uCode */ 372 u32 next_entry; /* index of next entry to be written by uCode */
363 373
364 base = priv->device_pointers.error_event_table; 374 base = priv->device_pointers.error_event_table;
365 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { 375 if (iwlagn_hw_valid_rtc_data_addr(base)) {
366 capacity = iwl_read_targ_mem(priv, base); 376 capacity = iwl_read_targ_mem(priv, base);
367 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); 377 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
368 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); 378 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
@@ -440,383 +450,8 @@ static void iwl_bg_tx_flush(struct work_struct *work)
440 if (!iwl_is_ready_rf(priv)) 450 if (!iwl_is_ready_rf(priv))
441 return; 451 return;
442 452
443 if (priv->cfg->ops->lib->txfifo_flush) { 453 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
444 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n"); 454 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
445 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
446 }
447}
448
449/**
450 * iwl_rx_handle - Main entry function for receiving responses from uCode
451 *
452 * Uses the priv->rx_handlers callback function array to invoke
453 * the appropriate handlers, including command responses,
454 * frame-received notifications, and other notifications.
455 */
456static void iwl_rx_handle(struct iwl_priv *priv)
457{
458 struct iwl_rx_mem_buffer *rxb;
459 struct iwl_rx_packet *pkt;
460 struct iwl_rx_queue *rxq = &priv->rxq;
461 u32 r, i;
462 int reclaim;
463 unsigned long flags;
464 u8 fill_rx = 0;
465 u32 count = 8;
466 int total_empty;
467
468 /* uCode's read index (stored in shared DRAM) indicates the last Rx
469 * buffer that the driver may process (last buffer filled by ucode). */
470 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
471 i = rxq->read;
472
473 /* Rx interrupt, but nothing sent from uCode */
474 if (i == r)
475 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
476
477 /* calculate total frames need to be restock after handling RX */
478 total_empty = r - rxq->write_actual;
479 if (total_empty < 0)
480 total_empty += RX_QUEUE_SIZE;
481
482 if (total_empty > (RX_QUEUE_SIZE / 2))
483 fill_rx = 1;
484
485 while (i != r) {
486 int len;
487
488 rxb = rxq->queue[i];
489
490 /* If an RXB doesn't have a Rx queue slot associated with it,
491 * then a bug has been introduced in the queue refilling
492 * routines -- catch it here */
493 if (WARN_ON(rxb == NULL)) {
494 i = (i + 1) & RX_QUEUE_MASK;
495 continue;
496 }
497
498 rxq->queue[i] = NULL;
499
500 pci_unmap_page(priv->pci_dev, rxb->page_dma,
501 PAGE_SIZE << priv->hw_params.rx_page_order,
502 PCI_DMA_FROMDEVICE);
503 pkt = rxb_addr(rxb);
504
505 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
506 len += sizeof(u32); /* account for status word */
507 trace_iwlwifi_dev_rx(priv, pkt, len);
508
509 /* Reclaim a command buffer only if this packet is a response
510 * to a (driver-originated) command.
511 * If the packet (e.g. Rx frame) originated from uCode,
512 * there is no command buffer to reclaim.
513 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
514 * but apparently a few don't get set; catch them here. */
515 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
516 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
517 (pkt->hdr.cmd != REPLY_RX) &&
518 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
519 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
520 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
521 (pkt->hdr.cmd != REPLY_TX);
522
523 /*
524 * Do the notification wait before RX handlers so
525 * even if the RX handler consumes the RXB we have
526 * access to it in the notification wait entry.
527 */
528 if (!list_empty(&priv->_agn.notif_waits)) {
529 struct iwl_notification_wait *w;
530
531 spin_lock(&priv->_agn.notif_wait_lock);
532 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
533 if (w->cmd == pkt->hdr.cmd) {
534 w->triggered = true;
535 if (w->fn)
536 w->fn(priv, pkt, w->fn_data);
537 }
538 }
539 spin_unlock(&priv->_agn.notif_wait_lock);
540
541 wake_up_all(&priv->_agn.notif_waitq);
542 }
543 if (priv->pre_rx_handler)
544 priv->pre_rx_handler(priv, rxb);
545
546 /* Based on type of command response or notification,
547 * handle those that need handling via function in
548 * rx_handlers table. See iwl_setup_rx_handlers() */
549 if (priv->rx_handlers[pkt->hdr.cmd]) {
550 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
551 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
552 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
553 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
554 } else {
555 /* No handling needed */
556 IWL_DEBUG_RX(priv,
557 "r %d i %d No handler needed for %s, 0x%02x\n",
558 r, i, get_cmd_string(pkt->hdr.cmd),
559 pkt->hdr.cmd);
560 }
561
562 /*
563 * XXX: After here, we should always check rxb->page
564 * against NULL before touching it or its virtual
565 * memory (pkt). Because some rx_handler might have
566 * already taken or freed the pages.
567 */
568
569 if (reclaim) {
570 /* Invoke any callbacks, transfer the buffer to caller,
571 * and fire off the (possibly) blocking iwl_send_cmd()
572 * as we reclaim the driver command queue */
573 if (rxb->page)
574 iwl_tx_cmd_complete(priv, rxb);
575 else
576 IWL_WARN(priv, "Claim null rxb?\n");
577 }
578
579 /* Reuse the page if possible. For notification packets and
580 * SKBs that fail to Rx correctly, add them back into the
581 * rx_free list for reuse later. */
582 spin_lock_irqsave(&rxq->lock, flags);
583 if (rxb->page != NULL) {
584 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
585 0, PAGE_SIZE << priv->hw_params.rx_page_order,
586 PCI_DMA_FROMDEVICE);
587 list_add_tail(&rxb->list, &rxq->rx_free);
588 rxq->free_count++;
589 } else
590 list_add_tail(&rxb->list, &rxq->rx_used);
591
592 spin_unlock_irqrestore(&rxq->lock, flags);
593
594 i = (i + 1) & RX_QUEUE_MASK;
595 /* If there are a lot of unused frames,
596 * restock the Rx queue so ucode wont assert. */
597 if (fill_rx) {
598 count++;
599 if (count >= 8) {
600 rxq->read = i;
601 iwlagn_rx_replenish_now(priv);
602 count = 0;
603 }
604 }
605 }
606
607 /* Backtrack one entry */
608 rxq->read = i;
609 if (fill_rx)
610 iwlagn_rx_replenish_now(priv);
611 else
612 iwlagn_rx_queue_restock(priv);
613}
614
615/* tasklet for iwlagn interrupt */
616static void iwl_irq_tasklet(struct iwl_priv *priv)
617{
618 u32 inta = 0;
619 u32 handled = 0;
620 unsigned long flags;
621 u32 i;
622#ifdef CONFIG_IWLWIFI_DEBUG
623 u32 inta_mask;
624#endif
625
626 spin_lock_irqsave(&priv->lock, flags);
627
628 /* Ack/clear/reset pending uCode interrupts.
629 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
630 */
631 /* There is a hardware bug in the interrupt mask function that some
632 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
633 * they are disabled in the CSR_INT_MASK register. Furthermore the
634 * ICT interrupt handling mechanism has another bug that might cause
635 * these unmasked interrupts fail to be detected. We workaround the
636 * hardware bugs here by ACKing all the possible interrupts so that
637 * interrupt coalescing can still be achieved.
638 */
639 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
640
641 inta = priv->_agn.inta;
642
643#ifdef CONFIG_IWLWIFI_DEBUG
644 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
645 /* just for debug */
646 inta_mask = iwl_read32(priv, CSR_INT_MASK);
647 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
648 inta, inta_mask);
649 }
650#endif
651
652 spin_unlock_irqrestore(&priv->lock, flags);
653
654 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
655 priv->_agn.inta = 0;
656
657 /* Now service all interrupt bits discovered above. */
658 if (inta & CSR_INT_BIT_HW_ERR) {
659 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
660
661 /* Tell the device to stop sending interrupts */
662 iwl_disable_interrupts(priv);
663
664 priv->isr_stats.hw++;
665 iwl_irq_handle_error(priv);
666
667 handled |= CSR_INT_BIT_HW_ERR;
668
669 return;
670 }
671
672#ifdef CONFIG_IWLWIFI_DEBUG
673 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
674 /* NIC fires this, but we don't use it, redundant with WAKEUP */
675 if (inta & CSR_INT_BIT_SCD) {
676 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
677 "the frame/frames.\n");
678 priv->isr_stats.sch++;
679 }
680
681 /* Alive notification via Rx interrupt will do the real work */
682 if (inta & CSR_INT_BIT_ALIVE) {
683 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
684 priv->isr_stats.alive++;
685 }
686 }
687#endif
688 /* Safely ignore these bits for debug checks below */
689 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
690
691 /* HW RF KILL switch toggled */
692 if (inta & CSR_INT_BIT_RF_KILL) {
693 int hw_rf_kill = 0;
694 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
695 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
696 hw_rf_kill = 1;
697
698 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
699 hw_rf_kill ? "disable radio" : "enable radio");
700
701 priv->isr_stats.rfkill++;
702
703 /* driver only loads ucode once setting the interface up.
704 * the driver allows loading the ucode even if the radio
705 * is killed. Hence update the killswitch state here. The
706 * rfkill handler will care about restarting if needed.
707 */
708 if (!test_bit(STATUS_ALIVE, &priv->status)) {
709 if (hw_rf_kill)
710 set_bit(STATUS_RF_KILL_HW, &priv->status);
711 else
712 clear_bit(STATUS_RF_KILL_HW, &priv->status);
713 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
714 }
715
716 handled |= CSR_INT_BIT_RF_KILL;
717 }
718
719 /* Chip got too hot and stopped itself */
720 if (inta & CSR_INT_BIT_CT_KILL) {
721 IWL_ERR(priv, "Microcode CT kill error detected.\n");
722 priv->isr_stats.ctkill++;
723 handled |= CSR_INT_BIT_CT_KILL;
724 }
725
726 /* Error detected by uCode */
727 if (inta & CSR_INT_BIT_SW_ERR) {
728 IWL_ERR(priv, "Microcode SW error detected. "
729 " Restarting 0x%X.\n", inta);
730 priv->isr_stats.sw++;
731 iwl_irq_handle_error(priv);
732 handled |= CSR_INT_BIT_SW_ERR;
733 }
734
735 /* uCode wakes up after power-down sleep */
736 if (inta & CSR_INT_BIT_WAKEUP) {
737 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
738 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
739 for (i = 0; i < priv->hw_params.max_txq_num; i++)
740 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
741
742 priv->isr_stats.wakeup++;
743
744 handled |= CSR_INT_BIT_WAKEUP;
745 }
746
747 /* All uCode command responses, including Tx command responses,
748 * Rx "responses" (frame-received notification), and other
749 * notifications from uCode come through here*/
750 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
751 CSR_INT_BIT_RX_PERIODIC)) {
752 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
753 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
754 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
755 iwl_write32(priv, CSR_FH_INT_STATUS,
756 CSR_FH_INT_RX_MASK);
757 }
758 if (inta & CSR_INT_BIT_RX_PERIODIC) {
759 handled |= CSR_INT_BIT_RX_PERIODIC;
760 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
761 }
762 /* Sending RX interrupt require many steps to be done in the
763 * the device:
764 * 1- write interrupt to current index in ICT table.
765 * 2- dma RX frame.
766 * 3- update RX shared data to indicate last write index.
767 * 4- send interrupt.
768 * This could lead to RX race, driver could receive RX interrupt
769 * but the shared data changes does not reflect this;
770 * periodic interrupt will detect any dangling Rx activity.
771 */
772
773 /* Disable periodic interrupt; we use it as just a one-shot. */
774 iwl_write8(priv, CSR_INT_PERIODIC_REG,
775 CSR_INT_PERIODIC_DIS);
776 iwl_rx_handle(priv);
777
778 /*
779 * Enable periodic interrupt in 8 msec only if we received
780 * real RX interrupt (instead of just periodic int), to catch
781 * any dangling Rx interrupt. If it was just the periodic
782 * interrupt, there was no dangling Rx activity, and no need
783 * to extend the periodic interrupt; one-shot is enough.
784 */
785 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
786 iwl_write8(priv, CSR_INT_PERIODIC_REG,
787 CSR_INT_PERIODIC_ENA);
788
789 priv->isr_stats.rx++;
790 }
791
792 /* This "Tx" DMA channel is used only for loading uCode */
793 if (inta & CSR_INT_BIT_FH_TX) {
794 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
795 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
796 priv->isr_stats.tx++;
797 handled |= CSR_INT_BIT_FH_TX;
798 /* Wake up uCode load routine, now that load is complete */
799 priv->ucode_write_complete = 1;
800 wake_up_interruptible(&priv->wait_command_queue);
801 }
802
803 if (inta & ~handled) {
804 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
805 priv->isr_stats.unhandled++;
806 }
807
808 if (inta & ~(priv->inta_mask)) {
809 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
810 inta & ~priv->inta_mask);
811 }
812
813 /* Re-enable all interrupts */
814 /* only Re-enable if disabled by irq */
815 if (test_bit(STATUS_INT_ENABLED, &priv->status))
816 iwl_enable_interrupts(priv);
817 /* Re-enable RF_KILL if it occurred */
818 else if (handled & CSR_INT_BIT_RF_KILL)
819 iwl_enable_rfkill_int(priv);
820} 455}
821 456
822/***************************************************************************** 457/*****************************************************************************
@@ -939,22 +574,29 @@ static struct attribute_group iwl_attribute_group = {
939 * 574 *
940 ******************************************************************************/ 575 ******************************************************************************/
941 576
942static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc) 577static void iwl_free_fw_desc(struct iwl_priv *priv, struct fw_desc *desc)
943{ 578{
944 if (desc->v_addr) 579 if (desc->v_addr)
945 dma_free_coherent(&pci_dev->dev, desc->len, 580 dma_free_coherent(priv->bus->dev, desc->len,
946 desc->v_addr, desc->p_addr); 581 desc->v_addr, desc->p_addr);
947 desc->v_addr = NULL; 582 desc->v_addr = NULL;
948 desc->len = 0; 583 desc->len = 0;
949} 584}
950 585
951static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img) 586static void iwl_free_fw_img(struct iwl_priv *priv, struct fw_img *img)
587{
588 iwl_free_fw_desc(priv, &img->code);
589 iwl_free_fw_desc(priv, &img->data);
590}
591
592static void iwl_dealloc_ucode(struct iwl_priv *priv)
952{ 593{
953 iwl_free_fw_desc(pci_dev, &img->code); 594 iwl_free_fw_img(priv, &priv->ucode_rt);
954 iwl_free_fw_desc(pci_dev, &img->data); 595 iwl_free_fw_img(priv, &priv->ucode_init);
596 iwl_free_fw_img(priv, &priv->ucode_wowlan);
955} 597}
956 598
957static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc, 599static int iwl_alloc_fw_desc(struct iwl_priv *priv, struct fw_desc *desc,
958 const void *data, size_t len) 600 const void *data, size_t len)
959{ 601{
960 if (!len) { 602 if (!len) {
@@ -962,21 +604,16 @@ static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
962 return -EINVAL; 604 return -EINVAL;
963 } 605 }
964 606
965 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len, 607 desc->v_addr = dma_alloc_coherent(priv->bus->dev, len,
966 &desc->p_addr, GFP_KERNEL); 608 &desc->p_addr, GFP_KERNEL);
967 if (!desc->v_addr) 609 if (!desc->v_addr)
968 return -ENOMEM; 610 return -ENOMEM;
611
969 desc->len = len; 612 desc->len = len;
970 memcpy(desc->v_addr, data, len); 613 memcpy(desc->v_addr, data, len);
971 return 0; 614 return 0;
972} 615}
973 616
974static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
975{
976 iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt);
977 iwl_free_fw_img(priv->pci_dev, &priv->ucode_init);
978}
979
980struct iwlagn_ucode_capabilities { 617struct iwlagn_ucode_capabilities {
981 u32 max_probe_length; 618 u32 max_probe_length;
982 u32 standard_phy_calibration_size; 619 u32 standard_phy_calibration_size;
@@ -1021,13 +658,14 @@ static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1021 priv->firmware_name); 658 priv->firmware_name);
1022 659
1023 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, 660 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1024 &priv->pci_dev->dev, GFP_KERNEL, priv, 661 priv->bus->dev,
1025 iwl_ucode_callback); 662 GFP_KERNEL, priv, iwl_ucode_callback);
1026} 663}
1027 664
1028struct iwlagn_firmware_pieces { 665struct iwlagn_firmware_pieces {
1029 const void *inst, *data, *init, *init_data; 666 const void *inst, *data, *init, *init_data, *wowlan_inst, *wowlan_data;
1030 size_t inst_size, data_size, init_size, init_data_size; 667 size_t inst_size, data_size, init_size, init_data_size,
668 wowlan_inst_size, wowlan_data_size;
1031 669
1032 u32 build; 670 u32 build;
1033 671
@@ -1266,6 +904,14 @@ static int iwlagn_load_firmware(struct iwl_priv *priv,
1266 goto invalid_tlv_len; 904 goto invalid_tlv_len;
1267 priv->enhance_sensitivity_table = true; 905 priv->enhance_sensitivity_table = true;
1268 break; 906 break;
907 case IWL_UCODE_TLV_WOWLAN_INST:
908 pieces->wowlan_inst = tlv_data;
909 pieces->wowlan_inst_size = tlv_len;
910 break;
911 case IWL_UCODE_TLV_WOWLAN_DATA:
912 pieces->wowlan_data = tlv_data;
913 pieces->wowlan_data_size = tlv_len;
914 break;
1269 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE: 915 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1270 if (tlv_len != sizeof(u32)) 916 if (tlv_len != sizeof(u32))
1271 goto invalid_tlv_len; 917 goto invalid_tlv_len;
@@ -1443,23 +1089,35 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1443 /* Runtime instructions and 2 copies of data: 1089 /* Runtime instructions and 2 copies of data:
1444 * 1) unmodified from disk 1090 * 1) unmodified from disk
1445 * 2) backup cache for save/restore during power-downs */ 1091 * 2) backup cache for save/restore during power-downs */
1446 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code, 1092 if (iwl_alloc_fw_desc(priv, &priv->ucode_rt.code,
1447 pieces.inst, pieces.inst_size)) 1093 pieces.inst, pieces.inst_size))
1448 goto err_pci_alloc; 1094 goto err_pci_alloc;
1449 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data, 1095 if (iwl_alloc_fw_desc(priv, &priv->ucode_rt.data,
1450 pieces.data, pieces.data_size)) 1096 pieces.data, pieces.data_size))
1451 goto err_pci_alloc; 1097 goto err_pci_alloc;
1452 1098
1453 /* Initialization instructions and data */ 1099 /* Initialization instructions and data */
1454 if (pieces.init_size && pieces.init_data_size) { 1100 if (pieces.init_size && pieces.init_data_size) {
1455 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code, 1101 if (iwl_alloc_fw_desc(priv, &priv->ucode_init.code,
1456 pieces.init, pieces.init_size)) 1102 pieces.init, pieces.init_size))
1457 goto err_pci_alloc; 1103 goto err_pci_alloc;
1458 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data, 1104 if (iwl_alloc_fw_desc(priv, &priv->ucode_init.data,
1459 pieces.init_data, pieces.init_data_size)) 1105 pieces.init_data, pieces.init_data_size))
1460 goto err_pci_alloc; 1106 goto err_pci_alloc;
1461 } 1107 }
1462 1108
1109 /* WoWLAN instructions and data */
1110 if (pieces.wowlan_inst_size && pieces.wowlan_data_size) {
1111 if (iwl_alloc_fw_desc(priv, &priv->ucode_wowlan.code,
1112 pieces.wowlan_inst,
1113 pieces.wowlan_inst_size))
1114 goto err_pci_alloc;
1115 if (iwl_alloc_fw_desc(priv, &priv->ucode_wowlan.data,
1116 pieces.wowlan_data,
1117 pieces.wowlan_data_size))
1118 goto err_pci_alloc;
1119 }
1120
1463 /* Now that we can no longer fail, copy information */ 1121 /* Now that we can no longer fail, copy information */
1464 1122
1465 /* 1123 /*
@@ -1467,25 +1125,26 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1467 * for each event, which is of mode 1 (including timestamp) for all 1125 * for each event, which is of mode 1 (including timestamp) for all
1468 * new microcodes that include this information. 1126 * new microcodes that include this information.
1469 */ 1127 */
1470 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr; 1128 priv->init_evtlog_ptr = pieces.init_evtlog_ptr;
1471 if (pieces.init_evtlog_size) 1129 if (pieces.init_evtlog_size)
1472 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12; 1130 priv->init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1473 else 1131 else
1474 priv->_agn.init_evtlog_size = 1132 priv->init_evtlog_size =
1475 priv->cfg->base_params->max_event_log_size; 1133 priv->cfg->base_params->max_event_log_size;
1476 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr; 1134 priv->init_errlog_ptr = pieces.init_errlog_ptr;
1477 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr; 1135 priv->inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1478 if (pieces.inst_evtlog_size) 1136 if (pieces.inst_evtlog_size)
1479 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12; 1137 priv->inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1480 else 1138 else
1481 priv->_agn.inst_evtlog_size = 1139 priv->inst_evtlog_size =
1482 priv->cfg->base_params->max_event_log_size; 1140 priv->cfg->base_params->max_event_log_size;
1483 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; 1141 priv->inst_errlog_ptr = pieces.inst_errlog_ptr;
1484 1142
1485 priv->new_scan_threshold_behaviour = 1143 priv->new_scan_threshold_behaviour =
1486 !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN); 1144 !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN);
1487 1145
1488 if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) { 1146 if ((priv->cfg->sku & EEPROM_SKU_CAP_IPAN_ENABLE) &&
1147 (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN)) {
1489 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); 1148 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1490 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN; 1149 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1491 } else 1150 } else
@@ -1505,9 +1164,9 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1505 ucode_capa.standard_phy_calibration_size = 1164 ucode_capa.standard_phy_calibration_size =
1506 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE; 1165 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1507 1166
1508 priv->_agn.phy_calib_chain_noise_reset_cmd = 1167 priv->phy_calib_chain_noise_reset_cmd =
1509 ucode_capa.standard_phy_calibration_size; 1168 ucode_capa.standard_phy_calibration_size;
1510 priv->_agn.phy_calib_chain_noise_gain_cmd = 1169 priv->phy_calib_chain_noise_gain_cmd =
1511 ucode_capa.standard_phy_calibration_size + 1; 1170 ucode_capa.standard_phy_calibration_size + 1;
1512 1171
1513 /************************************************** 1172 /**************************************************
@@ -1523,7 +1182,7 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1523 if (err) 1182 if (err)
1524 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); 1183 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1525 1184
1526 err = sysfs_create_group(&priv->pci_dev->dev.kobj, 1185 err = sysfs_create_group(&(priv->bus->dev->kobj),
1527 &iwl_attribute_group); 1186 &iwl_attribute_group);
1528 if (err) { 1187 if (err) {
1529 IWL_ERR(priv, "failed to create sysfs device attributes\n"); 1188 IWL_ERR(priv, "failed to create sysfs device attributes\n");
@@ -1532,7 +1191,7 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1532 1191
1533 /* We have our copies now, allow OS release its copies */ 1192 /* We have our copies now, allow OS release its copies */
1534 release_firmware(ucode_raw); 1193 release_firmware(ucode_raw);
1535 complete(&priv->_agn.firmware_loading_complete); 1194 complete(&priv->firmware_loading_complete);
1536 return; 1195 return;
1537 1196
1538 try_again: 1197 try_again:
@@ -1544,14 +1203,14 @@ static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1544 1203
1545 err_pci_alloc: 1204 err_pci_alloc:
1546 IWL_ERR(priv, "failed to allocate pci memory\n"); 1205 IWL_ERR(priv, "failed to allocate pci memory\n");
1547 iwl_dealloc_ucode_pci(priv); 1206 iwl_dealloc_ucode(priv);
1548 out_unbind: 1207 out_unbind:
1549 complete(&priv->_agn.firmware_loading_complete); 1208 complete(&priv->firmware_loading_complete);
1550 device_release_driver(&priv->pci_dev->dev); 1209 device_release_driver(priv->bus->dev);
1551 release_firmware(ucode_raw); 1210 release_firmware(ucode_raw);
1552} 1211}
1553 1212
1554static const char *desc_lookup_text[] = { 1213static const char * const desc_lookup_text[] = {
1555 "OK", 1214 "OK",
1556 "FAIL", 1215 "FAIL",
1557 "BAD_PARAM", 1216 "BAD_PARAM",
@@ -1575,7 +1234,7 @@ static const char *desc_lookup_text[] = {
1575 "NMI_INTERRUPT_DATA_ACTION_PT", 1234 "NMI_INTERRUPT_DATA_ACTION_PT",
1576 "NMI_TRM_HW_ER", 1235 "NMI_TRM_HW_ER",
1577 "NMI_INTERRUPT_TRM", 1236 "NMI_INTERRUPT_TRM",
1578 "NMI_INTERRUPT_BREAK_POINT" 1237 "NMI_INTERRUPT_BREAK_POINT",
1579 "DEBUG_0", 1238 "DEBUG_0",
1580 "DEBUG_1", 1239 "DEBUG_1",
1581 "DEBUG_2", 1240 "DEBUG_2",
@@ -1626,19 +1285,19 @@ void iwl_dump_nic_error_log(struct iwl_priv *priv)
1626 struct iwl_error_event_table table; 1285 struct iwl_error_event_table table;
1627 1286
1628 base = priv->device_pointers.error_event_table; 1287 base = priv->device_pointers.error_event_table;
1629 if (priv->ucode_type == UCODE_SUBTYPE_INIT) { 1288 if (priv->ucode_type == IWL_UCODE_INIT) {
1630 if (!base) 1289 if (!base)
1631 base = priv->_agn.init_errlog_ptr; 1290 base = priv->init_errlog_ptr;
1632 } else { 1291 } else {
1633 if (!base) 1292 if (!base)
1634 base = priv->_agn.inst_errlog_ptr; 1293 base = priv->inst_errlog_ptr;
1635 } 1294 }
1636 1295
1637 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { 1296 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
1638 IWL_ERR(priv, 1297 IWL_ERR(priv,
1639 "Not valid error log pointer 0x%08X for %s uCode\n", 1298 "Not valid error log pointer 0x%08X for %s uCode\n",
1640 base, 1299 base,
1641 (priv->ucode_type == UCODE_SUBTYPE_INIT) 1300 (priv->ucode_type == IWL_UCODE_INIT)
1642 ? "Init" : "RT"); 1301 ? "Init" : "RT");
1643 return; 1302 return;
1644 } 1303 }
@@ -1702,12 +1361,12 @@ static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1702 return pos; 1361 return pos;
1703 1362
1704 base = priv->device_pointers.log_event_table; 1363 base = priv->device_pointers.log_event_table;
1705 if (priv->ucode_type == UCODE_SUBTYPE_INIT) { 1364 if (priv->ucode_type == IWL_UCODE_INIT) {
1706 if (!base) 1365 if (!base)
1707 base = priv->_agn.init_evtlog_ptr; 1366 base = priv->init_evtlog_ptr;
1708 } else { 1367 } else {
1709 if (!base) 1368 if (!base)
1710 base = priv->_agn.inst_evtlog_ptr; 1369 base = priv->inst_evtlog_ptr;
1711 } 1370 }
1712 1371
1713 if (mode == 0) 1372 if (mode == 0)
@@ -1815,21 +1474,21 @@ int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1815 size_t bufsz = 0; 1474 size_t bufsz = 0;
1816 1475
1817 base = priv->device_pointers.log_event_table; 1476 base = priv->device_pointers.log_event_table;
1818 if (priv->ucode_type == UCODE_SUBTYPE_INIT) { 1477 if (priv->ucode_type == IWL_UCODE_INIT) {
1819 logsize = priv->_agn.init_evtlog_size; 1478 logsize = priv->init_evtlog_size;
1820 if (!base) 1479 if (!base)
1821 base = priv->_agn.init_evtlog_ptr; 1480 base = priv->init_evtlog_ptr;
1822 } else { 1481 } else {
1823 logsize = priv->_agn.inst_evtlog_size; 1482 logsize = priv->inst_evtlog_size;
1824 if (!base) 1483 if (!base)
1825 base = priv->_agn.inst_evtlog_ptr; 1484 base = priv->inst_evtlog_ptr;
1826 } 1485 }
1827 1486
1828 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { 1487 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
1829 IWL_ERR(priv, 1488 IWL_ERR(priv,
1830 "Invalid event log pointer 0x%08X for %s uCode\n", 1489 "Invalid event log pointer 0x%08X for %s uCode\n",
1831 base, 1490 base,
1832 (priv->ucode_type == UCODE_SUBTYPE_INIT) 1491 (priv->ucode_type == IWL_UCODE_INIT)
1833 ? "Init" : "RT"); 1492 ? "Init" : "RT");
1834 return -EINVAL; 1493 return -EINVAL;
1835 } 1494 }
@@ -1928,8 +1587,9 @@ static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1928 adv_cmd.critical_temperature_exit = 1587 adv_cmd.critical_temperature_exit =
1929 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold); 1588 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
1930 1589
1931 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, 1590 ret = trans_send_cmd_pdu(&priv->trans,
1932 sizeof(adv_cmd), &adv_cmd); 1591 REPLY_CT_KILL_CONFIG_CMD,
1592 CMD_SYNC, sizeof(adv_cmd), &adv_cmd);
1933 if (ret) 1593 if (ret)
1934 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); 1594 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1935 else 1595 else
@@ -1943,8 +1603,9 @@ static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1943 cmd.critical_temperature_R = 1603 cmd.critical_temperature_R =
1944 cpu_to_le32(priv->hw_params.ct_kill_threshold); 1604 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1945 1605
1946 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, 1606 ret = trans_send_cmd_pdu(&priv->trans,
1947 sizeof(cmd), &cmd); 1607 REPLY_CT_KILL_CONFIG_CMD,
1608 CMD_SYNC, sizeof(cmd), &cmd);
1948 if (ret) 1609 if (ret)
1949 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); 1610 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1950 else 1611 else
@@ -1968,10 +1629,29 @@ static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
1968 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; 1629 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
1969 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg); 1630 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
1970 1631
1971 return iwl_send_cmd(priv, &cmd); 1632 return trans_send_cmd(&priv->trans, &cmd);
1972} 1633}
1973 1634
1974 1635
1636static int iwlagn_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1637{
1638 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1639 .valid = cpu_to_le32(valid_tx_ant),
1640 };
1641
1642 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1643 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1644 return trans_send_cmd_pdu(&priv->trans,
1645 TX_ANT_CONFIGURATION_CMD,
1646 CMD_SYNC,
1647 sizeof(struct iwl_tx_ant_config_cmd),
1648 &tx_ant_cmd);
1649 } else {
1650 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1651 return -EOPNOTSUPP;
1652 }
1653}
1654
1975/** 1655/**
1976 * iwl_alive_start - called after REPLY_ALIVE notification received 1656 * iwl_alive_start - called after REPLY_ALIVE notification received
1977 * from protocol/runtime uCode (initialization uCode's 1657 * from protocol/runtime uCode (initialization uCode's
@@ -1982,6 +1662,7 @@ int iwl_alive_start(struct iwl_priv *priv)
1982 int ret = 0; 1662 int ret = 0;
1983 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; 1663 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1984 1664
1665 /*TODO: this should go to the transport layer */
1985 iwl_reset_ict(priv); 1666 iwl_reset_ict(priv);
1986 1667
1987 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); 1668 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
@@ -1999,11 +1680,18 @@ int iwl_alive_start(struct iwl_priv *priv)
1999 if (priv->cfg->bt_params && 1680 if (priv->cfg->bt_params &&
2000 priv->cfg->bt_params->advanced_bt_coexist) { 1681 priv->cfg->bt_params->advanced_bt_coexist) {
2001 /* Configure Bluetooth device coexistence support */ 1682 /* Configure Bluetooth device coexistence support */
1683 if (priv->cfg->bt_params->bt_sco_disable)
1684 priv->bt_enable_pspoll = false;
1685 else
1686 priv->bt_enable_pspoll = true;
1687
2002 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; 1688 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2003 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; 1689 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2004 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; 1690 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2005 priv->cfg->ops->hcmd->send_bt_config(priv); 1691 iwlagn_send_advance_bt_config(priv);
2006 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS; 1692 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
1693 priv->cur_rssi_ctx = NULL;
1694
2007 iwlagn_send_prio_tbl(priv); 1695 iwlagn_send_prio_tbl(priv);
2008 1696
2009 /* FIXME: w/a to force change uCode BT state machine */ 1697 /* FIXME: w/a to force change uCode BT state machine */
@@ -2015,7 +1703,13 @@ int iwl_alive_start(struct iwl_priv *priv)
2015 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); 1703 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2016 if (ret) 1704 if (ret)
2017 return ret; 1705 return ret;
1706 } else {
1707 /*
1708 * default is 2-wire BT coexexistence support
1709 */
1710 iwl_send_bt_config(priv);
2018 } 1711 }
1712
2019 if (priv->hw_params.calib_rt_cfg) 1713 if (priv->hw_params.calib_rt_cfg)
2020 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg); 1714 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2021 1715
@@ -2024,10 +1718,9 @@ int iwl_alive_start(struct iwl_priv *priv)
2024 priv->active_rate = IWL_RATES_MASK; 1718 priv->active_rate = IWL_RATES_MASK;
2025 1719
2026 /* Configure Tx antenna selection based on H/W config */ 1720 /* Configure Tx antenna selection based on H/W config */
2027 if (priv->cfg->ops->hcmd->set_tx_ant) 1721 iwlagn_send_tx_ant_config(priv, priv->cfg->valid_tx_ant);
2028 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2029 1722
2030 if (iwl_is_associated_ctx(ctx)) { 1723 if (iwl_is_associated_ctx(ctx) && !priv->wowlan) {
2031 struct iwl_rxon_cmd *active_rxon = 1724 struct iwl_rxon_cmd *active_rxon =
2032 (struct iwl_rxon_cmd *)&ctx->active; 1725 (struct iwl_rxon_cmd *)&ctx->active;
2033 /* apply any changes in staging */ 1726 /* apply any changes in staging */
@@ -2039,24 +1732,18 @@ int iwl_alive_start(struct iwl_priv *priv)
2039 for_each_context(priv, tmp) 1732 for_each_context(priv, tmp)
2040 iwl_connection_init_rx_config(priv, tmp); 1733 iwl_connection_init_rx_config(priv, tmp);
2041 1734
2042 if (priv->cfg->ops->hcmd->set_rxon_chain) 1735 iwlagn_set_rxon_chain(priv, ctx);
2043 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2044 } 1736 }
2045 1737
2046 if (!priv->cfg->bt_params || (priv->cfg->bt_params && 1738 if (!priv->wowlan) {
2047 !priv->cfg->bt_params->advanced_bt_coexist)) { 1739 /* WoWLAN ucode will not reply in the same way, skip it */
2048 /* 1740 iwl_reset_run_time_calib(priv);
2049 * default is 2-wire BT coexexistence support
2050 */
2051 priv->cfg->ops->hcmd->send_bt_config(priv);
2052 } 1741 }
2053 1742
2054 iwl_reset_run_time_calib(priv);
2055
2056 set_bit(STATUS_READY, &priv->status); 1743 set_bit(STATUS_READY, &priv->status);
2057 1744
2058 /* Configure the adapter for unassociated operation */ 1745 /* Configure the adapter for unassociated operation */
2059 ret = iwlcore_commit_rxon(priv, ctx); 1746 ret = iwlagn_commit_rxon(priv, ctx);
2060 if (ret) 1747 if (ret)
2061 return ret; 1748 return ret;
2062 1749
@@ -2090,6 +1777,8 @@ static void __iwl_down(struct iwl_priv *priv)
2090 1777
2091 /* reset BT coex data */ 1778 /* reset BT coex data */
2092 priv->bt_status = 0; 1779 priv->bt_status = 0;
1780 priv->cur_rssi_ctx = NULL;
1781 priv->bt_is_sco = 0;
2093 if (priv->cfg->bt_params) 1782 if (priv->cfg->bt_params)
2094 priv->bt_traffic_load = 1783 priv->bt_traffic_load =
2095 priv->cfg->bt_params->bt_init_traffic_load; 1784 priv->cfg->bt_params->bt_init_traffic_load;
@@ -2116,7 +1805,7 @@ static void __iwl_down(struct iwl_priv *priv)
2116 test_bit(STATUS_EXIT_PENDING, &priv->status) << 1805 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2117 STATUS_EXIT_PENDING; 1806 STATUS_EXIT_PENDING;
2118 1807
2119 iwlagn_stop_device(priv); 1808 trans_stop_device(&priv->trans);
2120 1809
2121 dev_kfree_skb(priv->beacon_skb); 1810 dev_kfree_skb(priv->beacon_skb);
2122 priv->beacon_skb = NULL; 1811 priv->beacon_skb = NULL;
@@ -2131,55 +1820,6 @@ static void iwl_down(struct iwl_priv *priv)
2131 iwl_cancel_deferred_work(priv); 1820 iwl_cancel_deferred_work(priv);
2132} 1821}
2133 1822
2134#define HW_READY_TIMEOUT (50)
2135
2136/* Note: returns poll_bit return value, which is >= 0 if success */
2137static int iwl_set_hw_ready(struct iwl_priv *priv)
2138{
2139 int ret;
2140
2141 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2142 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2143
2144 /* See if we got it */
2145 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2146 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2147 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2148 HW_READY_TIMEOUT);
2149
2150 IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
2151 return ret;
2152}
2153
2154/* Note: returns standard 0/-ERROR code */
2155int iwl_prepare_card_hw(struct iwl_priv *priv)
2156{
2157 int ret;
2158
2159 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2160
2161 ret = iwl_set_hw_ready(priv);
2162 if (ret >= 0)
2163 return 0;
2164
2165 /* If HW is not ready, prepare the conditions to check again */
2166 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2167 CSR_HW_IF_CONFIG_REG_PREPARE);
2168
2169 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2170 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2171 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2172
2173 if (ret < 0)
2174 return ret;
2175
2176 /* HW should be ready by now, check again. */
2177 ret = iwl_set_hw_ready(priv);
2178 if (ret >= 0)
2179 return 0;
2180 return ret;
2181}
2182
2183#define MAX_HW_RESTARTS 5 1823#define MAX_HW_RESTARTS 5
2184 1824
2185static int __iwl_up(struct iwl_priv *priv) 1825static int __iwl_up(struct iwl_priv *priv)
@@ -2210,8 +1850,7 @@ static int __iwl_up(struct iwl_priv *priv)
2210 1850
2211 ret = iwlagn_load_ucode_wait_alive(priv, 1851 ret = iwlagn_load_ucode_wait_alive(priv,
2212 &priv->ucode_rt, 1852 &priv->ucode_rt,
2213 UCODE_SUBTYPE_REGULAR, 1853 IWL_UCODE_REGULAR);
2214 UCODE_SUBTYPE_REGULAR_NEW);
2215 if (ret) { 1854 if (ret) {
2216 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret); 1855 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
2217 goto error; 1856 goto error;
@@ -2266,6 +1905,7 @@ static void iwlagn_prepare_restart(struct iwl_priv *priv)
2266 u8 bt_ci_compliance; 1905 u8 bt_ci_compliance;
2267 u8 bt_load; 1906 u8 bt_load;
2268 u8 bt_status; 1907 u8 bt_status;
1908 bool bt_is_sco;
2269 1909
2270 lockdep_assert_held(&priv->mutex); 1910 lockdep_assert_held(&priv->mutex);
2271 1911
@@ -2286,6 +1926,7 @@ static void iwlagn_prepare_restart(struct iwl_priv *priv)
2286 bt_ci_compliance = priv->bt_ci_compliance; 1926 bt_ci_compliance = priv->bt_ci_compliance;
2287 bt_load = priv->bt_traffic_load; 1927 bt_load = priv->bt_traffic_load;
2288 bt_status = priv->bt_status; 1928 bt_status = priv->bt_status;
1929 bt_is_sco = priv->bt_is_sco;
2289 1930
2290 __iwl_down(priv); 1931 __iwl_down(priv);
2291 1932
@@ -2293,6 +1934,7 @@ static void iwlagn_prepare_restart(struct iwl_priv *priv)
2293 priv->bt_ci_compliance = bt_ci_compliance; 1934 priv->bt_ci_compliance = bt_ci_compliance;
2294 priv->bt_traffic_load = bt_load; 1935 priv->bt_traffic_load = bt_load;
2295 priv->bt_status = bt_status; 1936 priv->bt_status = bt_status;
1937 priv->bt_is_sco = bt_is_sco;
2296} 1938}
2297 1939
2298static void iwl_bg_restart(struct work_struct *data) 1940static void iwl_bg_restart(struct work_struct *data)
@@ -2313,19 +1955,6 @@ static void iwl_bg_restart(struct work_struct *data)
2313 } 1955 }
2314} 1956}
2315 1957
2316static void iwl_bg_rx_replenish(struct work_struct *data)
2317{
2318 struct iwl_priv *priv =
2319 container_of(data, struct iwl_priv, rx_replenish);
2320
2321 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2322 return;
2323
2324 mutex_lock(&priv->mutex);
2325 iwlagn_rx_replenish(priv);
2326 mutex_unlock(&priv->mutex);
2327}
2328
2329static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb, 1958static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2330 struct ieee80211_channel *chan, 1959 struct ieee80211_channel *chan,
2331 enum nl80211_channel_type channel_type, 1960 enum nl80211_channel_type channel_type,
@@ -2360,7 +1989,7 @@ static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2360 1989
2361 /* TODO: queue up if scanning? */ 1990 /* TODO: queue up if scanning? */
2362 if (test_bit(STATUS_SCANNING, &priv->status) || 1991 if (test_bit(STATUS_SCANNING, &priv->status) ||
2363 priv->_agn.offchan_tx_skb) { 1992 priv->offchan_tx_skb) {
2364 ret = -EBUSY; 1993 ret = -EBUSY;
2365 goto out; 1994 goto out;
2366 } 1995 }
@@ -2374,14 +2003,14 @@ static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2374 goto out; 2003 goto out;
2375 } 2004 }
2376 2005
2377 priv->_agn.offchan_tx_skb = skb; 2006 priv->offchan_tx_skb = skb;
2378 priv->_agn.offchan_tx_timeout = wait; 2007 priv->offchan_tx_timeout = wait;
2379 priv->_agn.offchan_tx_chan = chan; 2008 priv->offchan_tx_chan = chan;
2380 2009
2381 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif, 2010 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2382 IWL_SCAN_OFFCH_TX, chan->band); 2011 IWL_SCAN_OFFCH_TX, chan->band);
2383 if (ret) 2012 if (ret)
2384 priv->_agn.offchan_tx_skb = NULL; 2013 priv->offchan_tx_skb = NULL;
2385 out: 2014 out:
2386 mutex_unlock(&priv->mutex); 2015 mutex_unlock(&priv->mutex);
2387 free: 2016 free:
@@ -2398,12 +2027,12 @@ static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2398 2027
2399 mutex_lock(&priv->mutex); 2028 mutex_lock(&priv->mutex);
2400 2029
2401 if (!priv->_agn.offchan_tx_skb) { 2030 if (!priv->offchan_tx_skb) {
2402 ret = -EINVAL; 2031 ret = -EINVAL;
2403 goto unlock; 2032 goto unlock;
2404 } 2033 }
2405 2034
2406 priv->_agn.offchan_tx_skb = NULL; 2035 priv->offchan_tx_skb = NULL;
2407 2036
2408 ret = iwl_scan_cancel_timeout(priv, 200); 2037 ret = iwl_scan_cancel_timeout(priv, 200);
2409 if (ret) 2038 if (ret)
@@ -2420,6 +2049,77 @@ unlock:
2420 * 2049 *
2421 *****************************************************************************/ 2050 *****************************************************************************/
2422 2051
2052static const struct ieee80211_iface_limit iwlagn_sta_ap_limits[] = {
2053 {
2054 .max = 1,
2055 .types = BIT(NL80211_IFTYPE_STATION),
2056 },
2057 {
2058 .max = 1,
2059 .types = BIT(NL80211_IFTYPE_AP),
2060 },
2061};
2062
2063static const struct ieee80211_iface_limit iwlagn_2sta_limits[] = {
2064 {
2065 .max = 2,
2066 .types = BIT(NL80211_IFTYPE_STATION),
2067 },
2068};
2069
2070static const struct ieee80211_iface_limit iwlagn_p2p_sta_go_limits[] = {
2071 {
2072 .max = 1,
2073 .types = BIT(NL80211_IFTYPE_STATION),
2074 },
2075 {
2076 .max = 1,
2077 .types = BIT(NL80211_IFTYPE_P2P_GO) |
2078 BIT(NL80211_IFTYPE_AP),
2079 },
2080};
2081
2082static const struct ieee80211_iface_limit iwlagn_p2p_2sta_limits[] = {
2083 {
2084 .max = 2,
2085 .types = BIT(NL80211_IFTYPE_STATION),
2086 },
2087 {
2088 .max = 1,
2089 .types = BIT(NL80211_IFTYPE_P2P_CLIENT),
2090 },
2091};
2092
2093static const struct ieee80211_iface_combination
2094iwlagn_iface_combinations_dualmode[] = {
2095 { .num_different_channels = 1,
2096 .max_interfaces = 2,
2097 .beacon_int_infra_match = true,
2098 .limits = iwlagn_sta_ap_limits,
2099 .n_limits = ARRAY_SIZE(iwlagn_sta_ap_limits),
2100 },
2101 { .num_different_channels = 1,
2102 .max_interfaces = 2,
2103 .limits = iwlagn_2sta_limits,
2104 .n_limits = ARRAY_SIZE(iwlagn_2sta_limits),
2105 },
2106};
2107
2108static const struct ieee80211_iface_combination
2109iwlagn_iface_combinations_p2p[] = {
2110 { .num_different_channels = 1,
2111 .max_interfaces = 2,
2112 .beacon_int_infra_match = true,
2113 .limits = iwlagn_p2p_sta_go_limits,
2114 .n_limits = ARRAY_SIZE(iwlagn_p2p_sta_go_limits),
2115 },
2116 { .num_different_channels = 1,
2117 .max_interfaces = 2,
2118 .limits = iwlagn_p2p_2sta_limits,
2119 .n_limits = ARRAY_SIZE(iwlagn_p2p_2sta_limits),
2120 },
2121};
2122
2423/* 2123/*
2424 * Not a mac80211 entry point function, but it fits in with all the 2124 * Not a mac80211 entry point function, but it fits in with all the
2425 * other mac80211 functions grouped here. 2125 * other mac80211 functions grouped here.
@@ -2445,7 +2145,7 @@ static int iwl_mac_setup_register(struct iwl_priv *priv,
2445 hw->flags |= IEEE80211_HW_SUPPORTS_PS | 2145 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2446 IEEE80211_HW_SUPPORTS_DYNAMIC_PS; 2146 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2447 2147
2448 if (priv->cfg->sku & IWL_SKU_N) 2148 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
2449 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | 2149 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2450 IEEE80211_HW_SUPPORTS_STATIC_SMPS; 2150 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2451 2151
@@ -2460,17 +2160,45 @@ static int iwl_mac_setup_register(struct iwl_priv *priv,
2460 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes; 2160 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2461 } 2161 }
2462 2162
2163 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
2164
2165 if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT)) {
2166 hw->wiphy->iface_combinations = iwlagn_iface_combinations_p2p;
2167 hw->wiphy->n_iface_combinations =
2168 ARRAY_SIZE(iwlagn_iface_combinations_p2p);
2169 } else if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_AP)) {
2170 hw->wiphy->iface_combinations = iwlagn_iface_combinations_dualmode;
2171 hw->wiphy->n_iface_combinations =
2172 ARRAY_SIZE(iwlagn_iface_combinations_dualmode);
2173 }
2174
2463 hw->wiphy->max_remain_on_channel_duration = 1000; 2175 hw->wiphy->max_remain_on_channel_duration = 1000;
2464 2176
2465 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | 2177 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2466 WIPHY_FLAG_DISABLE_BEACON_HINTS | 2178 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2467 WIPHY_FLAG_IBSS_RSN; 2179 WIPHY_FLAG_IBSS_RSN;
2468 2180
2469 /* 2181 if (priv->ucode_wowlan.code.len && device_can_wakeup(priv->bus->dev)) {
2470 * For now, disable PS by default because it affects 2182 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT |
2471 * RX performance significantly. 2183 WIPHY_WOWLAN_DISCONNECT |
2472 */ 2184 WIPHY_WOWLAN_EAP_IDENTITY_REQ |
2473 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 2185 WIPHY_WOWLAN_RFKILL_RELEASE;
2186 if (!iwlagn_mod_params.sw_crypto)
2187 hw->wiphy->wowlan.flags |=
2188 WIPHY_WOWLAN_SUPPORTS_GTK_REKEY |
2189 WIPHY_WOWLAN_GTK_REKEY_FAILURE;
2190
2191 hw->wiphy->wowlan.n_patterns = IWLAGN_WOWLAN_MAX_PATTERNS;
2192 hw->wiphy->wowlan.pattern_min_len =
2193 IWLAGN_WOWLAN_MIN_PATTERN_LEN;
2194 hw->wiphy->wowlan.pattern_max_len =
2195 IWLAGN_WOWLAN_MAX_PATTERN_LEN;
2196 }
2197
2198 if (iwlagn_mod_params.power_save)
2199 hw->wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
2200 else
2201 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2474 2202
2475 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; 2203 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2476 /* we create the 802.11 header and a zero-length SSID element */ 2204 /* we create the 802.11 header and a zero-length SSID element */
@@ -2551,6 +2279,471 @@ static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2551 IWL_DEBUG_MAC80211(priv, "leave\n"); 2279 IWL_DEBUG_MAC80211(priv, "leave\n");
2552} 2280}
2553 2281
2282#ifdef CONFIG_PM
2283static int iwlagn_send_patterns(struct iwl_priv *priv,
2284 struct cfg80211_wowlan *wowlan)
2285{
2286 struct iwlagn_wowlan_patterns_cmd *pattern_cmd;
2287 struct iwl_host_cmd cmd = {
2288 .id = REPLY_WOWLAN_PATTERNS,
2289 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
2290 .flags = CMD_SYNC,
2291 };
2292 int i, err;
2293
2294 if (!wowlan->n_patterns)
2295 return 0;
2296
2297 cmd.len[0] = sizeof(*pattern_cmd) +
2298 wowlan->n_patterns * sizeof(struct iwlagn_wowlan_pattern);
2299
2300 pattern_cmd = kmalloc(cmd.len[0], GFP_KERNEL);
2301 if (!pattern_cmd)
2302 return -ENOMEM;
2303
2304 pattern_cmd->n_patterns = cpu_to_le32(wowlan->n_patterns);
2305
2306 for (i = 0; i < wowlan->n_patterns; i++) {
2307 int mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2308
2309 memcpy(&pattern_cmd->patterns[i].mask,
2310 wowlan->patterns[i].mask, mask_len);
2311 memcpy(&pattern_cmd->patterns[i].pattern,
2312 wowlan->patterns[i].pattern,
2313 wowlan->patterns[i].pattern_len);
2314 pattern_cmd->patterns[i].mask_size = mask_len;
2315 pattern_cmd->patterns[i].pattern_size =
2316 wowlan->patterns[i].pattern_len;
2317 }
2318
2319 cmd.data[0] = pattern_cmd;
2320 err = trans_send_cmd(&priv->trans, &cmd);
2321 kfree(pattern_cmd);
2322 return err;
2323}
2324#endif
2325
2326static void iwlagn_mac_set_rekey_data(struct ieee80211_hw *hw,
2327 struct ieee80211_vif *vif,
2328 struct cfg80211_gtk_rekey_data *data)
2329{
2330 struct iwl_priv *priv = hw->priv;
2331
2332 if (iwlagn_mod_params.sw_crypto)
2333 return;
2334
2335 mutex_lock(&priv->mutex);
2336
2337 if (priv->contexts[IWL_RXON_CTX_BSS].vif != vif)
2338 goto out;
2339
2340 memcpy(priv->kek, data->kek, NL80211_KEK_LEN);
2341 memcpy(priv->kck, data->kck, NL80211_KCK_LEN);
2342 priv->replay_ctr = cpu_to_le64(be64_to_cpup((__be64 *)&data->replay_ctr));
2343 priv->have_rekey_data = true;
2344
2345 out:
2346 mutex_unlock(&priv->mutex);
2347}
2348
2349struct wowlan_key_data {
2350 struct iwl_rxon_context *ctx;
2351 struct iwlagn_wowlan_rsc_tsc_params_cmd *rsc_tsc;
2352 struct iwlagn_wowlan_tkip_params_cmd *tkip;
2353 const u8 *bssid;
2354 bool error, use_rsc_tsc, use_tkip;
2355};
2356
2357#ifdef CONFIG_PM
2358static void iwlagn_convert_p1k(u16 *p1k, __le16 *out)
2359{
2360 int i;
2361
2362 for (i = 0; i < IWLAGN_P1K_SIZE; i++)
2363 out[i] = cpu_to_le16(p1k[i]);
2364}
2365
2366static void iwlagn_wowlan_program_keys(struct ieee80211_hw *hw,
2367 struct ieee80211_vif *vif,
2368 struct ieee80211_sta *sta,
2369 struct ieee80211_key_conf *key,
2370 void *_data)
2371{
2372 struct iwl_priv *priv = hw->priv;
2373 struct wowlan_key_data *data = _data;
2374 struct iwl_rxon_context *ctx = data->ctx;
2375 struct aes_sc *aes_sc, *aes_tx_sc = NULL;
2376 struct tkip_sc *tkip_sc, *tkip_tx_sc = NULL;
2377 struct iwlagn_p1k_cache *rx_p1ks;
2378 u8 *rx_mic_key;
2379 struct ieee80211_key_seq seq;
2380 u32 cur_rx_iv32 = 0;
2381 u16 p1k[IWLAGN_P1K_SIZE];
2382 int ret, i;
2383
2384 mutex_lock(&priv->mutex);
2385
2386 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2387 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
2388 !sta && !ctx->key_mapping_keys)
2389 ret = iwl_set_default_wep_key(priv, ctx, key);
2390 else
2391 ret = iwl_set_dynamic_key(priv, ctx, key, sta);
2392
2393 if (ret) {
2394 IWL_ERR(priv, "Error setting key during suspend!\n");
2395 data->error = true;
2396 }
2397
2398 switch (key->cipher) {
2399 case WLAN_CIPHER_SUITE_TKIP:
2400 if (sta) {
2401 tkip_sc = data->rsc_tsc->all_tsc_rsc.tkip.unicast_rsc;
2402 tkip_tx_sc = &data->rsc_tsc->all_tsc_rsc.tkip.tsc;
2403
2404 rx_p1ks = data->tkip->rx_uni;
2405
2406 ieee80211_get_key_tx_seq(key, &seq);
2407 tkip_tx_sc->iv16 = cpu_to_le16(seq.tkip.iv16);
2408 tkip_tx_sc->iv32 = cpu_to_le32(seq.tkip.iv32);
2409
2410 ieee80211_get_tkip_p1k_iv(key, seq.tkip.iv32, p1k);
2411 iwlagn_convert_p1k(p1k, data->tkip->tx.p1k);
2412
2413 memcpy(data->tkip->mic_keys.tx,
2414 &key->key[NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY],
2415 IWLAGN_MIC_KEY_SIZE);
2416
2417 rx_mic_key = data->tkip->mic_keys.rx_unicast;
2418 } else {
2419 tkip_sc = data->rsc_tsc->all_tsc_rsc.tkip.multicast_rsc;
2420 rx_p1ks = data->tkip->rx_multi;
2421 rx_mic_key = data->tkip->mic_keys.rx_mcast;
2422 }
2423
2424 /*
2425 * For non-QoS this relies on the fact that both the uCode and
2426 * mac80211 use TID 0 (as they need to to avoid replay attacks)
2427 * for checking the IV in the frames.
2428 */
2429 for (i = 0; i < IWLAGN_NUM_RSC; i++) {
2430 ieee80211_get_key_rx_seq(key, i, &seq);
2431 tkip_sc[i].iv16 = cpu_to_le16(seq.tkip.iv16);
2432 tkip_sc[i].iv32 = cpu_to_le32(seq.tkip.iv32);
2433 /* wrapping isn't allowed, AP must rekey */
2434 if (seq.tkip.iv32 > cur_rx_iv32)
2435 cur_rx_iv32 = seq.tkip.iv32;
2436 }
2437
2438 ieee80211_get_tkip_rx_p1k(key, data->bssid, cur_rx_iv32, p1k);
2439 iwlagn_convert_p1k(p1k, rx_p1ks[0].p1k);
2440 ieee80211_get_tkip_rx_p1k(key, data->bssid,
2441 cur_rx_iv32 + 1, p1k);
2442 iwlagn_convert_p1k(p1k, rx_p1ks[1].p1k);
2443
2444 memcpy(rx_mic_key,
2445 &key->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY],
2446 IWLAGN_MIC_KEY_SIZE);
2447
2448 data->use_tkip = true;
2449 data->use_rsc_tsc = true;
2450 break;
2451 case WLAN_CIPHER_SUITE_CCMP:
2452 if (sta) {
2453 u8 *pn = seq.ccmp.pn;
2454
2455 aes_sc = data->rsc_tsc->all_tsc_rsc.aes.unicast_rsc;
2456 aes_tx_sc = &data->rsc_tsc->all_tsc_rsc.aes.tsc;
2457
2458 ieee80211_get_key_tx_seq(key, &seq);
2459 aes_tx_sc->pn = cpu_to_le64(
2460 (u64)pn[5] |
2461 ((u64)pn[4] << 8) |
2462 ((u64)pn[3] << 16) |
2463 ((u64)pn[2] << 24) |
2464 ((u64)pn[1] << 32) |
2465 ((u64)pn[0] << 40));
2466 } else
2467 aes_sc = data->rsc_tsc->all_tsc_rsc.aes.multicast_rsc;
2468
2469 /*
2470 * For non-QoS this relies on the fact that both the uCode and
2471 * mac80211 use TID 0 for checking the IV in the frames.
2472 */
2473 for (i = 0; i < IWLAGN_NUM_RSC; i++) {
2474 u8 *pn = seq.ccmp.pn;
2475
2476 ieee80211_get_key_rx_seq(key, i, &seq);
2477 aes_sc->pn = cpu_to_le64(
2478 (u64)pn[5] |
2479 ((u64)pn[4] << 8) |
2480 ((u64)pn[3] << 16) |
2481 ((u64)pn[2] << 24) |
2482 ((u64)pn[1] << 32) |
2483 ((u64)pn[0] << 40));
2484 }
2485 data->use_rsc_tsc = true;
2486 break;
2487 }
2488
2489 mutex_unlock(&priv->mutex);
2490}
2491
2492static int iwlagn_mac_suspend(struct ieee80211_hw *hw,
2493 struct cfg80211_wowlan *wowlan)
2494{
2495 struct iwl_priv *priv = hw->priv;
2496 struct iwlagn_wowlan_wakeup_filter_cmd wakeup_filter_cmd;
2497 struct iwl_rxon_cmd rxon;
2498 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2499 struct iwlagn_wowlan_kek_kck_material_cmd kek_kck_cmd;
2500 struct iwlagn_wowlan_tkip_params_cmd tkip_cmd = {};
2501 struct wowlan_key_data key_data = {
2502 .ctx = ctx,
2503 .bssid = ctx->active.bssid_addr,
2504 .use_rsc_tsc = false,
2505 .tkip = &tkip_cmd,
2506 .use_tkip = false,
2507 };
2508 int ret, i;
2509 u16 seq;
2510
2511 if (WARN_ON(!wowlan))
2512 return -EINVAL;
2513
2514 mutex_lock(&priv->mutex);
2515
2516 /* Don't attempt WoWLAN when not associated, tear down instead. */
2517 if (!ctx->vif || ctx->vif->type != NL80211_IFTYPE_STATION ||
2518 !iwl_is_associated_ctx(ctx)) {
2519 ret = 1;
2520 goto out;
2521 }
2522
2523 key_data.rsc_tsc = kzalloc(sizeof(*key_data.rsc_tsc), GFP_KERNEL);
2524 if (!key_data.rsc_tsc) {
2525 ret = -ENOMEM;
2526 goto out;
2527 }
2528
2529 memset(&wakeup_filter_cmd, 0, sizeof(wakeup_filter_cmd));
2530
2531 /*
2532 * We know the last used seqno, and the uCode expects to know that
2533 * one, it will increment before TX.
2534 */
2535 seq = le16_to_cpu(priv->last_seq_ctl) & IEEE80211_SCTL_SEQ;
2536 wakeup_filter_cmd.non_qos_seq = cpu_to_le16(seq);
2537
2538 /*
2539 * For QoS counters, we store the one to use next, so subtract 0x10
2540 * since the uCode will add 0x10 before using the value.
2541 */
2542 for (i = 0; i < 8; i++) {
2543 seq = priv->stations[IWL_AP_ID].tid[i].seq_number;
2544 seq -= 0x10;
2545 wakeup_filter_cmd.qos_seq[i] = cpu_to_le16(seq);
2546 }
2547
2548 if (wowlan->disconnect)
2549 wakeup_filter_cmd.enabled |=
2550 cpu_to_le32(IWLAGN_WOWLAN_WAKEUP_BEACON_MISS |
2551 IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE);
2552 if (wowlan->magic_pkt)
2553 wakeup_filter_cmd.enabled |=
2554 cpu_to_le32(IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET);
2555 if (wowlan->gtk_rekey_failure)
2556 wakeup_filter_cmd.enabled |=
2557 cpu_to_le32(IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL);
2558 if (wowlan->eap_identity_req)
2559 wakeup_filter_cmd.enabled |=
2560 cpu_to_le32(IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ);
2561 if (wowlan->four_way_handshake)
2562 wakeup_filter_cmd.enabled |=
2563 cpu_to_le32(IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE);
2564 if (wowlan->rfkill_release)
2565 wakeup_filter_cmd.enabled |=
2566 cpu_to_le32(IWLAGN_WOWLAN_WAKEUP_RFKILL);
2567 if (wowlan->n_patterns)
2568 wakeup_filter_cmd.enabled |=
2569 cpu_to_le32(IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH);
2570
2571 iwl_scan_cancel_timeout(priv, 200);
2572
2573 memcpy(&rxon, &ctx->active, sizeof(rxon));
2574
2575 trans_stop_device(&priv->trans);
2576
2577 priv->wowlan = true;
2578
2579 ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_wowlan,
2580 IWL_UCODE_WOWLAN);
2581 if (ret)
2582 goto error;
2583
2584 /* now configure WoWLAN ucode */
2585 ret = iwl_alive_start(priv);
2586 if (ret)
2587 goto error;
2588
2589 memcpy(&ctx->staging, &rxon, sizeof(rxon));
2590 ret = iwlagn_commit_rxon(priv, ctx);
2591 if (ret)
2592 goto error;
2593
2594 ret = iwl_power_update_mode(priv, true);
2595 if (ret)
2596 goto error;
2597
2598 if (!iwlagn_mod_params.sw_crypto) {
2599 /* mark all keys clear */
2600 priv->ucode_key_table = 0;
2601 ctx->key_mapping_keys = 0;
2602
2603 /*
2604 * This needs to be unlocked due to lock ordering
2605 * constraints. Since we're in the suspend path
2606 * that isn't really a problem though.
2607 */
2608 mutex_unlock(&priv->mutex);
2609 ieee80211_iter_keys(priv->hw, ctx->vif,
2610 iwlagn_wowlan_program_keys,
2611 &key_data);
2612 mutex_lock(&priv->mutex);
2613 if (key_data.error) {
2614 ret = -EIO;
2615 goto error;
2616 }
2617
2618 if (key_data.use_rsc_tsc) {
2619 struct iwl_host_cmd rsc_tsc_cmd = {
2620 .id = REPLY_WOWLAN_TSC_RSC_PARAMS,
2621 .flags = CMD_SYNC,
2622 .data[0] = key_data.rsc_tsc,
2623 .dataflags[0] = IWL_HCMD_DFL_NOCOPY,
2624 .len[0] = sizeof(*key_data.rsc_tsc),
2625 };
2626
2627 ret = trans_send_cmd(&priv->trans, &rsc_tsc_cmd);
2628 if (ret)
2629 goto error;
2630 }
2631
2632 if (key_data.use_tkip) {
2633 ret = trans_send_cmd_pdu(&priv->trans,
2634 REPLY_WOWLAN_TKIP_PARAMS,
2635 CMD_SYNC, sizeof(tkip_cmd),
2636 &tkip_cmd);
2637 if (ret)
2638 goto error;
2639 }
2640
2641 if (priv->have_rekey_data) {
2642 memset(&kek_kck_cmd, 0, sizeof(kek_kck_cmd));
2643 memcpy(kek_kck_cmd.kck, priv->kck, NL80211_KCK_LEN);
2644 kek_kck_cmd.kck_len = cpu_to_le16(NL80211_KCK_LEN);
2645 memcpy(kek_kck_cmd.kek, priv->kek, NL80211_KEK_LEN);
2646 kek_kck_cmd.kek_len = cpu_to_le16(NL80211_KEK_LEN);
2647 kek_kck_cmd.replay_ctr = priv->replay_ctr;
2648
2649 ret = trans_send_cmd_pdu(&priv->trans,
2650 REPLY_WOWLAN_KEK_KCK_MATERIAL,
2651 CMD_SYNC, sizeof(kek_kck_cmd),
2652 &kek_kck_cmd);
2653 if (ret)
2654 goto error;
2655 }
2656 }
2657
2658 ret = trans_send_cmd_pdu(&priv->trans, REPLY_WOWLAN_WAKEUP_FILTER,
2659 CMD_SYNC, sizeof(wakeup_filter_cmd),
2660 &wakeup_filter_cmd);
2661 if (ret)
2662 goto error;
2663
2664 ret = iwlagn_send_patterns(priv, wowlan);
2665 if (ret)
2666 goto error;
2667
2668 device_set_wakeup_enable(priv->bus->dev, true);
2669
2670 /* Now let the ucode operate on its own */
2671 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
2672 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
2673
2674 goto out;
2675
2676 error:
2677 priv->wowlan = false;
2678 iwlagn_prepare_restart(priv);
2679 ieee80211_restart_hw(priv->hw);
2680 out:
2681 mutex_unlock(&priv->mutex);
2682 kfree(key_data.rsc_tsc);
2683 return ret;
2684}
2685
2686static int iwlagn_mac_resume(struct ieee80211_hw *hw)
2687{
2688 struct iwl_priv *priv = hw->priv;
2689 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2690 struct ieee80211_vif *vif;
2691 unsigned long flags;
2692 u32 base, status = 0xffffffff;
2693 int ret = -EIO;
2694
2695 mutex_lock(&priv->mutex);
2696
2697 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2698 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
2699
2700 base = priv->device_pointers.error_event_table;
2701 if (iwlagn_hw_valid_rtc_data_addr(base)) {
2702 spin_lock_irqsave(&priv->reg_lock, flags);
2703 ret = iwl_grab_nic_access_silent(priv);
2704 if (ret == 0) {
2705 iwl_write32(priv, HBUS_TARG_MEM_RADDR, base);
2706 status = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
2707 iwl_release_nic_access(priv);
2708 }
2709 spin_unlock_irqrestore(&priv->reg_lock, flags);
2710
2711#ifdef CONFIG_IWLWIFI_DEBUGFS
2712 if (ret == 0) {
2713 if (!priv->wowlan_sram)
2714 priv->wowlan_sram =
2715 kzalloc(priv->ucode_wowlan.data.len,
2716 GFP_KERNEL);
2717
2718 if (priv->wowlan_sram)
2719 _iwl_read_targ_mem_words(
2720 priv, 0x800000, priv->wowlan_sram,
2721 priv->ucode_wowlan.data.len / 4);
2722 }
2723#endif
2724 }
2725
2726 /* we'll clear ctx->vif during iwlagn_prepare_restart() */
2727 vif = ctx->vif;
2728
2729 priv->wowlan = false;
2730
2731 device_set_wakeup_enable(priv->bus->dev, false);
2732
2733 iwlagn_prepare_restart(priv);
2734
2735 memset((void *)&ctx->active, 0, sizeof(ctx->active));
2736 iwl_connection_init_rx_config(priv, ctx);
2737 iwlagn_set_rxon_chain(priv, ctx);
2738
2739 mutex_unlock(&priv->mutex);
2740
2741 ieee80211_resume_disconnect(vif);
2742
2743 return 1;
2744}
2745#endif
2746
2554static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 2747static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2555{ 2748{
2556 struct iwl_priv *priv = hw->priv; 2749 struct iwl_priv *priv = hw->priv;
@@ -2573,14 +2766,8 @@ static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2573 u32 iv32, u16 *phase1key) 2766 u32 iv32, u16 *phase1key)
2574{ 2767{
2575 struct iwl_priv *priv = hw->priv; 2768 struct iwl_priv *priv = hw->priv;
2576 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2577
2578 IWL_DEBUG_MAC80211(priv, "enter\n");
2579
2580 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2581 iv32, phase1key);
2582 2769
2583 IWL_DEBUG_MAC80211(priv, "leave\n"); 2770 iwl_update_tkip_key(priv, vif, keyconf, sta, iv32, phase1key);
2584} 2771}
2585 2772
2586static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 2773static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
@@ -2592,7 +2779,6 @@ static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2592 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; 2779 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2593 struct iwl_rxon_context *ctx = vif_priv->ctx; 2780 struct iwl_rxon_context *ctx = vif_priv->ctx;
2594 int ret; 2781 int ret;
2595 u8 sta_id;
2596 bool is_default_wep_key = false; 2782 bool is_default_wep_key = false;
2597 2783
2598 IWL_DEBUG_MAC80211(priv, "enter\n"); 2784 IWL_DEBUG_MAC80211(priv, "enter\n");
@@ -2603,20 +2789,27 @@ static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2603 } 2789 }
2604 2790
2605 /* 2791 /*
2606 * To support IBSS RSN, don't program group keys in IBSS, the 2792 * We could program these keys into the hardware as well, but we
2607 * hardware will then not attempt to decrypt the frames. 2793 * don't expect much multicast traffic in IBSS and having keys
2794 * for more stations is probably more useful.
2795 *
2796 * Mark key TX-only and return 0.
2608 */ 2797 */
2609 if (vif->type == NL80211_IFTYPE_ADHOC && 2798 if (vif->type == NL80211_IFTYPE_ADHOC &&
2610 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 2799 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
2611 return -EOPNOTSUPP; 2800 key->hw_key_idx = WEP_INVALID_OFFSET;
2801 return 0;
2802 }
2612 2803
2613 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta); 2804 /* If they key was TX-only, accept deletion */
2614 if (sta_id == IWL_INVALID_STATION) 2805 if (cmd == DISABLE_KEY && key->hw_key_idx == WEP_INVALID_OFFSET)
2615 return -EINVAL; 2806 return 0;
2616 2807
2617 mutex_lock(&priv->mutex); 2808 mutex_lock(&priv->mutex);
2618 iwl_scan_cancel_timeout(priv, 100); 2809 iwl_scan_cancel_timeout(priv, 100);
2619 2810
2811 BUILD_BUG_ON(WEP_INVALID_OFFSET == IWLAGN_HW_KEY_DEFAULT);
2812
2620 /* 2813 /*
2621 * If we are getting WEP group key and we didn't receive any key mapping 2814 * If we are getting WEP group key and we didn't receive any key mapping
2622 * so far, we are in legacy wep mode (group key only), otherwise we are 2815 * so far, we are in legacy wep mode (group key only), otherwise we are
@@ -2624,22 +2817,30 @@ static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2624 * In legacy wep mode, we use another host command to the uCode. 2817 * In legacy wep mode, we use another host command to the uCode.
2625 */ 2818 */
2626 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || 2819 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2627 key->cipher == WLAN_CIPHER_SUITE_WEP104) && 2820 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) {
2628 !sta) {
2629 if (cmd == SET_KEY) 2821 if (cmd == SET_KEY)
2630 is_default_wep_key = !ctx->key_mapping_keys; 2822 is_default_wep_key = !ctx->key_mapping_keys;
2631 else 2823 else
2632 is_default_wep_key = 2824 is_default_wep_key =
2633 (key->hw_key_idx == HW_KEY_DEFAULT); 2825 key->hw_key_idx == IWLAGN_HW_KEY_DEFAULT;
2634 } 2826 }
2635 2827
2828
2636 switch (cmd) { 2829 switch (cmd) {
2637 case SET_KEY: 2830 case SET_KEY:
2638 if (is_default_wep_key) 2831 if (is_default_wep_key) {
2639 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key); 2832 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
2640 else 2833 break;
2641 ret = iwl_set_dynamic_key(priv, vif_priv->ctx, 2834 }
2642 key, sta_id); 2835 ret = iwl_set_dynamic_key(priv, vif_priv->ctx, key, sta);
2836 if (ret) {
2837 /*
2838 * can't add key for RX, but we don't need it
2839 * in the device for TX so still return 0
2840 */
2841 ret = 0;
2842 key->hw_key_idx = WEP_INVALID_OFFSET;
2843 }
2643 2844
2644 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); 2845 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2645 break; 2846 break;
@@ -2647,7 +2848,7 @@ static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2647 if (is_default_wep_key) 2848 if (is_default_wep_key)
2648 ret = iwl_remove_default_wep_key(priv, ctx, key); 2849 ret = iwl_remove_default_wep_key(priv, ctx, key);
2649 else 2850 else
2650 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id); 2851 ret = iwl_remove_dynamic_key(priv, ctx, key, sta);
2651 2852
2652 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); 2853 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2653 break; 2854 break;
@@ -2674,7 +2875,7 @@ static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2674 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", 2875 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2675 sta->addr, tid); 2876 sta->addr, tid);
2676 2877
2677 if (!(priv->cfg->sku & IWL_SKU_N)) 2878 if (!(priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE))
2678 return -EACCES; 2879 return -EACCES;
2679 2880
2680 mutex_lock(&priv->mutex); 2881 mutex_lock(&priv->mutex);
@@ -2694,29 +2895,26 @@ static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2694 IWL_DEBUG_HT(priv, "start Tx\n"); 2895 IWL_DEBUG_HT(priv, "start Tx\n");
2695 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn); 2896 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
2696 if (ret == 0) { 2897 if (ret == 0) {
2697 priv->_agn.agg_tids_count++; 2898 priv->agg_tids_count++;
2698 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", 2899 IWL_DEBUG_HT(priv, "priv->agg_tids_count = %u\n",
2699 priv->_agn.agg_tids_count); 2900 priv->agg_tids_count);
2700 } 2901 }
2701 break; 2902 break;
2702 case IEEE80211_AMPDU_TX_STOP: 2903 case IEEE80211_AMPDU_TX_STOP:
2703 IWL_DEBUG_HT(priv, "stop Tx\n"); 2904 IWL_DEBUG_HT(priv, "stop Tx\n");
2704 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid); 2905 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
2705 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { 2906 if ((ret == 0) && (priv->agg_tids_count > 0)) {
2706 priv->_agn.agg_tids_count--; 2907 priv->agg_tids_count--;
2707 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", 2908 IWL_DEBUG_HT(priv, "priv->agg_tids_count = %u\n",
2708 priv->_agn.agg_tids_count); 2909 priv->agg_tids_count);
2709 } 2910 }
2710 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 2911 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2711 ret = 0; 2912 ret = 0;
2712 if (priv->cfg->ht_params && 2913 if (priv->cfg->ht_params &&
2713 priv->cfg->ht_params->use_rts_for_aggregation) { 2914 priv->cfg->ht_params->use_rts_for_aggregation) {
2714 struct iwl_station_priv *sta_priv =
2715 (void *) sta->drv_priv;
2716 /* 2915 /*
2717 * switch off RTS/CTS if it was previously enabled 2916 * switch off RTS/CTS if it was previously enabled
2718 */ 2917 */
2719
2720 sta_priv->lq_sta.lq.general_params.flags &= 2918 sta_priv->lq_sta.lq.general_params.flags &=
2721 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; 2919 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2722 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), 2920 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
@@ -2726,7 +2924,8 @@ static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2726 case IEEE80211_AMPDU_TX_OPERATIONAL: 2924 case IEEE80211_AMPDU_TX_OPERATIONAL:
2727 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF); 2925 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
2728 2926
2729 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size); 2927 trans_txq_agg_setup(&priv->trans, iwl_sta_id(sta), tid,
2928 buf_size);
2730 2929
2731 /* 2930 /*
2732 * If the limit is 0, then it wasn't initialised yet, 2931 * If the limit is 0, then it wasn't initialised yet,
@@ -2764,6 +2963,9 @@ static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2764 2963
2765 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), 2964 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2766 &sta_priv->lq_sta.lq, CMD_ASYNC, false); 2965 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
2966
2967 IWL_INFO(priv, "Tx aggregation enabled on ra = %pM tid = %d\n",
2968 sta->addr, tid);
2767 ret = 0; 2969 ret = 0;
2768 break; 2970 break;
2769 } 2971 }
@@ -2833,7 +3035,6 @@ static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
2833 */ 3035 */
2834 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; 3036 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2835 u16 ch; 3037 u16 ch;
2836 unsigned long flags = 0;
2837 3038
2838 IWL_DEBUG_MAC80211(priv, "enter\n"); 3039 IWL_DEBUG_MAC80211(priv, "enter\n");
2839 3040
@@ -2850,65 +3051,64 @@ static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
2850 if (!iwl_is_associated_ctx(ctx)) 3051 if (!iwl_is_associated_ctx(ctx))
2851 goto out; 3052 goto out;
2852 3053
2853 if (priv->cfg->ops->lib->set_channel_switch) { 3054 if (!priv->cfg->lib->set_channel_switch)
3055 goto out;
2854 3056
2855 ch = channel->hw_value; 3057 ch = channel->hw_value;
2856 if (le16_to_cpu(ctx->active.channel) != ch) { 3058 if (le16_to_cpu(ctx->active.channel) == ch)
2857 ch_info = iwl_get_channel_info(priv, 3059 goto out;
2858 channel->band, 3060
2859 ch); 3061 ch_info = iwl_get_channel_info(priv, channel->band, ch);
2860 if (!is_channel_valid(ch_info)) { 3062 if (!is_channel_valid(ch_info)) {
2861 IWL_DEBUG_MAC80211(priv, "invalid channel\n"); 3063 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
2862 goto out; 3064 goto out;
2863 } 3065 }
2864 spin_lock_irqsave(&priv->lock, flags); 3066
2865 3067 spin_lock_irq(&priv->lock);
2866 priv->current_ht_config.smps = conf->smps_mode; 3068
2867 3069 priv->current_ht_config.smps = conf->smps_mode;
2868 /* Configure HT40 channels */ 3070
2869 ctx->ht.enabled = conf_is_ht(conf); 3071 /* Configure HT40 channels */
2870 if (ctx->ht.enabled) { 3072 ctx->ht.enabled = conf_is_ht(conf);
2871 if (conf_is_ht40_minus(conf)) { 3073 if (ctx->ht.enabled) {
2872 ctx->ht.extension_chan_offset = 3074 if (conf_is_ht40_minus(conf)) {
2873 IEEE80211_HT_PARAM_CHA_SEC_BELOW; 3075 ctx->ht.extension_chan_offset =
2874 ctx->ht.is_40mhz = true; 3076 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2875 } else if (conf_is_ht40_plus(conf)) { 3077 ctx->ht.is_40mhz = true;
2876 ctx->ht.extension_chan_offset = 3078 } else if (conf_is_ht40_plus(conf)) {
2877 IEEE80211_HT_PARAM_CHA_SEC_ABOVE; 3079 ctx->ht.extension_chan_offset =
2878 ctx->ht.is_40mhz = true; 3080 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2879 } else { 3081 ctx->ht.is_40mhz = true;
2880 ctx->ht.extension_chan_offset = 3082 } else {
2881 IEEE80211_HT_PARAM_CHA_SEC_NONE; 3083 ctx->ht.extension_chan_offset =
2882 ctx->ht.is_40mhz = false; 3084 IEEE80211_HT_PARAM_CHA_SEC_NONE;
2883 } 3085 ctx->ht.is_40mhz = false;
2884 } else
2885 ctx->ht.is_40mhz = false;
2886
2887 if ((le16_to_cpu(ctx->staging.channel) != ch))
2888 ctx->staging.flags = 0;
2889
2890 iwl_set_rxon_channel(priv, channel, ctx);
2891 iwl_set_rxon_ht(priv, ht_conf);
2892 iwl_set_flags_for_band(priv, ctx, channel->band,
2893 ctx->vif);
2894 spin_unlock_irqrestore(&priv->lock, flags);
2895
2896 iwl_set_rate(priv);
2897 /*
2898 * at this point, staging_rxon has the
2899 * configuration for channel switch
2900 */
2901 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
2902 priv->switch_channel = cpu_to_le16(ch);
2903 if (priv->cfg->ops->lib->set_channel_switch(priv,
2904 ch_switch)) {
2905 clear_bit(STATUS_CHANNEL_SWITCH_PENDING,
2906 &priv->status);
2907 priv->switch_channel = 0;
2908 ieee80211_chswitch_done(ctx->vif, false);
2909 }
2910 } 3086 }
3087 } else
3088 ctx->ht.is_40mhz = false;
3089
3090 if ((le16_to_cpu(ctx->staging.channel) != ch))
3091 ctx->staging.flags = 0;
3092
3093 iwl_set_rxon_channel(priv, channel, ctx);
3094 iwl_set_rxon_ht(priv, ht_conf);
3095 iwl_set_flags_for_band(priv, ctx, channel->band, ctx->vif);
3096
3097 spin_unlock_irq(&priv->lock);
3098
3099 iwl_set_rate(priv);
3100 /*
3101 * at this point, staging_rxon has the
3102 * configuration for channel switch
3103 */
3104 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
3105 priv->switch_channel = cpu_to_le16(ch);
3106 if (priv->cfg->lib->set_channel_switch(priv, ch_switch)) {
3107 clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
3108 priv->switch_channel = 0;
3109 ieee80211_chswitch_done(ctx->vif, false);
2911 } 3110 }
3111
2912out: 3112out:
2913 mutex_unlock(&priv->mutex); 3113 mutex_unlock(&priv->mutex);
2914 IWL_DEBUG_MAC80211(priv, "leave\n"); 3114 IWL_DEBUG_MAC80211(priv, "leave\n");
@@ -2971,10 +3171,6 @@ static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
2971 mutex_lock(&priv->mutex); 3171 mutex_lock(&priv->mutex);
2972 IWL_DEBUG_MAC80211(priv, "enter\n"); 3172 IWL_DEBUG_MAC80211(priv, "enter\n");
2973 3173
2974 /* do not support "flush" */
2975 if (!priv->cfg->ops->lib->txfifo_flush)
2976 goto done;
2977
2978 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { 3174 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2979 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n"); 3175 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
2980 goto done; 3176 goto done;
@@ -2990,7 +3186,7 @@ static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
2990 */ 3186 */
2991 if (drop) { 3187 if (drop) {
2992 IWL_DEBUG_MAC80211(priv, "send flush command\n"); 3188 IWL_DEBUG_MAC80211(priv, "send flush command\n");
2993 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) { 3189 if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
2994 IWL_ERR(priv, "flush request fail\n"); 3190 IWL_ERR(priv, "flush request fail\n");
2995 goto done; 3191 goto done;
2996 } 3192 }
@@ -3017,9 +3213,9 @@ static void iwlagn_disable_roc(struct iwl_priv *priv)
3017 iwl_set_rxon_channel(priv, chan, ctx); 3213 iwl_set_rxon_channel(priv, chan, ctx);
3018 iwl_set_flags_for_band(priv, ctx, chan->band, NULL); 3214 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3019 3215
3020 priv->_agn.hw_roc_channel = NULL; 3216 priv->hw_roc_channel = NULL;
3021 3217
3022 iwlcore_commit_rxon(priv, ctx); 3218 iwlagn_commit_rxon(priv, ctx);
3023 3219
3024 ctx->is_active = false; 3220 ctx->is_active = false;
3025} 3221}
@@ -3027,7 +3223,7 @@ static void iwlagn_disable_roc(struct iwl_priv *priv)
3027static void iwlagn_bg_roc_done(struct work_struct *work) 3223static void iwlagn_bg_roc_done(struct work_struct *work)
3028{ 3224{
3029 struct iwl_priv *priv = container_of(work, struct iwl_priv, 3225 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3030 _agn.hw_roc_work.work); 3226 hw_roc_work.work);
3031 3227
3032 mutex_lock(&priv->mutex); 3228 mutex_lock(&priv->mutex);
3033 ieee80211_remain_on_channel_expired(priv->hw); 3229 ieee80211_remain_on_channel_expired(priv->hw);
@@ -3059,11 +3255,11 @@ static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3059 } 3255 }
3060 3256
3061 priv->contexts[IWL_RXON_CTX_PAN].is_active = true; 3257 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3062 priv->_agn.hw_roc_channel = channel; 3258 priv->hw_roc_channel = channel;
3063 priv->_agn.hw_roc_chantype = channel_type; 3259 priv->hw_roc_chantype = channel_type;
3064 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024); 3260 priv->hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3065 iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]); 3261 iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3066 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work, 3262 queue_delayed_work(priv->workqueue, &priv->hw_roc_work,
3067 msecs_to_jiffies(duration + 20)); 3263 msecs_to_jiffies(duration + 20));
3068 3264
3069 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */ 3265 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
@@ -3082,7 +3278,7 @@ static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3082 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) 3278 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3083 return -EOPNOTSUPP; 3279 return -EOPNOTSUPP;
3084 3280
3085 cancel_delayed_work_sync(&priv->_agn.hw_roc_work); 3281 cancel_delayed_work_sync(&priv->hw_roc_work);
3086 3282
3087 mutex_lock(&priv->mutex); 3283 mutex_lock(&priv->mutex);
3088 iwlagn_disable_roc(priv); 3284 iwlagn_disable_roc(priv);
@@ -3104,18 +3300,17 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv)
3104 init_waitqueue_head(&priv->wait_command_queue); 3300 init_waitqueue_head(&priv->wait_command_queue);
3105 3301
3106 INIT_WORK(&priv->restart, iwl_bg_restart); 3302 INIT_WORK(&priv->restart, iwl_bg_restart);
3107 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3108 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); 3303 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3109 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); 3304 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3110 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush); 3305 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3111 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency); 3306 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3112 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config); 3307 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3113 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done); 3308 INIT_DELAYED_WORK(&priv->hw_roc_work, iwlagn_bg_roc_done);
3114 3309
3115 iwl_setup_scan_deferred_work(priv); 3310 iwl_setup_scan_deferred_work(priv);
3116 3311
3117 if (priv->cfg->ops->lib->setup_deferred_work) 3312 if (priv->cfg->lib->bt_setup_deferred_work)
3118 priv->cfg->ops->lib->setup_deferred_work(priv); 3313 priv->cfg->lib->bt_setup_deferred_work(priv);
3119 3314
3120 init_timer(&priv->statistics_periodic); 3315 init_timer(&priv->statistics_periodic);
3121 priv->statistics_periodic.data = (unsigned long)priv; 3316 priv->statistics_periodic.data = (unsigned long)priv;
@@ -3128,15 +3323,12 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv)
3128 init_timer(&priv->watchdog); 3323 init_timer(&priv->watchdog);
3129 priv->watchdog.data = (unsigned long)priv; 3324 priv->watchdog.data = (unsigned long)priv;
3130 priv->watchdog.function = iwl_bg_watchdog; 3325 priv->watchdog.function = iwl_bg_watchdog;
3131
3132 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3133 iwl_irq_tasklet, (unsigned long)priv);
3134} 3326}
3135 3327
3136static void iwl_cancel_deferred_work(struct iwl_priv *priv) 3328static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3137{ 3329{
3138 if (priv->cfg->ops->lib->cancel_deferred_work) 3330 if (priv->cfg->lib->cancel_deferred_work)
3139 priv->cfg->ops->lib->cancel_deferred_work(priv); 3331 priv->cfg->lib->cancel_deferred_work(priv);
3140 3332
3141 cancel_work_sync(&priv->run_time_calib_work); 3333 cancel_work_sync(&priv->run_time_calib_work);
3142 cancel_work_sync(&priv->beacon_update); 3334 cancel_work_sync(&priv->beacon_update);
@@ -3187,7 +3379,7 @@ static int iwl_init_drv(struct iwl_priv *priv)
3187 priv->iw_mode = NL80211_IFTYPE_STATION; 3379 priv->iw_mode = NL80211_IFTYPE_STATION;
3188 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; 3380 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3189 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; 3381 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3190 priv->_agn.agg_tids_count = 0; 3382 priv->agg_tids_count = 0;
3191 3383
3192 /* initialize force reset */ 3384 /* initialize force reset */
3193 priv->force_reset[IWL_RF_RESET].reset_duration = 3385 priv->force_reset[IWL_RF_RESET].reset_duration =
@@ -3198,9 +3390,7 @@ static int iwl_init_drv(struct iwl_priv *priv)
3198 priv->rx_statistics_jiffies = jiffies; 3390 priv->rx_statistics_jiffies = jiffies;
3199 3391
3200 /* Choose which receivers/antennas to use */ 3392 /* Choose which receivers/antennas to use */
3201 if (priv->cfg->ops->hcmd->set_rxon_chain) 3393 iwlagn_set_rxon_chain(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
3202 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3203 &priv->contexts[IWL_RXON_CTX_BSS]);
3204 3394
3205 iwl_init_scan_params(priv); 3395 iwl_init_scan_params(priv);
3206 3396
@@ -3243,12 +3433,42 @@ static void iwl_uninit_drv(struct iwl_priv *priv)
3243 iwl_free_channel_map(priv); 3433 iwl_free_channel_map(priv);
3244 kfree(priv->scan_cmd); 3434 kfree(priv->scan_cmd);
3245 kfree(priv->beacon_cmd); 3435 kfree(priv->beacon_cmd);
3436#ifdef CONFIG_IWLWIFI_DEBUGFS
3437 kfree(priv->wowlan_sram);
3438#endif
3439}
3440
3441static void iwl_mac_rssi_callback(struct ieee80211_hw *hw,
3442 enum ieee80211_rssi_event rssi_event)
3443{
3444 struct iwl_priv *priv = hw->priv;
3445
3446 mutex_lock(&priv->mutex);
3447
3448 if (priv->cfg->bt_params &&
3449 priv->cfg->bt_params->advanced_bt_coexist) {
3450 if (rssi_event == RSSI_EVENT_LOW)
3451 priv->bt_enable_pspoll = true;
3452 else if (rssi_event == RSSI_EVENT_HIGH)
3453 priv->bt_enable_pspoll = false;
3454
3455 iwlagn_send_advance_bt_config(priv);
3456 } else {
3457 IWL_DEBUG_MAC80211(priv, "Advanced BT coex disabled,"
3458 "ignoring RSSI callback\n");
3459 }
3460
3461 mutex_unlock(&priv->mutex);
3246} 3462}
3247 3463
3248struct ieee80211_ops iwlagn_hw_ops = { 3464struct ieee80211_ops iwlagn_hw_ops = {
3249 .tx = iwlagn_mac_tx, 3465 .tx = iwlagn_mac_tx,
3250 .start = iwlagn_mac_start, 3466 .start = iwlagn_mac_start,
3251 .stop = iwlagn_mac_stop, 3467 .stop = iwlagn_mac_stop,
3468#ifdef CONFIG_PM
3469 .suspend = iwlagn_mac_suspend,
3470 .resume = iwlagn_mac_resume,
3471#endif
3252 .add_interface = iwl_mac_add_interface, 3472 .add_interface = iwl_mac_add_interface,
3253 .remove_interface = iwl_mac_remove_interface, 3473 .remove_interface = iwl_mac_remove_interface,
3254 .change_interface = iwl_mac_change_interface, 3474 .change_interface = iwl_mac_change_interface,
@@ -3256,6 +3476,7 @@ struct ieee80211_ops iwlagn_hw_ops = {
3256 .configure_filter = iwlagn_configure_filter, 3476 .configure_filter = iwlagn_configure_filter,
3257 .set_key = iwlagn_mac_set_key, 3477 .set_key = iwlagn_mac_set_key,
3258 .update_tkip_key = iwlagn_mac_update_tkip_key, 3478 .update_tkip_key = iwlagn_mac_update_tkip_key,
3479 .set_rekey_data = iwlagn_mac_set_rekey_data,
3259 .conf_tx = iwl_mac_conf_tx, 3480 .conf_tx = iwl_mac_conf_tx,
3260 .bss_info_changed = iwlagn_bss_info_changed, 3481 .bss_info_changed = iwlagn_bss_info_changed,
3261 .ampdu_action = iwlagn_mac_ampdu_action, 3482 .ampdu_action = iwlagn_mac_ampdu_action,
@@ -3270,15 +3491,13 @@ struct ieee80211_ops iwlagn_hw_ops = {
3270 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel, 3491 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3271 .offchannel_tx = iwl_mac_offchannel_tx, 3492 .offchannel_tx = iwl_mac_offchannel_tx,
3272 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait, 3493 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3494 .rssi_callback = iwl_mac_rssi_callback,
3273 CFG80211_TESTMODE_CMD(iwl_testmode_cmd) 3495 CFG80211_TESTMODE_CMD(iwl_testmode_cmd)
3496 CFG80211_TESTMODE_DUMP(iwl_testmode_dump)
3274}; 3497};
3275 3498
3276static u32 iwl_hw_detect(struct iwl_priv *priv) 3499static u32 iwl_hw_detect(struct iwl_priv *priv)
3277{ 3500{
3278 u8 rev_id;
3279
3280 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3281 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3282 return iwl_read32(priv, CSR_HW_REV); 3501 return iwl_read32(priv, CSR_HW_REV);
3283} 3502}
3284 3503
@@ -3294,10 +3513,10 @@ static int iwl_set_hw_params(struct iwl_priv *priv)
3294 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL; 3513 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3295 3514
3296 if (iwlagn_mod_params.disable_11n) 3515 if (iwlagn_mod_params.disable_11n)
3297 priv->cfg->sku &= ~IWL_SKU_N; 3516 priv->cfg->sku &= ~EEPROM_SKU_CAP_11N_ENABLE;
3298 3517
3299 /* Device-specific setup */ 3518 /* Device-specific setup */
3300 return priv->cfg->ops->lib->set_hw_params(priv); 3519 return priv->cfg->lib->set_hw_params(priv);
3301} 3520}
3302 3521
3303static const u8 iwlagn_bss_ac_to_fifo[] = { 3522static const u8 iwlagn_bss_ac_to_fifo[] = {
@@ -3344,29 +3563,9 @@ out:
3344 return hw; 3563 return hw;
3345} 3564}
3346 3565
3347static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3566static void iwl_init_context(struct iwl_priv *priv)
3348{ 3567{
3349 int err = 0, i; 3568 int i;
3350 struct iwl_priv *priv;
3351 struct ieee80211_hw *hw;
3352 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3353 unsigned long flags;
3354 u16 pci_cmd, num_mac;
3355 u32 hw_rev;
3356
3357 /************************
3358 * 1. Allocating HW data
3359 ************************/
3360
3361 hw = iwl_alloc_all(cfg);
3362 if (!hw) {
3363 err = -ENOMEM;
3364 goto out;
3365 }
3366 priv = hw->priv;
3367 /* At this point both hw and priv are allocated. */
3368
3369 priv->ucode_type = UCODE_SUBTYPE_NONE_LOADED;
3370 3569
3371 /* 3570 /*
3372 * The default context is always valid, 3571 * The default context is always valid,
@@ -3398,8 +3597,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3398 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS; 3597 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3399 3598
3400 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON; 3599 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3401 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING; 3600 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd =
3402 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC; 3601 REPLY_WIPAN_RXON_TIMING;
3602 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd =
3603 REPLY_WIPAN_RXON_ASSOC;
3403 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM; 3604 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3404 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN; 3605 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3405 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY; 3606 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
@@ -3419,12 +3620,35 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3419 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P; 3620 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3420 3621
3421 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); 3622 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3623}
3422 3624
3423 SET_IEEE80211_DEV(hw, &pdev->dev); 3625int iwl_probe(struct iwl_bus *bus, struct iwl_cfg *cfg)
3626{
3627 int err = 0;
3628 struct iwl_priv *priv;
3629 struct ieee80211_hw *hw;
3630 u16 num_mac;
3631 u32 hw_rev;
3632
3633 /************************
3634 * 1. Allocating HW data
3635 ************************/
3636 hw = iwl_alloc_all(cfg);
3637 if (!hw) {
3638 err = -ENOMEM;
3639 goto out;
3640 }
3641
3642 priv = hw->priv;
3643 priv->bus = bus;
3644 bus_set_drv_data(priv->bus, priv);
3645
3646 /* At this point both hw and priv are allocated. */
3647
3648 SET_IEEE80211_DEV(hw, priv->bus->dev);
3424 3649
3425 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); 3650 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3426 priv->cfg = cfg; 3651 priv->cfg = cfg;
3427 priv->pci_dev = pdev;
3428 priv->inta_mask = CSR_INI_SET_MASK; 3652 priv->inta_mask = CSR_INI_SET_MASK;
3429 3653
3430 /* is antenna coupling more than 35dB ? */ 3654 /* is antenna coupling more than 35dB ? */
@@ -3440,53 +3664,6 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3440 if (iwl_alloc_traffic_mem(priv)) 3664 if (iwl_alloc_traffic_mem(priv))
3441 IWL_ERR(priv, "Not enough memory to generate traffic log\n"); 3665 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3442 3666
3443 /**************************
3444 * 2. Initializing PCI bus
3445 **************************/
3446 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3447 PCIE_LINK_STATE_CLKPM);
3448
3449 if (pci_enable_device(pdev)) {
3450 err = -ENODEV;
3451 goto out_ieee80211_free_hw;
3452 }
3453
3454 pci_set_master(pdev);
3455
3456 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3457 if (!err)
3458 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3459 if (err) {
3460 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3461 if (!err)
3462 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3463 /* both attempts failed: */
3464 if (err) {
3465 IWL_WARN(priv, "No suitable DMA available.\n");
3466 goto out_pci_disable_device;
3467 }
3468 }
3469
3470 err = pci_request_regions(pdev, DRV_NAME);
3471 if (err)
3472 goto out_pci_disable_device;
3473
3474 pci_set_drvdata(pdev, priv);
3475
3476
3477 /***********************
3478 * 3. Read REV register
3479 ***********************/
3480 priv->hw_base = pci_iomap(pdev, 0, 0);
3481 if (!priv->hw_base) {
3482 err = -ENODEV;
3483 goto out_pci_release_regions;
3484 }
3485
3486 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3487 (unsigned long long) pci_resource_len(pdev, 0));
3488 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3489
3490 /* these spin locks will be used in apm_ops.init and EEPROM access 3667 /* these spin locks will be used in apm_ops.init and EEPROM access
3491 * we should init now 3668 * we should init now
3492 */ 3669 */
@@ -3500,17 +3677,21 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3500 */ 3677 */
3501 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 3678 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3502 3679
3680 /***********************
3681 * 3. Read REV register
3682 ***********************/
3503 hw_rev = iwl_hw_detect(priv); 3683 hw_rev = iwl_hw_detect(priv);
3504 IWL_INFO(priv, "Detected %s, REV=0x%X\n", 3684 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3505 priv->cfg->name, hw_rev); 3685 priv->cfg->name, hw_rev);
3506 3686
3507 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3687 err = iwl_trans_register(&priv->trans, priv);
3508 * PCI Tx retries from interfering with C3 CPU state */ 3688 if (err)
3509 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3689 goto out_free_traffic_mem;
3510 3690
3511 if (iwl_prepare_card_hw(priv)) { 3691 if (trans_prepare_card_hw(&priv->trans)) {
3692 err = -EIO;
3512 IWL_WARN(priv, "Failed, HW not ready\n"); 3693 IWL_WARN(priv, "Failed, HW not ready\n");
3513 goto out_iounmap; 3694 goto out_free_trans;
3514 } 3695 }
3515 3696
3516 /***************** 3697 /*****************
@@ -3520,7 +3701,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3520 err = iwl_eeprom_init(priv, hw_rev); 3701 err = iwl_eeprom_init(priv, hw_rev);
3521 if (err) { 3702 if (err) {
3522 IWL_ERR(priv, "Unable to init EEPROM\n"); 3703 IWL_ERR(priv, "Unable to init EEPROM\n");
3523 goto out_iounmap; 3704 goto out_free_trans;
3524 } 3705 }
3525 err = iwl_eeprom_check_version(priv); 3706 err = iwl_eeprom_check_version(priv);
3526 if (err) 3707 if (err)
@@ -3543,10 +3724,14 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3543 priv->hw->wiphy->n_addresses++; 3724 priv->hw->wiphy->n_addresses++;
3544 } 3725 }
3545 3726
3727 /* initialize all valid contexts */
3728 iwl_init_context(priv);
3729
3546 /************************ 3730 /************************
3547 * 5. Setup HW constants 3731 * 5. Setup HW constants
3548 ************************/ 3732 ************************/
3549 if (iwl_set_hw_params(priv)) { 3733 if (iwl_set_hw_params(priv)) {
3734 err = -ENOENT;
3550 IWL_ERR(priv, "failed to set hw parameters\n"); 3735 IWL_ERR(priv, "failed to set hw parameters\n");
3551 goto out_free_eeprom; 3736 goto out_free_eeprom;
3552 } 3737 }
@@ -3563,36 +3748,14 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3563 /******************** 3748 /********************
3564 * 7. Setup services 3749 * 7. Setup services
3565 ********************/ 3750 ********************/
3566 spin_lock_irqsave(&priv->lock, flags);
3567 iwl_disable_interrupts(priv);
3568 spin_unlock_irqrestore(&priv->lock, flags);
3569
3570 pci_enable_msi(priv->pci_dev);
3571
3572 iwl_alloc_isr_ict(priv);
3573
3574 err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3575 IRQF_SHARED, DRV_NAME, priv);
3576 if (err) {
3577 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3578 goto out_disable_msi;
3579 }
3580
3581 iwl_setup_deferred_work(priv); 3751 iwl_setup_deferred_work(priv);
3582 iwl_setup_rx_handlers(priv); 3752 iwl_setup_rx_handlers(priv);
3583 iwl_testmode_init(priv); 3753 iwl_testmode_init(priv);
3584 3754
3585 /********************************************* 3755 /*********************************************
3586 * 8. Enable interrupts and read RFKILL state 3756 * 8. Enable interrupts
3587 *********************************************/ 3757 *********************************************/
3588 3758
3589 /* enable rfkill interrupt: hw bug w/a */
3590 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3591 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3592 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3593 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3594 }
3595
3596 iwl_enable_rfkill_int(priv); 3759 iwl_enable_rfkill_int(priv);
3597 3760
3598 /* If platform's RF_KILL switch is NOT set to KILL */ 3761 /* If platform's RF_KILL switch is NOT set to KILL */
@@ -3607,7 +3770,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3607 iwl_power_initialize(priv); 3770 iwl_power_initialize(priv);
3608 iwl_tt_initialize(priv); 3771 iwl_tt_initialize(priv);
3609 3772
3610 init_completion(&priv->_agn.firmware_loading_complete); 3773 init_completion(&priv->firmware_loading_complete);
3611 3774
3612 err = iwl_request_firmware(priv, true); 3775 err = iwl_request_firmware(priv, true);
3613 if (err) 3776 if (err)
@@ -3615,44 +3778,32 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3615 3778
3616 return 0; 3779 return 0;
3617 3780
3618 out_destroy_workqueue: 3781out_destroy_workqueue:
3619 destroy_workqueue(priv->workqueue); 3782 destroy_workqueue(priv->workqueue);
3620 priv->workqueue = NULL; 3783 priv->workqueue = NULL;
3621 free_irq(priv->pci_dev->irq, priv);
3622 iwl_free_isr_ict(priv);
3623 out_disable_msi:
3624 pci_disable_msi(priv->pci_dev);
3625 iwl_uninit_drv(priv); 3784 iwl_uninit_drv(priv);
3626 out_free_eeprom: 3785out_free_eeprom:
3627 iwl_eeprom_free(priv); 3786 iwl_eeprom_free(priv);
3628 out_iounmap: 3787out_free_trans:
3629 pci_iounmap(pdev, priv->hw_base); 3788 trans_free(&priv->trans);
3630 out_pci_release_regions: 3789out_free_traffic_mem:
3631 pci_set_drvdata(pdev, NULL);
3632 pci_release_regions(pdev);
3633 out_pci_disable_device:
3634 pci_disable_device(pdev);
3635 out_ieee80211_free_hw:
3636 iwl_free_traffic_mem(priv); 3790 iwl_free_traffic_mem(priv);
3637 ieee80211_free_hw(priv->hw); 3791 ieee80211_free_hw(priv->hw);
3638 out: 3792out:
3639 return err; 3793 return err;
3640} 3794}
3641 3795
3642static void __devexit iwl_pci_remove(struct pci_dev *pdev) 3796void __devexit iwl_remove(struct iwl_priv * priv)
3643{ 3797{
3644 struct iwl_priv *priv = pci_get_drvdata(pdev);
3645 unsigned long flags; 3798 unsigned long flags;
3646 3799
3647 if (!priv) 3800 wait_for_completion(&priv->firmware_loading_complete);
3648 return;
3649
3650 wait_for_completion(&priv->_agn.firmware_loading_complete);
3651 3801
3652 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); 3802 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3653 3803
3654 iwl_dbgfs_unregister(priv); 3804 iwl_dbgfs_unregister(priv);
3655 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); 3805 sysfs_remove_group(&priv->bus->dev->kobj,
3806 &iwl_attribute_group);
3656 3807
3657 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to 3808 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3658 * to be called and iwl_down since we are removing the device 3809 * to be called and iwl_down since we are removing the device
@@ -3680,17 +3831,15 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3680 iwl_disable_interrupts(priv); 3831 iwl_disable_interrupts(priv);
3681 spin_unlock_irqrestore(&priv->lock, flags); 3832 spin_unlock_irqrestore(&priv->lock, flags);
3682 3833
3683 iwl_synchronize_irq(priv); 3834 trans_sync_irq(&priv->trans);
3684 3835
3685 iwl_dealloc_ucode_pci(priv); 3836 iwl_dealloc_ucode(priv);
3686 3837
3687 if (priv->rxq.bd) 3838 trans_rx_free(&priv->trans);
3688 iwlagn_rx_queue_free(priv, &priv->rxq); 3839 trans_tx_free(&priv->trans);
3689 iwlagn_hw_txq_ctx_free(priv);
3690 3840
3691 iwl_eeprom_free(priv); 3841 iwl_eeprom_free(priv);
3692 3842
3693
3694 /*netif_stop_queue(dev); */ 3843 /*netif_stop_queue(dev); */
3695 flush_workqueue(priv->workqueue); 3844 flush_workqueue(priv->workqueue);
3696 3845
@@ -3701,16 +3850,11 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3701 priv->workqueue = NULL; 3850 priv->workqueue = NULL;
3702 iwl_free_traffic_mem(priv); 3851 iwl_free_traffic_mem(priv);
3703 3852
3704 free_irq(priv->pci_dev->irq, priv); 3853 trans_free(&priv->trans);
3705 pci_disable_msi(priv->pci_dev);
3706 pci_iounmap(pdev, priv->hw_base);
3707 pci_release_regions(pdev);
3708 pci_disable_device(pdev);
3709 pci_set_drvdata(pdev, NULL);
3710 3854
3711 iwl_uninit_drv(priv); 3855 bus_set_drv_data(priv->bus, NULL);
3712 3856
3713 iwl_free_isr_ict(priv); 3857 iwl_uninit_drv(priv);
3714 3858
3715 dev_kfree_skb(priv->beacon_skb); 3859 dev_kfree_skb(priv->beacon_skb);
3716 3860
@@ -3723,206 +3867,6 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3723 * driver and module entry point 3867 * driver and module entry point
3724 * 3868 *
3725 *****************************************************************************/ 3869 *****************************************************************************/
3726
3727/* Hardware specific file defines the PCI IDs table for that hardware module */
3728static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
3729 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3730 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3731 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3732 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3733 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3734 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3735 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3736 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3737 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3738 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3739 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3740 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3741 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3742 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3743 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3744 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3745 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3746 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3747 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3748 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3749 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3750 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3751 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3752 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3753
3754/* 5300 Series WiFi */
3755 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3756 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3757 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3758 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3759 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3760 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3761 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3762 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3763 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3764 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3765 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3766 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3767
3768/* 5350 Series WiFi/WiMax */
3769 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3770 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3771 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3772
3773/* 5150 Series Wifi/WiMax */
3774 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3775 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3776 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3777 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3778 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3779 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3780
3781 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3782 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3783 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3784 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
3785
3786/* 6x00 Series */
3787 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3788 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3789 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3790 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3791 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3792 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3793 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3794 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3795 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3796 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3797
3798/* 6x05 Series */
3799 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
3800 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
3801 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
3802 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
3803 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
3804 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
3805 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
3806
3807/* 6x30 Series */
3808 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
3809 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
3810 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
3811 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
3812 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
3813 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
3814 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
3815 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
3816 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
3817 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
3818 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
3819 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
3820 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
3821 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
3822 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
3823 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
3824
3825/* 6x50 WiFi/WiMax Series */
3826 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3827 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3828 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3829 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3830 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3831 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3832
3833/* 6150 WiFi/WiMax Series */
3834 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
3835 {IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
3836 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
3837 {IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
3838 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
3839 {IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
3840
3841/* 1000 Series WiFi */
3842 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3843 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3844 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3845 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3846 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3847 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3848 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3849 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3850 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3851 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3852 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3853 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
3854
3855/* 100 Series WiFi */
3856 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
3857 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
3858 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
3859 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
3860 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
3861 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
3862
3863/* 130 Series WiFi */
3864 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
3865 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
3866 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
3867 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
3868 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
3869 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
3870
3871/* 2x00 Series */
3872 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
3873 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
3874 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
3875 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
3876 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
3877 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
3878
3879/* 2x30 Series */
3880 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
3881 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
3882 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
3883 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
3884 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
3885 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
3886
3887/* 6x35 Series */
3888 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
3889 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
3890 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
3891 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
3892 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
3893 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
3894 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
3895 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
3896 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
3897
3898/* 105 Series */
3899 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
3900 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
3901 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
3902 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
3903 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
3904 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
3905
3906/* 135 Series */
3907 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
3908 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
3909 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
3910 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
3911 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
3912 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
3913
3914 {0}
3915};
3916MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3917
3918static struct pci_driver iwl_driver = {
3919 .name = DRV_NAME,
3920 .id_table = iwl_hw_card_ids,
3921 .probe = iwl_pci_probe,
3922 .remove = __devexit_p(iwl_pci_remove),
3923 .driver.pm = IWL_PM_OPS,
3924};
3925
3926static int __init iwl_init(void) 3870static int __init iwl_init(void)
3927{ 3871{
3928 3872
@@ -3936,12 +3880,10 @@ static int __init iwl_init(void)
3936 return ret; 3880 return ret;
3937 } 3881 }
3938 3882
3939 ret = pci_register_driver(&iwl_driver); 3883 ret = iwl_pci_register_driver();
3940 if (ret) {
3941 pr_err("Unable to initialize PCI module\n");
3942 goto error_register;
3943 }
3944 3884
3885 if (ret)
3886 goto error_register;
3945 return ret; 3887 return ret;
3946 3888
3947error_register: 3889error_register:
@@ -3951,7 +3893,7 @@ error_register:
3951 3893
3952static void __exit iwl_exit(void) 3894static void __exit iwl_exit(void)
3953{ 3895{
3954 pci_unregister_driver(&iwl_driver); 3896 iwl_pci_unregister_driver();
3955 iwlagn_rate_control_unregister(); 3897 iwlagn_rate_control_unregister();
3956} 3898}
3957 3899
@@ -3993,3 +3935,51 @@ MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
3993 3935
3994module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO); 3936module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
3995MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])"); 3937MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
3938
3939module_param_named(wd_disable, iwlagn_mod_params.wd_disable, bool, S_IRUGO);
3940MODULE_PARM_DESC(wd_disable,
3941 "Disable stuck queue watchdog timer (default: 0 [enabled])");
3942
3943/*
3944 * set bt_coex_active to true, uCode will do kill/defer
3945 * every time the priority line is asserted (BT is sending signals on the
3946 * priority line in the PCIx).
3947 * set bt_coex_active to false, uCode will ignore the BT activity and
3948 * perform the normal operation
3949 *
3950 * User might experience transmit issue on some platform due to WiFi/BT
3951 * co-exist problem. The possible behaviors are:
3952 * Able to scan and finding all the available AP
3953 * Not able to associate with any AP
3954 * On those platforms, WiFi communication can be restored by set
3955 * "bt_coex_active" module parameter to "false"
3956 *
3957 * default: bt_coex_active = true (BT_COEX_ENABLE)
3958 */
3959module_param_named(bt_coex_active, iwlagn_mod_params.bt_coex_active,
3960 bool, S_IRUGO);
3961MODULE_PARM_DESC(bt_coex_active, "enable wifi/bt co-exist (default: enable)");
3962
3963module_param_named(led_mode, iwlagn_mod_params.led_mode, int, S_IRUGO);
3964MODULE_PARM_DESC(led_mode, "0=system default, "
3965 "1=On(RF On)/Off(RF Off), 2=blinking (default: 0)");
3966
3967module_param_named(power_save, iwlagn_mod_params.power_save,
3968 bool, S_IRUGO);
3969MODULE_PARM_DESC(power_save,
3970 "enable WiFi power management (default: disable)");
3971
3972module_param_named(power_level, iwlagn_mod_params.power_level,
3973 int, S_IRUGO);
3974MODULE_PARM_DESC(power_level,
3975 "default power save level (range from 1 - 5, default: 1)");
3976
3977/*
3978 * For now, keep using power level 1 instead of automatically
3979 * adjusting ...
3980 */
3981module_param_named(no_sleep_autoadjust, iwlagn_mod_params.no_sleep_autoadjust,
3982 bool, S_IRUGO);
3983MODULE_PARM_DESC(no_sleep_autoadjust,
3984 "don't automatically adjust sleep level "
3985 "according to maximum network latency (default: true)");
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.h b/drivers/net/wireless/iwlwifi/iwl-agn.h
index d1716844002e..d941c4c98e4b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.h
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.h
@@ -109,42 +109,25 @@ extern struct iwl_cfg iwl135_bg_cfg;
109extern struct iwl_cfg iwl135_bgn_cfg; 109extern struct iwl_cfg iwl135_bgn_cfg;
110 110
111extern struct iwl_mod_params iwlagn_mod_params; 111extern struct iwl_mod_params iwlagn_mod_params;
112extern struct iwl_hcmd_ops iwlagn_hcmd;
113extern struct iwl_hcmd_ops iwlagn_bt_hcmd;
114extern struct iwl_hcmd_utils_ops iwlagn_hcmd_utils;
115 112
116extern struct ieee80211_ops iwlagn_hw_ops; 113extern struct ieee80211_ops iwlagn_hw_ops;
117 114
118int iwl_reset_ict(struct iwl_priv *priv); 115int iwl_reset_ict(struct iwl_priv *priv);
119void iwl_disable_ict(struct iwl_priv *priv);
120int iwl_alloc_isr_ict(struct iwl_priv *priv);
121void iwl_free_isr_ict(struct iwl_priv *priv);
122irqreturn_t iwl_isr_ict(int irq, void *data);
123 116
124/* call this function to flush any scheduled tasklet */ 117static inline void iwl_set_calib_hdr(struct iwl_calib_hdr *hdr, u8 cmd)
125static inline void iwl_synchronize_irq(struct iwl_priv *priv)
126{ 118{
127 /* wait to make sure we flush pending tasklet*/ 119 hdr->op_code = cmd;
128 synchronize_irq(priv->pci_dev->irq); 120 hdr->first_group = 0;
129 tasklet_kill(&priv->irq_tasklet); 121 hdr->groups_num = 1;
122 hdr->data_valid = 1;
130} 123}
131 124
132int iwl_prepare_card_hw(struct iwl_priv *priv);
133
134int iwlagn_start_device(struct iwl_priv *priv);
135void iwlagn_stop_device(struct iwl_priv *priv);
136
137/* tx queue */ 125/* tx queue */
138void iwlagn_set_wr_ptrs(struct iwl_priv *priv,
139 int txq_id, u32 index);
140void iwlagn_tx_queue_set_status(struct iwl_priv *priv,
141 struct iwl_tx_queue *txq,
142 int tx_fifo_id, int scd_retry);
143void iwlagn_txq_set_sched(struct iwl_priv *priv, u32 mask);
144void iwl_free_tfds_in_queue(struct iwl_priv *priv, 126void iwl_free_tfds_in_queue(struct iwl_priv *priv,
145 int sta_id, int tid, int freed); 127 int sta_id, int tid, int freed);
146 128
147/* RXON */ 129/* RXON */
130int iwlagn_set_pan_params(struct iwl_priv *priv);
148int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx); 131int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx);
149void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx); 132void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx);
150int iwlagn_mac_config(struct ieee80211_hw *hw, u32 changed); 133int iwlagn_mac_config(struct ieee80211_hw *hw, u32 changed);
@@ -161,41 +144,29 @@ void iwlagn_send_prio_tbl(struct iwl_priv *priv);
161int iwlagn_run_init_ucode(struct iwl_priv *priv); 144int iwlagn_run_init_ucode(struct iwl_priv *priv);
162int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv, 145int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
163 struct fw_img *image, 146 struct fw_img *image,
164 int subtype, int alternate_subtype); 147 enum iwlagn_ucode_type ucode_type);
165 148
166/* lib */ 149/* lib */
167void iwl_check_abort_status(struct iwl_priv *priv, 150void iwl_check_abort_status(struct iwl_priv *priv,
168 u8 frame_count, u32 status); 151 u8 frame_count, u32 status);
169void iwlagn_rx_handler_setup(struct iwl_priv *priv);
170void iwlagn_setup_deferred_work(struct iwl_priv *priv);
171int iwlagn_hw_valid_rtc_data_addr(u32 addr); 152int iwlagn_hw_valid_rtc_data_addr(u32 addr);
172int iwlagn_send_tx_power(struct iwl_priv *priv); 153int iwlagn_send_tx_power(struct iwl_priv *priv);
173void iwlagn_temperature(struct iwl_priv *priv); 154void iwlagn_temperature(struct iwl_priv *priv);
174u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv); 155u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv);
175const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
176 size_t offset);
177void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
178int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
179int iwlagn_hw_nic_init(struct iwl_priv *priv);
180int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv); 156int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv);
181int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control); 157int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control);
182void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control); 158void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control);
159int iwlagn_send_beacon_cmd(struct iwl_priv *priv);
183 160
184/* rx */ 161/* rx */
185void iwlagn_rx_queue_restock(struct iwl_priv *priv);
186void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority);
187void iwlagn_rx_replenish(struct iwl_priv *priv);
188void iwlagn_rx_replenish_now(struct iwl_priv *priv);
189void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq);
190int iwlagn_rxq_stop(struct iwl_priv *priv);
191int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band); 162int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band);
192void iwl_setup_rx_handlers(struct iwl_priv *priv); 163void iwl_setup_rx_handlers(struct iwl_priv *priv);
164void iwl_rx_dispatch(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
165
193 166
194/* tx */ 167/* tx */
195void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq); 168void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq,
196int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv, 169 int index);
197 struct iwl_tx_queue *txq,
198 dma_addr_t addr, u16 len, u8 reset);
199void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags, 170void iwlagn_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
200 struct ieee80211_tx_info *info); 171 struct ieee80211_tx_info *info);
201int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb); 172int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb);
@@ -203,18 +174,12 @@ int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
203 struct ieee80211_sta *sta, u16 tid, u16 *ssn); 174 struct ieee80211_sta *sta, u16 tid, u16 *ssn);
204int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif, 175int iwlagn_tx_agg_stop(struct iwl_priv *priv, struct ieee80211_vif *vif,
205 struct ieee80211_sta *sta, u16 tid); 176 struct ieee80211_sta *sta, u16 tid);
206void iwlagn_txq_agg_queue_setup(struct iwl_priv *priv,
207 struct ieee80211_sta *sta,
208 int tid, int frame_limit);
209int iwlagn_txq_check_empty(struct iwl_priv *priv, 177int iwlagn_txq_check_empty(struct iwl_priv *priv,
210 int sta_id, u8 tid, int txq_id); 178 int sta_id, u8 tid, int txq_id);
211void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv, 179void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
212 struct iwl_rx_mem_buffer *rxb); 180 struct iwl_rx_mem_buffer *rxb);
181void iwlagn_rx_reply_tx(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
213int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index); 182int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index);
214void iwlagn_hw_txq_ctx_free(struct iwl_priv *priv);
215int iwlagn_txq_ctx_alloc(struct iwl_priv *priv);
216void iwlagn_txq_ctx_reset(struct iwl_priv *priv);
217void iwlagn_txq_ctx_stop(struct iwl_priv *priv);
218 183
219static inline u32 iwl_tx_status_to_mac80211(u32 status) 184static inline u32 iwl_tx_status_to_mac80211(u32 status)
220{ 185{
@@ -249,10 +214,6 @@ void iwlagn_post_scan(struct iwl_priv *priv);
249int iwlagn_manage_ibss_station(struct iwl_priv *priv, 214int iwlagn_manage_ibss_station(struct iwl_priv *priv,
250 struct ieee80211_vif *vif, bool add); 215 struct ieee80211_vif *vif, bool add);
251 216
252/* hcmd */
253int iwlagn_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant);
254int iwlagn_send_beacon_cmd(struct iwl_priv *priv);
255
256/* bt coex */ 217/* bt coex */
257void iwlagn_send_advance_bt_config(struct iwl_priv *priv); 218void iwlagn_send_advance_bt_config(struct iwl_priv *priv);
258void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv, 219void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
@@ -260,6 +221,8 @@ void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
260void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv); 221void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv);
261void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv); 222void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv);
262void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv); 223void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv);
224void iwlagn_bt_coex_rssi_monitor(struct iwl_priv *priv);
225void iwlagn_bt_adjust_rssi_monitor(struct iwl_priv *priv, bool rssi_ena);
263 226
264#ifdef CONFIG_IWLWIFI_DEBUG 227#ifdef CONFIG_IWLWIFI_DEBUG
265const char *iwl_get_tx_fail_reason(u32 status); 228const char *iwl_get_tx_fail_reason(u32 status);
@@ -283,11 +246,13 @@ int iwl_set_default_wep_key(struct iwl_priv *priv,
283int iwl_restore_default_wep_keys(struct iwl_priv *priv, 246int iwl_restore_default_wep_keys(struct iwl_priv *priv,
284 struct iwl_rxon_context *ctx); 247 struct iwl_rxon_context *ctx);
285int iwl_set_dynamic_key(struct iwl_priv *priv, struct iwl_rxon_context *ctx, 248int iwl_set_dynamic_key(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
286 struct ieee80211_key_conf *key, u8 sta_id); 249 struct ieee80211_key_conf *key,
250 struct ieee80211_sta *sta);
287int iwl_remove_dynamic_key(struct iwl_priv *priv, struct iwl_rxon_context *ctx, 251int iwl_remove_dynamic_key(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
288 struct ieee80211_key_conf *key, u8 sta_id); 252 struct ieee80211_key_conf *key,
253 struct ieee80211_sta *sta);
289void iwl_update_tkip_key(struct iwl_priv *priv, 254void iwl_update_tkip_key(struct iwl_priv *priv,
290 struct iwl_rxon_context *ctx, 255 struct ieee80211_vif *vif,
291 struct ieee80211_key_conf *keyconf, 256 struct ieee80211_key_conf *keyconf,
292 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key); 257 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key);
293int iwl_sta_tx_modify_enable_tid(struct iwl_priv *priv, int sta_id, int tid); 258int iwl_sta_tx_modify_enable_tid(struct iwl_priv *priv, int sta_id, int tid);
@@ -296,6 +261,8 @@ int iwl_sta_rx_agg_start(struct iwl_priv *priv, struct ieee80211_sta *sta,
296int iwl_sta_rx_agg_stop(struct iwl_priv *priv, struct ieee80211_sta *sta, 261int iwl_sta_rx_agg_stop(struct iwl_priv *priv, struct ieee80211_sta *sta,
297 int tid); 262 int tid);
298void iwl_sta_modify_sleep_tx_count(struct iwl_priv *priv, int sta_id, int cnt); 263void iwl_sta_modify_sleep_tx_count(struct iwl_priv *priv, int sta_id, int cnt);
264int iwl_update_bcast_station(struct iwl_priv *priv,
265 struct iwl_rxon_context *ctx);
299int iwl_update_bcast_stations(struct iwl_priv *priv); 266int iwl_update_bcast_stations(struct iwl_priv *priv);
300void iwlagn_mac_sta_notify(struct ieee80211_hw *hw, 267void iwlagn_mac_sta_notify(struct ieee80211_hw *hw,
301 struct ieee80211_vif *vif, 268 struct ieee80211_vif *vif,
@@ -343,6 +310,9 @@ extern int iwl_alive_start(struct iwl_priv *priv);
343/* svtool */ 310/* svtool */
344#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL 311#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
345extern int iwl_testmode_cmd(struct ieee80211_hw *hw, void *data, int len); 312extern int iwl_testmode_cmd(struct ieee80211_hw *hw, void *data, int len);
313extern int iwl_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
314 struct netlink_callback *cb,
315 void *data, int len);
346extern void iwl_testmode_init(struct iwl_priv *priv); 316extern void iwl_testmode_init(struct iwl_priv *priv);
347extern void iwl_testmode_cleanup(struct iwl_priv *priv); 317extern void iwl_testmode_cleanup(struct iwl_priv *priv);
348#else 318#else
@@ -352,6 +322,13 @@ int iwl_testmode_cmd(struct ieee80211_hw *hw, void *data, int len)
352 return -ENOSYS; 322 return -ENOSYS;
353} 323}
354static inline 324static inline
325int iwl_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
326 struct netlink_callback *cb,
327 void *data, int len)
328{
329 return -ENOSYS;
330}
331static inline
355void iwl_testmode_init(struct iwl_priv *priv) 332void iwl_testmode_init(struct iwl_priv *priv)
356{ 333{
357} 334}
diff --git a/drivers/net/wireless/iwlwifi/iwl-bus.h b/drivers/net/wireless/iwlwifi/iwl-bus.h
new file mode 100644
index 000000000000..f3ee1c0c004c
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-bus.h
@@ -0,0 +1,139 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63#ifndef __iwl_pci_h__
64#define __iwl_pci_h__
65
66struct iwl_bus;
67
68/**
69 * struct iwl_bus_ops - bus specific operations
70 * @get_pm_support: must returns true if the bus can go to sleep
71 * @apm_config: will be called during the config of the APM configuration
72 * @set_drv_data: set the drv_data pointer to the bus layer
73 * @get_hw_id: prints the hw_id in the provided buffer
74 * @write8: write a byte to register at offset ofs
75 * @write32: write a dword to register at offset ofs
76 * @wread32: read a dword at register at offset ofs
77 */
78struct iwl_bus_ops {
79 bool (*get_pm_support)(struct iwl_bus *bus);
80 void (*apm_config)(struct iwl_bus *bus);
81 void (*set_drv_data)(struct iwl_bus *bus, void *drv_data);
82 void (*get_hw_id)(struct iwl_bus *bus, char buf[], int buf_len);
83 void (*write8)(struct iwl_bus *bus, u32 ofs, u8 val);
84 void (*write32)(struct iwl_bus *bus, u32 ofs, u32 val);
85 u32 (*read32)(struct iwl_bus *bus, u32 ofs);
86};
87
88struct iwl_bus {
89 /* Common data to all buses */
90 void *drv_data; /* driver's context */
91 struct device *dev;
92 struct iwl_bus_ops *ops;
93
94 unsigned int irq;
95
96 /* pointer to bus specific struct */
97 /*Ensure that this pointer will always be aligned to sizeof pointer */
98 char bus_specific[0] __attribute__((__aligned__(sizeof(void *))));
99};
100
101static inline bool bus_get_pm_support(struct iwl_bus *bus)
102{
103 return bus->ops->get_pm_support(bus);
104}
105
106static inline void bus_apm_config(struct iwl_bus *bus)
107{
108 bus->ops->apm_config(bus);
109}
110
111static inline void bus_set_drv_data(struct iwl_bus *bus, void *drv_data)
112{
113 bus->ops->set_drv_data(bus, drv_data);
114}
115
116static inline void bus_get_hw_id(struct iwl_bus *bus, char buf[], int buf_len)
117{
118 bus->ops->get_hw_id(bus, buf, buf_len);
119}
120
121static inline void bus_write8(struct iwl_bus *bus, u32 ofs, u8 val)
122{
123 bus->ops->write8(bus, ofs, val);
124}
125
126static inline void bus_write32(struct iwl_bus *bus, u32 ofs, u32 val)
127{
128 bus->ops->write32(bus, ofs, val);
129}
130
131static inline u32 bus_read32(struct iwl_bus *bus, u32 ofs)
132{
133 return bus->ops->read32(bus, ofs);
134}
135
136int __must_check iwl_pci_register_driver(void);
137void iwl_pci_unregister_driver(void);
138
139#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h
index 6ee5f1aa555c..5769ca5cebca 100644
--- a/drivers/net/wireless/iwlwifi/iwl-commands.h
+++ b/drivers/net/wireless/iwlwifi/iwl-commands.h
@@ -188,6 +188,13 @@ enum {
188 REPLY_WIPAN_NOA_NOTIFICATION = 0xbc, 188 REPLY_WIPAN_NOA_NOTIFICATION = 0xbc,
189 REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd, 189 REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd,
190 190
191 REPLY_WOWLAN_PATTERNS = 0xe0,
192 REPLY_WOWLAN_WAKEUP_FILTER = 0xe1,
193 REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2,
194 REPLY_WOWLAN_TKIP_PARAMS = 0xe3,
195 REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
196 REPLY_WOWLAN_GET_STATUS = 0xe5,
197
191 REPLY_MAX = 0xff 198 REPLY_MAX = 0xff
192}; 199};
193 200
@@ -384,18 +391,6 @@ struct iwl_tx_ant_config_cmd {
384 391
385#define UCODE_VALID_OK cpu_to_le32(0x1) 392#define UCODE_VALID_OK cpu_to_le32(0x1)
386 393
387enum iwlagn_ucode_subtype {
388 UCODE_SUBTYPE_REGULAR = 0,
389 UCODE_SUBTYPE_REGULAR_NEW = 1,
390 UCODE_SUBTYPE_INIT = 9,
391
392 /*
393 * Not a valid subtype, the ucode has just a u8, so
394 * we can use something > 0xff for this value.
395 */
396 UCODE_SUBTYPE_NONE_LOADED = 0x100,
397};
398
399/** 394/**
400 * REPLY_ALIVE = 0x1 (response only, not a command) 395 * REPLY_ALIVE = 0x1 (response only, not a command)
401 * 396 *
@@ -844,6 +839,8 @@ struct iwl_qosparam_cmd {
844#define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000) 839#define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
845#define STA_KEY_MAX_NUM 8 840#define STA_KEY_MAX_NUM 8
846#define STA_KEY_MAX_NUM_PAN 16 841#define STA_KEY_MAX_NUM_PAN 16
842/* must not match WEP_INVALID_OFFSET */
843#define IWLAGN_HW_KEY_DEFAULT 0xfe
847 844
848/* Flags indicate whether to modify vs. don't change various station params */ 845/* Flags indicate whether to modify vs. don't change various station params */
849#define STA_MODIFY_KEY_MASK 0x01 846#define STA_MODIFY_KEY_MASK 0x01
@@ -984,15 +981,26 @@ struct iwl_rem_sta_cmd {
984 u8 reserved2[2]; 981 u8 reserved2[2];
985} __packed; 982} __packed;
986 983
987#define IWL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0)) 984
988#define IWL_TX_FIFO_BE_MSK cpu_to_le32(BIT(1)) 985/* WiFi queues mask */
989#define IWL_TX_FIFO_VI_MSK cpu_to_le32(BIT(2)) 986#define IWL_SCD_BK_MSK cpu_to_le32(BIT(0))
990#define IWL_TX_FIFO_VO_MSK cpu_to_le32(BIT(3)) 987#define IWL_SCD_BE_MSK cpu_to_le32(BIT(1))
988#define IWL_SCD_VI_MSK cpu_to_le32(BIT(2))
989#define IWL_SCD_VO_MSK cpu_to_le32(BIT(3))
990#define IWL_SCD_MGMT_MSK cpu_to_le32(BIT(3))
991
992/* PAN queues mask */
993#define IWL_PAN_SCD_BK_MSK cpu_to_le32(BIT(4))
994#define IWL_PAN_SCD_BE_MSK cpu_to_le32(BIT(5))
995#define IWL_PAN_SCD_VI_MSK cpu_to_le32(BIT(6))
996#define IWL_PAN_SCD_VO_MSK cpu_to_le32(BIT(7))
997#define IWL_PAN_SCD_MGMT_MSK cpu_to_le32(BIT(7))
998#define IWL_PAN_SCD_MULTICAST_MSK cpu_to_le32(BIT(8))
999
991#define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00) 1000#define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
992 1001
993#define IWL_DROP_SINGLE 0 1002#define IWL_DROP_SINGLE 0
994#define IWL_DROP_SELECTED 1 1003#define IWL_DROP_ALL (BIT(IWL_RXON_CTX_BSS) | BIT(IWL_RXON_CTX_PAN))
995#define IWL_DROP_ALL 2
996 1004
997/* 1005/*
998 * REPLY_TXFIFO_FLUSH = 0x1e(command and response) 1006 * REPLY_TXFIFO_FLUSH = 0x1e(command and response)
@@ -1932,6 +1940,9 @@ struct iwl_bt_cmd {
1932/* Disable Sync PSPoll on SCO/eSCO */ 1940/* Disable Sync PSPoll on SCO/eSCO */
1933#define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7) 1941#define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7)
1934 1942
1943#define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75 /* dBm */
1944#define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65 /* dBm */
1945
1935#define IWLAGN_BT_PRIO_BOOST_MAX 0xFF 1946#define IWLAGN_BT_PRIO_BOOST_MAX 0xFF
1936#define IWLAGN_BT_PRIO_BOOST_MIN 0x00 1947#define IWLAGN_BT_PRIO_BOOST_MIN 0x00
1937#define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0 1948#define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0
@@ -3153,7 +3164,6 @@ struct iwl_enhance_sensitivity_cmd {
3153/* The default calibrate table size if not specified by firmware */ 3164/* The default calibrate table size if not specified by firmware */
3154#define IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18 3165#define IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
3155enum { 3166enum {
3156 IWL_PHY_CALIBRATE_DIFF_GAIN_CMD = 7,
3157 IWL_PHY_CALIBRATE_DC_CMD = 8, 3167 IWL_PHY_CALIBRATE_DC_CMD = 8,
3158 IWL_PHY_CALIBRATE_LO_CMD = 9, 3168 IWL_PHY_CALIBRATE_LO_CMD = 9,
3159 IWL_PHY_CALIBRATE_TX_IQ_CMD = 11, 3169 IWL_PHY_CALIBRATE_TX_IQ_CMD = 11,
@@ -3166,22 +3176,36 @@ enum {
3166 3176
3167#define IWL_MAX_PHY_CALIBRATE_TBL_SIZE (253) 3177#define IWL_MAX_PHY_CALIBRATE_TBL_SIZE (253)
3168 3178
3169#define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(0xffffffff)
3170
3171/* This enum defines the bitmap of various calibrations to enable in both 3179/* This enum defines the bitmap of various calibrations to enable in both
3172 * init ucode and runtime ucode through CALIBRATION_CFG_CMD. 3180 * init ucode and runtime ucode through CALIBRATION_CFG_CMD.
3173 */ 3181 */
3174enum iwl_ucode_calib_cfg { 3182enum iwl_ucode_calib_cfg {
3175 IWL_CALIB_CFG_RX_BB_IDX, 3183 IWL_CALIB_CFG_RX_BB_IDX = BIT(0),
3176 IWL_CALIB_CFG_DC_IDX, 3184 IWL_CALIB_CFG_DC_IDX = BIT(1),
3177 IWL_CALIB_CFG_TX_IQ_IDX, 3185 IWL_CALIB_CFG_LO_IDX = BIT(2),
3178 IWL_CALIB_CFG_RX_IQ_IDX, 3186 IWL_CALIB_CFG_TX_IQ_IDX = BIT(3),
3179 IWL_CALIB_CFG_NOISE_IDX, 3187 IWL_CALIB_CFG_RX_IQ_IDX = BIT(4),
3180 IWL_CALIB_CFG_CRYSTAL_IDX, 3188 IWL_CALIB_CFG_NOISE_IDX = BIT(5),
3181 IWL_CALIB_CFG_TEMPERATURE_IDX, 3189 IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6),
3182 IWL_CALIB_CFG_PAPD_IDX, 3190 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7),
3191 IWL_CALIB_CFG_PAPD_IDX = BIT(8),
3192 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9),
3193 IWL_CALIB_CFG_TX_PWR_IDX = BIT(10),
3183}; 3194};
3184 3195
3196#define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3197 IWL_CALIB_CFG_DC_IDX | \
3198 IWL_CALIB_CFG_LO_IDX | \
3199 IWL_CALIB_CFG_TX_IQ_IDX | \
3200 IWL_CALIB_CFG_RX_IQ_IDX | \
3201 IWL_CALIB_CFG_NOISE_IDX | \
3202 IWL_CALIB_CFG_CRYSTAL_IDX | \
3203 IWL_CALIB_CFG_TEMPERATURE_IDX | \
3204 IWL_CALIB_CFG_PAPD_IDX | \
3205 IWL_CALIB_CFG_SENSITIVITY_IDX | \
3206 IWL_CALIB_CFG_TX_PWR_IDX)
3207
3208#define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))
3185 3209
3186struct iwl_calib_cfg_elmnt_s { 3210struct iwl_calib_cfg_elmnt_s {
3187 __le32 is_enable; 3211 __le32 is_enable;
@@ -3215,15 +3239,6 @@ struct iwl_calib_cmd {
3215 u8 data[0]; 3239 u8 data[0];
3216} __packed; 3240} __packed;
3217 3241
3218/* IWL_PHY_CALIBRATE_DIFF_GAIN_CMD (7) */
3219struct iwl_calib_diff_gain_cmd {
3220 struct iwl_calib_hdr hdr;
3221 s8 diff_gain_a; /* see above */
3222 s8 diff_gain_b;
3223 s8 diff_gain_c;
3224 u8 reserved1;
3225} __packed;
3226
3227struct iwl_calib_xtal_freq_cmd { 3242struct iwl_calib_xtal_freq_cmd {
3228 struct iwl_calib_hdr hdr; 3243 struct iwl_calib_hdr hdr;
3229 u8 cap_pin1; 3244 u8 cap_pin1;
@@ -3231,11 +3246,11 @@ struct iwl_calib_xtal_freq_cmd {
3231 u8 pad[2]; 3246 u8 pad[2];
3232} __packed; 3247} __packed;
3233 3248
3234#define DEFAULT_RADIO_SENSOR_OFFSET 2700 3249#define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)
3235struct iwl_calib_temperature_offset_cmd { 3250struct iwl_calib_temperature_offset_cmd {
3236 struct iwl_calib_hdr hdr; 3251 struct iwl_calib_hdr hdr;
3237 s16 radio_sensor_offset; 3252 __le16 radio_sensor_offset;
3238 s16 reserved; 3253 __le16 reserved;
3239} __packed; 3254} __packed;
3240 3255
3241/* IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD */ 3256/* IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD */
@@ -3756,6 +3771,127 @@ struct iwl_bt_coex_prot_env_cmd {
3756 u8 reserved[2]; 3771 u8 reserved[2];
3757} __attribute__((packed)); 3772} __attribute__((packed));
3758 3773
3774/*
3775 * REPLY_WOWLAN_PATTERNS
3776 */
3777#define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16
3778#define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128
3779
3780struct iwlagn_wowlan_pattern {
3781 u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8];
3782 u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN];
3783 u8 mask_size;
3784 u8 pattern_size;
3785 __le16 reserved;
3786} __packed;
3787
3788#define IWLAGN_WOWLAN_MAX_PATTERNS 20
3789
3790struct iwlagn_wowlan_patterns_cmd {
3791 __le32 n_patterns;
3792 struct iwlagn_wowlan_pattern patterns[];
3793} __packed;
3794
3795/*
3796 * REPLY_WOWLAN_WAKEUP_FILTER
3797 */
3798enum iwlagn_wowlan_wakeup_filters {
3799 IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0),
3800 IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1),
3801 IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2),
3802 IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3),
3803 IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4),
3804 IWLAGN_WOWLAN_WAKEUP_RFKILL = BIT(5),
3805 IWLAGN_WOWLAN_WAKEUP_UCODE_ERROR = BIT(6),
3806 IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(7),
3807 IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(8),
3808 IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(9),
3809 IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(10),
3810};
3811
3812struct iwlagn_wowlan_wakeup_filter_cmd {
3813 __le32 enabled;
3814 __le16 non_qos_seq;
3815 u8 min_sleep_seconds;
3816 u8 reserved;
3817 __le16 qos_seq[8];
3818};
3819
3820/*
3821 * REPLY_WOWLAN_TSC_RSC_PARAMS
3822 */
3823#define IWLAGN_NUM_RSC 16
3824
3825struct tkip_sc {
3826 __le16 iv16;
3827 __le16 pad;
3828 __le32 iv32;
3829} __packed;
3830
3831struct iwlagn_tkip_rsc_tsc {
3832 struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC];
3833 struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC];
3834 struct tkip_sc tsc;
3835} __packed;
3836
3837struct aes_sc {
3838 __le64 pn;
3839} __packed;
3840
3841struct iwlagn_aes_rsc_tsc {
3842 struct aes_sc unicast_rsc[IWLAGN_NUM_RSC];
3843 struct aes_sc multicast_rsc[IWLAGN_NUM_RSC];
3844 struct aes_sc tsc;
3845} __packed;
3846
3847union iwlagn_all_tsc_rsc {
3848 struct iwlagn_tkip_rsc_tsc tkip;
3849 struct iwlagn_aes_rsc_tsc aes;
3850};
3851
3852struct iwlagn_wowlan_rsc_tsc_params_cmd {
3853 union iwlagn_all_tsc_rsc all_tsc_rsc;
3854} __packed;
3855
3856/*
3857 * REPLY_WOWLAN_TKIP_PARAMS
3858 */
3859#define IWLAGN_MIC_KEY_SIZE 8
3860#define IWLAGN_P1K_SIZE 5
3861struct iwlagn_mic_keys {
3862 u8 tx[IWLAGN_MIC_KEY_SIZE];
3863 u8 rx_unicast[IWLAGN_MIC_KEY_SIZE];
3864 u8 rx_mcast[IWLAGN_MIC_KEY_SIZE];
3865} __packed;
3866
3867struct iwlagn_p1k_cache {
3868 __le16 p1k[IWLAGN_P1K_SIZE];
3869} __packed;
3870
3871#define IWLAGN_NUM_RX_P1K_CACHE 2
3872
3873struct iwlagn_wowlan_tkip_params_cmd {
3874 struct iwlagn_mic_keys mic_keys;
3875 struct iwlagn_p1k_cache tx;
3876 struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE];
3877 struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE];
3878} __packed;
3879
3880/*
3881 * REPLY_WOWLAN_KEK_KCK_MATERIAL
3882 */
3883
3884#define IWLAGN_KCK_MAX_SIZE 32
3885#define IWLAGN_KEK_MAX_SIZE 32
3886
3887struct iwlagn_wowlan_kek_kck_material_cmd {
3888 u8 kck[IWLAGN_KCK_MAX_SIZE];
3889 u8 kek[IWLAGN_KEK_MAX_SIZE];
3890 __le16 kck_len;
3891 __le16 kek_len;
3892 __le64 replay_ctr;
3893} __packed;
3894
3759/****************************************************************************** 3895/******************************************************************************
3760 * (13) 3896 * (13)
3761 * Union of all expected notifications/responses: 3897 * Union of all expected notifications/responses:
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index 45cc51c9c93e..cf376f62b2f6 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -42,27 +42,7 @@
42#include "iwl-sta.h" 42#include "iwl-sta.h"
43#include "iwl-helpers.h" 43#include "iwl-helpers.h"
44#include "iwl-agn.h" 44#include "iwl-agn.h"
45 45#include "iwl-trans.h"
46
47/*
48 * set bt_coex_active to true, uCode will do kill/defer
49 * every time the priority line is asserted (BT is sending signals on the
50 * priority line in the PCIx).
51 * set bt_coex_active to false, uCode will ignore the BT activity and
52 * perform the normal operation
53 *
54 * User might experience transmit issue on some platform due to WiFi/BT
55 * co-exist problem. The possible behaviors are:
56 * Able to scan and finding all the available AP
57 * Not able to associate with any AP
58 * On those platforms, WiFi communication can be restored by set
59 * "bt_coex_active" module parameter to "false"
60 *
61 * default: bt_coex_active = true (BT_COEX_ENABLE)
62 */
63bool bt_coex_active = true;
64module_param(bt_coex_active, bool, S_IRUGO);
65MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
66 46
67u32 iwl_debug_level; 47u32 iwl_debug_level;
68 48
@@ -164,7 +144,7 @@ int iwlcore_init_geos(struct iwl_priv *priv)
164 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE]; 144 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
165 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE; 145 sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
166 146
167 if (priv->cfg->sku & IWL_SKU_N) 147 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
168 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, 148 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
169 IEEE80211_BAND_5GHZ); 149 IEEE80211_BAND_5GHZ);
170 150
@@ -174,7 +154,7 @@ int iwlcore_init_geos(struct iwl_priv *priv)
174 sband->bitrates = rates; 154 sband->bitrates = rates;
175 sband->n_bitrates = IWL_RATE_COUNT_LEGACY; 155 sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
176 156
177 if (priv->cfg->sku & IWL_SKU_N) 157 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
178 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap, 158 iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
179 IEEE80211_BAND_2GHZ); 159 IEEE80211_BAND_2GHZ);
180 160
@@ -229,12 +209,12 @@ int iwlcore_init_geos(struct iwl_priv *priv)
229 priv->tx_power_next = max_tx_power; 209 priv->tx_power_next = max_tx_power;
230 210
231 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) && 211 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
232 priv->cfg->sku & IWL_SKU_A) { 212 priv->cfg->sku & EEPROM_SKU_CAP_BAND_52GHZ) {
213 char buf[32];
214 bus_get_hw_id(priv->bus, buf, sizeof(buf));
233 IWL_INFO(priv, "Incorrectly detected BG card as ABG. " 215 IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
234 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n", 216 "Please send your %s to maintainer.\n", buf);
235 priv->pci_dev->device, 217 priv->cfg->sku &= ~EEPROM_SKU_CAP_BAND_52GHZ;
236 priv->pci_dev->subsystem_device);
237 priv->cfg->sku &= ~IWL_SKU_A;
238 } 218 }
239 219
240 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n", 220 IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
@@ -383,6 +363,8 @@ int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
383 ctx->timing.beacon_interval = cpu_to_le16(beacon_int); 363 ctx->timing.beacon_interval = cpu_to_le16(beacon_int);
384 } 364 }
385 365
366 ctx->beacon_int = beacon_int;
367
386 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ 368 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
387 interval_tm = beacon_int * TIME_UNIT; 369 interval_tm = beacon_int * TIME_UNIT;
388 rem = do_div(tsf, interval_tm); 370 rem = do_div(tsf, interval_tm);
@@ -396,8 +378,8 @@ int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
396 le32_to_cpu(ctx->timing.beacon_init_val), 378 le32_to_cpu(ctx->timing.beacon_init_val),
397 le16_to_cpu(ctx->timing.atim_window)); 379 le16_to_cpu(ctx->timing.atim_window));
398 380
399 return iwl_send_cmd_pdu(priv, ctx->rxon_timing_cmd, 381 return trans_send_cmd_pdu(&priv->trans, ctx->rxon_timing_cmd,
400 sizeof(ctx->timing), &ctx->timing); 382 CMD_SYNC, sizeof(ctx->timing), &ctx->timing);
401} 383}
402 384
403void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx, 385void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
@@ -547,19 +529,6 @@ int iwl_full_rxon_required(struct iwl_priv *priv,
547 return 0; 529 return 0;
548} 530}
549 531
550u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv,
551 struct iwl_rxon_context *ctx)
552{
553 /*
554 * Assign the lowest rate -- should really get this from
555 * the beacon skb from mac80211.
556 */
557 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK)
558 return IWL_RATE_1M_PLCP;
559 else
560 return IWL_RATE_6M_PLCP;
561}
562
563static void _iwl_set_rxon_ht(struct iwl_priv *priv, 532static void _iwl_set_rxon_ht(struct iwl_priv *priv,
564 struct iwl_ht_config *ht_conf, 533 struct iwl_ht_config *ht_conf,
565 struct iwl_rxon_context *ctx) 534 struct iwl_rxon_context *ctx)
@@ -619,8 +588,7 @@ static void _iwl_set_rxon_ht(struct iwl_priv *priv,
619 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; 588 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
620 } 589 }
621 590
622 if (priv->cfg->ops->hcmd->set_rxon_chain) 591 iwlagn_set_rxon_chain(priv, ctx);
623 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
624 592
625 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X " 593 IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
626 "extension channel offset 0x%x\n", 594 "extension channel offset 0x%x\n",
@@ -874,12 +842,12 @@ static void iwlagn_abort_notification_waits(struct iwl_priv *priv)
874 unsigned long flags; 842 unsigned long flags;
875 struct iwl_notification_wait *wait_entry; 843 struct iwl_notification_wait *wait_entry;
876 844
877 spin_lock_irqsave(&priv->_agn.notif_wait_lock, flags); 845 spin_lock_irqsave(&priv->notif_wait_lock, flags);
878 list_for_each_entry(wait_entry, &priv->_agn.notif_waits, list) 846 list_for_each_entry(wait_entry, &priv->notif_waits, list)
879 wait_entry->aborted = true; 847 wait_entry->aborted = true;
880 spin_unlock_irqrestore(&priv->_agn.notif_wait_lock, flags); 848 spin_unlock_irqrestore(&priv->notif_wait_lock, flags);
881 849
882 wake_up_all(&priv->_agn.notif_waitq); 850 wake_up_all(&priv->notif_waitq);
883} 851}
884 852
885void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand) 853void iwlagn_fw_error(struct iwl_priv *priv, bool ondemand)
@@ -1018,8 +986,6 @@ void iwl_apm_stop(struct iwl_priv *priv)
1018int iwl_apm_init(struct iwl_priv *priv) 986int iwl_apm_init(struct iwl_priv *priv)
1019{ 987{
1020 int ret = 0; 988 int ret = 0;
1021 u16 lctl;
1022
1023 IWL_DEBUG_INFO(priv, "Init card's basic functions\n"); 989 IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
1024 990
1025 /* 991 /*
@@ -1048,27 +1014,7 @@ int iwl_apm_init(struct iwl_priv *priv)
1048 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1014 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1049 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 1015 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
1050 1016
1051 /* 1017 bus_apm_config(priv->bus);
1052 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
1053 * Check if BIOS (or OS) enabled L1-ASPM on this device.
1054 * If so (likely), disable L0S, so device moves directly L0->L1;
1055 * costs negligible amount of power savings.
1056 * If not (unlikely), enable L0S, so there is at least some
1057 * power savings, even without L1.
1058 */
1059 lctl = iwl_pcie_link_ctl(priv);
1060 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
1061 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
1062 /* L1-ASPM enabled; disable(!) L0S */
1063 iwl_set_bit(priv, CSR_GIO_REG,
1064 CSR_GIO_REG_VAL_L0S_ENABLED);
1065 IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
1066 } else {
1067 /* L1-ASPM disabled; enable(!) L0S */
1068 iwl_clear_bit(priv, CSR_GIO_REG,
1069 CSR_GIO_REG_VAL_L0S_ENABLED);
1070 IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
1071 }
1072 1018
1073 /* Configure analog phase-lock-loop before activating to D0A */ 1019 /* Configure analog phase-lock-loop before activating to D0A */
1074 if (priv->cfg->base_params->pll_cfg_val) 1020 if (priv->cfg->base_params->pll_cfg_val)
@@ -1127,9 +1073,6 @@ int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1127 if (priv->tx_power_user_lmt == tx_power && !force) 1073 if (priv->tx_power_user_lmt == tx_power && !force)
1128 return 0; 1074 return 0;
1129 1075
1130 if (!priv->cfg->ops->lib->send_tx_power)
1131 return -EOPNOTSUPP;
1132
1133 if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) { 1076 if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) {
1134 IWL_WARN(priv, 1077 IWL_WARN(priv,
1135 "Requested user TXPOWER %d below lower limit %d.\n", 1078 "Requested user TXPOWER %d below lower limit %d.\n",
@@ -1163,7 +1106,7 @@ int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
1163 prev_tx_power = priv->tx_power_user_lmt; 1106 prev_tx_power = priv->tx_power_user_lmt;
1164 priv->tx_power_user_lmt = tx_power; 1107 priv->tx_power_user_lmt = tx_power;
1165 1108
1166 ret = priv->cfg->ops->lib->send_tx_power(priv); 1109 ret = iwlagn_send_tx_power(priv);
1167 1110
1168 /* if fail to set tx_power, restore the orig. tx power */ 1111 /* if fail to set tx_power, restore the orig. tx power */
1169 if (ret) { 1112 if (ret) {
@@ -1182,7 +1125,7 @@ void iwl_send_bt_config(struct iwl_priv *priv)
1182 .kill_cts_mask = 0, 1125 .kill_cts_mask = 0,
1183 }; 1126 };
1184 1127
1185 if (!bt_coex_active) 1128 if (!iwlagn_mod_params.bt_coex_active)
1186 bt_cmd.flags = BT_COEX_DISABLE; 1129 bt_cmd.flags = BT_COEX_DISABLE;
1187 else 1130 else
1188 bt_cmd.flags = BT_COEX_ENABLE; 1131 bt_cmd.flags = BT_COEX_ENABLE;
@@ -1191,8 +1134,8 @@ void iwl_send_bt_config(struct iwl_priv *priv)
1191 IWL_DEBUG_INFO(priv, "BT coex %s\n", 1134 IWL_DEBUG_INFO(priv, "BT coex %s\n",
1192 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); 1135 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
1193 1136
1194 if (iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG, 1137 if (trans_send_cmd_pdu(&priv->trans, REPLY_BT_CONFIG,
1195 sizeof(struct iwl_bt_cmd), &bt_cmd)) 1138 CMD_SYNC, sizeof(struct iwl_bt_cmd), &bt_cmd))
1196 IWL_ERR(priv, "failed to send BT Coex Config\n"); 1139 IWL_ERR(priv, "failed to send BT Coex Config\n");
1197} 1140}
1198 1141
@@ -1204,11 +1147,13 @@ int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags, bool clear)
1204 }; 1147 };
1205 1148
1206 if (flags & CMD_ASYNC) 1149 if (flags & CMD_ASYNC)
1207 return iwl_send_cmd_pdu_async(priv, REPLY_STATISTICS_CMD, 1150 return trans_send_cmd_pdu(&priv->trans, REPLY_STATISTICS_CMD,
1151 CMD_ASYNC,
1208 sizeof(struct iwl_statistics_cmd), 1152 sizeof(struct iwl_statistics_cmd),
1209 &statistics_cmd, NULL); 1153 &statistics_cmd);
1210 else 1154 else
1211 return iwl_send_cmd_pdu(priv, REPLY_STATISTICS_CMD, 1155 return trans_send_cmd_pdu(&priv->trans, REPLY_STATISTICS_CMD,
1156 CMD_SYNC,
1212 sizeof(struct iwl_statistics_cmd), 1157 sizeof(struct iwl_statistics_cmd),
1213 &statistics_cmd); 1158 &statistics_cmd);
1214} 1159}
@@ -1275,10 +1220,9 @@ static int iwl_set_mode(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1275{ 1220{
1276 iwl_connection_init_rx_config(priv, ctx); 1221 iwl_connection_init_rx_config(priv, ctx);
1277 1222
1278 if (priv->cfg->ops->hcmd->set_rxon_chain) 1223 iwlagn_set_rxon_chain(priv, ctx);
1279 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
1280 1224
1281 return iwlcore_commit_rxon(priv, ctx); 1225 return iwlagn_commit_rxon(priv, ctx);
1282} 1226}
1283 1227
1284static int iwl_setup_interface(struct iwl_priv *priv, 1228static int iwl_setup_interface(struct iwl_priv *priv,
@@ -1431,26 +1375,6 @@ void iwl_mac_remove_interface(struct ieee80211_hw *hw,
1431 1375
1432} 1376}
1433 1377
1434int iwl_alloc_txq_mem(struct iwl_priv *priv)
1435{
1436 if (!priv->txq)
1437 priv->txq = kzalloc(
1438 sizeof(struct iwl_tx_queue) *
1439 priv->cfg->base_params->num_of_queues,
1440 GFP_KERNEL);
1441 if (!priv->txq) {
1442 IWL_ERR(priv, "Not enough memory for txq\n");
1443 return -ENOMEM;
1444 }
1445 return 0;
1446}
1447
1448void iwl_free_txq_mem(struct iwl_priv *priv)
1449{
1450 kfree(priv->txq);
1451 priv->txq = NULL;
1452}
1453
1454#ifdef CONFIG_IWLWIFI_DEBUGFS 1378#ifdef CONFIG_IWLWIFI_DEBUGFS
1455 1379
1456#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES) 1380#define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
@@ -1912,7 +1836,7 @@ void iwl_setup_watchdog(struct iwl_priv *priv)
1912{ 1836{
1913 unsigned int timeout = priv->cfg->base_params->wd_timeout; 1837 unsigned int timeout = priv->cfg->base_params->wd_timeout;
1914 1838
1915 if (timeout) 1839 if (timeout && !iwlagn_mod_params.wd_disable)
1916 mod_timer(&priv->watchdog, 1840 mod_timer(&priv->watchdog,
1917 jiffies + msecs_to_jiffies(IWL_WD_TICK(timeout))); 1841 jiffies + msecs_to_jiffies(IWL_WD_TICK(timeout)));
1918 else 1842 else
@@ -1973,35 +1897,28 @@ __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
1973 1897
1974#ifdef CONFIG_PM 1898#ifdef CONFIG_PM
1975 1899
1976int iwl_pci_suspend(struct device *device) 1900int iwl_suspend(struct iwl_priv *priv)
1977{ 1901{
1978 struct pci_dev *pdev = to_pci_dev(device);
1979 struct iwl_priv *priv = pci_get_drvdata(pdev);
1980
1981 /* 1902 /*
1982 * This function is called when system goes into suspend state 1903 * This function is called when system goes into suspend state
1983 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function 1904 * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
1984 * first but since iwl_mac_stop() has no knowledge of who the caller is, 1905 * first but since iwl_mac_stop() has no knowledge of who the caller is,
1985 * it will not call apm_ops.stop() to stop the DMA operation. 1906 * it will not call apm_ops.stop() to stop the DMA operation.
1986 * Calling apm_ops.stop here to make sure we stop the DMA. 1907 * Calling apm_ops.stop here to make sure we stop the DMA.
1908 *
1909 * But of course ... if we have configured WoWLAN then we did other
1910 * things already :-)
1987 */ 1911 */
1988 iwl_apm_stop(priv); 1912 if (!priv->wowlan)
1913 iwl_apm_stop(priv);
1989 1914
1990 return 0; 1915 return 0;
1991} 1916}
1992 1917
1993int iwl_pci_resume(struct device *device) 1918int iwl_resume(struct iwl_priv *priv)
1994{ 1919{
1995 struct pci_dev *pdev = to_pci_dev(device);
1996 struct iwl_priv *priv = pci_get_drvdata(pdev);
1997 bool hw_rfkill = false; 1920 bool hw_rfkill = false;
1998 1921
1999 /*
2000 * We disable the RETRY_TIMEOUT register (0x41) to keep
2001 * PCI Tx retries from interfering with C3 CPU state.
2002 */
2003 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2004
2005 iwl_enable_interrupts(priv); 1922 iwl_enable_interrupts(priv);
2006 1923
2007 if (!(iwl_read32(priv, CSR_GP_CNTRL) & 1924 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
@@ -2018,13 +1935,4 @@ int iwl_pci_resume(struct device *device)
2018 return 0; 1935 return 0;
2019} 1936}
2020 1937
2021const struct dev_pm_ops iwl_pm_ops = {
2022 .suspend = iwl_pci_suspend,
2023 .resume = iwl_pci_resume,
2024 .freeze = iwl_pci_suspend,
2025 .thaw = iwl_pci_resume,
2026 .poweroff = iwl_pci_suspend,
2027 .restore = iwl_pci_resume,
2028};
2029
2030#endif /* CONFIG_PM */ 1938#endif /* CONFIG_PM */
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h
index a54d416ec345..3e6bb734dcb7 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.h
+++ b/drivers/net/wireless/iwlwifi/iwl-core.h
@@ -76,95 +76,29 @@ struct iwl_cmd;
76#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation" 76#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
77#define DRV_AUTHOR "<ilw@linux.intel.com>" 77#define DRV_AUTHOR "<ilw@linux.intel.com>"
78 78
79#define IWL_PCI_DEVICE(dev, subdev, cfg) \
80 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
81 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
82 .driver_data = (kernel_ulong_t)&(cfg)
83
84#define TIME_UNIT 1024 79#define TIME_UNIT 1024
85 80
86#define IWL_SKU_G 0x1
87#define IWL_SKU_A 0x2
88#define IWL_SKU_N 0x8
89
90#define IWL_CMD(x) case x: return #x 81#define IWL_CMD(x) case x: return #x
91 82
92struct iwl_hcmd_ops {
93 int (*commit_rxon)(struct iwl_priv *priv, struct iwl_rxon_context *ctx);
94 void (*set_rxon_chain)(struct iwl_priv *priv,
95 struct iwl_rxon_context *ctx);
96 int (*set_tx_ant)(struct iwl_priv *priv, u8 valid_tx_ant);
97 void (*send_bt_config)(struct iwl_priv *priv);
98 int (*set_pan_params)(struct iwl_priv *priv);
99};
100
101struct iwl_hcmd_utils_ops {
102 u16 (*build_addsta_hcmd)(const struct iwl_addsta_cmd *cmd, u8 *data);
103 void (*gain_computation)(struct iwl_priv *priv,
104 u32 *average_noise,
105 u16 min_average_noise_antennat_i,
106 u32 min_average_noise,
107 u8 default_chain);
108 void (*chain_noise_reset)(struct iwl_priv *priv);
109 void (*tx_cmd_protection)(struct iwl_priv *priv,
110 struct ieee80211_tx_info *info,
111 __le16 fc, __le32 *tx_flags);
112 int (*calc_rssi)(struct iwl_priv *priv,
113 struct iwl_rx_phy_res *rx_resp);
114 int (*request_scan)(struct iwl_priv *priv, struct ieee80211_vif *vif);
115 void (*post_scan)(struct iwl_priv *priv);
116};
117
118struct iwl_apm_ops {
119 int (*init)(struct iwl_priv *priv);
120 void (*config)(struct iwl_priv *priv);
121};
122
123struct iwl_temp_ops {
124 void (*temperature)(struct iwl_priv *priv);
125};
126
127struct iwl_lib_ops { 83struct iwl_lib_ops {
128 /* set hw dependent parameters */ 84 /* set hw dependent parameters */
129 int (*set_hw_params)(struct iwl_priv *priv); 85 int (*set_hw_params)(struct iwl_priv *priv);
130 /* setup Rx handler */ 86 /* setup BT Rx handler */
131 void (*rx_handler_setup)(struct iwl_priv *priv); 87 void (*bt_rx_handler_setup)(struct iwl_priv *priv);
132 /* setup deferred work */ 88 /* setup BT related deferred work */
133 void (*setup_deferred_work)(struct iwl_priv *priv); 89 void (*bt_setup_deferred_work)(struct iwl_priv *priv);
134 /* cancel deferred work */ 90 /* cancel deferred work */
135 void (*cancel_deferred_work)(struct iwl_priv *priv); 91 void (*cancel_deferred_work)(struct iwl_priv *priv);
136 /* check validity of rtc data address */
137 int (*is_valid_rtc_data_addr)(u32 addr);
138 int (*set_channel_switch)(struct iwl_priv *priv, 92 int (*set_channel_switch)(struct iwl_priv *priv,
139 struct ieee80211_channel_switch *ch_switch); 93 struct ieee80211_channel_switch *ch_switch);
140 /* power management */ 94 /* device specific configuration */
141 struct iwl_apm_ops apm_ops; 95 void (*nic_config)(struct iwl_priv *priv);
142
143 /* power */
144 int (*send_tx_power) (struct iwl_priv *priv);
145 void (*update_chain_flags)(struct iwl_priv *priv);
146 96
147 /* eeprom operations (as defined in iwl-eeprom.h) */ 97 /* eeprom operations (as defined in iwl-eeprom.h) */
148 struct iwl_eeprom_ops eeprom_ops; 98 struct iwl_eeprom_ops eeprom_ops;
149 99
150 /* temperature */ 100 /* temperature */
151 struct iwl_temp_ops temp_ops; 101 void (*temperature)(struct iwl_priv *priv);
152
153 int (*txfifo_flush)(struct iwl_priv *priv, u16 flush_control);
154 void (*dev_txfifo_flush)(struct iwl_priv *priv, u16 flush_control);
155
156};
157
158/* NIC specific ops */
159struct iwl_nic_ops {
160 void (*additional_nic_config)(struct iwl_priv *priv);
161};
162
163struct iwl_ops {
164 const struct iwl_lib_ops *lib;
165 const struct iwl_hcmd_ops *hcmd;
166 const struct iwl_hcmd_utils_ops *utils;
167 const struct iwl_nic_ops *nic;
168}; 102};
169 103
170struct iwl_mod_params { 104struct iwl_mod_params {
@@ -176,6 +110,12 @@ struct iwl_mod_params {
176 int restart_fw; /* def: 1 = restart firmware */ 110 int restart_fw; /* def: 1 = restart firmware */
177 bool plcp_check; /* def: true = enable plcp health check */ 111 bool plcp_check; /* def: true = enable plcp health check */
178 bool ack_check; /* def: false = disable ack health check */ 112 bool ack_check; /* def: false = disable ack health check */
113 bool wd_disable; /* def: false = enable stuck queue check */
114 bool bt_coex_active; /* def: true = enable bt coex */
115 int led_mode; /* def: 0 = system default */
116 bool no_sleep_autoadjust; /* def: true = disable autoadjust */
117 bool power_save; /* def: false = disable power save */
118 int power_level; /* def: 1 = power level */
179}; 119};
180 120
181/* 121/*
@@ -225,7 +165,7 @@ struct iwl_base_params {
225 * @ampdu_factor: Maximum A-MPDU length factor 165 * @ampdu_factor: Maximum A-MPDU length factor
226 * @ampdu_density: Minimum A-MPDU spacing 166 * @ampdu_density: Minimum A-MPDU spacing
227 * @bt_sco_disable: uCode should not response to BT in SCO/ESCO mode 167 * @bt_sco_disable: uCode should not response to BT in SCO/ESCO mode
228*/ 168 */
229struct iwl_bt_params { 169struct iwl_bt_params {
230 bool advanced_bt_coexist; 170 bool advanced_bt_coexist;
231 u8 bt_init_traffic_load; 171 u8 bt_init_traffic_load;
@@ -238,19 +178,31 @@ struct iwl_bt_params {
238}; 178};
239/* 179/*
240 * @use_rts_for_aggregation: use rts/cts protection for HT traffic 180 * @use_rts_for_aggregation: use rts/cts protection for HT traffic
241*/ 181 */
242struct iwl_ht_params { 182struct iwl_ht_params {
243 const bool ht_greenfield_support; /* if used set to true */ 183 const bool ht_greenfield_support; /* if used set to true */
244 bool use_rts_for_aggregation; 184 bool use_rts_for_aggregation;
185 enum ieee80211_smps_mode smps_mode;
245}; 186};
246 187
247/** 188/**
248 * struct iwl_cfg 189 * struct iwl_cfg
190 * @name: Offical name of the device
249 * @fw_name_pre: Firmware filename prefix. The api version and extension 191 * @fw_name_pre: Firmware filename prefix. The api version and extension
250 * (.ucode) will be added to filename before loading from disk. The 192 * (.ucode) will be added to filename before loading from disk. The
251 * filename is constructed as fw_name_pre<api>.ucode. 193 * filename is constructed as fw_name_pre<api>.ucode.
252 * @ucode_api_max: Highest version of uCode API supported by driver. 194 * @ucode_api_max: Highest version of uCode API supported by driver.
253 * @ucode_api_min: Lowest version of uCode API supported by driver. 195 * @ucode_api_min: Lowest version of uCode API supported by driver.
196 * @valid_tx_ant: valid transmit antenna
197 * @valid_rx_ant: valid receive antenna
198 * @sku: sku information from EEPROM
199 * @eeprom_ver: EEPROM version
200 * @eeprom_calib_ver: EEPROM calibration version
201 * @lib: pointer to the lib ops
202 * @additional_nic_config: additional nic configuration
203 * @base_params: pointer to basic parameters
204 * @ht_params: point to ht patameters
205 * @bt_params: pointer to bt parameters
254 * @pa_type: used by 6000 series only to identify the type of Power Amplifier 206 * @pa_type: used by 6000 series only to identify the type of Power Amplifier
255 * @need_dc_calib: need to perform init dc calibration 207 * @need_dc_calib: need to perform init dc calibration
256 * @need_temp_offset_calib: need to perform temperature offset calibration 208 * @need_temp_offset_calib: need to perform temperature offset calibration
@@ -260,7 +212,6 @@ struct iwl_ht_params {
260 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity 212 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
261 * @internal_wimax_coex: internal wifi/wimax combo device 213 * @internal_wimax_coex: internal wifi/wimax combo device
262 * @iq_invert: I/Q inversion 214 * @iq_invert: I/Q inversion
263 * @disable_otp_refresh: disable OTP refresh current limit
264 * 215 *
265 * We enable the driver to be backward compatible wrt API version. The 216 * We enable the driver to be backward compatible wrt API version. The
266 * driver specifies which APIs it supports (with @ucode_api_max being the 217 * driver specifies which APIs it supports (with @ucode_api_max being the
@@ -277,11 +228,7 @@ struct iwl_ht_params {
277 * } 228 * }
278 * 229 *
279 * The ideal usage of this infrastructure is to treat a new ucode API 230 * The ideal usage of this infrastructure is to treat a new ucode API
280 * release as a new hardware revision. That is, through utilizing the 231 * release as a new hardware revision.
281 * iwl_hcmd_utils_ops etc. we accommodate different command structures
282 * and flows between hardware versions (4965/5000) as well as their API
283 * versions.
284 *
285 */ 232 */
286struct iwl_cfg { 233struct iwl_cfg {
287 /* params specific to an individual device within a device family */ 234 /* params specific to an individual device within a device family */
@@ -291,10 +238,11 @@ struct iwl_cfg {
291 const unsigned int ucode_api_min; 238 const unsigned int ucode_api_min;
292 u8 valid_tx_ant; 239 u8 valid_tx_ant;
293 u8 valid_rx_ant; 240 u8 valid_rx_ant;
294 unsigned int sku; 241 u16 sku;
295 u16 eeprom_ver; 242 u16 eeprom_ver;
296 u16 eeprom_calib_ver; 243 u16 eeprom_calib_ver;
297 const struct iwl_ops *ops; 244 const struct iwl_lib_ops *lib;
245 void (*additional_nic_config)(struct iwl_priv *priv);
298 /* params not likely to change within a device family */ 246 /* params not likely to change within a device family */
299 struct iwl_base_params *base_params; 247 struct iwl_base_params *base_params;
300 /* params likely to change within a device family */ 248 /* params likely to change within a device family */
@@ -309,7 +257,6 @@ struct iwl_cfg {
309 const bool rx_with_siso_diversity; 257 const bool rx_with_siso_diversity;
310 const bool internal_wimax_coex; 258 const bool internal_wimax_coex;
311 const bool iq_invert; 259 const bool iq_invert;
312 const bool disable_otp_refresh;
313}; 260};
314 261
315/*************************** 262/***************************
@@ -346,9 +293,6 @@ void iwl_mac_remove_interface(struct ieee80211_hw *hw,
346int iwl_mac_change_interface(struct ieee80211_hw *hw, 293int iwl_mac_change_interface(struct ieee80211_hw *hw,
347 struct ieee80211_vif *vif, 294 struct ieee80211_vif *vif,
348 enum nl80211_iftype newtype, bool newp2p); 295 enum nl80211_iftype newtype, bool newp2p);
349int iwl_alloc_txq_mem(struct iwl_priv *priv);
350void iwl_free_txq_mem(struct iwl_priv *priv);
351
352#ifdef CONFIG_IWLWIFI_DEBUGFS 296#ifdef CONFIG_IWLWIFI_DEBUGFS
353int iwl_alloc_traffic_mem(struct iwl_priv *priv); 297int iwl_alloc_traffic_mem(struct iwl_priv *priv);
354void iwl_free_traffic_mem(struct iwl_priv *priv); 298void iwl_free_traffic_mem(struct iwl_priv *priv);
@@ -390,28 +334,8 @@ static inline void iwl_update_stats(struct iwl_priv *priv, bool is_tx,
390/***************************************************** 334/*****************************************************
391* RX 335* RX
392******************************************************/ 336******************************************************/
393void iwl_cmd_queue_free(struct iwl_priv *priv);
394void iwl_cmd_queue_unmap(struct iwl_priv *priv);
395int iwl_rx_queue_alloc(struct iwl_priv *priv);
396void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
397 struct iwl_rx_queue *q);
398int iwl_rx_queue_space(const struct iwl_rx_queue *q);
399void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
400
401void iwl_chswitch_done(struct iwl_priv *priv, bool is_success); 337void iwl_chswitch_done(struct iwl_priv *priv, bool is_success);
402 338
403/* TX helpers */
404
405/*****************************************************
406* TX
407******************************************************/
408void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq);
409int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
410 int slots_num, u32 txq_id);
411void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
412 int slots_num, u32 txq_id);
413void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id);
414void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id);
415void iwl_setup_watchdog(struct iwl_priv *priv); 339void iwl_setup_watchdog(struct iwl_priv *priv);
416/***************************************************** 340/*****************************************************
417 * TX power 341 * TX power
@@ -419,13 +343,6 @@ void iwl_setup_watchdog(struct iwl_priv *priv);
419int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force); 343int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force);
420 344
421/******************************************************************************* 345/*******************************************************************************
422 * Rate
423 ******************************************************************************/
424
425u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv,
426 struct iwl_rxon_context *ctx);
427
428/*******************************************************************************
429 * Scanning 346 * Scanning
430 ******************************************************************************/ 347 ******************************************************************************/
431void iwl_init_scan_params(struct iwl_priv *priv); 348void iwl_init_scan_params(struct iwl_priv *priv);
@@ -469,51 +386,19 @@ int __must_check iwl_scan_initiate(struct iwl_priv *priv,
469 *****************************************************/ 386 *****************************************************/
470 387
471const char *get_cmd_string(u8 cmd); 388const char *get_cmd_string(u8 cmd);
472int __must_check iwl_send_cmd_sync(struct iwl_priv *priv,
473 struct iwl_host_cmd *cmd);
474int iwl_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
475int __must_check iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id,
476 u16 len, const void *data);
477int iwl_send_cmd_pdu_async(struct iwl_priv *priv, u8 id, u16 len,
478 const void *data,
479 void (*callback)(struct iwl_priv *priv,
480 struct iwl_device_cmd *cmd,
481 struct iwl_rx_packet *pkt));
482
483int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
484
485
486/*****************************************************
487 * PCI *
488 *****************************************************/
489
490static inline u16 iwl_pcie_link_ctl(struct iwl_priv *priv)
491{
492 int pos;
493 u16 pci_lnk_ctl;
494 pos = pci_find_capability(priv->pci_dev, PCI_CAP_ID_EXP);
495 pci_read_config_word(priv->pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
496 return pci_lnk_ctl;
497}
498
499void iwl_bg_watchdog(unsigned long data); 389void iwl_bg_watchdog(unsigned long data);
500u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval); 390u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval);
501__le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base, 391__le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
502 u32 addon, u32 beacon_interval); 392 u32 addon, u32 beacon_interval);
503 393
504#ifdef CONFIG_PM 394#ifdef CONFIG_PM
505int iwl_pci_suspend(struct device *device); 395int iwl_suspend(struct iwl_priv *priv);
506int iwl_pci_resume(struct device *device); 396int iwl_resume(struct iwl_priv *priv);
507extern const struct dev_pm_ops iwl_pm_ops;
508
509#define IWL_PM_OPS (&iwl_pm_ops)
510
511#else /* !CONFIG_PM */
512
513#define IWL_PM_OPS NULL
514
515#endif /* !CONFIG_PM */ 397#endif /* !CONFIG_PM */
516 398
399int iwl_probe(struct iwl_bus *bus, struct iwl_cfg *cfg);
400void __devexit iwl_remove(struct iwl_priv * priv);
401
517/***************************************************** 402/*****************************************************
518* Error Handling Debugging 403* Error Handling Debugging
519******************************************************/ 404******************************************************/
@@ -613,11 +498,7 @@ void iwl_apm_stop(struct iwl_priv *priv);
613int iwl_apm_init(struct iwl_priv *priv); 498int iwl_apm_init(struct iwl_priv *priv);
614 499
615int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx); 500int iwl_send_rxon_timing(struct iwl_priv *priv, struct iwl_rxon_context *ctx);
616static inline int iwlcore_commit_rxon(struct iwl_priv *priv, 501
617 struct iwl_rxon_context *ctx)
618{
619 return priv->cfg->ops->hcmd->commit_rxon(priv, ctx);
620}
621static inline const struct ieee80211_supported_band *iwl_get_hw_mode( 502static inline const struct ieee80211_supported_band *iwl_get_hw_mode(
622 struct iwl_priv *priv, enum ieee80211_band band) 503 struct iwl_priv *priv, enum ieee80211_band band)
623{ 504{
@@ -630,7 +511,6 @@ static inline bool iwl_advanced_bt_coexist(struct iwl_priv *priv)
630 priv->cfg->bt_params->advanced_bt_coexist; 511 priv->cfg->bt_params->advanced_bt_coexist;
631} 512}
632 513
633extern bool bt_coex_active;
634extern bool bt_siso_mode; 514extern bool bt_siso_mode;
635 515
636 516
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h
index 5ab90ba7a024..d6dbb0423045 100644
--- a/drivers/net/wireless/iwlwifi/iwl-csr.h
+++ b/drivers/net/wireless/iwlwifi/iwl-csr.h
@@ -351,6 +351,7 @@
351#define CSR_UCODE_SW_BIT_RFKILL (0x00000002) 351#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
352#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) 352#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
353#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) 353#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
354#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
354 355
355/* GP Driver */ 356/* GP Driver */
356#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) 357#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
diff --git a/drivers/net/wireless/iwlwifi/iwl-debug.h b/drivers/net/wireless/iwlwifi/iwl-debug.h
index 2824ccbcc1fc..f9a407e40aff 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debug.h
+++ b/drivers/net/wireless/iwlwifi/iwl-debug.h
@@ -32,10 +32,10 @@
32struct iwl_priv; 32struct iwl_priv;
33extern u32 iwl_debug_level; 33extern u32 iwl_debug_level;
34 34
35#define IWL_ERR(p, f, a...) dev_err(&((p)->pci_dev->dev), f, ## a) 35#define IWL_ERR(p, f, a...) dev_err(p->bus->dev, f, ## a)
36#define IWL_WARN(p, f, a...) dev_warn(&((p)->pci_dev->dev), f, ## a) 36#define IWL_WARN(p, f, a...) dev_warn(p->bus->dev, f, ## a)
37#define IWL_INFO(p, f, a...) dev_info(&((p)->pci_dev->dev), f, ## a) 37#define IWL_INFO(p, f, a...) dev_info(p->bus->dev, f, ## a)
38#define IWL_CRIT(p, f, a...) dev_crit(&((p)->pci_dev->dev), f, ## a) 38#define IWL_CRIT(p, f, a...) dev_crit(p->bus->dev, f, ## a)
39 39
40#define iwl_print_hex_error(priv, p, len) \ 40#define iwl_print_hex_error(priv, p, len) \
41do { \ 41do { \
@@ -78,8 +78,6 @@ static inline void iwl_print_hex_dump(struct iwl_priv *priv, int level,
78#ifdef CONFIG_IWLWIFI_DEBUGFS 78#ifdef CONFIG_IWLWIFI_DEBUGFS
79int iwl_dbgfs_register(struct iwl_priv *priv, const char *name); 79int iwl_dbgfs_register(struct iwl_priv *priv, const char *name);
80void iwl_dbgfs_unregister(struct iwl_priv *priv); 80void iwl_dbgfs_unregister(struct iwl_priv *priv);
81extern int iwl_dbgfs_statistics_flag(struct iwl_priv *priv, char *buf,
82 int bufsz);
83#else 81#else
84static inline int iwl_dbgfs_register(struct iwl_priv *priv, const char *name) 82static inline int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
85{ 83{
@@ -125,13 +123,13 @@ static inline void iwl_dbgfs_unregister(struct iwl_priv *priv)
125/* 0x00000F00 - 0x00000100 */ 123/* 0x00000F00 - 0x00000100 */
126#define IWL_DL_POWER (1 << 8) 124#define IWL_DL_POWER (1 << 8)
127#define IWL_DL_TEMP (1 << 9) 125#define IWL_DL_TEMP (1 << 9)
128#define IWL_DL_NOTIF (1 << 10) 126/* reserved (1 << 10) */
129#define IWL_DL_SCAN (1 << 11) 127#define IWL_DL_SCAN (1 << 11)
130/* 0x0000F000 - 0x00001000 */ 128/* 0x0000F000 - 0x00001000 */
131#define IWL_DL_ASSOC (1 << 12) 129#define IWL_DL_ASSOC (1 << 12)
132#define IWL_DL_DROP (1 << 13) 130#define IWL_DL_DROP (1 << 13)
133#define IWL_DL_TXPOWER (1 << 14) 131/* reserved (1 << 14) */
134#define IWL_DL_AP (1 << 15) 132#define IWL_DL_COEX (1 << 15)
135/* 0x000F0000 - 0x00010000 */ 133/* 0x000F0000 - 0x00010000 */
136#define IWL_DL_FW (1 << 16) 134#define IWL_DL_FW (1 << 16)
137#define IWL_DL_RF_KILL (1 << 17) 135#define IWL_DL_RF_KILL (1 << 17)
@@ -171,12 +169,10 @@ static inline void iwl_dbgfs_unregister(struct iwl_priv *priv)
171#define IWL_DEBUG_DROP(p, f, a...) IWL_DEBUG(p, IWL_DL_DROP, f, ## a) 169#define IWL_DEBUG_DROP(p, f, a...) IWL_DEBUG(p, IWL_DL_DROP, f, ## a)
172#define IWL_DEBUG_DROP_LIMIT(p, f, a...) \ 170#define IWL_DEBUG_DROP_LIMIT(p, f, a...) \
173 IWL_DEBUG_LIMIT(p, IWL_DL_DROP, f, ## a) 171 IWL_DEBUG_LIMIT(p, IWL_DL_DROP, f, ## a)
174#define IWL_DEBUG_AP(p, f, a...) IWL_DEBUG(p, IWL_DL_AP, f, ## a) 172#define IWL_DEBUG_COEX(p, f, a...) IWL_DEBUG(p, IWL_DL_COEX, f, ## a)
175#define IWL_DEBUG_TXPOWER(p, f, a...) IWL_DEBUG(p, IWL_DL_TXPOWER, f, ## a)
176#define IWL_DEBUG_RATE(p, f, a...) IWL_DEBUG(p, IWL_DL_RATE, f, ## a) 173#define IWL_DEBUG_RATE(p, f, a...) IWL_DEBUG(p, IWL_DL_RATE, f, ## a)
177#define IWL_DEBUG_RATE_LIMIT(p, f, a...) \ 174#define IWL_DEBUG_RATE_LIMIT(p, f, a...) \
178 IWL_DEBUG_LIMIT(p, IWL_DL_RATE, f, ## a) 175 IWL_DEBUG_LIMIT(p, IWL_DL_RATE, f, ## a)
179#define IWL_DEBUG_NOTIF(p, f, a...) IWL_DEBUG(p, IWL_DL_NOTIF, f, ## a)
180#define IWL_DEBUG_ASSOC(p, f, a...) \ 176#define IWL_DEBUG_ASSOC(p, f, a...) \
181 IWL_DEBUG(p, IWL_DL_ASSOC | IWL_DL_INFO, f, ## a) 177 IWL_DEBUG(p, IWL_DL_ASSOC | IWL_DL_INFO, f, ## a)
182#define IWL_DEBUG_ASSOC_LIMIT(p, f, a...) \ 178#define IWL_DEBUG_ASSOC_LIMIT(p, f, a...) \
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
index 0e6a04b739ad..ec1485b2d3fe 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
@@ -227,7 +227,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
227 /* default is to dump the entire data segment */ 227 /* default is to dump the entire data segment */
228 if (!priv->dbgfs_sram_offset && !priv->dbgfs_sram_len) { 228 if (!priv->dbgfs_sram_offset && !priv->dbgfs_sram_len) {
229 priv->dbgfs_sram_offset = 0x800000; 229 priv->dbgfs_sram_offset = 0x800000;
230 if (priv->ucode_type == UCODE_SUBTYPE_INIT) 230 if (priv->ucode_type == IWL_UCODE_INIT)
231 priv->dbgfs_sram_len = priv->ucode_init.data.len; 231 priv->dbgfs_sram_len = priv->ucode_init.data.len;
232 else 232 else
233 priv->dbgfs_sram_len = priv->ucode_rt.data.len; 233 priv->dbgfs_sram_len = priv->ucode_rt.data.len;
@@ -322,6 +322,19 @@ static ssize_t iwl_dbgfs_sram_write(struct file *file,
322 return count; 322 return count;
323} 323}
324 324
325static ssize_t iwl_dbgfs_wowlan_sram_read(struct file *file,
326 char __user *user_buf,
327 size_t count, loff_t *ppos)
328{
329 struct iwl_priv *priv = file->private_data;
330
331 if (!priv->wowlan_sram)
332 return -ENODATA;
333
334 return simple_read_from_buffer(user_buf, count, ppos,
335 priv->wowlan_sram,
336 priv->ucode_wowlan.data.len);
337}
325static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf, 338static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf,
326 size_t count, loff_t *ppos) 339 size_t count, loff_t *ppos)
327{ 340{
@@ -856,6 +869,7 @@ static ssize_t iwl_dbgfs_current_sleep_command_read(struct file *file,
856} 869}
857 870
858DEBUGFS_READ_WRITE_FILE_OPS(sram); 871DEBUGFS_READ_WRITE_FILE_OPS(sram);
872DEBUGFS_READ_FILE_OPS(wowlan_sram);
859DEBUGFS_READ_WRITE_FILE_OPS(log_event); 873DEBUGFS_READ_WRITE_FILE_OPS(log_event);
860DEBUGFS_READ_FILE_OPS(nvm); 874DEBUGFS_READ_FILE_OPS(nvm);
861DEBUGFS_READ_FILE_OPS(stations); 875DEBUGFS_READ_FILE_OPS(stations);
@@ -1915,121 +1929,121 @@ static ssize_t iwl_dbgfs_reply_tx_error_read(struct file *file,
1915 pos += scnprintf(buf + pos, bufsz - pos, "Statistics_TX_Error:\n"); 1929 pos += scnprintf(buf + pos, bufsz - pos, "Statistics_TX_Error:\n");
1916 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t\t%u\n", 1930 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t\t%u\n",
1917 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_DELAY), 1931 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_DELAY),
1918 priv->_agn.reply_tx_stats.pp_delay); 1932 priv->reply_tx_stats.pp_delay);
1919 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1933 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1920 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_FEW_BYTES), 1934 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_FEW_BYTES),
1921 priv->_agn.reply_tx_stats.pp_few_bytes); 1935 priv->reply_tx_stats.pp_few_bytes);
1922 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1936 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1923 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_BT_PRIO), 1937 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_BT_PRIO),
1924 priv->_agn.reply_tx_stats.pp_bt_prio); 1938 priv->reply_tx_stats.pp_bt_prio);
1925 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1939 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1926 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_QUIET_PERIOD), 1940 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_QUIET_PERIOD),
1927 priv->_agn.reply_tx_stats.pp_quiet_period); 1941 priv->reply_tx_stats.pp_quiet_period);
1928 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1942 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1929 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_CALC_TTAK), 1943 iwl_get_tx_fail_reason(TX_STATUS_POSTPONE_CALC_TTAK),
1930 priv->_agn.reply_tx_stats.pp_calc_ttak); 1944 priv->reply_tx_stats.pp_calc_ttak);
1931 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n", 1945 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n",
1932 iwl_get_tx_fail_reason( 1946 iwl_get_tx_fail_reason(
1933 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY), 1947 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY),
1934 priv->_agn.reply_tx_stats.int_crossed_retry); 1948 priv->reply_tx_stats.int_crossed_retry);
1935 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1949 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1936 iwl_get_tx_fail_reason(TX_STATUS_FAIL_SHORT_LIMIT), 1950 iwl_get_tx_fail_reason(TX_STATUS_FAIL_SHORT_LIMIT),
1937 priv->_agn.reply_tx_stats.short_limit); 1951 priv->reply_tx_stats.short_limit);
1938 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1952 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1939 iwl_get_tx_fail_reason(TX_STATUS_FAIL_LONG_LIMIT), 1953 iwl_get_tx_fail_reason(TX_STATUS_FAIL_LONG_LIMIT),
1940 priv->_agn.reply_tx_stats.long_limit); 1954 priv->reply_tx_stats.long_limit);
1941 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1955 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1942 iwl_get_tx_fail_reason(TX_STATUS_FAIL_FIFO_UNDERRUN), 1956 iwl_get_tx_fail_reason(TX_STATUS_FAIL_FIFO_UNDERRUN),
1943 priv->_agn.reply_tx_stats.fifo_underrun); 1957 priv->reply_tx_stats.fifo_underrun);
1944 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1958 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1945 iwl_get_tx_fail_reason(TX_STATUS_FAIL_DRAIN_FLOW), 1959 iwl_get_tx_fail_reason(TX_STATUS_FAIL_DRAIN_FLOW),
1946 priv->_agn.reply_tx_stats.drain_flow); 1960 priv->reply_tx_stats.drain_flow);
1947 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1961 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1948 iwl_get_tx_fail_reason(TX_STATUS_FAIL_RFKILL_FLUSH), 1962 iwl_get_tx_fail_reason(TX_STATUS_FAIL_RFKILL_FLUSH),
1949 priv->_agn.reply_tx_stats.rfkill_flush); 1963 priv->reply_tx_stats.rfkill_flush);
1950 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1964 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1951 iwl_get_tx_fail_reason(TX_STATUS_FAIL_LIFE_EXPIRE), 1965 iwl_get_tx_fail_reason(TX_STATUS_FAIL_LIFE_EXPIRE),
1952 priv->_agn.reply_tx_stats.life_expire); 1966 priv->reply_tx_stats.life_expire);
1953 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1967 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1954 iwl_get_tx_fail_reason(TX_STATUS_FAIL_DEST_PS), 1968 iwl_get_tx_fail_reason(TX_STATUS_FAIL_DEST_PS),
1955 priv->_agn.reply_tx_stats.dest_ps); 1969 priv->reply_tx_stats.dest_ps);
1956 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1970 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1957 iwl_get_tx_fail_reason(TX_STATUS_FAIL_HOST_ABORTED), 1971 iwl_get_tx_fail_reason(TX_STATUS_FAIL_HOST_ABORTED),
1958 priv->_agn.reply_tx_stats.host_abort); 1972 priv->reply_tx_stats.host_abort);
1959 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1973 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1960 iwl_get_tx_fail_reason(TX_STATUS_FAIL_BT_RETRY), 1974 iwl_get_tx_fail_reason(TX_STATUS_FAIL_BT_RETRY),
1961 priv->_agn.reply_tx_stats.pp_delay); 1975 priv->reply_tx_stats.pp_delay);
1962 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1976 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1963 iwl_get_tx_fail_reason(TX_STATUS_FAIL_STA_INVALID), 1977 iwl_get_tx_fail_reason(TX_STATUS_FAIL_STA_INVALID),
1964 priv->_agn.reply_tx_stats.sta_invalid); 1978 priv->reply_tx_stats.sta_invalid);
1965 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1979 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1966 iwl_get_tx_fail_reason(TX_STATUS_FAIL_FRAG_DROPPED), 1980 iwl_get_tx_fail_reason(TX_STATUS_FAIL_FRAG_DROPPED),
1967 priv->_agn.reply_tx_stats.frag_drop); 1981 priv->reply_tx_stats.frag_drop);
1968 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1982 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1969 iwl_get_tx_fail_reason(TX_STATUS_FAIL_TID_DISABLE), 1983 iwl_get_tx_fail_reason(TX_STATUS_FAIL_TID_DISABLE),
1970 priv->_agn.reply_tx_stats.tid_disable); 1984 priv->reply_tx_stats.tid_disable);
1971 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1985 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1972 iwl_get_tx_fail_reason(TX_STATUS_FAIL_FIFO_FLUSHED), 1986 iwl_get_tx_fail_reason(TX_STATUS_FAIL_FIFO_FLUSHED),
1973 priv->_agn.reply_tx_stats.fifo_flush); 1987 priv->reply_tx_stats.fifo_flush);
1974 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n", 1988 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n",
1975 iwl_get_tx_fail_reason( 1989 iwl_get_tx_fail_reason(
1976 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL), 1990 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL),
1977 priv->_agn.reply_tx_stats.insuff_cf_poll); 1991 priv->reply_tx_stats.insuff_cf_poll);
1978 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 1992 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1979 iwl_get_tx_fail_reason(TX_STATUS_FAIL_PASSIVE_NO_RX), 1993 iwl_get_tx_fail_reason(TX_STATUS_FAIL_PASSIVE_NO_RX),
1980 priv->_agn.reply_tx_stats.fail_hw_drop); 1994 priv->reply_tx_stats.fail_hw_drop);
1981 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n", 1995 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n",
1982 iwl_get_tx_fail_reason( 1996 iwl_get_tx_fail_reason(
1983 TX_STATUS_FAIL_NO_BEACON_ON_RADAR), 1997 TX_STATUS_FAIL_NO_BEACON_ON_RADAR),
1984 priv->_agn.reply_tx_stats.sta_color_mismatch); 1998 priv->reply_tx_stats.sta_color_mismatch);
1985 pos += scnprintf(buf + pos, bufsz - pos, "UNKNOWN:\t\t\t%u\n", 1999 pos += scnprintf(buf + pos, bufsz - pos, "UNKNOWN:\t\t\t%u\n",
1986 priv->_agn.reply_tx_stats.unknown); 2000 priv->reply_tx_stats.unknown);
1987 2001
1988 pos += scnprintf(buf + pos, bufsz - pos, 2002 pos += scnprintf(buf + pos, bufsz - pos,
1989 "\nStatistics_Agg_TX_Error:\n"); 2003 "\nStatistics_Agg_TX_Error:\n");
1990 2004
1991 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 2005 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1992 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_UNDERRUN_MSK), 2006 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_UNDERRUN_MSK),
1993 priv->_agn.reply_agg_tx_stats.underrun); 2007 priv->reply_agg_tx_stats.underrun);
1994 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 2008 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1995 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_BT_PRIO_MSK), 2009 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_BT_PRIO_MSK),
1996 priv->_agn.reply_agg_tx_stats.bt_prio); 2010 priv->reply_agg_tx_stats.bt_prio);
1997 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 2011 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
1998 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_FEW_BYTES_MSK), 2012 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_FEW_BYTES_MSK),
1999 priv->_agn.reply_agg_tx_stats.few_bytes); 2013 priv->reply_agg_tx_stats.few_bytes);
2000 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 2014 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
2001 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_ABORT_MSK), 2015 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_ABORT_MSK),
2002 priv->_agn.reply_agg_tx_stats.abort); 2016 priv->reply_agg_tx_stats.abort);
2003 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n", 2017 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n",
2004 iwl_get_agg_tx_fail_reason( 2018 iwl_get_agg_tx_fail_reason(
2005 AGG_TX_STATE_LAST_SENT_TTL_MSK), 2019 AGG_TX_STATE_LAST_SENT_TTL_MSK),
2006 priv->_agn.reply_agg_tx_stats.last_sent_ttl); 2020 priv->reply_agg_tx_stats.last_sent_ttl);
2007 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n", 2021 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n",
2008 iwl_get_agg_tx_fail_reason( 2022 iwl_get_agg_tx_fail_reason(
2009 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK), 2023 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK),
2010 priv->_agn.reply_agg_tx_stats.last_sent_try); 2024 priv->reply_agg_tx_stats.last_sent_try);
2011 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n", 2025 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n",
2012 iwl_get_agg_tx_fail_reason( 2026 iwl_get_agg_tx_fail_reason(
2013 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK), 2027 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK),
2014 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill); 2028 priv->reply_agg_tx_stats.last_sent_bt_kill);
2015 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 2029 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
2016 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_SCD_QUERY_MSK), 2030 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_SCD_QUERY_MSK),
2017 priv->_agn.reply_agg_tx_stats.scd_query); 2031 priv->reply_agg_tx_stats.scd_query);
2018 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n", 2032 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t%u\n",
2019 iwl_get_agg_tx_fail_reason( 2033 iwl_get_agg_tx_fail_reason(
2020 AGG_TX_STATE_TEST_BAD_CRC32_MSK), 2034 AGG_TX_STATE_TEST_BAD_CRC32_MSK),
2021 priv->_agn.reply_agg_tx_stats.bad_crc32); 2035 priv->reply_agg_tx_stats.bad_crc32);
2022 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 2036 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
2023 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_RESPONSE_MSK), 2037 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_RESPONSE_MSK),
2024 priv->_agn.reply_agg_tx_stats.response); 2038 priv->reply_agg_tx_stats.response);
2025 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 2039 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
2026 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_DUMP_TX_MSK), 2040 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_DUMP_TX_MSK),
2027 priv->_agn.reply_agg_tx_stats.dump_tx); 2041 priv->reply_agg_tx_stats.dump_tx);
2028 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n", 2042 pos += scnprintf(buf + pos, bufsz - pos, "%s:\t\t\t%u\n",
2029 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_DELAY_TX_MSK), 2043 iwl_get_agg_tx_fail_reason(AGG_TX_STATE_DELAY_TX_MSK),
2030 priv->_agn.reply_agg_tx_stats.delay_tx); 2044 priv->reply_agg_tx_stats.delay_tx);
2031 pos += scnprintf(buf + pos, bufsz - pos, "UNKNOWN:\t\t\t%u\n", 2045 pos += scnprintf(buf + pos, bufsz - pos, "UNKNOWN:\t\t\t%u\n",
2032 priv->_agn.reply_agg_tx_stats.unknown); 2046 priv->reply_agg_tx_stats.unknown);
2033 2047
2034 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2048 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2035 kfree(buf); 2049 kfree(buf);
@@ -2493,7 +2507,7 @@ static ssize_t iwl_dbgfs_txfifo_flush_write(struct file *file,
2493 if (iwl_is_rfkill(priv)) 2507 if (iwl_is_rfkill(priv))
2494 return -EFAULT; 2508 return -EFAULT;
2495 2509
2496 priv->cfg->ops->lib->dev_txfifo_flush(priv, IWL_DROP_ALL); 2510 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
2497 2511
2498 return count; 2512 return count;
2499} 2513}
@@ -2667,6 +2681,7 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
2667 2681
2668 DEBUGFS_ADD_FILE(nvm, dir_data, S_IRUSR); 2682 DEBUGFS_ADD_FILE(nvm, dir_data, S_IRUSR);
2669 DEBUGFS_ADD_FILE(sram, dir_data, S_IWUSR | S_IRUSR); 2683 DEBUGFS_ADD_FILE(sram, dir_data, S_IWUSR | S_IRUSR);
2684 DEBUGFS_ADD_FILE(wowlan_sram, dir_data, S_IRUSR);
2670 DEBUGFS_ADD_FILE(log_event, dir_data, S_IWUSR | S_IRUSR); 2685 DEBUGFS_ADD_FILE(log_event, dir_data, S_IWUSR | S_IRUSR);
2671 DEBUGFS_ADD_FILE(stations, dir_data, S_IRUSR); 2686 DEBUGFS_ADD_FILE(stations, dir_data, S_IRUSR);
2672 DEBUGFS_ADD_FILE(channels, dir_data, S_IRUSR); 2687 DEBUGFS_ADD_FILE(channels, dir_data, S_IRUSR);
@@ -2693,8 +2708,7 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
2693 DEBUGFS_ADD_FILE(ucode_rx_stats, dir_debug, S_IRUSR); 2708 DEBUGFS_ADD_FILE(ucode_rx_stats, dir_debug, S_IRUSR);
2694 DEBUGFS_ADD_FILE(ucode_tx_stats, dir_debug, S_IRUSR); 2709 DEBUGFS_ADD_FILE(ucode_tx_stats, dir_debug, S_IRUSR);
2695 DEBUGFS_ADD_FILE(ucode_general_stats, dir_debug, S_IRUSR); 2710 DEBUGFS_ADD_FILE(ucode_general_stats, dir_debug, S_IRUSR);
2696 if (priv->cfg->ops->lib->dev_txfifo_flush) 2711 DEBUGFS_ADD_FILE(txfifo_flush, dir_debug, S_IWUSR);
2697 DEBUGFS_ADD_FILE(txfifo_flush, dir_debug, S_IWUSR);
2698 DEBUGFS_ADD_FILE(protection_mode, dir_debug, S_IWUSR | S_IRUSR); 2712 DEBUGFS_ADD_FILE(protection_mode, dir_debug, S_IWUSR | S_IRUSR);
2699 2713
2700 DEBUGFS_ADD_FILE(sensitivity, dir_debug, S_IRUSR); 2714 DEBUGFS_ADD_FILE(sensitivity, dir_debug, S_IRUSR);
diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h
index c8de236c141b..6c9790cac8d0 100644
--- a/drivers/net/wireless/iwlwifi/iwl-dev.h
+++ b/drivers/net/wireless/iwlwifi/iwl-dev.h
@@ -31,6 +31,7 @@
31#ifndef __iwl_dev_h__ 31#ifndef __iwl_dev_h__
32#define __iwl_dev_h__ 32#define __iwl_dev_h__
33 33
34#include <linux/interrupt.h>
34#include <linux/pci.h> /* for struct pci_device_id */ 35#include <linux/pci.h> /* for struct pci_device_id */
35#include <linux/kernel.h> 36#include <linux/kernel.h>
36#include <linux/wait.h> 37#include <linux/wait.h>
@@ -47,6 +48,10 @@
47#include "iwl-power.h" 48#include "iwl-power.h"
48#include "iwl-agn-rs.h" 49#include "iwl-agn-rs.h"
49#include "iwl-agn-tt.h" 50#include "iwl-agn-tt.h"
51#include "iwl-bus.h"
52#include "iwl-trans.h"
53
54#define DRV_NAME "iwlagn"
50 55
51struct iwl_tx_queue; 56struct iwl_tx_queue;
52 57
@@ -257,11 +262,9 @@ struct iwl_channel_info {
257 262
258enum { 263enum {
259 CMD_SYNC = 0, 264 CMD_SYNC = 0,
260 CMD_SIZE_NORMAL = 0, 265 CMD_ASYNC = BIT(0),
261 CMD_NO_SKB = 0, 266 CMD_WANT_SKB = BIT(1),
262 CMD_ASYNC = (1 << 1), 267 CMD_ON_DEMAND = BIT(2),
263 CMD_WANT_SKB = (1 << 2),
264 CMD_MAPPED = (1 << 3),
265}; 268};
266 269
267#define DEF_CMD_PAYLOAD_SIZE 320 270#define DEF_CMD_PAYLOAD_SIZE 320
@@ -294,6 +297,16 @@ enum iwl_hcmd_dataflag {
294 IWL_HCMD_DFL_NOCOPY = BIT(0), 297 IWL_HCMD_DFL_NOCOPY = BIT(0),
295}; 298};
296 299
300/**
301 * struct iwl_host_cmd - Host command to the uCode
302 * @data: array of chunks that composes the data of the host command
303 * @reply_page: pointer to the page that holds the response to the host command
304 * @callback:
305 * @flags: can be CMD_* note CMD_WANT_SKB is incompatible withe CMD_ASYNC
306 * @len: array of the lenths of the chunks in data
307 * @dataflags:
308 * @id: id of the host command
309 */
297struct iwl_host_cmd { 310struct iwl_host_cmd {
298 const void *data[IWL_MAX_CMD_TFDS]; 311 const void *data[IWL_MAX_CMD_TFDS];
299 unsigned long reply_page; 312 unsigned long reply_page;
@@ -385,13 +398,6 @@ struct iwl_tid_data {
385 struct iwl_ht_agg agg; 398 struct iwl_ht_agg agg;
386}; 399};
387 400
388struct iwl_hw_key {
389 u32 cipher;
390 int keylen;
391 u8 keyidx;
392 u8 key[32];
393};
394
395union iwl_ht_rate_supp { 401union iwl_ht_rate_supp {
396 u16 rates; 402 u16 rates;
397 struct { 403 struct {
@@ -444,7 +450,6 @@ struct iwl_station_entry {
444 struct iwl_addsta_cmd sta; 450 struct iwl_addsta_cmd sta;
445 struct iwl_tid_data tid[MAX_TID_COUNT]; 451 struct iwl_tid_data tid[MAX_TID_COUNT];
446 u8 used, ctxid; 452 u8 used, ctxid;
447 struct iwl_hw_key keyinfo;
448 struct iwl_link_quality_cmd *lq; 453 struct iwl_link_quality_cmd *lq;
449}; 454};
450 455
@@ -547,7 +552,8 @@ enum iwl_ucode_tlv_type {
547 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13, 552 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
548 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14, 553 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
549 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15, 554 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
550 /* 16 and 17 reserved for future use */ 555 IWL_UCODE_TLV_WOWLAN_INST = 16,
556 IWL_UCODE_TLV_WOWLAN_DATA = 17,
551 IWL_UCODE_TLV_FLAGS = 18, 557 IWL_UCODE_TLV_FLAGS = 18,
552}; 558};
553 559
@@ -631,7 +637,6 @@ struct iwl_sensitivity_ranges {
631/** 637/**
632 * struct iwl_hw_params 638 * struct iwl_hw_params
633 * @max_txq_num: Max # Tx queues supported 639 * @max_txq_num: Max # Tx queues supported
634 * @dma_chnl_num: Number of Tx DMA/FIFO channels
635 * @scd_bc_tbls_size: size of scheduler byte count tables 640 * @scd_bc_tbls_size: size of scheduler byte count tables
636 * @tfd_size: TFD size 641 * @tfd_size: TFD size
637 * @tx/rx_chains_num: Number of TX/RX chains 642 * @tx/rx_chains_num: Number of TX/RX chains
@@ -653,7 +658,6 @@ struct iwl_sensitivity_ranges {
653 */ 658 */
654struct iwl_hw_params { 659struct iwl_hw_params {
655 u8 max_txq_num; 660 u8 max_txq_num;
656 u8 dma_chnl_num;
657 u16 scd_bc_tbls_size; 661 u16 scd_bc_tbls_size;
658 u32 tfd_size; 662 u32 tfd_size;
659 u8 tx_chains_num; 663 u8 tx_chains_num;
@@ -663,7 +667,6 @@ struct iwl_hw_params {
663 u16 max_rxq_size; 667 u16 max_rxq_size;
664 u16 max_rxq_log; 668 u16 max_rxq_log;
665 u32 rx_page_order; 669 u32 rx_page_order;
666 u32 rx_wrt_ptr_reg;
667 u8 max_stations; 670 u8 max_stations;
668 u8 ht40_channel; 671 u8 ht40_channel;
669 u8 max_beacon_itrvl; /* in 1024 ms */ 672 u8 max_beacon_itrvl; /* in 1024 ms */
@@ -694,8 +697,6 @@ struct iwl_hw_params {
694 ****************************************************************************/ 697 ****************************************************************************/
695extern void iwl_update_chain_flags(struct iwl_priv *priv); 698extern void iwl_update_chain_flags(struct iwl_priv *priv);
696extern const u8 iwl_bcast_addr[ETH_ALEN]; 699extern const u8 iwl_bcast_addr[ETH_ALEN];
697extern int iwl_rxq_stop(struct iwl_priv *priv);
698extern void iwl_txq_ctx_stop(struct iwl_priv *priv);
699extern int iwl_queue_space(const struct iwl_queue *q); 700extern int iwl_queue_space(const struct iwl_queue *q);
700static inline int iwl_queue_used(const struct iwl_queue *q, int i) 701static inline int iwl_queue_used(const struct iwl_queue *q, int i)
701{ 702{
@@ -1152,6 +1153,8 @@ struct iwl_rxon_context {
1152 1153
1153 __le32 station_flags; 1154 __le32 station_flags;
1154 1155
1156 int beacon_int;
1157
1155 struct { 1158 struct {
1156 bool non_gf_sta_present; 1159 bool non_gf_sta_present;
1157 u8 protection; 1160 u8 protection;
@@ -1168,14 +1171,29 @@ enum iwl_scan_type {
1168 IWL_SCAN_OFFCH_TX, 1171 IWL_SCAN_OFFCH_TX,
1169}; 1172};
1170 1173
1174enum iwlagn_ucode_type {
1175 IWL_UCODE_NONE,
1176 IWL_UCODE_REGULAR,
1177 IWL_UCODE_INIT,
1178 IWL_UCODE_WOWLAN,
1179};
1180
1171#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL 1181#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1172struct iwl_testmode_trace { 1182struct iwl_testmode_trace {
1183 u32 buff_size;
1184 u32 total_size;
1185 u32 num_chunks;
1173 u8 *cpu_addr; 1186 u8 *cpu_addr;
1174 u8 *trace_addr; 1187 u8 *trace_addr;
1175 dma_addr_t dma_addr; 1188 dma_addr_t dma_addr;
1176 bool trace_enabled; 1189 bool trace_enabled;
1177}; 1190};
1178#endif 1191#endif
1192
1193/* uCode ownership */
1194#define IWL_OWNERSHIP_DRIVER 0
1195#define IWL_OWNERSHIP_TM 1
1196
1179struct iwl_priv { 1197struct iwl_priv {
1180 1198
1181 /* ieee device used by generic ieee processing code */ 1199 /* ieee device used by generic ieee processing code */
@@ -1243,11 +1261,8 @@ struct iwl_priv {
1243 spinlock_t reg_lock; /* protect hw register access */ 1261 spinlock_t reg_lock; /* protect hw register access */
1244 struct mutex mutex; 1262 struct mutex mutex;
1245 1263
1246 /* basic pci-network driver stuff */ 1264 struct iwl_bus *bus; /* bus specific data */
1247 struct pci_dev *pci_dev; 1265 struct iwl_trans trans;
1248
1249 /* pci hardware address support */
1250 void __iomem *hw_base;
1251 1266
1252 /* microcode/device supports multiple contexts */ 1267 /* microcode/device supports multiple contexts */
1253 u8 valid_contexts; 1268 u8 valid_contexts;
@@ -1267,10 +1282,15 @@ struct iwl_priv {
1267 int fw_index; /* firmware we're trying to load */ 1282 int fw_index; /* firmware we're trying to load */
1268 u32 ucode_ver; /* version of ucode, copy of 1283 u32 ucode_ver; /* version of ucode, copy of
1269 iwl_ucode.ver */ 1284 iwl_ucode.ver */
1285
1286 /* uCode owner: default: IWL_OWNERSHIP_DRIVER */
1287 u8 ucode_owner;
1288
1270 struct fw_img ucode_rt; 1289 struct fw_img ucode_rt;
1271 struct fw_img ucode_init; 1290 struct fw_img ucode_init;
1291 struct fw_img ucode_wowlan;
1272 1292
1273 enum iwlagn_ucode_subtype ucode_type; 1293 enum iwlagn_ucode_type ucode_type;
1274 u8 ucode_write_complete; /* the image write is complete */ 1294 u8 ucode_write_complete; /* the image write is complete */
1275 char firmware_name[25]; 1295 char firmware_name[25];
1276 1296
@@ -1341,6 +1361,8 @@ struct iwl_priv {
1341 1361
1342 u8 mac80211_registered; 1362 u8 mac80211_registered;
1343 1363
1364 bool wowlan;
1365
1344 /* eeprom -- this is in the card's little endian byte order */ 1366 /* eeprom -- this is in the card's little endian byte order */
1345 u8 *eeprom; 1367 u8 *eeprom;
1346 int nvm_device_type; 1368 int nvm_device_type;
@@ -1376,56 +1398,54 @@ struct iwl_priv {
1376 } accum_stats, delta_stats, max_delta_stats; 1398 } accum_stats, delta_stats, max_delta_stats;
1377#endif 1399#endif
1378 1400
1379 struct { 1401 /* INT ICT Table */
1380 /* INT ICT Table */ 1402 __le32 *ict_tbl;
1381 __le32 *ict_tbl; 1403 void *ict_tbl_vir;
1382 void *ict_tbl_vir; 1404 dma_addr_t ict_tbl_dma;
1383 dma_addr_t ict_tbl_dma; 1405 dma_addr_t aligned_ict_tbl_dma;
1384 dma_addr_t aligned_ict_tbl_dma; 1406 int ict_index;
1385 int ict_index; 1407 u32 inta;
1386 u32 inta; 1408 bool use_ict;
1387 bool use_ict; 1409 /*
1388 /* 1410 * reporting the number of tids has AGG on. 0 means
1389 * reporting the number of tids has AGG on. 0 means 1411 * no AGGREGATION
1390 * no AGGREGATION 1412 */
1391 */ 1413 u8 agg_tids_count;
1392 u8 agg_tids_count; 1414
1393 1415 struct iwl_rx_phy_res last_phy_res;
1394 struct iwl_rx_phy_res last_phy_res; 1416 bool last_phy_res_valid;
1395 bool last_phy_res_valid; 1417
1396 1418 struct completion firmware_loading_complete;
1397 struct completion firmware_loading_complete; 1419
1398 1420 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1399 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; 1421 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1400 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; 1422
1401 1423 /*
1402 /* 1424 * chain noise reset and gain commands are the
1403 * chain noise reset and gain commands are the 1425 * two extra calibration commands follows the standard
1404 * two extra calibration commands follows the standard 1426 * phy calibration commands
1405 * phy calibration commands 1427 */
1406 */ 1428 u8 phy_calib_chain_noise_reset_cmd;
1407 u8 phy_calib_chain_noise_reset_cmd; 1429 u8 phy_calib_chain_noise_gain_cmd;
1408 u8 phy_calib_chain_noise_gain_cmd; 1430
1409 1431 /* counts reply_tx error */
1410 /* counts reply_tx error */ 1432 struct reply_tx_error_statistics reply_tx_stats;
1411 struct reply_tx_error_statistics reply_tx_stats; 1433 struct reply_agg_tx_error_statistics reply_agg_tx_stats;
1412 struct reply_agg_tx_error_statistics reply_agg_tx_stats; 1434 /* notification wait support */
1413 /* notification wait support */ 1435 struct list_head notif_waits;
1414 struct list_head notif_waits; 1436 spinlock_t notif_wait_lock;
1415 spinlock_t notif_wait_lock; 1437 wait_queue_head_t notif_waitq;
1416 wait_queue_head_t notif_waitq; 1438
1417 1439 /* remain-on-channel offload support */
1418 /* remain-on-channel offload support */ 1440 struct ieee80211_channel *hw_roc_channel;
1419 struct ieee80211_channel *hw_roc_channel; 1441 struct delayed_work hw_roc_work;
1420 struct delayed_work hw_roc_work; 1442 enum nl80211_channel_type hw_roc_chantype;
1421 enum nl80211_channel_type hw_roc_chantype; 1443 int hw_roc_duration;
1422 int hw_roc_duration; 1444 bool hw_roc_setup;
1423 bool hw_roc_setup; 1445
1424 1446 struct sk_buff *offchan_tx_skb;
1425 struct sk_buff *offchan_tx_skb; 1447 int offchan_tx_timeout;
1426 int offchan_tx_timeout; 1448 struct ieee80211_channel *offchan_tx_chan;
1427 struct ieee80211_channel *offchan_tx_chan;
1428 } _agn;
1429 1449
1430 /* bt coex */ 1450 /* bt coex */
1431 u8 bt_enable_flag; 1451 u8 bt_enable_flag;
@@ -1442,6 +1462,9 @@ struct iwl_priv {
1442 u16 dynamic_frag_thresh; 1462 u16 dynamic_frag_thresh;
1443 u8 bt_ci_compliance; 1463 u8 bt_ci_compliance;
1444 struct work_struct bt_traffic_change_work; 1464 struct work_struct bt_traffic_change_work;
1465 bool bt_enable_pspoll;
1466 struct iwl_rxon_context *cur_rssi_ctx;
1467 bool bt_is_sco;
1445 1468
1446 struct iwl_hw_params hw_params; 1469 struct iwl_hw_params hw_params;
1447 1470
@@ -1492,6 +1515,7 @@ struct iwl_priv {
1492 struct dentry *debugfs_dir; 1515 struct dentry *debugfs_dir;
1493 u32 dbgfs_sram_offset, dbgfs_sram_len; 1516 u32 dbgfs_sram_offset, dbgfs_sram_len;
1494 bool disable_ht40; 1517 bool disable_ht40;
1518 void *wowlan_sram;
1495#endif /* CONFIG_IWLWIFI_DEBUGFS */ 1519#endif /* CONFIG_IWLWIFI_DEBUGFS */
1496 1520
1497 struct work_struct txpower_work; 1521 struct work_struct txpower_work;
@@ -1509,9 +1533,14 @@ struct iwl_priv {
1509 bool led_registered; 1533 bool led_registered;
1510#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL 1534#ifdef CONFIG_IWLWIFI_DEVICE_SVTOOL
1511 struct iwl_testmode_trace testmode_trace; 1535 struct iwl_testmode_trace testmode_trace;
1536 u32 tm_fixed_rate;
1512#endif 1537#endif
1513 u32 dbg_fixed_rate;
1514 1538
1539 /* WoWLAN GTK rekey data */
1540 u8 kck[NL80211_KCK_LEN], kek[NL80211_KEK_LEN];
1541 __le64 replay_ctr;
1542 __le16 last_seq_ctl;
1543 bool have_rekey_data;
1515}; /*iwl_priv */ 1544}; /*iwl_priv */
1516 1545
1517static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id) 1546static inline void iwl_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index 47a56bc1cd12..19d31a5e32e5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -407,11 +407,6 @@ static int iwl_find_otp_image(struct iwl_priv *priv,
407 return -EINVAL; 407 return -EINVAL;
408} 408}
409 409
410const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
411{
412 return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
413}
414
415u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset) 410u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
416{ 411{
417 if (!priv->eeprom) 412 if (!priv->eeprom)
@@ -449,7 +444,7 @@ int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev)
449 } 444 }
450 e = (__le16 *)priv->eeprom; 445 e = (__le16 *)priv->eeprom;
451 446
452 priv->cfg->ops->lib->apm_ops.init(priv); 447 iwl_apm_init(priv);
453 448
454 ret = iwl_eeprom_verify_signature(priv); 449 ret = iwl_eeprom_verify_signature(priv);
455 if (ret < 0) { 450 if (ret < 0) {
@@ -548,7 +543,7 @@ static void iwl_init_band_reference(const struct iwl_priv *priv,
548 const struct iwl_eeprom_channel **eeprom_ch_info, 543 const struct iwl_eeprom_channel **eeprom_ch_info,
549 const u8 **eeprom_ch_index) 544 const u8 **eeprom_ch_index)
550{ 545{
551 u32 offset = priv->cfg->ops->lib-> 546 u32 offset = priv->cfg->lib->
552 eeprom_ops.regulatory_bands[eep_band - 1]; 547 eeprom_ops.regulatory_bands[eep_band - 1];
553 switch (eep_band) { 548 switch (eep_band) {
554 case 1: /* 2.4GHz band */ 549 case 1: /* 2.4GHz band */
@@ -754,9 +749,9 @@ int iwl_init_channel_map(struct iwl_priv *priv)
754 } 749 }
755 750
756 /* Check if we do have HT40 channels */ 751 /* Check if we do have HT40 channels */
757 if (priv->cfg->ops->lib->eeprom_ops.regulatory_bands[5] == 752 if (priv->cfg->lib->eeprom_ops.regulatory_bands[5] ==
758 EEPROM_REGULATORY_BAND_NO_HT40 && 753 EEPROM_REGULATORY_BAND_NO_HT40 &&
759 priv->cfg->ops->lib->eeprom_ops.regulatory_bands[6] == 754 priv->cfg->lib->eeprom_ops.regulatory_bands[6] ==
760 EEPROM_REGULATORY_BAND_NO_HT40) 755 EEPROM_REGULATORY_BAND_NO_HT40)
761 return 0; 756 return 0;
762 757
@@ -792,8 +787,8 @@ int iwl_init_channel_map(struct iwl_priv *priv)
792 * driver need to process addition information 787 * driver need to process addition information
793 * to determine the max channel tx power limits 788 * to determine the max channel tx power limits
794 */ 789 */
795 if (priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower) 790 if (priv->cfg->lib->eeprom_ops.update_enhanced_txpower)
796 priv->cfg->ops->lib->eeprom_ops.update_enhanced_txpower(priv); 791 priv->cfg->lib->eeprom_ops.update_enhanced_txpower(priv);
797 792
798 return 0; 793 return 0;
799} 794}
@@ -834,3 +829,28 @@ const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
834 829
835 return NULL; 830 return NULL;
836} 831}
832
833void iwl_rf_config(struct iwl_priv *priv)
834{
835 u16 radio_cfg;
836
837 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
838
839 /* write radio config values to register */
840 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) <= EEPROM_RF_CONFIG_TYPE_MAX) {
841 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
842 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
843 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
844 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
845 IWL_INFO(priv, "Radio type=0x%x-0x%x-0x%x\n",
846 EEPROM_RF_CFG_TYPE_MSK(radio_cfg),
847 EEPROM_RF_CFG_STEP_MSK(radio_cfg),
848 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
849 } else
850 WARN_ON(1);
851
852 /* set CSR_HW_CONFIG_REG for uCode use */
853 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
854 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
855 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
856}
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.h b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
index c960c6fa009b..e4bf8ac5e64e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.h
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
@@ -110,12 +110,10 @@ enum {
110}; 110};
111 111
112/* SKU Capabilities */ 112/* SKU Capabilities */
113/* 5000 and up */ 113#define EEPROM_SKU_CAP_BAND_24GHZ (1 << 4)
114#define EEPROM_SKU_CAP_BAND_POS (4) 114#define EEPROM_SKU_CAP_BAND_52GHZ (1 << 5)
115#define EEPROM_SKU_CAP_BAND_SELECTION \
116 (3 << EEPROM_SKU_CAP_BAND_POS)
117#define EEPROM_SKU_CAP_11N_ENABLE (1 << 6) 115#define EEPROM_SKU_CAP_11N_ENABLE (1 << 6)
118#define EEPROM_SKU_CAP_AMT_ENABLE (1 << 7) 116#define EEPROM_SKU_CAP_AMT_ENABLE (1 << 7)
119#define EEPROM_SKU_CAP_IPAN_ENABLE (1 << 8) 117#define EEPROM_SKU_CAP_IPAN_ENABLE (1 << 8)
120 118
121/* *regulatory* channel data format in eeprom, one for each channel. 119/* *regulatory* channel data format in eeprom, one for each channel.
@@ -164,16 +162,12 @@ struct iwl_eeprom_enhanced_txpwr {
164 s8 mimo3_max; 162 s8 mimo3_max;
165} __packed; 163} __packed;
166 164
167/* 5000 Specific */ 165/* calibration */
168#define EEPROM_5000_TX_POWER_VERSION (4)
169#define EEPROM_5000_EEPROM_VERSION (0x11A)
170
171/* 5000 and up calibration */
172#define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION) 166#define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
173#define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL) 167#define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL)
174 168
175/* 5000 temperature */ 169/* temperature */
176#define EEPROM_5000_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL) 170#define EEPROM_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL)
177 171
178/* agn links */ 172/* agn links */
179#define EEPROM_LINK_HOST (2*0x64) 173#define EEPROM_LINK_HOST (2*0x64)
@@ -205,6 +199,10 @@ struct iwl_eeprom_enhanced_txpwr {
205#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS ((0x80)\ 199#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS ((0x80)\
206 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */ 200 | INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */
207 201
202/* 5000 Specific */
203#define EEPROM_5000_TX_POWER_VERSION (4)
204#define EEPROM_5000_EEPROM_VERSION (0x11A)
205
208/* 5050 Specific */ 206/* 5050 Specific */
209#define EEPROM_5050_TX_POWER_VERSION (4) 207#define EEPROM_5050_TX_POWER_VERSION (4)
210#define EEPROM_5050_EEPROM_VERSION (0x21E) 208#define EEPROM_5050_EEPROM_VERSION (0x21E)
@@ -270,13 +268,13 @@ extern const u8 iwl_eeprom_band_1[14];
270 268
271/* General */ 269/* General */
272#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ 270#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
271#define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
273#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ 272#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
274#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ 273#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
275#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ 274#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
276#define EEPROM_VERSION (2*0x44) /* 2 bytes */ 275#define EEPROM_VERSION (2*0x44) /* 2 bytes */
277#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ 276#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
278#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ 277#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
279#define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
280#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ 278#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
281#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ 279#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
282 280
@@ -294,7 +292,6 @@ extern const u8 iwl_eeprom_band_1[14];
294 292
295struct iwl_eeprom_ops { 293struct iwl_eeprom_ops {
296 const u32 regulatory_bands[7]; 294 const u32 regulatory_bands[7];
297 const u8* (*query_addr) (const struct iwl_priv *priv, size_t offset);
298 void (*update_enhanced_txpower) (struct iwl_priv *priv); 295 void (*update_enhanced_txpower) (struct iwl_priv *priv);
299}; 296};
300 297
@@ -311,5 +308,6 @@ void iwl_free_channel_map(struct iwl_priv *priv);
311const struct iwl_channel_info *iwl_get_channel_info( 308const struct iwl_channel_info *iwl_get_channel_info(
312 const struct iwl_priv *priv, 309 const struct iwl_priv *priv,
313 enum ieee80211_band band, u16 channel); 310 enum ieee80211_band band, u16 channel);
311void iwl_rf_config(struct iwl_priv *priv);
314 312
315#endif /* __iwl_eeprom_h__ */ 313#endif /* __iwl_eeprom_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-fh.h b/drivers/net/wireless/iwlwifi/iwl-fh.h
index 6dfa806aefec..0ad60b3c04db 100644
--- a/drivers/net/wireless/iwlwifi/iwl-fh.h
+++ b/drivers/net/wireless/iwlwifi/iwl-fh.h
@@ -326,7 +326,7 @@
326#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) 326#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
327 327
328/* Find Control/Status reg for given Tx DMA/FIFO channel */ 328/* Find Control/Status reg for given Tx DMA/FIFO channel */
329#define FH50_TCSR_CHNL_NUM (8) 329#define FH_TCSR_CHNL_NUM (8)
330 330
331/* TCSR: tx_config register values */ 331/* TCSR: tx_config register values */
332#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 332#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
diff --git a/drivers/net/wireless/iwlwifi/iwl-hcmd.c b/drivers/net/wireless/iwlwifi/iwl-hcmd.c
deleted file mode 100644
index 76f996623140..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-hcmd.c
+++ /dev/null
@@ -1,291 +0,0 @@
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/sched.h>
32#include <net/mac80211.h>
33
34#include "iwl-dev.h" /* FIXME: remove */
35#include "iwl-debug.h"
36#include "iwl-eeprom.h"
37#include "iwl-core.h"
38
39
40const char *get_cmd_string(u8 cmd)
41{
42 switch (cmd) {
43 IWL_CMD(REPLY_ALIVE);
44 IWL_CMD(REPLY_ERROR);
45 IWL_CMD(REPLY_RXON);
46 IWL_CMD(REPLY_RXON_ASSOC);
47 IWL_CMD(REPLY_QOS_PARAM);
48 IWL_CMD(REPLY_RXON_TIMING);
49 IWL_CMD(REPLY_ADD_STA);
50 IWL_CMD(REPLY_REMOVE_STA);
51 IWL_CMD(REPLY_REMOVE_ALL_STA);
52 IWL_CMD(REPLY_TXFIFO_FLUSH);
53 IWL_CMD(REPLY_WEPKEY);
54 IWL_CMD(REPLY_TX);
55 IWL_CMD(REPLY_LEDS_CMD);
56 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
57 IWL_CMD(COEX_PRIORITY_TABLE_CMD);
58 IWL_CMD(COEX_MEDIUM_NOTIFICATION);
59 IWL_CMD(COEX_EVENT_CMD);
60 IWL_CMD(REPLY_QUIET_CMD);
61 IWL_CMD(REPLY_CHANNEL_SWITCH);
62 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
63 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
64 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
65 IWL_CMD(POWER_TABLE_CMD);
66 IWL_CMD(PM_SLEEP_NOTIFICATION);
67 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
68 IWL_CMD(REPLY_SCAN_CMD);
69 IWL_CMD(REPLY_SCAN_ABORT_CMD);
70 IWL_CMD(SCAN_START_NOTIFICATION);
71 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
72 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
73 IWL_CMD(BEACON_NOTIFICATION);
74 IWL_CMD(REPLY_TX_BEACON);
75 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
76 IWL_CMD(QUIET_NOTIFICATION);
77 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
78 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
79 IWL_CMD(REPLY_BT_CONFIG);
80 IWL_CMD(REPLY_STATISTICS_CMD);
81 IWL_CMD(STATISTICS_NOTIFICATION);
82 IWL_CMD(REPLY_CARD_STATE_CMD);
83 IWL_CMD(CARD_STATE_NOTIFICATION);
84 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
85 IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
86 IWL_CMD(SENSITIVITY_CMD);
87 IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
88 IWL_CMD(REPLY_RX_PHY_CMD);
89 IWL_CMD(REPLY_RX_MPDU_CMD);
90 IWL_CMD(REPLY_RX);
91 IWL_CMD(REPLY_COMPRESSED_BA);
92 IWL_CMD(CALIBRATION_CFG_CMD);
93 IWL_CMD(CALIBRATION_RES_NOTIFICATION);
94 IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION);
95 IWL_CMD(REPLY_TX_POWER_DBM_CMD);
96 IWL_CMD(TEMPERATURE_NOTIFICATION);
97 IWL_CMD(TX_ANT_CONFIGURATION_CMD);
98 IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF);
99 IWL_CMD(REPLY_BT_COEX_PRIO_TABLE);
100 IWL_CMD(REPLY_BT_COEX_PROT_ENV);
101 IWL_CMD(REPLY_WIPAN_PARAMS);
102 IWL_CMD(REPLY_WIPAN_RXON);
103 IWL_CMD(REPLY_WIPAN_RXON_TIMING);
104 IWL_CMD(REPLY_WIPAN_RXON_ASSOC);
105 IWL_CMD(REPLY_WIPAN_QOS_PARAM);
106 IWL_CMD(REPLY_WIPAN_WEPKEY);
107 IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH);
108 IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION);
109 IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE);
110 default:
111 return "UNKNOWN";
112
113 }
114}
115
116#define HOST_COMPLETE_TIMEOUT (HZ / 2)
117
118static void iwl_generic_cmd_callback(struct iwl_priv *priv,
119 struct iwl_device_cmd *cmd,
120 struct iwl_rx_packet *pkt)
121{
122 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
123 IWL_ERR(priv, "Bad return from %s (0x%08X)\n",
124 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
125 return;
126 }
127
128#ifdef CONFIG_IWLWIFI_DEBUG
129 switch (cmd->hdr.cmd) {
130 case REPLY_TX_LINK_QUALITY_CMD:
131 case SENSITIVITY_CMD:
132 IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n",
133 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
134 break;
135 default:
136 IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n",
137 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
138 }
139#endif
140}
141
142static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
143{
144 int ret;
145
146 if (WARN_ON(!(cmd->flags & CMD_ASYNC)))
147 return -EINVAL;
148
149 /* An asynchronous command can not expect an SKB to be set. */
150 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
151 return -EINVAL;
152
153 /* Assign a generic callback if one is not provided */
154 if (!cmd->callback)
155 cmd->callback = iwl_generic_cmd_callback;
156
157 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
158 return -EBUSY;
159
160 ret = iwl_enqueue_hcmd(priv, cmd);
161 if (ret < 0) {
162 IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
163 get_cmd_string(cmd->id), ret);
164 return ret;
165 }
166 return 0;
167}
168
169int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
170{
171 int cmd_idx;
172 int ret;
173
174 if (WARN_ON(cmd->flags & CMD_ASYNC))
175 return -EINVAL;
176
177 /* A synchronous command can not have a callback set. */
178 if (WARN_ON(cmd->callback))
179 return -EINVAL;
180
181 IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n",
182 get_cmd_string(cmd->id));
183
184 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
185 IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n",
186 get_cmd_string(cmd->id));
187
188 cmd_idx = iwl_enqueue_hcmd(priv, cmd);
189 if (cmd_idx < 0) {
190 ret = cmd_idx;
191 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
192 IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
193 get_cmd_string(cmd->id), ret);
194 return ret;
195 }
196
197 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
198 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
199 HOST_COMPLETE_TIMEOUT);
200 if (!ret) {
201 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
202 IWL_ERR(priv,
203 "Error sending %s: time out after %dms.\n",
204 get_cmd_string(cmd->id),
205 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
206
207 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
208 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
209 get_cmd_string(cmd->id));
210 ret = -ETIMEDOUT;
211 goto cancel;
212 }
213 }
214
215 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
216 IWL_ERR(priv, "Command %s aborted: RF KILL Switch\n",
217 get_cmd_string(cmd->id));
218 ret = -ECANCELED;
219 goto fail;
220 }
221 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
222 IWL_ERR(priv, "Command %s failed: FW Error\n",
223 get_cmd_string(cmd->id));
224 ret = -EIO;
225 goto fail;
226 }
227 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
228 IWL_ERR(priv, "Error: Response NULL in '%s'\n",
229 get_cmd_string(cmd->id));
230 ret = -EIO;
231 goto cancel;
232 }
233
234 return 0;
235
236cancel:
237 if (cmd->flags & CMD_WANT_SKB) {
238 /*
239 * Cancel the CMD_WANT_SKB flag for the cmd in the
240 * TX cmd queue. Otherwise in case the cmd comes
241 * in later, it will possibly set an invalid
242 * address (cmd->meta.source).
243 */
244 priv->txq[priv->cmd_queue].meta[cmd_idx].flags &=
245 ~CMD_WANT_SKB;
246 }
247fail:
248 if (cmd->reply_page) {
249 iwl_free_pages(priv, cmd->reply_page);
250 cmd->reply_page = 0;
251 }
252
253 return ret;
254}
255
256int iwl_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
257{
258 if (cmd->flags & CMD_ASYNC)
259 return iwl_send_cmd_async(priv, cmd);
260
261 return iwl_send_cmd_sync(priv, cmd);
262}
263
264int iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
265{
266 struct iwl_host_cmd cmd = {
267 .id = id,
268 .len = { len, },
269 .data = { data, },
270 };
271
272 return iwl_send_cmd_sync(priv, &cmd);
273}
274
275int iwl_send_cmd_pdu_async(struct iwl_priv *priv,
276 u8 id, u16 len, const void *data,
277 void (*callback)(struct iwl_priv *priv,
278 struct iwl_device_cmd *cmd,
279 struct iwl_rx_packet *pkt))
280{
281 struct iwl_host_cmd cmd = {
282 .id = id,
283 .len = { len, },
284 .data = { data, },
285 };
286
287 cmd.flags |= CMD_ASYNC;
288 cmd.callback = callback;
289
290 return iwl_send_cmd_async(priv, &cmd);
291}
diff --git a/drivers/net/wireless/iwlwifi/iwl-helpers.h b/drivers/net/wireless/iwlwifi/iwl-helpers.h
index 41207a3645b8..9d91552d13c1 100644
--- a/drivers/net/wireless/iwlwifi/iwl-helpers.h
+++ b/drivers/net/wireless/iwlwifi/iwl-helpers.h
@@ -120,7 +120,16 @@ static inline void iwl_wake_any_queue(struct iwl_priv *priv,
120 } 120 }
121} 121}
122 122
123#ifdef ieee80211_stop_queue
124#undef ieee80211_stop_queue
125#endif
126
123#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue 127#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
128
129#ifdef ieee80211_wake_queue
130#undef ieee80211_wake_queue
131#endif
132
124#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue 133#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
125 134
126static inline void iwl_disable_interrupts(struct iwl_priv *priv) 135static inline void iwl_disable_interrupts(struct iwl_priv *priv)
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.h b/drivers/net/wireless/iwlwifi/iwl-io.h
index 869edc580ec6..19a093101122 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.h
+++ b/drivers/net/wireless/iwlwifi/iwl-io.h
@@ -34,22 +34,23 @@
34#include "iwl-dev.h" 34#include "iwl-dev.h"
35#include "iwl-debug.h" 35#include "iwl-debug.h"
36#include "iwl-devtrace.h" 36#include "iwl-devtrace.h"
37#include "iwl-bus.h"
37 38
38static inline void iwl_write8(struct iwl_priv *priv, u32 ofs, u8 val) 39static inline void iwl_write8(struct iwl_priv *priv, u32 ofs, u8 val)
39{ 40{
40 trace_iwlwifi_dev_iowrite8(priv, ofs, val); 41 trace_iwlwifi_dev_iowrite8(priv, ofs, val);
41 iowrite8(val, priv->hw_base + ofs); 42 bus_write8(priv->bus, ofs, val);
42} 43}
43 44
44static inline void iwl_write32(struct iwl_priv *priv, u32 ofs, u32 val) 45static inline void iwl_write32(struct iwl_priv *priv, u32 ofs, u32 val)
45{ 46{
46 trace_iwlwifi_dev_iowrite32(priv, ofs, val); 47 trace_iwlwifi_dev_iowrite32(priv, ofs, val);
47 iowrite32(val, priv->hw_base + ofs); 48 bus_write32(priv->bus, ofs, val);
48} 49}
49 50
50static inline u32 iwl_read32(struct iwl_priv *priv, u32 ofs) 51static inline u32 iwl_read32(struct iwl_priv *priv, u32 ofs)
51{ 52{
52 u32 val = ioread32(priv->hw_base + ofs); 53 u32 val = bus_read32(priv->bus, ofs);
53 trace_iwlwifi_dev_ioread32(priv, ofs, val); 54 trace_iwlwifi_dev_ioread32(priv, ofs, val);
54 return val; 55 return val;
55} 56}
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c
index 7c23beb49d7c..a67ae56d5464 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-led.c
@@ -28,8 +28,6 @@
28#include <linux/kernel.h> 28#include <linux/kernel.h>
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h> 31#include <linux/delay.h>
34#include <linux/skbuff.h> 32#include <linux/skbuff.h>
35#include <linux/netdevice.h> 33#include <linux/netdevice.h>
@@ -40,13 +38,9 @@
40 38
41#include "iwl-dev.h" 39#include "iwl-dev.h"
42#include "iwl-core.h" 40#include "iwl-core.h"
41#include "iwl-agn.h"
43#include "iwl-io.h" 42#include "iwl-io.h"
44 43#include "iwl-trans.h"
45/* default: IWL_LED_BLINK(0) using blinking index table */
46static int led_mode;
47module_param(led_mode, int, S_IRUGO);
48MODULE_PARM_DESC(led_mode, "0=system default, "
49 "1=On(RF On)/Off(RF Off), 2=blinking");
50 44
51/* Throughput OFF time(ms) ON time (ms) 45/* Throughput OFF time(ms) ON time (ms)
52 * >300 25 25 46 * >300 25 25
@@ -118,7 +112,7 @@ static int iwl_send_led_cmd(struct iwl_priv *priv, struct iwl_led_cmd *led_cmd)
118 if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) 112 if (reg != (reg & CSR_LED_BSM_CTRL_MSK))
119 iwl_write32(priv, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); 113 iwl_write32(priv, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK);
120 114
121 return iwl_send_cmd(priv, &cmd); 115 return trans_send_cmd(&priv->trans, &cmd);
122} 116}
123 117
124/* Set led pattern command */ 118/* Set led pattern command */
@@ -181,7 +175,7 @@ static int iwl_led_blink_set(struct led_classdev *led_cdev,
181 175
182void iwl_leds_init(struct iwl_priv *priv) 176void iwl_leds_init(struct iwl_priv *priv)
183{ 177{
184 int mode = led_mode; 178 int mode = iwlagn_mod_params.led_mode;
185 int ret; 179 int ret;
186 180
187 if (mode == IWL_LED_DEFAULT) 181 if (mode == IWL_LED_DEFAULT)
@@ -209,7 +203,8 @@ void iwl_leds_init(struct iwl_priv *priv)
209 break; 203 break;
210 } 204 }
211 205
212 ret = led_classdev_register(&priv->pci_dev->dev, &priv->led); 206 ret = led_classdev_register(priv->bus->dev,
207 &priv->led);
213 if (ret) { 208 if (ret) {
214 kfree(priv->led.name); 209 kfree(priv->led.name);
215 return; 210 return;
diff --git a/drivers/net/wireless/iwlwifi/iwl-pci.c b/drivers/net/wireless/iwlwifi/iwl-pci.c
new file mode 100644
index 000000000000..fb7e436b40c7
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-pci.c
@@ -0,0 +1,569 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63#include <linux/pci.h>
64#include <linux/pci-aspm.h>
65
66#include "iwl-bus.h"
67#include "iwl-agn.h"
68#include "iwl-core.h"
69#include "iwl-io.h"
70
71/* PCI registers */
72#define PCI_CFG_RETRY_TIMEOUT 0x041
73#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
74#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
75
76struct iwl_pci_bus {
77 /* basic pci-network driver stuff */
78 struct pci_dev *pci_dev;
79
80 /* pci hardware address support */
81 void __iomem *hw_base;
82};
83
84#define IWL_BUS_GET_PCI_BUS(_iwl_bus) \
85 ((struct iwl_pci_bus *) ((_iwl_bus)->bus_specific))
86
87#define IWL_BUS_GET_PCI_DEV(_iwl_bus) \
88 ((IWL_BUS_GET_PCI_BUS(_iwl_bus))->pci_dev)
89
90static u16 iwl_pciexp_link_ctrl(struct iwl_bus *bus)
91{
92 int pos;
93 u16 pci_lnk_ctl;
94 struct pci_dev *pci_dev = IWL_BUS_GET_PCI_DEV(bus);
95
96 pos = pci_pcie_cap(pci_dev);
97 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
98 return pci_lnk_ctl;
99}
100
101static bool iwl_pci_is_pm_supported(struct iwl_bus *bus)
102{
103 u16 lctl = iwl_pciexp_link_ctrl(bus);
104
105 return !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
106}
107
108static void iwl_pci_apm_config(struct iwl_bus *bus)
109{
110 /*
111 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
112 * Check if BIOS (or OS) enabled L1-ASPM on this device.
113 * If so (likely), disable L0S, so device moves directly L0->L1;
114 * costs negligible amount of power savings.
115 * If not (unlikely), enable L0S, so there is at least some
116 * power savings, even without L1.
117 */
118 u16 lctl = iwl_pciexp_link_ctrl(bus);
119
120 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
121 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
122 /* L1-ASPM enabled; disable(!) L0S */
123 iwl_set_bit(bus->drv_data, CSR_GIO_REG,
124 CSR_GIO_REG_VAL_L0S_ENABLED);
125 dev_printk(KERN_INFO, bus->dev, "L1 Enabled; Disabling L0S\n");
126 } else {
127 /* L1-ASPM disabled; enable(!) L0S */
128 iwl_clear_bit(bus->drv_data, CSR_GIO_REG,
129 CSR_GIO_REG_VAL_L0S_ENABLED);
130 dev_printk(KERN_INFO, bus->dev, "L1 Disabled; Enabling L0S\n");
131 }
132}
133
134static void iwl_pci_set_drv_data(struct iwl_bus *bus, void *drv_data)
135{
136 bus->drv_data = drv_data;
137}
138
139static void iwl_pci_get_hw_id(struct iwl_bus *bus, char buf[],
140 int buf_len)
141{
142 struct pci_dev *pci_dev = IWL_BUS_GET_PCI_DEV(bus);
143
144 snprintf(buf, buf_len, "PCI ID: 0x%04X:0x%04X", pci_dev->device,
145 pci_dev->subsystem_device);
146}
147
148static void iwl_pci_write8(struct iwl_bus *bus, u32 ofs, u8 val)
149{
150 iowrite8(val, IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
151}
152
153static void iwl_pci_write32(struct iwl_bus *bus, u32 ofs, u32 val)
154{
155 iowrite32(val, IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
156}
157
158static u32 iwl_pci_read32(struct iwl_bus *bus, u32 ofs)
159{
160 u32 val = ioread32(IWL_BUS_GET_PCI_BUS(bus)->hw_base + ofs);
161 return val;
162}
163
164static struct iwl_bus_ops pci_ops = {
165 .get_pm_support = iwl_pci_is_pm_supported,
166 .apm_config = iwl_pci_apm_config,
167 .set_drv_data = iwl_pci_set_drv_data,
168 .get_hw_id = iwl_pci_get_hw_id,
169 .write8 = iwl_pci_write8,
170 .write32 = iwl_pci_write32,
171 .read32 = iwl_pci_read32,
172};
173
174#define IWL_PCI_DEVICE(dev, subdev, cfg) \
175 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
176 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
177 .driver_data = (kernel_ulong_t)&(cfg)
178
179/* Hardware specific file defines the PCI IDs table for that hardware module */
180static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
181 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
182 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
183 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
184 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
185 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
186 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
187 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
188 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
189 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
190 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
191 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
192 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
193 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
194 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
195 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
196 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
197 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
198 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
199 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
200 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
201 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
202 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
203 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
204 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
205
206/* 5300 Series WiFi */
207 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
208 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
209 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
210 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
211 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
212 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
213 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
214 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
215 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
216 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
217 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
218 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
219
220/* 5350 Series WiFi/WiMax */
221 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
222 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
223 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
224
225/* 5150 Series Wifi/WiMax */
226 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
227 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
228 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
229 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
230 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
231 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
232
233 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
234 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
235 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
236 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
237
238/* 6x00 Series */
239 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
240 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
241 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
242 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
243 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
244 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
245 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
246 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
247 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
248 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
249
250/* 6x05 Series */
251 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
252 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
253 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
254 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
255 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
256 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
257 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
258
259/* 6x30 Series */
260 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
261 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
262 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
263 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
264 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
265 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
266 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
267 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
268 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
269 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
270 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
271 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
272 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
273 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
274 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
275 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
276
277/* 6x50 WiFi/WiMax Series */
278 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
279 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
280 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
281 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
282 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
283 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
284
285/* 6150 WiFi/WiMax Series */
286 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
287 {IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
288 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
289 {IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
290 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
291 {IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
292
293/* 1000 Series WiFi */
294 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
295 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
296 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
297 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
298 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
299 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
300 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
301 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
302 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
303 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
304 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
305 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
306
307/* 100 Series WiFi */
308 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
309 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
310 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
311 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
312 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
313 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
314
315/* 130 Series WiFi */
316 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
317 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
318 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
319 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
320 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
321 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
322
323/* 2x00 Series */
324 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
325 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
326 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
327 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
328 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
329 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
330
331/* 2x30 Series */
332 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
333 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
334 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
335 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
336 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
337 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
338
339/* 6x35 Series */
340 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
341 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
342 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
343 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
344 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
345 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
346 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
347 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
348 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
349
350/* 105 Series */
351 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
352 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
353 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
354 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
355 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
356 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
357
358/* 135 Series */
359 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
360 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
361 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
362 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
363 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
364 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
365
366 {0}
367};
368MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
369
370static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
371{
372 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
373 struct iwl_bus *bus;
374 struct iwl_pci_bus *pci_bus;
375 u16 pci_cmd;
376 int err;
377
378 bus = kzalloc(sizeof(*bus) + sizeof(*pci_bus), GFP_KERNEL);
379 if (!bus) {
380 dev_printk(KERN_ERR, &pdev->dev,
381 "Couldn't allocate iwl_pci_bus");
382 err = -ENOMEM;
383 goto out_no_pci;
384 }
385
386 pci_bus = IWL_BUS_GET_PCI_BUS(bus);
387 pci_bus->pci_dev = pdev;
388
389 /* W/A - seems to solve weird behavior. We need to remove this if we
390 * don't want to stay in L1 all the time. This wastes a lot of power */
391 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
392 PCIE_LINK_STATE_CLKPM);
393
394 if (pci_enable_device(pdev)) {
395 err = -ENODEV;
396 goto out_no_pci;
397 }
398
399 pci_set_master(pdev);
400
401 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
402 if (!err)
403 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
404 if (err) {
405 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
406 if (!err)
407 err = pci_set_consistent_dma_mask(pdev,
408 DMA_BIT_MASK(32));
409 /* both attempts failed: */
410 if (err) {
411 dev_printk(KERN_ERR, bus->dev,
412 "No suitable DMA available.\n");
413 goto out_pci_disable_device;
414 }
415 }
416
417 err = pci_request_regions(pdev, DRV_NAME);
418 if (err) {
419 dev_printk(KERN_ERR, bus->dev, "pci_request_regions failed");
420 goto out_pci_disable_device;
421 }
422
423 pci_bus->hw_base = pci_iomap(pdev, 0, 0);
424 if (!pci_bus->hw_base) {
425 dev_printk(KERN_ERR, bus->dev, "pci_iomap failed");
426 err = -ENODEV;
427 goto out_pci_release_regions;
428 }
429
430 dev_printk(KERN_INFO, &pdev->dev,
431 "pci_resource_len = 0x%08llx\n",
432 (unsigned long long) pci_resource_len(pdev, 0));
433 dev_printk(KERN_INFO, &pdev->dev,
434 "pci_resource_base = %p\n", pci_bus->hw_base);
435
436 dev_printk(KERN_INFO, &pdev->dev,
437 "HW Revision ID = 0x%X\n", pdev->revision);
438
439 /* We disable the RETRY_TIMEOUT register (0x41) to keep
440 * PCI Tx retries from interfering with C3 CPU state */
441 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
442
443 err = pci_enable_msi(pdev);
444 if (err) {
445 dev_printk(KERN_ERR, &pdev->dev, "pci_enable_msi failed");
446 goto out_iounmap;
447 }
448
449 /* TODO: Move this away, not needed if not MSI */
450 /* enable rfkill interrupt: hw bug w/a */
451 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
452 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
453 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
454 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
455 }
456
457 pci_set_drvdata(pdev, bus);
458
459 bus->dev = &pdev->dev;
460 bus->irq = pdev->irq;
461 bus->ops = &pci_ops;
462
463 err = iwl_probe(bus, cfg);
464 if (err)
465 goto out_disable_msi;
466 return 0;
467
468out_disable_msi:
469 pci_disable_msi(pdev);
470out_iounmap:
471 pci_iounmap(pdev, pci_bus->hw_base);
472out_pci_release_regions:
473 pci_set_drvdata(pdev, NULL);
474 pci_release_regions(pdev);
475out_pci_disable_device:
476 pci_disable_device(pdev);
477out_no_pci:
478 kfree(bus);
479 return err;
480}
481
482static void iwl_pci_down(struct iwl_bus *bus)
483{
484 struct iwl_pci_bus *pci_bus = (struct iwl_pci_bus *) bus->bus_specific;
485
486 pci_disable_msi(pci_bus->pci_dev);
487 pci_iounmap(pci_bus->pci_dev, pci_bus->hw_base);
488 pci_release_regions(pci_bus->pci_dev);
489 pci_disable_device(pci_bus->pci_dev);
490 pci_set_drvdata(pci_bus->pci_dev, NULL);
491
492 kfree(bus);
493}
494
495static void __devexit iwl_pci_remove(struct pci_dev *pdev)
496{
497 struct iwl_bus *bus = pci_get_drvdata(pdev);
498
499 iwl_remove(bus->drv_data);
500
501 iwl_pci_down(bus);
502}
503
504#ifdef CONFIG_PM
505
506static int iwl_pci_suspend(struct device *device)
507{
508 struct pci_dev *pdev = to_pci_dev(device);
509 struct iwl_bus *bus = pci_get_drvdata(pdev);
510
511 /* Before you put code here, think about WoWLAN. You cannot check here
512 * whether WoWLAN is enabled or not, and your code will run even if
513 * WoWLAN is enabled - don't kill the NIC, someone may need it in Sx.
514 */
515
516 return iwl_suspend(bus->drv_data);
517}
518
519static int iwl_pci_resume(struct device *device)
520{
521 struct pci_dev *pdev = to_pci_dev(device);
522 struct iwl_bus *bus = pci_get_drvdata(pdev);
523
524 /* Before you put code here, think about WoWLAN. You cannot check here
525 * whether WoWLAN is enabled or not, and your code will run even if
526 * WoWLAN is enabled - the NIC may be alive.
527 */
528
529 /*
530 * We disable the RETRY_TIMEOUT register (0x41) to keep
531 * PCI Tx retries from interfering with C3 CPU state.
532 */
533 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
534
535 return iwl_resume(bus->drv_data);
536}
537
538static SIMPLE_DEV_PM_OPS(iwl_dev_pm_ops, iwl_pci_suspend, iwl_pci_resume);
539
540#define IWL_PM_OPS (&iwl_dev_pm_ops)
541
542#else
543
544#define IWL_PM_OPS NULL
545
546#endif
547
548static struct pci_driver iwl_pci_driver = {
549 .name = DRV_NAME,
550 .id_table = iwl_hw_card_ids,
551 .probe = iwl_pci_probe,
552 .remove = __devexit_p(iwl_pci_remove),
553 .driver.pm = IWL_PM_OPS,
554};
555
556int __must_check iwl_pci_register_driver(void)
557{
558 int ret;
559 ret = pci_register_driver(&iwl_pci_driver);
560 if (ret)
561 pr_err("Unable to initialize PCI module\n");
562
563 return ret;
564}
565
566void iwl_pci_unregister_driver(void)
567{
568 pci_unregister_driver(&iwl_pci_driver);
569}
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.c b/drivers/net/wireless/iwlwifi/iwl-power.c
index 595c930b28ae..3ec619c6881c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-power.c
+++ b/drivers/net/wireless/iwlwifi/iwl-power.c
@@ -36,11 +36,13 @@
36 36
37#include "iwl-eeprom.h" 37#include "iwl-eeprom.h"
38#include "iwl-dev.h" 38#include "iwl-dev.h"
39#include "iwl-agn.h"
39#include "iwl-core.h" 40#include "iwl-core.h"
40#include "iwl-io.h" 41#include "iwl-io.h"
41#include "iwl-commands.h" 42#include "iwl-commands.h"
42#include "iwl-debug.h" 43#include "iwl-debug.h"
43#include "iwl-power.h" 44#include "iwl-power.h"
45#include "iwl-trans.h"
44 46
45/* 47/*
46 * Setting power level allows the card to go to sleep when not busy. 48 * Setting power level allows the card to go to sleep when not busy.
@@ -51,16 +53,6 @@
51 */ 53 */
52 54
53/* 55/*
54 * For now, keep using power level 1 instead of automatically
55 * adjusting ...
56 */
57bool no_sleep_autoadjust = true;
58module_param(no_sleep_autoadjust, bool, S_IRUGO);
59MODULE_PARM_DESC(no_sleep_autoadjust,
60 "don't automatically adjust sleep level "
61 "according to maximum network latency");
62
63/*
64 * This defines the old power levels. They are still used by default 56 * This defines the old power levels. They are still used by default
65 * (level 1) and for thermal throttle (levels 3 through 5) 57 * (level 1) and for thermal throttle (levels 3 through 5)
66 */ 58 */
@@ -254,7 +246,7 @@ static void iwl_static_sleep_cmd(struct iwl_priv *priv,
254 } 246 }
255 } 247 }
256 248
257 if (priv->power_data.pci_pm) 249 if (priv->power_data.bus_pm)
258 cmd->flags |= IWL_POWER_PCI_PM_MSK; 250 cmd->flags |= IWL_POWER_PCI_PM_MSK;
259 else 251 else
260 cmd->flags &= ~IWL_POWER_PCI_PM_MSK; 252 cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
@@ -269,7 +261,7 @@ static void iwl_power_sleep_cam_cmd(struct iwl_priv *priv,
269{ 261{
270 memset(cmd, 0, sizeof(*cmd)); 262 memset(cmd, 0, sizeof(*cmd));
271 263
272 if (priv->power_data.pci_pm) 264 if (priv->power_data.bus_pm)
273 cmd->flags |= IWL_POWER_PCI_PM_MSK; 265 cmd->flags |= IWL_POWER_PCI_PM_MSK;
274 266
275 IWL_DEBUG_POWER(priv, "Sleep command for CAM\n"); 267 IWL_DEBUG_POWER(priv, "Sleep command for CAM\n");
@@ -305,7 +297,7 @@ static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
305 cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK | 297 cmd->flags = IWL_POWER_DRIVER_ALLOW_SLEEP_MSK |
306 IWL_POWER_FAST_PD; /* no use seeing frames for others */ 298 IWL_POWER_FAST_PD; /* no use seeing frames for others */
307 299
308 if (priv->power_data.pci_pm) 300 if (priv->power_data.bus_pm)
309 cmd->flags |= IWL_POWER_PCI_PM_MSK; 301 cmd->flags |= IWL_POWER_PCI_PM_MSK;
310 302
311 if (priv->cfg->base_params->shadow_reg_enable) 303 if (priv->cfg->base_params->shadow_reg_enable)
@@ -343,7 +335,7 @@ static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
343 le32_to_cpu(cmd->sleep_interval[3]), 335 le32_to_cpu(cmd->sleep_interval[3]),
344 le32_to_cpu(cmd->sleep_interval[4])); 336 le32_to_cpu(cmd->sleep_interval[4]));
345 337
346 return iwl_send_cmd_pdu(priv, POWER_TABLE_CMD, 338 return trans_send_cmd_pdu(&priv->trans, POWER_TABLE_CMD, CMD_SYNC,
347 sizeof(struct iwl_powertable_cmd), cmd); 339 sizeof(struct iwl_powertable_cmd), cmd);
348} 340}
349 341
@@ -355,7 +347,9 @@ static void iwl_power_build_cmd(struct iwl_priv *priv,
355 347
356 dtimper = priv->hw->conf.ps_dtim_period ?: 1; 348 dtimper = priv->hw->conf.ps_dtim_period ?: 1;
357 349
358 if (priv->hw->conf.flags & IEEE80211_CONF_IDLE) 350 if (priv->wowlan)
351 iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, dtimper);
352 else if (priv->hw->conf.flags & IEEE80211_CONF_IDLE)
359 iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20); 353 iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
360 else if (iwl_tt_is_low_power_state(priv)) { 354 else if (iwl_tt_is_low_power_state(priv)) {
361 /* in thermal throttling low power state */ 355 /* in thermal throttling low power state */
@@ -367,9 +361,15 @@ static void iwl_power_build_cmd(struct iwl_priv *priv,
367 iwl_static_sleep_cmd(priv, cmd, 361 iwl_static_sleep_cmd(priv, cmd,
368 priv->power_data.debug_sleep_level_override, 362 priv->power_data.debug_sleep_level_override,
369 dtimper); 363 dtimper);
370 else if (no_sleep_autoadjust) 364 else if (iwlagn_mod_params.no_sleep_autoadjust) {
371 iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper); 365 if (iwlagn_mod_params.power_level > IWL_POWER_INDEX_1 &&
372 else 366 iwlagn_mod_params.power_level <= IWL_POWER_INDEX_5)
367 iwl_static_sleep_cmd(priv, cmd,
368 iwlagn_mod_params.power_level, dtimper);
369 else
370 iwl_static_sleep_cmd(priv, cmd,
371 IWL_POWER_INDEX_1, dtimper);
372 } else
373 iwl_power_fill_sleep_cmd(priv, cmd, 373 iwl_power_fill_sleep_cmd(priv, cmd,
374 priv->hw->conf.dynamic_ps_timeout, 374 priv->hw->conf.dynamic_ps_timeout,
375 priv->hw->conf.max_sleep_period); 375 priv->hw->conf.max_sleep_period);
@@ -408,9 +408,9 @@ int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
408 if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)) 408 if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
409 clear_bit(STATUS_POWER_PMI, &priv->status); 409 clear_bit(STATUS_POWER_PMI, &priv->status);
410 410
411 if (priv->cfg->ops->lib->update_chain_flags && update_chains) 411 if (update_chains)
412 priv->cfg->ops->lib->update_chain_flags(priv); 412 iwl_update_chain_flags(priv);
413 else if (priv->cfg->ops->lib->update_chain_flags) 413 else
414 IWL_DEBUG_POWER(priv, 414 IWL_DEBUG_POWER(priv,
415 "Cannot update the power, chain noise " 415 "Cannot update the power, chain noise "
416 "calibration running: %d\n", 416 "calibration running: %d\n",
@@ -434,9 +434,7 @@ int iwl_power_update_mode(struct iwl_priv *priv, bool force)
434/* initialize to default */ 434/* initialize to default */
435void iwl_power_initialize(struct iwl_priv *priv) 435void iwl_power_initialize(struct iwl_priv *priv)
436{ 436{
437 u16 lctl = iwl_pcie_link_ctl(priv); 437 priv->power_data.bus_pm = bus_get_pm_support(priv->bus);
438
439 priv->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
440 438
441 priv->power_data.debug_sleep_level_override = -1; 439 priv->power_data.debug_sleep_level_override = -1;
442 440
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.h b/drivers/net/wireless/iwlwifi/iwl-power.h
index 59635d784e27..5f7b720cf1a4 100644
--- a/drivers/net/wireless/iwlwifi/iwl-power.h
+++ b/drivers/net/wireless/iwlwifi/iwl-power.h
@@ -43,7 +43,7 @@ struct iwl_power_mgr {
43 struct iwl_powertable_cmd sleep_cmd; 43 struct iwl_powertable_cmd sleep_cmd;
44 struct iwl_powertable_cmd sleep_cmd_next; 44 struct iwl_powertable_cmd sleep_cmd_next;
45 int debug_sleep_level_override; 45 int debug_sleep_level_override;
46 bool pci_pm; 46 bool bus_pm;
47}; 47};
48 48
49int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd, 49int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index f00d188b2cfc..2f267b8aabbb 100644
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -168,6 +168,7 @@
168 * the scheduler (especially for queue #4/#9, the command queue, otherwise 168 * the scheduler (especially for queue #4/#9, the command queue, otherwise
169 * the driver can't issue commands!): 169 * the driver can't issue commands!):
170 */ 170 */
171#define SCD_MEM_LOWER_BOUND (0x0000)
171 172
172/** 173/**
173 * Max Tx window size is the max number of contiguous TFDs that the scheduler 174 * Max Tx window size is the max number of contiguous TFDs that the scheduler
@@ -177,53 +178,61 @@
177#define SCD_WIN_SIZE 64 178#define SCD_WIN_SIZE 64
178#define SCD_FRAME_LIMIT 64 179#define SCD_FRAME_LIMIT 64
179 180
180#define IWL_SCD_TXFIFO_POS_TID (0) 181#define SCD_TXFIFO_POS_TID (0)
181#define IWL_SCD_TXFIFO_POS_RA (4) 182#define SCD_TXFIFO_POS_RA (4)
182#define IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 183#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
183 184
184/* agn SCD */ 185/* agn SCD */
185#define IWLAGN_SCD_QUEUE_STTS_REG_POS_TXF (0) 186#define SCD_QUEUE_STTS_REG_POS_TXF (0)
186#define IWLAGN_SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 187#define SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
187#define IWLAGN_SCD_QUEUE_STTS_REG_POS_WSL (4) 188#define SCD_QUEUE_STTS_REG_POS_WSL (4)
188#define IWLAGN_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 189#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
189#define IWLAGN_SCD_QUEUE_STTS_REG_MSK (0x00FF0000) 190#define SCD_QUEUE_STTS_REG_MSK (0x00FF0000)
190 191
191#define IWLAGN_SCD_QUEUE_CTX_REG1_CREDIT_POS (8) 192#define SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
192#define IWLAGN_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00) 193#define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
193#define IWLAGN_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24) 194#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
194#define IWLAGN_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000) 195#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
195#define IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0) 196#define SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
196#define IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F) 197#define SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
197#define IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 198#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
198#define IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 199#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
199 200
200#define IWLAGN_SCD_CONTEXT_DATA_OFFSET (0x600) 201/* Context Data */
201#define IWLAGN_SCD_TX_STTS_BITMAP_OFFSET (0x7B1) 202#define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
202#define IWLAGN_SCD_TRANSLATE_TBL_OFFSET (0x7E0) 203#define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
203 204
204#define IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(x)\ 205/* Tx status */
205 (IWLAGN_SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) 206#define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
206 207#define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
207#define IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ 208
208 ((IWLAGN_SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffc) 209/* Translation Data */
209 210#define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
210#define IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv) \ 211#define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
212
213#define SCD_CONTEXT_QUEUE_OFFSET(x)\
214 (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
215
216#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
217 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
218
219#define SCD_QUEUECHAIN_SEL_ALL(priv) \
211 (((1<<(priv)->hw_params.max_txq_num) - 1) &\ 220 (((1<<(priv)->hw_params.max_txq_num) - 1) &\
212 (~(1<<(priv)->cmd_queue))) 221 (~(1<<(priv)->cmd_queue)))
213 222
214#define IWLAGN_SCD_BASE (PRPH_BASE + 0xa02c00) 223#define SCD_BASE (PRPH_BASE + 0xa02c00)
215 224
216#define IWLAGN_SCD_SRAM_BASE_ADDR (IWLAGN_SCD_BASE + 0x0) 225#define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
217#define IWLAGN_SCD_DRAM_BASE_ADDR (IWLAGN_SCD_BASE + 0x8) 226#define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
218#define IWLAGN_SCD_AIT (IWLAGN_SCD_BASE + 0x0c) 227#define SCD_AIT (SCD_BASE + 0x0c)
219#define IWLAGN_SCD_TXFACT (IWLAGN_SCD_BASE + 0x10) 228#define SCD_TXFACT (SCD_BASE + 0x10)
220#define IWLAGN_SCD_ACTIVE (IWLAGN_SCD_BASE + 0x14) 229#define SCD_ACTIVE (SCD_BASE + 0x14)
221#define IWLAGN_SCD_QUEUE_WRPTR(x) (IWLAGN_SCD_BASE + 0x18 + (x) * 4) 230#define SCD_QUEUE_WRPTR(x) (SCD_BASE + 0x18 + (x) * 4)
222#define IWLAGN_SCD_QUEUE_RDPTR(x) (IWLAGN_SCD_BASE + 0x68 + (x) * 4) 231#define SCD_QUEUE_RDPTR(x) (SCD_BASE + 0x68 + (x) * 4)
223#define IWLAGN_SCD_QUEUECHAIN_SEL (IWLAGN_SCD_BASE + 0xe8) 232#define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
224#define IWLAGN_SCD_AGGR_SEL (IWLAGN_SCD_BASE + 0x248) 233#define SCD_AGGR_SEL (SCD_BASE + 0x248)
225#define IWLAGN_SCD_INTERRUPT_MASK (IWLAGN_SCD_BASE + 0x108) 234#define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
226#define IWLAGN_SCD_QUEUE_STATUS_BITS(x) (IWLAGN_SCD_BASE + 0x10c + (x) * 4) 235#define SCD_QUEUE_STATUS_BITS(x) (SCD_BASE + 0x10c + (x) * 4)
227 236
228/*********************** END TX SCHEDULER *************************************/ 237/*********************** END TX SCHEDULER *************************************/
229 238
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c
index b774517aa9fa..8e314003b63a 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-rx.c
@@ -41,183 +41,6 @@
41#include "iwl-agn-calib.h" 41#include "iwl-agn-calib.h"
42#include "iwl-agn.h" 42#include "iwl-agn.h"
43 43
44/******************************************************************************
45 *
46 * RX path functions
47 *
48 ******************************************************************************/
49
50/*
51 * Rx theory of operation
52 *
53 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
54 * each of which point to Receive Buffers to be filled by the NIC. These get
55 * used not only for Rx frames, but for any command response or notification
56 * from the NIC. The driver and NIC manage the Rx buffers by means
57 * of indexes into the circular buffer.
58 *
59 * Rx Queue Indexes
60 * The host/firmware share two index registers for managing the Rx buffers.
61 *
62 * The READ index maps to the first position that the firmware may be writing
63 * to -- the driver can read up to (but not including) this position and get
64 * good data.
65 * The READ index is managed by the firmware once the card is enabled.
66 *
67 * The WRITE index maps to the last position the driver has read from -- the
68 * position preceding WRITE is the last slot the firmware can place a packet.
69 *
70 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
71 * WRITE = READ.
72 *
73 * During initialization, the host sets up the READ queue position to the first
74 * INDEX position, and WRITE to the last (READ - 1 wrapped)
75 *
76 * When the firmware places a packet in a buffer, it will advance the READ index
77 * and fire the RX interrupt. The driver can then query the READ index and
78 * process as many packets as possible, moving the WRITE index forward as it
79 * resets the Rx queue buffers with new memory.
80 *
81 * The management in the driver is as follows:
82 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
83 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
84 * to replenish the iwl->rxq->rx_free.
85 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
86 * iwl->rxq is replenished and the READ INDEX is updated (updating the
87 * 'processed' and 'read' driver indexes as well)
88 * + A received packet is processed and handed to the kernel network stack,
89 * detached from the iwl->rxq. The driver 'processed' index is updated.
90 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
91 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
92 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
93 * were enough free buffers and RX_STALLED is set it is cleared.
94 *
95 *
96 * Driver sequence:
97 *
98 * iwl_rx_queue_alloc() Allocates rx_free
99 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
100 * iwl_rx_queue_restock
101 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
102 * queue, updates firmware pointers, and updates
103 * the WRITE index. If insufficient rx_free buffers
104 * are available, schedules iwl_rx_replenish
105 *
106 * -- enable interrupts --
107 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
108 * READ INDEX, detaching the SKB from the pool.
109 * Moves the packet buffer from queue to rx_used.
110 * Calls iwl_rx_queue_restock to refill any empty
111 * slots.
112 * ...
113 *
114 */
115
116/**
117 * iwl_rx_queue_space - Return number of free slots available in queue.
118 */
119int iwl_rx_queue_space(const struct iwl_rx_queue *q)
120{
121 int s = q->read - q->write;
122 if (s <= 0)
123 s += RX_QUEUE_SIZE;
124 /* keep some buffer to not confuse full and empty queue */
125 s -= 2;
126 if (s < 0)
127 s = 0;
128 return s;
129}
130
131/**
132 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
133 */
134void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
135{
136 unsigned long flags;
137 u32 rx_wrt_ptr_reg = priv->hw_params.rx_wrt_ptr_reg;
138 u32 reg;
139
140 spin_lock_irqsave(&q->lock, flags);
141
142 if (q->need_update == 0)
143 goto exit_unlock;
144
145 if (priv->cfg->base_params->shadow_reg_enable) {
146 /* shadow register enabled */
147 /* Device expects a multiple of 8 */
148 q->write_actual = (q->write & ~0x7);
149 iwl_write32(priv, rx_wrt_ptr_reg, q->write_actual);
150 } else {
151 /* If power-saving is in use, make sure device is awake */
152 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
153 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
154
155 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
156 IWL_DEBUG_INFO(priv,
157 "Rx queue requesting wakeup,"
158 " GP1 = 0x%x\n", reg);
159 iwl_set_bit(priv, CSR_GP_CNTRL,
160 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
161 goto exit_unlock;
162 }
163
164 q->write_actual = (q->write & ~0x7);
165 iwl_write_direct32(priv, rx_wrt_ptr_reg,
166 q->write_actual);
167
168 /* Else device is assumed to be awake */
169 } else {
170 /* Device expects a multiple of 8 */
171 q->write_actual = (q->write & ~0x7);
172 iwl_write_direct32(priv, rx_wrt_ptr_reg,
173 q->write_actual);
174 }
175 }
176 q->need_update = 0;
177
178 exit_unlock:
179 spin_unlock_irqrestore(&q->lock, flags);
180}
181
182int iwl_rx_queue_alloc(struct iwl_priv *priv)
183{
184 struct iwl_rx_queue *rxq = &priv->rxq;
185 struct device *dev = &priv->pci_dev->dev;
186 int i;
187
188 spin_lock_init(&rxq->lock);
189 INIT_LIST_HEAD(&rxq->rx_free);
190 INIT_LIST_HEAD(&rxq->rx_used);
191
192 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
193 rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
194 GFP_KERNEL);
195 if (!rxq->bd)
196 goto err_bd;
197
198 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct iwl_rb_status),
199 &rxq->rb_stts_dma, GFP_KERNEL);
200 if (!rxq->rb_stts)
201 goto err_rb;
202
203 /* Fill the rx_used queue with _all_ of the Rx buffers */
204 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
205 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
206
207 /* Set us so that we have processed and used all buffers, but have
208 * not restocked the Rx queue with fresh buffers */
209 rxq->read = rxq->write = 0;
210 rxq->write_actual = 0;
211 rxq->free_count = 0;
212 rxq->need_update = 0;
213 return 0;
214
215err_rb:
216 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
217 rxq->bd_dma);
218err_bd:
219 return -ENOMEM;
220}
221 44
222/****************************************************************************** 45/******************************************************************************
223 * 46 *
@@ -347,7 +170,7 @@ static bool iwl_good_ack_health(struct iwl_priv *priv,
347 int actual_delta, expected_delta, ba_timeout_delta; 170 int actual_delta, expected_delta, ba_timeout_delta;
348 struct statistics_tx *old; 171 struct statistics_tx *old;
349 172
350 if (priv->_agn.agg_tids_count) 173 if (priv->agg_tids_count)
351 return true; 174 return true;
352 175
353 old = &priv->statistics.tx; 176 old = &priv->statistics.tx;
@@ -665,8 +488,8 @@ static void iwl_rx_statistics(struct iwl_priv *priv,
665 iwl_rx_calc_noise(priv); 488 iwl_rx_calc_noise(priv);
666 queue_work(priv->workqueue, &priv->run_time_calib_work); 489 queue_work(priv->workqueue, &priv->run_time_calib_work);
667 } 490 }
668 if (priv->cfg->ops->lib->temp_ops.temperature && change) 491 if (priv->cfg->lib->temperature && change)
669 priv->cfg->ops->lib->temp_ops.temperature(priv); 492 priv->cfg->lib->temperature(priv);
670} 493}
671 494
672static void iwl_rx_reply_statistics(struct iwl_priv *priv, 495static void iwl_rx_reply_statistics(struct iwl_priv *priv,
@@ -769,8 +592,8 @@ static void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
769{ 592{
770 struct iwl_rx_packet *pkt = rxb_addr(rxb); 593 struct iwl_rx_packet *pkt = rxb_addr(rxb);
771 594
772 priv->_agn.last_phy_res_valid = true; 595 priv->last_phy_res_valid = true;
773 memcpy(&priv->_agn.last_phy_res, pkt->u.raw, 596 memcpy(&priv->last_phy_res, pkt->u.raw,
774 sizeof(struct iwl_rx_phy_res)); 597 sizeof(struct iwl_rx_phy_res));
775} 598}
776 599
@@ -943,6 +766,47 @@ static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
943 return decrypt_out; 766 return decrypt_out;
944} 767}
945 768
769/* Calc max signal level (dBm) among 3 possible receivers */
770static int iwlagn_calc_rssi(struct iwl_priv *priv,
771 struct iwl_rx_phy_res *rx_resp)
772{
773 /* data from PHY/DSP regarding signal strength, etc.,
774 * contents are always there, not configurable by host
775 */
776 struct iwlagn_non_cfg_phy *ncphy =
777 (struct iwlagn_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
778 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
779 u8 agc;
780
781 val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_AGC_IDX]);
782 agc = (val & IWLAGN_OFDM_AGC_MSK) >> IWLAGN_OFDM_AGC_BIT_POS;
783
784 /* Find max rssi among 3 possible receivers.
785 * These values are measured by the digital signal processor (DSP).
786 * They should stay fairly constant even as the signal strength varies,
787 * if the radio's automatic gain control (AGC) is working right.
788 * AGC value (see below) will provide the "interesting" info.
789 */
790 val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_RSSI_AB_IDX]);
791 rssi_a = (val & IWLAGN_OFDM_RSSI_INBAND_A_BITMSK) >>
792 IWLAGN_OFDM_RSSI_A_BIT_POS;
793 rssi_b = (val & IWLAGN_OFDM_RSSI_INBAND_B_BITMSK) >>
794 IWLAGN_OFDM_RSSI_B_BIT_POS;
795 val = le32_to_cpu(ncphy->non_cfg_phy[IWLAGN_RX_RES_RSSI_C_IDX]);
796 rssi_c = (val & IWLAGN_OFDM_RSSI_INBAND_C_BITMSK) >>
797 IWLAGN_OFDM_RSSI_C_BIT_POS;
798
799 max_rssi = max_t(u32, rssi_a, rssi_b);
800 max_rssi = max_t(u32, max_rssi, rssi_c);
801
802 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
803 rssi_a, rssi_b, rssi_c, max_rssi, agc);
804
805 /* dBm = max_rssi dB - agc dB - constant.
806 * Higher AGC (higher radio gain) means lower signal. */
807 return max_rssi - agc - IWLAGN_RSSI_OFFSET;
808}
809
946/* Called for REPLY_RX (legacy ABG frames), or 810/* Called for REPLY_RX (legacy ABG frames), or
947 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */ 811 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
948static void iwl_rx_reply_rx(struct iwl_priv *priv, 812static void iwl_rx_reply_rx(struct iwl_priv *priv,
@@ -977,11 +841,11 @@ static void iwl_rx_reply_rx(struct iwl_priv *priv,
977 phy_res->cfg_phy_cnt + len); 841 phy_res->cfg_phy_cnt + len);
978 ampdu_status = le32_to_cpu(rx_pkt_status); 842 ampdu_status = le32_to_cpu(rx_pkt_status);
979 } else { 843 } else {
980 if (!priv->_agn.last_phy_res_valid) { 844 if (!priv->last_phy_res_valid) {
981 IWL_ERR(priv, "MPDU frame without cached PHY data\n"); 845 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
982 return; 846 return;
983 } 847 }
984 phy_res = &priv->_agn.last_phy_res; 848 phy_res = &priv->last_phy_res;
985 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw; 849 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw;
986 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); 850 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
987 len = le16_to_cpu(amsdu->byte_count); 851 len = le16_to_cpu(amsdu->byte_count);
@@ -1024,7 +888,7 @@ static void iwl_rx_reply_rx(struct iwl_priv *priv,
1024 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); 888 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
1025 889
1026 /* Find max signal strength (dBm) among 3 antenna/receiver chains */ 890 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
1027 rx_status.signal = priv->cfg->ops->utils->calc_rssi(priv, phy_res); 891 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
1028 892
1029 iwl_dbg_log_rx_data_frame(priv, len, header); 893 iwl_dbg_log_rx_data_frame(priv, len, header);
1030 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n", 894 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
@@ -1102,6 +966,64 @@ void iwl_setup_rx_handlers(struct iwl_priv *priv)
1102 /* block ack */ 966 /* block ack */
1103 handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba; 967 handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
1104 968
1105 /* Set up hardware specific Rx handlers */ 969 /* init calibration handlers */
1106 priv->cfg->ops->lib->rx_handler_setup(priv); 970 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
971 iwlagn_rx_calib_result;
972 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
973
974 /* set up notification wait support */
975 spin_lock_init(&priv->notif_wait_lock);
976 INIT_LIST_HEAD(&priv->notif_waits);
977 init_waitqueue_head(&priv->notif_waitq);
978
979 /* Set up BT Rx handlers */
980 if (priv->cfg->lib->bt_rx_handler_setup)
981 priv->cfg->lib->bt_rx_handler_setup(priv);
982
983}
984
985void iwl_rx_dispatch(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
986{
987 struct iwl_rx_packet *pkt = rxb_addr(rxb);
988
989 /*
990 * Do the notification wait before RX handlers so
991 * even if the RX handler consumes the RXB we have
992 * access to it in the notification wait entry.
993 */
994 if (!list_empty(&priv->notif_waits)) {
995 struct iwl_notification_wait *w;
996
997 spin_lock(&priv->notif_wait_lock);
998 list_for_each_entry(w, &priv->notif_waits, list) {
999 if (w->cmd != pkt->hdr.cmd)
1000 continue;
1001 IWL_DEBUG_RX(priv,
1002 "Notif: %s, 0x%02x - wake the callers up\n",
1003 get_cmd_string(pkt->hdr.cmd),
1004 pkt->hdr.cmd);
1005 w->triggered = true;
1006 if (w->fn)
1007 w->fn(priv, pkt, w->fn_data);
1008 }
1009 spin_unlock(&priv->notif_wait_lock);
1010
1011 wake_up_all(&priv->notif_waitq);
1012 }
1013
1014 if (priv->pre_rx_handler)
1015 priv->pre_rx_handler(priv, rxb);
1016
1017 /* Based on type of command response or notification,
1018 * handle those that need handling via function in
1019 * rx_handlers table. See iwl_setup_rx_handlers() */
1020 if (priv->rx_handlers[pkt->hdr.cmd]) {
1021 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
1022 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1023 } else {
1024 /* No handling needed */
1025 IWL_DEBUG_RX(priv,
1026 "No handler needed for %s, 0x%02x\n",
1027 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
1028 }
1107} 1029}
diff --git a/drivers/net/wireless/iwlwifi/iwl-scan.c b/drivers/net/wireless/iwlwifi/iwl-scan.c
index d60d630cb93a..dd6937e97055 100644
--- a/drivers/net/wireless/iwlwifi/iwl-scan.c
+++ b/drivers/net/wireless/iwlwifi/iwl-scan.c
@@ -36,6 +36,8 @@
36#include "iwl-sta.h" 36#include "iwl-sta.h"
37#include "iwl-io.h" 37#include "iwl-io.h"
38#include "iwl-helpers.h" 38#include "iwl-helpers.h"
39#include "iwl-agn.h"
40#include "iwl-trans.h"
39 41
40/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after 42/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
41 * sending probe req. This should be set long enough to hear probe responses 43 * sending probe req. This should be set long enough to hear probe responses
@@ -60,7 +62,7 @@ static int iwl_send_scan_abort(struct iwl_priv *priv)
60 struct iwl_rx_packet *pkt; 62 struct iwl_rx_packet *pkt;
61 struct iwl_host_cmd cmd = { 63 struct iwl_host_cmd cmd = {
62 .id = REPLY_SCAN_ABORT_CMD, 64 .id = REPLY_SCAN_ABORT_CMD,
63 .flags = CMD_WANT_SKB, 65 .flags = CMD_SYNC | CMD_WANT_SKB,
64 }; 66 };
65 67
66 /* Exit instantly with error when device is not ready 68 /* Exit instantly with error when device is not ready
@@ -73,7 +75,7 @@ static int iwl_send_scan_abort(struct iwl_priv *priv)
73 test_bit(STATUS_EXIT_PENDING, &priv->status)) 75 test_bit(STATUS_EXIT_PENDING, &priv->status))
74 return -EIO; 76 return -EIO;
75 77
76 ret = iwl_send_cmd_sync(priv, &cmd); 78 ret = trans_send_cmd(&priv->trans, &cmd);
77 if (ret) 79 if (ret)
78 return ret; 80 return ret;
79 81
@@ -348,9 +350,6 @@ int __must_check iwl_scan_initiate(struct iwl_priv *priv,
348 350
349 lockdep_assert_held(&priv->mutex); 351 lockdep_assert_held(&priv->mutex);
350 352
351 if (WARN_ON(!priv->cfg->ops->utils->request_scan))
352 return -EOPNOTSUPP;
353
354 cancel_delayed_work(&priv->scan_check); 353 cancel_delayed_work(&priv->scan_check);
355 354
356 if (!iwl_is_ready_rf(priv)) { 355 if (!iwl_is_ready_rf(priv)) {
@@ -379,7 +378,7 @@ int __must_check iwl_scan_initiate(struct iwl_priv *priv,
379 priv->scan_start = jiffies; 378 priv->scan_start = jiffies;
380 priv->scan_band = band; 379 priv->scan_band = band;
381 380
382 ret = priv->cfg->ops->utils->request_scan(priv, vif); 381 ret = iwlagn_request_scan(priv, vif);
383 if (ret) { 382 if (ret) {
384 clear_bit(STATUS_SCANNING, &priv->status); 383 clear_bit(STATUS_SCANNING, &priv->status);
385 priv->scan_type = IWL_SCAN_NORMAL; 384 priv->scan_type = IWL_SCAN_NORMAL;
@@ -566,10 +565,10 @@ static void iwl_bg_scan_completed(struct work_struct *work)
566 goto out_settings; 565 goto out_settings;
567 } 566 }
568 567
569 if (priv->scan_type == IWL_SCAN_OFFCH_TX && priv->_agn.offchan_tx_skb) { 568 if (priv->scan_type == IWL_SCAN_OFFCH_TX && priv->offchan_tx_skb) {
570 ieee80211_tx_status_irqsafe(priv->hw, 569 ieee80211_tx_status_irqsafe(priv->hw,
571 priv->_agn.offchan_tx_skb); 570 priv->offchan_tx_skb);
572 priv->_agn.offchan_tx_skb = NULL; 571 priv->offchan_tx_skb = NULL;
573 } 572 }
574 573
575 if (priv->scan_type != IWL_SCAN_NORMAL && !aborted) { 574 if (priv->scan_type != IWL_SCAN_NORMAL && !aborted) {
@@ -600,14 +599,7 @@ out_settings:
600 if (!iwl_is_ready_rf(priv)) 599 if (!iwl_is_ready_rf(priv))
601 goto out; 600 goto out;
602 601
603 /* 602 iwlagn_post_scan(priv);
604 * We do not commit power settings while scan is pending,
605 * do it now if the settings changed.
606 */
607 iwl_power_set_mode(priv, &priv->power_data.sleep_cmd_next, false);
608 iwl_set_tx_power(priv, priv->tx_power_next, false);
609
610 priv->cfg->ops->utils->post_scan(priv);
611 603
612out: 604out:
613 mutex_unlock(&priv->mutex); 605 mutex_unlock(&priv->mutex);
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c
index 7df2814fd4f8..1ef3b7106ad5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.c
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.c
@@ -35,6 +35,8 @@
35#include "iwl-dev.h" 35#include "iwl-dev.h"
36#include "iwl-core.h" 36#include "iwl-core.h"
37#include "iwl-sta.h" 37#include "iwl-sta.h"
38#include "iwl-trans.h"
39#include "iwl-agn.h"
38 40
39/* priv->sta_lock must be held */ 41/* priv->sta_lock must be held */
40static void iwl_sta_ucode_activate(struct iwl_priv *priv, u8 sta_id) 42static void iwl_sta_ucode_activate(struct iwl_priv *priv, u8 sta_id)
@@ -132,6 +134,16 @@ static void iwl_add_sta_callback(struct iwl_priv *priv,
132 134
133} 135}
134 136
137static u16 iwlagn_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
138{
139 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
140 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
141 memcpy(addsta, cmd, size);
142 /* resrved in 5000 */
143 addsta->rate_n_flags = cpu_to_le16(0);
144 return size;
145}
146
135int iwl_send_add_sta(struct iwl_priv *priv, 147int iwl_send_add_sta(struct iwl_priv *priv,
136 struct iwl_addsta_cmd *sta, u8 flags) 148 struct iwl_addsta_cmd *sta, u8 flags)
137{ 149{
@@ -155,8 +167,8 @@ int iwl_send_add_sta(struct iwl_priv *priv,
155 might_sleep(); 167 might_sleep();
156 } 168 }
157 169
158 cmd.len[0] = priv->cfg->ops->utils->build_addsta_hcmd(sta, data); 170 cmd.len[0] = iwlagn_build_addsta_hcmd(sta, data);
159 ret = iwl_send_cmd(priv, &cmd); 171 ret = trans_send_cmd(&priv->trans, &cmd);
160 172
161 if (ret || (flags & CMD_ASYNC)) 173 if (ret || (flags & CMD_ASYNC))
162 return ret; 174 return ret;
@@ -412,7 +424,7 @@ static int iwl_send_remove_station(struct iwl_priv *priv,
412 424
413 cmd.flags |= CMD_WANT_SKB; 425 cmd.flags |= CMD_WANT_SKB;
414 426
415 ret = iwl_send_cmd(priv, &cmd); 427 ret = trans_send_cmd(&priv->trans, &cmd);
416 428
417 if (ret) 429 if (ret)
418 return ret; 430 return ret;
@@ -657,7 +669,7 @@ void iwl_reprogram_ap_sta(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
657 iwl_send_lq_cmd(priv, ctx, &lq, CMD_SYNC, true); 669 iwl_send_lq_cmd(priv, ctx, &lq, CMD_SYNC, true);
658} 670}
659 671
660int iwl_get_free_ucode_key_index(struct iwl_priv *priv) 672int iwl_get_free_ucode_key_offset(struct iwl_priv *priv)
661{ 673{
662 int i; 674 int i;
663 675
@@ -781,7 +793,7 @@ int iwl_send_lq_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
781 return -EINVAL; 793 return -EINVAL;
782 794
783 if (is_lq_table_valid(priv, ctx, lq)) 795 if (is_lq_table_valid(priv, ctx, lq))
784 ret = iwl_send_cmd(priv, &cmd); 796 ret = trans_send_cmd(&priv->trans, &cmd);
785 else 797 else
786 ret = -EINVAL; 798 ret = -EINVAL;
787 799
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.h b/drivers/net/wireless/iwlwifi/iwl-sta.h
index ff64027ff4cb..9a6768d66851 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.h
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.h
@@ -31,9 +31,6 @@
31 31
32#include "iwl-dev.h" 32#include "iwl-dev.h"
33 33
34#define HW_KEY_DYNAMIC 0
35#define HW_KEY_DEFAULT 1
36
37#define IWL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */ 34#define IWL_STA_DRIVER_ACTIVE BIT(0) /* driver entry is active */
38#define IWL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */ 35#define IWL_STA_UCODE_ACTIVE BIT(1) /* ucode entry is active */
39#define IWL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of 36#define IWL_STA_UCODE_INPROGRESS BIT(2) /* ucode entry is in process of
@@ -47,7 +44,7 @@ void iwl_restore_stations(struct iwl_priv *priv, struct iwl_rxon_context *ctx);
47void iwl_clear_ucode_stations(struct iwl_priv *priv, 44void iwl_clear_ucode_stations(struct iwl_priv *priv,
48 struct iwl_rxon_context *ctx); 45 struct iwl_rxon_context *ctx);
49void iwl_dealloc_bcast_stations(struct iwl_priv *priv); 46void iwl_dealloc_bcast_stations(struct iwl_priv *priv);
50int iwl_get_free_ucode_key_index(struct iwl_priv *priv); 47int iwl_get_free_ucode_key_offset(struct iwl_priv *priv);
51int iwl_send_add_sta(struct iwl_priv *priv, 48int iwl_send_add_sta(struct iwl_priv *priv,
52 struct iwl_addsta_cmd *sta, u8 flags); 49 struct iwl_addsta_cmd *sta, u8 flags);
53int iwl_add_station_common(struct iwl_priv *priv, struct iwl_rxon_context *ctx, 50int iwl_add_station_common(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
diff --git a/drivers/net/wireless/iwlwifi/iwl-sv-open.c b/drivers/net/wireless/iwlwifi/iwl-sv-open.c
index 69b7e6bf2d6f..b11f60de4f1e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sv-open.c
+++ b/drivers/net/wireless/iwlwifi/iwl-sv-open.c
@@ -69,7 +69,6 @@
69#include <net/mac80211.h> 69#include <net/mac80211.h>
70#include <net/netlink.h> 70#include <net/netlink.h>
71 71
72
73#include "iwl-dev.h" 72#include "iwl-dev.h"
74#include "iwl-core.h" 73#include "iwl-core.h"
75#include "iwl-debug.h" 74#include "iwl-debug.h"
@@ -77,7 +76,7 @@
77#include "iwl-io.h" 76#include "iwl-io.h"
78#include "iwl-agn.h" 77#include "iwl-agn.h"
79#include "iwl-testmode.h" 78#include "iwl-testmode.h"
80 79#include "iwl-trans.h"
81 80
82/* The TLVs used in the gnl message policy between the kernel module and 81/* The TLVs used in the gnl message policy between the kernel module and
83 * user space application. iwl_testmode_gnl_msg_policy is to be carried 82 * user space application. iwl_testmode_gnl_msg_policy is to be carried
@@ -101,9 +100,12 @@ struct nla_policy iwl_testmode_gnl_msg_policy[IWL_TM_ATTR_MAX] = {
101 [IWL_TM_ATTR_EEPROM] = { .type = NLA_UNSPEC, }, 100 [IWL_TM_ATTR_EEPROM] = { .type = NLA_UNSPEC, },
102 101
103 [IWL_TM_ATTR_TRACE_ADDR] = { .type = NLA_UNSPEC, }, 102 [IWL_TM_ATTR_TRACE_ADDR] = { .type = NLA_UNSPEC, },
104 [IWL_TM_ATTR_TRACE_DATA] = { .type = NLA_UNSPEC, }, 103 [IWL_TM_ATTR_TRACE_DUMP] = { .type = NLA_UNSPEC, },
104 [IWL_TM_ATTR_TRACE_SIZE] = { .type = NLA_U32, },
105 105
106 [IWL_TM_ATTR_FIXRATE] = { .type = NLA_U32, }, 106 [IWL_TM_ATTR_FIXRATE] = { .type = NLA_U32, },
107
108 [IWL_TM_ATTR_UCODE_OWNER] = { .type = NLA_U8, },
107}; 109};
108 110
109/* 111/*
@@ -179,19 +181,19 @@ void iwl_testmode_init(struct iwl_priv *priv)
179 181
180static void iwl_trace_cleanup(struct iwl_priv *priv) 182static void iwl_trace_cleanup(struct iwl_priv *priv)
181{ 183{
182 struct device *dev = &priv->pci_dev->dev;
183
184 if (priv->testmode_trace.trace_enabled) { 184 if (priv->testmode_trace.trace_enabled) {
185 if (priv->testmode_trace.cpu_addr && 185 if (priv->testmode_trace.cpu_addr &&
186 priv->testmode_trace.dma_addr) 186 priv->testmode_trace.dma_addr)
187 dma_free_coherent(dev, 187 dma_free_coherent(priv->bus->dev,
188 TRACE_TOTAL_SIZE, 188 priv->testmode_trace.total_size,
189 priv->testmode_trace.cpu_addr, 189 priv->testmode_trace.cpu_addr,
190 priv->testmode_trace.dma_addr); 190 priv->testmode_trace.dma_addr);
191 priv->testmode_trace.trace_enabled = false; 191 priv->testmode_trace.trace_enabled = false;
192 priv->testmode_trace.cpu_addr = NULL; 192 priv->testmode_trace.cpu_addr = NULL;
193 priv->testmode_trace.trace_addr = NULL; 193 priv->testmode_trace.trace_addr = NULL;
194 priv->testmode_trace.dma_addr = 0; 194 priv->testmode_trace.dma_addr = 0;
195 priv->testmode_trace.buff_size = 0;
196 priv->testmode_trace.total_size = 0;
195 } 197 }
196} 198}
197 199
@@ -229,6 +231,7 @@ static int iwl_testmode_ucode(struct ieee80211_hw *hw, struct nlattr **tb)
229 return -ENOMSG; 231 return -ENOMSG;
230 } 232 }
231 233
234 cmd.flags = CMD_ON_DEMAND;
232 cmd.id = nla_get_u8(tb[IWL_TM_ATTR_UCODE_CMD_ID]); 235 cmd.id = nla_get_u8(tb[IWL_TM_ATTR_UCODE_CMD_ID]);
233 cmd.data[0] = nla_data(tb[IWL_TM_ATTR_UCODE_CMD_DATA]); 236 cmd.data[0] = nla_data(tb[IWL_TM_ATTR_UCODE_CMD_DATA]);
234 cmd.len[0] = nla_len(tb[IWL_TM_ATTR_UCODE_CMD_DATA]); 237 cmd.len[0] = nla_len(tb[IWL_TM_ATTR_UCODE_CMD_DATA]);
@@ -236,7 +239,7 @@ static int iwl_testmode_ucode(struct ieee80211_hw *hw, struct nlattr **tb)
236 IWL_INFO(priv, "testmode ucode command ID 0x%x, flags 0x%x," 239 IWL_INFO(priv, "testmode ucode command ID 0x%x, flags 0x%x,"
237 " len %d\n", cmd.id, cmd.flags, cmd.len[0]); 240 " len %d\n", cmd.id, cmd.flags, cmd.len[0]);
238 /* ok, let's submit the command to ucode */ 241 /* ok, let's submit the command to ucode */
239 return iwl_send_cmd(priv, &cmd); 242 return trans_send_cmd(&priv->trans, &cmd);
240} 243}
241 244
242 245
@@ -394,7 +397,7 @@ static int iwl_testmode_driver(struct ieee80211_hw *hw, struct nlattr **tb)
394 397
395 case IWL_TM_CMD_APP2DEV_LOAD_INIT_FW: 398 case IWL_TM_CMD_APP2DEV_LOAD_INIT_FW:
396 status = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init, 399 status = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
397 UCODE_SUBTYPE_INIT, -1); 400 IWL_UCODE_INIT);
398 if (status) 401 if (status)
399 IWL_DEBUG_INFO(priv, 402 IWL_DEBUG_INFO(priv,
400 "Error loading init ucode: %d\n", status); 403 "Error loading init ucode: %d\n", status);
@@ -402,14 +405,13 @@ static int iwl_testmode_driver(struct ieee80211_hw *hw, struct nlattr **tb)
402 405
403 case IWL_TM_CMD_APP2DEV_CFG_INIT_CALIB: 406 case IWL_TM_CMD_APP2DEV_CFG_INIT_CALIB:
404 iwl_testmode_cfg_init_calib(priv); 407 iwl_testmode_cfg_init_calib(priv);
405 iwlagn_stop_device(priv); 408 trans_stop_device(&priv->trans);
406 break; 409 break;
407 410
408 case IWL_TM_CMD_APP2DEV_LOAD_RUNTIME_FW: 411 case IWL_TM_CMD_APP2DEV_LOAD_RUNTIME_FW:
409 status = iwlagn_load_ucode_wait_alive(priv, 412 status = iwlagn_load_ucode_wait_alive(priv,
410 &priv->ucode_rt, 413 &priv->ucode_rt,
411 UCODE_SUBTYPE_REGULAR, 414 IWL_UCODE_REGULAR);
412 UCODE_SUBTYPE_REGULAR_NEW);
413 if (status) { 415 if (status) {
414 IWL_DEBUG_INFO(priv, 416 IWL_DEBUG_INFO(priv,
415 "Error loading runtime ucode: %d\n", status); 417 "Error loading runtime ucode: %d\n", status);
@@ -450,7 +452,7 @@ static int iwl_testmode_driver(struct ieee80211_hw *hw, struct nlattr **tb)
450 "Error finding fixrate setting\n"); 452 "Error finding fixrate setting\n");
451 return -ENOMSG; 453 return -ENOMSG;
452 } 454 }
453 priv->dbg_fixed_rate = nla_get_u32(tb[IWL_TM_ATTR_FIXRATE]); 455 priv->tm_fixed_rate = nla_get_u32(tb[IWL_TM_ATTR_FIXRATE]);
454 break; 456 break;
455 457
456 default: 458 default:
@@ -482,16 +484,29 @@ static int iwl_testmode_trace(struct ieee80211_hw *hw, struct nlattr **tb)
482 struct iwl_priv *priv = hw->priv; 484 struct iwl_priv *priv = hw->priv;
483 struct sk_buff *skb; 485 struct sk_buff *skb;
484 int status = 0; 486 int status = 0;
485 struct device *dev = &priv->pci_dev->dev; 487 struct device *dev = priv->bus->dev;
486 488
487 switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) { 489 switch (nla_get_u32(tb[IWL_TM_ATTR_COMMAND])) {
488 case IWL_TM_CMD_APP2DEV_BEGIN_TRACE: 490 case IWL_TM_CMD_APP2DEV_BEGIN_TRACE:
489 if (priv->testmode_trace.trace_enabled) 491 if (priv->testmode_trace.trace_enabled)
490 return -EBUSY; 492 return -EBUSY;
491 493
494 if (!tb[IWL_TM_ATTR_TRACE_SIZE])
495 priv->testmode_trace.buff_size = TRACE_BUFF_SIZE_DEF;
496 else
497 priv->testmode_trace.buff_size =
498 nla_get_u32(tb[IWL_TM_ATTR_TRACE_SIZE]);
499 if (!priv->testmode_trace.buff_size)
500 return -EINVAL;
501 if (priv->testmode_trace.buff_size < TRACE_BUFF_SIZE_MIN ||
502 priv->testmode_trace.buff_size > TRACE_BUFF_SIZE_MAX)
503 return -EINVAL;
504
505 priv->testmode_trace.total_size =
506 priv->testmode_trace.buff_size + TRACE_BUFF_PADD;
492 priv->testmode_trace.cpu_addr = 507 priv->testmode_trace.cpu_addr =
493 dma_alloc_coherent(dev, 508 dma_alloc_coherent(dev,
494 TRACE_TOTAL_SIZE, 509 priv->testmode_trace.total_size,
495 &priv->testmode_trace.dma_addr, 510 &priv->testmode_trace.dma_addr,
496 GFP_KERNEL); 511 GFP_KERNEL);
497 if (!priv->testmode_trace.cpu_addr) 512 if (!priv->testmode_trace.cpu_addr)
@@ -500,7 +515,7 @@ static int iwl_testmode_trace(struct ieee80211_hw *hw, struct nlattr **tb)
500 priv->testmode_trace.trace_addr = (u8 *)PTR_ALIGN( 515 priv->testmode_trace.trace_addr = (u8 *)PTR_ALIGN(
501 priv->testmode_trace.cpu_addr, 0x100); 516 priv->testmode_trace.cpu_addr, 0x100);
502 memset(priv->testmode_trace.trace_addr, 0x03B, 517 memset(priv->testmode_trace.trace_addr, 0x03B,
503 TRACE_BUFF_SIZE); 518 priv->testmode_trace.buff_size);
504 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy, 519 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy,
505 sizeof(priv->testmode_trace.dma_addr) + 20); 520 sizeof(priv->testmode_trace.dma_addr) + 20);
506 if (!skb) { 521 if (!skb) {
@@ -518,34 +533,14 @@ static int iwl_testmode_trace(struct ieee80211_hw *hw, struct nlattr **tb)
518 "Error sending msg : %d\n", 533 "Error sending msg : %d\n",
519 status); 534 status);
520 } 535 }
536 priv->testmode_trace.num_chunks =
537 DIV_ROUND_UP(priv->testmode_trace.buff_size,
538 TRACE_CHUNK_SIZE);
521 break; 539 break;
522 540
523 case IWL_TM_CMD_APP2DEV_END_TRACE: 541 case IWL_TM_CMD_APP2DEV_END_TRACE:
524 iwl_trace_cleanup(priv); 542 iwl_trace_cleanup(priv);
525 break; 543 break;
526
527 case IWL_TM_CMD_APP2DEV_READ_TRACE:
528 if (priv->testmode_trace.trace_enabled &&
529 priv->testmode_trace.trace_addr) {
530 skb = cfg80211_testmode_alloc_reply_skb(hw->wiphy,
531 20 + TRACE_BUFF_SIZE);
532 if (skb == NULL) {
533 IWL_DEBUG_INFO(priv,
534 "Error allocating memory\n");
535 return -ENOMEM;
536 }
537 NLA_PUT(skb, IWL_TM_ATTR_TRACE_DATA,
538 TRACE_BUFF_SIZE,
539 priv->testmode_trace.trace_addr);
540 status = cfg80211_testmode_reply(skb);
541 if (status < 0) {
542 IWL_DEBUG_INFO(priv,
543 "Error sending msg : %d\n", status);
544 }
545 } else
546 return -EFAULT;
547 break;
548
549 default: 544 default:
550 IWL_DEBUG_INFO(priv, "Unknown testmode mem command ID\n"); 545 IWL_DEBUG_INFO(priv, "Unknown testmode mem command ID\n");
551 return -ENOSYS; 546 return -ENOSYS;
@@ -560,6 +555,73 @@ nla_put_failure:
560 return -EMSGSIZE; 555 return -EMSGSIZE;
561} 556}
562 557
558static int iwl_testmode_trace_dump(struct ieee80211_hw *hw, struct nlattr **tb,
559 struct sk_buff *skb,
560 struct netlink_callback *cb)
561{
562 struct iwl_priv *priv = hw->priv;
563 int idx, length;
564
565 if (priv->testmode_trace.trace_enabled &&
566 priv->testmode_trace.trace_addr) {
567 idx = cb->args[4];
568 if (idx >= priv->testmode_trace.num_chunks)
569 return -ENOENT;
570 length = TRACE_CHUNK_SIZE;
571 if (((idx + 1) == priv->testmode_trace.num_chunks) &&
572 (priv->testmode_trace.buff_size % TRACE_CHUNK_SIZE))
573 length = priv->testmode_trace.buff_size %
574 TRACE_CHUNK_SIZE;
575
576 NLA_PUT(skb, IWL_TM_ATTR_TRACE_DUMP, length,
577 priv->testmode_trace.trace_addr +
578 (TRACE_CHUNK_SIZE * idx));
579 idx++;
580 cb->args[4] = idx;
581 return 0;
582 } else
583 return -EFAULT;
584
585 nla_put_failure:
586 return -ENOBUFS;
587}
588
589/*
590 * This function handles the user application switch ucode ownership.
591 *
592 * It retrieves the mandatory fields IWL_TM_ATTR_UCODE_OWNER and
593 * decide who the current owner of the uCode
594 *
595 * If the current owner is OWNERSHIP_TM, then the only host command
596 * can deliver to uCode is from testmode, all the other host commands
597 * will dropped.
598 *
599 * default driver is the owner of uCode in normal operational mode
600 *
601 * @hw: ieee80211_hw object that represents the device
602 * @tb: gnl message fields from the user space
603 */
604static int iwl_testmode_ownership(struct ieee80211_hw *hw, struct nlattr **tb)
605{
606 struct iwl_priv *priv = hw->priv;
607 u8 owner;
608
609 if (!tb[IWL_TM_ATTR_UCODE_OWNER]) {
610 IWL_DEBUG_INFO(priv, "Error finding ucode owner\n");
611 return -ENOMSG;
612 }
613
614 owner = nla_get_u8(tb[IWL_TM_ATTR_UCODE_OWNER]);
615 if ((owner == IWL_OWNERSHIP_DRIVER) || (owner == IWL_OWNERSHIP_TM))
616 priv->ucode_owner = owner;
617 else {
618 IWL_DEBUG_INFO(priv, "Invalid owner\n");
619 return -EINVAL;
620 }
621 return 0;
622}
623
624
563/* The testmode gnl message handler that takes the gnl message from the 625/* The testmode gnl message handler that takes the gnl message from the
564 * user space and parses it per the policy iwl_testmode_gnl_msg_policy, then 626 * user space and parses it per the policy iwl_testmode_gnl_msg_policy, then
565 * invoke the corresponding handlers. 627 * invoke the corresponding handlers.
@@ -581,7 +643,7 @@ nla_put_failure:
581 */ 643 */
582int iwl_testmode_cmd(struct ieee80211_hw *hw, void *data, int len) 644int iwl_testmode_cmd(struct ieee80211_hw *hw, void *data, int len)
583{ 645{
584 struct nlattr *tb[IWL_TM_ATTR_MAX - 1]; 646 struct nlattr *tb[IWL_TM_ATTR_MAX];
585 struct iwl_priv *priv = hw->priv; 647 struct iwl_priv *priv = hw->priv;
586 int result; 648 int result;
587 649
@@ -629,6 +691,11 @@ int iwl_testmode_cmd(struct ieee80211_hw *hw, void *data, int len)
629 result = iwl_testmode_trace(hw, tb); 691 result = iwl_testmode_trace(hw, tb);
630 break; 692 break;
631 693
694 case IWL_TM_CMD_APP2DEV_OWNERSHIP:
695 IWL_DEBUG_INFO(priv, "testmode change uCode ownership\n");
696 result = iwl_testmode_ownership(hw, tb);
697 break;
698
632 default: 699 default:
633 IWL_DEBUG_INFO(priv, "Unknown testmode command\n"); 700 IWL_DEBUG_INFO(priv, "Unknown testmode command\n");
634 result = -ENOSYS; 701 result = -ENOSYS;
@@ -638,3 +705,50 @@ int iwl_testmode_cmd(struct ieee80211_hw *hw, void *data, int len)
638 mutex_unlock(&priv->mutex); 705 mutex_unlock(&priv->mutex);
639 return result; 706 return result;
640} 707}
708
709int iwl_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
710 struct netlink_callback *cb,
711 void *data, int len)
712{
713 struct nlattr *tb[IWL_TM_ATTR_MAX];
714 struct iwl_priv *priv = hw->priv;
715 int result;
716 u32 cmd;
717
718 if (cb->args[3]) {
719 /* offset by 1 since commands start at 0 */
720 cmd = cb->args[3] - 1;
721 } else {
722 result = nla_parse(tb, IWL_TM_ATTR_MAX - 1, data, len,
723 iwl_testmode_gnl_msg_policy);
724 if (result) {
725 IWL_DEBUG_INFO(priv,
726 "Error parsing the gnl message : %d\n", result);
727 return result;
728 }
729
730 /* IWL_TM_ATTR_COMMAND is absolutely mandatory */
731 if (!tb[IWL_TM_ATTR_COMMAND]) {
732 IWL_DEBUG_INFO(priv,
733 "Error finding testmode command type\n");
734 return -ENOMSG;
735 }
736 cmd = nla_get_u32(tb[IWL_TM_ATTR_COMMAND]);
737 cb->args[3] = cmd + 1;
738 }
739
740 /* in case multiple accesses to the device happens */
741 mutex_lock(&priv->mutex);
742 switch (cmd) {
743 case IWL_TM_CMD_APP2DEV_READ_TRACE:
744 IWL_DEBUG_INFO(priv, "uCode trace cmd to driver\n");
745 result = iwl_testmode_trace_dump(hw, tb, skb, cb);
746 break;
747 default:
748 result = -EINVAL;
749 break;
750 }
751
752 mutex_unlock(&priv->mutex);
753 return result;
754}
diff --git a/drivers/net/wireless/iwlwifi/iwl-testmode.h b/drivers/net/wireless/iwlwifi/iwl-testmode.h
index a88085e9b361..b980bda4b0f8 100644
--- a/drivers/net/wireless/iwlwifi/iwl-testmode.h
+++ b/drivers/net/wireless/iwlwifi/iwl-testmode.h
@@ -66,120 +66,161 @@
66#include <linux/types.h> 66#include <linux/types.h>
67 67
68 68
69/* Commands from user space to kernel space(IWL_TM_CMD_ID_APP2DEV_XX) and 69/*
70 * Commands from user space to kernel space(IWL_TM_CMD_ID_APP2DEV_XX) and
70 * from and kernel space to user space(IWL_TM_CMD_ID_DEV2APP_XX). 71 * from and kernel space to user space(IWL_TM_CMD_ID_DEV2APP_XX).
71 * The command ID is carried with IWL_TM_ATTR_COMMAND. There are three types of 72 * The command ID is carried with IWL_TM_ATTR_COMMAND.
72 * of command from user space and two types of command from kernel space. 73 *
73 * See below. 74 * @IWL_TM_CMD_APP2DEV_UCODE:
75 * commands from user application to the uCode,
76 * the actual uCode host command ID is carried with
77 * IWL_TM_ATTR_UCODE_CMD_ID
78 *
79 * @IWL_TM_CMD_APP2DEV_REG_READ32:
80 * @IWL_TM_CMD_APP2DEV_REG_WRITE32:
81 * @IWL_TM_CMD_APP2DEV_REG_WRITE8:
82 * commands from user applicaiton to access register
83 *
84 * @IWL_TM_CMD_APP2DEV_GET_DEVICENAME: retrieve device name
85 * @IWL_TM_CMD_APP2DEV_LOAD_INIT_FW: load initial uCode image
86 * @IWL_TM_CMD_APP2DEV_CFG_INIT_CALIB: perform calibration
87 * @IWL_TM_CMD_APP2DEV_LOAD_RUNTIME_FW: load runtime uCode image
88 * @IWL_TM_CMD_APP2DEV_GET_EEPROM: request EEPROM data
89 * @IWL_TM_CMD_APP2DEV_FIXRATE_REQ: set fix MCS
90 * commands fom user space for pure driver level operations
91 *
92 * @IWL_TM_CMD_APP2DEV_BEGIN_TRACE:
93 * @IWL_TM_CMD_APP2DEV_END_TRACE:
94 * @IWL_TM_CMD_APP2DEV_READ_TRACE:
95 * commands fom user space for uCode trace operations
96 *
97 * @IWL_TM_CMD_DEV2APP_SYNC_RSP:
98 * commands from kernel space to carry the synchronous response
99 * to user application
100 * @IWL_TM_CMD_DEV2APP_UCODE_RX_PKT:
101 * commands from kernel space to multicast the spontaneous messages
102 * to user application
103 * @IWL_TM_CMD_DEV2APP_EEPROM_RSP:
104 * commands from kernel space to carry the eeprom response
105 * to user application
106 * @IWL_TM_CMD_APP2DEV_OWNERSHIP:
107 * commands from user application to own change the ownership of the uCode
108 * if application has the ownership, the only host command from
109 * testmode will deliver to uCode. Default owner is driver
74 */ 110 */
75enum iwl_tm_cmd_t { 111enum iwl_tm_cmd_t {
76 /* commands from user application to the uCode, 112 IWL_TM_CMD_APP2DEV_UCODE = 1,
77 * the actual uCode host command ID is carried with 113 IWL_TM_CMD_APP2DEV_REG_READ32 = 2,
78 * IWL_TM_ATTR_UCODE_CMD_ID */ 114 IWL_TM_CMD_APP2DEV_REG_WRITE32 = 3,
79 IWL_TM_CMD_APP2DEV_UCODE = 1, 115 IWL_TM_CMD_APP2DEV_REG_WRITE8 = 4,
80 116 IWL_TM_CMD_APP2DEV_GET_DEVICENAME = 5,
81 /* commands from user applicaiton to access register */ 117 IWL_TM_CMD_APP2DEV_LOAD_INIT_FW = 6,
82 IWL_TM_CMD_APP2DEV_REG_READ32, 118 IWL_TM_CMD_APP2DEV_CFG_INIT_CALIB = 7,
83 IWL_TM_CMD_APP2DEV_REG_WRITE32, 119 IWL_TM_CMD_APP2DEV_LOAD_RUNTIME_FW = 8,
84 IWL_TM_CMD_APP2DEV_REG_WRITE8, 120 IWL_TM_CMD_APP2DEV_GET_EEPROM = 9,
85 121 IWL_TM_CMD_APP2DEV_FIXRATE_REQ = 10,
86 /* commands fom user space for pure driver level operations */ 122 IWL_TM_CMD_APP2DEV_BEGIN_TRACE = 11,
87 IWL_TM_CMD_APP2DEV_GET_DEVICENAME, 123 IWL_TM_CMD_APP2DEV_END_TRACE = 12,
88 IWL_TM_CMD_APP2DEV_LOAD_INIT_FW, 124 IWL_TM_CMD_APP2DEV_READ_TRACE = 13,
89 IWL_TM_CMD_APP2DEV_CFG_INIT_CALIB, 125 IWL_TM_CMD_DEV2APP_SYNC_RSP = 14,
90 IWL_TM_CMD_APP2DEV_LOAD_RUNTIME_FW, 126 IWL_TM_CMD_DEV2APP_UCODE_RX_PKT = 15,
91 IWL_TM_CMD_APP2DEV_GET_EEPROM, 127 IWL_TM_CMD_DEV2APP_EEPROM_RSP = 16,
92 IWL_TM_CMD_APP2DEV_FIXRATE_REQ, 128 IWL_TM_CMD_APP2DEV_OWNERSHIP = 17,
93 /* if there is other new command for the driver layer operation, 129 IWL_TM_CMD_MAX = 18,
94 * append them here */
95
96 /* commands fom user space for uCode trace operations */
97 IWL_TM_CMD_APP2DEV_BEGIN_TRACE,
98 IWL_TM_CMD_APP2DEV_END_TRACE,
99 IWL_TM_CMD_APP2DEV_READ_TRACE,
100
101 /* commands from kernel space to carry the synchronous response
102 * to user application */
103 IWL_TM_CMD_DEV2APP_SYNC_RSP,
104
105 /* commands from kernel space to multicast the spontaneous messages
106 * to user application */
107 IWL_TM_CMD_DEV2APP_UCODE_RX_PKT,
108
109 /* commands from kernel space to carry the eeprom response
110 * to user application */
111 IWL_TM_CMD_DEV2APP_EEPROM_RSP,
112
113 IWL_TM_CMD_MAX,
114}; 130};
115 131
132/*
133 * Atrribute filed in testmode command
134 * See enum iwl_tm_cmd_t.
135 *
136 * @IWL_TM_ATTR_NOT_APPLICABLE:
137 * The attribute is not applicable or invalid
138 * @IWL_TM_ATTR_COMMAND:
139 * From user space to kernel space:
140 * the command either destines to ucode, driver, or register;
141 * From kernel space to user space:
142 * the command either carries synchronous response,
143 * or the spontaneous message multicast from the device;
144 *
145 * @IWL_TM_ATTR_UCODE_CMD_ID:
146 * @IWL_TM_ATTR_UCODE_CMD_DATA:
147 * When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_UCODE,
148 * The mandatory fields are :
149 * IWL_TM_ATTR_UCODE_CMD_ID for recognizable command ID;
150 * IWL_TM_ATTR_COMMAND_FLAG for the flags of the commands;
151 * The optional fields are:
152 * IWL_TM_ATTR_UCODE_CMD_DATA for the actual command payload
153 * to the ucode
154 *
155 * @IWL_TM_ATTR_REG_OFFSET:
156 * @IWL_TM_ATTR_REG_VALUE8:
157 * @IWL_TM_ATTR_REG_VALUE32:
158 * When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_REG_XXX,
159 * The mandatory fields are:
160 * IWL_TM_ATTR_REG_OFFSET for the offset of the target register;
161 * IWL_TM_ATTR_REG_VALUE8 or IWL_TM_ATTR_REG_VALUE32 for value
162 *
163 * @IWL_TM_ATTR_SYNC_RSP:
164 * When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_DEV2APP_SYNC_RSP,
165 * The mandatory fields are:
166 * IWL_TM_ATTR_SYNC_RSP for the data content responding to the user
167 * application command
168 *
169 * @IWL_TM_ATTR_UCODE_RX_PKT:
170 * When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_DEV2APP_UCODE_RX_PKT,
171 * The mandatory fields are:
172 * IWL_TM_ATTR_UCODE_RX_PKT for the data content multicast to the user
173 * application
174 *
175 * @IWL_TM_ATTR_EEPROM:
176 * When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_DEV2APP_EEPROM,
177 * The mandatory fields are:
178 * IWL_TM_ATTR_EEPROM for the data content responging to the user
179 * application
180 *
181 * @IWL_TM_ATTR_TRACE_ADDR:
182 * @IWL_TM_ATTR_TRACE_SIZE:
183 * @IWL_TM_ATTR_TRACE_DUMP:
184 * When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_XXX_TRACE,
185 * The mandatory fields are:
186 * IWL_TM_ATTR_MEM_TRACE_ADDR for the trace address
187 * IWL_TM_ATTR_MEM_TRACE_SIZE for the trace buffer size
188 * IWL_TM_ATTR_MEM_TRACE_DUMP for the trace dump
189 *
190 * @IWL_TM_ATTR_FIXRATE:
191 * When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_FIXRATE_REQ,
192 * The mandatory fields are:
193 * IWL_TM_ATTR_FIXRATE for the fixed rate
194 *
195 * @IWL_TM_ATTR_UCODE_OWNER:
196 * When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_OWNERSHIP,
197 * The mandatory fields are:
198 * IWL_TM_ATTR_UCODE_OWNER for the new owner
199 */
116enum iwl_tm_attr_t { 200enum iwl_tm_attr_t {
117 IWL_TM_ATTR_NOT_APPLICABLE = 0, 201 IWL_TM_ATTR_NOT_APPLICABLE = 0,
118 202 IWL_TM_ATTR_COMMAND = 1,
119 /* From user space to kernel space: 203 IWL_TM_ATTR_UCODE_CMD_ID = 2,
120 * the command either destines to ucode, driver, or register; 204 IWL_TM_ATTR_UCODE_CMD_DATA = 3,
121 * See enum iwl_tm_cmd_t. 205 IWL_TM_ATTR_REG_OFFSET = 4,
122 * 206 IWL_TM_ATTR_REG_VALUE8 = 5,
123 * From kernel space to user space: 207 IWL_TM_ATTR_REG_VALUE32 = 6,
124 * the command either carries synchronous response, 208 IWL_TM_ATTR_SYNC_RSP = 7,
125 * or the spontaneous message multicast from the device; 209 IWL_TM_ATTR_UCODE_RX_PKT = 8,
126 * See enum iwl_tm_cmd_t. */ 210 IWL_TM_ATTR_EEPROM = 9,
127 IWL_TM_ATTR_COMMAND, 211 IWL_TM_ATTR_TRACE_ADDR = 10,
128 212 IWL_TM_ATTR_TRACE_SIZE = 11,
129 /* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_UCODE, 213 IWL_TM_ATTR_TRACE_DUMP = 12,
130 * The mandatory fields are : 214 IWL_TM_ATTR_FIXRATE = 13,
131 * IWL_TM_ATTR_UCODE_CMD_ID for recognizable command ID; 215 IWL_TM_ATTR_UCODE_OWNER = 14,
132 * IWL_TM_ATTR_COMMAND_FLAG for the flags of the commands; 216 IWL_TM_ATTR_MAX = 15,
133 * The optional fields are:
134 * IWL_TM_ATTR_UCODE_CMD_DATA for the actual command payload
135 * to the ucode */
136 IWL_TM_ATTR_UCODE_CMD_ID,
137 IWL_TM_ATTR_UCODE_CMD_DATA,
138
139 /* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_REG_XXX,
140 * The mandatory fields are:
141 * IWL_TM_ATTR_REG_OFFSET for the offset of the target register;
142 * IWL_TM_ATTR_REG_VALUE8 or IWL_TM_ATTR_REG_VALUE32 for value */
143 IWL_TM_ATTR_REG_OFFSET,
144 IWL_TM_ATTR_REG_VALUE8,
145 IWL_TM_ATTR_REG_VALUE32,
146
147 /* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_DEV2APP_SYNC_RSP,
148 * The mandatory fields are:
149 * IWL_TM_ATTR_SYNC_RSP for the data content responding to the user
150 * application command */
151 IWL_TM_ATTR_SYNC_RSP,
152 /* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_DEV2APP_UCODE_RX_PKT,
153 * The mandatory fields are:
154 * IWL_TM_ATTR_UCODE_RX_PKT for the data content multicast to the user
155 * application */
156 IWL_TM_ATTR_UCODE_RX_PKT,
157
158 /* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_DEV2APP_EEPROM,
159 * The mandatory fields are:
160 * IWL_TM_ATTR_EEPROM for the data content responging to the user
161 * application */
162 IWL_TM_ATTR_EEPROM,
163
164 /* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_XXX_TRACE,
165 * The mandatory fields are:
166 * IWL_TM_ATTR_MEM_TRACE_ADDR for the trace address
167 */
168 IWL_TM_ATTR_TRACE_ADDR,
169 IWL_TM_ATTR_TRACE_DATA,
170
171 /* When IWL_TM_ATTR_COMMAND is IWL_TM_CMD_APP2DEV_FIXRATE_REQ,
172 * The mandatory fields are:
173 * IWL_TM_ATTR_FIXRATE for the fixed rate
174 */
175 IWL_TM_ATTR_FIXRATE,
176
177 IWL_TM_ATTR_MAX,
178}; 217};
179 218
180/* uCode trace buffer */ 219/* uCode trace buffer */
181#define TRACE_BUFF_SIZE 0x20000 220#define TRACE_BUFF_SIZE_MAX 0x200000
221#define TRACE_BUFF_SIZE_MIN 0x20000
222#define TRACE_BUFF_SIZE_DEF TRACE_BUFF_SIZE_MIN
182#define TRACE_BUFF_PADD 0x2000 223#define TRACE_BUFF_PADD 0x2000
183#define TRACE_TOTAL_SIZE (TRACE_BUFF_SIZE + TRACE_BUFF_PADD) 224#define TRACE_CHUNK_SIZE (PAGE_SIZE - 1024)
184 225
185#endif 226#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h b/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h
new file mode 100644
index 000000000000..b79330d84185
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-int-pcie.h
@@ -0,0 +1,82 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29#ifndef __iwl_trans_int_pcie_h__
30#define __iwl_trans_int_pcie_h__
31
32/*This file includes the declaration that are internal to the
33 * trans_pcie layer */
34
35/*****************************************************
36* RX
37******************************************************/
38void iwl_bg_rx_replenish(struct work_struct *data);
39void iwl_irq_tasklet(struct iwl_priv *priv);
40void iwlagn_rx_replenish(struct iwl_priv *priv);
41void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
42 struct iwl_rx_queue *q);
43
44/*****************************************************
45* ICT
46******************************************************/
47int iwl_reset_ict(struct iwl_priv *priv);
48void iwl_disable_ict(struct iwl_priv *priv);
49int iwl_alloc_isr_ict(struct iwl_priv *priv);
50void iwl_free_isr_ict(struct iwl_priv *priv);
51irqreturn_t iwl_isr_ict(int irq, void *data);
52
53
54/*****************************************************
55* TX / HCMD
56******************************************************/
57void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq);
58void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq,
59 int index);
60int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
61 struct iwl_tx_queue *txq,
62 dma_addr_t addr, u16 len, u8 reset);
63int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
64 int count, int slots_num, u32 id);
65int iwl_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
66int __must_check iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u32 flags,
67 u16 len, const void *data);
68void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb);
69void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
70 struct iwl_tx_queue *txq,
71 u16 byte_cnt);
72int iwl_trans_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
73 u16 ssn_idx, u8 tx_fifo);
74void iwl_trans_set_wr_ptrs(struct iwl_priv *priv,
75 int txq_id, u32 index);
76void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
77 struct iwl_tx_queue *txq,
78 int tx_fifo_id, int scd_retry);
79void iwl_trans_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
80 int frame_limit);
81
82#endif /* __iwl_trans_int_pcie_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c
new file mode 100644
index 000000000000..474860290404
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c
@@ -0,0 +1,979 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29#include <linux/sched.h>
30#include <linux/wait.h>
31#include <linux/gfp.h>
32
33#include "iwl-dev.h"
34#include "iwl-agn.h"
35#include "iwl-core.h"
36#include "iwl-io.h"
37#include "iwl-helpers.h"
38#include "iwl-trans-int-pcie.h"
39
40/******************************************************************************
41 *
42 * RX path functions
43 *
44 ******************************************************************************/
45
46/*
47 * Rx theory of operation
48 *
49 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
50 * each of which point to Receive Buffers to be filled by the NIC. These get
51 * used not only for Rx frames, but for any command response or notification
52 * from the NIC. The driver and NIC manage the Rx buffers by means
53 * of indexes into the circular buffer.
54 *
55 * Rx Queue Indexes
56 * The host/firmware share two index registers for managing the Rx buffers.
57 *
58 * The READ index maps to the first position that the firmware may be writing
59 * to -- the driver can read up to (but not including) this position and get
60 * good data.
61 * The READ index is managed by the firmware once the card is enabled.
62 *
63 * The WRITE index maps to the last position the driver has read from -- the
64 * position preceding WRITE is the last slot the firmware can place a packet.
65 *
66 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
67 * WRITE = READ.
68 *
69 * During initialization, the host sets up the READ queue position to the first
70 * INDEX position, and WRITE to the last (READ - 1 wrapped)
71 *
72 * When the firmware places a packet in a buffer, it will advance the READ index
73 * and fire the RX interrupt. The driver can then query the READ index and
74 * process as many packets as possible, moving the WRITE index forward as it
75 * resets the Rx queue buffers with new memory.
76 *
77 * The management in the driver is as follows:
78 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
79 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
80 * to replenish the iwl->rxq->rx_free.
81 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
82 * iwl->rxq is replenished and the READ INDEX is updated (updating the
83 * 'processed' and 'read' driver indexes as well)
84 * + A received packet is processed and handed to the kernel network stack,
85 * detached from the iwl->rxq. The driver 'processed' index is updated.
86 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
87 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
88 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
89 * were enough free buffers and RX_STALLED is set it is cleared.
90 *
91 *
92 * Driver sequence:
93 *
94 * iwl_rx_queue_alloc() Allocates rx_free
95 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
96 * iwl_rx_queue_restock
97 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
98 * queue, updates firmware pointers, and updates
99 * the WRITE index. If insufficient rx_free buffers
100 * are available, schedules iwl_rx_replenish
101 *
102 * -- enable interrupts --
103 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
104 * READ INDEX, detaching the SKB from the pool.
105 * Moves the packet buffer from queue to rx_used.
106 * Calls iwl_rx_queue_restock to refill any empty
107 * slots.
108 * ...
109 *
110 */
111
112/**
113 * iwl_rx_queue_space - Return number of free slots available in queue.
114 */
115static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
116{
117 int s = q->read - q->write;
118 if (s <= 0)
119 s += RX_QUEUE_SIZE;
120 /* keep some buffer to not confuse full and empty queue */
121 s -= 2;
122 if (s < 0)
123 s = 0;
124 return s;
125}
126
127/**
128 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
129 */
130void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv,
131 struct iwl_rx_queue *q)
132{
133 unsigned long flags;
134 u32 reg;
135
136 spin_lock_irqsave(&q->lock, flags);
137
138 if (q->need_update == 0)
139 goto exit_unlock;
140
141 if (priv->cfg->base_params->shadow_reg_enable) {
142 /* shadow register enabled */
143 /* Device expects a multiple of 8 */
144 q->write_actual = (q->write & ~0x7);
145 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write_actual);
146 } else {
147 /* If power-saving is in use, make sure device is awake */
148 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
149 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
150
151 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
152 IWL_DEBUG_INFO(priv,
153 "Rx queue requesting wakeup,"
154 " GP1 = 0x%x\n", reg);
155 iwl_set_bit(priv, CSR_GP_CNTRL,
156 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
157 goto exit_unlock;
158 }
159
160 q->write_actual = (q->write & ~0x7);
161 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
162 q->write_actual);
163
164 /* Else device is assumed to be awake */
165 } else {
166 /* Device expects a multiple of 8 */
167 q->write_actual = (q->write & ~0x7);
168 iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
169 q->write_actual);
170 }
171 }
172 q->need_update = 0;
173
174 exit_unlock:
175 spin_unlock_irqrestore(&q->lock, flags);
176}
177
178/**
179 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
180 */
181static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
182 dma_addr_t dma_addr)
183{
184 return cpu_to_le32((u32)(dma_addr >> 8));
185}
186
187/**
188 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
189 *
190 * If there are slots in the RX queue that need to be restocked,
191 * and we have free pre-allocated buffers, fill the ranks as much
192 * as we can, pulling from rx_free.
193 *
194 * This moves the 'write' index forward to catch up with 'processed', and
195 * also updates the memory address in the firmware to reference the new
196 * target buffer.
197 */
198static void iwlagn_rx_queue_restock(struct iwl_priv *priv)
199{
200 struct iwl_rx_queue *rxq = &priv->rxq;
201 struct list_head *element;
202 struct iwl_rx_mem_buffer *rxb;
203 unsigned long flags;
204
205 spin_lock_irqsave(&rxq->lock, flags);
206 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
207 /* The overwritten rxb must be a used one */
208 rxb = rxq->queue[rxq->write];
209 BUG_ON(rxb && rxb->page);
210
211 /* Get next free Rx buffer, remove from free list */
212 element = rxq->rx_free.next;
213 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
214 list_del(element);
215
216 /* Point to Rx buffer via next RBD in circular buffer */
217 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
218 rxb->page_dma);
219 rxq->queue[rxq->write] = rxb;
220 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
221 rxq->free_count--;
222 }
223 spin_unlock_irqrestore(&rxq->lock, flags);
224 /* If the pre-allocated buffer pool is dropping low, schedule to
225 * refill it */
226 if (rxq->free_count <= RX_LOW_WATERMARK)
227 queue_work(priv->workqueue, &priv->rx_replenish);
228
229
230 /* If we've added more space for the firmware to place data, tell it.
231 * Increment device's write pointer in multiples of 8. */
232 if (rxq->write_actual != (rxq->write & ~0x7)) {
233 spin_lock_irqsave(&rxq->lock, flags);
234 rxq->need_update = 1;
235 spin_unlock_irqrestore(&rxq->lock, flags);
236 iwl_rx_queue_update_write_ptr(priv, rxq);
237 }
238}
239
240/**
241 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
242 *
243 * When moving to rx_free an SKB is allocated for the slot.
244 *
245 * Also restock the Rx queue via iwl_rx_queue_restock.
246 * This is called as a scheduled work item (except for during initialization)
247 */
248static void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
249{
250 struct iwl_rx_queue *rxq = &priv->rxq;
251 struct list_head *element;
252 struct iwl_rx_mem_buffer *rxb;
253 struct page *page;
254 unsigned long flags;
255 gfp_t gfp_mask = priority;
256
257 while (1) {
258 spin_lock_irqsave(&rxq->lock, flags);
259 if (list_empty(&rxq->rx_used)) {
260 spin_unlock_irqrestore(&rxq->lock, flags);
261 return;
262 }
263 spin_unlock_irqrestore(&rxq->lock, flags);
264
265 if (rxq->free_count > RX_LOW_WATERMARK)
266 gfp_mask |= __GFP_NOWARN;
267
268 if (priv->hw_params.rx_page_order > 0)
269 gfp_mask |= __GFP_COMP;
270
271 /* Alloc a new receive buffer */
272 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
273 if (!page) {
274 if (net_ratelimit())
275 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
276 "order: %d\n",
277 priv->hw_params.rx_page_order);
278
279 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
280 net_ratelimit())
281 IWL_CRIT(priv, "Failed to alloc_pages with %s."
282 "Only %u free buffers remaining.\n",
283 priority == GFP_ATOMIC ?
284 "GFP_ATOMIC" : "GFP_KERNEL",
285 rxq->free_count);
286 /* We don't reschedule replenish work here -- we will
287 * call the restock method and if it still needs
288 * more buffers it will schedule replenish */
289 return;
290 }
291
292 spin_lock_irqsave(&rxq->lock, flags);
293
294 if (list_empty(&rxq->rx_used)) {
295 spin_unlock_irqrestore(&rxq->lock, flags);
296 __free_pages(page, priv->hw_params.rx_page_order);
297 return;
298 }
299 element = rxq->rx_used.next;
300 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
301 list_del(element);
302
303 spin_unlock_irqrestore(&rxq->lock, flags);
304
305 BUG_ON(rxb->page);
306 rxb->page = page;
307 /* Get physical address of the RB */
308 rxb->page_dma = dma_map_page(priv->bus->dev, page, 0,
309 PAGE_SIZE << priv->hw_params.rx_page_order,
310 DMA_FROM_DEVICE);
311 /* dma address must be no more than 36 bits */
312 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
313 /* and also 256 byte aligned! */
314 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
315
316 spin_lock_irqsave(&rxq->lock, flags);
317
318 list_add_tail(&rxb->list, &rxq->rx_free);
319 rxq->free_count++;
320
321 spin_unlock_irqrestore(&rxq->lock, flags);
322 }
323}
324
325void iwlagn_rx_replenish(struct iwl_priv *priv)
326{
327 unsigned long flags;
328
329 iwlagn_rx_allocate(priv, GFP_KERNEL);
330
331 spin_lock_irqsave(&priv->lock, flags);
332 iwlagn_rx_queue_restock(priv);
333 spin_unlock_irqrestore(&priv->lock, flags);
334}
335
336static void iwlagn_rx_replenish_now(struct iwl_priv *priv)
337{
338 iwlagn_rx_allocate(priv, GFP_ATOMIC);
339
340 iwlagn_rx_queue_restock(priv);
341}
342
343void iwl_bg_rx_replenish(struct work_struct *data)
344{
345 struct iwl_priv *priv =
346 container_of(data, struct iwl_priv, rx_replenish);
347
348 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
349 return;
350
351 mutex_lock(&priv->mutex);
352 iwlagn_rx_replenish(priv);
353 mutex_unlock(&priv->mutex);
354}
355
356/**
357 * iwl_rx_handle - Main entry function for receiving responses from uCode
358 *
359 * Uses the priv->rx_handlers callback function array to invoke
360 * the appropriate handlers, including command responses,
361 * frame-received notifications, and other notifications.
362 */
363static void iwl_rx_handle(struct iwl_priv *priv)
364{
365 struct iwl_rx_mem_buffer *rxb;
366 struct iwl_rx_packet *pkt;
367 struct iwl_rx_queue *rxq = &priv->rxq;
368 u32 r, i;
369 int reclaim;
370 unsigned long flags;
371 u8 fill_rx = 0;
372 u32 count = 8;
373 int total_empty;
374
375 /* uCode's read index (stored in shared DRAM) indicates the last Rx
376 * buffer that the driver may process (last buffer filled by ucode). */
377 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
378 i = rxq->read;
379
380 /* Rx interrupt, but nothing sent from uCode */
381 if (i == r)
382 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
383
384 /* calculate total frames need to be restock after handling RX */
385 total_empty = r - rxq->write_actual;
386 if (total_empty < 0)
387 total_empty += RX_QUEUE_SIZE;
388
389 if (total_empty > (RX_QUEUE_SIZE / 2))
390 fill_rx = 1;
391
392 while (i != r) {
393 int len;
394
395 rxb = rxq->queue[i];
396
397 /* If an RXB doesn't have a Rx queue slot associated with it,
398 * then a bug has been introduced in the queue refilling
399 * routines -- catch it here */
400 if (WARN_ON(rxb == NULL)) {
401 i = (i + 1) & RX_QUEUE_MASK;
402 continue;
403 }
404
405 rxq->queue[i] = NULL;
406
407 dma_unmap_page(priv->bus->dev, rxb->page_dma,
408 PAGE_SIZE << priv->hw_params.rx_page_order,
409 DMA_FROM_DEVICE);
410 pkt = rxb_addr(rxb);
411
412 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
413 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
414
415 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
416 len += sizeof(u32); /* account for status word */
417 trace_iwlwifi_dev_rx(priv, pkt, len);
418
419 /* Reclaim a command buffer only if this packet is a response
420 * to a (driver-originated) command.
421 * If the packet (e.g. Rx frame) originated from uCode,
422 * there is no command buffer to reclaim.
423 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
424 * but apparently a few don't get set; catch them here. */
425 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
426 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
427 (pkt->hdr.cmd != REPLY_RX) &&
428 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
429 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
430 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
431 (pkt->hdr.cmd != REPLY_TX);
432
433 iwl_rx_dispatch(priv, rxb);
434
435 /*
436 * XXX: After here, we should always check rxb->page
437 * against NULL before touching it or its virtual
438 * memory (pkt). Because some rx_handler might have
439 * already taken or freed the pages.
440 */
441
442 if (reclaim) {
443 /* Invoke any callbacks, transfer the buffer to caller,
444 * and fire off the (possibly) blocking
445 * trans_send_cmd()
446 * as we reclaim the driver command queue */
447 if (rxb->page)
448 iwl_tx_cmd_complete(priv, rxb);
449 else
450 IWL_WARN(priv, "Claim null rxb?\n");
451 }
452
453 /* Reuse the page if possible. For notification packets and
454 * SKBs that fail to Rx correctly, add them back into the
455 * rx_free list for reuse later. */
456 spin_lock_irqsave(&rxq->lock, flags);
457 if (rxb->page != NULL) {
458 rxb->page_dma = dma_map_page(priv->bus->dev, rxb->page,
459 0, PAGE_SIZE << priv->hw_params.rx_page_order,
460 DMA_FROM_DEVICE);
461 list_add_tail(&rxb->list, &rxq->rx_free);
462 rxq->free_count++;
463 } else
464 list_add_tail(&rxb->list, &rxq->rx_used);
465
466 spin_unlock_irqrestore(&rxq->lock, flags);
467
468 i = (i + 1) & RX_QUEUE_MASK;
469 /* If there are a lot of unused frames,
470 * restock the Rx queue so ucode wont assert. */
471 if (fill_rx) {
472 count++;
473 if (count >= 8) {
474 rxq->read = i;
475 iwlagn_rx_replenish_now(priv);
476 count = 0;
477 }
478 }
479 }
480
481 /* Backtrack one entry */
482 rxq->read = i;
483 if (fill_rx)
484 iwlagn_rx_replenish_now(priv);
485 else
486 iwlagn_rx_queue_restock(priv);
487}
488
489/* tasklet for iwlagn interrupt */
490void iwl_irq_tasklet(struct iwl_priv *priv)
491{
492 u32 inta = 0;
493 u32 handled = 0;
494 unsigned long flags;
495 u32 i;
496#ifdef CONFIG_IWLWIFI_DEBUG
497 u32 inta_mask;
498#endif
499
500 spin_lock_irqsave(&priv->lock, flags);
501
502 /* Ack/clear/reset pending uCode interrupts.
503 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
504 */
505 /* There is a hardware bug in the interrupt mask function that some
506 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
507 * they are disabled in the CSR_INT_MASK register. Furthermore the
508 * ICT interrupt handling mechanism has another bug that might cause
509 * these unmasked interrupts fail to be detected. We workaround the
510 * hardware bugs here by ACKing all the possible interrupts so that
511 * interrupt coalescing can still be achieved.
512 */
513 iwl_write32(priv, CSR_INT, priv->inta | ~priv->inta_mask);
514
515 inta = priv->inta;
516
517#ifdef CONFIG_IWLWIFI_DEBUG
518 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
519 /* just for debug */
520 inta_mask = iwl_read32(priv, CSR_INT_MASK);
521 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
522 inta, inta_mask);
523 }
524#endif
525
526 spin_unlock_irqrestore(&priv->lock, flags);
527
528 /* saved interrupt in inta variable now we can reset priv->inta */
529 priv->inta = 0;
530
531 /* Now service all interrupt bits discovered above. */
532 if (inta & CSR_INT_BIT_HW_ERR) {
533 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
534
535 /* Tell the device to stop sending interrupts */
536 iwl_disable_interrupts(priv);
537
538 priv->isr_stats.hw++;
539 iwl_irq_handle_error(priv);
540
541 handled |= CSR_INT_BIT_HW_ERR;
542
543 return;
544 }
545
546#ifdef CONFIG_IWLWIFI_DEBUG
547 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
548 /* NIC fires this, but we don't use it, redundant with WAKEUP */
549 if (inta & CSR_INT_BIT_SCD) {
550 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
551 "the frame/frames.\n");
552 priv->isr_stats.sch++;
553 }
554
555 /* Alive notification via Rx interrupt will do the real work */
556 if (inta & CSR_INT_BIT_ALIVE) {
557 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
558 priv->isr_stats.alive++;
559 }
560 }
561#endif
562 /* Safely ignore these bits for debug checks below */
563 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
564
565 /* HW RF KILL switch toggled */
566 if (inta & CSR_INT_BIT_RF_KILL) {
567 int hw_rf_kill = 0;
568 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
569 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
570 hw_rf_kill = 1;
571
572 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
573 hw_rf_kill ? "disable radio" : "enable radio");
574
575 priv->isr_stats.rfkill++;
576
577 /* driver only loads ucode once setting the interface up.
578 * the driver allows loading the ucode even if the radio
579 * is killed. Hence update the killswitch state here. The
580 * rfkill handler will care about restarting if needed.
581 */
582 if (!test_bit(STATUS_ALIVE, &priv->status)) {
583 if (hw_rf_kill)
584 set_bit(STATUS_RF_KILL_HW, &priv->status);
585 else
586 clear_bit(STATUS_RF_KILL_HW, &priv->status);
587 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
588 }
589
590 handled |= CSR_INT_BIT_RF_KILL;
591 }
592
593 /* Chip got too hot and stopped itself */
594 if (inta & CSR_INT_BIT_CT_KILL) {
595 IWL_ERR(priv, "Microcode CT kill error detected.\n");
596 priv->isr_stats.ctkill++;
597 handled |= CSR_INT_BIT_CT_KILL;
598 }
599
600 /* Error detected by uCode */
601 if (inta & CSR_INT_BIT_SW_ERR) {
602 IWL_ERR(priv, "Microcode SW error detected. "
603 " Restarting 0x%X.\n", inta);
604 priv->isr_stats.sw++;
605 iwl_irq_handle_error(priv);
606 handled |= CSR_INT_BIT_SW_ERR;
607 }
608
609 /* uCode wakes up after power-down sleep */
610 if (inta & CSR_INT_BIT_WAKEUP) {
611 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
612 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
613 for (i = 0; i < priv->hw_params.max_txq_num; i++)
614 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
615
616 priv->isr_stats.wakeup++;
617
618 handled |= CSR_INT_BIT_WAKEUP;
619 }
620
621 /* All uCode command responses, including Tx command responses,
622 * Rx "responses" (frame-received notification), and other
623 * notifications from uCode come through here*/
624 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
625 CSR_INT_BIT_RX_PERIODIC)) {
626 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
627 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
628 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
629 iwl_write32(priv, CSR_FH_INT_STATUS,
630 CSR_FH_INT_RX_MASK);
631 }
632 if (inta & CSR_INT_BIT_RX_PERIODIC) {
633 handled |= CSR_INT_BIT_RX_PERIODIC;
634 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
635 }
636 /* Sending RX interrupt require many steps to be done in the
637 * the device:
638 * 1- write interrupt to current index in ICT table.
639 * 2- dma RX frame.
640 * 3- update RX shared data to indicate last write index.
641 * 4- send interrupt.
642 * This could lead to RX race, driver could receive RX interrupt
643 * but the shared data changes does not reflect this;
644 * periodic interrupt will detect any dangling Rx activity.
645 */
646
647 /* Disable periodic interrupt; we use it as just a one-shot. */
648 iwl_write8(priv, CSR_INT_PERIODIC_REG,
649 CSR_INT_PERIODIC_DIS);
650 iwl_rx_handle(priv);
651
652 /*
653 * Enable periodic interrupt in 8 msec only if we received
654 * real RX interrupt (instead of just periodic int), to catch
655 * any dangling Rx interrupt. If it was just the periodic
656 * interrupt, there was no dangling Rx activity, and no need
657 * to extend the periodic interrupt; one-shot is enough.
658 */
659 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
660 iwl_write8(priv, CSR_INT_PERIODIC_REG,
661 CSR_INT_PERIODIC_ENA);
662
663 priv->isr_stats.rx++;
664 }
665
666 /* This "Tx" DMA channel is used only for loading uCode */
667 if (inta & CSR_INT_BIT_FH_TX) {
668 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
669 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
670 priv->isr_stats.tx++;
671 handled |= CSR_INT_BIT_FH_TX;
672 /* Wake up uCode load routine, now that load is complete */
673 priv->ucode_write_complete = 1;
674 wake_up_interruptible(&priv->wait_command_queue);
675 }
676
677 if (inta & ~handled) {
678 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
679 priv->isr_stats.unhandled++;
680 }
681
682 if (inta & ~(priv->inta_mask)) {
683 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
684 inta & ~priv->inta_mask);
685 }
686
687 /* Re-enable all interrupts */
688 /* only Re-enable if disabled by irq */
689 if (test_bit(STATUS_INT_ENABLED, &priv->status))
690 iwl_enable_interrupts(priv);
691 /* Re-enable RF_KILL if it occurred */
692 else if (handled & CSR_INT_BIT_RF_KILL)
693 iwl_enable_rfkill_int(priv);
694}
695
696/******************************************************************************
697 *
698 * ICT functions
699 *
700 ******************************************************************************/
701#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
702
703/* Free dram table */
704void iwl_free_isr_ict(struct iwl_priv *priv)
705{
706 if (priv->ict_tbl_vir) {
707 dma_free_coherent(priv->bus->dev,
708 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
709 priv->ict_tbl_vir,
710 priv->ict_tbl_dma);
711 priv->ict_tbl_vir = NULL;
712 memset(&priv->ict_tbl_dma, 0,
713 sizeof(priv->ict_tbl_dma));
714 memset(&priv->aligned_ict_tbl_dma, 0,
715 sizeof(priv->aligned_ict_tbl_dma));
716 }
717}
718
719
720/* allocate dram shared table it is a PAGE_SIZE aligned
721 * also reset all data related to ICT table interrupt.
722 */
723int iwl_alloc_isr_ict(struct iwl_priv *priv)
724{
725
726 /* allocate shrared data table */
727 priv->ict_tbl_vir =
728 dma_alloc_coherent(priv->bus->dev,
729 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
730 &priv->ict_tbl_dma, GFP_KERNEL);
731 if (!priv->ict_tbl_vir)
732 return -ENOMEM;
733
734 /* align table to PAGE_SIZE boundary */
735 priv->aligned_ict_tbl_dma =
736 ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
737
738 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
739 (unsigned long long)priv->ict_tbl_dma,
740 (unsigned long long)priv->aligned_ict_tbl_dma,
741 (int)(priv->aligned_ict_tbl_dma -
742 priv->ict_tbl_dma));
743
744 priv->ict_tbl = priv->ict_tbl_vir +
745 (priv->aligned_ict_tbl_dma -
746 priv->ict_tbl_dma);
747
748 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
749 priv->ict_tbl, priv->ict_tbl_vir,
750 (int)(priv->aligned_ict_tbl_dma -
751 priv->ict_tbl_dma));
752
753 /* reset table and index to all 0 */
754 memset(priv->ict_tbl_vir, 0,
755 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
756 priv->ict_index = 0;
757
758 /* add periodic RX interrupt */
759 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
760 return 0;
761}
762
763/* Device is going up inform it about using ICT interrupt table,
764 * also we need to tell the driver to start using ICT interrupt.
765 */
766int iwl_reset_ict(struct iwl_priv *priv)
767{
768 u32 val;
769 unsigned long flags;
770
771 if (!priv->ict_tbl_vir)
772 return 0;
773
774 spin_lock_irqsave(&priv->lock, flags);
775 iwl_disable_interrupts(priv);
776
777 memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
778
779 val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
780
781 val |= CSR_DRAM_INT_TBL_ENABLE;
782 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
783
784 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
785 "aligned dma address %Lx\n",
786 val,
787 (unsigned long long)priv->aligned_ict_tbl_dma);
788
789 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
790 priv->use_ict = true;
791 priv->ict_index = 0;
792 iwl_write32(priv, CSR_INT, priv->inta_mask);
793 iwl_enable_interrupts(priv);
794 spin_unlock_irqrestore(&priv->lock, flags);
795
796 return 0;
797}
798
799/* Device is going down disable ict interrupt usage */
800void iwl_disable_ict(struct iwl_priv *priv)
801{
802 unsigned long flags;
803
804 spin_lock_irqsave(&priv->lock, flags);
805 priv->use_ict = false;
806 spin_unlock_irqrestore(&priv->lock, flags);
807}
808
809static irqreturn_t iwl_isr(int irq, void *data)
810{
811 struct iwl_priv *priv = data;
812 u32 inta, inta_mask;
813 unsigned long flags;
814#ifdef CONFIG_IWLWIFI_DEBUG
815 u32 inta_fh;
816#endif
817 if (!priv)
818 return IRQ_NONE;
819
820 spin_lock_irqsave(&priv->lock, flags);
821
822 /* Disable (but don't clear!) interrupts here to avoid
823 * back-to-back ISRs and sporadic interrupts from our NIC.
824 * If we have something to service, the tasklet will re-enable ints.
825 * If we *don't* have something, we'll re-enable before leaving here. */
826 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
827 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
828
829 /* Discover which interrupts are active/pending */
830 inta = iwl_read32(priv, CSR_INT);
831
832 /* Ignore interrupt if there's nothing in NIC to service.
833 * This may be due to IRQ shared with another device,
834 * or due to sporadic interrupts thrown from our NIC. */
835 if (!inta) {
836 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
837 goto none;
838 }
839
840 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
841 /* Hardware disappeared. It might have already raised
842 * an interrupt */
843 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
844 goto unplugged;
845 }
846
847#ifdef CONFIG_IWLWIFI_DEBUG
848 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
849 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
850 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
851 "fh 0x%08x\n", inta, inta_mask, inta_fh);
852 }
853#endif
854
855 priv->inta |= inta;
856 /* iwl_irq_tasklet() will service interrupts and re-enable them */
857 if (likely(inta))
858 tasklet_schedule(&priv->irq_tasklet);
859 else if (test_bit(STATUS_INT_ENABLED, &priv->status) &&
860 !priv->inta)
861 iwl_enable_interrupts(priv);
862
863 unplugged:
864 spin_unlock_irqrestore(&priv->lock, flags);
865 return IRQ_HANDLED;
866
867 none:
868 /* re-enable interrupts here since we don't have anything to service. */
869 /* only Re-enable if disabled by irq and no schedules tasklet. */
870 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
871 iwl_enable_interrupts(priv);
872
873 spin_unlock_irqrestore(&priv->lock, flags);
874 return IRQ_NONE;
875}
876
877/* interrupt handler using ict table, with this interrupt driver will
878 * stop using INTA register to get device's interrupt, reading this register
879 * is expensive, device will write interrupts in ICT dram table, increment
880 * index then will fire interrupt to driver, driver will OR all ICT table
881 * entries from current index up to table entry with 0 value. the result is
882 * the interrupt we need to service, driver will set the entries back to 0 and
883 * set index.
884 */
885irqreturn_t iwl_isr_ict(int irq, void *data)
886{
887 struct iwl_priv *priv = data;
888 u32 inta, inta_mask;
889 u32 val = 0;
890 unsigned long flags;
891
892 if (!priv)
893 return IRQ_NONE;
894
895 /* dram interrupt table not set yet,
896 * use legacy interrupt.
897 */
898 if (!priv->use_ict)
899 return iwl_isr(irq, data);
900
901 spin_lock_irqsave(&priv->lock, flags);
902
903 /* Disable (but don't clear!) interrupts here to avoid
904 * back-to-back ISRs and sporadic interrupts from our NIC.
905 * If we have something to service, the tasklet will re-enable ints.
906 * If we *don't* have something, we'll re-enable before leaving here.
907 */
908 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
909 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
910
911
912 /* Ignore interrupt if there's nothing in NIC to service.
913 * This may be due to IRQ shared with another device,
914 * or due to sporadic interrupts thrown from our NIC. */
915 if (!priv->ict_tbl[priv->ict_index]) {
916 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
917 goto none;
918 }
919
920 /* read all entries that not 0 start with ict_index */
921 while (priv->ict_tbl[priv->ict_index]) {
922
923 val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
924 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
925 priv->ict_index,
926 le32_to_cpu(
927 priv->ict_tbl[priv->ict_index]));
928 priv->ict_tbl[priv->ict_index] = 0;
929 priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
930 ICT_COUNT);
931
932 }
933
934 /* We should not get this value, just ignore it. */
935 if (val == 0xffffffff)
936 val = 0;
937
938 /*
939 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
940 * (bit 15 before shifting it to 31) to clear when using interrupt
941 * coalescing. fortunately, bits 18 and 19 stay set when this happens
942 * so we use them to decide on the real state of the Rx bit.
943 * In order words, bit 15 is set if bit 18 or bit 19 are set.
944 */
945 if (val & 0xC0000)
946 val |= 0x8000;
947
948 inta = (0xff & val) | ((0xff00 & val) << 16);
949 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
950 inta, inta_mask, val);
951
952 inta &= priv->inta_mask;
953 priv->inta |= inta;
954
955 /* iwl_irq_tasklet() will service interrupts and re-enable them */
956 if (likely(inta))
957 tasklet_schedule(&priv->irq_tasklet);
958 else if (test_bit(STATUS_INT_ENABLED, &priv->status) &&
959 !priv->inta) {
960 /* Allow interrupt if was disabled by this handler and
961 * no tasklet was schedules, We should not enable interrupt,
962 * tasklet will enable it.
963 */
964 iwl_enable_interrupts(priv);
965 }
966
967 spin_unlock_irqrestore(&priv->lock, flags);
968 return IRQ_HANDLED;
969
970 none:
971 /* re-enable interrupts here since we don't have anything to service.
972 * only Re-enable if disabled by irq.
973 */
974 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
975 iwl_enable_interrupts(priv);
976
977 spin_unlock_irqrestore(&priv->lock, flags);
978 return IRQ_NONE;
979}
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
index 137dba95b1ad..a6b2b1db0b1d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c
@@ -26,18 +26,58 @@
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29
30#include <linux/etherdevice.h> 29#include <linux/etherdevice.h>
31#include <linux/sched.h>
32#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/sched.h>
33#include <net/mac80211.h> 32#include <net/mac80211.h>
34#include "iwl-eeprom.h" 33
35#include "iwl-agn.h" 34#include "iwl-agn.h"
36#include "iwl-dev.h" 35#include "iwl-dev.h"
37#include "iwl-core.h" 36#include "iwl-core.h"
38#include "iwl-sta.h"
39#include "iwl-io.h" 37#include "iwl-io.h"
40#include "iwl-helpers.h" 38#include "iwl-helpers.h"
39#include "iwl-trans-int-pcie.h"
40
41/**
42 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
43 */
44void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
45 struct iwl_tx_queue *txq,
46 u16 byte_cnt)
47{
48 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
49 int write_ptr = txq->q.write_ptr;
50 int txq_id = txq->q.id;
51 u8 sec_ctl = 0;
52 u8 sta_id = 0;
53 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
54 __le16 bc_ent;
55
56 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
57
58 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
59 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
60
61 switch (sec_ctl & TX_CMD_SEC_MSK) {
62 case TX_CMD_SEC_CCM:
63 len += CCMP_MIC_LEN;
64 break;
65 case TX_CMD_SEC_TKIP:
66 len += TKIP_ICV_LEN;
67 break;
68 case TX_CMD_SEC_WEP:
69 len += WEP_IV_LEN + WEP_ICV_LEN;
70 break;
71 }
72
73 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
74
75 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
76
77 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
78 scd_bc_tbl[txq_id].
79 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
80}
41 81
42/** 82/**
43 * iwl_txq_update_write_ptr - Send new write index to hardware 83 * iwl_txq_update_write_ptr - Send new write index to hardware
@@ -126,9 +166,8 @@ static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
126} 166}
127 167
128static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta, 168static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
129 struct iwl_tfd *tfd, int dma_dir) 169 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
130{ 170{
131 struct pci_dev *dev = priv->pci_dev;
132 int i; 171 int i;
133 int num_tbs; 172 int num_tbs;
134 173
@@ -143,14 +182,14 @@ static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
143 182
144 /* Unmap tx_cmd */ 183 /* Unmap tx_cmd */
145 if (num_tbs) 184 if (num_tbs)
146 pci_unmap_single(dev, 185 dma_unmap_single(priv->bus->dev,
147 dma_unmap_addr(meta, mapping), 186 dma_unmap_addr(meta, mapping),
148 dma_unmap_len(meta, len), 187 dma_unmap_len(meta, len),
149 PCI_DMA_BIDIRECTIONAL); 188 DMA_BIDIRECTIONAL);
150 189
151 /* Unmap chunks, if any. */ 190 /* Unmap chunks, if any. */
152 for (i = 1; i < num_tbs; i++) 191 for (i = 1; i < num_tbs; i++)
153 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), 192 dma_unmap_single(priv->bus->dev, iwl_tfd_tb_get_addr(tfd, i),
154 iwl_tfd_tb_get_len(tfd, i), dma_dir); 193 iwl_tfd_tb_get_len(tfd, i), dma_dir);
155} 194}
156 195
@@ -158,28 +197,29 @@ static void iwlagn_unmap_tfd(struct iwl_priv *priv, struct iwl_cmd_meta *meta,
158 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 197 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
159 * @priv - driver private data 198 * @priv - driver private data
160 * @txq - tx queue 199 * @txq - tx queue
200 * @index - the index of the TFD to be freed
161 * 201 *
162 * Does NOT advance any TFD circular buffer read/write indexes 202 * Does NOT advance any TFD circular buffer read/write indexes
163 * Does NOT free the TFD itself (which is within circular buffer) 203 * Does NOT free the TFD itself (which is within circular buffer)
164 */ 204 */
165void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) 205void iwlagn_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq,
206 int index)
166{ 207{
167 struct iwl_tfd *tfd_tmp = txq->tfds; 208 struct iwl_tfd *tfd_tmp = txq->tfds;
168 int index = txq->q.read_ptr;
169 209
170 iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index], 210 iwlagn_unmap_tfd(priv, &txq->meta[index], &tfd_tmp[index],
171 PCI_DMA_TODEVICE); 211 DMA_TO_DEVICE);
172 212
173 /* free SKB */ 213 /* free SKB */
174 if (txq->txb) { 214 if (txq->txb) {
175 struct sk_buff *skb; 215 struct sk_buff *skb;
176 216
177 skb = txq->txb[txq->q.read_ptr].skb; 217 skb = txq->txb[index].skb;
178 218
179 /* can be called from irqs-disabled context */ 219 /* can be called from irqs-disabled context */
180 if (skb) { 220 if (skb) {
181 dev_kfree_skb_any(skb); 221 dev_kfree_skb_any(skb);
182 txq->txb[txq->q.read_ptr].skb = NULL; 222 txq->txb[index].skb = NULL;
183 } 223 }
184 } 224 }
185} 225}
@@ -221,140 +261,6 @@ int iwlagn_txq_attach_buf_to_tfd(struct iwl_priv *priv,
221 return 0; 261 return 0;
222} 262}
223 263
224/*
225 * Tell nic where to find circular buffer of Tx Frame Descriptors for
226 * given Tx queue, and enable the DMA channel used for that queue.
227 *
228 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
229 * channels supported in hardware.
230 */
231static int iwlagn_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
232{
233 int txq_id = txq->q.id;
234
235 /* Circular buffer (TFD queue in DRAM) physical base address */
236 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
237 txq->q.dma_addr >> 8);
238
239 return 0;
240}
241
242/**
243 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
244 */
245void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
246{
247 struct iwl_tx_queue *txq = &priv->txq[txq_id];
248 struct iwl_queue *q = &txq->q;
249
250 if (q->n_bd == 0)
251 return;
252
253 while (q->write_ptr != q->read_ptr) {
254 iwlagn_txq_free_tfd(priv, txq);
255 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
256 }
257}
258
259/**
260 * iwl_tx_queue_free - Deallocate DMA queue.
261 * @txq: Transmit queue to deallocate.
262 *
263 * Empty queue by removing and destroying all BD's.
264 * Free all buffers.
265 * 0-fill, but do not free "txq" descriptor structure.
266 */
267void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
268{
269 struct iwl_tx_queue *txq = &priv->txq[txq_id];
270 struct device *dev = &priv->pci_dev->dev;
271 int i;
272
273 iwl_tx_queue_unmap(priv, txq_id);
274
275 /* De-alloc array of command/tx buffers */
276 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
277 kfree(txq->cmd[i]);
278
279 /* De-alloc circular buffer of TFDs */
280 if (txq->q.n_bd)
281 dma_free_coherent(dev, priv->hw_params.tfd_size *
282 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
283
284 /* De-alloc array of per-TFD driver data */
285 kfree(txq->txb);
286 txq->txb = NULL;
287
288 /* deallocate arrays */
289 kfree(txq->cmd);
290 kfree(txq->meta);
291 txq->cmd = NULL;
292 txq->meta = NULL;
293
294 /* 0-fill queue descriptor structure */
295 memset(txq, 0, sizeof(*txq));
296}
297
298/**
299 * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
300 */
301void iwl_cmd_queue_unmap(struct iwl_priv *priv)
302{
303 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
304 struct iwl_queue *q = &txq->q;
305 int i;
306
307 if (q->n_bd == 0)
308 return;
309
310 while (q->read_ptr != q->write_ptr) {
311 i = get_cmd_index(q, q->read_ptr);
312
313 if (txq->meta[i].flags & CMD_MAPPED) {
314 iwlagn_unmap_tfd(priv, &txq->meta[i], &txq->tfds[i],
315 PCI_DMA_BIDIRECTIONAL);
316 txq->meta[i].flags = 0;
317 }
318
319 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
320 }
321}
322
323/**
324 * iwl_cmd_queue_free - Deallocate DMA queue.
325 * @txq: Transmit queue to deallocate.
326 *
327 * Empty queue by removing and destroying all BD's.
328 * Free all buffers.
329 * 0-fill, but do not free "txq" descriptor structure.
330 */
331void iwl_cmd_queue_free(struct iwl_priv *priv)
332{
333 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
334 struct device *dev = &priv->pci_dev->dev;
335 int i;
336
337 iwl_cmd_queue_unmap(priv);
338
339 /* De-alloc array of command/tx buffers */
340 for (i = 0; i < TFD_CMD_SLOTS; i++)
341 kfree(txq->cmd[i]);
342
343 /* De-alloc circular buffer of TFDs */
344 if (txq->q.n_bd)
345 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
346 txq->tfds, txq->q.dma_addr);
347
348 /* deallocate arrays */
349 kfree(txq->cmd);
350 kfree(txq->meta);
351 txq->cmd = NULL;
352 txq->meta = NULL;
353
354 /* 0-fill queue descriptor structure */
355 memset(txq, 0, sizeof(*txq));
356}
357
358/*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 264/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
359 * DMA services 265 * DMA services
360 * 266 *
@@ -393,11 +299,10 @@ int iwl_queue_space(const struct iwl_queue *q)
393 return s; 299 return s;
394} 300}
395 301
396
397/** 302/**
398 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 303 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
399 */ 304 */
400static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q, 305int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
401 int count, int slots_num, u32 id) 306 int count, int slots_num, u32 id)
402{ 307{
403 q->n_bd = count; 308 q->n_bd = count;
@@ -427,122 +332,185 @@ static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
427 return 0; 332 return 0;
428} 333}
429 334
430/** 335/*TODO: this functions should NOT be exported from trans module - export it
431 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue 336 * until the reclaim flow will be brought to the transport module too.
432 */ 337 * Add a declaration to make sparse happy */
433static int iwl_tx_queue_alloc(struct iwl_priv *priv, 338void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
434 struct iwl_tx_queue *txq, u32 id) 339 struct iwl_tx_queue *txq);
340
341void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
342 struct iwl_tx_queue *txq)
435{ 343{
436 struct device *dev = &priv->pci_dev->dev; 344 struct iwlagn_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
437 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; 345 int txq_id = txq->q.id;
438 346 int read_ptr = txq->q.read_ptr;
439 /* Driver private data, only for Tx (not command) queues, 347 u8 sta_id = 0;
440 * not shared with device. */ 348 __le16 bc_ent;
441 if (id != priv->cmd_queue) {
442 txq->txb = kzalloc(sizeof(txq->txb[0]) *
443 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
444 if (!txq->txb) {
445 IWL_ERR(priv, "kmalloc for auxiliary BD "
446 "structures failed\n");
447 goto error;
448 }
449 } else {
450 txq->txb = NULL;
451 }
452 349
453 /* Circular buffer of transmit frame descriptors (TFDs), 350 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
454 * shared with device */ 351
455 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, 352 if (txq_id != priv->cmd_queue)
456 GFP_KERNEL); 353 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
457 if (!txq->tfds) { 354
458 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz); 355 bc_ent = cpu_to_le16(1 | (sta_id << 12));
459 goto error; 356 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
460 } 357
461 txq->q.id = id; 358 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
359 scd_bc_tbl[txq_id].
360 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
361}
362
363static int iwlagn_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
364 u16 txq_id)
365{
366 u32 tbl_dw_addr;
367 u32 tbl_dw;
368 u16 scd_q2ratid;
369
370 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
371
372 tbl_dw_addr = priv->scd_base_addr +
373 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
374
375 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
376
377 if (txq_id & 0x1)
378 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
379 else
380 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
381
382 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
462 383
463 return 0; 384 return 0;
385}
386
387static void iwlagn_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
388{
389 /* Simply stop the queue, but don't change any configuration;
390 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
391 iwl_write_prph(priv,
392 SCD_QUEUE_STATUS_BITS(txq_id),
393 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
394 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
395}
396
397void iwl_trans_set_wr_ptrs(struct iwl_priv *priv,
398 int txq_id, u32 index)
399{
400 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
401 (index & 0xff) | (txq_id << 8));
402 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
403}
404
405void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
406 struct iwl_tx_queue *txq,
407 int tx_fifo_id, int scd_retry)
408{
409 int txq_id = txq->q.id;
410 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
464 411
465 error: 412 iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id),
466 kfree(txq->txb); 413 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
467 txq->txb = NULL; 414 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
415 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
416 SCD_QUEUE_STTS_REG_MSK);
468 417
469 return -ENOMEM; 418 txq->sched_retry = scd_retry;
419
420 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
421 active ? "Activate" : "Deactivate",
422 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
470} 423}
471 424
472/** 425void iwl_trans_txq_agg_setup(struct iwl_priv *priv, int sta_id, int tid,
473 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue 426 int frame_limit)
474 */
475int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
476 int slots_num, u32 txq_id)
477{ 427{
478 int i, len; 428 int tx_fifo, txq_id, ssn_idx;
479 int ret; 429 u16 ra_tid;
430 unsigned long flags;
431 struct iwl_tid_data *tid_data;
480 432
481 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * slots_num, 433 if (WARN_ON(sta_id == IWL_INVALID_STATION))
482 GFP_KERNEL); 434 return;
483 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * slots_num, 435 if (WARN_ON(tid >= MAX_TID_COUNT))
484 GFP_KERNEL); 436 return;
485 437
486 if (!txq->meta || !txq->cmd) 438 spin_lock_irqsave(&priv->sta_lock, flags);
487 goto out_free_arrays; 439 tid_data = &priv->stations[sta_id].tid[tid];
440 ssn_idx = SEQ_TO_SN(tid_data->seq_number);
441 txq_id = tid_data->agg.txq_id;
442 tx_fifo = tid_data->agg.tx_fifo;
443 spin_unlock_irqrestore(&priv->sta_lock, flags);
488 444
489 len = sizeof(struct iwl_device_cmd); 445 ra_tid = BUILD_RAxTID(sta_id, tid);
490 for (i = 0; i < slots_num; i++) {
491 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
492 if (!txq->cmd[i])
493 goto err;
494 }
495 446
496 /* Alloc driver data array and TFD circular buffer */ 447 spin_lock_irqsave(&priv->lock, flags);
497 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
498 if (ret)
499 goto err;
500 448
501 txq->need_update = 0; 449 /* Stop this Tx queue before configuring it */
450 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
502 451
503 /* 452 /* Map receiver-address / traffic-ID to this queue */
504 * For the default queues 0-3, set up the swq_id 453 iwlagn_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
505 * already -- all others need to get one later
506 * (if they need one at all).
507 */
508 if (txq_id < 4)
509 iwl_set_swq_id(txq, txq_id, txq_id);
510 454
511 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise 455 /* Set this queue as a chain-building queue */
512 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 456 iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
513 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
514 457
515 /* Initialize queue's high/low-water marks, and head/tail indexes */ 458 /* enable aggregations for the queue */
516 ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); 459 iwl_set_bits_prph(priv, SCD_AGGR_SEL, (1<<txq_id));
517 if (ret)
518 return ret;
519 460
520 /* Tell device where to find queue */ 461 /* Place first TFD at index corresponding to start sequence number.
521 iwlagn_tx_queue_init(priv, txq); 462 * Assumes that ssn_idx is valid (!= 0xFFF) */
463 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
464 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
465 iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx);
522 466
523 return 0; 467 /* Set up Tx window size and frame limit for this queue */
524err: 468 iwl_write_targ_mem(priv, priv->scd_base_addr +
525 for (i = 0; i < slots_num; i++) 469 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
526 kfree(txq->cmd[i]); 470 sizeof(u32),
527out_free_arrays: 471 ((frame_limit <<
528 kfree(txq->meta); 472 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
529 kfree(txq->cmd); 473 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
530 474 ((frame_limit <<
531 return -ENOMEM; 475 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
476 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
477
478 iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
479
480 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
481 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
482
483 spin_unlock_irqrestore(&priv->lock, flags);
532} 484}
533 485
534void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq, 486int iwl_trans_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
535 int slots_num, u32 txq_id) 487 u16 ssn_idx, u8 tx_fifo)
536{ 488{
537 memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * slots_num); 489 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
490 (IWLAGN_FIRST_AMPDU_QUEUE +
491 priv->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
492 IWL_ERR(priv,
493 "queue number out of range: %d, must be %d to %d\n",
494 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
495 IWLAGN_FIRST_AMPDU_QUEUE +
496 priv->cfg->base_params->num_of_ampdu_queues - 1);
497 return -EINVAL;
498 }
538 499
539 txq->need_update = 0; 500 iwlagn_tx_queue_stop_scheduler(priv, txq_id);
501
502 iwl_clear_bits_prph(priv, SCD_AGGR_SEL, (1 << txq_id));
540 503
541 /* Initialize queue's high/low-water marks, and head/tail indexes */ 504 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
542 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); 505 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
506 /* supposes that ssn_idx is valid (!= 0xFFF) */
507 iwl_trans_set_wr_ptrs(priv, txq_id, ssn_idx);
543 508
544 /* Tell device where to find queue */ 509 iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
545 iwlagn_tx_queue_init(priv, txq); 510 iwl_txq_ctx_deactivate(priv, txq_id);
511 iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
512
513 return 0;
546} 514}
547 515
548/*************** HOST COMMAND QUEUE FUNCTIONS *****/ 516/*************** HOST COMMAND QUEUE FUNCTIONS *****/
@@ -556,7 +524,7 @@ void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
556 * failed. On success, it turns the index (> 0) of command in the 524 * failed. On success, it turns the index (> 0) of command in the
557 * command queue. 525 * command queue.
558 */ 526 */
559int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) 527static int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
560{ 528{
561 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue]; 529 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
562 struct iwl_queue *q = &txq->q; 530 struct iwl_queue *q = &txq->q;
@@ -581,6 +549,12 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
581 return -EIO; 549 return -EIO;
582 } 550 }
583 551
552 if ((priv->ucode_owner == IWL_OWNERSHIP_TM) &&
553 !(cmd->flags & CMD_ON_DEMAND)) {
554 IWL_DEBUG_HC(priv, "tm own the uCode, no regular hcmd send\n");
555 return -EIO;
556 }
557
584 copy_size = sizeof(out_cmd->hdr); 558 copy_size = sizeof(out_cmd->hdr);
585 cmd_size = sizeof(out_cmd->hdr); 559 cmd_size = sizeof(out_cmd->hdr);
586 560
@@ -634,11 +608,6 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
634 out_cmd = txq->cmd[idx]; 608 out_cmd = txq->cmd[idx];
635 out_meta = &txq->meta[idx]; 609 out_meta = &txq->meta[idx];
636 610
637 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
638 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
639 return -ENOSPC;
640 }
641
642 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 611 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
643 if (cmd->flags & CMD_WANT_SKB) 612 if (cmd->flags & CMD_WANT_SKB)
644 out_meta->source = cmd; 613 out_meta->source = cmd;
@@ -671,9 +640,9 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
671 le16_to_cpu(out_cmd->hdr.sequence), cmd_size, 640 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
672 q->write_ptr, idx, priv->cmd_queue); 641 q->write_ptr, idx, priv->cmd_queue);
673 642
674 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr, 643 phys_addr = dma_map_single(priv->bus->dev, &out_cmd->hdr, copy_size,
675 copy_size, PCI_DMA_BIDIRECTIONAL); 644 DMA_BIDIRECTIONAL);
676 if (unlikely(pci_dma_mapping_error(priv->pci_dev, phys_addr))) { 645 if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
677 idx = -ENOMEM; 646 idx = -ENOMEM;
678 goto out; 647 goto out;
679 } 648 }
@@ -693,12 +662,12 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
693 continue; 662 continue;
694 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)) 663 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
695 continue; 664 continue;
696 phys_addr = pci_map_single(priv->pci_dev, (void *)cmd->data[i], 665 phys_addr = dma_map_single(priv->bus->dev, (void *)cmd->data[i],
697 cmd->len[i], PCI_DMA_BIDIRECTIONAL); 666 cmd->len[i], DMA_BIDIRECTIONAL);
698 if (pci_dma_mapping_error(priv->pci_dev, phys_addr)) { 667 if (dma_mapping_error(priv->bus->dev, phys_addr)) {
699 iwlagn_unmap_tfd(priv, out_meta, 668 iwlagn_unmap_tfd(priv, out_meta,
700 &txq->tfds[q->write_ptr], 669 &txq->tfds[q->write_ptr],
701 PCI_DMA_BIDIRECTIONAL); 670 DMA_BIDIRECTIONAL);
702 idx = -ENOMEM; 671 idx = -ENOMEM;
703 goto out; 672 goto out;
704 } 673 }
@@ -712,7 +681,7 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
712#endif 681#endif
713 } 682 }
714 683
715 out_meta->flags = cmd->flags | CMD_MAPPED; 684 out_meta->flags = cmd->flags;
716 685
717 txq->need_update = 1; 686 txq->need_update = 1;
718 687
@@ -748,9 +717,9 @@ static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
748 int nfreed = 0; 717 int nfreed = 0;
749 718
750 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) { 719 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
751 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, " 720 IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), "
752 "is out of range [0-%d] %d %d.\n", txq_id, 721 "index %d is out of range [0-%d] %d %d.\n", __func__,
753 idx, q->n_bd, q->write_ptr, q->read_ptr); 722 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
754 return; 723 return;
755 } 724 }
756 725
@@ -802,7 +771,7 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
802 cmd = txq->cmd[cmd_index]; 771 cmd = txq->cmd[cmd_index];
803 meta = &txq->meta[cmd_index]; 772 meta = &txq->meta[cmd_index];
804 773
805 iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], PCI_DMA_BIDIRECTIONAL); 774 iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL);
806 775
807 /* Input error checking is done when commands are added to queue. */ 776 /* Input error checking is done when commands are added to queue. */
808 if (meta->flags & CMD_WANT_SKB) { 777 if (meta->flags & CMD_WANT_SKB) {
@@ -822,8 +791,246 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
822 wake_up_interruptible(&priv->wait_command_queue); 791 wake_up_interruptible(&priv->wait_command_queue);
823 } 792 }
824 793
825 /* Mark as unmapped */
826 meta->flags = 0; 794 meta->flags = 0;
827 795
828 spin_unlock_irqrestore(&priv->hcmd_lock, flags); 796 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
829} 797}
798
799const char *get_cmd_string(u8 cmd)
800{
801 switch (cmd) {
802 IWL_CMD(REPLY_ALIVE);
803 IWL_CMD(REPLY_ERROR);
804 IWL_CMD(REPLY_RXON);
805 IWL_CMD(REPLY_RXON_ASSOC);
806 IWL_CMD(REPLY_QOS_PARAM);
807 IWL_CMD(REPLY_RXON_TIMING);
808 IWL_CMD(REPLY_ADD_STA);
809 IWL_CMD(REPLY_REMOVE_STA);
810 IWL_CMD(REPLY_REMOVE_ALL_STA);
811 IWL_CMD(REPLY_TXFIFO_FLUSH);
812 IWL_CMD(REPLY_WEPKEY);
813 IWL_CMD(REPLY_TX);
814 IWL_CMD(REPLY_LEDS_CMD);
815 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
816 IWL_CMD(COEX_PRIORITY_TABLE_CMD);
817 IWL_CMD(COEX_MEDIUM_NOTIFICATION);
818 IWL_CMD(COEX_EVENT_CMD);
819 IWL_CMD(REPLY_QUIET_CMD);
820 IWL_CMD(REPLY_CHANNEL_SWITCH);
821 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
822 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
823 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
824 IWL_CMD(POWER_TABLE_CMD);
825 IWL_CMD(PM_SLEEP_NOTIFICATION);
826 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
827 IWL_CMD(REPLY_SCAN_CMD);
828 IWL_CMD(REPLY_SCAN_ABORT_CMD);
829 IWL_CMD(SCAN_START_NOTIFICATION);
830 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
831 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
832 IWL_CMD(BEACON_NOTIFICATION);
833 IWL_CMD(REPLY_TX_BEACON);
834 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
835 IWL_CMD(QUIET_NOTIFICATION);
836 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
837 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
838 IWL_CMD(REPLY_BT_CONFIG);
839 IWL_CMD(REPLY_STATISTICS_CMD);
840 IWL_CMD(STATISTICS_NOTIFICATION);
841 IWL_CMD(REPLY_CARD_STATE_CMD);
842 IWL_CMD(CARD_STATE_NOTIFICATION);
843 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
844 IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
845 IWL_CMD(SENSITIVITY_CMD);
846 IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
847 IWL_CMD(REPLY_RX_PHY_CMD);
848 IWL_CMD(REPLY_RX_MPDU_CMD);
849 IWL_CMD(REPLY_RX);
850 IWL_CMD(REPLY_COMPRESSED_BA);
851 IWL_CMD(CALIBRATION_CFG_CMD);
852 IWL_CMD(CALIBRATION_RES_NOTIFICATION);
853 IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION);
854 IWL_CMD(REPLY_TX_POWER_DBM_CMD);
855 IWL_CMD(TEMPERATURE_NOTIFICATION);
856 IWL_CMD(TX_ANT_CONFIGURATION_CMD);
857 IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF);
858 IWL_CMD(REPLY_BT_COEX_PRIO_TABLE);
859 IWL_CMD(REPLY_BT_COEX_PROT_ENV);
860 IWL_CMD(REPLY_WIPAN_PARAMS);
861 IWL_CMD(REPLY_WIPAN_RXON);
862 IWL_CMD(REPLY_WIPAN_RXON_TIMING);
863 IWL_CMD(REPLY_WIPAN_RXON_ASSOC);
864 IWL_CMD(REPLY_WIPAN_QOS_PARAM);
865 IWL_CMD(REPLY_WIPAN_WEPKEY);
866 IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH);
867 IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION);
868 IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE);
869 IWL_CMD(REPLY_WOWLAN_PATTERNS);
870 IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER);
871 IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS);
872 IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS);
873 IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL);
874 IWL_CMD(REPLY_WOWLAN_GET_STATUS);
875 default:
876 return "UNKNOWN";
877
878 }
879}
880
881#define HOST_COMPLETE_TIMEOUT (2 * HZ)
882
883static void iwl_generic_cmd_callback(struct iwl_priv *priv,
884 struct iwl_device_cmd *cmd,
885 struct iwl_rx_packet *pkt)
886{
887 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
888 IWL_ERR(priv, "Bad return from %s (0x%08X)\n",
889 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
890 return;
891 }
892
893#ifdef CONFIG_IWLWIFI_DEBUG
894 switch (cmd->hdr.cmd) {
895 case REPLY_TX_LINK_QUALITY_CMD:
896 case SENSITIVITY_CMD:
897 IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n",
898 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
899 break;
900 default:
901 IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n",
902 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
903 }
904#endif
905}
906
907static int iwl_send_cmd_async(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
908{
909 int ret;
910
911 /* An asynchronous command can not expect an SKB to be set. */
912 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
913 return -EINVAL;
914
915 /* Assign a generic callback if one is not provided */
916 if (!cmd->callback)
917 cmd->callback = iwl_generic_cmd_callback;
918
919 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
920 return -EBUSY;
921
922 ret = iwl_enqueue_hcmd(priv, cmd);
923 if (ret < 0) {
924 IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
925 get_cmd_string(cmd->id), ret);
926 return ret;
927 }
928 return 0;
929}
930
931static int iwl_send_cmd_sync(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
932{
933 int cmd_idx;
934 int ret;
935
936 lockdep_assert_held(&priv->mutex);
937
938 /* A synchronous command can not have a callback set. */
939 if (WARN_ON(cmd->callback))
940 return -EINVAL;
941
942 IWL_DEBUG_INFO(priv, "Attempting to send sync command %s\n",
943 get_cmd_string(cmd->id));
944
945 set_bit(STATUS_HCMD_ACTIVE, &priv->status);
946 IWL_DEBUG_INFO(priv, "Setting HCMD_ACTIVE for command %s\n",
947 get_cmd_string(cmd->id));
948
949 cmd_idx = iwl_enqueue_hcmd(priv, cmd);
950 if (cmd_idx < 0) {
951 ret = cmd_idx;
952 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
953 IWL_ERR(priv, "Error sending %s: enqueue_hcmd failed: %d\n",
954 get_cmd_string(cmd->id), ret);
955 return ret;
956 }
957
958 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
959 !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
960 HOST_COMPLETE_TIMEOUT);
961 if (!ret) {
962 if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
963 IWL_ERR(priv,
964 "Error sending %s: time out after %dms.\n",
965 get_cmd_string(cmd->id),
966 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
967
968 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
969 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command"
970 "%s\n", get_cmd_string(cmd->id));
971 ret = -ETIMEDOUT;
972 goto cancel;
973 }
974 }
975
976 if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
977 IWL_ERR(priv, "Command %s aborted: RF KILL Switch\n",
978 get_cmd_string(cmd->id));
979 ret = -ECANCELED;
980 goto fail;
981 }
982 if (test_bit(STATUS_FW_ERROR, &priv->status)) {
983 IWL_ERR(priv, "Command %s failed: FW Error\n",
984 get_cmd_string(cmd->id));
985 ret = -EIO;
986 goto fail;
987 }
988 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
989 IWL_ERR(priv, "Error: Response NULL in '%s'\n",
990 get_cmd_string(cmd->id));
991 ret = -EIO;
992 goto cancel;
993 }
994
995 return 0;
996
997cancel:
998 if (cmd->flags & CMD_WANT_SKB) {
999 /*
1000 * Cancel the CMD_WANT_SKB flag for the cmd in the
1001 * TX cmd queue. Otherwise in case the cmd comes
1002 * in later, it will possibly set an invalid
1003 * address (cmd->meta.source).
1004 */
1005 priv->txq[priv->cmd_queue].meta[cmd_idx].flags &=
1006 ~CMD_WANT_SKB;
1007 }
1008fail:
1009 if (cmd->reply_page) {
1010 iwl_free_pages(priv, cmd->reply_page);
1011 cmd->reply_page = 0;
1012 }
1013
1014 return ret;
1015}
1016
1017int iwl_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1018{
1019 if (cmd->flags & CMD_ASYNC)
1020 return iwl_send_cmd_async(priv, cmd);
1021
1022 return iwl_send_cmd_sync(priv, cmd);
1023}
1024
1025int iwl_send_cmd_pdu(struct iwl_priv *priv, u8 id, u32 flags, u16 len,
1026 const void *data)
1027{
1028 struct iwl_host_cmd cmd = {
1029 .id = id,
1030 .len = { len, },
1031 .data = { data, },
1032 .flags = flags,
1033 };
1034
1035 return iwl_send_cmd(priv, &cmd);
1036}
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans.c b/drivers/net/wireless/iwlwifi/iwl-trans.c
new file mode 100644
index 000000000000..41f0de914008
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-trans.c
@@ -0,0 +1,1172 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63#include "iwl-dev.h"
64#include "iwl-trans.h"
65#include "iwl-core.h"
66#include "iwl-helpers.h"
67#include "iwl-trans-int-pcie.h"
68/*TODO remove uneeded includes when the transport layer tx_free will be here */
69#include "iwl-agn.h"
70#include "iwl-core.h"
71
72static int iwl_trans_rx_alloc(struct iwl_priv *priv)
73{
74 struct iwl_rx_queue *rxq = &priv->rxq;
75 struct device *dev = priv->bus->dev;
76
77 memset(&priv->rxq, 0, sizeof(priv->rxq));
78
79 spin_lock_init(&rxq->lock);
80 INIT_LIST_HEAD(&rxq->rx_free);
81 INIT_LIST_HEAD(&rxq->rx_used);
82
83 if (WARN_ON(rxq->bd || rxq->rb_stts))
84 return -EINVAL;
85
86 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
87 rxq->bd = dma_alloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
88 &rxq->bd_dma, GFP_KERNEL);
89 if (!rxq->bd)
90 goto err_bd;
91 memset(rxq->bd, 0, sizeof(__le32) * RX_QUEUE_SIZE);
92
93 /*Allocate the driver's pointer to receive buffer status */
94 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(*rxq->rb_stts),
95 &rxq->rb_stts_dma, GFP_KERNEL);
96 if (!rxq->rb_stts)
97 goto err_rb_stts;
98 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
99
100 return 0;
101
102err_rb_stts:
103 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
104 rxq->bd, rxq->bd_dma);
105 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
106 rxq->bd = NULL;
107err_bd:
108 return -ENOMEM;
109}
110
111static void iwl_trans_rxq_free_rx_bufs(struct iwl_priv *priv)
112{
113 struct iwl_rx_queue *rxq = &priv->rxq;
114 int i;
115
116 /* Fill the rx_used queue with _all_ of the Rx buffers */
117 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
118 /* In the reset function, these buffers may have been allocated
119 * to an SKB, so we need to unmap and free potential storage */
120 if (rxq->pool[i].page != NULL) {
121 dma_unmap_page(priv->bus->dev, rxq->pool[i].page_dma,
122 PAGE_SIZE << priv->hw_params.rx_page_order,
123 DMA_FROM_DEVICE);
124 __iwl_free_pages(priv, rxq->pool[i].page);
125 rxq->pool[i].page = NULL;
126 }
127 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
128 }
129}
130
131static void iwl_trans_rx_hw_init(struct iwl_priv *priv,
132 struct iwl_rx_queue *rxq)
133{
134 u32 rb_size;
135 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
136 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
137
138 rb_timeout = RX_RB_TIMEOUT;
139
140 if (iwlagn_mod_params.amsdu_size_8K)
141 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
142 else
143 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
144
145 /* Stop Rx DMA */
146 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
147
148 /* Reset driver's Rx queue write index */
149 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
150
151 /* Tell device where to find RBD circular buffer in DRAM */
152 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
153 (u32)(rxq->bd_dma >> 8));
154
155 /* Tell device where in DRAM to update its Rx status */
156 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
157 rxq->rb_stts_dma >> 4);
158
159 /* Enable Rx DMA
160 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
161 * the credit mechanism in 5000 HW RX FIFO
162 * Direct rx interrupts to hosts
163 * Rx buffer size 4 or 8k
164 * RB timeout 0x10
165 * 256 RBDs
166 */
167 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
168 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
169 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
170 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
171 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
172 rb_size|
173 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
174 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
175
176 /* Set interrupt coalescing timer to default (2048 usecs) */
177 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
178}
179
180static int iwl_rx_init(struct iwl_priv *priv)
181{
182 struct iwl_rx_queue *rxq = &priv->rxq;
183 int i, err;
184 unsigned long flags;
185
186 if (!rxq->bd) {
187 err = iwl_trans_rx_alloc(priv);
188 if (err)
189 return err;
190 }
191
192 spin_lock_irqsave(&rxq->lock, flags);
193 INIT_LIST_HEAD(&rxq->rx_free);
194 INIT_LIST_HEAD(&rxq->rx_used);
195
196 iwl_trans_rxq_free_rx_bufs(priv);
197
198 for (i = 0; i < RX_QUEUE_SIZE; i++)
199 rxq->queue[i] = NULL;
200
201 /* Set us so that we have processed and used all buffers, but have
202 * not restocked the Rx queue with fresh buffers */
203 rxq->read = rxq->write = 0;
204 rxq->write_actual = 0;
205 rxq->free_count = 0;
206 spin_unlock_irqrestore(&rxq->lock, flags);
207
208 iwlagn_rx_replenish(priv);
209
210 iwl_trans_rx_hw_init(priv, rxq);
211
212 spin_lock_irqsave(&priv->lock, flags);
213 rxq->need_update = 1;
214 iwl_rx_queue_update_write_ptr(priv, rxq);
215 spin_unlock_irqrestore(&priv->lock, flags);
216
217 return 0;
218}
219
220static void iwl_trans_rx_free(struct iwl_priv *priv)
221{
222 struct iwl_rx_queue *rxq = &priv->rxq;
223 unsigned long flags;
224
225 /*if rxq->bd is NULL, it means that nothing has been allocated,
226 * exit now */
227 if (!rxq->bd) {
228 IWL_DEBUG_INFO(priv, "Free NULL rx context\n");
229 return;
230 }
231
232 spin_lock_irqsave(&rxq->lock, flags);
233 iwl_trans_rxq_free_rx_bufs(priv);
234 spin_unlock_irqrestore(&rxq->lock, flags);
235
236 dma_free_coherent(priv->bus->dev, sizeof(__le32) * RX_QUEUE_SIZE,
237 rxq->bd, rxq->bd_dma);
238 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
239 rxq->bd = NULL;
240
241 if (rxq->rb_stts)
242 dma_free_coherent(priv->bus->dev,
243 sizeof(struct iwl_rb_status),
244 rxq->rb_stts, rxq->rb_stts_dma);
245 else
246 IWL_DEBUG_INFO(priv, "Free rxq->rb_stts which is NULL\n");
247 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
248 rxq->rb_stts = NULL;
249}
250
251static int iwl_trans_rx_stop(struct iwl_priv *priv)
252{
253
254 /* stop Rx DMA */
255 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
256 return iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
257 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
258}
259
260static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
261 struct iwl_dma_ptr *ptr, size_t size)
262{
263 if (WARN_ON(ptr->addr))
264 return -EINVAL;
265
266 ptr->addr = dma_alloc_coherent(priv->bus->dev, size,
267 &ptr->dma, GFP_KERNEL);
268 if (!ptr->addr)
269 return -ENOMEM;
270 ptr->size = size;
271 return 0;
272}
273
274static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
275 struct iwl_dma_ptr *ptr)
276{
277 if (unlikely(!ptr->addr))
278 return;
279
280 dma_free_coherent(priv->bus->dev, ptr->size, ptr->addr, ptr->dma);
281 memset(ptr, 0, sizeof(*ptr));
282}
283
284static int iwl_trans_txq_alloc(struct iwl_priv *priv, struct iwl_tx_queue *txq,
285 int slots_num, u32 txq_id)
286{
287 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
288 int i;
289
290 if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
291 return -EINVAL;
292
293 txq->q.n_window = slots_num;
294
295 txq->meta = kzalloc(sizeof(txq->meta[0]) * slots_num,
296 GFP_KERNEL);
297 txq->cmd = kzalloc(sizeof(txq->cmd[0]) * slots_num,
298 GFP_KERNEL);
299
300 if (!txq->meta || !txq->cmd)
301 goto error;
302
303 for (i = 0; i < slots_num; i++) {
304 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
305 GFP_KERNEL);
306 if (!txq->cmd[i])
307 goto error;
308 }
309
310 /* Alloc driver data array and TFD circular buffer */
311 /* Driver private data, only for Tx (not command) queues,
312 * not shared with device. */
313 if (txq_id != priv->cmd_queue) {
314 txq->txb = kzalloc(sizeof(txq->txb[0]) *
315 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
316 if (!txq->txb) {
317 IWL_ERR(priv, "kmalloc for auxiliary BD "
318 "structures failed\n");
319 goto error;
320 }
321 } else {
322 txq->txb = NULL;
323 }
324
325 /* Circular buffer of transmit frame descriptors (TFDs),
326 * shared with device */
327 txq->tfds = dma_alloc_coherent(priv->bus->dev, tfd_sz, &txq->q.dma_addr,
328 GFP_KERNEL);
329 if (!txq->tfds) {
330 IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
331 goto error;
332 }
333 txq->q.id = txq_id;
334
335 return 0;
336error:
337 kfree(txq->txb);
338 txq->txb = NULL;
339 /* since txq->cmd has been zeroed,
340 * all non allocated cmd[i] will be NULL */
341 if (txq->cmd)
342 for (i = 0; i < slots_num; i++)
343 kfree(txq->cmd[i]);
344 kfree(txq->meta);
345 kfree(txq->cmd);
346 txq->meta = NULL;
347 txq->cmd = NULL;
348
349 return -ENOMEM;
350
351}
352
353static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
354 int slots_num, u32 txq_id)
355{
356 int ret;
357
358 txq->need_update = 0;
359 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
360
361 /*
362 * For the default queues 0-3, set up the swq_id
363 * already -- all others need to get one later
364 * (if they need one at all).
365 */
366 if (txq_id < 4)
367 iwl_set_swq_id(txq, txq_id, txq_id);
368
369 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
370 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
371 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
372
373 /* Initialize queue's high/low-water marks, and head/tail indexes */
374 ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
375 txq_id);
376 if (ret)
377 return ret;
378
379 /*
380 * Tell nic where to find circular buffer of Tx Frame Descriptors for
381 * given Tx queue, and enable the DMA channel used for that queue.
382 * Circular buffer (TFD queue in DRAM) physical base address */
383 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
384 txq->q.dma_addr >> 8);
385
386 return 0;
387}
388
389/**
390 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
391 */
392static void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
393{
394 struct iwl_tx_queue *txq = &priv->txq[txq_id];
395 struct iwl_queue *q = &txq->q;
396
397 if (!q->n_bd)
398 return;
399
400 while (q->write_ptr != q->read_ptr) {
401 /* The read_ptr needs to bound by q->n_window */
402 iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr));
403 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
404 }
405}
406
407/**
408 * iwl_tx_queue_free - Deallocate DMA queue.
409 * @txq: Transmit queue to deallocate.
410 *
411 * Empty queue by removing and destroying all BD's.
412 * Free all buffers.
413 * 0-fill, but do not free "txq" descriptor structure.
414 */
415static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
416{
417 struct iwl_tx_queue *txq = &priv->txq[txq_id];
418 struct device *dev = priv->bus->dev;
419 int i;
420 if (WARN_ON(!txq))
421 return;
422
423 iwl_tx_queue_unmap(priv, txq_id);
424
425 /* De-alloc array of command/tx buffers */
426 for (i = 0; i < txq->q.n_window; i++)
427 kfree(txq->cmd[i]);
428
429 /* De-alloc circular buffer of TFDs */
430 if (txq->q.n_bd) {
431 dma_free_coherent(dev, priv->hw_params.tfd_size *
432 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
433 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
434 }
435
436 /* De-alloc array of per-TFD driver data */
437 kfree(txq->txb);
438 txq->txb = NULL;
439
440 /* deallocate arrays */
441 kfree(txq->cmd);
442 kfree(txq->meta);
443 txq->cmd = NULL;
444 txq->meta = NULL;
445
446 /* 0-fill queue descriptor structure */
447 memset(txq, 0, sizeof(*txq));
448}
449
450/**
451 * iwl_trans_tx_free - Free TXQ Context
452 *
453 * Destroy all TX DMA queues and structures
454 */
455static void iwl_trans_tx_free(struct iwl_priv *priv)
456{
457 int txq_id;
458
459 /* Tx queues */
460 if (priv->txq) {
461 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
462 iwl_tx_queue_free(priv, txq_id);
463 }
464
465 kfree(priv->txq);
466 priv->txq = NULL;
467
468 iwlagn_free_dma_ptr(priv, &priv->kw);
469
470 iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
471}
472
473/**
474 * iwl_trans_tx_alloc - allocate TX context
475 * Allocate all Tx DMA structures and initialize them
476 *
477 * @param priv
478 * @return error code
479 */
480static int iwl_trans_tx_alloc(struct iwl_priv *priv)
481{
482 int ret;
483 int txq_id, slots_num;
484
485 /*It is not allowed to alloc twice, so warn when this happens.
486 * We cannot rely on the previous allocation, so free and fail */
487 if (WARN_ON(priv->txq)) {
488 ret = -EINVAL;
489 goto error;
490 }
491
492 ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
493 priv->hw_params.scd_bc_tbls_size);
494 if (ret) {
495 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
496 goto error;
497 }
498
499 /* Alloc keep-warm buffer */
500 ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
501 if (ret) {
502 IWL_ERR(priv, "Keep Warm allocation failed\n");
503 goto error;
504 }
505
506 priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
507 priv->cfg->base_params->num_of_queues, GFP_KERNEL);
508 if (!priv->txq) {
509 IWL_ERR(priv, "Not enough memory for txq\n");
510 ret = ENOMEM;
511 goto error;
512 }
513
514 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
515 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
516 slots_num = (txq_id == priv->cmd_queue) ?
517 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
518 ret = iwl_trans_txq_alloc(priv, &priv->txq[txq_id], slots_num,
519 txq_id);
520 if (ret) {
521 IWL_ERR(priv, "Tx %d queue alloc failed\n", txq_id);
522 goto error;
523 }
524 }
525
526 return 0;
527
528error:
529 trans_tx_free(&priv->trans);
530
531 return ret;
532}
533static int iwl_tx_init(struct iwl_priv *priv)
534{
535 int ret;
536 int txq_id, slots_num;
537 unsigned long flags;
538 bool alloc = false;
539
540 if (!priv->txq) {
541 ret = iwl_trans_tx_alloc(priv);
542 if (ret)
543 goto error;
544 alloc = true;
545 }
546
547 spin_lock_irqsave(&priv->lock, flags);
548
549 /* Turn off all Tx DMA fifos */
550 iwl_write_prph(priv, SCD_TXFACT, 0);
551
552 /* Tell NIC where to find the "keep warm" buffer */
553 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
554
555 spin_unlock_irqrestore(&priv->lock, flags);
556
557 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
558 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
559 slots_num = (txq_id == priv->cmd_queue) ?
560 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
561 ret = iwl_trans_txq_init(priv, &priv->txq[txq_id], slots_num,
562 txq_id);
563 if (ret) {
564 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
565 goto error;
566 }
567 }
568
569 return 0;
570error:
571 /*Upon error, free only if we allocated something */
572 if (alloc)
573 trans_tx_free(&priv->trans);
574 return ret;
575}
576
577static void iwl_set_pwr_vmain(struct iwl_priv *priv)
578{
579/*
580 * (for documentation purposes)
581 * to set power to V_AUX, do:
582
583 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
584 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
585 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
586 ~APMG_PS_CTRL_MSK_PWR_SRC);
587 */
588
589 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
590 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
591 ~APMG_PS_CTRL_MSK_PWR_SRC);
592}
593
594static int iwl_nic_init(struct iwl_priv *priv)
595{
596 unsigned long flags;
597
598 /* nic_init */
599 spin_lock_irqsave(&priv->lock, flags);
600 iwl_apm_init(priv);
601
602 /* Set interrupt coalescing calibration timer to default (512 usecs) */
603 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
604
605 spin_unlock_irqrestore(&priv->lock, flags);
606
607 iwl_set_pwr_vmain(priv);
608
609 priv->cfg->lib->nic_config(priv);
610
611 /* Allocate the RX queue, or reset if it is already allocated */
612 iwl_rx_init(priv);
613
614 /* Allocate or reset and init all Tx and Command queues */
615 if (iwl_tx_init(priv))
616 return -ENOMEM;
617
618 if (priv->cfg->base_params->shadow_reg_enable) {
619 /* enable shadow regs in HW */
620 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
621 0x800FFFFF);
622 }
623
624 set_bit(STATUS_INIT, &priv->status);
625
626 return 0;
627}
628
629#define HW_READY_TIMEOUT (50)
630
631/* Note: returns poll_bit return value, which is >= 0 if success */
632static int iwl_set_hw_ready(struct iwl_priv *priv)
633{
634 int ret;
635
636 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
637 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
638
639 /* See if we got it */
640 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
641 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
642 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
643 HW_READY_TIMEOUT);
644
645 IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
646 return ret;
647}
648
649/* Note: returns standard 0/-ERROR code */
650static int iwl_trans_prepare_card_hw(struct iwl_priv *priv)
651{
652 int ret;
653
654 IWL_DEBUG_INFO(priv, "iwl_trans_prepare_card_hw enter\n");
655
656 ret = iwl_set_hw_ready(priv);
657 if (ret >= 0)
658 return 0;
659
660 /* If HW is not ready, prepare the conditions to check again */
661 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
662 CSR_HW_IF_CONFIG_REG_PREPARE);
663
664 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
665 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
666 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
667
668 if (ret < 0)
669 return ret;
670
671 /* HW should be ready by now, check again. */
672 ret = iwl_set_hw_ready(priv);
673 if (ret >= 0)
674 return 0;
675 return ret;
676}
677
678static int iwl_trans_start_device(struct iwl_priv *priv)
679{
680 int ret;
681
682 priv->ucode_owner = IWL_OWNERSHIP_DRIVER;
683
684 if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
685 iwl_trans_prepare_card_hw(priv)) {
686 IWL_WARN(priv, "Exit HW not ready\n");
687 return -EIO;
688 }
689
690 /* If platform's RF_KILL switch is NOT set to KILL */
691 if (iwl_read32(priv, CSR_GP_CNTRL) &
692 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
693 clear_bit(STATUS_RF_KILL_HW, &priv->status);
694 else
695 set_bit(STATUS_RF_KILL_HW, &priv->status);
696
697 if (iwl_is_rfkill(priv)) {
698 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
699 iwl_enable_interrupts(priv);
700 return -ERFKILL;
701 }
702
703 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
704
705 ret = iwl_nic_init(priv);
706 if (ret) {
707 IWL_ERR(priv, "Unable to init nic\n");
708 return ret;
709 }
710
711 /* make sure rfkill handshake bits are cleared */
712 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
713 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
714 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
715
716 /* clear (again), then enable host interrupts */
717 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
718 iwl_enable_interrupts(priv);
719
720 /* really make sure rfkill handshake bits are cleared */
721 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
722 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
723
724 return 0;
725}
726
727/*
728 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
729 * must be called under priv->lock and mac access
730 */
731static void iwl_trans_txq_set_sched(struct iwl_priv *priv, u32 mask)
732{
733 iwl_write_prph(priv, SCD_TXFACT, mask);
734}
735
736#define IWL_AC_UNSET -1
737
738struct queue_to_fifo_ac {
739 s8 fifo, ac;
740};
741
742static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
743 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
744 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
745 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
746 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
747 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
748 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
749 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
750 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
751 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
752 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
753};
754
755static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
756 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
757 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
758 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
759 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
760 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
761 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
762 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
763 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
764 { IWL_TX_FIFO_BE_IPAN, 2, },
765 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
766};
767static void iwl_trans_tx_start(struct iwl_priv *priv)
768{
769 const struct queue_to_fifo_ac *queue_to_fifo;
770 struct iwl_rxon_context *ctx;
771 u32 a;
772 unsigned long flags;
773 int i, chan;
774 u32 reg_val;
775
776 spin_lock_irqsave(&priv->lock, flags);
777
778 priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
779 a = priv->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
780 /* reset conext data memory */
781 for (; a < priv->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
782 a += 4)
783 iwl_write_targ_mem(priv, a, 0);
784 /* reset tx status memory */
785 for (; a < priv->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
786 a += 4)
787 iwl_write_targ_mem(priv, a, 0);
788 for (; a < priv->scd_base_addr +
789 SCD_TRANS_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
790 iwl_write_targ_mem(priv, a, 0);
791
792 iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
793 priv->scd_bc_tbls.dma >> 10);
794
795 /* Enable DMA channel */
796 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
797 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
798 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
799 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
800
801 /* Update FH chicken bits */
802 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
803 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
804 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
805
806 iwl_write_prph(priv, SCD_QUEUECHAIN_SEL,
807 SCD_QUEUECHAIN_SEL_ALL(priv));
808 iwl_write_prph(priv, SCD_AGGR_SEL, 0);
809
810 /* initiate the queues */
811 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
812 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
813 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
814 iwl_write_targ_mem(priv, priv->scd_base_addr +
815 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
816 iwl_write_targ_mem(priv, priv->scd_base_addr +
817 SCD_CONTEXT_QUEUE_OFFSET(i) +
818 sizeof(u32),
819 ((SCD_WIN_SIZE <<
820 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
821 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
822 ((SCD_FRAME_LIMIT <<
823 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
824 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
825 }
826
827 iwl_write_prph(priv, SCD_INTERRUPT_MASK,
828 IWL_MASK(0, priv->hw_params.max_txq_num));
829
830 /* Activate all Tx DMA/FIFO channels */
831 iwl_trans_txq_set_sched(priv, IWL_MASK(0, 7));
832
833 /* map queues to FIFOs */
834 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
835 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
836 else
837 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
838
839 iwl_trans_set_wr_ptrs(priv, priv->cmd_queue, 0);
840
841 /* make sure all queue are not stopped */
842 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
843 for (i = 0; i < 4; i++)
844 atomic_set(&priv->queue_stop_count[i], 0);
845 for_each_context(priv, ctx)
846 ctx->last_tx_rejected = false;
847
848 /* reset to 0 to enable all the queue first */
849 priv->txq_ctx_active_msk = 0;
850
851 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
852 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
853
854 for (i = 0; i < 10; i++) {
855 int fifo = queue_to_fifo[i].fifo;
856 int ac = queue_to_fifo[i].ac;
857
858 iwl_txq_ctx_activate(priv, i);
859
860 if (fifo == IWL_TX_FIFO_UNUSED)
861 continue;
862
863 if (ac != IWL_AC_UNSET)
864 iwl_set_swq_id(&priv->txq[i], ac, i);
865 iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
866 }
867
868 spin_unlock_irqrestore(&priv->lock, flags);
869
870 /* Enable L1-Active */
871 iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
872 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
873}
874
875/**
876 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
877 */
878static int iwl_trans_tx_stop(struct iwl_priv *priv)
879{
880 int ch, txq_id;
881 unsigned long flags;
882
883 /* Turn off all Tx DMA fifos */
884 spin_lock_irqsave(&priv->lock, flags);
885
886 iwl_trans_txq_set_sched(priv, 0);
887
888 /* Stop each Tx DMA channel, and wait for it to be idle */
889 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
890 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
891 if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
892 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
893 1000))
894 IWL_ERR(priv, "Failing on timeout while stopping"
895 " DMA channel %d [0x%08x]", ch,
896 iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
897 }
898 spin_unlock_irqrestore(&priv->lock, flags);
899
900 if (!priv->txq) {
901 IWL_WARN(priv, "Stopping tx queues that aren't allocated...");
902 return 0;
903 }
904
905 /* Unmap DMA from host system and free skb's */
906 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
907 iwl_tx_queue_unmap(priv, txq_id);
908
909 return 0;
910}
911
912static void iwl_trans_stop_device(struct iwl_priv *priv)
913{
914 unsigned long flags;
915
916 /* stop and reset the on-board processor */
917 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
918
919 /* tell the device to stop sending interrupts */
920 spin_lock_irqsave(&priv->lock, flags);
921 iwl_disable_interrupts(priv);
922 spin_unlock_irqrestore(&priv->lock, flags);
923 trans_sync_irq(&priv->trans);
924
925 /* device going down, Stop using ICT table */
926 iwl_disable_ict(priv);
927
928 /*
929 * If a HW restart happens during firmware loading,
930 * then the firmware loading might call this function
931 * and later it might be called again due to the
932 * restart. So don't process again if the device is
933 * already dead.
934 */
935 if (test_bit(STATUS_DEVICE_ENABLED, &priv->status)) {
936 iwl_trans_tx_stop(priv);
937 iwl_trans_rx_stop(priv);
938
939 /* Power-down device's busmaster DMA clocks */
940 iwl_write_prph(priv, APMG_CLK_DIS_REG,
941 APMG_CLK_VAL_DMA_CLK_RQT);
942 udelay(5);
943 }
944
945 /* Make sure (redundant) we've released our request to stay awake */
946 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
947
948 /* Stop the device, and put it in low power state */
949 iwl_apm_stop(priv);
950}
951
952static struct iwl_tx_cmd *iwl_trans_get_tx_cmd(struct iwl_priv *priv,
953 int txq_id)
954{
955 struct iwl_tx_queue *txq = &priv->txq[txq_id];
956 struct iwl_queue *q = &txq->q;
957 struct iwl_device_cmd *dev_cmd;
958
959 if (unlikely(iwl_queue_space(q) < q->high_mark))
960 return NULL;
961
962 /*
963 * Set up the Tx-command (not MAC!) header.
964 * Store the chosen Tx queue and TFD index within the sequence field;
965 * after Tx, uCode's Tx response will return this value so driver can
966 * locate the frame within the tx queue and do post-tx processing.
967 */
968 dev_cmd = txq->cmd[q->write_ptr];
969 memset(dev_cmd, 0, sizeof(*dev_cmd));
970 dev_cmd->hdr.cmd = REPLY_TX;
971 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
972 INDEX_TO_SEQ(q->write_ptr)));
973 return &dev_cmd->cmd.tx;
974}
975
976static int iwl_trans_tx(struct iwl_priv *priv, struct sk_buff *skb,
977 struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
978 struct iwl_rxon_context *ctx)
979{
980 struct iwl_tx_queue *txq = &priv->txq[txq_id];
981 struct iwl_queue *q = &txq->q;
982 struct iwl_device_cmd *dev_cmd = txq->cmd[q->write_ptr];
983 struct iwl_cmd_meta *out_meta;
984
985 dma_addr_t phys_addr = 0;
986 dma_addr_t txcmd_phys;
987 dma_addr_t scratch_phys;
988 u16 len, firstlen, secondlen;
989 u8 wait_write_ptr = 0;
990 u8 hdr_len = ieee80211_hdrlen(fc);
991
992 /* Set up driver data for this TFD */
993 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
994 txq->txb[q->write_ptr].skb = skb;
995 txq->txb[q->write_ptr].ctx = ctx;
996
997 /* Set up first empty entry in queue's array of Tx/cmd buffers */
998 out_meta = &txq->meta[q->write_ptr];
999
1000 /*
1001 * Use the first empty entry in this queue's command buffer array
1002 * to contain the Tx command and MAC header concatenated together
1003 * (payload data will be in another buffer).
1004 * Size of this varies, due to varying MAC header length.
1005 * If end is not dword aligned, we'll have 2 extra bytes at the end
1006 * of the MAC header (device reads on dword boundaries).
1007 * We'll tell device about this padding later.
1008 */
1009 len = sizeof(struct iwl_tx_cmd) +
1010 sizeof(struct iwl_cmd_header) + hdr_len;
1011 firstlen = (len + 3) & ~3;
1012
1013 /* Tell NIC about any 2-byte padding after MAC header */
1014 if (firstlen != len)
1015 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1016
1017 /* Physical address of this Tx command's header (not MAC header!),
1018 * within command buffer array. */
1019 txcmd_phys = dma_map_single(priv->bus->dev,
1020 &dev_cmd->hdr, firstlen,
1021 DMA_BIDIRECTIONAL);
1022 if (unlikely(dma_mapping_error(priv->bus->dev, txcmd_phys)))
1023 return -1;
1024 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1025 dma_unmap_len_set(out_meta, len, firstlen);
1026
1027 if (!ieee80211_has_morefrags(fc)) {
1028 txq->need_update = 1;
1029 } else {
1030 wait_write_ptr = 1;
1031 txq->need_update = 0;
1032 }
1033
1034 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1035 * if any (802.11 null frames have no payload). */
1036 secondlen = skb->len - hdr_len;
1037 if (secondlen > 0) {
1038 phys_addr = dma_map_single(priv->bus->dev, skb->data + hdr_len,
1039 secondlen, DMA_TO_DEVICE);
1040 if (unlikely(dma_mapping_error(priv->bus->dev, phys_addr))) {
1041 dma_unmap_single(priv->bus->dev,
1042 dma_unmap_addr(out_meta, mapping),
1043 dma_unmap_len(out_meta, len),
1044 DMA_BIDIRECTIONAL);
1045 return -1;
1046 }
1047 }
1048
1049 /* Attach buffers to TFD */
1050 iwlagn_txq_attach_buf_to_tfd(priv, txq, txcmd_phys, firstlen, 1);
1051 if (secondlen > 0)
1052 iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
1053 secondlen, 0);
1054
1055 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1056 offsetof(struct iwl_tx_cmd, scratch);
1057
1058 /* take back ownership of DMA buffer to enable update */
1059 dma_sync_single_for_cpu(priv->bus->dev, txcmd_phys, firstlen,
1060 DMA_BIDIRECTIONAL);
1061 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1062 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1063
1064 IWL_DEBUG_TX(priv, "sequence nr = 0X%x\n",
1065 le16_to_cpu(dev_cmd->hdr.sequence));
1066 IWL_DEBUG_TX(priv, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1067 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1068 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1069
1070 /* Set up entry for this TFD in Tx byte-count array */
1071 if (ampdu)
1072 iwl_trans_txq_update_byte_cnt_tbl(priv, txq,
1073 le16_to_cpu(tx_cmd->len));
1074
1075 dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
1076 DMA_BIDIRECTIONAL);
1077
1078 trace_iwlwifi_dev_tx(priv,
1079 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1080 sizeof(struct iwl_tfd),
1081 &dev_cmd->hdr, firstlen,
1082 skb->data + hdr_len, secondlen);
1083
1084 /* Tell device the write index *just past* this latest filled TFD */
1085 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1086 iwl_txq_update_write_ptr(priv, txq);
1087
1088 /*
1089 * At this point the frame is "transmitted" successfully
1090 * and we will get a TX status notification eventually,
1091 * regardless of the value of ret. "ret" only indicates
1092 * whether or not we should update the write pointer.
1093 */
1094 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
1095 if (wait_write_ptr) {
1096 txq->need_update = 1;
1097 iwl_txq_update_write_ptr(priv, txq);
1098 } else {
1099 iwl_stop_queue(priv, txq);
1100 }
1101 }
1102 return 0;
1103}
1104
1105static void iwl_trans_kick_nic(struct iwl_priv *priv)
1106{
1107 /* Remove all resets to allow NIC to operate */
1108 iwl_write32(priv, CSR_RESET, 0);
1109}
1110
1111static void iwl_trans_sync_irq(struct iwl_priv *priv)
1112{
1113 /* wait to make sure we flush pending tasklet*/
1114 synchronize_irq(priv->bus->irq);
1115 tasklet_kill(&priv->irq_tasklet);
1116}
1117
1118static void iwl_trans_free(struct iwl_priv *priv)
1119{
1120 free_irq(priv->bus->irq, priv);
1121 iwl_free_isr_ict(priv);
1122}
1123
1124static const struct iwl_trans_ops trans_ops = {
1125 .start_device = iwl_trans_start_device,
1126 .prepare_card_hw = iwl_trans_prepare_card_hw,
1127 .stop_device = iwl_trans_stop_device,
1128
1129 .tx_start = iwl_trans_tx_start,
1130
1131 .rx_free = iwl_trans_rx_free,
1132 .tx_free = iwl_trans_tx_free,
1133
1134 .send_cmd = iwl_send_cmd,
1135 .send_cmd_pdu = iwl_send_cmd_pdu,
1136
1137 .get_tx_cmd = iwl_trans_get_tx_cmd,
1138 .tx = iwl_trans_tx,
1139
1140 .txq_agg_disable = iwl_trans_txq_agg_disable,
1141 .txq_agg_setup = iwl_trans_txq_agg_setup,
1142
1143 .kick_nic = iwl_trans_kick_nic,
1144
1145 .sync_irq = iwl_trans_sync_irq,
1146 .free = iwl_trans_free,
1147};
1148
1149int iwl_trans_register(struct iwl_trans *trans, struct iwl_priv *priv)
1150{
1151 int err;
1152
1153 priv->trans.ops = &trans_ops;
1154 priv->trans.priv = priv;
1155
1156 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
1157 iwl_irq_tasklet, (unsigned long)priv);
1158
1159 iwl_alloc_isr_ict(priv);
1160
1161 err = request_irq(priv->bus->irq, iwl_isr_ict, IRQF_SHARED,
1162 DRV_NAME, priv);
1163 if (err) {
1164 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->bus->irq);
1165 iwl_free_isr_ict(priv);
1166 return err;
1167 }
1168
1169 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
1170
1171 return 0;
1172}
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans.h b/drivers/net/wireless/iwlwifi/iwl-trans.h
new file mode 100644
index 000000000000..7993aa7ae668
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-trans.h
@@ -0,0 +1,225 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2007 - 2011 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63#ifndef __iwl_trans_h__
64#define __iwl_trans_h__
65
66 /*This file includes the declaration that are exported from the transport
67 * layer */
68
69struct iwl_priv;
70struct iwl_rxon_context;
71struct iwl_host_cmd;
72
73/**
74 * struct iwl_trans_ops - transport specific operations
75 * @start_device: allocates and inits all the resources for the transport
76 * layer.
77 * @prepare_card_hw: claim the ownership on the HW. Will be called during
78 * probe.
79 * @tx_start: starts and configures all the Tx fifo - usually done once the fw
80 * is alive.
81 * @stop_device:stops the whole device (embedded CPU put to reset)
82 * @rx_free: frees the rx memory
83 * @tx_free: frees the tx memory
84 * @send_cmd:send a host command
85 * @send_cmd_pdu:send a host command: flags can be CMD_*
86 * @get_tx_cmd: returns a pointer to a new Tx cmd for the upper layer use
87 * @tx: send an skb
88 * @txq_agg_setup: setup a tx queue for AMPDU - will be called once the HW is
89 * ready and a successful ADDBA response has been received.
90 * @txq_agg_disable: de-configure a Tx queue to send AMPDUs
91 * @kick_nic: remove the RESET from the embedded CPU and let it run
92 * @sync_irq: the upper layer will typically disable interrupt and call this
93 * handler. After this handler returns, it is guaranteed that all
94 * the ISR / tasklet etc... have finished running and the transport
95 * layer shall not pass any Rx.
96 * @free: release all the ressource for the transport layer itself such as
97 * irq, tasklet etc...
98 */
99struct iwl_trans_ops {
100
101 int (*start_device)(struct iwl_priv *priv);
102 int (*prepare_card_hw)(struct iwl_priv *priv);
103 void (*stop_device)(struct iwl_priv *priv);
104 void (*tx_start)(struct iwl_priv *priv);
105 void (*tx_free)(struct iwl_priv *priv);
106 void (*rx_free)(struct iwl_priv *priv);
107
108 int (*send_cmd)(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
109
110 int (*send_cmd_pdu)(struct iwl_priv *priv, u8 id, u32 flags, u16 len,
111 const void *data);
112 struct iwl_tx_cmd * (*get_tx_cmd)(struct iwl_priv *priv, int txq_id);
113 int (*tx)(struct iwl_priv *priv, struct sk_buff *skb,
114 struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
115 struct iwl_rxon_context *ctx);
116
117 int (*txq_agg_disable)(struct iwl_priv *priv, u16 txq_id,
118 u16 ssn_idx, u8 tx_fifo);
119 void (*txq_agg_setup)(struct iwl_priv *priv, int sta_id, int tid,
120 int frame_limit);
121
122 void (*kick_nic)(struct iwl_priv *priv);
123
124 void (*sync_irq)(struct iwl_priv *priv);
125 void (*free)(struct iwl_priv *priv);
126};
127
128struct iwl_trans {
129 const struct iwl_trans_ops *ops;
130 struct iwl_priv *priv;
131};
132
133static inline int trans_start_device(struct iwl_trans *trans)
134{
135 return trans->ops->start_device(trans->priv);
136}
137
138static inline int trans_prepare_card_hw(struct iwl_trans *trans)
139{
140 return trans->ops->prepare_card_hw(trans->priv);
141}
142
143static inline void trans_stop_device(struct iwl_trans *trans)
144{
145 trans->ops->stop_device(trans->priv);
146}
147
148static inline void trans_tx_start(struct iwl_trans *trans)
149{
150 trans->ops->tx_start(trans->priv);
151}
152
153static inline void trans_rx_free(struct iwl_trans *trans)
154{
155 trans->ops->rx_free(trans->priv);
156}
157
158static inline void trans_tx_free(struct iwl_trans *trans)
159{
160 trans->ops->tx_free(trans->priv);
161}
162
163static inline int trans_send_cmd(struct iwl_trans *trans,
164 struct iwl_host_cmd *cmd)
165{
166 return trans->ops->send_cmd(trans->priv, cmd);
167}
168
169static inline int trans_send_cmd_pdu(struct iwl_trans *trans, u8 id, u32 flags,
170 u16 len, const void *data)
171{
172 return trans->ops->send_cmd_pdu(trans->priv, id, flags, len, data);
173}
174
175static inline struct iwl_tx_cmd *trans_get_tx_cmd(struct iwl_trans *trans,
176 int txq_id)
177{
178 return trans->ops->get_tx_cmd(trans->priv, txq_id);
179}
180
181static inline int trans_tx(struct iwl_trans *trans, struct sk_buff *skb,
182 struct iwl_tx_cmd *tx_cmd, int txq_id, __le16 fc, bool ampdu,
183 struct iwl_rxon_context *ctx)
184{
185 return trans->ops->tx(trans->priv, skb, tx_cmd, txq_id, fc, ampdu, ctx);
186}
187
188static inline int trans_txq_agg_disable(struct iwl_trans *trans, u16 txq_id,
189 u16 ssn_idx, u8 tx_fifo)
190{
191 return trans->ops->txq_agg_disable(trans->priv, txq_id,
192 ssn_idx, tx_fifo);
193}
194
195static inline void trans_txq_agg_setup(struct iwl_trans *trans, int sta_id,
196 int tid, int frame_limit)
197{
198 trans->ops->txq_agg_setup(trans->priv, sta_id, tid, frame_limit);
199}
200
201static inline void trans_kick_nic(struct iwl_trans *trans)
202{
203 trans->ops->kick_nic(trans->priv);
204}
205
206static inline void trans_sync_irq(struct iwl_trans *trans)
207{
208 trans->ops->sync_irq(trans->priv);
209}
210
211static inline void trans_free(struct iwl_trans *trans)
212{
213 trans->ops->free(trans->priv);
214}
215
216int iwl_trans_register(struct iwl_trans *trans, struct iwl_priv *priv);
217
218/*TODO: this functions should NOT be exported from trans module - export it
219 * until the reclaim flow will be brought to the transport module too */
220
221struct iwl_tx_queue;
222void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
223 struct iwl_tx_queue *txq);
224
225#endif /* __iwl_trans_h__ */
diff --git a/drivers/net/wireless/iwmc3200wifi/fw.c b/drivers/net/wireless/iwmc3200wifi/fw.c
index 49067092d336..6f1afe6bbc8c 100644
--- a/drivers/net/wireless/iwmc3200wifi/fw.c
+++ b/drivers/net/wireless/iwmc3200wifi/fw.c
@@ -187,7 +187,7 @@ static int iwm_load_img(struct iwm_priv *iwm, const char *img_name)
187 if (ret < 0) 187 if (ret < 0)
188 goto err_release_fw; 188 goto err_release_fw;
189 opcode_idx++; 189 opcode_idx++;
190 }; 190 }
191 191
192 /* Read firmware version */ 192 /* Read firmware version */
193 fw_offset = iwm_fw_op_offset(iwm, fw, IWM_HDR_REC_OP_SW_VER, 0); 193 fw_offset = iwm_fw_op_offset(iwm, fw, IWM_HDR_REC_OP_SW_VER, 0);
diff --git a/drivers/net/wireless/libertas/cfg.c b/drivers/net/wireless/libertas/cfg.c
index 5d637af2d7c3..b456a53b64b1 100644
--- a/drivers/net/wireless/libertas/cfg.c
+++ b/drivers/net/wireless/libertas/cfg.c
@@ -8,6 +8,7 @@
8 8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 10
11#include <linux/hardirq.h>
11#include <linux/sched.h> 12#include <linux/sched.h>
12#include <linux/wait.h> 13#include <linux/wait.h>
13#include <linux/slab.h> 14#include <linux/slab.h>
diff --git a/drivers/net/wireless/libertas/cmd.c b/drivers/net/wireless/libertas/cmd.c
index 71c8f3fccfa1..dbd24a4607ec 100644
--- a/drivers/net/wireless/libertas/cmd.c
+++ b/drivers/net/wireless/libertas/cmd.c
@@ -3,6 +3,7 @@
3 * It prepares command and sends it to firmware when it is ready. 3 * It prepares command and sends it to firmware when it is ready.
4 */ 4 */
5 5
6#include <linux/hardirq.h>
6#include <linux/kfifo.h> 7#include <linux/kfifo.h>
7#include <linux/sched.h> 8#include <linux/sched.h>
8#include <linux/slab.h> 9#include <linux/slab.h>
@@ -873,6 +874,7 @@ int lbs_get_reg(struct lbs_private *priv, u16 reg, u16 offset, u32 *value)
873 memset(&cmd, 0, sizeof(cmd)); 874 memset(&cmd, 0, sizeof(cmd));
874 cmd.hdr.size = cpu_to_le16(sizeof(cmd)); 875 cmd.hdr.size = cpu_to_le16(sizeof(cmd));
875 cmd.action = cpu_to_le16(CMD_ACT_GET); 876 cmd.action = cpu_to_le16(CMD_ACT_GET);
877 cmd.offset = cpu_to_le16(offset);
876 878
877 if (reg != CMD_MAC_REG_ACCESS && 879 if (reg != CMD_MAC_REG_ACCESS &&
878 reg != CMD_BBP_REG_ACCESS && 880 reg != CMD_BBP_REG_ACCESS &&
@@ -882,7 +884,7 @@ int lbs_get_reg(struct lbs_private *priv, u16 reg, u16 offset, u32 *value)
882 } 884 }
883 885
884 ret = lbs_cmd_with_response(priv, reg, &cmd); 886 ret = lbs_cmd_with_response(priv, reg, &cmd);
885 if (ret) { 887 if (!ret) {
886 if (reg == CMD_BBP_REG_ACCESS || reg == CMD_RF_REG_ACCESS) 888 if (reg == CMD_BBP_REG_ACCESS || reg == CMD_RF_REG_ACCESS)
887 *value = cmd.value.bbp_rf; 889 *value = cmd.value.bbp_rf;
888 else if (reg == CMD_MAC_REG_ACCESS) 890 else if (reg == CMD_MAC_REG_ACCESS)
@@ -915,6 +917,7 @@ int lbs_set_reg(struct lbs_private *priv, u16 reg, u16 offset, u32 value)
915 memset(&cmd, 0, sizeof(cmd)); 917 memset(&cmd, 0, sizeof(cmd));
916 cmd.hdr.size = cpu_to_le16(sizeof(cmd)); 918 cmd.hdr.size = cpu_to_le16(sizeof(cmd));
917 cmd.action = cpu_to_le16(CMD_ACT_SET); 919 cmd.action = cpu_to_le16(CMD_ACT_SET);
920 cmd.offset = cpu_to_le16(offset);
918 921
919 if (reg == CMD_BBP_REG_ACCESS || reg == CMD_RF_REG_ACCESS) 922 if (reg == CMD_BBP_REG_ACCESS || reg == CMD_RF_REG_ACCESS)
920 cmd.value.bbp_rf = (u8) (value & 0xFF); 923 cmd.value.bbp_rf = (u8) (value & 0xFF);
@@ -1067,16 +1070,34 @@ static void lbs_cleanup_and_insert_cmd(struct lbs_private *priv,
1067 spin_unlock_irqrestore(&priv->driver_lock, flags); 1070 spin_unlock_irqrestore(&priv->driver_lock, flags);
1068} 1071}
1069 1072
1070void lbs_complete_command(struct lbs_private *priv, struct cmd_ctrl_node *cmd, 1073void __lbs_complete_command(struct lbs_private *priv, struct cmd_ctrl_node *cmd,
1071 int result) 1074 int result)
1072{ 1075{
1076 /*
1077 * Normally, commands are removed from cmdpendingq before being
1078 * submitted. However, we can arrive here on alternative codepaths
1079 * where the command is still pending. Make sure the command really
1080 * isn't part of a list at this point.
1081 */
1082 list_del_init(&cmd->list);
1083
1073 cmd->result = result; 1084 cmd->result = result;
1074 cmd->cmdwaitqwoken = 1; 1085 cmd->cmdwaitqwoken = 1;
1075 wake_up_interruptible(&cmd->cmdwait_q); 1086 wake_up(&cmd->cmdwait_q);
1076 1087
1077 if (!cmd->callback || cmd->callback == lbs_cmd_async_callback) 1088 if (!cmd->callback || cmd->callback == lbs_cmd_async_callback)
1078 __lbs_cleanup_and_insert_cmd(priv, cmd); 1089 __lbs_cleanup_and_insert_cmd(priv, cmd);
1079 priv->cur_cmd = NULL; 1090 priv->cur_cmd = NULL;
1091 wake_up_interruptible(&priv->waitq);
1092}
1093
1094void lbs_complete_command(struct lbs_private *priv, struct cmd_ctrl_node *cmd,
1095 int result)
1096{
1097 unsigned long flags;
1098 spin_lock_irqsave(&priv->driver_lock, flags);
1099 __lbs_complete_command(priv, cmd, result);
1100 spin_unlock_irqrestore(&priv->driver_lock, flags);
1080} 1101}
1081 1102
1082int lbs_set_radio(struct lbs_private *priv, u8 preamble, u8 radio_on) 1103int lbs_set_radio(struct lbs_private *priv, u8 preamble, u8 radio_on)
@@ -1248,7 +1269,7 @@ static struct cmd_ctrl_node *lbs_get_free_cmd_node(struct lbs_private *priv)
1248 if (!list_empty(&priv->cmdfreeq)) { 1269 if (!list_empty(&priv->cmdfreeq)) {
1249 tempnode = list_first_entry(&priv->cmdfreeq, 1270 tempnode = list_first_entry(&priv->cmdfreeq,
1250 struct cmd_ctrl_node, list); 1271 struct cmd_ctrl_node, list);
1251 list_del(&tempnode->list); 1272 list_del_init(&tempnode->list);
1252 } else { 1273 } else {
1253 lbs_deb_host("GET_CMD_NODE: cmd_ctrl_node is not available\n"); 1274 lbs_deb_host("GET_CMD_NODE: cmd_ctrl_node is not available\n");
1254 tempnode = NULL; 1275 tempnode = NULL;
@@ -1356,10 +1377,7 @@ int lbs_execute_next_command(struct lbs_private *priv)
1356 cpu_to_le16(PS_MODE_ACTION_EXIT_PS)) { 1377 cpu_to_le16(PS_MODE_ACTION_EXIT_PS)) {
1357 lbs_deb_host( 1378 lbs_deb_host(
1358 "EXEC_NEXT_CMD: ignore ENTER_PS cmd\n"); 1379 "EXEC_NEXT_CMD: ignore ENTER_PS cmd\n");
1359 spin_lock_irqsave(&priv->driver_lock, flags);
1360 list_del(&cmdnode->list);
1361 lbs_complete_command(priv, cmdnode, 0); 1380 lbs_complete_command(priv, cmdnode, 0);
1362 spin_unlock_irqrestore(&priv->driver_lock, flags);
1363 1381
1364 ret = 0; 1382 ret = 0;
1365 goto done; 1383 goto done;
@@ -1369,10 +1387,7 @@ int lbs_execute_next_command(struct lbs_private *priv)
1369 (priv->psstate == PS_STATE_PRE_SLEEP)) { 1387 (priv->psstate == PS_STATE_PRE_SLEEP)) {
1370 lbs_deb_host( 1388 lbs_deb_host(
1371 "EXEC_NEXT_CMD: ignore EXIT_PS cmd in sleep\n"); 1389 "EXEC_NEXT_CMD: ignore EXIT_PS cmd in sleep\n");
1372 spin_lock_irqsave(&priv->driver_lock, flags);
1373 list_del(&cmdnode->list);
1374 lbs_complete_command(priv, cmdnode, 0); 1390 lbs_complete_command(priv, cmdnode, 0);
1375 spin_unlock_irqrestore(&priv->driver_lock, flags);
1376 priv->needtowakeup = 1; 1391 priv->needtowakeup = 1;
1377 1392
1378 ret = 0; 1393 ret = 0;
@@ -1384,7 +1399,7 @@ int lbs_execute_next_command(struct lbs_private *priv)
1384 } 1399 }
1385 } 1400 }
1386 spin_lock_irqsave(&priv->driver_lock, flags); 1401 spin_lock_irqsave(&priv->driver_lock, flags);
1387 list_del(&cmdnode->list); 1402 list_del_init(&cmdnode->list);
1388 spin_unlock_irqrestore(&priv->driver_lock, flags); 1403 spin_unlock_irqrestore(&priv->driver_lock, flags);
1389 lbs_deb_host("EXEC_NEXT_CMD: sending command 0x%04x\n", 1404 lbs_deb_host("EXEC_NEXT_CMD: sending command 0x%04x\n",
1390 le16_to_cpu(cmd->command)); 1405 le16_to_cpu(cmd->command));
@@ -1667,7 +1682,13 @@ int __lbs_cmd(struct lbs_private *priv, uint16_t command,
1667 } 1682 }
1668 1683
1669 might_sleep(); 1684 might_sleep();
1670 wait_event_interruptible(cmdnode->cmdwait_q, cmdnode->cmdwaitqwoken); 1685
1686 /*
1687 * Be careful with signals here. A signal may be received as the system
1688 * goes into suspend or resume. We do not want this to interrupt the
1689 * command, so we perform an uninterruptible sleep.
1690 */
1691 wait_event(cmdnode->cmdwait_q, cmdnode->cmdwaitqwoken);
1671 1692
1672 spin_lock_irqsave(&priv->driver_lock, flags); 1693 spin_lock_irqsave(&priv->driver_lock, flags);
1673 ret = cmdnode->result; 1694 ret = cmdnode->result;
diff --git a/drivers/net/wireless/libertas/cmd.h b/drivers/net/wireless/libertas/cmd.h
index 7109d6b717ea..b280ef7a0aea 100644
--- a/drivers/net/wireless/libertas/cmd.h
+++ b/drivers/net/wireless/libertas/cmd.h
@@ -59,6 +59,8 @@ int lbs_allocate_cmd_buffer(struct lbs_private *priv);
59int lbs_free_cmd_buffer(struct lbs_private *priv); 59int lbs_free_cmd_buffer(struct lbs_private *priv);
60 60
61int lbs_execute_next_command(struct lbs_private *priv); 61int lbs_execute_next_command(struct lbs_private *priv);
62void __lbs_complete_command(struct lbs_private *priv, struct cmd_ctrl_node *cmd,
63 int result);
62void lbs_complete_command(struct lbs_private *priv, struct cmd_ctrl_node *cmd, 64void lbs_complete_command(struct lbs_private *priv, struct cmd_ctrl_node *cmd,
63 int result); 65 int result);
64int lbs_process_command_response(struct lbs_private *priv, u8 *data, u32 len); 66int lbs_process_command_response(struct lbs_private *priv, u8 *data, u32 len);
diff --git a/drivers/net/wireless/libertas/cmdresp.c b/drivers/net/wireless/libertas/cmdresp.c
index 207fc361db84..178b222b3ce1 100644
--- a/drivers/net/wireless/libertas/cmdresp.c
+++ b/drivers/net/wireless/libertas/cmdresp.c
@@ -3,6 +3,7 @@
3 * responses as well as events generated by firmware. 3 * responses as well as events generated by firmware.
4 */ 4 */
5 5
6#include <linux/hardirq.h>
6#include <linux/slab.h> 7#include <linux/slab.h>
7#include <linux/delay.h> 8#include <linux/delay.h>
8#include <linux/sched.h> 9#include <linux/sched.h>
@@ -165,7 +166,7 @@ int lbs_process_command_response(struct lbs_private *priv, u8 *data, u32 len)
165 lbs_deb_host("CMD_RESP: PS action 0x%X\n", action); 166 lbs_deb_host("CMD_RESP: PS action 0x%X\n", action);
166 } 167 }
167 168
168 lbs_complete_command(priv, priv->cur_cmd, result); 169 __lbs_complete_command(priv, priv->cur_cmd, result);
169 spin_unlock_irqrestore(&priv->driver_lock, flags); 170 spin_unlock_irqrestore(&priv->driver_lock, flags);
170 171
171 ret = 0; 172 ret = 0;
@@ -186,7 +187,7 @@ int lbs_process_command_response(struct lbs_private *priv, u8 *data, u32 len)
186 break; 187 break;
187 188
188 } 189 }
189 lbs_complete_command(priv, priv->cur_cmd, result); 190 __lbs_complete_command(priv, priv->cur_cmd, result);
190 spin_unlock_irqrestore(&priv->driver_lock, flags); 191 spin_unlock_irqrestore(&priv->driver_lock, flags);
191 192
192 ret = -1; 193 ret = -1;
@@ -204,7 +205,7 @@ int lbs_process_command_response(struct lbs_private *priv, u8 *data, u32 len)
204 205
205 if (priv->cur_cmd) { 206 if (priv->cur_cmd) {
206 /* Clean up and Put current command back to cmdfreeq */ 207 /* Clean up and Put current command back to cmdfreeq */
207 lbs_complete_command(priv, priv->cur_cmd, result); 208 __lbs_complete_command(priv, priv->cur_cmd, result);
208 } 209 }
209 spin_unlock_irqrestore(&priv->driver_lock, flags); 210 spin_unlock_irqrestore(&priv->driver_lock, flags);
210 211
diff --git a/drivers/net/wireless/libertas/debugfs.c b/drivers/net/wireless/libertas/debugfs.c
index 23250f621761..1af182778844 100644
--- a/drivers/net/wireless/libertas/debugfs.c
+++ b/drivers/net/wireless/libertas/debugfs.c
@@ -1,6 +1,7 @@
1#include <linux/dcache.h> 1#include <linux/dcache.h>
2#include <linux/debugfs.h> 2#include <linux/debugfs.h>
3#include <linux/delay.h> 3#include <linux/delay.h>
4#include <linux/hardirq.h>
4#include <linux/mm.h> 5#include <linux/mm.h>
5#include <linux/string.h> 6#include <linux/string.h>
6#include <linux/slab.h> 7#include <linux/slab.h>
diff --git a/drivers/net/wireless/libertas/dev.h b/drivers/net/wireless/libertas/dev.h
index 76d018beebf4..adb3490e3cf5 100644
--- a/drivers/net/wireless/libertas/dev.h
+++ b/drivers/net/wireless/libertas/dev.h
@@ -44,9 +44,7 @@ struct lbs_private {
44 /* Mesh */ 44 /* Mesh */
45 struct net_device *mesh_dev; /* Virtual device */ 45 struct net_device *mesh_dev; /* Virtual device */
46#ifdef CONFIG_LIBERTAS_MESH 46#ifdef CONFIG_LIBERTAS_MESH
47 u32 mesh_connect_status;
48 struct lbs_mesh_stats mstats; 47 struct lbs_mesh_stats mstats;
49 int mesh_open;
50 uint16_t mesh_tlv; 48 uint16_t mesh_tlv;
51 u8 mesh_ssid[IEEE80211_MAX_SSID_LEN + 1]; 49 u8 mesh_ssid[IEEE80211_MAX_SSID_LEN + 1];
52 u8 mesh_ssid_len; 50 u8 mesh_ssid_len;
diff --git a/drivers/net/wireless/libertas/ethtool.c b/drivers/net/wireless/libertas/ethtool.c
index 29dbce4a9f86..4dfb3bfd2cf3 100644
--- a/drivers/net/wireless/libertas/ethtool.c
+++ b/drivers/net/wireless/libertas/ethtool.c
@@ -1,3 +1,4 @@
1#include <linux/hardirq.h>
1#include <linux/netdevice.h> 2#include <linux/netdevice.h>
2#include <linux/ethtool.h> 3#include <linux/ethtool.h>
3#include <linux/delay.h> 4#include <linux/delay.h>
diff --git a/drivers/net/wireless/libertas/if_sdio.c b/drivers/net/wireless/libertas/if_sdio.c
index 224e9853c480..387786e1b394 100644
--- a/drivers/net/wireless/libertas/if_sdio.c
+++ b/drivers/net/wireless/libertas/if_sdio.c
@@ -892,6 +892,37 @@ static int if_sdio_reset_deep_sleep_wakeup(struct lbs_private *priv)
892 892
893} 893}
894 894
895static struct mmc_host *reset_host;
896
897static void if_sdio_reset_card_worker(struct work_struct *work)
898{
899 /*
900 * The actual reset operation must be run outside of lbs_thread. This
901 * is because mmc_remove_host() will cause the device to be instantly
902 * destroyed, and the libertas driver then needs to end lbs_thread,
903 * leading to a deadlock.
904 *
905 * We run it in a workqueue totally independent from the if_sdio_card
906 * instance for that reason.
907 */
908
909 pr_info("Resetting card...");
910 mmc_remove_host(reset_host);
911 mmc_add_host(reset_host);
912}
913static DECLARE_WORK(card_reset_work, if_sdio_reset_card_worker);
914
915static void if_sdio_reset_card(struct lbs_private *priv)
916{
917 struct if_sdio_card *card = priv->card;
918
919 if (work_pending(&card_reset_work))
920 return;
921
922 reset_host = card->func->card->host;
923 schedule_work(&card_reset_work);
924}
925
895/*******************************************************************/ 926/*******************************************************************/
896/* SDIO callbacks */ 927/* SDIO callbacks */
897/*******************************************************************/ 928/*******************************************************************/
@@ -1065,6 +1096,7 @@ static int if_sdio_probe(struct sdio_func *func,
1065 priv->enter_deep_sleep = if_sdio_enter_deep_sleep; 1096 priv->enter_deep_sleep = if_sdio_enter_deep_sleep;
1066 priv->exit_deep_sleep = if_sdio_exit_deep_sleep; 1097 priv->exit_deep_sleep = if_sdio_exit_deep_sleep;
1067 priv->reset_deep_sleep_wakeup = if_sdio_reset_deep_sleep_wakeup; 1098 priv->reset_deep_sleep_wakeup = if_sdio_reset_deep_sleep_wakeup;
1099 priv->reset_card = if_sdio_reset_card;
1068 1100
1069 sdio_claim_host(func); 1101 sdio_claim_host(func);
1070 1102
@@ -1301,6 +1333,8 @@ static void __exit if_sdio_exit_module(void)
1301 /* Set the flag as user is removing this module. */ 1333 /* Set the flag as user is removing this module. */
1302 user_rmmod = 1; 1334 user_rmmod = 1;
1303 1335
1336 cancel_work_sync(&card_reset_work);
1337
1304 sdio_unregister_driver(&if_sdio_driver); 1338 sdio_unregister_driver(&if_sdio_driver);
1305 1339
1306 lbs_deb_leave(LBS_DEB_SDIO); 1340 lbs_deb_leave(LBS_DEB_SDIO);
diff --git a/drivers/net/wireless/libertas/if_spi.c b/drivers/net/wireless/libertas/if_spi.c
index 463352c890d7..e0286cfbc91d 100644
--- a/drivers/net/wireless/libertas/if_spi.c
+++ b/drivers/net/wireless/libertas/if_spi.c
@@ -19,6 +19,8 @@
19 19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21 21
22#include <linux/hardirq.h>
23#include <linux/interrupt.h>
22#include <linux/moduleparam.h> 24#include <linux/moduleparam.h>
23#include <linux/firmware.h> 25#include <linux/firmware.h>
24#include <linux/jiffies.h> 26#include <linux/jiffies.h>
@@ -1032,7 +1034,6 @@ static irqreturn_t if_spi_host_interrupt(int irq, void *dev_id)
1032static int if_spi_init_card(struct if_spi_card *card) 1034static int if_spi_init_card(struct if_spi_card *card)
1033{ 1035{
1034 struct lbs_private *priv = card->priv; 1036 struct lbs_private *priv = card->priv;
1035 struct spi_device *spi = card->spi;
1036 int err, i; 1037 int err, i;
1037 u32 scratch; 1038 u32 scratch;
1038 const struct firmware *helper = NULL; 1039 const struct firmware *helper = NULL;
@@ -1080,8 +1081,9 @@ static int if_spi_init_card(struct if_spi_card *card)
1080 "attached to SPI bus_num %d, chip_select %d. " 1081 "attached to SPI bus_num %d, chip_select %d. "
1081 "spi->max_speed_hz=%d\n", 1082 "spi->max_speed_hz=%d\n",
1082 card->card_id, card->card_rev, 1083 card->card_id, card->card_rev,
1083 spi->master->bus_num, spi->chip_select, 1084 card->spi->master->bus_num,
1084 spi->max_speed_hz); 1085 card->spi->chip_select,
1086 card->spi->max_speed_hz);
1085 err = if_spi_prog_helper_firmware(card, helper); 1087 err = if_spi_prog_helper_firmware(card, helper);
1086 if (err) 1088 if (err)
1087 goto out; 1089 goto out;
diff --git a/drivers/net/wireless/libertas/main.c b/drivers/net/wireless/libertas/main.c
index 8c40949cb076..94652c5a25de 100644
--- a/drivers/net/wireless/libertas/main.c
+++ b/drivers/net/wireless/libertas/main.c
@@ -9,6 +9,7 @@
9#include <linux/moduleparam.h> 9#include <linux/moduleparam.h>
10#include <linux/delay.h> 10#include <linux/delay.h>
11#include <linux/etherdevice.h> 11#include <linux/etherdevice.h>
12#include <linux/hardirq.h>
12#include <linux/netdevice.h> 13#include <linux/netdevice.h>
13#include <linux/if_arp.h> 14#include <linux/if_arp.h>
14#include <linux/kthread.h> 15#include <linux/kthread.h>
@@ -511,7 +512,7 @@ static int lbs_thread(void *data)
511 if (priv->connect_status == LBS_CONNECTED) 512 if (priv->connect_status == LBS_CONNECTED)
512 netif_wake_queue(priv->dev); 513 netif_wake_queue(priv->dev);
513 if (priv->mesh_dev && 514 if (priv->mesh_dev &&
514 lbs_mesh_connected(priv)) 515 netif_running(priv->mesh_dev))
515 netif_wake_queue(priv->mesh_dev); 516 netif_wake_queue(priv->mesh_dev);
516 } 517 }
517 } 518 }
@@ -638,6 +639,14 @@ static void lbs_cmd_timeout_handler(unsigned long data)
638 le16_to_cpu(priv->cur_cmd->cmdbuf->command)); 639 le16_to_cpu(priv->cur_cmd->cmdbuf->command));
639 640
640 priv->cmd_timed_out = 1; 641 priv->cmd_timed_out = 1;
642
643 /*
644 * If the device didn't even acknowledge the command, reset the state
645 * so that we don't block all future commands due to this one timeout.
646 */
647 if (priv->dnld_sent == DNLD_CMD_SENT)
648 priv->dnld_sent = DNLD_RES_RECEIVED;
649
641 wake_up_interruptible(&priv->waitq); 650 wake_up_interruptible(&priv->waitq);
642out: 651out:
643 spin_unlock_irqrestore(&priv->driver_lock, flags); 652 spin_unlock_irqrestore(&priv->driver_lock, flags);
@@ -994,7 +1003,7 @@ void lbs_stop_card(struct lbs_private *priv)
994 list_for_each_entry(cmdnode, &priv->cmdpendingq, list) { 1003 list_for_each_entry(cmdnode, &priv->cmdpendingq, list) {
995 cmdnode->result = -ENOENT; 1004 cmdnode->result = -ENOENT;
996 cmdnode->cmdwaitqwoken = 1; 1005 cmdnode->cmdwaitqwoken = 1;
997 wake_up_interruptible(&cmdnode->cmdwait_q); 1006 wake_up(&cmdnode->cmdwait_q);
998 } 1007 }
999 1008
1000 /* Flush the command the card is currently processing */ 1009 /* Flush the command the card is currently processing */
@@ -1002,7 +1011,7 @@ void lbs_stop_card(struct lbs_private *priv)
1002 lbs_deb_main("clearing current command\n"); 1011 lbs_deb_main("clearing current command\n");
1003 priv->cur_cmd->result = -ENOENT; 1012 priv->cur_cmd->result = -ENOENT;
1004 priv->cur_cmd->cmdwaitqwoken = 1; 1013 priv->cur_cmd->cmdwaitqwoken = 1;
1005 wake_up_interruptible(&priv->cur_cmd->cmdwait_q); 1014 wake_up(&priv->cur_cmd->cmdwait_q);
1006 } 1015 }
1007 lbs_deb_main("done clearing commands\n"); 1016 lbs_deb_main("done clearing commands\n");
1008 spin_unlock_irqrestore(&priv->driver_lock, flags); 1017 spin_unlock_irqrestore(&priv->driver_lock, flags);
diff --git a/drivers/net/wireless/libertas/mesh.c b/drivers/net/wireless/libertas/mesh.c
index 24cf06680c6b..be72c08ea2a7 100644
--- a/drivers/net/wireless/libertas/mesh.c
+++ b/drivers/net/wireless/libertas/mesh.c
@@ -2,6 +2,7 @@
2 2
3#include <linux/delay.h> 3#include <linux/delay.h>
4#include <linux/etherdevice.h> 4#include <linux/etherdevice.h>
5#include <linux/hardirq.h>
5#include <linux/netdevice.h> 6#include <linux/netdevice.h>
6#include <linux/if_ether.h> 7#include <linux/if_ether.h>
7#include <linux/if_arp.h> 8#include <linux/if_arp.h>
@@ -14,6 +15,121 @@
14#include "cmd.h" 15#include "cmd.h"
15 16
16 17
18static int lbs_add_mesh(struct lbs_private *priv);
19
20/***************************************************************************
21 * Mesh command handling
22 */
23
24static int lbs_mesh_access(struct lbs_private *priv, uint16_t cmd_action,
25 struct cmd_ds_mesh_access *cmd)
26{
27 int ret;
28
29 lbs_deb_enter_args(LBS_DEB_CMD, "action %d", cmd_action);
30
31 cmd->hdr.command = cpu_to_le16(CMD_MESH_ACCESS);
32 cmd->hdr.size = cpu_to_le16(sizeof(*cmd));
33 cmd->hdr.result = 0;
34
35 cmd->action = cpu_to_le16(cmd_action);
36
37 ret = lbs_cmd_with_response(priv, CMD_MESH_ACCESS, cmd);
38
39 lbs_deb_leave(LBS_DEB_CMD);
40 return ret;
41}
42
43static int __lbs_mesh_config_send(struct lbs_private *priv,
44 struct cmd_ds_mesh_config *cmd,
45 uint16_t action, uint16_t type)
46{
47 int ret;
48 u16 command = CMD_MESH_CONFIG_OLD;
49
50 lbs_deb_enter(LBS_DEB_CMD);
51
52 /*
53 * Command id is 0xac for v10 FW along with mesh interface
54 * id in bits 14-13-12.
55 */
56 if (priv->mesh_tlv == TLV_TYPE_MESH_ID)
57 command = CMD_MESH_CONFIG |
58 (MESH_IFACE_ID << MESH_IFACE_BIT_OFFSET);
59
60 cmd->hdr.command = cpu_to_le16(command);
61 cmd->hdr.size = cpu_to_le16(sizeof(struct cmd_ds_mesh_config));
62 cmd->hdr.result = 0;
63
64 cmd->type = cpu_to_le16(type);
65 cmd->action = cpu_to_le16(action);
66
67 ret = lbs_cmd_with_response(priv, command, cmd);
68
69 lbs_deb_leave(LBS_DEB_CMD);
70 return ret;
71}
72
73static int lbs_mesh_config_send(struct lbs_private *priv,
74 struct cmd_ds_mesh_config *cmd,
75 uint16_t action, uint16_t type)
76{
77 int ret;
78
79 if (!(priv->fwcapinfo & FW_CAPINFO_PERSISTENT_CONFIG))
80 return -EOPNOTSUPP;
81
82 ret = __lbs_mesh_config_send(priv, cmd, action, type);
83 return ret;
84}
85
86/* This function is the CMD_MESH_CONFIG legacy function. It only handles the
87 * START and STOP actions. The extended actions supported by CMD_MESH_CONFIG
88 * are all handled by preparing a struct cmd_ds_mesh_config and passing it to
89 * lbs_mesh_config_send.
90 */
91static int lbs_mesh_config(struct lbs_private *priv, uint16_t action,
92 uint16_t chan)
93{
94 struct cmd_ds_mesh_config cmd;
95 struct mrvl_meshie *ie;
96 DECLARE_SSID_BUF(ssid);
97
98 memset(&cmd, 0, sizeof(cmd));
99 cmd.channel = cpu_to_le16(chan);
100 ie = (struct mrvl_meshie *)cmd.data;
101
102 switch (action) {
103 case CMD_ACT_MESH_CONFIG_START:
104 ie->id = WLAN_EID_GENERIC;
105 ie->val.oui[0] = 0x00;
106 ie->val.oui[1] = 0x50;
107 ie->val.oui[2] = 0x43;
108 ie->val.type = MARVELL_MESH_IE_TYPE;
109 ie->val.subtype = MARVELL_MESH_IE_SUBTYPE;
110 ie->val.version = MARVELL_MESH_IE_VERSION;
111 ie->val.active_protocol_id = MARVELL_MESH_PROTO_ID_HWMP;
112 ie->val.active_metric_id = MARVELL_MESH_METRIC_ID;
113 ie->val.mesh_capability = MARVELL_MESH_CAPABILITY;
114 ie->val.mesh_id_len = priv->mesh_ssid_len;
115 memcpy(ie->val.mesh_id, priv->mesh_ssid, priv->mesh_ssid_len);
116 ie->len = sizeof(struct mrvl_meshie_val) -
117 IEEE80211_MAX_SSID_LEN + priv->mesh_ssid_len;
118 cmd.length = cpu_to_le16(sizeof(struct mrvl_meshie_val));
119 break;
120 case CMD_ACT_MESH_CONFIG_STOP:
121 break;
122 default:
123 return -1;
124 }
125 lbs_deb_cmd("mesh config action %d type %x channel %d SSID %s\n",
126 action, priv->mesh_tlv, chan,
127 print_ssid(ssid, priv->mesh_ssid, priv->mesh_ssid_len));
128
129 return __lbs_mesh_config_send(priv, &cmd, action, priv->mesh_tlv);
130}
131
132
17/*************************************************************************** 133/***************************************************************************
18 * Mesh sysfs support 134 * Mesh sysfs support
19 */ 135 */
@@ -154,17 +270,11 @@ static ssize_t lbs_mesh_set(struct device *dev,
154{ 270{
155 struct lbs_private *priv = to_net_dev(dev)->ml_priv; 271 struct lbs_private *priv = to_net_dev(dev)->ml_priv;
156 int enable; 272 int enable;
157 int ret, action = CMD_ACT_MESH_CONFIG_STOP;
158 273
159 sscanf(buf, "%x", &enable); 274 sscanf(buf, "%x", &enable);
160 enable = !!enable; 275 enable = !!enable;
161 if (enable == !!priv->mesh_dev) 276 if (enable == !!priv->mesh_dev)
162 return count; 277 return count;
163 if (enable)
164 action = CMD_ACT_MESH_CONFIG_START;
165 ret = lbs_mesh_config(priv, action, priv->channel);
166 if (ret)
167 return ret;
168 278
169 if (enable) 279 if (enable)
170 lbs_add_mesh(priv); 280 lbs_add_mesh(priv);
@@ -199,582 +309,11 @@ static struct attribute *lbs_mesh_sysfs_entries[] = {
199 NULL, 309 NULL,
200}; 310};
201 311
202static struct attribute_group lbs_mesh_attr_group = { 312static const struct attribute_group lbs_mesh_attr_group = {
203 .attrs = lbs_mesh_sysfs_entries, 313 .attrs = lbs_mesh_sysfs_entries,
204}; 314};
205 315
206 316
207
208/***************************************************************************
209 * Initializing and starting, stopping mesh
210 */
211
212/*
213 * Check mesh FW version and appropriately send the mesh start
214 * command
215 */
216int lbs_init_mesh(struct lbs_private *priv)
217{
218 struct net_device *dev = priv->dev;
219 int ret = 0;
220
221 lbs_deb_enter(LBS_DEB_MESH);
222
223 priv->mesh_connect_status = LBS_DISCONNECTED;
224
225 /* Determine mesh_fw_ver from fwrelease and fwcapinfo */
226 /* 5.0.16p0 9.0.0.p0 is known to NOT support any mesh */
227 /* 5.110.22 have mesh command with 0xa3 command id */
228 /* 10.0.0.p0 FW brings in mesh config command with different id */
229 /* Check FW version MSB and initialize mesh_fw_ver */
230 if (MRVL_FW_MAJOR_REV(priv->fwrelease) == MRVL_FW_V5) {
231 /* Enable mesh, if supported, and work out which TLV it uses.
232 0x100 + 291 is an unofficial value used in 5.110.20.pXX
233 0x100 + 37 is the official value used in 5.110.21.pXX
234 but we check them in that order because 20.pXX doesn't
235 give an error -- it just silently fails. */
236
237 /* 5.110.20.pXX firmware will fail the command if the channel
238 doesn't match the existing channel. But only if the TLV
239 is correct. If the channel is wrong, _BOTH_ versions will
240 give an error to 0x100+291, and allow 0x100+37 to succeed.
241 It's just that 5.110.20.pXX will not have done anything
242 useful */
243
244 priv->mesh_tlv = TLV_TYPE_OLD_MESH_ID;
245 if (lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
246 priv->channel)) {
247 priv->mesh_tlv = TLV_TYPE_MESH_ID;
248 if (lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
249 priv->channel))
250 priv->mesh_tlv = 0;
251 }
252 } else
253 if ((MRVL_FW_MAJOR_REV(priv->fwrelease) >= MRVL_FW_V10) &&
254 (priv->fwcapinfo & MESH_CAPINFO_ENABLE_MASK)) {
255 /* 10.0.0.pXX new firmwares should succeed with TLV
256 * 0x100+37; Do not invoke command with old TLV.
257 */
258 priv->mesh_tlv = TLV_TYPE_MESH_ID;
259 if (lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
260 priv->channel))
261 priv->mesh_tlv = 0;
262 }
263
264
265 if (priv->mesh_tlv) {
266 sprintf(priv->mesh_ssid, "mesh");
267 priv->mesh_ssid_len = 4;
268
269 lbs_add_mesh(priv);
270
271 if (device_create_file(&dev->dev, &dev_attr_lbs_mesh))
272 netdev_err(dev, "cannot register lbs_mesh attribute\n");
273
274 ret = 1;
275 }
276
277 lbs_deb_leave_args(LBS_DEB_MESH, "ret %d", ret);
278 return ret;
279}
280
281
282int lbs_deinit_mesh(struct lbs_private *priv)
283{
284 struct net_device *dev = priv->dev;
285 int ret = 0;
286
287 lbs_deb_enter(LBS_DEB_MESH);
288
289 if (priv->mesh_tlv) {
290 device_remove_file(&dev->dev, &dev_attr_lbs_mesh);
291 ret = 1;
292 }
293
294 lbs_deb_leave_args(LBS_DEB_MESH, "ret %d", ret);
295 return ret;
296}
297
298
299/**
300 * lbs_mesh_stop - close the mshX interface
301 *
302 * @dev: A pointer to &net_device structure
303 * returns: 0
304 */
305static int lbs_mesh_stop(struct net_device *dev)
306{
307 struct lbs_private *priv = dev->ml_priv;
308
309 lbs_deb_enter(LBS_DEB_MESH);
310 spin_lock_irq(&priv->driver_lock);
311
312 priv->mesh_open = 0;
313 priv->mesh_connect_status = LBS_DISCONNECTED;
314
315 netif_stop_queue(dev);
316 netif_carrier_off(dev);
317
318 spin_unlock_irq(&priv->driver_lock);
319
320 schedule_work(&priv->mcast_work);
321
322 lbs_deb_leave(LBS_DEB_MESH);
323 return 0;
324}
325
326/**
327 * lbs_mesh_dev_open - open the mshX interface
328 *
329 * @dev: A pointer to &net_device structure
330 * returns: 0 or -EBUSY if monitor mode active
331 */
332static int lbs_mesh_dev_open(struct net_device *dev)
333{
334 struct lbs_private *priv = dev->ml_priv;
335 int ret = 0;
336
337 lbs_deb_enter(LBS_DEB_NET);
338
339 spin_lock_irq(&priv->driver_lock);
340
341 if (priv->wdev->iftype == NL80211_IFTYPE_MONITOR) {
342 ret = -EBUSY;
343 goto out;
344 }
345
346 priv->mesh_open = 1;
347 priv->mesh_connect_status = LBS_CONNECTED;
348 netif_carrier_on(dev);
349
350 if (!priv->tx_pending_len)
351 netif_wake_queue(dev);
352 out:
353
354 spin_unlock_irq(&priv->driver_lock);
355 lbs_deb_leave_args(LBS_DEB_NET, "ret %d", ret);
356 return ret;
357}
358
359static const struct net_device_ops mesh_netdev_ops = {
360 .ndo_open = lbs_mesh_dev_open,
361 .ndo_stop = lbs_mesh_stop,
362 .ndo_start_xmit = lbs_hard_start_xmit,
363 .ndo_set_mac_address = lbs_set_mac_address,
364 .ndo_set_multicast_list = lbs_set_multicast_list,
365};
366
367/**
368 * lbs_add_mesh - add mshX interface
369 *
370 * @priv: A pointer to the &struct lbs_private structure
371 * returns: 0 if successful, -X otherwise
372 */
373int lbs_add_mesh(struct lbs_private *priv)
374{
375 struct net_device *mesh_dev = NULL;
376 int ret = 0;
377
378 lbs_deb_enter(LBS_DEB_MESH);
379
380 /* Allocate a virtual mesh device */
381 mesh_dev = alloc_netdev(0, "msh%d", ether_setup);
382 if (!mesh_dev) {
383 lbs_deb_mesh("init mshX device failed\n");
384 ret = -ENOMEM;
385 goto done;
386 }
387 mesh_dev->ml_priv = priv;
388 priv->mesh_dev = mesh_dev;
389
390 mesh_dev->netdev_ops = &mesh_netdev_ops;
391 mesh_dev->ethtool_ops = &lbs_ethtool_ops;
392 memcpy(mesh_dev->dev_addr, priv->dev->dev_addr, ETH_ALEN);
393
394 SET_NETDEV_DEV(priv->mesh_dev, priv->dev->dev.parent);
395
396 mesh_dev->flags |= IFF_BROADCAST | IFF_MULTICAST;
397 /* Register virtual mesh interface */
398 ret = register_netdev(mesh_dev);
399 if (ret) {
400 pr_err("cannot register mshX virtual interface\n");
401 goto err_free;
402 }
403
404 ret = sysfs_create_group(&(mesh_dev->dev.kobj), &lbs_mesh_attr_group);
405 if (ret)
406 goto err_unregister;
407
408 lbs_persist_config_init(mesh_dev);
409
410 /* Everything successful */
411 ret = 0;
412 goto done;
413
414err_unregister:
415 unregister_netdev(mesh_dev);
416
417err_free:
418 free_netdev(mesh_dev);
419
420done:
421 lbs_deb_leave_args(LBS_DEB_MESH, "ret %d", ret);
422 return ret;
423}
424
425void lbs_remove_mesh(struct lbs_private *priv)
426{
427 struct net_device *mesh_dev;
428
429 mesh_dev = priv->mesh_dev;
430 if (!mesh_dev)
431 return;
432
433 lbs_deb_enter(LBS_DEB_MESH);
434 netif_stop_queue(mesh_dev);
435 netif_carrier_off(mesh_dev);
436 sysfs_remove_group(&(mesh_dev->dev.kobj), &lbs_mesh_attr_group);
437 lbs_persist_config_remove(mesh_dev);
438 unregister_netdev(mesh_dev);
439 priv->mesh_dev = NULL;
440 free_netdev(mesh_dev);
441 lbs_deb_leave(LBS_DEB_MESH);
442}
443
444
445
446/***************************************************************************
447 * Sending and receiving
448 */
449struct net_device *lbs_mesh_set_dev(struct lbs_private *priv,
450 struct net_device *dev, struct rxpd *rxpd)
451{
452 if (priv->mesh_dev) {
453 if (priv->mesh_tlv == TLV_TYPE_OLD_MESH_ID) {
454 if (rxpd->rx_control & RxPD_MESH_FRAME)
455 dev = priv->mesh_dev;
456 } else if (priv->mesh_tlv == TLV_TYPE_MESH_ID) {
457 if (rxpd->u.bss.bss_num == MESH_IFACE_ID)
458 dev = priv->mesh_dev;
459 }
460 }
461 return dev;
462}
463
464
465void lbs_mesh_set_txpd(struct lbs_private *priv,
466 struct net_device *dev, struct txpd *txpd)
467{
468 if (dev == priv->mesh_dev) {
469 if (priv->mesh_tlv == TLV_TYPE_OLD_MESH_ID)
470 txpd->tx_control |= cpu_to_le32(TxPD_MESH_FRAME);
471 else if (priv->mesh_tlv == TLV_TYPE_MESH_ID)
472 txpd->u.bss.bss_num = MESH_IFACE_ID;
473 }
474}
475
476
477/***************************************************************************
478 * Mesh command handling
479 */
480
481/**
482 * lbs_mesh_bt_add_del - Add or delete Mesh Blinding Table entries
483 *
484 * @priv: A pointer to &struct lbs_private structure
485 * @add: TRUE to add the entry, FALSE to delete it
486 * @addr1: Destination address to blind or unblind
487 *
488 * returns: 0 on success, error on failure
489 */
490int lbs_mesh_bt_add_del(struct lbs_private *priv, bool add, u8 *addr1)
491{
492 struct cmd_ds_bt_access cmd;
493 int ret = 0;
494
495 lbs_deb_enter(LBS_DEB_CMD);
496
497 BUG_ON(addr1 == NULL);
498
499 memset(&cmd, 0, sizeof(cmd));
500 cmd.hdr.size = cpu_to_le16(sizeof(cmd));
501 memcpy(cmd.addr1, addr1, ETH_ALEN);
502 if (add) {
503 cmd.action = cpu_to_le16(CMD_ACT_BT_ACCESS_ADD);
504 lbs_deb_hex(LBS_DEB_MESH, "BT_ADD: blinded MAC addr",
505 addr1, ETH_ALEN);
506 } else {
507 cmd.action = cpu_to_le16(CMD_ACT_BT_ACCESS_DEL);
508 lbs_deb_hex(LBS_DEB_MESH, "BT_DEL: blinded MAC addr",
509 addr1, ETH_ALEN);
510 }
511
512 ret = lbs_cmd_with_response(priv, CMD_BT_ACCESS, &cmd);
513
514 lbs_deb_leave_args(LBS_DEB_CMD, "ret %d", ret);
515 return ret;
516}
517
518/**
519 * lbs_mesh_bt_reset - Reset/clear the mesh blinding table
520 *
521 * @priv: A pointer to &struct lbs_private structure
522 *
523 * returns: 0 on success, error on failure
524 */
525int lbs_mesh_bt_reset(struct lbs_private *priv)
526{
527 struct cmd_ds_bt_access cmd;
528 int ret = 0;
529
530 lbs_deb_enter(LBS_DEB_CMD);
531
532 memset(&cmd, 0, sizeof(cmd));
533 cmd.hdr.size = cpu_to_le16(sizeof(cmd));
534 cmd.action = cpu_to_le16(CMD_ACT_BT_ACCESS_RESET);
535
536 ret = lbs_cmd_with_response(priv, CMD_BT_ACCESS, &cmd);
537
538 lbs_deb_leave_args(LBS_DEB_CMD, "ret %d", ret);
539 return ret;
540}
541
542/**
543 * lbs_mesh_bt_get_inverted - Gets the inverted status of the mesh
544 * blinding table
545 *
546 * Normally the firmware "blinds" or ignores traffic from mesh nodes in the
547 * table, but an inverted table allows *only* traffic from nodes listed in
548 * the table.
549 *
550 * @priv: A pointer to &struct lbs_private structure
551 * @inverted: On success, TRUE if the blinding table is inverted,
552 * FALSE if it is not inverted
553 *
554 * returns: 0 on success, error on failure
555 */
556int lbs_mesh_bt_get_inverted(struct lbs_private *priv, bool *inverted)
557{
558 struct cmd_ds_bt_access cmd;
559 int ret = 0;
560
561 lbs_deb_enter(LBS_DEB_CMD);
562
563 BUG_ON(inverted == NULL);
564
565 memset(&cmd, 0, sizeof(cmd));
566 cmd.hdr.size = cpu_to_le16(sizeof(cmd));
567 cmd.action = cpu_to_le16(CMD_ACT_BT_ACCESS_GET_INVERT);
568
569 ret = lbs_cmd_with_response(priv, CMD_BT_ACCESS, &cmd);
570 if (ret == 0)
571 *inverted = !!cmd.id;
572
573 lbs_deb_leave_args(LBS_DEB_CMD, "ret %d", ret);
574 return ret;
575}
576
577/**
578 * lbs_mesh_bt_set_inverted - Sets the inverted status of the mesh
579 * blinding table
580 *
581 * Normally the firmware "blinds" or ignores traffic from mesh nodes in the
582 * table, but an inverted table allows *only* traffic from nodes listed in
583 * the table.
584 *
585 * @priv: A pointer to &struct lbs_private structure
586 * @inverted: TRUE to invert the blinding table (only traffic from
587 * listed nodes allowed), FALSE to return it
588 * to normal state (listed nodes ignored)
589 *
590 * returns: 0 on success, error on failure
591 */
592int lbs_mesh_bt_set_inverted(struct lbs_private *priv, bool inverted)
593{
594 struct cmd_ds_bt_access cmd;
595 int ret = 0;
596
597 lbs_deb_enter(LBS_DEB_CMD);
598
599 memset(&cmd, 0, sizeof(cmd));
600 cmd.hdr.size = cpu_to_le16(sizeof(cmd));
601 cmd.action = cpu_to_le16(CMD_ACT_BT_ACCESS_SET_INVERT);
602 cmd.id = cpu_to_le32(!!inverted);
603
604 ret = lbs_cmd_with_response(priv, CMD_BT_ACCESS, &cmd);
605
606 lbs_deb_leave_args(LBS_DEB_CMD, "ret %d", ret);
607 return ret;
608}
609
610/**
611 * lbs_mesh_bt_get_entry - List an entry in the mesh blinding table
612 *
613 * @priv: A pointer to &struct lbs_private structure
614 * @id: The ID of the entry to list
615 * @addr1: MAC address associated with the table entry
616 *
617 * returns: 0 on success, error on failure
618 */
619int lbs_mesh_bt_get_entry(struct lbs_private *priv, u32 id, u8 *addr1)
620{
621 struct cmd_ds_bt_access cmd;
622 int ret = 0;
623
624 lbs_deb_enter(LBS_DEB_CMD);
625
626 BUG_ON(addr1 == NULL);
627
628 memset(&cmd, 0, sizeof(cmd));
629 cmd.hdr.size = cpu_to_le16(sizeof(cmd));
630 cmd.action = cpu_to_le16(CMD_ACT_BT_ACCESS_SET_INVERT);
631 cmd.id = cpu_to_le32(id);
632
633 ret = lbs_cmd_with_response(priv, CMD_BT_ACCESS, &cmd);
634 if (ret == 0)
635 memcpy(addr1, cmd.addr1, sizeof(cmd.addr1));
636
637 lbs_deb_leave_args(LBS_DEB_CMD, "ret %d", ret);
638 return ret;
639}
640
641/**
642 * lbs_cmd_fwt_access - Access the mesh forwarding table
643 *
644 * @priv: A pointer to &struct lbs_private structure
645 * @cmd_action: The forwarding table action to perform
646 * @cmd: The pre-filled FWT_ACCESS command
647 *
648 * returns: 0 on success and 'cmd' will be filled with the
649 * firmware's response
650 */
651int lbs_cmd_fwt_access(struct lbs_private *priv, u16 cmd_action,
652 struct cmd_ds_fwt_access *cmd)
653{
654 int ret;
655
656 lbs_deb_enter_args(LBS_DEB_CMD, "action %d", cmd_action);
657
658 cmd->hdr.command = cpu_to_le16(CMD_FWT_ACCESS);
659 cmd->hdr.size = cpu_to_le16(sizeof(struct cmd_ds_fwt_access));
660 cmd->hdr.result = 0;
661 cmd->action = cpu_to_le16(cmd_action);
662
663 ret = lbs_cmd_with_response(priv, CMD_FWT_ACCESS, cmd);
664
665 lbs_deb_leave_args(LBS_DEB_CMD, "ret %d", ret);
666 return 0;
667}
668
669int lbs_mesh_access(struct lbs_private *priv, uint16_t cmd_action,
670 struct cmd_ds_mesh_access *cmd)
671{
672 int ret;
673
674 lbs_deb_enter_args(LBS_DEB_CMD, "action %d", cmd_action);
675
676 cmd->hdr.command = cpu_to_le16(CMD_MESH_ACCESS);
677 cmd->hdr.size = cpu_to_le16(sizeof(*cmd));
678 cmd->hdr.result = 0;
679
680 cmd->action = cpu_to_le16(cmd_action);
681
682 ret = lbs_cmd_with_response(priv, CMD_MESH_ACCESS, cmd);
683
684 lbs_deb_leave(LBS_DEB_CMD);
685 return ret;
686}
687
688static int __lbs_mesh_config_send(struct lbs_private *priv,
689 struct cmd_ds_mesh_config *cmd,
690 uint16_t action, uint16_t type)
691{
692 int ret;
693 u16 command = CMD_MESH_CONFIG_OLD;
694
695 lbs_deb_enter(LBS_DEB_CMD);
696
697 /*
698 * Command id is 0xac for v10 FW along with mesh interface
699 * id in bits 14-13-12.
700 */
701 if (priv->mesh_tlv == TLV_TYPE_MESH_ID)
702 command = CMD_MESH_CONFIG |
703 (MESH_IFACE_ID << MESH_IFACE_BIT_OFFSET);
704
705 cmd->hdr.command = cpu_to_le16(command);
706 cmd->hdr.size = cpu_to_le16(sizeof(struct cmd_ds_mesh_config));
707 cmd->hdr.result = 0;
708
709 cmd->type = cpu_to_le16(type);
710 cmd->action = cpu_to_le16(action);
711
712 ret = lbs_cmd_with_response(priv, command, cmd);
713
714 lbs_deb_leave(LBS_DEB_CMD);
715 return ret;
716}
717
718int lbs_mesh_config_send(struct lbs_private *priv,
719 struct cmd_ds_mesh_config *cmd,
720 uint16_t action, uint16_t type)
721{
722 int ret;
723
724 if (!(priv->fwcapinfo & FW_CAPINFO_PERSISTENT_CONFIG))
725 return -EOPNOTSUPP;
726
727 ret = __lbs_mesh_config_send(priv, cmd, action, type);
728 return ret;
729}
730
731/* This function is the CMD_MESH_CONFIG legacy function. It only handles the
732 * START and STOP actions. The extended actions supported by CMD_MESH_CONFIG
733 * are all handled by preparing a struct cmd_ds_mesh_config and passing it to
734 * lbs_mesh_config_send.
735 */
736int lbs_mesh_config(struct lbs_private *priv, uint16_t action, uint16_t chan)
737{
738 struct cmd_ds_mesh_config cmd;
739 struct mrvl_meshie *ie;
740 DECLARE_SSID_BUF(ssid);
741
742 memset(&cmd, 0, sizeof(cmd));
743 cmd.channel = cpu_to_le16(chan);
744 ie = (struct mrvl_meshie *)cmd.data;
745
746 switch (action) {
747 case CMD_ACT_MESH_CONFIG_START:
748 ie->id = WLAN_EID_GENERIC;
749 ie->val.oui[0] = 0x00;
750 ie->val.oui[1] = 0x50;
751 ie->val.oui[2] = 0x43;
752 ie->val.type = MARVELL_MESH_IE_TYPE;
753 ie->val.subtype = MARVELL_MESH_IE_SUBTYPE;
754 ie->val.version = MARVELL_MESH_IE_VERSION;
755 ie->val.active_protocol_id = MARVELL_MESH_PROTO_ID_HWMP;
756 ie->val.active_metric_id = MARVELL_MESH_METRIC_ID;
757 ie->val.mesh_capability = MARVELL_MESH_CAPABILITY;
758 ie->val.mesh_id_len = priv->mesh_ssid_len;
759 memcpy(ie->val.mesh_id, priv->mesh_ssid, priv->mesh_ssid_len);
760 ie->len = sizeof(struct mrvl_meshie_val) -
761 IEEE80211_MAX_SSID_LEN + priv->mesh_ssid_len;
762 cmd.length = cpu_to_le16(sizeof(struct mrvl_meshie_val));
763 break;
764 case CMD_ACT_MESH_CONFIG_STOP:
765 break;
766 default:
767 return -1;
768 }
769 lbs_deb_cmd("mesh config action %d type %x channel %d SSID %s\n",
770 action, priv->mesh_tlv, chan,
771 print_ssid(ssid, priv->mesh_ssid, priv->mesh_ssid_len));
772
773 return __lbs_mesh_config_send(priv, &cmd, action, priv->mesh_tlv);
774}
775
776
777
778/*************************************************************************** 317/***************************************************************************
779 * Persistent configuration support 318 * Persistent configuration support
780 */ 319 */
@@ -1231,7 +770,7 @@ static struct attribute *boot_opts_attrs[] = {
1231 NULL 770 NULL
1232}; 771};
1233 772
1234static struct attribute_group boot_opts_group = { 773static const struct attribute_group boot_opts_group = {
1235 .name = "boot_options", 774 .name = "boot_options",
1236 .attrs = boot_opts_attrs, 775 .attrs = boot_opts_attrs,
1237}; 776};
@@ -1244,31 +783,299 @@ static struct attribute *mesh_ie_attrs[] = {
1244 NULL 783 NULL
1245}; 784};
1246 785
1247static struct attribute_group mesh_ie_group = { 786static const struct attribute_group mesh_ie_group = {
1248 .name = "mesh_ie", 787 .name = "mesh_ie",
1249 .attrs = mesh_ie_attrs, 788 .attrs = mesh_ie_attrs,
1250}; 789};
1251 790
1252void lbs_persist_config_init(struct net_device *dev) 791static void lbs_persist_config_init(struct net_device *dev)
1253{ 792{
1254 int ret; 793 int ret;
1255 ret = sysfs_create_group(&(dev->dev.kobj), &boot_opts_group); 794 ret = sysfs_create_group(&(dev->dev.kobj), &boot_opts_group);
1256 ret = sysfs_create_group(&(dev->dev.kobj), &mesh_ie_group); 795 ret = sysfs_create_group(&(dev->dev.kobj), &mesh_ie_group);
1257} 796}
1258 797
1259void lbs_persist_config_remove(struct net_device *dev) 798static void lbs_persist_config_remove(struct net_device *dev)
1260{ 799{
1261 sysfs_remove_group(&(dev->dev.kobj), &boot_opts_group); 800 sysfs_remove_group(&(dev->dev.kobj), &boot_opts_group);
1262 sysfs_remove_group(&(dev->dev.kobj), &mesh_ie_group); 801 sysfs_remove_group(&(dev->dev.kobj), &mesh_ie_group);
1263} 802}
1264 803
1265 804
805/***************************************************************************
806 * Initializing and starting, stopping mesh
807 */
808
809/*
810 * Check mesh FW version and appropriately send the mesh start
811 * command
812 */
813int lbs_init_mesh(struct lbs_private *priv)
814{
815 struct net_device *dev = priv->dev;
816 int ret = 0;
817
818 lbs_deb_enter(LBS_DEB_MESH);
819
820 /* Determine mesh_fw_ver from fwrelease and fwcapinfo */
821 /* 5.0.16p0 9.0.0.p0 is known to NOT support any mesh */
822 /* 5.110.22 have mesh command with 0xa3 command id */
823 /* 10.0.0.p0 FW brings in mesh config command with different id */
824 /* Check FW version MSB and initialize mesh_fw_ver */
825 if (MRVL_FW_MAJOR_REV(priv->fwrelease) == MRVL_FW_V5) {
826 /* Enable mesh, if supported, and work out which TLV it uses.
827 0x100 + 291 is an unofficial value used in 5.110.20.pXX
828 0x100 + 37 is the official value used in 5.110.21.pXX
829 but we check them in that order because 20.pXX doesn't
830 give an error -- it just silently fails. */
831
832 /* 5.110.20.pXX firmware will fail the command if the channel
833 doesn't match the existing channel. But only if the TLV
834 is correct. If the channel is wrong, _BOTH_ versions will
835 give an error to 0x100+291, and allow 0x100+37 to succeed.
836 It's just that 5.110.20.pXX will not have done anything
837 useful */
838
839 priv->mesh_tlv = TLV_TYPE_OLD_MESH_ID;
840 if (lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
841 priv->channel)) {
842 priv->mesh_tlv = TLV_TYPE_MESH_ID;
843 if (lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
844 priv->channel))
845 priv->mesh_tlv = 0;
846 }
847 } else
848 if ((MRVL_FW_MAJOR_REV(priv->fwrelease) >= MRVL_FW_V10) &&
849 (priv->fwcapinfo & MESH_CAPINFO_ENABLE_MASK)) {
850 /* 10.0.0.pXX new firmwares should succeed with TLV
851 * 0x100+37; Do not invoke command with old TLV.
852 */
853 priv->mesh_tlv = TLV_TYPE_MESH_ID;
854 if (lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START,
855 priv->channel))
856 priv->mesh_tlv = 0;
857 }
858
859 /* Stop meshing until interface is brought up */
860 lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_STOP, priv->channel);
861
862 if (priv->mesh_tlv) {
863 sprintf(priv->mesh_ssid, "mesh");
864 priv->mesh_ssid_len = 4;
865
866 lbs_add_mesh(priv);
867
868 if (device_create_file(&dev->dev, &dev_attr_lbs_mesh))
869 netdev_err(dev, "cannot register lbs_mesh attribute\n");
870
871 ret = 1;
872 }
873
874 lbs_deb_leave_args(LBS_DEB_MESH, "ret %d", ret);
875 return ret;
876}
877
878
879int lbs_deinit_mesh(struct lbs_private *priv)
880{
881 struct net_device *dev = priv->dev;
882 int ret = 0;
883
884 lbs_deb_enter(LBS_DEB_MESH);
885
886 if (priv->mesh_tlv) {
887 device_remove_file(&dev->dev, &dev_attr_lbs_mesh);
888 ret = 1;
889 }
890
891 lbs_deb_leave_args(LBS_DEB_MESH, "ret %d", ret);
892 return ret;
893}
894
895
896/**
897 * lbs_mesh_stop - close the mshX interface
898 *
899 * @dev: A pointer to &net_device structure
900 * returns: 0
901 */
902static int lbs_mesh_stop(struct net_device *dev)
903{
904 struct lbs_private *priv = dev->ml_priv;
905
906 lbs_deb_enter(LBS_DEB_MESH);
907 lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_STOP, priv->channel);
908
909 spin_lock_irq(&priv->driver_lock);
910
911 netif_stop_queue(dev);
912 netif_carrier_off(dev);
913
914 spin_unlock_irq(&priv->driver_lock);
915
916 schedule_work(&priv->mcast_work);
917
918 lbs_deb_leave(LBS_DEB_MESH);
919 return 0;
920}
921
922/**
923 * lbs_mesh_dev_open - open the mshX interface
924 *
925 * @dev: A pointer to &net_device structure
926 * returns: 0 or -EBUSY if monitor mode active
927 */
928static int lbs_mesh_dev_open(struct net_device *dev)
929{
930 struct lbs_private *priv = dev->ml_priv;
931 int ret = 0;
932
933 lbs_deb_enter(LBS_DEB_NET);
934
935 spin_lock_irq(&priv->driver_lock);
936
937 if (priv->wdev->iftype == NL80211_IFTYPE_MONITOR) {
938 ret = -EBUSY;
939 spin_unlock_irq(&priv->driver_lock);
940 goto out;
941 }
942
943 netif_carrier_on(dev);
944
945 if (!priv->tx_pending_len)
946 netif_wake_queue(dev);
947
948 spin_unlock_irq(&priv->driver_lock);
949
950 ret = lbs_mesh_config(priv, CMD_ACT_MESH_CONFIG_START, priv->channel);
951
952out:
953 lbs_deb_leave_args(LBS_DEB_NET, "ret %d", ret);
954 return ret;
955}
956
957static const struct net_device_ops mesh_netdev_ops = {
958 .ndo_open = lbs_mesh_dev_open,
959 .ndo_stop = lbs_mesh_stop,
960 .ndo_start_xmit = lbs_hard_start_xmit,
961 .ndo_set_mac_address = lbs_set_mac_address,
962 .ndo_set_multicast_list = lbs_set_multicast_list,
963};
964
965/**
966 * lbs_add_mesh - add mshX interface
967 *
968 * @priv: A pointer to the &struct lbs_private structure
969 * returns: 0 if successful, -X otherwise
970 */
971static int lbs_add_mesh(struct lbs_private *priv)
972{
973 struct net_device *mesh_dev = NULL;
974 int ret = 0;
975
976 lbs_deb_enter(LBS_DEB_MESH);
977
978 /* Allocate a virtual mesh device */
979 mesh_dev = alloc_netdev(0, "msh%d", ether_setup);
980 if (!mesh_dev) {
981 lbs_deb_mesh("init mshX device failed\n");
982 ret = -ENOMEM;
983 goto done;
984 }
985 mesh_dev->ml_priv = priv;
986 priv->mesh_dev = mesh_dev;
987
988 mesh_dev->netdev_ops = &mesh_netdev_ops;
989 mesh_dev->ethtool_ops = &lbs_ethtool_ops;
990 memcpy(mesh_dev->dev_addr, priv->dev->dev_addr, ETH_ALEN);
991
992 SET_NETDEV_DEV(priv->mesh_dev, priv->dev->dev.parent);
993
994 mesh_dev->flags |= IFF_BROADCAST | IFF_MULTICAST;
995 /* Register virtual mesh interface */
996 ret = register_netdev(mesh_dev);
997 if (ret) {
998 pr_err("cannot register mshX virtual interface\n");
999 goto err_free;
1000 }
1001
1002 ret = sysfs_create_group(&(mesh_dev->dev.kobj), &lbs_mesh_attr_group);
1003 if (ret)
1004 goto err_unregister;
1005
1006 lbs_persist_config_init(mesh_dev);
1007
1008 /* Everything successful */
1009 ret = 0;
1010 goto done;
1011
1012err_unregister:
1013 unregister_netdev(mesh_dev);
1014
1015err_free:
1016 free_netdev(mesh_dev);
1017
1018done:
1019 lbs_deb_leave_args(LBS_DEB_MESH, "ret %d", ret);
1020 return ret;
1021}
1022
1023void lbs_remove_mesh(struct lbs_private *priv)
1024{
1025 struct net_device *mesh_dev;
1026
1027 mesh_dev = priv->mesh_dev;
1028 if (!mesh_dev)
1029 return;
1030
1031 lbs_deb_enter(LBS_DEB_MESH);
1032 netif_stop_queue(mesh_dev);
1033 netif_carrier_off(mesh_dev);
1034 sysfs_remove_group(&(mesh_dev->dev.kobj), &lbs_mesh_attr_group);
1035 lbs_persist_config_remove(mesh_dev);
1036 unregister_netdev(mesh_dev);
1037 priv->mesh_dev = NULL;
1038 free_netdev(mesh_dev);
1039 lbs_deb_leave(LBS_DEB_MESH);
1040}
1041
1042
1043/***************************************************************************
1044 * Sending and receiving
1045 */
1046struct net_device *lbs_mesh_set_dev(struct lbs_private *priv,
1047 struct net_device *dev, struct rxpd *rxpd)
1048{
1049 if (priv->mesh_dev) {
1050 if (priv->mesh_tlv == TLV_TYPE_OLD_MESH_ID) {
1051 if (rxpd->rx_control & RxPD_MESH_FRAME)
1052 dev = priv->mesh_dev;
1053 } else if (priv->mesh_tlv == TLV_TYPE_MESH_ID) {
1054 if (rxpd->u.bss.bss_num == MESH_IFACE_ID)
1055 dev = priv->mesh_dev;
1056 }
1057 }
1058 return dev;
1059}
1060
1061
1062void lbs_mesh_set_txpd(struct lbs_private *priv,
1063 struct net_device *dev, struct txpd *txpd)
1064{
1065 if (dev == priv->mesh_dev) {
1066 if (priv->mesh_tlv == TLV_TYPE_OLD_MESH_ID)
1067 txpd->tx_control |= cpu_to_le32(TxPD_MESH_FRAME);
1068 else if (priv->mesh_tlv == TLV_TYPE_MESH_ID)
1069 txpd->u.bss.bss_num = MESH_IFACE_ID;
1070 }
1071}
1072
1266 1073
1267/*************************************************************************** 1074/***************************************************************************
1268 * Ethtool related 1075 * Ethtool related
1269 */ 1076 */
1270 1077
1271static const char *mesh_stat_strings[] = { 1078static const char * const mesh_stat_strings[] = {
1272 "drop_duplicate_bcast", 1079 "drop_duplicate_bcast",
1273 "drop_ttl_zero", 1080 "drop_ttl_zero",
1274 "drop_no_fwd_route", 1081 "drop_no_fwd_route",
diff --git a/drivers/net/wireless/libertas/mesh.h b/drivers/net/wireless/libertas/mesh.h
index ee95c73ed5f4..50144913f2ab 100644
--- a/drivers/net/wireless/libertas/mesh.h
+++ b/drivers/net/wireless/libertas/mesh.h
@@ -31,7 +31,6 @@ struct lbs_private;
31int lbs_init_mesh(struct lbs_private *priv); 31int lbs_init_mesh(struct lbs_private *priv);
32int lbs_deinit_mesh(struct lbs_private *priv); 32int lbs_deinit_mesh(struct lbs_private *priv);
33 33
34int lbs_add_mesh(struct lbs_private *priv);
35void lbs_remove_mesh(struct lbs_private *priv); 34void lbs_remove_mesh(struct lbs_private *priv);
36 35
37 36
@@ -52,29 +51,6 @@ struct cmd_ds_command;
52struct cmd_ds_mesh_access; 51struct cmd_ds_mesh_access;
53struct cmd_ds_mesh_config; 52struct cmd_ds_mesh_config;
54 53
55int lbs_mesh_bt_add_del(struct lbs_private *priv, bool add, u8 *addr1);
56int lbs_mesh_bt_reset(struct lbs_private *priv);
57int lbs_mesh_bt_get_inverted(struct lbs_private *priv, bool *inverted);
58int lbs_mesh_bt_set_inverted(struct lbs_private *priv, bool inverted);
59int lbs_mesh_bt_get_entry(struct lbs_private *priv, u32 id, u8 *addr1);
60
61int lbs_cmd_fwt_access(struct lbs_private *priv, u16 cmd_action,
62 struct cmd_ds_fwt_access *cmd);
63
64int lbs_mesh_access(struct lbs_private *priv, uint16_t cmd_action,
65 struct cmd_ds_mesh_access *cmd);
66int lbs_mesh_config_send(struct lbs_private *priv,
67 struct cmd_ds_mesh_config *cmd,
68 uint16_t action, uint16_t type);
69int lbs_mesh_config(struct lbs_private *priv, uint16_t enable, uint16_t chan);
70
71
72
73/* Persistent configuration */
74
75void lbs_persist_config_init(struct net_device *net);
76void lbs_persist_config_remove(struct net_device *net);
77
78 54
79/* Ethtool statistics */ 55/* Ethtool statistics */
80 56
@@ -87,11 +63,6 @@ void lbs_mesh_ethtool_get_strings(struct net_device *dev,
87 uint32_t stringset, uint8_t *s); 63 uint32_t stringset, uint8_t *s);
88 64
89 65
90/* Accessors */
91
92#define lbs_mesh_open(priv) (priv->mesh_open)
93#define lbs_mesh_connected(priv) (priv->mesh_connect_status == LBS_CONNECTED)
94
95#else 66#else
96 67
97#define lbs_init_mesh(priv) 68#define lbs_init_mesh(priv)
@@ -101,8 +72,6 @@ void lbs_mesh_ethtool_get_strings(struct net_device *dev,
101#define lbs_mesh_set_dev(priv, dev, rxpd) (dev) 72#define lbs_mesh_set_dev(priv, dev, rxpd) (dev)
102#define lbs_mesh_set_txpd(priv, dev, txpd) 73#define lbs_mesh_set_txpd(priv, dev, txpd)
103#define lbs_mesh_config(priv, enable, chan) 74#define lbs_mesh_config(priv, enable, chan)
104#define lbs_mesh_open(priv) (0)
105#define lbs_mesh_connected(priv) (0)
106 75
107#endif 76#endif
108 77
diff --git a/drivers/net/wireless/libertas/rx.c b/drivers/net/wireless/libertas/rx.c
index fdb0448301a0..bfb8898ae518 100644
--- a/drivers/net/wireless/libertas/rx.c
+++ b/drivers/net/wireless/libertas/rx.c
@@ -5,6 +5,7 @@
5#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 5#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
6 6
7#include <linux/etherdevice.h> 7#include <linux/etherdevice.h>
8#include <linux/hardirq.h>
8#include <linux/slab.h> 9#include <linux/slab.h>
9#include <linux/types.h> 10#include <linux/types.h>
10#include <net/cfg80211.h> 11#include <net/cfg80211.h>
diff --git a/drivers/net/wireless/libertas/tx.c b/drivers/net/wireless/libertas/tx.c
index bbb95f88dc01..a6e85134cfe1 100644
--- a/drivers/net/wireless/libertas/tx.c
+++ b/drivers/net/wireless/libertas/tx.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * This file contains the handling of TX in wlan driver. 2 * This file contains the handling of TX in wlan driver.
3 */ 3 */
4#include <linux/hardirq.h>
4#include <linux/netdevice.h> 5#include <linux/netdevice.h>
5#include <linux/etherdevice.h> 6#include <linux/etherdevice.h>
6#include <linux/sched.h> 7#include <linux/sched.h>
@@ -198,7 +199,7 @@ void lbs_send_tx_feedback(struct lbs_private *priv, u32 try_count)
198 if (priv->connect_status == LBS_CONNECTED) 199 if (priv->connect_status == LBS_CONNECTED)
199 netif_wake_queue(priv->dev); 200 netif_wake_queue(priv->dev);
200 201
201 if (priv->mesh_dev && lbs_mesh_connected(priv)) 202 if (priv->mesh_dev && netif_running(priv->mesh_dev))
202 netif_wake_queue(priv->mesh_dev); 203 netif_wake_queue(priv->mesh_dev);
203} 204}
204EXPORT_SYMBOL_GPL(lbs_send_tx_feedback); 205EXPORT_SYMBOL_GPL(lbs_send_tx_feedback);
diff --git a/drivers/net/wireless/libertas_tf/cmd.c b/drivers/net/wireless/libertas_tf/cmd.c
index 8945afd6ce3e..13557fe0bf95 100644
--- a/drivers/net/wireless/libertas_tf/cmd.c
+++ b/drivers/net/wireless/libertas_tf/cmd.c
@@ -9,6 +9,7 @@
9 */ 9 */
10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 11
12#include <linux/hardirq.h>
12#include <linux/slab.h> 13#include <linux/slab.h>
13 14
14#include "libertas_tf.h" 15#include "libertas_tf.h"
diff --git a/drivers/net/wireless/libertas_tf/main.c b/drivers/net/wireless/libertas_tf/main.c
index d4005081f1df..acc461aa385e 100644
--- a/drivers/net/wireless/libertas_tf/main.c
+++ b/drivers/net/wireless/libertas_tf/main.c
@@ -9,6 +9,7 @@
9 */ 9 */
10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 11
12#include <linux/hardirq.h>
12#include <linux/slab.h> 13#include <linux/slab.h>
13 14
14#include <linux/etherdevice.h> 15#include <linux/etherdevice.h>
@@ -585,7 +586,7 @@ int lbtf_rx(struct lbtf_private *priv, struct sk_buff *skb)
585 need_padding ^= ieee80211_has_a4(hdr->frame_control); 586 need_padding ^= ieee80211_has_a4(hdr->frame_control);
586 need_padding ^= ieee80211_is_data_qos(hdr->frame_control) && 587 need_padding ^= ieee80211_is_data_qos(hdr->frame_control) &&
587 (*ieee80211_get_qos_ctl(hdr) & 588 (*ieee80211_get_qos_ctl(hdr) &
588 IEEE80211_QOS_CONTROL_A_MSDU_PRESENT); 589 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
589 590
590 if (need_padding) { 591 if (need_padding) {
591 memmove(skb->data + 2, skb->data, skb->len); 592 memmove(skb->data + 2, skb->data, skb->len);
diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c
index 9d4a40ee16c4..031cd89b1768 100644
--- a/drivers/net/wireless/mac80211_hwsim.c
+++ b/drivers/net/wireless/mac80211_hwsim.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * mac80211_hwsim - software simulator of 802.11 radio(s) for mac80211 2 * mac80211_hwsim - software simulator of 802.11 radio(s) for mac80211
3 * Copyright (c) 2008, Jouni Malinen <j@w1.fi> 3 * Copyright (c) 2008, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2011, Javier Lopez <jlopex@gmail.com>
4 * 5 *
5 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -25,11 +26,17 @@
25#include <linux/rtnetlink.h> 26#include <linux/rtnetlink.h>
26#include <linux/etherdevice.h> 27#include <linux/etherdevice.h>
27#include <linux/debugfs.h> 28#include <linux/debugfs.h>
29#include <net/genetlink.h>
30#include "mac80211_hwsim.h"
31
32#define WARN_QUEUE 100
33#define MAX_QUEUE 200
28 34
29MODULE_AUTHOR("Jouni Malinen"); 35MODULE_AUTHOR("Jouni Malinen");
30MODULE_DESCRIPTION("Software simulator of 802.11 radio(s) for mac80211"); 36MODULE_DESCRIPTION("Software simulator of 802.11 radio(s) for mac80211");
31MODULE_LICENSE("GPL"); 37MODULE_LICENSE("GPL");
32 38
39int wmediumd_pid;
33static int radios = 2; 40static int radios = 2;
34module_param(radios, int, 0444); 41module_param(radios, int, 0444);
35MODULE_PARM_DESC(radios, "Number of simulated radios"); 42MODULE_PARM_DESC(radios, "Number of simulated radios");
@@ -302,6 +309,7 @@ struct mac80211_hwsim_data {
302 struct dentry *debugfs; 309 struct dentry *debugfs;
303 struct dentry *debugfs_ps; 310 struct dentry *debugfs_ps;
304 311
312 struct sk_buff_head pending; /* packets pending */
305 /* 313 /*
306 * Only radios in the same group can communicate together (the 314 * Only radios in the same group can communicate together (the
307 * channel has to match too). Each bit represents a group. A 315 * channel has to match too). Each bit represents a group. A
@@ -322,6 +330,32 @@ struct hwsim_radiotap_hdr {
322 __le16 rt_chbitmask; 330 __le16 rt_chbitmask;
323} __packed; 331} __packed;
324 332
333/* MAC80211_HWSIM netlinf family */
334static struct genl_family hwsim_genl_family = {
335 .id = GENL_ID_GENERATE,
336 .hdrsize = 0,
337 .name = "MAC80211_HWSIM",
338 .version = 1,
339 .maxattr = HWSIM_ATTR_MAX,
340};
341
342/* MAC80211_HWSIM netlink policy */
343
344static struct nla_policy hwsim_genl_policy[HWSIM_ATTR_MAX + 1] = {
345 [HWSIM_ATTR_ADDR_RECEIVER] = { .type = NLA_UNSPEC,
346 .len = 6*sizeof(u8) },
347 [HWSIM_ATTR_ADDR_TRANSMITTER] = { .type = NLA_UNSPEC,
348 .len = 6*sizeof(u8) },
349 [HWSIM_ATTR_FRAME] = { .type = NLA_BINARY,
350 .len = IEEE80211_MAX_DATA_LEN },
351 [HWSIM_ATTR_FLAGS] = { .type = NLA_U32 },
352 [HWSIM_ATTR_RX_RATE] = { .type = NLA_U32 },
353 [HWSIM_ATTR_SIGNAL] = { .type = NLA_U32 },
354 [HWSIM_ATTR_TX_INFO] = { .type = NLA_UNSPEC,
355 .len = IEEE80211_TX_MAX_RATES*sizeof(
356 struct hwsim_tx_rate)},
357 [HWSIM_ATTR_COOKIE] = { .type = NLA_U64 },
358};
325 359
326static netdev_tx_t hwsim_mon_xmit(struct sk_buff *skb, 360static netdev_tx_t hwsim_mon_xmit(struct sk_buff *skb,
327 struct net_device *dev) 361 struct net_device *dev)
@@ -478,9 +512,89 @@ static bool mac80211_hwsim_addr_match(struct mac80211_hwsim_data *data,
478 return md.ret; 512 return md.ret;
479} 513}
480 514
515static void mac80211_hwsim_tx_frame_nl(struct ieee80211_hw *hw,
516 struct sk_buff *my_skb,
517 int dst_pid)
518{
519 struct sk_buff *skb;
520 struct mac80211_hwsim_data *data = hw->priv;
521 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) my_skb->data;
522 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(my_skb);
523 void *msg_head;
524 unsigned int hwsim_flags = 0;
525 int i;
526 struct hwsim_tx_rate tx_attempts[IEEE80211_TX_MAX_RATES];
527
528 if (data->idle) {
529 wiphy_debug(hw->wiphy, "Trying to TX when idle - reject\n");
530 dev_kfree_skb(my_skb);
531 return;
532 }
533
534 if (data->ps != PS_DISABLED)
535 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
536 /* If the queue contains MAX_QUEUE skb's drop some */
537 if (skb_queue_len(&data->pending) >= MAX_QUEUE) {
538 /* Droping until WARN_QUEUE level */
539 while (skb_queue_len(&data->pending) >= WARN_QUEUE)
540 skb_dequeue(&data->pending);
541 }
542
543 skb = genlmsg_new(NLMSG_GOODSIZE, GFP_ATOMIC);
544 if (skb == NULL)
545 goto nla_put_failure;
546
547 msg_head = genlmsg_put(skb, 0, 0, &hwsim_genl_family, 0,
548 HWSIM_CMD_FRAME);
549 if (msg_head == NULL) {
550 printk(KERN_DEBUG "mac80211_hwsim: problem with msg_head\n");
551 goto nla_put_failure;
552 }
553
554 NLA_PUT(skb, HWSIM_ATTR_ADDR_TRANSMITTER,
555 sizeof(struct mac_address), data->addresses[1].addr);
481 556
482static bool mac80211_hwsim_tx_frame(struct ieee80211_hw *hw, 557 /* We get the skb->data */
483 struct sk_buff *skb) 558 NLA_PUT(skb, HWSIM_ATTR_FRAME, my_skb->len, my_skb->data);
559
560 /* We get the flags for this transmission, and we translate them to
561 wmediumd flags */
562
563 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)
564 hwsim_flags |= HWSIM_TX_CTL_REQ_TX_STATUS;
565
566 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
567 hwsim_flags |= HWSIM_TX_CTL_NO_ACK;
568
569 NLA_PUT_U32(skb, HWSIM_ATTR_FLAGS, hwsim_flags);
570
571 /* We get the tx control (rate and retries) info*/
572
573 for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
574 tx_attempts[i].idx = info->status.rates[i].idx;
575 tx_attempts[i].count = info->status.rates[i].count;
576 }
577
578 NLA_PUT(skb, HWSIM_ATTR_TX_INFO,
579 sizeof(struct hwsim_tx_rate)*IEEE80211_TX_MAX_RATES,
580 tx_attempts);
581
582 /* We create a cookie to identify this skb */
583 NLA_PUT_U64(skb, HWSIM_ATTR_COOKIE, (unsigned long) my_skb);
584
585 genlmsg_end(skb, msg_head);
586 genlmsg_unicast(&init_net, skb, dst_pid);
587
588 /* Enqueue the packet */
589 skb_queue_tail(&data->pending, my_skb);
590 return;
591
592nla_put_failure:
593 printk(KERN_DEBUG "mac80211_hwsim: error occured in %s\n", __func__);
594}
595
596static bool mac80211_hwsim_tx_frame_no_nl(struct ieee80211_hw *hw,
597 struct sk_buff *skb)
484{ 598{
485 struct mac80211_hwsim_data *data = hw->priv, *data2; 599 struct mac80211_hwsim_data *data = hw->priv, *data2;
486 bool ack = false; 600 bool ack = false;
@@ -540,11 +654,11 @@ static bool mac80211_hwsim_tx_frame(struct ieee80211_hw *hw,
540 return ack; 654 return ack;
541} 655}
542 656
543
544static void mac80211_hwsim_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 657static void mac80211_hwsim_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
545{ 658{
546 bool ack; 659 bool ack;
547 struct ieee80211_tx_info *txi; 660 struct ieee80211_tx_info *txi;
661 int _pid;
548 662
549 mac80211_hwsim_monitor_rx(hw, skb); 663 mac80211_hwsim_monitor_rx(hw, skb);
550 664
@@ -554,7 +668,15 @@ static void mac80211_hwsim_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
554 return; 668 return;
555 } 669 }
556 670
557 ack = mac80211_hwsim_tx_frame(hw, skb); 671 /* wmediumd mode check */
672 _pid = wmediumd_pid;
673
674 if (_pid)
675 return mac80211_hwsim_tx_frame_nl(hw, skb, _pid);
676
677 /* NO wmediumd detected, perfect medium simulation */
678 ack = mac80211_hwsim_tx_frame_no_nl(hw, skb);
679
558 if (ack && skb->len >= 16) { 680 if (ack && skb->len >= 16) {
559 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 681 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
560 mac80211_hwsim_monitor_ack(hw, hdr->addr2); 682 mac80211_hwsim_monitor_ack(hw, hdr->addr2);
@@ -635,6 +757,7 @@ static void mac80211_hwsim_beacon_tx(void *arg, u8 *mac,
635 struct ieee80211_hw *hw = arg; 757 struct ieee80211_hw *hw = arg;
636 struct sk_buff *skb; 758 struct sk_buff *skb;
637 struct ieee80211_tx_info *info; 759 struct ieee80211_tx_info *info;
760 int _pid;
638 761
639 hwsim_check_magic(vif); 762 hwsim_check_magic(vif);
640 763
@@ -649,7 +772,14 @@ static void mac80211_hwsim_beacon_tx(void *arg, u8 *mac,
649 info = IEEE80211_SKB_CB(skb); 772 info = IEEE80211_SKB_CB(skb);
650 773
651 mac80211_hwsim_monitor_rx(hw, skb); 774 mac80211_hwsim_monitor_rx(hw, skb);
652 mac80211_hwsim_tx_frame(hw, skb); 775
776 /* wmediumd mode check */
777 _pid = wmediumd_pid;
778
779 if (_pid)
780 return mac80211_hwsim_tx_frame_nl(hw, skb, _pid);
781
782 mac80211_hwsim_tx_frame_no_nl(hw, skb);
653 dev_kfree_skb(skb); 783 dev_kfree_skb(skb);
654} 784}
655 785
@@ -966,12 +1096,7 @@ static int mac80211_hwsim_ampdu_action(struct ieee80211_hw *hw,
966 1096
967static void mac80211_hwsim_flush(struct ieee80211_hw *hw, bool drop) 1097static void mac80211_hwsim_flush(struct ieee80211_hw *hw, bool drop)
968{ 1098{
969 /* 1099 /* Not implemented, queues only on kernel side */
970 * In this special case, there's nothing we need to
971 * do because hwsim does transmission synchronously.
972 * In the future, when it does transmissions via
973 * userspace, we may need to do something.
974 */
975} 1100}
976 1101
977struct hw_scan_done { 1102struct hw_scan_done {
@@ -1005,6 +1130,8 @@ static int mac80211_hwsim_hw_scan(struct ieee80211_hw *hw,
1005 for (i = 0; i < req->n_channels; i++) 1130 for (i = 0; i < req->n_channels; i++)
1006 printk(KERN_DEBUG "hwsim hw_scan freq %d\n", 1131 printk(KERN_DEBUG "hwsim hw_scan freq %d\n",
1007 req->channels[i]->center_freq); 1132 req->channels[i]->center_freq);
1133 print_hex_dump(KERN_DEBUG, "scan IEs: ", DUMP_PREFIX_OFFSET,
1134 16, 1, req->ie, req->ie_len, 1);
1008 1135
1009 ieee80211_queue_delayed_work(hw, &hsd->w, 2 * HZ); 1136 ieee80211_queue_delayed_work(hw, &hsd->w, 2 * HZ);
1010 1137
@@ -1119,6 +1246,7 @@ static void hwsim_send_ps_poll(void *dat, u8 *mac, struct ieee80211_vif *vif)
1119 struct hwsim_vif_priv *vp = (void *)vif->drv_priv; 1246 struct hwsim_vif_priv *vp = (void *)vif->drv_priv;
1120 struct sk_buff *skb; 1247 struct sk_buff *skb;
1121 struct ieee80211_pspoll *pspoll; 1248 struct ieee80211_pspoll *pspoll;
1249 int _pid;
1122 1250
1123 if (!vp->assoc) 1251 if (!vp->assoc)
1124 return; 1252 return;
@@ -1137,8 +1265,15 @@ static void hwsim_send_ps_poll(void *dat, u8 *mac, struct ieee80211_vif *vif)
1137 pspoll->aid = cpu_to_le16(0xc000 | vp->aid); 1265 pspoll->aid = cpu_to_le16(0xc000 | vp->aid);
1138 memcpy(pspoll->bssid, vp->bssid, ETH_ALEN); 1266 memcpy(pspoll->bssid, vp->bssid, ETH_ALEN);
1139 memcpy(pspoll->ta, mac, ETH_ALEN); 1267 memcpy(pspoll->ta, mac, ETH_ALEN);
1140 if (!mac80211_hwsim_tx_frame(data->hw, skb)) 1268
1141 printk(KERN_DEBUG "%s: PS-Poll frame not ack'ed\n", __func__); 1269 /* wmediumd mode check */
1270 _pid = wmediumd_pid;
1271
1272 if (_pid)
1273 return mac80211_hwsim_tx_frame_nl(data->hw, skb, _pid);
1274
1275 if (!mac80211_hwsim_tx_frame_no_nl(data->hw, skb))
1276 printk(KERN_DEBUG "%s: PS-poll frame not ack'ed\n", __func__);
1142 dev_kfree_skb(skb); 1277 dev_kfree_skb(skb);
1143} 1278}
1144 1279
@@ -1149,6 +1284,7 @@ static void hwsim_send_nullfunc(struct mac80211_hwsim_data *data, u8 *mac,
1149 struct hwsim_vif_priv *vp = (void *)vif->drv_priv; 1284 struct hwsim_vif_priv *vp = (void *)vif->drv_priv;
1150 struct sk_buff *skb; 1285 struct sk_buff *skb;
1151 struct ieee80211_hdr *hdr; 1286 struct ieee80211_hdr *hdr;
1287 int _pid;
1152 1288
1153 if (!vp->assoc) 1289 if (!vp->assoc)
1154 return; 1290 return;
@@ -1168,7 +1304,14 @@ static void hwsim_send_nullfunc(struct mac80211_hwsim_data *data, u8 *mac,
1168 memcpy(hdr->addr1, vp->bssid, ETH_ALEN); 1304 memcpy(hdr->addr1, vp->bssid, ETH_ALEN);
1169 memcpy(hdr->addr2, mac, ETH_ALEN); 1305 memcpy(hdr->addr2, mac, ETH_ALEN);
1170 memcpy(hdr->addr3, vp->bssid, ETH_ALEN); 1306 memcpy(hdr->addr3, vp->bssid, ETH_ALEN);
1171 if (!mac80211_hwsim_tx_frame(data->hw, skb)) 1307
1308 /* wmediumd mode check */
1309 _pid = wmediumd_pid;
1310
1311 if (_pid)
1312 return mac80211_hwsim_tx_frame_nl(data->hw, skb, _pid);
1313
1314 if (!mac80211_hwsim_tx_frame_no_nl(data->hw, skb))
1172 printk(KERN_DEBUG "%s: nullfunc frame not ack'ed\n", __func__); 1315 printk(KERN_DEBUG "%s: nullfunc frame not ack'ed\n", __func__);
1173 dev_kfree_skb(skb); 1316 dev_kfree_skb(skb);
1174} 1317}
@@ -1248,6 +1391,273 @@ DEFINE_SIMPLE_ATTRIBUTE(hwsim_fops_group,
1248 hwsim_fops_group_read, hwsim_fops_group_write, 1391 hwsim_fops_group_read, hwsim_fops_group_write,
1249 "%llx\n"); 1392 "%llx\n");
1250 1393
1394struct mac80211_hwsim_data *get_hwsim_data_ref_from_addr(
1395 struct mac_address *addr)
1396{
1397 struct mac80211_hwsim_data *data;
1398 bool _found = false;
1399
1400 spin_lock_bh(&hwsim_radio_lock);
1401 list_for_each_entry(data, &hwsim_radios, list) {
1402 if (memcmp(data->addresses[1].addr, addr,
1403 sizeof(struct mac_address)) == 0) {
1404 _found = true;
1405 break;
1406 }
1407 }
1408 spin_unlock_bh(&hwsim_radio_lock);
1409
1410 if (!_found)
1411 return NULL;
1412
1413 return data;
1414}
1415
1416static int hwsim_tx_info_frame_received_nl(struct sk_buff *skb_2,
1417 struct genl_info *info)
1418{
1419
1420 struct ieee80211_hdr *hdr;
1421 struct mac80211_hwsim_data *data2;
1422 struct ieee80211_tx_info *txi;
1423 struct hwsim_tx_rate *tx_attempts;
1424 struct sk_buff __user *ret_skb;
1425 struct sk_buff *skb, *tmp;
1426 struct mac_address *src;
1427 unsigned int hwsim_flags;
1428
1429 int i;
1430 bool found = false;
1431
1432 if (!info->attrs[HWSIM_ATTR_ADDR_TRANSMITTER] ||
1433 !info->attrs[HWSIM_ATTR_FLAGS] ||
1434 !info->attrs[HWSIM_ATTR_COOKIE] ||
1435 !info->attrs[HWSIM_ATTR_TX_INFO])
1436 goto out;
1437
1438 src = (struct mac_address *)nla_data(
1439 info->attrs[HWSIM_ATTR_ADDR_TRANSMITTER]);
1440 hwsim_flags = nla_get_u32(info->attrs[HWSIM_ATTR_FLAGS]);
1441
1442 ret_skb = (struct sk_buff __user *)
1443 (unsigned long) nla_get_u64(info->attrs[HWSIM_ATTR_COOKIE]);
1444
1445 data2 = get_hwsim_data_ref_from_addr(src);
1446
1447 if (data2 == NULL)
1448 goto out;
1449
1450 /* look for the skb matching the cookie passed back from user */
1451 skb_queue_walk_safe(&data2->pending, skb, tmp) {
1452 if (skb == ret_skb) {
1453 skb_unlink(skb, &data2->pending);
1454 found = true;
1455 break;
1456 }
1457 }
1458
1459 /* not found */
1460 if (!found)
1461 goto out;
1462
1463 /* Tx info received because the frame was broadcasted on user space,
1464 so we get all the necessary info: tx attempts and skb control buff */
1465
1466 tx_attempts = (struct hwsim_tx_rate *)nla_data(
1467 info->attrs[HWSIM_ATTR_TX_INFO]);
1468
1469 /* now send back TX status */
1470 txi = IEEE80211_SKB_CB(skb);
1471
1472 if (txi->control.vif)
1473 hwsim_check_magic(txi->control.vif);
1474 if (txi->control.sta)
1475 hwsim_check_sta_magic(txi->control.sta);
1476
1477 ieee80211_tx_info_clear_status(txi);
1478
1479 for (i = 0; i < IEEE80211_TX_MAX_RATES; i++) {
1480 txi->status.rates[i].idx = tx_attempts[i].idx;
1481 txi->status.rates[i].count = tx_attempts[i].count;
1482 /*txi->status.rates[i].flags = 0;*/
1483 }
1484
1485 txi->status.ack_signal = nla_get_u32(info->attrs[HWSIM_ATTR_SIGNAL]);
1486
1487 if (!(hwsim_flags & HWSIM_TX_CTL_NO_ACK) &&
1488 (hwsim_flags & HWSIM_TX_STAT_ACK)) {
1489 if (skb->len >= 16) {
1490 hdr = (struct ieee80211_hdr *) skb->data;
1491 mac80211_hwsim_monitor_ack(data2->hw, hdr->addr2);
1492 }
1493 }
1494 ieee80211_tx_status_irqsafe(data2->hw, skb);
1495 return 0;
1496out:
1497 return -EINVAL;
1498
1499}
1500
1501static int hwsim_cloned_frame_received_nl(struct sk_buff *skb_2,
1502 struct genl_info *info)
1503{
1504
1505 struct mac80211_hwsim_data *data2;
1506 struct ieee80211_rx_status rx_status;
1507 struct mac_address *dst;
1508 int frame_data_len;
1509 char *frame_data;
1510 struct sk_buff *skb = NULL;
1511
1512 if (!info->attrs[HWSIM_ATTR_ADDR_RECEIVER] ||
1513 !info->attrs[HWSIM_ATTR_FRAME] ||
1514 !info->attrs[HWSIM_ATTR_RX_RATE] ||
1515 !info->attrs[HWSIM_ATTR_SIGNAL])
1516 goto out;
1517
1518 dst = (struct mac_address *)nla_data(
1519 info->attrs[HWSIM_ATTR_ADDR_RECEIVER]);
1520
1521 frame_data_len = nla_len(info->attrs[HWSIM_ATTR_FRAME]);
1522 frame_data = (char *)nla_data(info->attrs[HWSIM_ATTR_FRAME]);
1523
1524 /* Allocate new skb here */
1525 skb = alloc_skb(frame_data_len, GFP_KERNEL);
1526 if (skb == NULL)
1527 goto err;
1528
1529 if (frame_data_len <= IEEE80211_MAX_DATA_LEN) {
1530 /* Copy the data */
1531 memcpy(skb_put(skb, frame_data_len), frame_data,
1532 frame_data_len);
1533 } else
1534 goto err;
1535
1536 data2 = get_hwsim_data_ref_from_addr(dst);
1537
1538 if (data2 == NULL)
1539 goto out;
1540
1541 /* check if radio is configured properly */
1542
1543 if (data2->idle || !data2->started || !data2->channel)
1544 goto out;
1545
1546 /*A frame is received from user space*/
1547 memset(&rx_status, 0, sizeof(rx_status));
1548 rx_status.freq = data2->channel->center_freq;
1549 rx_status.band = data2->channel->band;
1550 rx_status.rate_idx = nla_get_u32(info->attrs[HWSIM_ATTR_RX_RATE]);
1551 rx_status.signal = nla_get_u32(info->attrs[HWSIM_ATTR_SIGNAL]);
1552
1553 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
1554 ieee80211_rx_irqsafe(data2->hw, skb);
1555
1556 return 0;
1557err:
1558 printk(KERN_DEBUG "mac80211_hwsim: error occured in %s\n", __func__);
1559 goto out;
1560out:
1561 dev_kfree_skb(skb);
1562 return -EINVAL;
1563}
1564
1565static int hwsim_register_received_nl(struct sk_buff *skb_2,
1566 struct genl_info *info)
1567{
1568 if (info == NULL)
1569 goto out;
1570
1571 wmediumd_pid = info->snd_pid;
1572
1573 printk(KERN_DEBUG "mac80211_hwsim: received a REGISTER, "
1574 "switching to wmediumd mode with pid %d\n", info->snd_pid);
1575
1576 return 0;
1577out:
1578 printk(KERN_DEBUG "mac80211_hwsim: error occured in %s\n", __func__);
1579 return -EINVAL;
1580}
1581
1582/* Generic Netlink operations array */
1583static struct genl_ops hwsim_ops[] = {
1584 {
1585 .cmd = HWSIM_CMD_REGISTER,
1586 .policy = hwsim_genl_policy,
1587 .doit = hwsim_register_received_nl,
1588 .flags = GENL_ADMIN_PERM,
1589 },
1590 {
1591 .cmd = HWSIM_CMD_FRAME,
1592 .policy = hwsim_genl_policy,
1593 .doit = hwsim_cloned_frame_received_nl,
1594 },
1595 {
1596 .cmd = HWSIM_CMD_TX_INFO_FRAME,
1597 .policy = hwsim_genl_policy,
1598 .doit = hwsim_tx_info_frame_received_nl,
1599 },
1600};
1601
1602static int mac80211_hwsim_netlink_notify(struct notifier_block *nb,
1603 unsigned long state,
1604 void *_notify)
1605{
1606 struct netlink_notify *notify = _notify;
1607
1608 if (state != NETLINK_URELEASE)
1609 return NOTIFY_DONE;
1610
1611 if (notify->pid == wmediumd_pid) {
1612 printk(KERN_INFO "mac80211_hwsim: wmediumd released netlink"
1613 " socket, switching to perfect channel medium\n");
1614 wmediumd_pid = 0;
1615 }
1616 return NOTIFY_DONE;
1617
1618}
1619
1620static struct notifier_block hwsim_netlink_notifier = {
1621 .notifier_call = mac80211_hwsim_netlink_notify,
1622};
1623
1624static int hwsim_init_netlink(void)
1625{
1626 int rc;
1627 printk(KERN_INFO "mac80211_hwsim: initializing netlink\n");
1628
1629 wmediumd_pid = 0;
1630
1631 rc = genl_register_family_with_ops(&hwsim_genl_family,
1632 hwsim_ops, ARRAY_SIZE(hwsim_ops));
1633 if (rc)
1634 goto failure;
1635
1636 rc = netlink_register_notifier(&hwsim_netlink_notifier);
1637 if (rc)
1638 goto failure;
1639
1640 return 0;
1641
1642failure:
1643 printk(KERN_DEBUG "mac80211_hwsim: error occured in %s\n", __func__);
1644 return -EINVAL;
1645}
1646
1647static void hwsim_exit_netlink(void)
1648{
1649 int ret;
1650
1651 printk(KERN_INFO "mac80211_hwsim: closing netlink\n");
1652 /* unregister the notifier */
1653 netlink_unregister_notifier(&hwsim_netlink_notifier);
1654 /* unregister the family */
1655 ret = genl_unregister_family(&hwsim_genl_family);
1656 if (ret)
1657 printk(KERN_DEBUG "mac80211_hwsim: "
1658 "unregister family %i\n", ret);
1659}
1660
1251static int __init init_mac80211_hwsim(void) 1661static int __init init_mac80211_hwsim(void)
1252{ 1662{
1253 int i, err = 0; 1663 int i, err = 0;
@@ -1298,6 +1708,7 @@ static int __init init_mac80211_hwsim(void)
1298 goto failed_drvdata; 1708 goto failed_drvdata;
1299 } 1709 }
1300 data->dev->driver = &mac80211_hwsim_driver; 1710 data->dev->driver = &mac80211_hwsim_driver;
1711 skb_queue_head_init(&data->pending);
1301 1712
1302 SET_IEEE80211_DEV(hw, data->dev); 1713 SET_IEEE80211_DEV(hw, data->dev);
1303 addr[3] = i >> 8; 1714 addr[3] = i >> 8;
@@ -1379,6 +1790,10 @@ static int __init init_mac80211_hwsim(void)
1379 data->group = 1; 1790 data->group = 1;
1380 mutex_init(&data->mutex); 1791 mutex_init(&data->mutex);
1381 1792
1793 /* Enable frame retransmissions for lossy channels */
1794 hw->max_rates = 4;
1795 hw->max_rate_tries = 11;
1796
1382 /* Work to be done prior to ieee80211_register_hw() */ 1797 /* Work to be done prior to ieee80211_register_hw() */
1383 switch (regtest) { 1798 switch (regtest) {
1384 case HWSIM_REGTEST_DISABLED: 1799 case HWSIM_REGTEST_DISABLED:
@@ -1515,12 +1930,29 @@ static int __init init_mac80211_hwsim(void)
1515 if (hwsim_mon == NULL) 1930 if (hwsim_mon == NULL)
1516 goto failed; 1931 goto failed;
1517 1932
1518 err = register_netdev(hwsim_mon); 1933 rtnl_lock();
1934
1935 err = dev_alloc_name(hwsim_mon, hwsim_mon->name);
1519 if (err < 0) 1936 if (err < 0)
1520 goto failed_mon; 1937 goto failed_mon;
1521 1938
1939
1940 err = register_netdevice(hwsim_mon);
1941 if (err < 0)
1942 goto failed_mon;
1943
1944 rtnl_unlock();
1945
1946 err = hwsim_init_netlink();
1947 if (err < 0)
1948 goto failed_nl;
1949
1522 return 0; 1950 return 0;
1523 1951
1952failed_nl:
1953 printk(KERN_DEBUG "mac_80211_hwsim: failed initializing netlink\n");
1954 return err;
1955
1524failed_mon: 1956failed_mon:
1525 rtnl_unlock(); 1957 rtnl_unlock();
1526 free_netdev(hwsim_mon); 1958 free_netdev(hwsim_mon);
@@ -1541,6 +1973,8 @@ static void __exit exit_mac80211_hwsim(void)
1541{ 1973{
1542 printk(KERN_DEBUG "mac80211_hwsim: unregister radios\n"); 1974 printk(KERN_DEBUG "mac80211_hwsim: unregister radios\n");
1543 1975
1976 hwsim_exit_netlink();
1977
1544 mac80211_hwsim_free(); 1978 mac80211_hwsim_free();
1545 unregister_netdev(hwsim_mon); 1979 unregister_netdev(hwsim_mon);
1546} 1980}
diff --git a/drivers/net/wireless/mac80211_hwsim.h b/drivers/net/wireless/mac80211_hwsim.h
new file mode 100644
index 000000000000..afaad5a443b6
--- /dev/null
+++ b/drivers/net/wireless/mac80211_hwsim.h
@@ -0,0 +1,133 @@
1/*
2 * mac80211_hwsim - software simulator of 802.11 radio(s) for mac80211
3 * Copyright (c) 2008, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2011, Javier Lopez <jlopex@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MAC80211_HWSIM_H
12#define __MAC80211_HWSIM_H
13
14/**
15 * enum hwsim_tx_control_flags - flags to describe transmission info/status
16 *
17 * These flags are used to give the wmediumd extra information in order to
18 * modify its behavior for each frame
19 *
20 * @HWSIM_TX_CTL_REQ_TX_STATUS: require TX status callback for this frame.
21 * @HWSIM_TX_CTL_NO_ACK: tell the wmediumd not to wait for an ack
22 * @HWSIM_TX_STAT_ACK: Frame was acknowledged
23 *
24 */
25enum hwsim_tx_control_flags {
26 HWSIM_TX_CTL_REQ_TX_STATUS = BIT(0),
27 HWSIM_TX_CTL_NO_ACK = BIT(1),
28 HWSIM_TX_STAT_ACK = BIT(2),
29};
30
31/**
32 * DOC: Frame transmission/registration support
33 *
34 * Frame transmission and registration support exists to allow userspace
35 * entities such as wmediumd to receive and process all broadcasted
36 * frames from a mac80211_hwsim radio device.
37 *
38 * This allow user space applications to decide if the frame should be
39 * dropped or not and implement a wireless medium simulator at user space.
40 *
41 * Registration is done by sending a register message to the driver and
42 * will be automatically unregistered if the user application doesn't
43 * responds to sent frames.
44 * Once registered the user application has to take responsibility of
45 * broadcasting the frames to all listening mac80211_hwsim radio
46 * interfaces.
47 *
48 * For more technical details, see the corresponding command descriptions
49 * below.
50 */
51
52/**
53 * enum hwsim_commands - supported hwsim commands
54 *
55 * @HWSIM_CMD_UNSPEC: unspecified command to catch errors
56 *
57 * @HWSIM_CMD_REGISTER: request to register and received all broadcasted
58 * frames by any mac80211_hwsim radio device.
59 * @HWSIM_CMD_FRAME: send/receive a broadcasted frame from/to kernel/user
60 * space, uses:
61 * %HWSIM_ATTR_ADDR_TRANSMITTER, %HWSIM_ATTR_ADDR_RECEIVER,
62 * %HWSIM_ATTR_FRAME, %HWSIM_ATTR_FLAGS, %HWSIM_ATTR_RX_RATE,
63 * %HWSIM_ATTR_SIGNAL, %HWSIM_ATTR_COOKIE
64 * @HWSIM_CMD_TX_INFO_FRAME: Transmission info report from user space to
65 * kernel, uses:
66 * %HWSIM_ATTR_ADDR_TRANSMITTER, %HWSIM_ATTR_FLAGS,
67 * %HWSIM_ATTR_TX_INFO, %HWSIM_ATTR_SIGNAL, %HWSIM_ATTR_COOKIE
68 * @__HWSIM_CMD_MAX: enum limit
69 */
70enum {
71 HWSIM_CMD_UNSPEC,
72 HWSIM_CMD_REGISTER,
73 HWSIM_CMD_FRAME,
74 HWSIM_CMD_TX_INFO_FRAME,
75 __HWSIM_CMD_MAX,
76};
77#define HWSIM_CMD_MAX (_HWSIM_CMD_MAX - 1)
78
79/**
80 * enum hwsim_attrs - hwsim netlink attributes
81 *
82 * @HWSIM_ATTR_UNSPEC: unspecified attribute to catch errors
83 *
84 * @HWSIM_ATTR_ADDR_RECEIVER: MAC address of the radio device that
85 * the frame is broadcasted to
86 * @HWSIM_ATTR_ADDR_TRANSMITTER: MAC address of the radio device that
87 * the frame was broadcasted from
88 * @HWSIM_ATTR_FRAME: Data array
89 * @HWSIM_ATTR_FLAGS: mac80211 transmission flags, used to process
90 properly the frame at user space
91 * @HWSIM_ATTR_RX_RATE: estimated rx rate index for this frame at user
92 space
93 * @HWSIM_ATTR_SIGNAL: estimated RX signal for this frame at user
94 space
95 * @HWSIM_ATTR_TX_INFO: ieee80211_tx_rate array
96 * @HWSIM_ATTR_COOKIE: sk_buff cookie to identify the frame
97 * @__HWSIM_ATTR_MAX: enum limit
98 */
99
100
101enum {
102 HWSIM_ATTR_UNSPEC,
103 HWSIM_ATTR_ADDR_RECEIVER,
104 HWSIM_ATTR_ADDR_TRANSMITTER,
105 HWSIM_ATTR_FRAME,
106 HWSIM_ATTR_FLAGS,
107 HWSIM_ATTR_RX_RATE,
108 HWSIM_ATTR_SIGNAL,
109 HWSIM_ATTR_TX_INFO,
110 HWSIM_ATTR_COOKIE,
111 __HWSIM_ATTR_MAX,
112};
113#define HWSIM_ATTR_MAX (__HWSIM_ATTR_MAX - 1)
114
115/**
116 * struct hwsim_tx_rate - rate selection/status
117 *
118 * @idx: rate index to attempt to send with
119 * @count: number of tries in this rate before going to the next rate
120 *
121 * A value of -1 for @idx indicates an invalid rate and, if used
122 * in an array of retry rates, that no more rates should be tried.
123 *
124 * When used for transmit status reporting, the driver should
125 * always report the rate and number of retries used.
126 *
127 */
128struct hwsim_tx_rate {
129 s8 idx;
130 u8 count;
131} __packed;
132
133#endif /* __MAC80211_HWSIM_H */
diff --git a/drivers/net/wireless/mwifiex/11n.c b/drivers/net/wireless/mwifiex/11n.c
index 916183d39009..34bba5234294 100644
--- a/drivers/net/wireless/mwifiex/11n.c
+++ b/drivers/net/wireless/mwifiex/11n.c
@@ -185,13 +185,12 @@ int mwifiex_ret_11n_addba_req(struct mwifiex_private *priv,
185 * 185 *
186 * Handling includes changing the header fields into CPU format. 186 * Handling includes changing the header fields into CPU format.
187 */ 187 */
188int mwifiex_ret_11n_cfg(struct host_cmd_ds_command *resp, void *data_buf) 188int mwifiex_ret_11n_cfg(struct host_cmd_ds_command *resp,
189 struct mwifiex_ds_11n_tx_cfg *tx_cfg)
189{ 190{
190 struct mwifiex_ds_11n_tx_cfg *tx_cfg;
191 struct host_cmd_ds_11n_cfg *htcfg = &resp->params.htcfg; 191 struct host_cmd_ds_11n_cfg *htcfg = &resp->params.htcfg;
192 192
193 if (data_buf) { 193 if (tx_cfg) {
194 tx_cfg = (struct mwifiex_ds_11n_tx_cfg *) data_buf;
195 tx_cfg->tx_htcap = le16_to_cpu(htcfg->ht_tx_cap); 194 tx_cfg->tx_htcap = le16_to_cpu(htcfg->ht_tx_cap);
196 tx_cfg->tx_htinfo = le16_to_cpu(htcfg->ht_tx_info); 195 tx_cfg->tx_htinfo = le16_to_cpu(htcfg->ht_tx_info);
197 } 196 }
@@ -208,11 +207,10 @@ int mwifiex_ret_11n_cfg(struct host_cmd_ds_command *resp, void *data_buf)
208 */ 207 */
209int mwifiex_cmd_recfg_tx_buf(struct mwifiex_private *priv, 208int mwifiex_cmd_recfg_tx_buf(struct mwifiex_private *priv,
210 struct host_cmd_ds_command *cmd, int cmd_action, 209 struct host_cmd_ds_command *cmd, int cmd_action,
211 void *data_buf) 210 u16 *buf_size)
212{ 211{
213 struct host_cmd_ds_txbuf_cfg *tx_buf = &cmd->params.tx_buf; 212 struct host_cmd_ds_txbuf_cfg *tx_buf = &cmd->params.tx_buf;
214 u16 action = (u16) cmd_action; 213 u16 action = (u16) cmd_action;
215 u16 buf_size = *((u16 *) data_buf);
216 214
217 cmd->command = cpu_to_le16(HostCmd_CMD_RECONFIGURE_TX_BUFF); 215 cmd->command = cpu_to_le16(HostCmd_CMD_RECONFIGURE_TX_BUFF);
218 cmd->size = 216 cmd->size =
@@ -220,8 +218,8 @@ int mwifiex_cmd_recfg_tx_buf(struct mwifiex_private *priv,
220 tx_buf->action = cpu_to_le16(action); 218 tx_buf->action = cpu_to_le16(action);
221 switch (action) { 219 switch (action) {
222 case HostCmd_ACT_GEN_SET: 220 case HostCmd_ACT_GEN_SET:
223 dev_dbg(priv->adapter->dev, "cmd: set tx_buf=%d\n", buf_size); 221 dev_dbg(priv->adapter->dev, "cmd: set tx_buf=%d\n", *buf_size);
224 tx_buf->buff_size = cpu_to_le16(buf_size); 222 tx_buf->buff_size = cpu_to_le16(*buf_size);
225 break; 223 break;
226 case HostCmd_ACT_GEN_GET: 224 case HostCmd_ACT_GEN_GET:
227 default: 225 default:
@@ -240,13 +238,12 @@ int mwifiex_cmd_recfg_tx_buf(struct mwifiex_private *priv,
240 * - Ensuring correct endian-ness 238 * - Ensuring correct endian-ness
241 */ 239 */
242int mwifiex_cmd_amsdu_aggr_ctrl(struct host_cmd_ds_command *cmd, 240int mwifiex_cmd_amsdu_aggr_ctrl(struct host_cmd_ds_command *cmd,
243 int cmd_action, void *data_buf) 241 int cmd_action,
242 struct mwifiex_ds_11n_amsdu_aggr_ctrl *aa_ctrl)
244{ 243{
245 struct host_cmd_ds_amsdu_aggr_ctrl *amsdu_ctrl = 244 struct host_cmd_ds_amsdu_aggr_ctrl *amsdu_ctrl =
246 &cmd->params.amsdu_aggr_ctrl; 245 &cmd->params.amsdu_aggr_ctrl;
247 u16 action = (u16) cmd_action; 246 u16 action = (u16) cmd_action;
248 struct mwifiex_ds_11n_amsdu_aggr_ctrl *aa_ctrl =
249 (struct mwifiex_ds_11n_amsdu_aggr_ctrl *) data_buf;
250 247
251 cmd->command = cpu_to_le16(HostCmd_CMD_AMSDU_AGGR_CTRL); 248 cmd->command = cpu_to_le16(HostCmd_CMD_AMSDU_AGGR_CTRL);
252 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_amsdu_aggr_ctrl) 249 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_amsdu_aggr_ctrl)
@@ -272,15 +269,13 @@ int mwifiex_cmd_amsdu_aggr_ctrl(struct host_cmd_ds_command *cmd,
272 * Handling includes changing the header fields into CPU format. 269 * Handling includes changing the header fields into CPU format.
273 */ 270 */
274int mwifiex_ret_amsdu_aggr_ctrl(struct host_cmd_ds_command *resp, 271int mwifiex_ret_amsdu_aggr_ctrl(struct host_cmd_ds_command *resp,
275 void *data_buf) 272 struct mwifiex_ds_11n_amsdu_aggr_ctrl
273 *amsdu_aggr_ctrl)
276{ 274{
277 struct mwifiex_ds_11n_amsdu_aggr_ctrl *amsdu_aggr_ctrl;
278 struct host_cmd_ds_amsdu_aggr_ctrl *amsdu_ctrl = 275 struct host_cmd_ds_amsdu_aggr_ctrl *amsdu_ctrl =
279 &resp->params.amsdu_aggr_ctrl; 276 &resp->params.amsdu_aggr_ctrl;
280 277
281 if (data_buf) { 278 if (amsdu_aggr_ctrl) {
282 amsdu_aggr_ctrl =
283 (struct mwifiex_ds_11n_amsdu_aggr_ctrl *) data_buf;
284 amsdu_aggr_ctrl->enable = le16_to_cpu(amsdu_ctrl->enable); 279 amsdu_aggr_ctrl->enable = le16_to_cpu(amsdu_ctrl->enable);
285 amsdu_aggr_ctrl->curr_buf_size = 280 amsdu_aggr_ctrl->curr_buf_size =
286 le16_to_cpu(amsdu_ctrl->curr_buf_size); 281 le16_to_cpu(amsdu_ctrl->curr_buf_size);
@@ -296,12 +291,10 @@ int mwifiex_ret_amsdu_aggr_ctrl(struct host_cmd_ds_command *resp,
296 * - Setting HT Tx capability and HT Tx information fields 291 * - Setting HT Tx capability and HT Tx information fields
297 * - Ensuring correct endian-ness 292 * - Ensuring correct endian-ness
298 */ 293 */
299int mwifiex_cmd_11n_cfg(struct host_cmd_ds_command *cmd, 294int mwifiex_cmd_11n_cfg(struct host_cmd_ds_command *cmd, u16 cmd_action,
300 u16 cmd_action, void *data_buf) 295 struct mwifiex_ds_11n_tx_cfg *txcfg)
301{ 296{
302 struct host_cmd_ds_11n_cfg *htcfg = &cmd->params.htcfg; 297 struct host_cmd_ds_11n_cfg *htcfg = &cmd->params.htcfg;
303 struct mwifiex_ds_11n_tx_cfg *txcfg =
304 (struct mwifiex_ds_11n_tx_cfg *) data_buf;
305 298
306 cmd->command = cpu_to_le16(HostCmd_CMD_11N_CFG); 299 cmd->command = cpu_to_le16(HostCmd_CMD_11N_CFG);
307 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_11n_cfg) + S_DS_GEN); 300 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_11n_cfg) + S_DS_GEN);
diff --git a/drivers/net/wireless/mwifiex/11n.h b/drivers/net/wireless/mwifiex/11n.h
index a4390a1a2a9f..90b421e343d4 100644
--- a/drivers/net/wireless/mwifiex/11n.h
+++ b/drivers/net/wireless/mwifiex/11n.h
@@ -29,9 +29,9 @@ int mwifiex_ret_11n_delba(struct mwifiex_private *priv,
29int mwifiex_ret_11n_addba_req(struct mwifiex_private *priv, 29int mwifiex_ret_11n_addba_req(struct mwifiex_private *priv,
30 struct host_cmd_ds_command *resp); 30 struct host_cmd_ds_command *resp);
31int mwifiex_ret_11n_cfg(struct host_cmd_ds_command *resp, 31int mwifiex_ret_11n_cfg(struct host_cmd_ds_command *resp,
32 void *data_buf); 32 struct mwifiex_ds_11n_tx_cfg *tx_cfg);
33int mwifiex_cmd_11n_cfg(struct host_cmd_ds_command *cmd, 33int mwifiex_cmd_11n_cfg(struct host_cmd_ds_command *cmd, u16 cmd_action,
34 u16 cmd_action, void *data_buf); 34 struct mwifiex_ds_11n_tx_cfg *txcfg);
35 35
36int mwifiex_cmd_append_11n_tlv(struct mwifiex_private *priv, 36int mwifiex_cmd_append_11n_tlv(struct mwifiex_private *priv,
37 struct mwifiex_bssdescriptor *bss_desc, 37 struct mwifiex_bssdescriptor *bss_desc,
@@ -62,12 +62,14 @@ int mwifiex_get_rx_reorder_tbl(struct mwifiex_private *priv,
62int mwifiex_get_tx_ba_stream_tbl(struct mwifiex_private *priv, 62int mwifiex_get_tx_ba_stream_tbl(struct mwifiex_private *priv,
63 struct mwifiex_ds_tx_ba_stream_tbl *buf); 63 struct mwifiex_ds_tx_ba_stream_tbl *buf);
64int mwifiex_ret_amsdu_aggr_ctrl(struct host_cmd_ds_command *resp, 64int mwifiex_ret_amsdu_aggr_ctrl(struct host_cmd_ds_command *resp,
65 void *data_buf); 65 struct mwifiex_ds_11n_amsdu_aggr_ctrl
66 *amsdu_aggr_ctrl);
66int mwifiex_cmd_recfg_tx_buf(struct mwifiex_private *priv, 67int mwifiex_cmd_recfg_tx_buf(struct mwifiex_private *priv,
67 struct host_cmd_ds_command *cmd, 68 struct host_cmd_ds_command *cmd,
68 int cmd_action, void *data_buf); 69 int cmd_action, u16 *buf_size);
69int mwifiex_cmd_amsdu_aggr_ctrl(struct host_cmd_ds_command *cmd, 70int mwifiex_cmd_amsdu_aggr_ctrl(struct host_cmd_ds_command *cmd,
70 int cmd_action, void *data_buf); 71 int cmd_action,
72 struct mwifiex_ds_11n_amsdu_aggr_ctrl *aa_ctrl);
71 73
72/* 74/*
73 * This function checks whether AMPDU is allowed or not for a particular TID. 75 * This function checks whether AMPDU is allowed or not for a particular TID.
diff --git a/drivers/net/wireless/mwifiex/11n_aggr.c b/drivers/net/wireless/mwifiex/11n_aggr.c
index f807447e4d99..1a453a605b3f 100644
--- a/drivers/net/wireless/mwifiex/11n_aggr.c
+++ b/drivers/net/wireless/mwifiex/11n_aggr.c
@@ -164,12 +164,13 @@ mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,
164 struct mwifiex_tx_param tx_param; 164 struct mwifiex_tx_param tx_param;
165 struct txpd *ptx_pd = NULL; 165 struct txpd *ptx_pd = NULL;
166 166
167 if (skb_queue_empty(&pra_list->skb_head)) { 167 skb_src = skb_peek(&pra_list->skb_head);
168 if (!skb_src) {
168 spin_unlock_irqrestore(&priv->wmm.ra_list_spinlock, 169 spin_unlock_irqrestore(&priv->wmm.ra_list_spinlock,
169 ra_list_flags); 170 ra_list_flags);
170 return 0; 171 return 0;
171 } 172 }
172 skb_src = skb_peek(&pra_list->skb_head); 173
173 tx_info_src = MWIFIEX_SKB_TXCB(skb_src); 174 tx_info_src = MWIFIEX_SKB_TXCB(skb_src);
174 skb_aggr = dev_alloc_skb(adapter->tx_buf_size); 175 skb_aggr = dev_alloc_skb(adapter->tx_buf_size);
175 if (!skb_aggr) { 176 if (!skb_aggr) {
@@ -184,17 +185,15 @@ mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,
184 tx_info_aggr->bss_index = tx_info_src->bss_index; 185 tx_info_aggr->bss_index = tx_info_src->bss_index;
185 skb_aggr->priority = skb_src->priority; 186 skb_aggr->priority = skb_src->priority;
186 187
187 while (skb_src && ((skb_headroom(skb_aggr) + skb_src->len 188 do {
188 + LLC_SNAP_LEN) 189 /* Check if AMSDU can accommodate this MSDU */
189 <= adapter->tx_buf_size)) { 190 if (skb_tailroom(skb_aggr) < (skb_src->len + LLC_SNAP_LEN))
191 break;
190 192
191 if (!skb_queue_empty(&pra_list->skb_head)) 193 skb_src = skb_dequeue(&pra_list->skb_head);
192 skb_src = skb_dequeue(&pra_list->skb_head);
193 else
194 skb_src = NULL;
195 194
196 if (skb_src) 195 pra_list->total_pkts_size -= skb_src->len;
197 pra_list->total_pkts_size -= skb_src->len; 196 pra_list->total_pkts--;
198 197
199 atomic_dec(&priv->wmm.tx_pkts_queued); 198 atomic_dec(&priv->wmm.tx_pkts_queued);
200 199
@@ -212,11 +211,15 @@ mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,
212 return -1; 211 return -1;
213 } 212 }
214 213
215 if (!skb_queue_empty(&pra_list->skb_head)) 214 if (skb_tailroom(skb_aggr) < pad) {
216 skb_src = skb_peek(&pra_list->skb_head); 215 pad = 0;
217 else 216 break;
218 skb_src = NULL; 217 }
219 } 218 skb_put(skb_aggr, pad);
219
220 skb_src = skb_peek(&pra_list->skb_head);
221
222 } while (skb_src);
220 223
221 spin_unlock_irqrestore(&priv->wmm.ra_list_spinlock, ra_list_flags); 224 spin_unlock_irqrestore(&priv->wmm.ra_list_spinlock, ra_list_flags);
222 225
@@ -230,11 +233,19 @@ mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,
230 233
231 skb_push(skb_aggr, headroom); 234 skb_push(skb_aggr, headroom);
232 235
233 tx_param.next_pkt_len = ((pra_list->total_pkts_size) ? 236 /*
234 (((pra_list->total_pkts_size) > 237 * Padding per MSDU will affect the length of next
235 adapter->tx_buf_size) ? adapter-> 238 * packet and hence the exact length of next packet
236 tx_buf_size : pra_list->total_pkts_size + 239 * is uncertain here.
237 LLC_SNAP_LEN + sizeof(struct txpd)) : 0); 240 *
241 * Also, aggregation of transmission buffer, while
242 * downloading the data to the card, wont gain much
243 * on the AMSDU packets as the AMSDU packets utilizes
244 * the transmission buffer space to the maximum
245 * (adapter->tx_buf_size).
246 */
247 tx_param.next_pkt_len = 0;
248
238 ret = adapter->if_ops.host_to_card(adapter, MWIFIEX_TYPE_DATA, 249 ret = adapter->if_ops.host_to_card(adapter, MWIFIEX_TYPE_DATA,
239 skb_aggr->data, 250 skb_aggr->data,
240 skb_aggr->len, &tx_param); 251 skb_aggr->len, &tx_param);
@@ -258,6 +269,7 @@ mwifiex_11n_aggregate_pkt(struct mwifiex_private *priv,
258 skb_queue_tail(&pra_list->skb_head, skb_aggr); 269 skb_queue_tail(&pra_list->skb_head, skb_aggr);
259 270
260 pra_list->total_pkts_size += skb_aggr->len; 271 pra_list->total_pkts_size += skb_aggr->len;
272 pra_list->total_pkts++;
261 273
262 atomic_inc(&priv->wmm.tx_pkts_queued); 274 atomic_inc(&priv->wmm.tx_pkts_queued);
263 275
diff --git a/drivers/net/wireless/mwifiex/11n_rxreorder.c b/drivers/net/wireless/mwifiex/11n_rxreorder.c
index e5dfdc39a921..7aa9aa0ac958 100644
--- a/drivers/net/wireless/mwifiex/11n_rxreorder.c
+++ b/drivers/net/wireless/mwifiex/11n_rxreorder.c
@@ -328,13 +328,12 @@ int mwifiex_cmd_11n_addba_req(struct host_cmd_ds_command *cmd, void *data_buf)
328 */ 328 */
329int mwifiex_cmd_11n_addba_rsp_gen(struct mwifiex_private *priv, 329int mwifiex_cmd_11n_addba_rsp_gen(struct mwifiex_private *priv,
330 struct host_cmd_ds_command *cmd, 330 struct host_cmd_ds_command *cmd,
331 void *data_buf) 331 struct host_cmd_ds_11n_addba_req
332 *cmd_addba_req)
332{ 333{
333 struct host_cmd_ds_11n_addba_rsp *add_ba_rsp = 334 struct host_cmd_ds_11n_addba_rsp *add_ba_rsp =
334 (struct host_cmd_ds_11n_addba_rsp *) 335 (struct host_cmd_ds_11n_addba_rsp *)
335 &cmd->params.add_ba_rsp; 336 &cmd->params.add_ba_rsp;
336 struct host_cmd_ds_11n_addba_req *cmd_addba_req =
337 (struct host_cmd_ds_11n_addba_req *) data_buf;
338 u8 tid; 337 u8 tid;
339 int win_size; 338 int win_size;
340 uint16_t block_ack_param_set; 339 uint16_t block_ack_param_set;
diff --git a/drivers/net/wireless/mwifiex/11n_rxreorder.h b/drivers/net/wireless/mwifiex/11n_rxreorder.h
index f3ca8c8c18f9..033c8adbdcd4 100644
--- a/drivers/net/wireless/mwifiex/11n_rxreorder.h
+++ b/drivers/net/wireless/mwifiex/11n_rxreorder.h
@@ -52,8 +52,9 @@ int mwifiex_ret_11n_addba_resp(struct mwifiex_private *priv,
52int mwifiex_cmd_11n_delba(struct host_cmd_ds_command *cmd, 52int mwifiex_cmd_11n_delba(struct host_cmd_ds_command *cmd,
53 void *data_buf); 53 void *data_buf);
54int mwifiex_cmd_11n_addba_rsp_gen(struct mwifiex_private *priv, 54int mwifiex_cmd_11n_addba_rsp_gen(struct mwifiex_private *priv,
55 struct host_cmd_ds_command 55 struct host_cmd_ds_command *cmd,
56 *cmd, void *data_buf); 56 struct host_cmd_ds_11n_addba_req
57 *cmd_addba_req);
57int mwifiex_cmd_11n_addba_req(struct host_cmd_ds_command *cmd, 58int mwifiex_cmd_11n_addba_req(struct host_cmd_ds_command *cmd,
58 void *data_buf); 59 void *data_buf);
59void mwifiex_11n_cleanup_reorder_tbl(struct mwifiex_private *priv); 60void mwifiex_11n_cleanup_reorder_tbl(struct mwifiex_private *priv);
diff --git a/drivers/net/wireless/mwifiex/cfg80211.c b/drivers/net/wireless/mwifiex/cfg80211.c
index 687c1f223497..352d2c5da1fc 100644
--- a/drivers/net/wireless/mwifiex/cfg80211.c
+++ b/drivers/net/wireless/mwifiex/cfg80211.c
@@ -672,6 +672,59 @@ static const u32 mwifiex_cipher_suites[] = {
672}; 672};
673 673
674/* 674/*
675 * CFG802.11 operation handler for setting bit rates.
676 *
677 * Function selects legacy bang B/G/BG from corresponding bitrates selection.
678 * Currently only 2.4GHz band is supported.
679 */
680static int mwifiex_cfg80211_set_bitrate_mask(struct wiphy *wiphy,
681 struct net_device *dev,
682 const u8 *peer,
683 const struct cfg80211_bitrate_mask *mask)
684{
685 struct mwifiex_ds_band_cfg band_cfg;
686 struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev);
687 int index = 0, mode = 0, i;
688
689 /* Currently only 2.4GHz is supported */
690 for (i = 0; i < mwifiex_band_2ghz.n_bitrates; i++) {
691 /*
692 * Rates below 6 Mbps in the table are CCK rates; 802.11b
693 * and from 6 they are OFDM; 802.11G
694 */
695 if (mwifiex_rates[i].bitrate == 60) {
696 index = 1 << i;
697 break;
698 }
699 }
700
701 if (mask->control[IEEE80211_BAND_2GHZ].legacy < index) {
702 mode = BAND_B;
703 } else {
704 mode = BAND_G;
705 if (mask->control[IEEE80211_BAND_2GHZ].legacy % index)
706 mode |= BAND_B;
707 }
708
709 memset(&band_cfg, 0, sizeof(band_cfg));
710 band_cfg.config_bands = mode;
711
712 if (priv->bss_mode == NL80211_IFTYPE_ADHOC)
713 band_cfg.adhoc_start_band = mode;
714
715 band_cfg.sec_chan_offset = NO_SEC_CHANNEL;
716
717 if (mwifiex_set_radio_band_cfg(priv, &band_cfg))
718 return -EFAULT;
719
720 wiphy_debug(wiphy, "info: device configured in 802.11%s%s mode\n",
721 (mode & BAND_B) ? "b" : "",
722 (mode & BAND_G) ? "g" : "");
723
724 return 0;
725}
726
727/*
675 * CFG802.11 operation handler for disconnection request. 728 * CFG802.11 operation handler for disconnection request.
676 * 729 *
677 * This function does not work when there is already a disconnection 730 * This function does not work when there is already a disconnection
@@ -960,7 +1013,7 @@ mwifiex_cfg80211_assoc(struct mwifiex_private *priv, size_t ssid_len, u8 *ssid,
960 ret = mwifiex_set_gen_ie(priv, sme->ie, sme->ie_len); 1013 ret = mwifiex_set_gen_ie(priv, sme->ie, sme->ie_len);
961 1014
962 if (sme->key) { 1015 if (sme->key) {
963 if (mwifiex_is_alg_wep(0) | mwifiex_is_alg_wep(0)) { 1016 if (mwifiex_is_alg_wep(priv->sec_info.encryption_mode)) {
964 dev_dbg(priv->adapter->dev, 1017 dev_dbg(priv->adapter->dev,
965 "info: setting wep encryption" 1018 "info: setting wep encryption"
966 " with key len %d\n", sme->key_len); 1019 " with key len %d\n", sme->key_len);
@@ -1225,6 +1278,7 @@ static struct cfg80211_ops mwifiex_cfg80211_ops = {
1225 .set_default_key = mwifiex_cfg80211_set_default_key, 1278 .set_default_key = mwifiex_cfg80211_set_default_key,
1226 .set_power_mgmt = mwifiex_cfg80211_set_power_mgmt, 1279 .set_power_mgmt = mwifiex_cfg80211_set_power_mgmt,
1227 .set_tx_power = mwifiex_cfg80211_set_tx_power, 1280 .set_tx_power = mwifiex_cfg80211_set_tx_power,
1281 .set_bitrate_mask = mwifiex_cfg80211_set_bitrate_mask,
1228}; 1282};
1229 1283
1230/* 1284/*
diff --git a/drivers/net/wireless/mwifiex/cmdevt.c b/drivers/net/wireless/mwifiex/cmdevt.c
index cd89fed206ae..b5352afb8714 100644
--- a/drivers/net/wireless/mwifiex/cmdevt.c
+++ b/drivers/net/wireless/mwifiex/cmdevt.c
@@ -104,13 +104,11 @@ mwifiex_clean_cmd_node(struct mwifiex_adapter *adapter,
104 * main thread. 104 * main thread.
105 */ 105 */
106static int mwifiex_cmd_host_cmd(struct mwifiex_private *priv, 106static int mwifiex_cmd_host_cmd(struct mwifiex_private *priv,
107 struct host_cmd_ds_command *cmd, void *data_buf) 107 struct host_cmd_ds_command *cmd,
108 struct mwifiex_ds_misc_cmd *pcmd_ptr)
108{ 109{
109 struct mwifiex_ds_misc_cmd *pcmd_ptr =
110 (struct mwifiex_ds_misc_cmd *) data_buf;
111
112 /* Copy the HOST command to command buffer */ 110 /* Copy the HOST command to command buffer */
113 memcpy((void *) cmd, pcmd_ptr->cmd, pcmd_ptr->len); 111 memcpy(cmd, pcmd_ptr->cmd, pcmd_ptr->len);
114 dev_dbg(priv->adapter->dev, "cmd: host cmd size = %d\n", pcmd_ptr->len); 112 dev_dbg(priv->adapter->dev, "cmd: host cmd size = %d\n", pcmd_ptr->len);
115 return 0; 113 return 0;
116} 114}
@@ -707,15 +705,14 @@ int mwifiex_process_cmdresp(struct mwifiex_adapter *adapter)
707 705
708 if (adapter->curr_cmd->cmd_flag & CMD_F_HOSTCMD) { 706 if (adapter->curr_cmd->cmd_flag & CMD_F_HOSTCMD) {
709 /* Copy original response back to response buffer */ 707 /* Copy original response back to response buffer */
710 struct mwifiex_ds_misc_cmd *hostcmd = NULL; 708 struct mwifiex_ds_misc_cmd *hostcmd;
711 uint16_t size = le16_to_cpu(resp->size); 709 uint16_t size = le16_to_cpu(resp->size);
712 dev_dbg(adapter->dev, "info: host cmd resp size = %d\n", size); 710 dev_dbg(adapter->dev, "info: host cmd resp size = %d\n", size);
713 size = min_t(u16, size, MWIFIEX_SIZE_OF_CMD_BUFFER); 711 size = min_t(u16, size, MWIFIEX_SIZE_OF_CMD_BUFFER);
714 if (adapter->curr_cmd->data_buf) { 712 if (adapter->curr_cmd->data_buf) {
715 hostcmd = (struct mwifiex_ds_misc_cmd *) 713 hostcmd = adapter->curr_cmd->data_buf;
716 adapter->curr_cmd->data_buf;
717 hostcmd->len = size; 714 hostcmd->len = size;
718 memcpy(hostcmd->cmd, (void *) resp, size); 715 memcpy(hostcmd->cmd, resp, size);
719 } 716 }
720 } 717 }
721 orig_cmdresp_no = le16_to_cpu(resp->command); 718 orig_cmdresp_no = le16_to_cpu(resp->command);
@@ -1155,7 +1152,7 @@ EXPORT_SYMBOL_GPL(mwifiex_process_sleep_confirm_resp);
1155int mwifiex_cmd_enh_power_mode(struct mwifiex_private *priv, 1152int mwifiex_cmd_enh_power_mode(struct mwifiex_private *priv,
1156 struct host_cmd_ds_command *cmd, 1153 struct host_cmd_ds_command *cmd,
1157 u16 cmd_action, uint16_t ps_bitmap, 1154 u16 cmd_action, uint16_t ps_bitmap,
1158 void *data_buf) 1155 struct mwifiex_ds_auto_ds *auto_ds)
1159{ 1156{
1160 struct host_cmd_ds_802_11_ps_mode_enh *psmode_enh = 1157 struct host_cmd_ds_802_11_ps_mode_enh *psmode_enh =
1161 &cmd->params.psmode_enh; 1158 &cmd->params.psmode_enh;
@@ -1218,9 +1215,8 @@ int mwifiex_cmd_enh_power_mode(struct mwifiex_private *priv,
1218 sizeof(struct mwifiex_ie_types_header)); 1215 sizeof(struct mwifiex_ie_types_header));
1219 cmd_size += sizeof(*auto_ds_tlv); 1216 cmd_size += sizeof(*auto_ds_tlv);
1220 tlv += sizeof(*auto_ds_tlv); 1217 tlv += sizeof(*auto_ds_tlv);
1221 if (data_buf) 1218 if (auto_ds)
1222 idletime = ((struct mwifiex_ds_auto_ds *) 1219 idletime = auto_ds->idle_time;
1223 data_buf)->idle_time;
1224 dev_dbg(priv->adapter->dev, 1220 dev_dbg(priv->adapter->dev,
1225 "cmd: PS Command: Enter Auto Deep Sleep\n"); 1221 "cmd: PS Command: Enter Auto Deep Sleep\n");
1226 auto_ds_tlv->deep_sleep_timeout = cpu_to_le16(idletime); 1222 auto_ds_tlv->deep_sleep_timeout = cpu_to_le16(idletime);
@@ -1239,7 +1235,7 @@ int mwifiex_cmd_enh_power_mode(struct mwifiex_private *priv,
1239 */ 1235 */
1240int mwifiex_ret_enh_power_mode(struct mwifiex_private *priv, 1236int mwifiex_ret_enh_power_mode(struct mwifiex_private *priv,
1241 struct host_cmd_ds_command *resp, 1237 struct host_cmd_ds_command *resp,
1242 void *data_buf) 1238 struct mwifiex_ds_pm_cfg *pm_cfg)
1243{ 1239{
1244 struct mwifiex_adapter *adapter = priv->adapter; 1240 struct mwifiex_adapter *adapter = priv->adapter;
1245 struct host_cmd_ds_802_11_ps_mode_enh *ps_mode = 1241 struct host_cmd_ds_802_11_ps_mode_enh *ps_mode =
@@ -1282,10 +1278,8 @@ int mwifiex_ret_enh_power_mode(struct mwifiex_private *priv,
1282 1278
1283 dev_dbg(adapter->dev, "cmd: ps_bitmap=%#x\n", ps_bitmap); 1279 dev_dbg(adapter->dev, "cmd: ps_bitmap=%#x\n", ps_bitmap);
1284 1280
1285 if (data_buf) { 1281 if (pm_cfg) {
1286 /* This section is for get power save mode */ 1282 /* This section is for get power save mode */
1287 struct mwifiex_ds_pm_cfg *pm_cfg =
1288 (struct mwifiex_ds_pm_cfg *)data_buf;
1289 if (ps_bitmap & BITMAP_STA_PS) 1283 if (ps_bitmap & BITMAP_STA_PS)
1290 pm_cfg->param.ps_mode = 1; 1284 pm_cfg->param.ps_mode = 1;
1291 else 1285 else
diff --git a/drivers/net/wireless/mwifiex/debugfs.c b/drivers/net/wireless/mwifiex/debugfs.c
index 46d65e02c7ba..d26a78b6b3c4 100644
--- a/drivers/net/wireless/mwifiex/debugfs.c
+++ b/drivers/net/wireless/mwifiex/debugfs.c
@@ -27,8 +27,8 @@ static struct dentry *mwifiex_dfs_dir;
27 27
28static char *bss_modes[] = { 28static char *bss_modes[] = {
29 "Unknown", 29 "Unknown",
30 "Managed",
31 "Ad-hoc", 30 "Ad-hoc",
31 "Managed",
32 "Auto" 32 "Auto"
33}; 33};
34 34
@@ -216,28 +216,19 @@ mwifiex_info_read(struct file *file, char __user *ubuf,
216 p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]); 216 p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
217 p += sprintf(p, "media_state=\"%s\"\n", 217 p += sprintf(p, "media_state=\"%s\"\n",
218 (!priv->media_connected ? "Disconnected" : "Connected")); 218 (!priv->media_connected ? "Disconnected" : "Connected"));
219 p += sprintf(p, "mac_address=\"%02x:%02x:%02x:%02x:%02x:%02x\"\n", 219 p += sprintf(p, "mac_address=\"%pM\"\n", netdev->dev_addr);
220 netdev->dev_addr[0], netdev->dev_addr[1],
221 netdev->dev_addr[2], netdev->dev_addr[3],
222 netdev->dev_addr[4], netdev->dev_addr[5]);
223 220
224 if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_STA) { 221 if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_STA) {
225 p += sprintf(p, "multicast_count=\"%d\"\n", 222 p += sprintf(p, "multicast_count=\"%d\"\n",
226 netdev_mc_count(netdev)); 223 netdev_mc_count(netdev));
227 p += sprintf(p, "essid=\"%s\"\n", info.ssid.ssid); 224 p += sprintf(p, "essid=\"%s\"\n", info.ssid.ssid);
228 p += sprintf(p, "bssid=\"%02x:%02x:%02x:%02x:%02x:%02x\"\n", 225 p += sprintf(p, "bssid=\"%pM\"\n", info.bssid);
229 info.bssid[0], info.bssid[1],
230 info.bssid[2], info.bssid[3],
231 info.bssid[4], info.bssid[5]);
232 p += sprintf(p, "channel=\"%d\"\n", (int) info.bss_chan); 226 p += sprintf(p, "channel=\"%d\"\n", (int) info.bss_chan);
233 p += sprintf(p, "region_code = \"%02x\"\n", info.region_code); 227 p += sprintf(p, "region_code = \"%02x\"\n", info.region_code);
234 228
235 netdev_for_each_mc_addr(ha, netdev) 229 netdev_for_each_mc_addr(ha, netdev)
236 p += sprintf(p, "multicast_address[%d]=" 230 p += sprintf(p, "multicast_address[%d]=\"%pM\"\n",
237 "\"%02x:%02x:%02x:%02x:%02x:%02x\"\n", i++, 231 i++, ha->addr);
238 ha->addr[0], ha->addr[1],
239 ha->addr[2], ha->addr[3],
240 ha->addr[4], ha->addr[5]);
241 } 232 }
242 233
243 p += sprintf(p, "num_tx_bytes = %lu\n", priv->stats.tx_bytes); 234 p += sprintf(p, "num_tx_bytes = %lu\n", priv->stats.tx_bytes);
@@ -451,26 +442,18 @@ mwifiex_debug_read(struct file *file, char __user *ubuf,
451 if (info.tx_tbl_num) { 442 if (info.tx_tbl_num) {
452 p += sprintf(p, "Tx BA stream table:\n"); 443 p += sprintf(p, "Tx BA stream table:\n");
453 for (i = 0; i < info.tx_tbl_num; i++) 444 for (i = 0; i < info.tx_tbl_num; i++)
454 p += sprintf(p, "tid = %d, " 445 p += sprintf(p, "tid = %d, ra = %pM\n",
455 "ra = %02x:%02x:%02x:%02x:%02x:%02x\n", 446 info.tx_tbl[i].tid, info.tx_tbl[i].ra);
456 info.tx_tbl[i].tid, info.tx_tbl[i].ra[0],
457 info.tx_tbl[i].ra[1], info.tx_tbl[i].ra[2],
458 info.tx_tbl[i].ra[3], info.tx_tbl[i].ra[4],
459 info.tx_tbl[i].ra[5]);
460 } 447 }
461 448
462 if (info.rx_tbl_num) { 449 if (info.rx_tbl_num) {
463 p += sprintf(p, "Rx reorder table:\n"); 450 p += sprintf(p, "Rx reorder table:\n");
464 for (i = 0; i < info.rx_tbl_num; i++) { 451 for (i = 0; i < info.rx_tbl_num; i++) {
465 452 p += sprintf(p, "tid = %d, ta = %pM, "
466 p += sprintf(p, "tid = %d, "
467 "ta = %02x:%02x:%02x:%02x:%02x:%02x, "
468 "start_win = %d, " 453 "start_win = %d, "
469 "win_size = %d, buffer: ", 454 "win_size = %d, buffer: ",
470 info.rx_tbl[i].tid, 455 info.rx_tbl[i].tid,
471 info.rx_tbl[i].ta[0], info.rx_tbl[i].ta[1], 456 info.rx_tbl[i].ta,
472 info.rx_tbl[i].ta[2], info.rx_tbl[i].ta[3],
473 info.rx_tbl[i].ta[4], info.rx_tbl[i].ta[5],
474 info.rx_tbl[i].start_win, 457 info.rx_tbl[i].start_win,
475 info.rx_tbl[i].win_size); 458 info.rx_tbl[i].win_size);
476 459
diff --git a/drivers/net/wireless/mwifiex/decl.h b/drivers/net/wireless/mwifiex/decl.h
index 0e90b0986ed8..94ddc9038cb3 100644
--- a/drivers/net/wireless/mwifiex/decl.h
+++ b/drivers/net/wireless/mwifiex/decl.h
@@ -30,7 +30,9 @@
30 30
31#define MWIFIEX_MAX_BSS_NUM (1) 31#define MWIFIEX_MAX_BSS_NUM (1)
32 32
33#define MWIFIEX_MIN_DATA_HEADER_LEN 32 /* (sizeof(mwifiex_txpd)) */ 33#define MWIFIEX_MIN_DATA_HEADER_LEN 36 /* sizeof(mwifiex_txpd)
34 * + 4 byte alignment
35 */
34 36
35#define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED 2 37#define MWIFIEX_MAX_TX_BASTREAM_SUPPORTED 2
36#define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED 16 38#define MWIFIEX_MAX_RX_BASTREAM_SUPPORTED 16
diff --git a/drivers/net/wireless/mwifiex/fw.h b/drivers/net/wireless/mwifiex/fw.h
index afdd145dff0b..4fee0993b186 100644
--- a/drivers/net/wireless/mwifiex/fw.h
+++ b/drivers/net/wireless/mwifiex/fw.h
@@ -157,6 +157,17 @@ enum MWIFIEX_802_11_WEP_STATUS {
157#define ISSUPP_RXSTBC(Dot11nDevCap) (Dot11nDevCap & BIT(26)) 157#define ISSUPP_RXSTBC(Dot11nDevCap) (Dot11nDevCap & BIT(26))
158#define ISSUPP_GREENFIELD(Dot11nDevCap) (Dot11nDevCap & BIT(29)) 158#define ISSUPP_GREENFIELD(Dot11nDevCap) (Dot11nDevCap & BIT(29))
159 159
160/* httxcfg bitmap
161 * 0 reserved
162 * 1 20/40 Mhz enable(1)/disable(0)
163 * 2-3 reserved
164 * 4 green field enable(1)/disable(0)
165 * 5 short GI in 20 Mhz enable(1)/disable(0)
166 * 6 short GI in 40 Mhz enable(1)/disable(0)
167 * 7-15 reserved
168 */
169#define MWIFIEX_FW_DEF_HTTXCFG (BIT(1) | BIT(4) | BIT(5) | BIT(6))
170
160#define GET_RXMCSSUPP(DevMCSSupported) (DevMCSSupported & 0x0f) 171#define GET_RXMCSSUPP(DevMCSSupported) (DevMCSSupported & 0x0f)
161#define SETHT_MCS32(x) (x[4] |= 1) 172#define SETHT_MCS32(x) (x[4] |= 1)
162 173
diff --git a/drivers/net/wireless/mwifiex/ioctl.h b/drivers/net/wireless/mwifiex/ioctl.h
index 7c1c5ee40eb9..f6bcc868562f 100644
--- a/drivers/net/wireless/mwifiex/ioctl.h
+++ b/drivers/net/wireless/mwifiex/ioctl.h
@@ -249,6 +249,7 @@ struct mwifiex_ds_hs_cfg {
249}; 249};
250 250
251#define DEEP_SLEEP_ON 1 251#define DEEP_SLEEP_ON 1
252#define DEEP_SLEEP_OFF 0
252#define DEEP_SLEEP_IDLE_TIME 100 253#define DEEP_SLEEP_IDLE_TIME 100
253#define PS_MODE_AUTO 1 254#define PS_MODE_AUTO 1
254 255
diff --git a/drivers/net/wireless/mwifiex/join.c b/drivers/net/wireless/mwifiex/join.c
index 5eab3dc29b1c..644e2e405cb5 100644
--- a/drivers/net/wireless/mwifiex/join.c
+++ b/drivers/net/wireless/mwifiex/join.c
@@ -364,10 +364,9 @@ static int mwifiex_append_rsn_ie_wpa_wpa2(struct mwifiex_private *priv,
364 */ 364 */
365int mwifiex_cmd_802_11_associate(struct mwifiex_private *priv, 365int mwifiex_cmd_802_11_associate(struct mwifiex_private *priv,
366 struct host_cmd_ds_command *cmd, 366 struct host_cmd_ds_command *cmd,
367 void *data_buf) 367 struct mwifiex_bssdescriptor *bss_desc)
368{ 368{
369 struct host_cmd_ds_802_11_associate *assoc = &cmd->params.associate; 369 struct host_cmd_ds_802_11_associate *assoc = &cmd->params.associate;
370 struct mwifiex_bssdescriptor *bss_desc;
371 struct mwifiex_ie_types_ssid_param_set *ssid_tlv; 370 struct mwifiex_ie_types_ssid_param_set *ssid_tlv;
372 struct mwifiex_ie_types_phy_param_set *phy_tlv; 371 struct mwifiex_ie_types_phy_param_set *phy_tlv;
373 struct mwifiex_ie_types_ss_param_set *ss_tlv; 372 struct mwifiex_ie_types_ss_param_set *ss_tlv;
@@ -380,7 +379,6 @@ int mwifiex_cmd_802_11_associate(struct mwifiex_private *priv,
380 u8 *pos; 379 u8 *pos;
381 int rsn_ie_len = 0; 380 int rsn_ie_len = 0;
382 381
383 bss_desc = (struct mwifiex_bssdescriptor *) data_buf;
384 pos = (u8 *) assoc; 382 pos = (u8 *) assoc;
385 383
386 mwifiex_cfg_tx_buf(priv, bss_desc); 384 mwifiex_cfg_tx_buf(priv, bss_desc);
@@ -748,7 +746,8 @@ done:
748 */ 746 */
749int 747int
750mwifiex_cmd_802_11_ad_hoc_start(struct mwifiex_private *priv, 748mwifiex_cmd_802_11_ad_hoc_start(struct mwifiex_private *priv,
751 struct host_cmd_ds_command *cmd, void *data_buf) 749 struct host_cmd_ds_command *cmd,
750 struct mwifiex_802_11_ssid *req_ssid)
752{ 751{
753 int rsn_ie_len = 0; 752 int rsn_ie_len = 0;
754 struct mwifiex_adapter *adapter = priv->adapter; 753 struct mwifiex_adapter *adapter = priv->adapter;
@@ -786,20 +785,15 @@ mwifiex_cmd_802_11_ad_hoc_start(struct mwifiex_private *priv,
786 785
787 memset(adhoc_start->ssid, 0, IEEE80211_MAX_SSID_LEN); 786 memset(adhoc_start->ssid, 0, IEEE80211_MAX_SSID_LEN);
788 787
789 memcpy(adhoc_start->ssid, 788 memcpy(adhoc_start->ssid, req_ssid->ssid, req_ssid->ssid_len);
790 ((struct mwifiex_802_11_ssid *) data_buf)->ssid,
791 ((struct mwifiex_802_11_ssid *) data_buf)->ssid_len);
792 789
793 dev_dbg(adapter->dev, "info: ADHOC_S_CMD: SSID = %s\n", 790 dev_dbg(adapter->dev, "info: ADHOC_S_CMD: SSID = %s\n",
794 adhoc_start->ssid); 791 adhoc_start->ssid);
795 792
796 memset(bss_desc->ssid.ssid, 0, IEEE80211_MAX_SSID_LEN); 793 memset(bss_desc->ssid.ssid, 0, IEEE80211_MAX_SSID_LEN);
797 memcpy(bss_desc->ssid.ssid, 794 memcpy(bss_desc->ssid.ssid, req_ssid->ssid, req_ssid->ssid_len);
798 ((struct mwifiex_802_11_ssid *) data_buf)->ssid,
799 ((struct mwifiex_802_11_ssid *) data_buf)->ssid_len);
800 795
801 bss_desc->ssid.ssid_len = 796 bss_desc->ssid.ssid_len = req_ssid->ssid_len;
802 ((struct mwifiex_802_11_ssid *) data_buf)->ssid_len;
803 797
804 /* Set the BSS mode */ 798 /* Set the BSS mode */
805 adhoc_start->bss_mode = HostCmd_BSS_MODE_IBSS; 799 adhoc_start->bss_mode = HostCmd_BSS_MODE_IBSS;
@@ -1036,13 +1030,12 @@ mwifiex_cmd_802_11_ad_hoc_start(struct mwifiex_private *priv,
1036 */ 1030 */
1037int 1031int
1038mwifiex_cmd_802_11_ad_hoc_join(struct mwifiex_private *priv, 1032mwifiex_cmd_802_11_ad_hoc_join(struct mwifiex_private *priv,
1039 struct host_cmd_ds_command *cmd, void *data_buf) 1033 struct host_cmd_ds_command *cmd,
1034 struct mwifiex_bssdescriptor *bss_desc)
1040{ 1035{
1041 int rsn_ie_len = 0; 1036 int rsn_ie_len = 0;
1042 struct host_cmd_ds_802_11_ad_hoc_join *adhoc_join = 1037 struct host_cmd_ds_802_11_ad_hoc_join *adhoc_join =
1043 &cmd->params.adhoc_join; 1038 &cmd->params.adhoc_join;
1044 struct mwifiex_bssdescriptor *bss_desc =
1045 (struct mwifiex_bssdescriptor *) data_buf;
1046 struct mwifiex_ie_types_chan_list_param_set *chan_tlv; 1039 struct mwifiex_ie_types_chan_list_param_set *chan_tlv;
1047 u32 cmd_append_size = 0; 1040 u32 cmd_append_size = 0;
1048 u16 tmp_cap; 1041 u16 tmp_cap;
diff --git a/drivers/net/wireless/mwifiex/main.c b/drivers/net/wireless/mwifiex/main.c
index f0582259c935..e5fc53dc6887 100644
--- a/drivers/net/wireless/mwifiex/main.c
+++ b/drivers/net/wireless/mwifiex/main.c
@@ -26,17 +26,12 @@
26 26
27const char driver_version[] = "mwifiex " VERSION " (%s) "; 27const char driver_version[] = "mwifiex " VERSION " (%s) ";
28 28
29struct mwifiex_adapter *g_adapter;
30EXPORT_SYMBOL_GPL(g_adapter);
31
32static struct mwifiex_bss_attr mwifiex_bss_sta[] = { 29static struct mwifiex_bss_attr mwifiex_bss_sta[] = {
33 {MWIFIEX_BSS_TYPE_STA, MWIFIEX_DATA_FRAME_TYPE_ETH_II, true, 0, 0}, 30 {MWIFIEX_BSS_TYPE_STA, MWIFIEX_DATA_FRAME_TYPE_ETH_II, true, 0, 0},
34}; 31};
35 32
36static int drv_mode = DRV_MODE_STA; 33static int drv_mode = DRV_MODE_STA;
37 34
38static char fw_name[32] = DEFAULT_FW_NAME;
39
40/* Supported drv_mode table */ 35/* Supported drv_mode table */
41static struct mwifiex_drv_mode mwifiex_drv_mode_tbl[] = { 36static struct mwifiex_drv_mode mwifiex_drv_mode_tbl[] = {
42 { 37 {
@@ -62,7 +57,8 @@ static struct mwifiex_drv_mode mwifiex_drv_mode_tbl[] = {
62 * proper cleanup before exiting. 57 * proper cleanup before exiting.
63 */ 58 */
64static int mwifiex_register(void *card, struct mwifiex_if_ops *if_ops, 59static int mwifiex_register(void *card, struct mwifiex_if_ops *if_ops,
65 struct mwifiex_drv_mode *drv_mode_ptr) 60 struct mwifiex_drv_mode *drv_mode_ptr,
61 void **padapter)
66{ 62{
67 struct mwifiex_adapter *adapter; 63 struct mwifiex_adapter *adapter;
68 int i; 64 int i;
@@ -71,7 +67,7 @@ static int mwifiex_register(void *card, struct mwifiex_if_ops *if_ops,
71 if (!adapter) 67 if (!adapter)
72 return -ENOMEM; 68 return -ENOMEM;
73 69
74 g_adapter = adapter; 70 *padapter = adapter;
75 adapter->card = card; 71 adapter->card = card;
76 72
77 /* Save interface specific operations in adapter */ 73 /* Save interface specific operations in adapter */
@@ -326,7 +322,7 @@ exit_main_proc:
326 * and initializing the private structures. 322 * and initializing the private structures.
327 */ 323 */
328static int 324static int
329mwifiex_init_sw(void *card, struct mwifiex_if_ops *if_ops) 325mwifiex_init_sw(void *card, struct mwifiex_if_ops *if_ops, void **padapter)
330{ 326{
331 int i; 327 int i;
332 struct mwifiex_drv_mode *drv_mode_ptr; 328 struct mwifiex_drv_mode *drv_mode_ptr;
@@ -345,7 +341,7 @@ mwifiex_init_sw(void *card, struct mwifiex_if_ops *if_ops)
345 return -1; 341 return -1;
346 } 342 }
347 343
348 if (mwifiex_register(card, if_ops, drv_mode_ptr)) 344 if (mwifiex_register(card, if_ops, drv_mode_ptr, padapter))
349 return -1; 345 return -1;
350 346
351 return 0; 347 return 0;
@@ -384,20 +380,8 @@ static int mwifiex_init_hw_fw(struct mwifiex_adapter *adapter)
384 380
385 memset(&fw, 0, sizeof(struct mwifiex_fw_image)); 381 memset(&fw, 0, sizeof(struct mwifiex_fw_image));
386 382
387 switch (adapter->revision_id) { 383 err = request_firmware(&adapter->firmware, adapter->fw_name,
388 case SD8787_W0: 384 adapter->dev);
389 case SD8787_W1:
390 strcpy(fw_name, SD8787_W1_FW_NAME);
391 break;
392 case SD8787_A0:
393 case SD8787_A1:
394 strcpy(fw_name, SD8787_AX_FW_NAME);
395 break;
396 default:
397 break;
398 }
399
400 err = request_firmware(&adapter->firmware, fw_name, adapter->dev);
401 if (err < 0) { 385 if (err < 0) {
402 dev_err(adapter->dev, "request_firmware() returned" 386 dev_err(adapter->dev, "request_firmware() returned"
403 " error code %#x\n", err); 387 " error code %#x\n", err);
@@ -569,7 +553,7 @@ static int
569mwifiex_set_mac_address(struct net_device *dev, void *addr) 553mwifiex_set_mac_address(struct net_device *dev, void *addr)
570{ 554{
571 struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev); 555 struct mwifiex_private *priv = mwifiex_netdev_get_priv(dev);
572 struct sockaddr *hw_addr = (struct sockaddr *) addr; 556 struct sockaddr *hw_addr = addr;
573 int ret; 557 int ret;
574 558
575 memcpy(priv->curr_addr, hw_addr->sa_data, ETH_ALEN); 559 memcpy(priv->curr_addr, hw_addr->sa_data, ETH_ALEN);
@@ -869,13 +853,11 @@ mwifiex_add_card(void *card, struct semaphore *sem,
869 if (down_interruptible(sem)) 853 if (down_interruptible(sem))
870 goto exit_sem_err; 854 goto exit_sem_err;
871 855
872 if (mwifiex_init_sw(card, if_ops)) { 856 if (mwifiex_init_sw(card, if_ops, (void **)&adapter)) {
873 pr_err("%s: software init failed\n", __func__); 857 pr_err("%s: software init failed\n", __func__);
874 goto err_init_sw; 858 goto err_init_sw;
875 } 859 }
876 860
877 adapter = g_adapter;
878
879 adapter->hw_status = MWIFIEX_HW_STATUS_INITIALIZING; 861 adapter->hw_status = MWIFIEX_HW_STATUS_INITIALIZING;
880 adapter->surprise_removed = false; 862 adapter->surprise_removed = false;
881 init_waitqueue_head(&adapter->init_wait_q); 863 init_waitqueue_head(&adapter->init_wait_q);
diff --git a/drivers/net/wireless/mwifiex/main.h b/drivers/net/wireless/mwifiex/main.h
index 8316b3cd92cd..2215c3c97354 100644
--- a/drivers/net/wireless/mwifiex/main.h
+++ b/drivers/net/wireless/mwifiex/main.h
@@ -39,7 +39,6 @@
39#include "fw.h" 39#include "fw.h"
40 40
41extern const char driver_version[]; 41extern const char driver_version[];
42extern struct mwifiex_adapter *g_adapter;
43 42
44enum { 43enum {
45 MWIFIEX_ASYNC_CMD, 44 MWIFIEX_ASYNC_CMD,
@@ -48,15 +47,6 @@ enum {
48 47
49#define DRV_MODE_STA 0x1 48#define DRV_MODE_STA 0x1
50 49
51#define SD8787_W0 0x30
52#define SD8787_W1 0x31
53#define SD8787_A0 0x40
54#define SD8787_A1 0x41
55
56#define DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
57#define SD8787_W1_FW_NAME "mrvl/sd8787_uapsta_w1.bin"
58#define SD8787_AX_FW_NAME "mrvl/sd8787_uapsta.bin"
59
60struct mwifiex_drv_mode { 50struct mwifiex_drv_mode {
61 u16 drv_mode; 51 u16 drv_mode;
62 u16 intf_num; 52 u16 intf_num;
@@ -190,6 +180,7 @@ struct mwifiex_ra_list_tbl {
190 struct sk_buff_head skb_head; 180 struct sk_buff_head skb_head;
191 u8 ra[ETH_ALEN]; 181 u8 ra[ETH_ALEN];
192 u32 total_pkts_size; 182 u32 total_pkts_size;
183 u32 total_pkts;
193 u32 is_11n_enabled; 184 u32 is_11n_enabled;
194}; 185};
195 186
@@ -576,10 +567,10 @@ struct mwifiex_adapter {
576 u8 priv_num; 567 u8 priv_num;
577 struct mwifiex_drv_mode *drv_mode; 568 struct mwifiex_drv_mode *drv_mode;
578 const struct firmware *firmware; 569 const struct firmware *firmware;
570 char fw_name[32];
579 struct device *dev; 571 struct device *dev;
580 bool surprise_removed; 572 bool surprise_removed;
581 u32 fw_release_number; 573 u32 fw_release_number;
582 u32 revision_id;
583 u16 init_wait_q_woken; 574 u16 init_wait_q_woken;
584 wait_queue_head_t init_wait_q; 575 wait_queue_head_t init_wait_q;
585 void *card; 576 void *card;
@@ -745,10 +736,10 @@ void mwifiex_process_sleep_confirm_resp(struct mwifiex_adapter *, u8 *,
745int mwifiex_cmd_enh_power_mode(struct mwifiex_private *priv, 736int mwifiex_cmd_enh_power_mode(struct mwifiex_private *priv,
746 struct host_cmd_ds_command *cmd, 737 struct host_cmd_ds_command *cmd,
747 u16 cmd_action, uint16_t ps_bitmap, 738 u16 cmd_action, uint16_t ps_bitmap,
748 void *data_buf); 739 struct mwifiex_ds_auto_ds *auto_ds);
749int mwifiex_ret_enh_power_mode(struct mwifiex_private *priv, 740int mwifiex_ret_enh_power_mode(struct mwifiex_private *priv,
750 struct host_cmd_ds_command *resp, 741 struct host_cmd_ds_command *resp,
751 void *data_buf); 742 struct mwifiex_ds_pm_cfg *pm_cfg);
752void mwifiex_process_hs_config(struct mwifiex_adapter *adapter); 743void mwifiex_process_hs_config(struct mwifiex_adapter *adapter);
753void mwifiex_hs_activated_event(struct mwifiex_private *priv, 744void mwifiex_hs_activated_event(struct mwifiex_private *priv,
754 u8 activated); 745 u8 activated);
@@ -760,7 +751,7 @@ int mwifiex_sta_prepare_cmd(struct mwifiex_private *, uint16_t cmd_no,
760 u16 cmd_action, u32 cmd_oid, 751 u16 cmd_action, u32 cmd_oid,
761 void *data_buf, void *cmd_buf); 752 void *data_buf, void *cmd_buf);
762int mwifiex_process_sta_cmdresp(struct mwifiex_private *, u16 cmdresp_no, 753int mwifiex_process_sta_cmdresp(struct mwifiex_private *, u16 cmdresp_no,
763 void *cmd_buf); 754 struct host_cmd_ds_command *resp);
764int mwifiex_process_sta_rx_packet(struct mwifiex_adapter *, 755int mwifiex_process_sta_rx_packet(struct mwifiex_adapter *,
765 struct sk_buff *skb); 756 struct sk_buff *skb);
766int mwifiex_process_sta_event(struct mwifiex_private *); 757int mwifiex_process_sta_event(struct mwifiex_private *);
@@ -769,7 +760,7 @@ int mwifiex_sta_init_cmd(struct mwifiex_private *, u8 first_sta);
769int mwifiex_scan_networks(struct mwifiex_private *priv, 760int mwifiex_scan_networks(struct mwifiex_private *priv,
770 const struct mwifiex_user_scan_cfg *user_scan_in); 761 const struct mwifiex_user_scan_cfg *user_scan_in);
771int mwifiex_cmd_802_11_scan(struct host_cmd_ds_command *cmd, 762int mwifiex_cmd_802_11_scan(struct host_cmd_ds_command *cmd,
772 void *data_buf); 763 struct mwifiex_scan_cmd_config *scan_cfg);
773void mwifiex_queue_scan_cmd(struct mwifiex_private *priv, 764void mwifiex_queue_scan_cmd(struct mwifiex_private *priv,
774 struct cmd_ctrl_node *cmd_node); 765 struct cmd_ctrl_node *cmd_node);
775int mwifiex_ret_802_11_scan(struct mwifiex_private *priv, 766int mwifiex_ret_802_11_scan(struct mwifiex_private *priv,
@@ -786,8 +777,8 @@ s32 mwifiex_ssid_cmp(struct mwifiex_802_11_ssid *ssid1,
786int mwifiex_associate(struct mwifiex_private *priv, 777int mwifiex_associate(struct mwifiex_private *priv,
787 struct mwifiex_bssdescriptor *bss_desc); 778 struct mwifiex_bssdescriptor *bss_desc);
788int mwifiex_cmd_802_11_associate(struct mwifiex_private *priv, 779int mwifiex_cmd_802_11_associate(struct mwifiex_private *priv,
789 struct host_cmd_ds_command 780 struct host_cmd_ds_command *cmd,
790 *cmd, void *data_buf); 781 struct mwifiex_bssdescriptor *bss_desc);
791int mwifiex_ret_802_11_associate(struct mwifiex_private *priv, 782int mwifiex_ret_802_11_associate(struct mwifiex_private *priv,
792 struct host_cmd_ds_command *resp); 783 struct host_cmd_ds_command *resp);
793void mwifiex_reset_connect_state(struct mwifiex_private *priv); 784void mwifiex_reset_connect_state(struct mwifiex_private *priv);
@@ -800,10 +791,10 @@ int mwifiex_adhoc_join(struct mwifiex_private *priv,
800 struct mwifiex_bssdescriptor *bss_desc); 791 struct mwifiex_bssdescriptor *bss_desc);
801int mwifiex_cmd_802_11_ad_hoc_start(struct mwifiex_private *priv, 792int mwifiex_cmd_802_11_ad_hoc_start(struct mwifiex_private *priv,
802 struct host_cmd_ds_command *cmd, 793 struct host_cmd_ds_command *cmd,
803 void *data_buf); 794 struct mwifiex_802_11_ssid *req_ssid);
804int mwifiex_cmd_802_11_ad_hoc_join(struct mwifiex_private *priv, 795int mwifiex_cmd_802_11_ad_hoc_join(struct mwifiex_private *priv,
805 struct host_cmd_ds_command *cmd, 796 struct host_cmd_ds_command *cmd,
806 void *data_buf); 797 struct mwifiex_bssdescriptor *bss_desc);
807int mwifiex_ret_802_11_ad_hoc(struct mwifiex_private *priv, 798int mwifiex_ret_802_11_ad_hoc(struct mwifiex_private *priv,
808 struct host_cmd_ds_command *resp); 799 struct host_cmd_ds_command *resp);
809int mwifiex_cmd_802_11_bg_scan_query(struct host_cmd_ds_command *cmd); 800int mwifiex_cmd_802_11_bg_scan_query(struct host_cmd_ds_command *cmd);
@@ -938,6 +929,7 @@ int mwifiex_set_hs_params(struct mwifiex_private *priv,
938 struct mwifiex_ds_hs_cfg *hscfg); 929 struct mwifiex_ds_hs_cfg *hscfg);
939int mwifiex_cancel_hs(struct mwifiex_private *priv, int cmd_type); 930int mwifiex_cancel_hs(struct mwifiex_private *priv, int cmd_type);
940int mwifiex_enable_hs(struct mwifiex_adapter *adapter); 931int mwifiex_enable_hs(struct mwifiex_adapter *adapter);
932int mwifiex_disable_auto_ds(struct mwifiex_private *priv);
941int mwifiex_get_signal_info(struct mwifiex_private *priv, 933int mwifiex_get_signal_info(struct mwifiex_private *priv,
942 struct mwifiex_ds_get_signal *signal); 934 struct mwifiex_ds_get_signal *signal);
943int mwifiex_drv_get_data_rate(struct mwifiex_private *priv, 935int mwifiex_drv_get_data_rate(struct mwifiex_private *priv,
diff --git a/drivers/net/wireless/mwifiex/scan.c b/drivers/net/wireless/mwifiex/scan.c
index 5c22860fb40a..6f88c8ab5de5 100644
--- a/drivers/net/wireless/mwifiex/scan.c
+++ b/drivers/net/wireless/mwifiex/scan.c
@@ -2357,12 +2357,10 @@ int mwifiex_scan_networks(struct mwifiex_private *priv,
2357 * - Setting command ID, and proper size 2357 * - Setting command ID, and proper size
2358 * - Ensuring correct endian-ness 2358 * - Ensuring correct endian-ness
2359 */ 2359 */
2360int mwifiex_cmd_802_11_scan(struct host_cmd_ds_command *cmd, void *data_buf) 2360int mwifiex_cmd_802_11_scan(struct host_cmd_ds_command *cmd,
2361 struct mwifiex_scan_cmd_config *scan_cfg)
2361{ 2362{
2362 struct host_cmd_ds_802_11_scan *scan_cmd = &cmd->params.scan; 2363 struct host_cmd_ds_802_11_scan *scan_cmd = &cmd->params.scan;
2363 struct mwifiex_scan_cmd_config *scan_cfg;
2364
2365 scan_cfg = (struct mwifiex_scan_cmd_config *) data_buf;
2366 2364
2367 /* Set fixed field variables in scan command */ 2365 /* Set fixed field variables in scan command */
2368 scan_cmd->bss_mode = scan_cfg->bss_mode; 2366 scan_cmd->bss_mode = scan_cfg->bss_mode;
diff --git a/drivers/net/wireless/mwifiex/sdio.c b/drivers/net/wireless/mwifiex/sdio.c
index d425dbd91d19..82098ac483b8 100644
--- a/drivers/net/wireless/mwifiex/sdio.c
+++ b/drivers/net/wireless/mwifiex/sdio.c
@@ -31,10 +31,27 @@
31 31
32#define SDIO_VERSION "1.0" 32#define SDIO_VERSION "1.0"
33 33
34/* The mwifiex_sdio_remove() callback function is called when
35 * user removes this module from kernel space or ejects
36 * the card from the slot. The driver handles these 2 cases
37 * differently.
38 * If the user is removing the module, the few commands (FUNC_SHUTDOWN,
39 * HS_CANCEL etc.) are sent to the firmware.
40 * If the card is removed, there is no need to send these command.
41 *
42 * The variable 'user_rmmod' is used to distinguish these two
43 * scenarios. This flag is initialized as FALSE in case the card
44 * is removed, and will be set to TRUE for module removal when
45 * module_exit function is called.
46 */
47static u8 user_rmmod;
48
34static struct mwifiex_if_ops sdio_ops; 49static struct mwifiex_if_ops sdio_ops;
35 50
36static struct semaphore add_remove_card_sem; 51static struct semaphore add_remove_card_sem;
37 52
53static int mwifiex_sdio_resume(struct device *dev);
54
38/* 55/*
39 * SDIO probe. 56 * SDIO probe.
40 * 57 *
@@ -93,17 +110,39 @@ static void
93mwifiex_sdio_remove(struct sdio_func *func) 110mwifiex_sdio_remove(struct sdio_func *func)
94{ 111{
95 struct sdio_mmc_card *card; 112 struct sdio_mmc_card *card;
113 struct mwifiex_adapter *adapter;
114 int i;
96 115
97 pr_debug("info: SDIO func num=%d\n", func->num); 116 pr_debug("info: SDIO func num=%d\n", func->num);
98 117
99 if (func) { 118 card = sdio_get_drvdata(func);
100 card = sdio_get_drvdata(func); 119 if (!card)
101 if (card) { 120 return;
102 mwifiex_remove_card(card->adapter, 121
103 &add_remove_card_sem); 122 adapter = card->adapter;
104 kfree(card); 123 if (!adapter || !adapter->priv_num)
105 } 124 return;
125
126 if (user_rmmod) {
127 if (adapter->is_suspended)
128 mwifiex_sdio_resume(adapter->dev);
129
130 for (i = 0; i < adapter->priv_num; i++)
131 if ((GET_BSS_ROLE(adapter->priv[i]) ==
132 MWIFIEX_BSS_ROLE_STA) &&
133 adapter->priv[i]->media_connected)
134 mwifiex_deauthenticate(adapter->priv[i], NULL);
135
136 mwifiex_disable_auto_ds(mwifiex_get_priv(adapter,
137 MWIFIEX_BSS_ROLE_ANY));
138
139 mwifiex_init_shutdown_fw(mwifiex_get_priv(adapter,
140 MWIFIEX_BSS_ROLE_ANY),
141 MWIFIEX_FUNC_SHUTDOWN);
106 } 142 }
143
144 mwifiex_remove_card(card->adapter, &add_remove_card_sem);
145 kfree(card);
107} 146}
108 147
109/* 148/*
@@ -1283,7 +1322,7 @@ static int mwifiex_host_to_card_mp_aggr(struct mwifiex_adapter *adapter,
1283 if (!(card->mp_wr_bitmap & 1322 if (!(card->mp_wr_bitmap &
1284 (1 << card->curr_wr_port)) 1323 (1 << card->curr_wr_port))
1285 || !MP_TX_AGGR_BUF_HAS_ROOM( 1324 || !MP_TX_AGGR_BUF_HAS_ROOM(
1286 card, next_pkt_len)) 1325 card, pkt_len + next_pkt_len))
1287 f_send_aggr_buf = 1; 1326 f_send_aggr_buf = 1;
1288 } else { 1327 } else {
1289 /* No room in Aggr buf, send it */ 1328 /* No room in Aggr buf, send it */
@@ -1531,6 +1570,7 @@ static int mwifiex_register_dev(struct mwifiex_adapter *adapter)
1531 sdio_set_drvdata(func, card); 1570 sdio_set_drvdata(func, card);
1532 1571
1533 adapter->dev = &func->dev; 1572 adapter->dev = &func->dev;
1573 strcpy(adapter->fw_name, SD8787_DEFAULT_FW_NAME);
1534 1574
1535 return 0; 1575 return 0;
1536 1576
@@ -1552,7 +1592,6 @@ disable_func:
1552 * the first interrupt got from bootloader 1592 * the first interrupt got from bootloader
1553 * - Disable host interrupt mask register 1593 * - Disable host interrupt mask register
1554 * - Get SDIO port 1594 * - Get SDIO port
1555 * - Get revision ID
1556 * - Initialize SDIO variables in card 1595 * - Initialize SDIO variables in card
1557 * - Allocate MP registers 1596 * - Allocate MP registers
1558 * - Allocate MPA Tx and Rx buffers 1597 * - Allocate MPA Tx and Rx buffers
@@ -1576,10 +1615,6 @@ static int mwifiex_init_sdio(struct mwifiex_adapter *adapter)
1576 /* Get SDIO ioport */ 1615 /* Get SDIO ioport */
1577 mwifiex_init_sdio_ioport(adapter); 1616 mwifiex_init_sdio_ioport(adapter);
1578 1617
1579 /* Get revision ID */
1580#define REV_ID_REG 0x5c
1581 mwifiex_read_reg(adapter, REV_ID_REG, &adapter->revision_id);
1582
1583 /* Initialize SDIO variables in card */ 1618 /* Initialize SDIO variables in card */
1584 card->mp_rd_bitmap = 0; 1619 card->mp_rd_bitmap = 0;
1585 card->mp_wr_bitmap = 0; 1620 card->mp_wr_bitmap = 0;
@@ -1700,6 +1735,9 @@ mwifiex_sdio_init_module(void)
1700{ 1735{
1701 sema_init(&add_remove_card_sem, 1); 1736 sema_init(&add_remove_card_sem, 1);
1702 1737
1738 /* Clear the flag in case user removes the card. */
1739 user_rmmod = 0;
1740
1703 return sdio_register_driver(&mwifiex_sdio); 1741 return sdio_register_driver(&mwifiex_sdio);
1704} 1742}
1705 1743
@@ -1715,32 +1753,12 @@ mwifiex_sdio_init_module(void)
1715static void 1753static void
1716mwifiex_sdio_cleanup_module(void) 1754mwifiex_sdio_cleanup_module(void)
1717{ 1755{
1718 struct mwifiex_adapter *adapter = g_adapter; 1756 if (!down_interruptible(&add_remove_card_sem))
1719 int i; 1757 up(&add_remove_card_sem);
1720
1721 if (down_interruptible(&add_remove_card_sem))
1722 goto exit_sem_err;
1723
1724 if (!adapter || !adapter->priv_num)
1725 goto exit;
1726
1727 if (adapter->is_suspended)
1728 mwifiex_sdio_resume(adapter->dev);
1729
1730 for (i = 0; i < adapter->priv_num; i++)
1731 if ((GET_BSS_ROLE(adapter->priv[i]) == MWIFIEX_BSS_ROLE_STA) &&
1732 adapter->priv[i]->media_connected)
1733 mwifiex_deauthenticate(adapter->priv[i], NULL);
1734
1735 if (!adapter->surprise_removed)
1736 mwifiex_init_shutdown_fw(mwifiex_get_priv(adapter,
1737 MWIFIEX_BSS_ROLE_ANY),
1738 MWIFIEX_FUNC_SHUTDOWN);
1739 1758
1740exit: 1759 /* Set the flag as user is removing this module. */
1741 up(&add_remove_card_sem); 1760 user_rmmod = 1;
1742 1761
1743exit_sem_err:
1744 sdio_unregister_driver(&mwifiex_sdio); 1762 sdio_unregister_driver(&mwifiex_sdio);
1745} 1763}
1746 1764
@@ -1751,4 +1769,4 @@ MODULE_AUTHOR("Marvell International Ltd.");
1751MODULE_DESCRIPTION("Marvell WiFi-Ex SDIO Driver version " SDIO_VERSION); 1769MODULE_DESCRIPTION("Marvell WiFi-Ex SDIO Driver version " SDIO_VERSION);
1752MODULE_VERSION(SDIO_VERSION); 1770MODULE_VERSION(SDIO_VERSION);
1753MODULE_LICENSE("GPL v2"); 1771MODULE_LICENSE("GPL v2");
1754MODULE_FIRMWARE("sd8787.bin"); 1772MODULE_FIRMWARE("mrvl/sd8787_uapsta.bin");
diff --git a/drivers/net/wireless/mwifiex/sdio.h b/drivers/net/wireless/mwifiex/sdio.h
index 4e97e90aa399..524f78f4ee69 100644
--- a/drivers/net/wireless/mwifiex/sdio.h
+++ b/drivers/net/wireless/mwifiex/sdio.h
@@ -28,6 +28,8 @@
28 28
29#include "main.h" 29#include "main.h"
30 30
31#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
32
31#define BLOCK_MODE 1 33#define BLOCK_MODE 1
32#define BYTE_MODE 0 34#define BYTE_MODE 0
33 35
@@ -52,10 +54,10 @@
52 54
53#define SDIO_MP_AGGR_DEF_PKT_LIMIT 8 55#define SDIO_MP_AGGR_DEF_PKT_LIMIT 8
54 56
55#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (4096) /* 4K */ 57#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
56 58
57/* Multi port RX aggregation buffer size */ 59/* Multi port RX aggregation buffer size */
58#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (4096) /* 4K */ 60#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
59 61
60/* Misc. Config Register : Auto Re-enable interrupts */ 62/* Misc. Config Register : Auto Re-enable interrupts */
61#define AUTO_RE_ENABLE_INT BIT(4) 63#define AUTO_RE_ENABLE_INT BIT(4)
diff --git a/drivers/net/wireless/mwifiex/sta_cmd.c b/drivers/net/wireless/mwifiex/sta_cmd.c
index 8af3a78d2723..c54ee287b878 100644
--- a/drivers/net/wireless/mwifiex/sta_cmd.c
+++ b/drivers/net/wireless/mwifiex/sta_cmd.c
@@ -67,10 +67,9 @@ mwifiex_cmd_802_11_rssi_info(struct mwifiex_private *priv,
67 */ 67 */
68static int mwifiex_cmd_mac_control(struct mwifiex_private *priv, 68static int mwifiex_cmd_mac_control(struct mwifiex_private *priv,
69 struct host_cmd_ds_command *cmd, 69 struct host_cmd_ds_command *cmd,
70 u16 cmd_action, void *data_buf) 70 u16 cmd_action, u16 *action)
71{ 71{
72 struct host_cmd_ds_mac_control *mac_ctrl = &cmd->params.mac_ctrl; 72 struct host_cmd_ds_mac_control *mac_ctrl = &cmd->params.mac_ctrl;
73 u16 action = *((u16 *) data_buf);
74 73
75 if (cmd_action != HostCmd_ACT_GEN_SET) { 74 if (cmd_action != HostCmd_ACT_GEN_SET) {
76 dev_err(priv->adapter->dev, 75 dev_err(priv->adapter->dev,
@@ -81,7 +80,7 @@ static int mwifiex_cmd_mac_control(struct mwifiex_private *priv,
81 cmd->command = cpu_to_le16(HostCmd_CMD_MAC_CONTROL); 80 cmd->command = cpu_to_le16(HostCmd_CMD_MAC_CONTROL);
82 cmd->size = 81 cmd->size =
83 cpu_to_le16(sizeof(struct host_cmd_ds_mac_control) + S_DS_GEN); 82 cpu_to_le16(sizeof(struct host_cmd_ds_mac_control) + S_DS_GEN);
84 mac_ctrl->action = cpu_to_le16(action); 83 mac_ctrl->action = cpu_to_le16(*action);
85 84
86 return 0; 85 return 0;
87} 86}
@@ -104,10 +103,9 @@ static int mwifiex_cmd_mac_control(struct mwifiex_private *priv,
104static int mwifiex_cmd_802_11_snmp_mib(struct mwifiex_private *priv, 103static int mwifiex_cmd_802_11_snmp_mib(struct mwifiex_private *priv,
105 struct host_cmd_ds_command *cmd, 104 struct host_cmd_ds_command *cmd,
106 u16 cmd_action, u32 cmd_oid, 105 u16 cmd_action, u32 cmd_oid,
107 void *data_buf) 106 u32 *ul_temp)
108{ 107{
109 struct host_cmd_ds_802_11_snmp_mib *snmp_mib = &cmd->params.smib; 108 struct host_cmd_ds_802_11_snmp_mib *snmp_mib = &cmd->params.smib;
110 u32 ul_temp;
111 109
112 dev_dbg(priv->adapter->dev, "cmd: SNMP_CMD: cmd_oid = 0x%x\n", cmd_oid); 110 dev_dbg(priv->adapter->dev, "cmd: SNMP_CMD: cmd_oid = 0x%x\n", cmd_oid);
113 cmd->command = cpu_to_le16(HostCmd_CMD_802_11_SNMP_MIB); 111 cmd->command = cpu_to_le16(HostCmd_CMD_802_11_SNMP_MIB);
@@ -127,9 +125,8 @@ static int mwifiex_cmd_802_11_snmp_mib(struct mwifiex_private *priv,
127 if (cmd_action == HostCmd_ACT_GEN_SET) { 125 if (cmd_action == HostCmd_ACT_GEN_SET) {
128 snmp_mib->query_type = cpu_to_le16(HostCmd_ACT_GEN_SET); 126 snmp_mib->query_type = cpu_to_le16(HostCmd_ACT_GEN_SET);
129 snmp_mib->buf_size = cpu_to_le16(sizeof(u16)); 127 snmp_mib->buf_size = cpu_to_le16(sizeof(u16));
130 ul_temp = *((u32 *) data_buf);
131 *((__le16 *) (snmp_mib->value)) = 128 *((__le16 *) (snmp_mib->value)) =
132 cpu_to_le16((u16) ul_temp); 129 cpu_to_le16((u16) *ul_temp);
133 cmd->size = cpu_to_le16(le16_to_cpu(cmd->size) 130 cmd->size = cpu_to_le16(le16_to_cpu(cmd->size)
134 + sizeof(u16)); 131 + sizeof(u16));
135 } 132 }
@@ -139,9 +136,8 @@ static int mwifiex_cmd_802_11_snmp_mib(struct mwifiex_private *priv,
139 if (cmd_action == HostCmd_ACT_GEN_SET) { 136 if (cmd_action == HostCmd_ACT_GEN_SET) {
140 snmp_mib->query_type = cpu_to_le16(HostCmd_ACT_GEN_SET); 137 snmp_mib->query_type = cpu_to_le16(HostCmd_ACT_GEN_SET);
141 snmp_mib->buf_size = cpu_to_le16(sizeof(u16)); 138 snmp_mib->buf_size = cpu_to_le16(sizeof(u16));
142 ul_temp = *((u32 *) data_buf);
143 *(__le16 *) (snmp_mib->value) = 139 *(__le16 *) (snmp_mib->value) =
144 cpu_to_le16((u16) ul_temp); 140 cpu_to_le16((u16) *ul_temp);
145 cmd->size = cpu_to_le16(le16_to_cpu(cmd->size) 141 cmd->size = cpu_to_le16(le16_to_cpu(cmd->size)
146 + sizeof(u16)); 142 + sizeof(u16));
147 } 143 }
@@ -152,9 +148,8 @@ static int mwifiex_cmd_802_11_snmp_mib(struct mwifiex_private *priv,
152 if (cmd_action == HostCmd_ACT_GEN_SET) { 148 if (cmd_action == HostCmd_ACT_GEN_SET) {
153 snmp_mib->query_type = cpu_to_le16(HostCmd_ACT_GEN_SET); 149 snmp_mib->query_type = cpu_to_le16(HostCmd_ACT_GEN_SET);
154 snmp_mib->buf_size = cpu_to_le16(sizeof(u16)); 150 snmp_mib->buf_size = cpu_to_le16(sizeof(u16));
155 ul_temp = (*(u32 *) data_buf);
156 *((__le16 *) (snmp_mib->value)) = 151 *((__le16 *) (snmp_mib->value)) =
157 cpu_to_le16((u16) ul_temp); 152 cpu_to_le16((u16) *ul_temp);
158 cmd->size = cpu_to_le16(le16_to_cpu(cmd->size) 153 cmd->size = cpu_to_le16(le16_to_cpu(cmd->size)
159 + sizeof(u16)); 154 + sizeof(u16));
160 } 155 }
@@ -164,9 +159,8 @@ static int mwifiex_cmd_802_11_snmp_mib(struct mwifiex_private *priv,
164 if (cmd_action == HostCmd_ACT_GEN_SET) { 159 if (cmd_action == HostCmd_ACT_GEN_SET) {
165 snmp_mib->query_type = cpu_to_le16(HostCmd_ACT_GEN_SET); 160 snmp_mib->query_type = cpu_to_le16(HostCmd_ACT_GEN_SET);
166 snmp_mib->buf_size = cpu_to_le16(sizeof(u16)); 161 snmp_mib->buf_size = cpu_to_le16(sizeof(u16));
167 ul_temp = *(u32 *) data_buf;
168 *((__le16 *) (snmp_mib->value)) = 162 *((__le16 *) (snmp_mib->value)) =
169 cpu_to_le16((u16) ul_temp); 163 cpu_to_le16((u16) *ul_temp);
170 cmd->size = cpu_to_le16(le16_to_cpu(cmd->size) 164 cmd->size = cpu_to_le16(le16_to_cpu(cmd->size)
171 + sizeof(u16)); 165 + sizeof(u16));
172 } 166 }
@@ -209,13 +203,11 @@ mwifiex_cmd_802_11_get_log(struct host_cmd_ds_command *cmd)
209 */ 203 */
210static int mwifiex_cmd_tx_rate_cfg(struct mwifiex_private *priv, 204static int mwifiex_cmd_tx_rate_cfg(struct mwifiex_private *priv,
211 struct host_cmd_ds_command *cmd, 205 struct host_cmd_ds_command *cmd,
212 u16 cmd_action, void *data_buf) 206 u16 cmd_action, u16 *pbitmap_rates)
213{ 207{
214 struct host_cmd_ds_tx_rate_cfg *rate_cfg = &cmd->params.tx_rate_cfg; 208 struct host_cmd_ds_tx_rate_cfg *rate_cfg = &cmd->params.tx_rate_cfg;
215 struct mwifiex_rate_scope *rate_scope; 209 struct mwifiex_rate_scope *rate_scope;
216 struct mwifiex_rate_drop_pattern *rate_drop; 210 struct mwifiex_rate_drop_pattern *rate_drop;
217 u16 *pbitmap_rates = (u16 *) data_buf;
218
219 u32 i; 211 u32 i;
220 212
221 cmd->command = cpu_to_le16(HostCmd_CMD_TX_RATE_CFG); 213 cmd->command = cpu_to_le16(HostCmd_CMD_TX_RATE_CFG);
@@ -272,10 +264,10 @@ static int mwifiex_cmd_tx_rate_cfg(struct mwifiex_private *priv,
272 * - Ensuring correct endian-ness 264 * - Ensuring correct endian-ness
273 */ 265 */
274static int mwifiex_cmd_tx_power_cfg(struct host_cmd_ds_command *cmd, 266static int mwifiex_cmd_tx_power_cfg(struct host_cmd_ds_command *cmd,
275 u16 cmd_action, void *data_buf) 267 u16 cmd_action,
268 struct host_cmd_ds_txpwr_cfg *txp)
276{ 269{
277 struct mwifiex_types_power_group *pg_tlv; 270 struct mwifiex_types_power_group *pg_tlv;
278 struct host_cmd_ds_txpwr_cfg *txp;
279 struct host_cmd_ds_txpwr_cfg *cmd_txp_cfg = &cmd->params.txp_cfg; 271 struct host_cmd_ds_txpwr_cfg *cmd_txp_cfg = &cmd->params.txp_cfg;
280 272
281 cmd->command = cpu_to_le16(HostCmd_CMD_TXPWR_CFG); 273 cmd->command = cpu_to_le16(HostCmd_CMD_TXPWR_CFG);
@@ -283,12 +275,11 @@ static int mwifiex_cmd_tx_power_cfg(struct host_cmd_ds_command *cmd,
283 cpu_to_le16(S_DS_GEN + sizeof(struct host_cmd_ds_txpwr_cfg)); 275 cpu_to_le16(S_DS_GEN + sizeof(struct host_cmd_ds_txpwr_cfg));
284 switch (cmd_action) { 276 switch (cmd_action) {
285 case HostCmd_ACT_GEN_SET: 277 case HostCmd_ACT_GEN_SET:
286 txp = (struct host_cmd_ds_txpwr_cfg *) data_buf;
287 if (txp->mode) { 278 if (txp->mode) {
288 pg_tlv = (struct mwifiex_types_power_group 279 pg_tlv = (struct mwifiex_types_power_group
289 *) ((unsigned long) data_buf + 280 *) ((unsigned long) txp +
290 sizeof(struct host_cmd_ds_txpwr_cfg)); 281 sizeof(struct host_cmd_ds_txpwr_cfg));
291 memmove(cmd_txp_cfg, data_buf, 282 memmove(cmd_txp_cfg, txp,
292 sizeof(struct host_cmd_ds_txpwr_cfg) + 283 sizeof(struct host_cmd_ds_txpwr_cfg) +
293 sizeof(struct mwifiex_types_power_group) + 284 sizeof(struct mwifiex_types_power_group) +
294 pg_tlv->length); 285 pg_tlv->length);
@@ -300,8 +291,7 @@ static int mwifiex_cmd_tx_power_cfg(struct host_cmd_ds_command *cmd,
300 sizeof(struct mwifiex_types_power_group) + 291 sizeof(struct mwifiex_types_power_group) +
301 pg_tlv->length); 292 pg_tlv->length);
302 } else { 293 } else {
303 memmove(cmd_txp_cfg, data_buf, 294 memmove(cmd_txp_cfg, txp, sizeof(*txp));
304 sizeof(struct host_cmd_ds_txpwr_cfg));
305 } 295 }
306 cmd_txp_cfg->action = cpu_to_le16(cmd_action); 296 cmd_txp_cfg->action = cpu_to_le16(cmd_action);
307 break; 297 break;
@@ -322,22 +312,23 @@ static int mwifiex_cmd_tx_power_cfg(struct host_cmd_ds_command *cmd,
322 * (as required) 312 * (as required)
323 * - Ensuring correct endian-ness 313 * - Ensuring correct endian-ness
324 */ 314 */
325static int mwifiex_cmd_802_11_hs_cfg(struct mwifiex_private *priv, 315static int
326 struct host_cmd_ds_command *cmd, 316mwifiex_cmd_802_11_hs_cfg(struct mwifiex_private *priv,
327 u16 cmd_action, 317 struct host_cmd_ds_command *cmd,
328 struct mwifiex_hs_config_param *data_buf) 318 u16 cmd_action,
319 struct mwifiex_hs_config_param *hscfg_param)
329{ 320{
330 struct mwifiex_adapter *adapter = priv->adapter; 321 struct mwifiex_adapter *adapter = priv->adapter;
331 struct host_cmd_ds_802_11_hs_cfg_enh *hs_cfg = &cmd->params.opt_hs_cfg; 322 struct host_cmd_ds_802_11_hs_cfg_enh *hs_cfg = &cmd->params.opt_hs_cfg;
332 u16 hs_activate = false; 323 u16 hs_activate = false;
333 324
334 if (data_buf == NULL) 325 if (!hscfg_param)
335 /* New Activate command */ 326 /* New Activate command */
336 hs_activate = true; 327 hs_activate = true;
337 cmd->command = cpu_to_le16(HostCmd_CMD_802_11_HS_CFG_ENH); 328 cmd->command = cpu_to_le16(HostCmd_CMD_802_11_HS_CFG_ENH);
338 329
339 if (!hs_activate && 330 if (!hs_activate &&
340 (data_buf->conditions 331 (hscfg_param->conditions
341 != cpu_to_le32(HOST_SLEEP_CFG_CANCEL)) 332 != cpu_to_le32(HOST_SLEEP_CFG_CANCEL))
342 && ((adapter->arp_filter_size > 0) 333 && ((adapter->arp_filter_size > 0)
343 && (adapter->arp_filter_size <= ARP_FILTER_MAX_BUF_SIZE))) { 334 && (adapter->arp_filter_size <= ARP_FILTER_MAX_BUF_SIZE))) {
@@ -359,9 +350,9 @@ static int mwifiex_cmd_802_11_hs_cfg(struct mwifiex_private *priv,
359 hs_cfg->params.hs_activate.resp_ctrl = RESP_NEEDED; 350 hs_cfg->params.hs_activate.resp_ctrl = RESP_NEEDED;
360 } else { 351 } else {
361 hs_cfg->action = cpu_to_le16(HS_CONFIGURE); 352 hs_cfg->action = cpu_to_le16(HS_CONFIGURE);
362 hs_cfg->params.hs_config.conditions = data_buf->conditions; 353 hs_cfg->params.hs_config.conditions = hscfg_param->conditions;
363 hs_cfg->params.hs_config.gpio = data_buf->gpio; 354 hs_cfg->params.hs_config.gpio = hscfg_param->gpio;
364 hs_cfg->params.hs_config.gap = data_buf->gap; 355 hs_cfg->params.hs_config.gap = hscfg_param->gap;
365 dev_dbg(adapter->dev, 356 dev_dbg(adapter->dev,
366 "cmd: HS_CFG_CMD: condition:0x%x gpio:0x%x gap:0x%x\n", 357 "cmd: HS_CFG_CMD: condition:0x%x gpio:0x%x gap:0x%x\n",
367 hs_cfg->params.hs_config.conditions, 358 hs_cfg->params.hs_config.conditions,
@@ -405,11 +396,11 @@ static int mwifiex_cmd_802_11_mac_address(struct mwifiex_private *priv,
405 * - Setting MAC multicast address 396 * - Setting MAC multicast address
406 * - Ensuring correct endian-ness 397 * - Ensuring correct endian-ness
407 */ 398 */
408static int mwifiex_cmd_mac_multicast_adr(struct host_cmd_ds_command *cmd, 399static int
409 u16 cmd_action, void *data_buf) 400mwifiex_cmd_mac_multicast_adr(struct host_cmd_ds_command *cmd,
401 u16 cmd_action,
402 struct mwifiex_multicast_list *mcast_list)
410{ 403{
411 struct mwifiex_multicast_list *mcast_list =
412 (struct mwifiex_multicast_list *) data_buf;
413 struct host_cmd_ds_mac_multicast_adr *mcast_addr = &cmd->params.mc_addr; 404 struct host_cmd_ds_mac_multicast_adr *mcast_addr = &cmd->params.mc_addr;
414 405
415 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_mac_multicast_adr) + 406 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_mac_multicast_adr) +
@@ -435,7 +426,7 @@ static int mwifiex_cmd_mac_multicast_adr(struct host_cmd_ds_command *cmd,
435 */ 426 */
436static int mwifiex_cmd_802_11_deauthenticate(struct mwifiex_private *priv, 427static int mwifiex_cmd_802_11_deauthenticate(struct mwifiex_private *priv,
437 struct host_cmd_ds_command *cmd, 428 struct host_cmd_ds_command *cmd,
438 void *data_buf) 429 u8 *mac)
439{ 430{
440 struct host_cmd_ds_802_11_deauthenticate *deauth = &cmd->params.deauth; 431 struct host_cmd_ds_802_11_deauthenticate *deauth = &cmd->params.deauth;
441 432
@@ -444,7 +435,7 @@ static int mwifiex_cmd_802_11_deauthenticate(struct mwifiex_private *priv,
444 + S_DS_GEN); 435 + S_DS_GEN);
445 436
446 /* Set AP MAC address */ 437 /* Set AP MAC address */
447 memcpy(deauth->mac_addr, (u8 *) data_buf, ETH_ALEN); 438 memcpy(deauth->mac_addr, mac, ETH_ALEN);
448 439
449 dev_dbg(priv->adapter->dev, "cmd: Deauth: %pM\n", deauth->mac_addr); 440 dev_dbg(priv->adapter->dev, "cmd: Deauth: %pM\n", deauth->mac_addr);
450 441
@@ -543,15 +534,14 @@ mwifiex_set_keyparamset_wep(struct mwifiex_private *priv,
543 * encryption (TKIP, AES) (as required) 534 * encryption (TKIP, AES) (as required)
544 * - Ensuring correct endian-ness 535 * - Ensuring correct endian-ness
545 */ 536 */
546static int mwifiex_cmd_802_11_key_material(struct mwifiex_private *priv, 537static int
547 struct host_cmd_ds_command *cmd, 538mwifiex_cmd_802_11_key_material(struct mwifiex_private *priv,
548 u16 cmd_action, 539 struct host_cmd_ds_command *cmd,
549 u32 cmd_oid, void *data_buf) 540 u16 cmd_action, u32 cmd_oid,
541 struct mwifiex_ds_encrypt_key *enc_key)
550{ 542{
551 struct host_cmd_ds_802_11_key_material *key_material = 543 struct host_cmd_ds_802_11_key_material *key_material =
552 &cmd->params.key_material; 544 &cmd->params.key_material;
553 struct mwifiex_ds_encrypt_key *enc_key =
554 (struct mwifiex_ds_encrypt_key *) data_buf;
555 u16 key_param_len = 0; 545 u16 key_param_len = 0;
556 int ret = 0; 546 int ret = 0;
557 const u8 bc_mac[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 547 const u8 bc_mac[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
@@ -741,7 +731,7 @@ static int mwifiex_cmd_802_11d_domain_info(struct mwifiex_private *priv,
741 */ 731 */
742static int mwifiex_cmd_802_11_rf_channel(struct mwifiex_private *priv, 732static int mwifiex_cmd_802_11_rf_channel(struct mwifiex_private *priv,
743 struct host_cmd_ds_command *cmd, 733 struct host_cmd_ds_command *cmd,
744 u16 cmd_action, void *data_buf) 734 u16 cmd_action, u16 *channel)
745{ 735{
746 struct host_cmd_ds_802_11_rf_channel *rf_chan = 736 struct host_cmd_ds_802_11_rf_channel *rf_chan =
747 &cmd->params.rf_channel; 737 &cmd->params.rf_channel;
@@ -759,7 +749,7 @@ static int mwifiex_cmd_802_11_rf_channel(struct mwifiex_private *priv,
759 749
760 rf_type = le16_to_cpu(rf_chan->rf_type); 750 rf_type = le16_to_cpu(rf_chan->rf_type);
761 SET_SECONDARYCHAN(rf_type, priv->adapter->chan_offset); 751 SET_SECONDARYCHAN(rf_type, priv->adapter->chan_offset);
762 rf_chan->current_channel = cpu_to_le16(*((u16 *) data_buf)); 752 rf_chan->current_channel = cpu_to_le16(*channel);
763 } 753 }
764 rf_chan->action = cpu_to_le16(cmd_action); 754 rf_chan->action = cpu_to_le16(cmd_action);
765 return 0; 755 return 0;
@@ -774,11 +764,10 @@ static int mwifiex_cmd_802_11_rf_channel(struct mwifiex_private *priv,
774 * - Ensuring correct endian-ness 764 * - Ensuring correct endian-ness
775 */ 765 */
776static int mwifiex_cmd_ibss_coalescing_status(struct host_cmd_ds_command *cmd, 766static int mwifiex_cmd_ibss_coalescing_status(struct host_cmd_ds_command *cmd,
777 u16 cmd_action, void *data_buf) 767 u16 cmd_action, u16 *enable)
778{ 768{
779 struct host_cmd_ds_802_11_ibss_status *ibss_coal = 769 struct host_cmd_ds_802_11_ibss_status *ibss_coal =
780 &(cmd->params.ibss_coalescing); 770 &(cmd->params.ibss_coalescing);
781 u16 enable = 0;
782 771
783 cmd->command = cpu_to_le16(HostCmd_CMD_802_11_IBSS_COALESCING_STATUS); 772 cmd->command = cpu_to_le16(HostCmd_CMD_802_11_IBSS_COALESCING_STATUS);
784 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_802_11_ibss_status) + 773 cmd->size = cpu_to_le16(sizeof(struct host_cmd_ds_802_11_ibss_status) +
@@ -788,9 +777,10 @@ static int mwifiex_cmd_ibss_coalescing_status(struct host_cmd_ds_command *cmd,
788 777
789 switch (cmd_action) { 778 switch (cmd_action) {
790 case HostCmd_ACT_GEN_SET: 779 case HostCmd_ACT_GEN_SET:
791 if (data_buf != NULL) 780 if (enable)
792 enable = *(u16 *) data_buf; 781 ibss_coal->enable = cpu_to_le16(*enable);
793 ibss_coal->enable = cpu_to_le16(enable); 782 else
783 ibss_coal->enable = 0;
794 break; 784 break;
795 785
796 /* In other case.. Nothing to do */ 786 /* In other case.. Nothing to do */
@@ -822,9 +812,8 @@ static int mwifiex_cmd_ibss_coalescing_status(struct host_cmd_ds_command *cmd,
822static int mwifiex_cmd_reg_access(struct host_cmd_ds_command *cmd, 812static int mwifiex_cmd_reg_access(struct host_cmd_ds_command *cmd,
823 u16 cmd_action, void *data_buf) 813 u16 cmd_action, void *data_buf)
824{ 814{
825 struct mwifiex_ds_reg_rw *reg_rw; 815 struct mwifiex_ds_reg_rw *reg_rw = data_buf;
826 816
827 reg_rw = (struct mwifiex_ds_reg_rw *) data_buf;
828 switch (le16_to_cpu(cmd->command)) { 817 switch (le16_to_cpu(cmd->command)) {
829 case HostCmd_CMD_MAC_REG_ACCESS: 818 case HostCmd_CMD_MAC_REG_ACCESS:
830 { 819 {
@@ -893,8 +882,7 @@ static int mwifiex_cmd_reg_access(struct host_cmd_ds_command *cmd,
893 } 882 }
894 case HostCmd_CMD_802_11_EEPROM_ACCESS: 883 case HostCmd_CMD_802_11_EEPROM_ACCESS:
895 { 884 {
896 struct mwifiex_ds_read_eeprom *rd_eeprom = 885 struct mwifiex_ds_read_eeprom *rd_eeprom = data_buf;
897 (struct mwifiex_ds_read_eeprom *) data_buf;
898 struct host_cmd_ds_802_11_eeprom_access *cmd_eeprom = 886 struct host_cmd_ds_802_11_eeprom_access *cmd_eeprom =
899 (struct host_cmd_ds_802_11_eeprom_access *) 887 (struct host_cmd_ds_802_11_eeprom_access *)
900 &cmd->params.eeprom; 888 &cmd->params.eeprom;
@@ -923,8 +911,7 @@ int mwifiex_sta_prepare_cmd(struct mwifiex_private *priv, uint16_t cmd_no,
923 u16 cmd_action, u32 cmd_oid, 911 u16 cmd_action, u32 cmd_oid,
924 void *data_buf, void *cmd_buf) 912 void *data_buf, void *cmd_buf)
925{ 913{
926 struct host_cmd_ds_command *cmd_ptr = 914 struct host_cmd_ds_command *cmd_ptr = cmd_buf;
927 (struct host_cmd_ds_command *) cmd_buf;
928 int ret = 0; 915 int ret = 0;
929 916
930 /* Prepare command */ 917 /* Prepare command */
@@ -1126,6 +1113,7 @@ int mwifiex_sta_init_cmd(struct mwifiex_private *priv, u8 first_sta)
1126 struct mwifiex_ds_11n_amsdu_aggr_ctrl amsdu_aggr_ctrl; 1113 struct mwifiex_ds_11n_amsdu_aggr_ctrl amsdu_aggr_ctrl;
1127 struct mwifiex_ds_auto_ds auto_ds; 1114 struct mwifiex_ds_auto_ds auto_ds;
1128 enum state_11d_t state_11d; 1115 enum state_11d_t state_11d;
1116 struct mwifiex_ds_11n_tx_cfg tx_cfg;
1129 1117
1130 if (first_sta) { 1118 if (first_sta) {
1131 1119
@@ -1181,7 +1169,7 @@ int mwifiex_sta_init_cmd(struct mwifiex_private *priv, u8 first_sta)
1181 /* Send request to firmware */ 1169 /* Send request to firmware */
1182 ret = mwifiex_send_cmd_async(priv, HostCmd_CMD_AMSDU_AGGR_CTRL, 1170 ret = mwifiex_send_cmd_async(priv, HostCmd_CMD_AMSDU_AGGR_CTRL,
1183 HostCmd_ACT_GEN_SET, 0, 1171 HostCmd_ACT_GEN_SET, 0,
1184 (void *) &amsdu_aggr_ctrl); 1172 &amsdu_aggr_ctrl);
1185 if (ret) 1173 if (ret)
1186 return -1; 1174 return -1;
1187 /* MAC Control must be the last command in init_fw */ 1175 /* MAC Control must be the last command in init_fw */
@@ -1211,8 +1199,15 @@ int mwifiex_sta_init_cmd(struct mwifiex_private *priv, u8 first_sta)
1211 if (ret) 1199 if (ret)
1212 dev_err(priv->adapter->dev, "11D: failed to enable 11D\n"); 1200 dev_err(priv->adapter->dev, "11D: failed to enable 11D\n");
1213 1201
1202 /* Send cmd to FW to configure 11n specific configuration
1203 * (Short GI, Channel BW, Green field support etc.) for transmit
1204 */
1205 tx_cfg.tx_htcap = MWIFIEX_FW_DEF_HTTXCFG;
1206 ret = mwifiex_send_cmd_async(priv, HostCmd_CMD_11N_CFG,
1207 HostCmd_ACT_GEN_SET, 0, &tx_cfg);
1208
1214 /* set last_init_cmd */ 1209 /* set last_init_cmd */
1215 priv->adapter->last_init_cmd = HostCmd_CMD_802_11_SNMP_MIB; 1210 priv->adapter->last_init_cmd = HostCmd_CMD_11N_CFG;
1216 ret = -EINPROGRESS; 1211 ret = -EINPROGRESS;
1217 1212
1218 return ret; 1213 return ret;
diff --git a/drivers/net/wireless/mwifiex/sta_cmdresp.c b/drivers/net/wireless/mwifiex/sta_cmdresp.c
index d08f76429a0a..6804239d87bd 100644
--- a/drivers/net/wireless/mwifiex/sta_cmdresp.c
+++ b/drivers/net/wireless/mwifiex/sta_cmdresp.c
@@ -120,11 +120,10 @@ mwifiex_process_cmdresp_error(struct mwifiex_private *priv,
120 */ 120 */
121static int mwifiex_ret_802_11_rssi_info(struct mwifiex_private *priv, 121static int mwifiex_ret_802_11_rssi_info(struct mwifiex_private *priv,
122 struct host_cmd_ds_command *resp, 122 struct host_cmd_ds_command *resp,
123 void *data_buf) 123 struct mwifiex_ds_get_signal *signal)
124{ 124{
125 struct host_cmd_ds_802_11_rssi_info_rsp *rssi_info_rsp = 125 struct host_cmd_ds_802_11_rssi_info_rsp *rssi_info_rsp =
126 &resp->params.rssi_info_rsp; 126 &resp->params.rssi_info_rsp;
127 struct mwifiex_ds_get_signal *signal;
128 127
129 priv->data_rssi_last = le16_to_cpu(rssi_info_rsp->data_rssi_last); 128 priv->data_rssi_last = le16_to_cpu(rssi_info_rsp->data_rssi_last);
130 priv->data_nf_last = le16_to_cpu(rssi_info_rsp->data_nf_last); 129 priv->data_nf_last = le16_to_cpu(rssi_info_rsp->data_nf_last);
@@ -139,9 +138,8 @@ static int mwifiex_ret_802_11_rssi_info(struct mwifiex_private *priv,
139 priv->bcn_nf_avg = le16_to_cpu(rssi_info_rsp->bcn_nf_avg); 138 priv->bcn_nf_avg = le16_to_cpu(rssi_info_rsp->bcn_nf_avg);
140 139
141 /* Need to indicate IOCTL complete */ 140 /* Need to indicate IOCTL complete */
142 if (data_buf) { 141 if (signal) {
143 signal = (struct mwifiex_ds_get_signal *) data_buf; 142 memset(signal, 0, sizeof(*signal));
144 memset(signal, 0, sizeof(struct mwifiex_ds_get_signal));
145 143
146 signal->selector = ALL_RSSI_INFO_MASK; 144 signal->selector = ALL_RSSI_INFO_MASK;
147 145
@@ -185,7 +183,7 @@ static int mwifiex_ret_802_11_rssi_info(struct mwifiex_private *priv,
185 */ 183 */
186static int mwifiex_ret_802_11_snmp_mib(struct mwifiex_private *priv, 184static int mwifiex_ret_802_11_snmp_mib(struct mwifiex_private *priv,
187 struct host_cmd_ds_command *resp, 185 struct host_cmd_ds_command *resp,
188 void *data_buf) 186 u32 *data_buf)
189{ 187{
190 struct host_cmd_ds_802_11_snmp_mib *smib = &resp->params.smib; 188 struct host_cmd_ds_802_11_snmp_mib *smib = &resp->params.smib;
191 u16 oid = le16_to_cpu(smib->oid); 189 u16 oid = le16_to_cpu(smib->oid);
@@ -198,7 +196,7 @@ static int mwifiex_ret_802_11_snmp_mib(struct mwifiex_private *priv,
198 if (query_type == HostCmd_ACT_GEN_GET) { 196 if (query_type == HostCmd_ACT_GEN_GET) {
199 ul_temp = le16_to_cpu(*((__le16 *) (smib->value))); 197 ul_temp = le16_to_cpu(*((__le16 *) (smib->value)));
200 if (data_buf) 198 if (data_buf)
201 *(u32 *)data_buf = ul_temp; 199 *data_buf = ul_temp;
202 switch (oid) { 200 switch (oid) {
203 case FRAG_THRESH_I: 201 case FRAG_THRESH_I:
204 dev_dbg(priv->adapter->dev, 202 dev_dbg(priv->adapter->dev,
@@ -228,14 +226,12 @@ static int mwifiex_ret_802_11_snmp_mib(struct mwifiex_private *priv,
228 */ 226 */
229static int mwifiex_ret_get_log(struct mwifiex_private *priv, 227static int mwifiex_ret_get_log(struct mwifiex_private *priv,
230 struct host_cmd_ds_command *resp, 228 struct host_cmd_ds_command *resp,
231 void *data_buf) 229 struct mwifiex_ds_get_stats *stats)
232{ 230{
233 struct host_cmd_ds_802_11_get_log *get_log = 231 struct host_cmd_ds_802_11_get_log *get_log =
234 (struct host_cmd_ds_802_11_get_log *) &resp->params.get_log; 232 (struct host_cmd_ds_802_11_get_log *) &resp->params.get_log;
235 struct mwifiex_ds_get_stats *stats;
236 233
237 if (data_buf) { 234 if (stats) {
238 stats = (struct mwifiex_ds_get_stats *) data_buf;
239 stats->mcast_tx_frame = le32_to_cpu(get_log->mcast_tx_frame); 235 stats->mcast_tx_frame = le32_to_cpu(get_log->mcast_tx_frame);
240 stats->failed = le32_to_cpu(get_log->failed); 236 stats->failed = le32_to_cpu(get_log->failed);
241 stats->retry = le32_to_cpu(get_log->retry); 237 stats->retry = le32_to_cpu(get_log->retry);
@@ -278,9 +274,8 @@ static int mwifiex_ret_get_log(struct mwifiex_private *priv,
278 */ 274 */
279static int mwifiex_ret_tx_rate_cfg(struct mwifiex_private *priv, 275static int mwifiex_ret_tx_rate_cfg(struct mwifiex_private *priv,
280 struct host_cmd_ds_command *resp, 276 struct host_cmd_ds_command *resp,
281 void *data_buf) 277 struct mwifiex_rate_cfg *ds_rate)
282{ 278{
283 struct mwifiex_rate_cfg *ds_rate;
284 struct host_cmd_ds_tx_rate_cfg *rate_cfg = &resp->params.tx_rate_cfg; 279 struct host_cmd_ds_tx_rate_cfg *rate_cfg = &resp->params.tx_rate_cfg;
285 struct mwifiex_rate_scope *rate_scope; 280 struct mwifiex_rate_scope *rate_scope;
286 struct mwifiex_ie_types_header *head; 281 struct mwifiex_ie_types_header *head;
@@ -329,8 +324,7 @@ static int mwifiex_ret_tx_rate_cfg(struct mwifiex_private *priv,
329 HostCmd_CMD_802_11_TX_RATE_QUERY, 324 HostCmd_CMD_802_11_TX_RATE_QUERY,
330 HostCmd_ACT_GEN_GET, 0, NULL); 325 HostCmd_ACT_GEN_GET, 0, NULL);
331 326
332 if (data_buf) { 327 if (ds_rate) {
333 ds_rate = (struct mwifiex_rate_cfg *) data_buf;
334 if (le16_to_cpu(rate_cfg->action) == HostCmd_ACT_GEN_GET) { 328 if (le16_to_cpu(rate_cfg->action) == HostCmd_ACT_GEN_GET) {
335 if (priv->is_data_rate_auto) { 329 if (priv->is_data_rate_auto) {
336 ds_rate->is_rate_auto = 1; 330 ds_rate->is_rate_auto = 1;
@@ -413,8 +407,7 @@ static int mwifiex_get_power_level(struct mwifiex_private *priv, void *data_buf)
413 * and saving the current Tx power level in driver. 407 * and saving the current Tx power level in driver.
414 */ 408 */
415static int mwifiex_ret_tx_power_cfg(struct mwifiex_private *priv, 409static int mwifiex_ret_tx_power_cfg(struct mwifiex_private *priv,
416 struct host_cmd_ds_command *resp, 410 struct host_cmd_ds_command *resp)
417 void *data_buf)
418{ 411{
419 struct mwifiex_adapter *adapter = priv->adapter; 412 struct mwifiex_adapter *adapter = priv->adapter;
420 struct host_cmd_ds_txpwr_cfg *txp_cfg = &resp->params.txp_cfg; 413 struct host_cmd_ds_txpwr_cfg *txp_cfg = &resp->params.txp_cfg;
@@ -631,7 +624,7 @@ static int mwifiex_ret_802_11d_domain_info(struct mwifiex_private *priv,
631 */ 624 */
632static int mwifiex_ret_802_11_rf_channel(struct mwifiex_private *priv, 625static int mwifiex_ret_802_11_rf_channel(struct mwifiex_private *priv,
633 struct host_cmd_ds_command *resp, 626 struct host_cmd_ds_command *resp,
634 void *data_buf) 627 u16 *data_buf)
635{ 628{
636 struct host_cmd_ds_802_11_rf_channel *rf_channel = 629 struct host_cmd_ds_802_11_rf_channel *rf_channel =
637 &resp->params.rf_channel; 630 &resp->params.rf_channel;
@@ -644,8 +637,9 @@ static int mwifiex_ret_802_11_rf_channel(struct mwifiex_private *priv,
644 /* Update the channel again */ 637 /* Update the channel again */
645 priv->curr_bss_params.bss_descriptor.channel = new_channel; 638 priv->curr_bss_params.bss_descriptor.channel = new_channel;
646 } 639 }
640
647 if (data_buf) 641 if (data_buf)
648 *((u16 *)data_buf) = new_channel; 642 *data_buf = new_channel;
649 643
650 return 0; 644 return 0;
651} 645}
@@ -658,13 +652,11 @@ static int mwifiex_ret_802_11_rf_channel(struct mwifiex_private *priv,
658 */ 652 */
659static int mwifiex_ret_ver_ext(struct mwifiex_private *priv, 653static int mwifiex_ret_ver_ext(struct mwifiex_private *priv,
660 struct host_cmd_ds_command *resp, 654 struct host_cmd_ds_command *resp,
661 void *data_buf) 655 struct host_cmd_ds_version_ext *version_ext)
662{ 656{
663 struct host_cmd_ds_version_ext *ver_ext = &resp->params.verext; 657 struct host_cmd_ds_version_ext *ver_ext = &resp->params.verext;
664 struct host_cmd_ds_version_ext *version_ext;
665 658
666 if (data_buf) { 659 if (version_ext) {
667 version_ext = (struct host_cmd_ds_version_ext *)data_buf;
668 version_ext->version_str_sel = ver_ext->version_str_sel; 660 version_ext->version_str_sel = ver_ext->version_str_sel;
669 memcpy(version_ext->version_str, ver_ext->version_str, 661 memcpy(version_ext->version_str, ver_ext->version_str,
670 sizeof(char) * 128); 662 sizeof(char) * 128);
@@ -686,8 +678,8 @@ static int mwifiex_ret_reg_access(u16 type, struct host_cmd_ds_command *resp,
686 struct mwifiex_ds_read_eeprom *eeprom; 678 struct mwifiex_ds_read_eeprom *eeprom;
687 679
688 if (data_buf) { 680 if (data_buf) {
689 reg_rw = (struct mwifiex_ds_reg_rw *) data_buf; 681 reg_rw = data_buf;
690 eeprom = (struct mwifiex_ds_read_eeprom *) data_buf; 682 eeprom = data_buf;
691 switch (type) { 683 switch (type) {
692 case HostCmd_CMD_MAC_REG_ACCESS: 684 case HostCmd_CMD_MAC_REG_ACCESS:
693 { 685 {
@@ -825,13 +817,11 @@ static int mwifiex_ret_ibss_coalescing_status(struct mwifiex_private *priv,
825 * This is a generic function, which calls command specific 817 * This is a generic function, which calls command specific
826 * response handlers based on the command ID. 818 * response handlers based on the command ID.
827 */ 819 */
828int mwifiex_process_sta_cmdresp(struct mwifiex_private *priv, 820int mwifiex_process_sta_cmdresp(struct mwifiex_private *priv, u16 cmdresp_no,
829 u16 cmdresp_no, void *cmd_buf) 821 struct host_cmd_ds_command *resp)
830{ 822{
831 int ret = 0; 823 int ret = 0;
832 struct mwifiex_adapter *adapter = priv->adapter; 824 struct mwifiex_adapter *adapter = priv->adapter;
833 struct host_cmd_ds_command *resp =
834 (struct host_cmd_ds_command *) cmd_buf;
835 void *data_buf = adapter->curr_cmd->data_buf; 825 void *data_buf = adapter->curr_cmd->data_buf;
836 826
837 /* If the command is not successful, cleanup and return failure */ 827 /* If the command is not successful, cleanup and return failure */
@@ -865,7 +855,7 @@ int mwifiex_process_sta_cmdresp(struct mwifiex_private *priv,
865 "info: CMD_RESP: BG_SCAN result is ready!\n"); 855 "info: CMD_RESP: BG_SCAN result is ready!\n");
866 break; 856 break;
867 case HostCmd_CMD_TXPWR_CFG: 857 case HostCmd_CMD_TXPWR_CFG:
868 ret = mwifiex_ret_tx_power_cfg(priv, resp, data_buf); 858 ret = mwifiex_ret_tx_power_cfg(priv, resp);
869 break; 859 break;
870 case HostCmd_CMD_802_11_PS_MODE_ENH: 860 case HostCmd_CMD_802_11_PS_MODE_ENH:
871 ret = mwifiex_ret_enh_power_mode(priv, resp, data_buf); 861 ret = mwifiex_ret_enh_power_mode(priv, resp, data_buf);
diff --git a/drivers/net/wireless/mwifiex/sta_ioctl.c b/drivers/net/wireless/mwifiex/sta_ioctl.c
index d05907d05039..c34ff8c4f4f8 100644
--- a/drivers/net/wireless/mwifiex/sta_ioctl.c
+++ b/drivers/net/wireless/mwifiex/sta_ioctl.c
@@ -487,6 +487,20 @@ int mwifiex_set_radio_band_cfg(struct mwifiex_private *priv,
487} 487}
488 488
489/* 489/*
490 * The function disables auto deep sleep mode.
491 */
492int mwifiex_disable_auto_ds(struct mwifiex_private *priv)
493{
494 struct mwifiex_ds_auto_ds auto_ds;
495
496 auto_ds.auto_ds = DEEP_SLEEP_OFF;
497
498 return mwifiex_send_cmd_sync(priv, HostCmd_CMD_802_11_PS_MODE_ENH,
499 DIS_AUTO_PS, BITMAP_AUTO_DS, &auto_ds);
500}
501EXPORT_SYMBOL_GPL(mwifiex_disable_auto_ds);
502
503/*
490 * IOCTL request handler to set/get active channel. 504 * IOCTL request handler to set/get active channel.
491 * 505 *
492 * This function performs validity checking on channel/frequency 506 * This function performs validity checking on channel/frequency
diff --git a/drivers/net/wireless/mwifiex/sta_rx.c b/drivers/net/wireless/mwifiex/sta_rx.c
index 1fdddece7479..27430512f7cd 100644
--- a/drivers/net/wireless/mwifiex/sta_rx.c
+++ b/drivers/net/wireless/mwifiex/sta_rx.c
@@ -187,7 +187,7 @@ int mwifiex_process_sta_rx_packet(struct mwifiex_adapter *adapter,
187 ret = mwifiex_11n_rx_reorder_pkt(priv, local_rx_pd->seq_num, 187 ret = mwifiex_11n_rx_reorder_pkt(priv, local_rx_pd->seq_num,
188 local_rx_pd->priority, ta, 188 local_rx_pd->priority, ta,
189 (u8) local_rx_pd->rx_pkt_type, 189 (u8) local_rx_pd->rx_pkt_type,
190 (void *) skb); 190 skb);
191 191
192 if (ret || (rx_pkt_type == PKT_TYPE_BAR)) { 192 if (ret || (rx_pkt_type == PKT_TYPE_BAR)) {
193 if (priv && (ret == -1)) 193 if (priv && (ret == -1))
diff --git a/drivers/net/wireless/mwifiex/sta_tx.c b/drivers/net/wireless/mwifiex/sta_tx.c
index fa6221bc9104..1822bfad8896 100644
--- a/drivers/net/wireless/mwifiex/sta_tx.c
+++ b/drivers/net/wireless/mwifiex/sta_tx.c
@@ -47,6 +47,7 @@ void *mwifiex_process_sta_txpd(struct mwifiex_private *priv,
47 struct mwifiex_adapter *adapter = priv->adapter; 47 struct mwifiex_adapter *adapter = priv->adapter;
48 struct txpd *local_tx_pd; 48 struct txpd *local_tx_pd;
49 struct mwifiex_txinfo *tx_info = MWIFIEX_SKB_TXCB(skb); 49 struct mwifiex_txinfo *tx_info = MWIFIEX_SKB_TXCB(skb);
50 u8 pad;
50 51
51 if (!skb->len) { 52 if (!skb->len) {
52 dev_err(adapter->dev, "Tx: bad packet length: %d\n", 53 dev_err(adapter->dev, "Tx: bad packet length: %d\n",
@@ -55,15 +56,19 @@ void *mwifiex_process_sta_txpd(struct mwifiex_private *priv,
55 return skb->data; 56 return skb->data;
56 } 57 }
57 58
58 BUG_ON(skb_headroom(skb) < (sizeof(*local_tx_pd) + INTF_HEADER_LEN)); 59 /* If skb->data is not aligned; add padding */
59 skb_push(skb, sizeof(*local_tx_pd)); 60 pad = (4 - (((void *)skb->data - NULL) & 0x3)) % 4;
61
62 BUG_ON(skb_headroom(skb) < (sizeof(*local_tx_pd) + INTF_HEADER_LEN
63 + pad));
64 skb_push(skb, sizeof(*local_tx_pd) + pad);
60 65
61 local_tx_pd = (struct txpd *) skb->data; 66 local_tx_pd = (struct txpd *) skb->data;
62 memset(local_tx_pd, 0, sizeof(struct txpd)); 67 memset(local_tx_pd, 0, sizeof(struct txpd));
63 local_tx_pd->bss_num = priv->bss_num; 68 local_tx_pd->bss_num = priv->bss_num;
64 local_tx_pd->bss_type = priv->bss_type; 69 local_tx_pd->bss_type = priv->bss_type;
65 local_tx_pd->tx_pkt_length = cpu_to_le16((u16) (skb->len - 70 local_tx_pd->tx_pkt_length = cpu_to_le16((u16) (skb->len -
66 sizeof(struct txpd))); 71 (sizeof(struct txpd) + pad)));
67 72
68 local_tx_pd->priority = (u8) skb->priority; 73 local_tx_pd->priority = (u8) skb->priority;
69 local_tx_pd->pkt_delay_2ms = 74 local_tx_pd->pkt_delay_2ms =
@@ -88,7 +93,7 @@ void *mwifiex_process_sta_txpd(struct mwifiex_private *priv,
88 } 93 }
89 94
90 /* Offset of actual data */ 95 /* Offset of actual data */
91 local_tx_pd->tx_pkt_offset = cpu_to_le16(sizeof(struct txpd)); 96 local_tx_pd->tx_pkt_offset = cpu_to_le16(sizeof(struct txpd) + pad);
92 97
93 /* make space for INTF_HEADER_LEN */ 98 /* make space for INTF_HEADER_LEN */
94 skb_push(skb, INTF_HEADER_LEN); 99 skb_push(skb, INTF_HEADER_LEN);
diff --git a/drivers/net/wireless/mwifiex/txrx.c b/drivers/net/wireless/mwifiex/txrx.c
index aaa50c074196..6190b2fa57a3 100644
--- a/drivers/net/wireless/mwifiex/txrx.c
+++ b/drivers/net/wireless/mwifiex/txrx.c
@@ -71,7 +71,7 @@ int mwifiex_process_tx(struct mwifiex_private *priv, struct sk_buff *skb,
71 u8 *head_ptr; 71 u8 *head_ptr;
72 struct txpd *local_tx_pd = NULL; 72 struct txpd *local_tx_pd = NULL;
73 73
74 head_ptr = (u8 *) mwifiex_process_sta_txpd(priv, skb); 74 head_ptr = mwifiex_process_sta_txpd(priv, skb);
75 if (head_ptr) { 75 if (head_ptr) {
76 if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_STA) 76 if (GET_BSS_ROLE(priv) == MWIFIEX_BSS_ROLE_STA)
77 local_tx_pd = 77 local_tx_pd =
diff --git a/drivers/net/wireless/mwifiex/wmm.c b/drivers/net/wireless/mwifiex/wmm.c
index 91634daec306..69e260b41711 100644
--- a/drivers/net/wireless/mwifiex/wmm.c
+++ b/drivers/net/wireless/mwifiex/wmm.c
@@ -121,6 +121,7 @@ mwifiex_wmm_allocate_ralist_node(struct mwifiex_adapter *adapter, u8 *ra)
121 memcpy(ra_list->ra, ra, ETH_ALEN); 121 memcpy(ra_list->ra, ra, ETH_ALEN);
122 122
123 ra_list->total_pkts_size = 0; 123 ra_list->total_pkts_size = 0;
124 ra_list->total_pkts = 0;
124 125
125 dev_dbg(adapter->dev, "info: allocated ra_list %p\n", ra_list); 126 dev_dbg(adapter->dev, "info: allocated ra_list %p\n", ra_list);
126 127
@@ -633,6 +634,8 @@ mwifiex_wmm_add_buf_txqueue(struct mwifiex_adapter *adapter,
633 ra_list = NULL; 634 ra_list = NULL;
634 } else { 635 } else {
635 memcpy(ra, skb->data, ETH_ALEN); 636 memcpy(ra, skb->data, ETH_ALEN);
637 if (ra[0] & 0x01)
638 memset(ra, 0xff, ETH_ALEN);
636 ra_list = mwifiex_wmm_get_queue_raptr(priv, tid_down, ra); 639 ra_list = mwifiex_wmm_get_queue_raptr(priv, tid_down, ra);
637 } 640 }
638 641
@@ -645,6 +648,7 @@ mwifiex_wmm_add_buf_txqueue(struct mwifiex_adapter *adapter,
645 skb_queue_tail(&ra_list->skb_head, skb); 648 skb_queue_tail(&ra_list->skb_head, skb);
646 649
647 ra_list->total_pkts_size += skb->len; 650 ra_list->total_pkts_size += skb->len;
651 ra_list->total_pkts++;
648 652
649 atomic_inc(&priv->wmm.tx_pkts_queued); 653 atomic_inc(&priv->wmm.tx_pkts_queued);
650 654
@@ -971,28 +975,6 @@ mwifiex_wmm_get_highest_priolist_ptr(struct mwifiex_adapter *adapter,
971} 975}
972 976
973/* 977/*
974 * This function gets the number of packets in the Tx queue of a
975 * particular RA list.
976 */
977static int
978mwifiex_num_pkts_in_txq(struct mwifiex_private *priv,
979 struct mwifiex_ra_list_tbl *ptr, int max_buf_size)
980{
981 int count = 0, total_size = 0;
982 struct sk_buff *skb, *tmp;
983
984 skb_queue_walk_safe(&ptr->skb_head, skb, tmp) {
985 total_size += skb->len;
986 if (total_size < max_buf_size)
987 ++count;
988 else
989 break;
990 }
991
992 return count;
993}
994
995/*
996 * This function sends a single packet to firmware for transmission. 978 * This function sends a single packet to firmware for transmission.
997 */ 979 */
998static void 980static void
@@ -1019,6 +1001,7 @@ mwifiex_send_single_packet(struct mwifiex_private *priv,
1019 dev_dbg(adapter->dev, "data: dequeuing the packet %p %p\n", ptr, skb); 1001 dev_dbg(adapter->dev, "data: dequeuing the packet %p %p\n", ptr, skb);
1020 1002
1021 ptr->total_pkts_size -= skb->len; 1003 ptr->total_pkts_size -= skb->len;
1004 ptr->total_pkts--;
1022 1005
1023 if (!skb_queue_empty(&ptr->skb_head)) 1006 if (!skb_queue_empty(&ptr->skb_head))
1024 skb_next = skb_peek(&ptr->skb_head); 1007 skb_next = skb_peek(&ptr->skb_head);
@@ -1044,6 +1027,7 @@ mwifiex_send_single_packet(struct mwifiex_private *priv,
1044 skb_queue_tail(&ptr->skb_head, skb); 1027 skb_queue_tail(&ptr->skb_head, skb);
1045 1028
1046 ptr->total_pkts_size += skb->len; 1029 ptr->total_pkts_size += skb->len;
1030 ptr->total_pkts++;
1047 tx_info->flags |= MWIFIEX_BUF_FLAG_REQUEUED_PKT; 1031 tx_info->flags |= MWIFIEX_BUF_FLAG_REQUEUED_PKT;
1048 spin_unlock_irqrestore(&priv->wmm.ra_list_spinlock, 1032 spin_unlock_irqrestore(&priv->wmm.ra_list_spinlock,
1049 ra_list_flags); 1033 ra_list_flags);
@@ -1231,9 +1215,9 @@ mwifiex_dequeue_tx_packet(struct mwifiex_adapter *adapter)
1231 } 1215 }
1232/* Minimum number of AMSDU */ 1216/* Minimum number of AMSDU */
1233#define MIN_NUM_AMSDU 2 1217#define MIN_NUM_AMSDU 2
1218
1234 if (mwifiex_is_amsdu_allowed(priv, tid) && 1219 if (mwifiex_is_amsdu_allowed(priv, tid) &&
1235 (mwifiex_num_pkts_in_txq(priv, ptr, adapter->tx_buf_size) >= 1220 (ptr->total_pkts >= MIN_NUM_AMSDU))
1236 MIN_NUM_AMSDU))
1237 mwifiex_11n_aggregate_pkt(priv, ptr, INTF_HEADER_LEN, 1221 mwifiex_11n_aggregate_pkt(priv, ptr, INTF_HEADER_LEN,
1238 ptr_index, flags); 1222 ptr_index, flags);
1239 /* ra_list_spinlock has been freed in 1223 /* ra_list_spinlock has been freed in
diff --git a/drivers/net/wireless/mwl8k.c b/drivers/net/wireless/mwl8k.c
index aeac3cc4dbe4..da36dbf8d871 100644
--- a/drivers/net/wireless/mwl8k.c
+++ b/drivers/net/wireless/mwl8k.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/interrupt.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/kernel.h> 15#include <linux/kernel.h>
15#include <linux/sched.h> 16#include <linux/sched.h>
@@ -1891,9 +1892,9 @@ mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1891 1892
1892 txpriority = index; 1893 txpriority = index;
1893 1894
1894 if (ieee80211_is_data_qos(wh->frame_control) && 1895 if (priv->ap_fw && sta && sta->ht_cap.ht_supported
1895 skb->protocol != cpu_to_be16(ETH_P_PAE) && 1896 && skb->protocol != cpu_to_be16(ETH_P_PAE)
1896 sta->ht_cap.ht_supported && priv->ap_fw) { 1897 && ieee80211_is_data_qos(wh->frame_control)) {
1897 tid = qos & 0xf; 1898 tid = qos & 0xf;
1898 mwl8k_tx_count_packet(sta, tid); 1899 mwl8k_tx_count_packet(sta, tid);
1899 spin_lock(&priv->stream_lock); 1900 spin_lock(&priv->stream_lock);
diff --git a/drivers/net/wireless/orinoco/airport.c b/drivers/net/wireless/orinoco/airport.c
index 4a0a0e5265c9..0ca8b1455cd9 100644
--- a/drivers/net/wireless/orinoco/airport.c
+++ b/drivers/net/wireless/orinoco/airport.c
@@ -150,7 +150,7 @@ airport_attach(struct macio_dev *mdev, const struct of_device_id *match)
150 struct orinoco_private *priv; 150 struct orinoco_private *priv;
151 struct airport *card; 151 struct airport *card;
152 unsigned long phys_addr; 152 unsigned long phys_addr;
153 hermes_t *hw; 153 struct hermes *hw;
154 154
155 if (macio_resource_count(mdev) < 1 || macio_irq_count(mdev) < 1) { 155 if (macio_resource_count(mdev) < 1 || macio_irq_count(mdev) < 1) {
156 printk(KERN_ERR PFX "Wrong interrupt/addresses in OF tree\n"); 156 printk(KERN_ERR PFX "Wrong interrupt/addresses in OF tree\n");
@@ -228,10 +228,9 @@ MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
228MODULE_DESCRIPTION("Driver for the Apple Airport wireless card."); 228MODULE_DESCRIPTION("Driver for the Apple Airport wireless card.");
229MODULE_LICENSE("Dual MPL/GPL"); 229MODULE_LICENSE("Dual MPL/GPL");
230 230
231static struct of_device_id airport_match[] = 231static struct of_device_id airport_match[] = {
232{
233 { 232 {
234 .name = "radio", 233 .name = "radio",
235 }, 234 },
236 {}, 235 {},
237}; 236};
@@ -240,7 +239,7 @@ MODULE_DEVICE_TABLE(of, airport_match);
240 239
241static struct macio_driver airport_driver = { 240static struct macio_driver airport_driver = {
242 .driver = { 241 .driver = {
243 .name = DRIVER_NAME, 242 .name = DRIVER_NAME,
244 .owner = THIS_MODULE, 243 .owner = THIS_MODULE,
245 .of_match_table = airport_match, 244 .of_match_table = airport_match,
246 }, 245 },
diff --git a/drivers/net/wireless/orinoco/cfg.c b/drivers/net/wireless/orinoco/cfg.c
index 736bbb9bd1d0..f7b15b8934fa 100644
--- a/drivers/net/wireless/orinoco/cfg.c
+++ b/drivers/net/wireless/orinoco/cfg.c
@@ -59,7 +59,7 @@ int orinoco_wiphy_register(struct wiphy *wiphy)
59 for (i = 0; i < NUM_CHANNELS; i++) { 59 for (i = 0; i < NUM_CHANNELS; i++) {
60 if (priv->channel_mask & (1 << i)) { 60 if (priv->channel_mask & (1 << i)) {
61 priv->channels[i].center_freq = 61 priv->channels[i].center_freq =
62 ieee80211_dsss_chan_to_freq(i+1); 62 ieee80211_dsss_chan_to_freq(i + 1);
63 channels++; 63 channels++;
64 } 64 }
65 } 65 }
@@ -182,7 +182,7 @@ static int orinoco_set_channel(struct wiphy *wiphy,
182 channel = ieee80211_freq_to_dsss_chan(chan->center_freq); 182 channel = ieee80211_freq_to_dsss_chan(chan->center_freq);
183 183
184 if ((channel < 1) || (channel > NUM_CHANNELS) || 184 if ((channel < 1) || (channel > NUM_CHANNELS) ||
185 !(priv->channel_mask & (1 << (channel-1)))) 185 !(priv->channel_mask & (1 << (channel - 1))))
186 return -EINVAL; 186 return -EINVAL;
187 187
188 if (orinoco_lock(priv, &flags) != 0) 188 if (orinoco_lock(priv, &flags) != 0)
@@ -191,7 +191,7 @@ static int orinoco_set_channel(struct wiphy *wiphy,
191 priv->channel = channel; 191 priv->channel = channel;
192 if (priv->iw_mode == NL80211_IFTYPE_MONITOR) { 192 if (priv->iw_mode == NL80211_IFTYPE_MONITOR) {
193 /* Fast channel change - no commit if successful */ 193 /* Fast channel change - no commit if successful */
194 hermes_t *hw = &priv->hw; 194 struct hermes *hw = &priv->hw;
195 err = hw->ops->cmd_wait(hw, HERMES_CMD_TEST | 195 err = hw->ops->cmd_wait(hw, HERMES_CMD_TEST |
196 HERMES_TEST_SET_CHANNEL, 196 HERMES_TEST_SET_CHANNEL,
197 channel, NULL); 197 channel, NULL);
diff --git a/drivers/net/wireless/orinoco/fw.c b/drivers/net/wireless/orinoco/fw.c
index 259d75853984..527cf5333db5 100644
--- a/drivers/net/wireless/orinoco/fw.c
+++ b/drivers/net/wireless/orinoco/fw.c
@@ -100,7 +100,7 @@ orinoco_dl_firmware(struct orinoco_private *priv,
100 /* Plug Data Area (PDA) */ 100 /* Plug Data Area (PDA) */
101 __le16 *pda; 101 __le16 *pda;
102 102
103 hermes_t *hw = &priv->hw; 103 struct hermes *hw = &priv->hw;
104 const struct firmware *fw_entry; 104 const struct firmware *fw_entry;
105 const struct orinoco_fw_header *hdr; 105 const struct orinoco_fw_header *hdr;
106 const unsigned char *first_block; 106 const unsigned char *first_block;
@@ -205,7 +205,7 @@ symbol_dl_image(struct orinoco_private *priv, const struct fw_info *fw,
205 const unsigned char *image, const void *end, 205 const unsigned char *image, const void *end,
206 int secondary) 206 int secondary)
207{ 207{
208 hermes_t *hw = &priv->hw; 208 struct hermes *hw = &priv->hw;
209 int ret = 0; 209 int ret = 0;
210 const unsigned char *ptr; 210 const unsigned char *ptr;
211 const unsigned char *first_block; 211 const unsigned char *first_block;
@@ -322,9 +322,8 @@ symbol_dl_firmware(struct orinoco_private *priv,
322 fw_entry->data + fw_entry->size, 1); 322 fw_entry->data + fw_entry->size, 1);
323 if (!orinoco_cached_fw_get(priv, false)) 323 if (!orinoco_cached_fw_get(priv, false))
324 release_firmware(fw_entry); 324 release_firmware(fw_entry);
325 if (ret) { 325 if (ret)
326 dev_err(dev, "Secondary firmware download failed\n"); 326 dev_err(dev, "Secondary firmware download failed\n");
327 }
328 327
329 return ret; 328 return ret;
330} 329}
diff --git a/drivers/net/wireless/orinoco/fw.h b/drivers/net/wireless/orinoco/fw.h
index 89fc26d25b06..aca63e3c4b5b 100644
--- a/drivers/net/wireless/orinoco/fw.h
+++ b/drivers/net/wireless/orinoco/fw.h
@@ -14,7 +14,7 @@ int orinoco_download(struct orinoco_private *priv);
14void orinoco_cache_fw(struct orinoco_private *priv, int ap); 14void orinoco_cache_fw(struct orinoco_private *priv, int ap);
15void orinoco_uncache_fw(struct orinoco_private *priv); 15void orinoco_uncache_fw(struct orinoco_private *priv);
16#else 16#else
17#define orinoco_cache_fw(priv, ap) do { } while(0) 17#define orinoco_cache_fw(priv, ap) do { } while (0)
18#define orinoco_uncache_fw(priv) do { } while (0) 18#define orinoco_uncache_fw(priv) do { } while (0)
19#endif 19#endif
20 20
diff --git a/drivers/net/wireless/orinoco/hermes.c b/drivers/net/wireless/orinoco/hermes.c
index 6c6a23e08df6..75c15bc7b34c 100644
--- a/drivers/net/wireless/orinoco/hermes.c
+++ b/drivers/net/wireless/orinoco/hermes.c
@@ -103,7 +103,7 @@ static const struct hermes_ops hermes_ops_local;
103 103
104 Callable from any context. 104 Callable from any context.
105*/ 105*/
106static int hermes_issue_cmd(hermes_t *hw, u16 cmd, u16 param0, 106static int hermes_issue_cmd(struct hermes *hw, u16 cmd, u16 param0,
107 u16 param1, u16 param2) 107 u16 param1, u16 param2)
108{ 108{
109 int k = CMD_BUSY_TIMEOUT; 109 int k = CMD_BUSY_TIMEOUT;
@@ -132,7 +132,7 @@ static int hermes_issue_cmd(hermes_t *hw, u16 cmd, u16 param0,
132 */ 132 */
133 133
134/* For doing cmds that wipe the magic constant in SWSUPPORT0 */ 134/* For doing cmds that wipe the magic constant in SWSUPPORT0 */
135static int hermes_doicmd_wait(hermes_t *hw, u16 cmd, 135static int hermes_doicmd_wait(struct hermes *hw, u16 cmd,
136 u16 parm0, u16 parm1, u16 parm2, 136 u16 parm0, u16 parm1, u16 parm2,
137 struct hermes_response *resp) 137 struct hermes_response *resp)
138{ 138{
@@ -185,7 +185,8 @@ out:
185 return err; 185 return err;
186} 186}
187 187
188void hermes_struct_init(hermes_t *hw, void __iomem *address, int reg_spacing) 188void hermes_struct_init(struct hermes *hw, void __iomem *address,
189 int reg_spacing)
189{ 190{
190 hw->iobase = address; 191 hw->iobase = address;
191 hw->reg_spacing = reg_spacing; 192 hw->reg_spacing = reg_spacing;
@@ -195,7 +196,7 @@ void hermes_struct_init(hermes_t *hw, void __iomem *address, int reg_spacing)
195} 196}
196EXPORT_SYMBOL(hermes_struct_init); 197EXPORT_SYMBOL(hermes_struct_init);
197 198
198static int hermes_init(hermes_t *hw) 199static int hermes_init(struct hermes *hw)
199{ 200{
200 u16 reg; 201 u16 reg;
201 int err = 0; 202 int err = 0;
@@ -249,7 +250,7 @@ static int hermes_init(hermes_t *hw)
249 * > 0 on error returned by the firmware 250 * > 0 on error returned by the firmware
250 * 251 *
251 * Callable from any context, but locking is your problem. */ 252 * Callable from any context, but locking is your problem. */
252static int hermes_docmd_wait(hermes_t *hw, u16 cmd, u16 parm0, 253static int hermes_docmd_wait(struct hermes *hw, u16 cmd, u16 parm0,
253 struct hermes_response *resp) 254 struct hermes_response *resp)
254{ 255{
255 int err; 256 int err;
@@ -313,7 +314,7 @@ static int hermes_docmd_wait(hermes_t *hw, u16 cmd, u16 parm0,
313 return err; 314 return err;
314} 315}
315 316
316static int hermes_allocate(hermes_t *hw, u16 size, u16 *fid) 317static int hermes_allocate(struct hermes *hw, u16 size, u16 *fid)
317{ 318{
318 int err = 0; 319 int err = 0;
319 int k; 320 int k;
@@ -363,7 +364,7 @@ static int hermes_allocate(hermes_t *hw, u16 size, u16 *fid)
363 * from firmware 364 * from firmware
364 * 365 *
365 * Callable from any context */ 366 * Callable from any context */
366static int hermes_bap_seek(hermes_t *hw, int bap, u16 id, u16 offset) 367static int hermes_bap_seek(struct hermes *hw, int bap, u16 id, u16 offset)
367{ 368{
368 int sreg = bap ? HERMES_SELECT1 : HERMES_SELECT0; 369 int sreg = bap ? HERMES_SELECT1 : HERMES_SELECT0;
369 int oreg = bap ? HERMES_OFFSET1 : HERMES_OFFSET0; 370 int oreg = bap ? HERMES_OFFSET1 : HERMES_OFFSET0;
@@ -422,7 +423,7 @@ static int hermes_bap_seek(hermes_t *hw, int bap, u16 id, u16 offset)
422 * 0 on success 423 * 0 on success
423 * > 0 on error from firmware 424 * > 0 on error from firmware
424 */ 425 */
425static int hermes_bap_pread(hermes_t *hw, int bap, void *buf, int len, 426static int hermes_bap_pread(struct hermes *hw, int bap, void *buf, int len,
426 u16 id, u16 offset) 427 u16 id, u16 offset)
427{ 428{
428 int dreg = bap ? HERMES_DATA1 : HERMES_DATA0; 429 int dreg = bap ? HERMES_DATA1 : HERMES_DATA0;
@@ -436,7 +437,7 @@ static int hermes_bap_pread(hermes_t *hw, int bap, void *buf, int len,
436 goto out; 437 goto out;
437 438
438 /* Actually do the transfer */ 439 /* Actually do the transfer */
439 hermes_read_words(hw, dreg, buf, len/2); 440 hermes_read_words(hw, dreg, buf, len / 2);
440 441
441 out: 442 out:
442 return err; 443 return err;
@@ -450,8 +451,8 @@ static int hermes_bap_pread(hermes_t *hw, int bap, void *buf, int len,
450 * 0 on success 451 * 0 on success
451 * > 0 on error from firmware 452 * > 0 on error from firmware
452 */ 453 */
453static int hermes_bap_pwrite(hermes_t *hw, int bap, const void *buf, int len, 454static int hermes_bap_pwrite(struct hermes *hw, int bap, const void *buf,
454 u16 id, u16 offset) 455 int len, u16 id, u16 offset)
455{ 456{
456 int dreg = bap ? HERMES_DATA1 : HERMES_DATA0; 457 int dreg = bap ? HERMES_DATA1 : HERMES_DATA0;
457 int err = 0; 458 int err = 0;
@@ -478,8 +479,8 @@ static int hermes_bap_pwrite(hermes_t *hw, int bap, const void *buf, int len,
478 * practice. 479 * practice.
479 * 480 *
480 * Callable from user or bh context. */ 481 * Callable from user or bh context. */
481static int hermes_read_ltv(hermes_t *hw, int bap, u16 rid, unsigned bufsize, 482static int hermes_read_ltv(struct hermes *hw, int bap, u16 rid,
482 u16 *length, void *buf) 483 unsigned bufsize, u16 *length, void *buf)
483{ 484{
484 int err = 0; 485 int err = 0;
485 int dreg = bap ? HERMES_DATA1 : HERMES_DATA0; 486 int dreg = bap ? HERMES_DATA1 : HERMES_DATA0;
@@ -523,7 +524,7 @@ static int hermes_read_ltv(hermes_t *hw, int bap, u16 rid, unsigned bufsize,
523 return 0; 524 return 0;
524} 525}
525 526
526static int hermes_write_ltv(hermes_t *hw, int bap, u16 rid, 527static int hermes_write_ltv(struct hermes *hw, int bap, u16 rid,
527 u16 length, const void *value) 528 u16 length, const void *value)
528{ 529{
529 int dreg = bap ? HERMES_DATA1 : HERMES_DATA0; 530 int dreg = bap ? HERMES_DATA1 : HERMES_DATA0;
@@ -553,14 +554,14 @@ static int hermes_write_ltv(hermes_t *hw, int bap, u16 rid,
553/*** Hermes AUX control ***/ 554/*** Hermes AUX control ***/
554 555
555static inline void 556static inline void
556hermes_aux_setaddr(hermes_t *hw, u32 addr) 557hermes_aux_setaddr(struct hermes *hw, u32 addr)
557{ 558{
558 hermes_write_reg(hw, HERMES_AUXPAGE, (u16) (addr >> 7)); 559 hermes_write_reg(hw, HERMES_AUXPAGE, (u16) (addr >> 7));
559 hermes_write_reg(hw, HERMES_AUXOFFSET, (u16) (addr & 0x7F)); 560 hermes_write_reg(hw, HERMES_AUXOFFSET, (u16) (addr & 0x7F));
560} 561}
561 562
562static inline int 563static inline int
563hermes_aux_control(hermes_t *hw, int enabled) 564hermes_aux_control(struct hermes *hw, int enabled)
564{ 565{
565 int desired_state = enabled ? HERMES_AUX_ENABLED : HERMES_AUX_DISABLED; 566 int desired_state = enabled ? HERMES_AUX_ENABLED : HERMES_AUX_DISABLED;
566 int action = enabled ? HERMES_AUX_ENABLE : HERMES_AUX_DISABLE; 567 int action = enabled ? HERMES_AUX_ENABLE : HERMES_AUX_DISABLE;
@@ -594,7 +595,7 @@ hermes_aux_control(hermes_t *hw, int enabled)
594 * wl_lkm Agere fw does 595 * wl_lkm Agere fw does
595 * Don't know about intersil 596 * Don't know about intersil
596 */ 597 */
597static int hermesi_program_init(hermes_t *hw, u32 offset) 598static int hermesi_program_init(struct hermes *hw, u32 offset)
598{ 599{
599 int err; 600 int err;
600 601
@@ -643,7 +644,7 @@ static int hermesi_program_init(hermes_t *hw, u32 offset)
643 * wl_lkm Agere fw does 644 * wl_lkm Agere fw does
644 * Don't know about intersil 645 * Don't know about intersil
645 */ 646 */
646static int hermesi_program_end(hermes_t *hw) 647static int hermesi_program_end(struct hermes *hw)
647{ 648{
648 struct hermes_response resp; 649 struct hermes_response resp;
649 int rc = 0; 650 int rc = 0;
@@ -684,7 +685,8 @@ static int hermes_program_bytes(struct hermes *hw, const char *data,
684} 685}
685 686
686/* Read PDA from the adapter */ 687/* Read PDA from the adapter */
687static int hermes_read_pda(hermes_t *hw, __le16 *pda, u32 pda_addr, u16 pda_len) 688static int hermes_read_pda(struct hermes *hw, __le16 *pda, u32 pda_addr,
689 u16 pda_len)
688{ 690{
689 int ret; 691 int ret;
690 u16 pda_size; 692 u16 pda_size;
diff --git a/drivers/net/wireless/orinoco/hermes.h b/drivers/net/wireless/orinoco/hermes.h
index d9f18c11682a..28a42448d329 100644
--- a/drivers/net/wireless/orinoco/hermes.h
+++ b/drivers/net/wireless/orinoco/hermes.h
@@ -28,7 +28,7 @@
28 * 28 *
29 * As a module of low level hardware access routines, there is no 29 * As a module of low level hardware access routines, there is no
30 * locking. Users of this module should ensure that they serialize 30 * locking. Users of this module should ensure that they serialize
31 * access to the hermes_t structure, and to the hardware 31 * access to the hermes structure, and to the hardware
32*/ 32*/
33 33
34#include <linux/if_ether.h> 34#include <linux/if_ether.h>
@@ -43,7 +43,7 @@
43#define HERMES_BAP_DATALEN_MAX (4096) 43#define HERMES_BAP_DATALEN_MAX (4096)
44#define HERMES_BAP_OFFSET_MAX (4096) 44#define HERMES_BAP_OFFSET_MAX (4096)
45#define HERMES_PORTID_MAX (7) 45#define HERMES_PORTID_MAX (7)
46#define HERMES_NUMPORTS_MAX (HERMES_PORTID_MAX+1) 46#define HERMES_NUMPORTS_MAX (HERMES_PORTID_MAX + 1)
47#define HERMES_PDR_LEN_MAX (260) /* in bytes, from EK */ 47#define HERMES_PDR_LEN_MAX (260) /* in bytes, from EK */
48#define HERMES_PDA_RECS_MAX (200) /* a guess */ 48#define HERMES_PDA_RECS_MAX (200) /* a guess */
49#define HERMES_PDA_LEN_MAX (1024) /* in bytes, from EK */ 49#define HERMES_PDA_LEN_MAX (1024) /* in bytes, from EK */
@@ -148,7 +148,7 @@
148#define HERMES_CMD_WRITEMIF (0x0031) 148#define HERMES_CMD_WRITEMIF (0x0031)
149 149
150/*--- Debugging Commands -----------------------------*/ 150/*--- Debugging Commands -----------------------------*/
151#define HERMES_CMD_TEST (0x0038) 151#define HERMES_CMD_TEST (0x0038)
152 152
153 153
154/* Test command arguments */ 154/* Test command arguments */
@@ -178,8 +178,8 @@
178 178
179#define HERMES_DESCRIPTOR_OFFSET 0 179#define HERMES_DESCRIPTOR_OFFSET 0
180#define HERMES_802_11_OFFSET (14) 180#define HERMES_802_11_OFFSET (14)
181#define HERMES_802_3_OFFSET (14+32) 181#define HERMES_802_3_OFFSET (14 + 32)
182#define HERMES_802_2_OFFSET (14+32+14) 182#define HERMES_802_2_OFFSET (14 + 32 + 14)
183#define HERMES_TXCNTL2_OFFSET (HERMES_802_3_OFFSET - 2) 183#define HERMES_TXCNTL2_OFFSET (HERMES_802_3_OFFSET - 2)
184 184
185#define HERMES_RXSTAT_ERR (0x0003) 185#define HERMES_RXSTAT_ERR (0x0003)
@@ -406,7 +406,7 @@ struct hermes_ops {
406}; 406};
407 407
408/* Basic control structure */ 408/* Basic control structure */
409typedef struct hermes { 409struct hermes {
410 void __iomem *iobase; 410 void __iomem *iobase;
411 int reg_spacing; 411 int reg_spacing;
412#define HERMES_16BIT_REGSPACING 0 412#define HERMES_16BIT_REGSPACING 0
@@ -415,7 +415,7 @@ typedef struct hermes {
415 bool eeprom_pda; 415 bool eeprom_pda;
416 const struct hermes_ops *ops; 416 const struct hermes_ops *ops;
417 void *priv; 417 void *priv;
418} hermes_t; 418};
419 419
420/* Register access convenience macros */ 420/* Register access convenience macros */
421#define hermes_read_reg(hw, off) \ 421#define hermes_read_reg(hw, off) \
@@ -427,28 +427,29 @@ typedef struct hermes {
427 hermes_write_reg((hw), HERMES_##name, (val)) 427 hermes_write_reg((hw), HERMES_##name, (val))
428 428
429/* Function prototypes */ 429/* Function prototypes */
430void hermes_struct_init(hermes_t *hw, void __iomem *address, int reg_spacing); 430void hermes_struct_init(struct hermes *hw, void __iomem *address,
431 int reg_spacing);
431 432
432/* Inline functions */ 433/* Inline functions */
433 434
434static inline int hermes_present(hermes_t *hw) 435static inline int hermes_present(struct hermes *hw)
435{ 436{
436 return hermes_read_regn(hw, SWSUPPORT0) == HERMES_MAGIC; 437 return hermes_read_regn(hw, SWSUPPORT0) == HERMES_MAGIC;
437} 438}
438 439
439static inline void hermes_set_irqmask(hermes_t *hw, u16 events) 440static inline void hermes_set_irqmask(struct hermes *hw, u16 events)
440{ 441{
441 hw->inten = events; 442 hw->inten = events;
442 hermes_write_regn(hw, INTEN, events); 443 hermes_write_regn(hw, INTEN, events);
443} 444}
444 445
445static inline int hermes_enable_port(hermes_t *hw, int port) 446static inline int hermes_enable_port(struct hermes *hw, int port)
446{ 447{
447 return hw->ops->cmd_wait(hw, HERMES_CMD_ENABLE | (port << 8), 448 return hw->ops->cmd_wait(hw, HERMES_CMD_ENABLE | (port << 8),
448 0, NULL); 449 0, NULL);
449} 450}
450 451
451static inline int hermes_disable_port(hermes_t *hw, int port) 452static inline int hermes_disable_port(struct hermes *hw, int port)
452{ 453{
453 return hw->ops->cmd_wait(hw, HERMES_CMD_DISABLE | (port << 8), 454 return hw->ops->cmd_wait(hw, HERMES_CMD_DISABLE | (port << 8),
454 0, NULL); 455 0, NULL);
@@ -456,13 +457,13 @@ static inline int hermes_disable_port(hermes_t *hw, int port)
456 457
457/* Initiate an INQUIRE command (tallies or scan). The result will come as an 458/* Initiate an INQUIRE command (tallies or scan). The result will come as an
458 * information frame in __orinoco_ev_info() */ 459 * information frame in __orinoco_ev_info() */
459static inline int hermes_inquire(hermes_t *hw, u16 rid) 460static inline int hermes_inquire(struct hermes *hw, u16 rid)
460{ 461{
461 return hw->ops->cmd_wait(hw, HERMES_CMD_INQUIRE, rid, NULL); 462 return hw->ops->cmd_wait(hw, HERMES_CMD_INQUIRE, rid, NULL);
462} 463}
463 464
464#define HERMES_BYTES_TO_RECLEN(n) ((((n)+1)/2) + 1) 465#define HERMES_BYTES_TO_RECLEN(n) ((((n) + 1) / 2) + 1)
465#define HERMES_RECLEN_TO_BYTES(n) (((n)-1) * 2) 466#define HERMES_RECLEN_TO_BYTES(n) (((n) - 1) * 2)
466 467
467/* Note that for the next two, the count is in 16-bit words, not bytes */ 468/* Note that for the next two, the count is in 16-bit words, not bytes */
468static inline void hermes_read_words(struct hermes *hw, int off, 469static inline void hermes_read_words(struct hermes *hw, int off,
@@ -498,7 +499,8 @@ static inline void hermes_clear_words(struct hermes *hw, int off,
498 (hw->ops->write_ltv((hw), (bap), (rid), \ 499 (hw->ops->write_ltv((hw), (bap), (rid), \
499 HERMES_BYTES_TO_RECLEN(sizeof(*buf)), (buf))) 500 HERMES_BYTES_TO_RECLEN(sizeof(*buf)), (buf)))
500 501
501static inline int hermes_read_wordrec(hermes_t *hw, int bap, u16 rid, u16 *word) 502static inline int hermes_read_wordrec(struct hermes *hw, int bap, u16 rid,
503 u16 *word)
502{ 504{
503 __le16 rec; 505 __le16 rec;
504 int err; 506 int err;
@@ -508,7 +510,8 @@ static inline int hermes_read_wordrec(hermes_t *hw, int bap, u16 rid, u16 *word)
508 return err; 510 return err;
509} 511}
510 512
511static inline int hermes_write_wordrec(hermes_t *hw, int bap, u16 rid, u16 word) 513static inline int hermes_write_wordrec(struct hermes *hw, int bap, u16 rid,
514 u16 word)
512{ 515{
513 __le16 rec = cpu_to_le16(word); 516 __le16 rec = cpu_to_le16(word);
514 return HERMES_WRITE_RECORD(hw, bap, rid, &rec); 517 return HERMES_WRITE_RECORD(hw, bap, rid, &rec);
diff --git a/drivers/net/wireless/orinoco/hermes_dld.c b/drivers/net/wireless/orinoco/hermes_dld.c
index 2b2b9a1a979c..4a10b7aca043 100644
--- a/drivers/net/wireless/orinoco/hermes_dld.c
+++ b/drivers/net/wireless/orinoco/hermes_dld.c
@@ -193,7 +193,7 @@ hermes_find_pdi(const struct pdi *first_pdi, u32 record_id, const void *end)
193 193
194/* Process one Plug Data Item - find corresponding PDR and plug it */ 194/* Process one Plug Data Item - find corresponding PDR and plug it */
195static int 195static int
196hermes_plug_pdi(hermes_t *hw, const struct pdr *first_pdr, 196hermes_plug_pdi(struct hermes *hw, const struct pdr *first_pdr,
197 const struct pdi *pdi, const void *pdr_end) 197 const struct pdi *pdi, const void *pdr_end)
198{ 198{
199 const struct pdr *pdr; 199 const struct pdr *pdr;
@@ -220,7 +220,7 @@ hermes_plug_pdi(hermes_t *hw, const struct pdr *first_pdr,
220 * Attempt to write every records that is in the specified pda 220 * Attempt to write every records that is in the specified pda
221 * which also has a valid production data record for the firmware. 221 * which also has a valid production data record for the firmware.
222 */ 222 */
223int hermes_apply_pda(hermes_t *hw, 223int hermes_apply_pda(struct hermes *hw,
224 const char *first_pdr, 224 const char *first_pdr,
225 const void *pdr_end, 225 const void *pdr_end,
226 const __le16 *pda, 226 const __le16 *pda,
@@ -274,7 +274,7 @@ hermes_blocks_length(const char *first_block, const void *end)
274/*** Hermes programming ***/ 274/*** Hermes programming ***/
275 275
276/* Program the data blocks */ 276/* Program the data blocks */
277int hermes_program(hermes_t *hw, const char *first_block, const void *end) 277int hermes_program(struct hermes *hw, const char *first_block, const void *end)
278{ 278{
279 const struct dblock *blk; 279 const struct dblock *blk;
280 u32 blkaddr; 280 u32 blkaddr;
@@ -387,7 +387,7 @@ DEFINE_DEFAULT_PDR(0x0161, 256,
387 * 387 *
388 * For certain records, use defaults if they are not found in pda. 388 * For certain records, use defaults if they are not found in pda.
389 */ 389 */
390int hermes_apply_pda_with_defaults(hermes_t *hw, 390int hermes_apply_pda_with_defaults(struct hermes *hw,
391 const char *first_pdr, 391 const char *first_pdr,
392 const void *pdr_end, 392 const void *pdr_end,
393 const __le16 *pda, 393 const __le16 *pda,
diff --git a/drivers/net/wireless/orinoco/hermes_dld.h b/drivers/net/wireless/orinoco/hermes_dld.h
index 583a5bcf9175..b5377e232c63 100644
--- a/drivers/net/wireless/orinoco/hermes_dld.h
+++ b/drivers/net/wireless/orinoco/hermes_dld.h
@@ -27,21 +27,21 @@
27 27
28#include "hermes.h" 28#include "hermes.h"
29 29
30int hermesi_program_init(hermes_t *hw, u32 offset); 30int hermesi_program_init(struct hermes *hw, u32 offset);
31int hermesi_program_end(hermes_t *hw); 31int hermesi_program_end(struct hermes *hw);
32int hermes_program(hermes_t *hw, const char *first_block, const void *end); 32int hermes_program(struct hermes *hw, const char *first_block, const void *end);
33 33
34int hermes_read_pda(hermes_t *hw, 34int hermes_read_pda(struct hermes *hw,
35 __le16 *pda, 35 __le16 *pda,
36 u32 pda_addr, 36 u32 pda_addr,
37 u16 pda_len, 37 u16 pda_len,
38 int use_eeprom); 38 int use_eeprom);
39int hermes_apply_pda(hermes_t *hw, 39int hermes_apply_pda(struct hermes *hw,
40 const char *first_pdr, 40 const char *first_pdr,
41 const void *pdr_end, 41 const void *pdr_end,
42 const __le16 *pda, 42 const __le16 *pda,
43 const void *pda_end); 43 const void *pda_end);
44int hermes_apply_pda_with_defaults(hermes_t *hw, 44int hermes_apply_pda_with_defaults(struct hermes *hw,
45 const char *first_pdr, 45 const char *first_pdr,
46 const void *pdr_end, 46 const void *pdr_end,
47 const __le16 *pda, 47 const __le16 *pda,
diff --git a/drivers/net/wireless/orinoco/hw.c b/drivers/net/wireless/orinoco/hw.c
index 3c7877a7c31c..c09c8437c0b8 100644
--- a/drivers/net/wireless/orinoco/hw.c
+++ b/drivers/net/wireless/orinoco/hw.c
@@ -47,7 +47,7 @@ struct comp_id {
47 u16 id, variant, major, minor; 47 u16 id, variant, major, minor;
48} __packed; 48} __packed;
49 49
50static inline fwtype_t determine_firmware_type(struct comp_id *nic_id) 50static inline enum fwtype determine_firmware_type(struct comp_id *nic_id)
51{ 51{
52 if (nic_id->id < 0x8000) 52 if (nic_id->id < 0x8000)
53 return FIRMWARE_TYPE_AGERE; 53 return FIRMWARE_TYPE_AGERE;
@@ -71,11 +71,11 @@ int determine_fw_capabilities(struct orinoco_private *priv,
71 u32 *hw_ver) 71 u32 *hw_ver)
72{ 72{
73 struct device *dev = priv->dev; 73 struct device *dev = priv->dev;
74 hermes_t *hw = &priv->hw; 74 struct hermes *hw = &priv->hw;
75 int err; 75 int err;
76 struct comp_id nic_id, sta_id; 76 struct comp_id nic_id, sta_id;
77 unsigned int firmver; 77 unsigned int firmver;
78 char tmp[SYMBOL_MAX_VER_LEN+1] __attribute__((aligned(2))); 78 char tmp[SYMBOL_MAX_VER_LEN + 1] __attribute__((aligned(2)));
79 79
80 /* Get the hardware version */ 80 /* Get the hardware version */
81 err = HERMES_READ_RECORD(hw, USER_BAP, HERMES_RID_NICID, &nic_id); 81 err = HERMES_READ_RECORD(hw, USER_BAP, HERMES_RID_NICID, &nic_id);
@@ -280,7 +280,7 @@ int orinoco_hw_read_card_settings(struct orinoco_private *priv, u8 *dev_addr)
280{ 280{
281 struct device *dev = priv->dev; 281 struct device *dev = priv->dev;
282 struct hermes_idstring nickbuf; 282 struct hermes_idstring nickbuf;
283 hermes_t *hw = &priv->hw; 283 struct hermes *hw = &priv->hw;
284 int len; 284 int len;
285 int err; 285 int err;
286 u16 reclen; 286 u16 reclen;
@@ -458,7 +458,7 @@ int orinoco_hw_program_rids(struct orinoco_private *priv)
458{ 458{
459 struct net_device *dev = priv->ndev; 459 struct net_device *dev = priv->ndev;
460 struct wireless_dev *wdev = netdev_priv(dev); 460 struct wireless_dev *wdev = netdev_priv(dev);
461 hermes_t *hw = &priv->hw; 461 struct hermes *hw = &priv->hw;
462 int err; 462 int err;
463 struct hermes_idstring idbuf; 463 struct hermes_idstring idbuf;
464 464
@@ -529,7 +529,7 @@ int orinoco_hw_program_rids(struct orinoco_private *priv)
529 memcpy(&idbuf.val, priv->desired_essid, sizeof(idbuf.val)); 529 memcpy(&idbuf.val, priv->desired_essid, sizeof(idbuf.val));
530 /* WinXP wants partner to configure OWNSSID even in IBSS mode. (jimc) */ 530 /* WinXP wants partner to configure OWNSSID even in IBSS mode. (jimc) */
531 err = hw->ops->write_ltv(hw, USER_BAP, HERMES_RID_CNFOWNSSID, 531 err = hw->ops->write_ltv(hw, USER_BAP, HERMES_RID_CNFOWNSSID,
532 HERMES_BYTES_TO_RECLEN(strlen(priv->desired_essid)+2), 532 HERMES_BYTES_TO_RECLEN(strlen(priv->desired_essid) + 2),
533 &idbuf); 533 &idbuf);
534 if (err) { 534 if (err) {
535 printk(KERN_ERR "%s: Error %d setting OWNSSID\n", 535 printk(KERN_ERR "%s: Error %d setting OWNSSID\n",
@@ -537,7 +537,7 @@ int orinoco_hw_program_rids(struct orinoco_private *priv)
537 return err; 537 return err;
538 } 538 }
539 err = hw->ops->write_ltv(hw, USER_BAP, HERMES_RID_CNFDESIREDSSID, 539 err = hw->ops->write_ltv(hw, USER_BAP, HERMES_RID_CNFDESIREDSSID,
540 HERMES_BYTES_TO_RECLEN(strlen(priv->desired_essid)+2), 540 HERMES_BYTES_TO_RECLEN(strlen(priv->desired_essid) + 2),
541 &idbuf); 541 &idbuf);
542 if (err) { 542 if (err) {
543 printk(KERN_ERR "%s: Error %d setting DESIREDSSID\n", 543 printk(KERN_ERR "%s: Error %d setting DESIREDSSID\n",
@@ -549,7 +549,7 @@ int orinoco_hw_program_rids(struct orinoco_private *priv)
549 idbuf.len = cpu_to_le16(strlen(priv->nick)); 549 idbuf.len = cpu_to_le16(strlen(priv->nick));
550 memcpy(&idbuf.val, priv->nick, sizeof(idbuf.val)); 550 memcpy(&idbuf.val, priv->nick, sizeof(idbuf.val));
551 err = hw->ops->write_ltv(hw, USER_BAP, HERMES_RID_CNFOWNNAME, 551 err = hw->ops->write_ltv(hw, USER_BAP, HERMES_RID_CNFOWNNAME,
552 HERMES_BYTES_TO_RECLEN(strlen(priv->nick)+2), 552 HERMES_BYTES_TO_RECLEN(strlen(priv->nick) + 2),
553 &idbuf); 553 &idbuf);
554 if (err) { 554 if (err) {
555 printk(KERN_ERR "%s: Error %d setting nickname\n", 555 printk(KERN_ERR "%s: Error %d setting nickname\n",
@@ -689,7 +689,7 @@ int orinoco_hw_program_rids(struct orinoco_private *priv)
689/* Get tsc from the firmware */ 689/* Get tsc from the firmware */
690int orinoco_hw_get_tkip_iv(struct orinoco_private *priv, int key, u8 *tsc) 690int orinoco_hw_get_tkip_iv(struct orinoco_private *priv, int key, u8 *tsc)
691{ 691{
692 hermes_t *hw = &priv->hw; 692 struct hermes *hw = &priv->hw;
693 int err = 0; 693 int err = 0;
694 u8 tsc_arr[4][ORINOCO_SEQ_LEN]; 694 u8 tsc_arr[4][ORINOCO_SEQ_LEN];
695 695
@@ -706,7 +706,7 @@ int orinoco_hw_get_tkip_iv(struct orinoco_private *priv, int key, u8 *tsc)
706 706
707int __orinoco_hw_set_bitrate(struct orinoco_private *priv) 707int __orinoco_hw_set_bitrate(struct orinoco_private *priv)
708{ 708{
709 hermes_t *hw = &priv->hw; 709 struct hermes *hw = &priv->hw;
710 int ratemode = priv->bitratemode; 710 int ratemode = priv->bitratemode;
711 int err = 0; 711 int err = 0;
712 712
@@ -737,7 +737,7 @@ int __orinoco_hw_set_bitrate(struct orinoco_private *priv)
737 737
738int orinoco_hw_get_act_bitrate(struct orinoco_private *priv, int *bitrate) 738int orinoco_hw_get_act_bitrate(struct orinoco_private *priv, int *bitrate)
739{ 739{
740 hermes_t *hw = &priv->hw; 740 struct hermes *hw = &priv->hw;
741 int i; 741 int i;
742 int err = 0; 742 int err = 0;
743 u16 val; 743 u16 val;
@@ -786,7 +786,7 @@ int __orinoco_hw_set_wap(struct orinoco_private *priv)
786{ 786{
787 int roaming_flag; 787 int roaming_flag;
788 int err = 0; 788 int err = 0;
789 hermes_t *hw = &priv->hw; 789 struct hermes *hw = &priv->hw;
790 790
791 switch (priv->firmware_type) { 791 switch (priv->firmware_type) {
792 case FIRMWARE_TYPE_AGERE: 792 case FIRMWARE_TYPE_AGERE:
@@ -818,7 +818,7 @@ int __orinoco_hw_set_wap(struct orinoco_private *priv)
818 * which is needed for 802.1x implementations. */ 818 * which is needed for 802.1x implementations. */
819int __orinoco_hw_setup_wepkeys(struct orinoco_private *priv) 819int __orinoco_hw_setup_wepkeys(struct orinoco_private *priv)
820{ 820{
821 hermes_t *hw = &priv->hw; 821 struct hermes *hw = &priv->hw;
822 int err = 0; 822 int err = 0;
823 int i; 823 int i;
824 824
@@ -902,7 +902,7 @@ int __orinoco_hw_setup_wepkeys(struct orinoco_private *priv)
902 902
903int __orinoco_hw_setup_enc(struct orinoco_private *priv) 903int __orinoco_hw_setup_enc(struct orinoco_private *priv)
904{ 904{
905 hermes_t *hw = &priv->hw; 905 struct hermes *hw = &priv->hw;
906 int err = 0; 906 int err = 0;
907 int master_wep_flag; 907 int master_wep_flag;
908 int auth_flag; 908 int auth_flag;
@@ -999,7 +999,7 @@ int __orinoco_hw_set_tkip_key(struct orinoco_private *priv, int key_idx,
999 u8 rx_mic[MIC_KEYLEN]; 999 u8 rx_mic[MIC_KEYLEN];
1000 u8 tsc[ORINOCO_SEQ_LEN]; 1000 u8 tsc[ORINOCO_SEQ_LEN];
1001 } __packed buf; 1001 } __packed buf;
1002 hermes_t *hw = &priv->hw; 1002 struct hermes *hw = &priv->hw;
1003 int ret; 1003 int ret;
1004 int err; 1004 int err;
1005 int k; 1005 int k;
@@ -1052,7 +1052,7 @@ int __orinoco_hw_set_tkip_key(struct orinoco_private *priv, int key_idx,
1052 1052
1053int orinoco_clear_tkip_key(struct orinoco_private *priv, int key_idx) 1053int orinoco_clear_tkip_key(struct orinoco_private *priv, int key_idx)
1054{ 1054{
1055 hermes_t *hw = &priv->hw; 1055 struct hermes *hw = &priv->hw;
1056 int err; 1056 int err;
1057 1057
1058 err = hermes_write_wordrec(hw, USER_BAP, 1058 err = hermes_write_wordrec(hw, USER_BAP,
@@ -1068,7 +1068,7 @@ int __orinoco_hw_set_multicast_list(struct orinoco_private *priv,
1068 struct net_device *dev, 1068 struct net_device *dev,
1069 int mc_count, int promisc) 1069 int mc_count, int promisc)
1070{ 1070{
1071 hermes_t *hw = &priv->hw; 1071 struct hermes *hw = &priv->hw;
1072 int err = 0; 1072 int err = 0;
1073 1073
1074 if (promisc != priv->promiscuous) { 1074 if (promisc != priv->promiscuous) {
@@ -1111,9 +1111,9 @@ int __orinoco_hw_set_multicast_list(struct orinoco_private *priv,
1111 1111
1112/* Return : < 0 -> error code ; >= 0 -> length */ 1112/* Return : < 0 -> error code ; >= 0 -> length */
1113int orinoco_hw_get_essid(struct orinoco_private *priv, int *active, 1113int orinoco_hw_get_essid(struct orinoco_private *priv, int *active,
1114 char buf[IW_ESSID_MAX_SIZE+1]) 1114 char buf[IW_ESSID_MAX_SIZE + 1])
1115{ 1115{
1116 hermes_t *hw = &priv->hw; 1116 struct hermes *hw = &priv->hw;
1117 int err = 0; 1117 int err = 0;
1118 struct hermes_idstring essidbuf; 1118 struct hermes_idstring essidbuf;
1119 char *p = (char *)(&essidbuf.val); 1119 char *p = (char *)(&essidbuf.val);
@@ -1166,7 +1166,7 @@ int orinoco_hw_get_essid(struct orinoco_private *priv, int *active,
1166 1166
1167int orinoco_hw_get_freq(struct orinoco_private *priv) 1167int orinoco_hw_get_freq(struct orinoco_private *priv)
1168{ 1168{
1169 hermes_t *hw = &priv->hw; 1169 struct hermes *hw = &priv->hw;
1170 int err = 0; 1170 int err = 0;
1171 u16 channel; 1171 u16 channel;
1172 int freq = 0; 1172 int freq = 0;
@@ -1206,7 +1206,7 @@ int orinoco_hw_get_freq(struct orinoco_private *priv)
1206int orinoco_hw_get_bitratelist(struct orinoco_private *priv, 1206int orinoco_hw_get_bitratelist(struct orinoco_private *priv,
1207 int *numrates, s32 *rates, int max) 1207 int *numrates, s32 *rates, int max)
1208{ 1208{
1209 hermes_t *hw = &priv->hw; 1209 struct hermes *hw = &priv->hw;
1210 struct hermes_idstring list; 1210 struct hermes_idstring list;
1211 unsigned char *p = (unsigned char *)&list.val; 1211 unsigned char *p = (unsigned char *)&list.val;
1212 int err = 0; 1212 int err = 0;
@@ -1238,7 +1238,7 @@ int orinoco_hw_trigger_scan(struct orinoco_private *priv,
1238 const struct cfg80211_ssid *ssid) 1238 const struct cfg80211_ssid *ssid)
1239{ 1239{
1240 struct net_device *dev = priv->ndev; 1240 struct net_device *dev = priv->ndev;
1241 hermes_t *hw = &priv->hw; 1241 struct hermes *hw = &priv->hw;
1242 unsigned long flags; 1242 unsigned long flags;
1243 int err = 0; 1243 int err = 0;
1244 1244
@@ -1323,7 +1323,7 @@ int orinoco_hw_trigger_scan(struct orinoco_private *priv,
1323int orinoco_hw_disassociate(struct orinoco_private *priv, 1323int orinoco_hw_disassociate(struct orinoco_private *priv,
1324 u8 *addr, u16 reason_code) 1324 u8 *addr, u16 reason_code)
1325{ 1325{
1326 hermes_t *hw = &priv->hw; 1326 struct hermes *hw = &priv->hw;
1327 int err; 1327 int err;
1328 1328
1329 struct { 1329 struct {
@@ -1346,7 +1346,7 @@ int orinoco_hw_disassociate(struct orinoco_private *priv,
1346int orinoco_hw_get_current_bssid(struct orinoco_private *priv, 1346int orinoco_hw_get_current_bssid(struct orinoco_private *priv,
1347 u8 *addr) 1347 u8 *addr)
1348{ 1348{
1349 hermes_t *hw = &priv->hw; 1349 struct hermes *hw = &priv->hw;
1350 int err; 1350 int err;
1351 1351
1352 err = hw->ops->read_ltv(hw, USER_BAP, HERMES_RID_CURRENTBSSID, 1352 err = hw->ops->read_ltv(hw, USER_BAP, HERMES_RID_CURRENTBSSID,
diff --git a/drivers/net/wireless/orinoco/hw.h b/drivers/net/wireless/orinoco/hw.h
index 97af71e79950..8f6831f4e328 100644
--- a/drivers/net/wireless/orinoco/hw.h
+++ b/drivers/net/wireless/orinoco/hw.h
@@ -45,7 +45,7 @@ int __orinoco_hw_set_multicast_list(struct orinoco_private *priv,
45 struct net_device *dev, 45 struct net_device *dev,
46 int mc_count, int promisc); 46 int mc_count, int promisc);
47int orinoco_hw_get_essid(struct orinoco_private *priv, int *active, 47int orinoco_hw_get_essid(struct orinoco_private *priv, int *active,
48 char buf[IW_ESSID_MAX_SIZE+1]); 48 char buf[IW_ESSID_MAX_SIZE + 1]);
49int orinoco_hw_get_freq(struct orinoco_private *priv); 49int orinoco_hw_get_freq(struct orinoco_private *priv);
50int orinoco_hw_get_bitratelist(struct orinoco_private *priv, 50int orinoco_hw_get_bitratelist(struct orinoco_private *priv,
51 int *numrates, s32 *rates, int max); 51 int *numrates, s32 *rates, int max);
diff --git a/drivers/net/wireless/orinoco/main.c b/drivers/net/wireless/orinoco/main.c
index 62c6b2b37dbe..ef7efe839bb8 100644
--- a/drivers/net/wireless/orinoco/main.c
+++ b/drivers/net/wireless/orinoco/main.c
@@ -4,7 +4,7 @@
4 * adaptors, with Lucent/Agere, Intersil or Symbol firmware. 4 * adaptors, with Lucent/Agere, Intersil or Symbol firmware.
5 * 5 *
6 * Current maintainers (as of 29 September 2003) are: 6 * Current maintainers (as of 29 September 2003) are:
7 * Pavel Roskin <proski AT gnu.org> 7 * Pavel Roskin <proski AT gnu.org>
8 * and David Gibson <hermes AT gibson.dropbear.id.au> 8 * and David Gibson <hermes AT gibson.dropbear.id.au>
9 * 9 *
10 * (C) Copyright David Gibson, IBM Corporation 2001-2003. 10 * (C) Copyright David Gibson, IBM Corporation 2001-2003.
@@ -146,10 +146,10 @@ static const u8 encaps_hdr[] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
146#define ORINOCO_MAX_MTU (IEEE80211_MAX_DATA_LEN - ENCAPS_OVERHEAD) 146#define ORINOCO_MAX_MTU (IEEE80211_MAX_DATA_LEN - ENCAPS_OVERHEAD)
147 147
148#define MAX_IRQLOOPS_PER_IRQ 10 148#define MAX_IRQLOOPS_PER_IRQ 10
149#define MAX_IRQLOOPS_PER_JIFFY (20000/HZ) /* Based on a guestimate of 149#define MAX_IRQLOOPS_PER_JIFFY (20000 / HZ) /* Based on a guestimate of
150 * how many events the 150 * how many events the
151 * device could 151 * device could
152 * legitimately generate */ 152 * legitimately generate */
153 153
154#define DUMMY_FID 0xFFFF 154#define DUMMY_FID 0xFFFF
155 155
@@ -157,7 +157,7 @@ static const u8 encaps_hdr[] = {0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00};
157 HERMES_MAX_MULTICAST : 0)*/ 157 HERMES_MAX_MULTICAST : 0)*/
158#define MAX_MULTICAST(priv) (HERMES_MAX_MULTICAST) 158#define MAX_MULTICAST(priv) (HERMES_MAX_MULTICAST)
159 159
160#define ORINOCO_INTEN (HERMES_EV_RX | HERMES_EV_ALLOC \ 160#define ORINOCO_INTEN (HERMES_EV_RX | HERMES_EV_ALLOC \
161 | HERMES_EV_TX | HERMES_EV_TXEXC \ 161 | HERMES_EV_TX | HERMES_EV_TXEXC \
162 | HERMES_EV_WTERR | HERMES_EV_INFO \ 162 | HERMES_EV_WTERR | HERMES_EV_INFO \
163 | HERMES_EV_INFDROP) 163 | HERMES_EV_INFDROP)
@@ -437,12 +437,12 @@ static netdev_tx_t orinoco_xmit(struct sk_buff *skb, struct net_device *dev)
437{ 437{
438 struct orinoco_private *priv = ndev_priv(dev); 438 struct orinoco_private *priv = ndev_priv(dev);
439 struct net_device_stats *stats = &priv->stats; 439 struct net_device_stats *stats = &priv->stats;
440 hermes_t *hw = &priv->hw; 440 struct hermes *hw = &priv->hw;
441 int err = 0; 441 int err = 0;
442 u16 txfid = priv->txfid; 442 u16 txfid = priv->txfid;
443 int tx_control; 443 int tx_control;
444 unsigned long flags; 444 unsigned long flags;
445 u8 mic_buf[MICHAEL_MIC_LEN+1]; 445 u8 mic_buf[MICHAEL_MIC_LEN + 1];
446 446
447 if (!netif_running(dev)) { 447 if (!netif_running(dev)) {
448 printk(KERN_ERR "%s: Tx on stopped device!\n", 448 printk(KERN_ERR "%s: Tx on stopped device!\n",
@@ -579,7 +579,7 @@ static netdev_tx_t orinoco_xmit(struct sk_buff *skb, struct net_device *dev)
579 return NETDEV_TX_BUSY; 579 return NETDEV_TX_BUSY;
580} 580}
581 581
582static void __orinoco_ev_alloc(struct net_device *dev, hermes_t *hw) 582static void __orinoco_ev_alloc(struct net_device *dev, struct hermes *hw)
583{ 583{
584 struct orinoco_private *priv = ndev_priv(dev); 584 struct orinoco_private *priv = ndev_priv(dev);
585 u16 fid = hermes_read_regn(hw, ALLOCFID); 585 u16 fid = hermes_read_regn(hw, ALLOCFID);
@@ -594,7 +594,7 @@ static void __orinoco_ev_alloc(struct net_device *dev, hermes_t *hw)
594 hermes_write_regn(hw, ALLOCFID, DUMMY_FID); 594 hermes_write_regn(hw, ALLOCFID, DUMMY_FID);
595} 595}
596 596
597static void __orinoco_ev_tx(struct net_device *dev, hermes_t *hw) 597static void __orinoco_ev_tx(struct net_device *dev, struct hermes *hw)
598{ 598{
599 struct orinoco_private *priv = ndev_priv(dev); 599 struct orinoco_private *priv = ndev_priv(dev);
600 struct net_device_stats *stats = &priv->stats; 600 struct net_device_stats *stats = &priv->stats;
@@ -606,7 +606,7 @@ static void __orinoco_ev_tx(struct net_device *dev, hermes_t *hw)
606 hermes_write_regn(hw, TXCOMPLFID, DUMMY_FID); 606 hermes_write_regn(hw, TXCOMPLFID, DUMMY_FID);
607} 607}
608 608
609static void __orinoco_ev_txexc(struct net_device *dev, hermes_t *hw) 609static void __orinoco_ev_txexc(struct net_device *dev, struct hermes *hw)
610{ 610{
611 struct orinoco_private *priv = ndev_priv(dev); 611 struct orinoco_private *priv = ndev_priv(dev);
612 struct net_device_stats *stats = &priv->stats; 612 struct net_device_stats *stats = &priv->stats;
@@ -753,7 +753,7 @@ static void orinoco_rx_monitor(struct net_device *dev, u16 rxfid,
753 struct sk_buff *skb; 753 struct sk_buff *skb;
754 struct orinoco_private *priv = ndev_priv(dev); 754 struct orinoco_private *priv = ndev_priv(dev);
755 struct net_device_stats *stats = &priv->stats; 755 struct net_device_stats *stats = &priv->stats;
756 hermes_t *hw = &priv->hw; 756 struct hermes *hw = &priv->hw;
757 757
758 len = le16_to_cpu(desc->data_len); 758 len = le16_to_cpu(desc->data_len);
759 759
@@ -840,7 +840,7 @@ static void orinoco_rx_monitor(struct net_device *dev, u16 rxfid,
840 stats->rx_dropped++; 840 stats->rx_dropped++;
841} 841}
842 842
843void __orinoco_ev_rx(struct net_device *dev, hermes_t *hw) 843void __orinoco_ev_rx(struct net_device *dev, struct hermes *hw)
844{ 844{
845 struct orinoco_private *priv = ndev_priv(dev); 845 struct orinoco_private *priv = ndev_priv(dev);
846 struct net_device_stats *stats = &priv->stats; 846 struct net_device_stats *stats = &priv->stats;
@@ -918,7 +918,7 @@ void __orinoco_ev_rx(struct net_device *dev, hermes_t *hw)
918 32bit boundary, plus 1 byte so we can read in odd length 918 32bit boundary, plus 1 byte so we can read in odd length
919 packets from the card, which has an IO granularity of 16 919 packets from the card, which has an IO granularity of 16
920 bits */ 920 bits */
921 skb = dev_alloc_skb(length+ETH_HLEN+2+1); 921 skb = dev_alloc_skb(length + ETH_HLEN + 2 + 1);
922 if (!skb) { 922 if (!skb) {
923 printk(KERN_WARNING "%s: Can't allocate skb for Rx\n", 923 printk(KERN_WARNING "%s: Can't allocate skb for Rx\n",
924 dev->name); 924 dev->name);
@@ -1402,7 +1402,7 @@ static void orinoco_process_scan_results(struct work_struct *work)
1402 spin_unlock_irqrestore(&priv->scan_lock, flags); 1402 spin_unlock_irqrestore(&priv->scan_lock, flags);
1403} 1403}
1404 1404
1405void __orinoco_ev_info(struct net_device *dev, hermes_t *hw) 1405void __orinoco_ev_info(struct net_device *dev, struct hermes *hw)
1406{ 1406{
1407 struct orinoco_private *priv = ndev_priv(dev); 1407 struct orinoco_private *priv = ndev_priv(dev);
1408 u16 infofid; 1408 u16 infofid;
@@ -1620,7 +1620,7 @@ void __orinoco_ev_info(struct net_device *dev, hermes_t *hw)
1620} 1620}
1621EXPORT_SYMBOL(__orinoco_ev_info); 1621EXPORT_SYMBOL(__orinoco_ev_info);
1622 1622
1623static void __orinoco_ev_infdrop(struct net_device *dev, hermes_t *hw) 1623static void __orinoco_ev_infdrop(struct net_device *dev, struct hermes *hw)
1624{ 1624{
1625 if (net_ratelimit()) 1625 if (net_ratelimit())
1626 printk(KERN_DEBUG "%s: Information frame lost.\n", dev->name); 1626 printk(KERN_DEBUG "%s: Information frame lost.\n", dev->name);
@@ -1831,7 +1831,7 @@ static int __orinoco_commit(struct orinoco_private *priv)
1831int orinoco_commit(struct orinoco_private *priv) 1831int orinoco_commit(struct orinoco_private *priv)
1832{ 1832{
1833 struct net_device *dev = priv->ndev; 1833 struct net_device *dev = priv->ndev;
1834 hermes_t *hw = &priv->hw; 1834 struct hermes *hw = &priv->hw;
1835 int err; 1835 int err;
1836 1836
1837 if (priv->broken_disableport) { 1837 if (priv->broken_disableport) {
@@ -1874,12 +1874,12 @@ int orinoco_commit(struct orinoco_private *priv)
1874/* Interrupt handler */ 1874/* Interrupt handler */
1875/********************************************************************/ 1875/********************************************************************/
1876 1876
1877static void __orinoco_ev_tick(struct net_device *dev, hermes_t *hw) 1877static void __orinoco_ev_tick(struct net_device *dev, struct hermes *hw)
1878{ 1878{
1879 printk(KERN_DEBUG "%s: TICK\n", dev->name); 1879 printk(KERN_DEBUG "%s: TICK\n", dev->name);
1880} 1880}
1881 1881
1882static void __orinoco_ev_wterr(struct net_device *dev, hermes_t *hw) 1882static void __orinoco_ev_wterr(struct net_device *dev, struct hermes *hw)
1883{ 1883{
1884 /* This seems to happen a fair bit under load, but ignoring it 1884 /* This seems to happen a fair bit under load, but ignoring it
1885 seems to work fine...*/ 1885 seems to work fine...*/
@@ -1891,7 +1891,7 @@ irqreturn_t orinoco_interrupt(int irq, void *dev_id)
1891{ 1891{
1892 struct orinoco_private *priv = dev_id; 1892 struct orinoco_private *priv = dev_id;
1893 struct net_device *dev = priv->ndev; 1893 struct net_device *dev = priv->ndev;
1894 hermes_t *hw = &priv->hw; 1894 struct hermes *hw = &priv->hw;
1895 int count = MAX_IRQLOOPS_PER_IRQ; 1895 int count = MAX_IRQLOOPS_PER_IRQ;
1896 u16 evstat, events; 1896 u16 evstat, events;
1897 /* These are used to detect a runaway interrupt situation. 1897 /* These are used to detect a runaway interrupt situation.
@@ -1958,7 +1958,7 @@ irqreturn_t orinoco_interrupt(int irq, void *dev_id)
1958 1958
1959 evstat = hermes_read_regn(hw, EVSTAT); 1959 evstat = hermes_read_regn(hw, EVSTAT);
1960 events = evstat & hw->inten; 1960 events = evstat & hw->inten;
1961 }; 1961 }
1962 1962
1963 orinoco_unlock(priv, &flags); 1963 orinoco_unlock(priv, &flags);
1964 return IRQ_HANDLED; 1964 return IRQ_HANDLED;
@@ -2017,8 +2017,8 @@ static void orinoco_unregister_pm_notifier(struct orinoco_private *priv)
2017 unregister_pm_notifier(&priv->pm_notifier); 2017 unregister_pm_notifier(&priv->pm_notifier);
2018} 2018}
2019#else /* !PM_SLEEP || HERMES_CACHE_FW_ON_INIT */ 2019#else /* !PM_SLEEP || HERMES_CACHE_FW_ON_INIT */
2020#define orinoco_register_pm_notifier(priv) do { } while(0) 2020#define orinoco_register_pm_notifier(priv) do { } while (0)
2021#define orinoco_unregister_pm_notifier(priv) do { } while(0) 2021#define orinoco_unregister_pm_notifier(priv) do { } while (0)
2022#endif 2022#endif
2023 2023
2024/********************************************************************/ 2024/********************************************************************/
@@ -2029,7 +2029,7 @@ int orinoco_init(struct orinoco_private *priv)
2029{ 2029{
2030 struct device *dev = priv->dev; 2030 struct device *dev = priv->dev;
2031 struct wiphy *wiphy = priv_to_wiphy(priv); 2031 struct wiphy *wiphy = priv_to_wiphy(priv);
2032 hermes_t *hw = &priv->hw; 2032 struct hermes *hw = &priv->hw;
2033 int err = 0; 2033 int err = 0;
2034 2034
2035 /* No need to lock, the hw_unavailable flag is already set in 2035 /* No need to lock, the hw_unavailable flag is already set in
diff --git a/drivers/net/wireless/orinoco/mic.c b/drivers/net/wireless/orinoco/mic.c
index c03e7f54d1b8..fce4a843e656 100644
--- a/drivers/net/wireless/orinoco/mic.c
+++ b/drivers/net/wireless/orinoco/mic.c
@@ -59,10 +59,10 @@ int orinoco_mic(struct crypto_hash *tfm_michael, u8 *key,
59 /* Copy header into buffer. We need the padding on the end zeroed */ 59 /* Copy header into buffer. We need the padding on the end zeroed */
60 memcpy(&hdr[0], da, ETH_ALEN); 60 memcpy(&hdr[0], da, ETH_ALEN);
61 memcpy(&hdr[ETH_ALEN], sa, ETH_ALEN); 61 memcpy(&hdr[ETH_ALEN], sa, ETH_ALEN);
62 hdr[ETH_ALEN*2] = priority; 62 hdr[ETH_ALEN * 2] = priority;
63 hdr[ETH_ALEN*2+1] = 0; 63 hdr[ETH_ALEN * 2 + 1] = 0;
64 hdr[ETH_ALEN*2+2] = 0; 64 hdr[ETH_ALEN * 2 + 2] = 0;
65 hdr[ETH_ALEN*2+3] = 0; 65 hdr[ETH_ALEN * 2 + 3] = 0;
66 66
67 /* Use scatter gather to MIC header and data in one go */ 67 /* Use scatter gather to MIC header and data in one go */
68 sg_init_table(sg, 2); 68 sg_init_table(sg, 2);
diff --git a/drivers/net/wireless/orinoco/orinoco.h b/drivers/net/wireless/orinoco/orinoco.h
index 255710ef082a..3bb936b9558c 100644
--- a/drivers/net/wireless/orinoco/orinoco.h
+++ b/drivers/net/wireless/orinoco/orinoco.h
@@ -49,11 +49,11 @@ enum orinoco_alg {
49 ORINOCO_ALG_TKIP 49 ORINOCO_ALG_TKIP
50}; 50};
51 51
52typedef enum { 52enum fwtype {
53 FIRMWARE_TYPE_AGERE, 53 FIRMWARE_TYPE_AGERE,
54 FIRMWARE_TYPE_INTERSIL, 54 FIRMWARE_TYPE_INTERSIL,
55 FIRMWARE_TYPE_SYMBOL 55 FIRMWARE_TYPE_SYMBOL
56} fwtype_t; 56};
57 57
58struct firmware; 58struct firmware;
59 59
@@ -88,11 +88,11 @@ struct orinoco_private {
88 struct iw_statistics wstats; 88 struct iw_statistics wstats;
89 89
90 /* Hardware control variables */ 90 /* Hardware control variables */
91 hermes_t hw; 91 struct hermes hw;
92 u16 txfid; 92 u16 txfid;
93 93
94 /* Capabilities of the hardware/firmware */ 94 /* Capabilities of the hardware/firmware */
95 fwtype_t firmware_type; 95 enum fwtype firmware_type;
96 int ibss_port; 96 int ibss_port;
97 int nicbuf_size; 97 int nicbuf_size;
98 u16 channel_mask; 98 u16 channel_mask;
@@ -122,8 +122,8 @@ struct orinoco_private {
122 struct key_params keys[ORINOCO_MAX_KEYS]; 122 struct key_params keys[ORINOCO_MAX_KEYS];
123 123
124 int bitratemode; 124 int bitratemode;
125 char nick[IW_ESSID_MAX_SIZE+1]; 125 char nick[IW_ESSID_MAX_SIZE + 1];
126 char desired_essid[IW_ESSID_MAX_SIZE+1]; 126 char desired_essid[IW_ESSID_MAX_SIZE + 1];
127 char desired_bssid[ETH_ALEN]; 127 char desired_bssid[ETH_ALEN];
128 int bssid_fixed; 128 int bssid_fixed;
129 u16 frag_thresh, mwo_robust; 129 u16 frag_thresh, mwo_robust;
@@ -197,8 +197,8 @@ extern int orinoco_up(struct orinoco_private *priv);
197extern void orinoco_down(struct orinoco_private *priv); 197extern void orinoco_down(struct orinoco_private *priv);
198extern irqreturn_t orinoco_interrupt(int irq, void *dev_id); 198extern irqreturn_t orinoco_interrupt(int irq, void *dev_id);
199 199
200extern void __orinoco_ev_info(struct net_device *dev, hermes_t *hw); 200extern void __orinoco_ev_info(struct net_device *dev, struct hermes *hw);
201extern void __orinoco_ev_rx(struct net_device *dev, hermes_t *hw); 201extern void __orinoco_ev_rx(struct net_device *dev, struct hermes *hw);
202 202
203int orinoco_process_xmit_skb(struct sk_buff *skb, 203int orinoco_process_xmit_skb(struct sk_buff *skb,
204 struct net_device *dev, 204 struct net_device *dev,
diff --git a/drivers/net/wireless/orinoco/orinoco_cs.c b/drivers/net/wireless/orinoco/orinoco_cs.c
index 88e3c0ebcaad..3f7fc4a0b43d 100644
--- a/drivers/net/wireless/orinoco/orinoco_cs.c
+++ b/drivers/net/wireless/orinoco/orinoco_cs.c
@@ -65,7 +65,7 @@ static void orinoco_cs_release(struct pcmcia_device *link);
65static void orinoco_cs_detach(struct pcmcia_device *p_dev); 65static void orinoco_cs_detach(struct pcmcia_device *p_dev);
66 66
67/********************************************************************/ 67/********************************************************************/
68/* Device methods */ 68/* Device methods */
69/********************************************************************/ 69/********************************************************************/
70 70
71static int 71static int
@@ -89,7 +89,7 @@ orinoco_cs_hard_reset(struct orinoco_private *priv)
89} 89}
90 90
91/********************************************************************/ 91/********************************************************************/
92/* PCMCIA stuff */ 92/* PCMCIA stuff */
93/********************************************************************/ 93/********************************************************************/
94 94
95static int 95static int
@@ -134,7 +134,7 @@ static int
134orinoco_cs_config(struct pcmcia_device *link) 134orinoco_cs_config(struct pcmcia_device *link)
135{ 135{
136 struct orinoco_private *priv = link->priv; 136 struct orinoco_private *priv = link->priv;
137 hermes_t *hw = &priv->hw; 137 struct hermes *hw = &priv->hw;
138 int ret; 138 int ret;
139 void __iomem *mem; 139 void __iomem *mem;
140 140
diff --git a/drivers/net/wireless/orinoco/orinoco_nortel.c b/drivers/net/wireless/orinoco/orinoco_nortel.c
index bc3ea0b67a4f..326396b313a6 100644
--- a/drivers/net/wireless/orinoco/orinoco_nortel.c
+++ b/drivers/net/wireless/orinoco/orinoco_nortel.c
@@ -296,8 +296,7 @@ static struct pci_driver orinoco_nortel_driver = {
296static char version[] __initdata = DRIVER_NAME " " DRIVER_VERSION 296static char version[] __initdata = DRIVER_NAME " " DRIVER_VERSION
297 " (Tobias Hoffmann & Christoph Jungegger <disdos@traum404.de>)"; 297 " (Tobias Hoffmann & Christoph Jungegger <disdos@traum404.de>)";
298MODULE_AUTHOR("Christoph Jungegger <disdos@traum404.de>"); 298MODULE_AUTHOR("Christoph Jungegger <disdos@traum404.de>");
299MODULE_DESCRIPTION 299MODULE_DESCRIPTION("Driver for wireless LAN cards using the Nortel PCI bridge");
300 ("Driver for wireless LAN cards using the Nortel PCI bridge");
301MODULE_LICENSE("Dual MPL/GPL"); 300MODULE_LICENSE("Dual MPL/GPL");
302 301
303static int __init orinoco_nortel_init(void) 302static int __init orinoco_nortel_init(void)
diff --git a/drivers/net/wireless/orinoco/orinoco_pci.c b/drivers/net/wireless/orinoco/orinoco_pci.c
index 468197f86673..6058c66b844e 100644
--- a/drivers/net/wireless/orinoco/orinoco_pci.c
+++ b/drivers/net/wireless/orinoco/orinoco_pci.c
@@ -6,7 +6,7 @@
6 * hermes registers, as well as the COR register. 6 * hermes registers, as well as the COR register.
7 * 7 *
8 * Current maintainers are: 8 * Current maintainers are:
9 * Pavel Roskin <proski AT gnu.org> 9 * Pavel Roskin <proski AT gnu.org>
10 * and David Gibson <hermes AT gibson.dropbear.id.au> 10 * and David Gibson <hermes AT gibson.dropbear.id.au>
11 * 11 *
12 * Some of this code is borrowed from orinoco_plx.c 12 * Some of this code is borrowed from orinoco_plx.c
@@ -81,7 +81,7 @@
81 */ 81 */
82static int orinoco_pci_cor_reset(struct orinoco_private *priv) 82static int orinoco_pci_cor_reset(struct orinoco_private *priv)
83{ 83{
84 hermes_t *hw = &priv->hw; 84 struct hermes *hw = &priv->hw;
85 unsigned long timeout; 85 unsigned long timeout;
86 u16 reg; 86 u16 reg;
87 87
diff --git a/drivers/net/wireless/orinoco/orinoco_plx.c b/drivers/net/wireless/orinoco/orinoco_plx.c
index 9358f4d2307b..2bac8248a991 100644
--- a/drivers/net/wireless/orinoco/orinoco_plx.c
+++ b/drivers/net/wireless/orinoco/orinoco_plx.c
@@ -4,7 +4,7 @@
4 * but are connected to the PCI bus by a PLX9052. 4 * but are connected to the PCI bus by a PLX9052.
5 * 5 *
6 * Current maintainers are: 6 * Current maintainers are:
7 * Pavel Roskin <proski AT gnu.org> 7 * Pavel Roskin <proski AT gnu.org>
8 * and David Gibson <hermes AT gibson.dropbear.id.au> 8 * and David Gibson <hermes AT gibson.dropbear.id.au>
9 * 9 *
10 * (C) Copyright David Gibson, IBM Corp. 2001-2003. 10 * (C) Copyright David Gibson, IBM Corp. 2001-2003.
@@ -102,14 +102,14 @@
102#define PLX_RESET_TIME (500) /* milliseconds */ 102#define PLX_RESET_TIME (500) /* milliseconds */
103 103
104#define PLX_INTCSR 0x4c /* Interrupt Control & Status Register */ 104#define PLX_INTCSR 0x4c /* Interrupt Control & Status Register */
105#define PLX_INTCSR_INTEN (1<<6) /* Interrupt Enable bit */ 105#define PLX_INTCSR_INTEN (1 << 6) /* Interrupt Enable bit */
106 106
107/* 107/*
108 * Do a soft reset of the card using the Configuration Option Register 108 * Do a soft reset of the card using the Configuration Option Register
109 */ 109 */
110static int orinoco_plx_cor_reset(struct orinoco_private *priv) 110static int orinoco_plx_cor_reset(struct orinoco_private *priv)
111{ 111{
112 hermes_t *hw = &priv->hw; 112 struct hermes *hw = &priv->hw;
113 struct orinoco_pci_card *card = priv->card; 113 struct orinoco_pci_card *card = priv->card;
114 unsigned long timeout; 114 unsigned long timeout;
115 u16 reg; 115 u16 reg;
diff --git a/drivers/net/wireless/orinoco/orinoco_tmd.c b/drivers/net/wireless/orinoco/orinoco_tmd.c
index 784605f0af15..93159d68ec93 100644
--- a/drivers/net/wireless/orinoco/orinoco_tmd.c
+++ b/drivers/net/wireless/orinoco/orinoco_tmd.c
@@ -59,7 +59,7 @@
59 */ 59 */
60static int orinoco_tmd_cor_reset(struct orinoco_private *priv) 60static int orinoco_tmd_cor_reset(struct orinoco_private *priv)
61{ 61{
62 hermes_t *hw = &priv->hw; 62 struct hermes *hw = &priv->hw;
63 struct orinoco_pci_card *card = priv->card; 63 struct orinoco_pci_card *card = priv->card;
64 unsigned long timeout; 64 unsigned long timeout;
65 u16 reg; 65 u16 reg;
diff --git a/drivers/net/wireless/orinoco/orinoco_usb.c b/drivers/net/wireless/orinoco/orinoco_usb.c
index b9aedf18a046..811e87f8a349 100644
--- a/drivers/net/wireless/orinoco/orinoco_usb.c
+++ b/drivers/net/wireless/orinoco/orinoco_usb.c
@@ -199,7 +199,7 @@ MODULE_FIRMWARE("orinoco_ezusb_fw");
199#define EZUSB_FRAME_DATA 1 199#define EZUSB_FRAME_DATA 1
200#define EZUSB_FRAME_CONTROL 2 200#define EZUSB_FRAME_CONTROL 2
201 201
202#define DEF_TIMEOUT (3*HZ) 202#define DEF_TIMEOUT (3 * HZ)
203 203
204#define BULK_BUF_SIZE 2048 204#define BULK_BUF_SIZE 2048
205 205
@@ -959,7 +959,7 @@ static int ezusb_access_ltv(struct ezusb_priv *upriv,
959 return retval; 959 return retval;
960} 960}
961 961
962static int ezusb_write_ltv(hermes_t *hw, int bap, u16 rid, 962static int ezusb_write_ltv(struct hermes *hw, int bap, u16 rid,
963 u16 length, const void *data) 963 u16 length, const void *data)
964{ 964{
965 struct ezusb_priv *upriv = hw->priv; 965 struct ezusb_priv *upriv = hw->priv;
@@ -989,7 +989,7 @@ static int ezusb_write_ltv(hermes_t *hw, int bap, u16 rid,
989 NULL, 0, NULL); 989 NULL, 0, NULL);
990} 990}
991 991
992static int ezusb_read_ltv(hermes_t *hw, int bap, u16 rid, 992static int ezusb_read_ltv(struct hermes *hw, int bap, u16 rid,
993 unsigned bufsize, u16 *length, void *buf) 993 unsigned bufsize, u16 *length, void *buf)
994{ 994{
995 struct ezusb_priv *upriv = hw->priv; 995 struct ezusb_priv *upriv = hw->priv;
@@ -1006,7 +1006,7 @@ static int ezusb_read_ltv(hermes_t *hw, int bap, u16 rid,
1006 buf, bufsize, length); 1006 buf, bufsize, length);
1007} 1007}
1008 1008
1009static int ezusb_doicmd_wait(hermes_t *hw, u16 cmd, u16 parm0, u16 parm1, 1009static int ezusb_doicmd_wait(struct hermes *hw, u16 cmd, u16 parm0, u16 parm1,
1010 u16 parm2, struct hermes_response *resp) 1010 u16 parm2, struct hermes_response *resp)
1011{ 1011{
1012 struct ezusb_priv *upriv = hw->priv; 1012 struct ezusb_priv *upriv = hw->priv;
@@ -1028,7 +1028,7 @@ static int ezusb_doicmd_wait(hermes_t *hw, u16 cmd, u16 parm0, u16 parm1,
1028 EZUSB_FRAME_CONTROL, NULL, 0, NULL); 1028 EZUSB_FRAME_CONTROL, NULL, 0, NULL);
1029} 1029}
1030 1030
1031static int ezusb_docmd_wait(hermes_t *hw, u16 cmd, u16 parm0, 1031static int ezusb_docmd_wait(struct hermes *hw, u16 cmd, u16 parm0,
1032 struct hermes_response *resp) 1032 struct hermes_response *resp)
1033{ 1033{
1034 struct ezusb_priv *upriv = hw->priv; 1034 struct ezusb_priv *upriv = hw->priv;
@@ -1196,7 +1196,7 @@ static netdev_tx_t ezusb_xmit(struct sk_buff *skb, struct net_device *dev)
1196 struct orinoco_private *priv = ndev_priv(dev); 1196 struct orinoco_private *priv = ndev_priv(dev);
1197 struct net_device_stats *stats = &priv->stats; 1197 struct net_device_stats *stats = &priv->stats;
1198 struct ezusb_priv *upriv = priv->card; 1198 struct ezusb_priv *upriv = priv->card;
1199 u8 mic[MICHAEL_MIC_LEN+1]; 1199 u8 mic[MICHAEL_MIC_LEN + 1];
1200 int err = 0; 1200 int err = 0;
1201 int tx_control; 1201 int tx_control;
1202 unsigned long flags; 1202 unsigned long flags;
@@ -1356,7 +1356,7 @@ static int ezusb_hard_reset(struct orinoco_private *priv)
1356} 1356}
1357 1357
1358 1358
1359static int ezusb_init(hermes_t *hw) 1359static int ezusb_init(struct hermes *hw)
1360{ 1360{
1361 struct ezusb_priv *upriv = hw->priv; 1361 struct ezusb_priv *upriv = hw->priv;
1362 int retval; 1362 int retval;
@@ -1438,7 +1438,7 @@ static void ezusb_bulk_in_callback(struct urb *urb)
1438 } else if (upriv->dev) { 1438 } else if (upriv->dev) {
1439 struct net_device *dev = upriv->dev; 1439 struct net_device *dev = upriv->dev;
1440 struct orinoco_private *priv = ndev_priv(dev); 1440 struct orinoco_private *priv = ndev_priv(dev);
1441 hermes_t *hw = &priv->hw; 1441 struct hermes *hw = &priv->hw;
1442 1442
1443 if (hermes_rid == EZUSB_RID_RX) { 1443 if (hermes_rid == EZUSB_RID_RX) {
1444 __orinoco_ev_rx(dev, hw); 1444 __orinoco_ev_rx(dev, hw);
@@ -1575,7 +1575,7 @@ static int ezusb_probe(struct usb_interface *interface,
1575{ 1575{
1576 struct usb_device *udev = interface_to_usbdev(interface); 1576 struct usb_device *udev = interface_to_usbdev(interface);
1577 struct orinoco_private *priv; 1577 struct orinoco_private *priv;
1578 hermes_t *hw; 1578 struct hermes *hw;
1579 struct ezusb_priv *upriv = NULL; 1579 struct ezusb_priv *upriv = NULL;
1580 struct usb_interface_descriptor *iface_desc; 1580 struct usb_interface_descriptor *iface_desc;
1581 struct usb_endpoint_descriptor *ep; 1581 struct usb_endpoint_descriptor *ep;
@@ -1757,7 +1757,7 @@ static struct usb_driver orinoco_driver = {
1757/* Can't be declared "const" or the whole __initdata section will 1757/* Can't be declared "const" or the whole __initdata section will
1758 * become const */ 1758 * become const */
1759static char version[] __initdata = DRIVER_NAME " " DRIVER_VERSION 1759static char version[] __initdata = DRIVER_NAME " " DRIVER_VERSION
1760 " (Manuel Estrada Sainz)"; 1760 " (Manuel Estrada Sainz)";
1761 1761
1762static int __init ezusb_module_init(void) 1762static int __init ezusb_module_init(void)
1763{ 1763{
@@ -1787,6 +1787,5 @@ module_init(ezusb_module_init);
1787module_exit(ezusb_module_exit); 1787module_exit(ezusb_module_exit);
1788 1788
1789MODULE_AUTHOR("Manuel Estrada Sainz"); 1789MODULE_AUTHOR("Manuel Estrada Sainz");
1790MODULE_DESCRIPTION 1790MODULE_DESCRIPTION("Driver for Orinoco wireless LAN cards using EZUSB bridge");
1791 ("Driver for Orinoco wireless LAN cards using EZUSB bridge");
1792MODULE_LICENSE("Dual MPL/GPL"); 1791MODULE_LICENSE("Dual MPL/GPL");
diff --git a/drivers/net/wireless/orinoco/spectrum_cs.c b/drivers/net/wireless/orinoco/spectrum_cs.c
index 81f3673d31d4..6e28ee4e9c52 100644
--- a/drivers/net/wireless/orinoco/spectrum_cs.c
+++ b/drivers/net/wireless/orinoco/spectrum_cs.c
@@ -11,9 +11,9 @@
11 * 11 *
12 * Copyright (C) 2002-2005 Pavel Roskin <proski@gnu.org> 12 * Copyright (C) 2002-2005 Pavel Roskin <proski@gnu.org>
13 * Portions based on orinoco_cs.c: 13 * Portions based on orinoco_cs.c:
14 * Copyright (C) David Gibson, Linuxcare Australia 14 * Copyright (C) David Gibson, Linuxcare Australia
15 * Portions based on Spectrum24tDnld.c from original spectrum24 driver: 15 * Portions based on Spectrum24tDnld.c from original spectrum24 driver:
16 * Copyright (C) Symbol Technologies. 16 * Copyright (C) Symbol Technologies.
17 * 17 *
18 * See copyright notice in file main.c. 18 * See copyright notice in file main.c.
19 */ 19 */
@@ -125,7 +125,7 @@ failed:
125} 125}
126 126
127/********************************************************************/ 127/********************************************************************/
128/* Device methods */ 128/* Device methods */
129/********************************************************************/ 129/********************************************************************/
130 130
131static int 131static int
@@ -150,7 +150,7 @@ spectrum_cs_stop_firmware(struct orinoco_private *priv, int idle)
150} 150}
151 151
152/********************************************************************/ 152/********************************************************************/
153/* PCMCIA stuff */ 153/* PCMCIA stuff */
154/********************************************************************/ 154/********************************************************************/
155 155
156static int 156static int
@@ -197,7 +197,7 @@ static int
197spectrum_cs_config(struct pcmcia_device *link) 197spectrum_cs_config(struct pcmcia_device *link)
198{ 198{
199 struct orinoco_private *priv = link->priv; 199 struct orinoco_private *priv = link->priv;
200 hermes_t *hw = &priv->hw; 200 struct hermes *hw = &priv->hw;
201 int ret; 201 int ret;
202 void __iomem *mem; 202 void __iomem *mem;
203 203
diff --git a/drivers/net/wireless/orinoco/wext.c b/drivers/net/wireless/orinoco/wext.c
index e793679e2e19..bbb9beb206b1 100644
--- a/drivers/net/wireless/orinoco/wext.c
+++ b/drivers/net/wireless/orinoco/wext.c
@@ -87,7 +87,7 @@ nomem:
87static struct iw_statistics *orinoco_get_wireless_stats(struct net_device *dev) 87static struct iw_statistics *orinoco_get_wireless_stats(struct net_device *dev)
88{ 88{
89 struct orinoco_private *priv = ndev_priv(dev); 89 struct orinoco_private *priv = ndev_priv(dev);
90 hermes_t *hw = &priv->hw; 90 struct hermes *hw = &priv->hw;
91 struct iw_statistics *wstats = &priv->wstats; 91 struct iw_statistics *wstats = &priv->wstats;
92 int err; 92 int err;
93 unsigned long flags; 93 unsigned long flags;
@@ -448,7 +448,7 @@ static int orinoco_ioctl_setfreq(struct net_device *dev,
448 } 448 }
449 449
450 if ((chan < 1) || (chan > NUM_CHANNELS) || 450 if ((chan < 1) || (chan > NUM_CHANNELS) ||
451 !(priv->channel_mask & (1 << (chan-1)))) 451 !(priv->channel_mask & (1 << (chan - 1))))
452 return -EINVAL; 452 return -EINVAL;
453 453
454 if (orinoco_lock(priv, &flags) != 0) 454 if (orinoco_lock(priv, &flags) != 0)
@@ -457,7 +457,7 @@ static int orinoco_ioctl_setfreq(struct net_device *dev,
457 priv->channel = chan; 457 priv->channel = chan;
458 if (priv->iw_mode == NL80211_IFTYPE_MONITOR) { 458 if (priv->iw_mode == NL80211_IFTYPE_MONITOR) {
459 /* Fast channel change - no commit if successful */ 459 /* Fast channel change - no commit if successful */
460 hermes_t *hw = &priv->hw; 460 struct hermes *hw = &priv->hw;
461 err = hw->ops->cmd_wait(hw, HERMES_CMD_TEST | 461 err = hw->ops->cmd_wait(hw, HERMES_CMD_TEST |
462 HERMES_TEST_SET_CHANNEL, 462 HERMES_TEST_SET_CHANNEL,
463 chan, NULL); 463 chan, NULL);
@@ -492,7 +492,7 @@ static int orinoco_ioctl_getsens(struct net_device *dev,
492 char *extra) 492 char *extra)
493{ 493{
494 struct orinoco_private *priv = ndev_priv(dev); 494 struct orinoco_private *priv = ndev_priv(dev);
495 hermes_t *hw = &priv->hw; 495 struct hermes *hw = &priv->hw;
496 u16 val; 496 u16 val;
497 int err; 497 int err;
498 unsigned long flags; 498 unsigned long flags;
@@ -668,7 +668,7 @@ static int orinoco_ioctl_getpower(struct net_device *dev,
668 char *extra) 668 char *extra)
669{ 669{
670 struct orinoco_private *priv = ndev_priv(dev); 670 struct orinoco_private *priv = ndev_priv(dev);
671 hermes_t *hw = &priv->hw; 671 struct hermes *hw = &priv->hw;
672 int err = 0; 672 int err = 0;
673 u16 enable, period, timeout, mcast; 673 u16 enable, period, timeout, mcast;
674 unsigned long flags; 674 unsigned long flags;
@@ -873,7 +873,7 @@ static int orinoco_ioctl_set_auth(struct net_device *dev,
873 union iwreq_data *wrqu, char *extra) 873 union iwreq_data *wrqu, char *extra)
874{ 874{
875 struct orinoco_private *priv = ndev_priv(dev); 875 struct orinoco_private *priv = ndev_priv(dev);
876 hermes_t *hw = &priv->hw; 876 struct hermes *hw = &priv->hw;
877 struct iw_param *param = &wrqu->param; 877 struct iw_param *param = &wrqu->param;
878 unsigned long flags; 878 unsigned long flags;
879 int ret = -EINPROGRESS; 879 int ret = -EINPROGRESS;
@@ -1269,7 +1269,7 @@ static int orinoco_ioctl_getrid(struct net_device *dev,
1269 char *extra) 1269 char *extra)
1270{ 1270{
1271 struct orinoco_private *priv = ndev_priv(dev); 1271 struct orinoco_private *priv = ndev_priv(dev);
1272 hermes_t *hw = &priv->hw; 1272 struct hermes *hw = &priv->hw;
1273 int rid = data->flags; 1273 int rid = data->flags;
1274 u16 length; 1274 u16 length;
1275 int err; 1275 int err;
diff --git a/drivers/net/wireless/p54/p54pci.h b/drivers/net/wireless/p54/p54pci.h
index ee9bc62a4fa2..7aa509f7e387 100644
--- a/drivers/net/wireless/p54/p54pci.h
+++ b/drivers/net/wireless/p54/p54pci.h
@@ -1,5 +1,6 @@
1#ifndef P54PCI_H 1#ifndef P54PCI_H
2#define P54PCI_H 2#define P54PCI_H
3#include <linux/interrupt.h>
3 4
4/* 5/*
5 * Defines for PCI based mac80211 Prism54 driver 6 * Defines for PCI based mac80211 Prism54 driver
diff --git a/drivers/net/wireless/prism54/islpci_dev.c b/drivers/net/wireless/prism54/islpci_dev.c
index ec2c75d77cea..5d0f61508a2e 100644
--- a/drivers/net/wireless/prism54/islpci_dev.c
+++ b/drivers/net/wireless/prism54/islpci_dev.c
@@ -18,6 +18,7 @@
18 * 18 *
19 */ 19 */
20 20
21#include <linux/hardirq.h>
21#include <linux/module.h> 22#include <linux/module.h>
22#include <linux/slab.h> 23#include <linux/slab.h>
23 24
diff --git a/drivers/net/wireless/prism54/islpci_dev.h b/drivers/net/wireless/prism54/islpci_dev.h
index c4d0f19b7cbc..c40403877f97 100644
--- a/drivers/net/wireless/prism54/islpci_dev.h
+++ b/drivers/net/wireless/prism54/islpci_dev.h
@@ -22,6 +22,7 @@
22#ifndef _ISLPCI_DEV_H 22#ifndef _ISLPCI_DEV_H
23#define _ISLPCI_DEV_H 23#define _ISLPCI_DEV_H
24 24
25#include <linux/irqreturn.h>
25#include <linux/netdevice.h> 26#include <linux/netdevice.h>
26#include <linux/wireless.h> 27#include <linux/wireless.h>
27#include <net/iw_handler.h> 28#include <net/iw_handler.h>
diff --git a/drivers/net/wireless/prism54/islpci_hotplug.c b/drivers/net/wireless/prism54/islpci_hotplug.c
index b5e64d71b7a6..9e68e0cb718e 100644
--- a/drivers/net/wireless/prism54/islpci_hotplug.c
+++ b/drivers/net/wireless/prism54/islpci_hotplug.c
@@ -17,6 +17,7 @@
17 * 17 *
18 */ 18 */
19 19
20#include <linux/interrupt.h>
20#include <linux/module.h> 21#include <linux/module.h>
21#include <linux/pci.h> 22#include <linux/pci.h>
22#include <linux/delay.h> 23#include <linux/delay.h>
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index b2f8b8fd4d2d..a0a7854facc0 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -83,14 +83,12 @@ config RT2800PCI_RT33XX
83config RT2800PCI_RT35XX 83config RT2800PCI_RT35XX
84 bool "rt2800pci - Include support for rt35xx devices (EXPERIMENTAL)" 84 bool "rt2800pci - Include support for rt35xx devices (EXPERIMENTAL)"
85 depends on EXPERIMENTAL 85 depends on EXPERIMENTAL
86 default n 86 default y
87 ---help--- 87 ---help---
88 This adds support for rt35xx wireless chipset family to the 88 This adds support for rt35xx wireless chipset family to the
89 rt2800pci driver. 89 rt2800pci driver.
90 Supported chips: RT3060, RT3062, RT3562, RT3592 90 Supported chips: RT3060, RT3062, RT3562, RT3592
91 91
92 Support for these devices is non-functional at the moment and is
93 intended for testers and developers.
94 92
95config RT2800PCI_RT53XX 93config RT2800PCI_RT53XX
96 bool "rt2800pci - Include support for rt53xx devices (EXPERIMENTAL)" 94 bool "rt2800pci - Include support for rt53xx devices (EXPERIMENTAL)"
@@ -154,15 +152,12 @@ config RT2800USB_RT33XX
154config RT2800USB_RT35XX 152config RT2800USB_RT35XX
155 bool "rt2800usb - Include support for rt35xx devices (EXPERIMENTAL)" 153 bool "rt2800usb - Include support for rt35xx devices (EXPERIMENTAL)"
156 depends on EXPERIMENTAL 154 depends on EXPERIMENTAL
157 default n 155 default y
158 ---help--- 156 ---help---
159 This adds support for rt35xx wireless chipset family to the 157 This adds support for rt35xx wireless chipset family to the
160 rt2800usb driver. 158 rt2800usb driver.
161 Supported chips: RT3572 159 Supported chips: RT3572
162 160
163 Support for these devices is non-functional at the moment and is
164 intended for testers and developers.
165
166config RT2800USB_RT53XX 161config RT2800USB_RT53XX
167 bool "rt2800usb - Include support for rt53xx devices (EXPERIMENTAL)" 162 bool "rt2800usb - Include support for rt53xx devices (EXPERIMENTAL)"
168 depends on EXPERIMENTAL 163 depends on EXPERIMENTAL
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 937f9e8bf05f..76bcc3547976 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -1723,6 +1723,7 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1723 .set_antenna = rt2x00mac_set_antenna, 1723 .set_antenna = rt2x00mac_set_antenna,
1724 .get_antenna = rt2x00mac_get_antenna, 1724 .get_antenna = rt2x00mac_get_antenna,
1725 .get_ringparam = rt2x00mac_get_ringparam, 1725 .get_ringparam = rt2x00mac_get_ringparam,
1726 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1726}; 1727};
1727 1728
1728static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = { 1729static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index d27d7b8ba3b6..c288d951c034 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -2016,6 +2016,7 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
2016 .set_antenna = rt2x00mac_set_antenna, 2016 .set_antenna = rt2x00mac_set_antenna,
2017 .get_antenna = rt2x00mac_get_antenna, 2017 .get_antenna = rt2x00mac_get_antenna,
2018 .get_ringparam = rt2x00mac_get_ringparam, 2018 .get_ringparam = rt2x00mac_get_ringparam,
2019 .tx_frames_pending = rt2x00mac_tx_frames_pending,
2019}; 2020};
2020 2021
2021static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { 2022static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index 15237c275486..53c5f878f61d 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -1827,6 +1827,7 @@ static const struct ieee80211_ops rt2500usb_mac80211_ops = {
1827 .set_antenna = rt2x00mac_set_antenna, 1827 .set_antenna = rt2x00mac_set_antenna,
1828 .get_antenna = rt2x00mac_get_antenna, 1828 .get_antenna = rt2x00mac_get_antenna,
1829 .get_ringparam = rt2x00mac_get_ringparam, 1829 .get_ringparam = rt2x00mac_get_ringparam,
1830 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1830}; 1831};
1831 1832
1832static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = { 1833static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index f67bc9b31b28..c69a7d71f4ca 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -1740,6 +1740,7 @@ struct mac_iveiv_entry {
1740/* 1740/*
1741 * BBP 3: RX Antenna 1741 * BBP 3: RX Antenna
1742 */ 1742 */
1743#define BBP3_RX_ADC FIELD8(0x03)
1743#define BBP3_RX_ANTENNA FIELD8(0x18) 1744#define BBP3_RX_ANTENNA FIELD8(0x18)
1744#define BBP3_HT40_MINUS FIELD8(0x20) 1745#define BBP3_HT40_MINUS FIELD8(0x20)
1745 1746
@@ -1783,6 +1784,8 @@ struct mac_iveiv_entry {
1783#define RFCSR1_TX0_PD FIELD8(0x08) 1784#define RFCSR1_TX0_PD FIELD8(0x08)
1784#define RFCSR1_RX1_PD FIELD8(0x10) 1785#define RFCSR1_RX1_PD FIELD8(0x10)
1785#define RFCSR1_TX1_PD FIELD8(0x20) 1786#define RFCSR1_TX1_PD FIELD8(0x20)
1787#define RFCSR1_RX2_PD FIELD8(0x40)
1788#define RFCSR1_TX2_PD FIELD8(0x80)
1786 1789
1787/* 1790/*
1788 * RFCSR 2: 1791 * RFCSR 2:
@@ -1790,15 +1793,25 @@ struct mac_iveiv_entry {
1790#define RFCSR2_RESCAL_EN FIELD8(0x80) 1793#define RFCSR2_RESCAL_EN FIELD8(0x80)
1791 1794
1792/* 1795/*
1796 * FRCSR 5:
1797 */
1798#define RFCSR5_R1 FIELD8(0x0c)
1799
1800/*
1793 * RFCSR 6: 1801 * RFCSR 6:
1794 */ 1802 */
1795#define RFCSR6_R1 FIELD8(0x03) 1803#define RFCSR6_R1 FIELD8(0x03)
1796#define RFCSR6_R2 FIELD8(0x40) 1804#define RFCSR6_R2 FIELD8(0x40)
1805#define RFCSR6_TXDIV FIELD8(0x0c)
1797 1806
1798/* 1807/*
1799 * RFCSR 7: 1808 * RFCSR 7:
1800 */ 1809 */
1801#define RFCSR7_RF_TUNING FIELD8(0x01) 1810#define RFCSR7_RF_TUNING FIELD8(0x01)
1811#define RFCSR7_R02 FIELD8(0x07)
1812#define RFCSR7_R3 FIELD8(0x08)
1813#define RFCSR7_R45 FIELD8(0x30)
1814#define RFCSR7_R67 FIELD8(0xc0)
1802 1815
1803/* 1816/*
1804 * RFCSR 11: 1817 * RFCSR 11:
@@ -1809,11 +1822,13 @@ struct mac_iveiv_entry {
1809 * RFCSR 12: 1822 * RFCSR 12:
1810 */ 1823 */
1811#define RFCSR12_TX_POWER FIELD8(0x1f) 1824#define RFCSR12_TX_POWER FIELD8(0x1f)
1825#define RFCSR12_DR0 FIELD8(0xe0)
1812 1826
1813/* 1827/*
1814 * RFCSR 13: 1828 * RFCSR 13:
1815 */ 1829 */
1816#define RFCSR13_TX_POWER FIELD8(0x1f) 1830#define RFCSR13_TX_POWER FIELD8(0x1f)
1831#define RFCSR13_DR0 FIELD8(0xe0)
1817 1832
1818/* 1833/*
1819 * RFCSR 15: 1834 * RFCSR 15:
@@ -2256,6 +2271,7 @@ struct mac_iveiv_entry {
2256#define MCU_ANT_SELECT 0X73 2271#define MCU_ANT_SELECT 0X73
2257#define MCU_BBP_SIGNAL 0x80 2272#define MCU_BBP_SIGNAL 0x80
2258#define MCU_POWER_SAVE 0x83 2273#define MCU_POWER_SAVE 0x83
2274#define MCU_BAND_SELECT 0x91
2259 2275
2260/* 2276/*
2261 * MCU mailbox tokens 2277 * MCU mailbox tokens
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 2a6aa85cc6c9..84ab7d1acb6a 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -401,7 +401,8 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
401 return -EBUSY; 401 return -EBUSY;
402 402
403 if (rt2x00_is_pci(rt2x00dev)) { 403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT5390)) { 404 if (rt2x00_rt(rt2x00dev, RT3572) ||
405 rt2x00_rt(rt2x00dev, RT5390)) {
405 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg); 406 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1); 407 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1); 408 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
@@ -600,49 +601,6 @@ void rt2800_process_rxwi(struct queue_entry *entry,
600} 601}
601EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 602EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
602 603
603static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
604{
605 __le32 *txwi;
606 u32 word;
607 int wcid, ack, pid;
608 int tx_wcid, tx_ack, tx_pid;
609
610 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
611 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
612 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
613
614 /*
615 * This frames has returned with an IO error,
616 * so the status report is not intended for this
617 * frame.
618 */
619 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
620 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
621 return false;
622 }
623
624 /*
625 * Validate if this TX status report is intended for
626 * this entry by comparing the WCID/ACK/PID fields.
627 */
628 txwi = rt2800_drv_get_txwi(entry);
629
630 rt2x00_desc_read(txwi, 1, &word);
631 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
632 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
633 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
634
635 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
636 WARNING(entry->queue->rt2x00dev,
637 "TX status report missed for queue %d entry %d\n",
638 entry->queue->qid, entry->entry_idx);
639 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
640 return false;
641 }
642
643 return true;
644}
645
646void rt2800_txdone_entry(struct queue_entry *entry, u32 status) 604void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
647{ 605{
648 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 606 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
@@ -725,45 +683,6 @@ void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
725} 683}
726EXPORT_SYMBOL_GPL(rt2800_txdone_entry); 684EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
727 685
728void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
729{
730 struct data_queue *queue;
731 struct queue_entry *entry;
732 u32 reg;
733 u8 qid;
734
735 while (kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
736
737 /* TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus
738 * qid is guaranteed to be one of the TX QIDs
739 */
740 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
741 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
742 if (unlikely(!queue)) {
743 WARNING(rt2x00dev, "Got TX status for an unavailable "
744 "queue %u, dropping\n", qid);
745 continue;
746 }
747
748 /*
749 * Inside each queue, we process each entry in a chronological
750 * order. We first check that the queue is not empty.
751 */
752 entry = NULL;
753 while (!rt2x00queue_empty(queue)) {
754 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
755 if (rt2800_txdone_entry_check(entry, reg))
756 break;
757 }
758
759 if (!entry || rt2x00queue_empty(queue))
760 break;
761
762 rt2800_txdone_entry(entry, reg);
763 }
764}
765EXPORT_SYMBOL_GPL(rt2800_txdone);
766
767void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) 686void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
768{ 687{
769 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 688 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
@@ -1355,7 +1274,7 @@ static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1355 gf20_rate = gf40_rate = 0x0003; 1274 gf20_rate = gf40_rate = 0x0003;
1356 } 1275 }
1357 break; 1276 break;
1358 }; 1277 }
1359 1278
1360 /* check for STAs not supporting greenfield mode */ 1279 /* check for STAs not supporting greenfield mode */
1361 if (any_sta_nongf) 1280 if (any_sta_nongf)
@@ -1433,6 +1352,40 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1433} 1352}
1434EXPORT_SYMBOL_GPL(rt2800_config_erp); 1353EXPORT_SYMBOL_GPL(rt2800_config_erp);
1435 1354
1355static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1356{
1357 u32 reg;
1358 u16 eeprom;
1359 u8 led_ctrl, led_g_mode, led_r_mode;
1360
1361 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1362 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1363 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1364 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1365 } else {
1366 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1367 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1368 }
1369 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1370
1371 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1372 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1373 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1374 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1375 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1376 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1377 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1378 if (led_ctrl == 0 || led_ctrl > 0x40) {
1379 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1380 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1381 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1382 } else {
1383 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1384 (led_g_mode << 2) | led_r_mode, 1);
1385 }
1386 }
1387}
1388
1436static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, 1389static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1437 enum antenna ant) 1390 enum antenna ant)
1438{ 1391{
@@ -1463,6 +1416,10 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1463 rt2800_bbp_read(rt2x00dev, 1, &r1); 1416 rt2800_bbp_read(rt2x00dev, 1, &r1);
1464 rt2800_bbp_read(rt2x00dev, 3, &r3); 1417 rt2800_bbp_read(rt2x00dev, 3, &r3);
1465 1418
1419 if (rt2x00_rt(rt2x00dev, RT3572) &&
1420 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1421 rt2800_config_3572bt_ant(rt2x00dev);
1422
1466 /* 1423 /*
1467 * Configure the TX antenna. 1424 * Configure the TX antenna.
1468 */ 1425 */
@@ -1471,7 +1428,11 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1471 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 1428 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1472 break; 1429 break;
1473 case 2: 1430 case 2:
1474 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); 1431 if (rt2x00_rt(rt2x00dev, RT3572) &&
1432 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1433 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1434 else
1435 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1475 break; 1436 break;
1476 case 3: 1437 case 3:
1477 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 1438 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
@@ -1496,7 +1457,15 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1496 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 1457 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1497 break; 1458 break;
1498 case 2: 1459 case 2:
1499 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); 1460 if (rt2x00_rt(rt2x00dev, RT3572) &&
1461 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1462 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1463 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1464 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1465 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1466 } else {
1467 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1468 }
1500 break; 1469 break;
1501 case 3: 1470 case 3:
1502 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); 1471 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
@@ -1630,6 +1599,161 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1630 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 1599 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1631} 1600}
1632 1601
1602static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1603 struct ieee80211_conf *conf,
1604 struct rf_channel *rf,
1605 struct channel_info *info)
1606{
1607 u8 rfcsr;
1608 u32 reg;
1609
1610 if (rf->channel <= 14) {
1611 rt2800_bbp_write(rt2x00dev, 25, 0x15);
1612 rt2800_bbp_write(rt2x00dev, 26, 0x85);
1613 } else {
1614 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1615 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1616 }
1617
1618 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1619 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1620
1621 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1622 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1623 if (rf->channel <= 14)
1624 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1625 else
1626 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1627 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1628
1629 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1630 if (rf->channel <= 14)
1631 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1632 else
1633 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1634 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1635
1636 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1637 if (rf->channel <= 14) {
1638 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1639 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1640 (info->default_power1 & 0x3) |
1641 ((info->default_power1 & 0xC) << 1));
1642 } else {
1643 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1644 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1645 (info->default_power1 & 0x3) |
1646 ((info->default_power1 & 0xC) << 1));
1647 }
1648 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1649
1650 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1651 if (rf->channel <= 14) {
1652 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1653 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1654 (info->default_power2 & 0x3) |
1655 ((info->default_power2 & 0xC) << 1));
1656 } else {
1657 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1658 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1659 (info->default_power2 & 0x3) |
1660 ((info->default_power2 & 0xC) << 1));
1661 }
1662 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1663
1664 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1665 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1666 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1667 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1668 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1669 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1670 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1671 if (rf->channel <= 14) {
1672 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1673 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1674 }
1675 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1676 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1677 } else {
1678 switch (rt2x00dev->default_ant.tx_chain_num) {
1679 case 1:
1680 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1681 case 2:
1682 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1683 break;
1684 }
1685
1686 switch (rt2x00dev->default_ant.rx_chain_num) {
1687 case 1:
1688 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1689 case 2:
1690 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1691 break;
1692 }
1693 }
1694 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1695
1696 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1697 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1698 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1699
1700 rt2800_rfcsr_write(rt2x00dev, 24,
1701 rt2x00dev->calibration[conf_is_ht40(conf)]);
1702 rt2800_rfcsr_write(rt2x00dev, 31,
1703 rt2x00dev->calibration[conf_is_ht40(conf)]);
1704
1705 if (rf->channel <= 14) {
1706 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1707 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1708 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1709 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1710 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1711 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
1712 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1713 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1714 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1715 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1716 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1717 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1718 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1719 } else {
1720 rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
1721 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1722 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1723 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1724 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1725 rt2800_rfcsr_write(rt2x00dev, 16, 0x7a);
1726 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1727 if (rf->channel <= 64) {
1728 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1729 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1730 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1731 } else if (rf->channel <= 128) {
1732 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1733 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1734 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1735 } else {
1736 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1737 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1738 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1739 }
1740 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1741 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1742 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1743 }
1744
1745 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1746 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1747 if (rf->channel <= 14)
1748 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1749 else
1750 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1751 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1752
1753 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1754 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1755 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1756}
1633 1757
1634#define RT5390_POWER_BOUND 0x27 1758#define RT5390_POWER_BOUND 0x27
1635#define RT5390_FREQ_OFFSET_BOUND 0x5f 1759#define RT5390_FREQ_OFFSET_BOUND 0x5f
@@ -1748,9 +1872,10 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1748 rt2x00_rf(rt2x00dev, RF3020) || 1872 rt2x00_rf(rt2x00dev, RF3020) ||
1749 rt2x00_rf(rt2x00dev, RF3021) || 1873 rt2x00_rf(rt2x00dev, RF3021) ||
1750 rt2x00_rf(rt2x00dev, RF3022) || 1874 rt2x00_rf(rt2x00dev, RF3022) ||
1751 rt2x00_rf(rt2x00dev, RF3052) ||
1752 rt2x00_rf(rt2x00dev, RF3320)) 1875 rt2x00_rf(rt2x00dev, RF3320))
1753 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 1876 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1877 else if (rt2x00_rf(rt2x00dev, RF3052))
1878 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
1754 else if (rt2x00_rf(rt2x00dev, RF5370) || 1879 else if (rt2x00_rf(rt2x00dev, RF5370) ||
1755 rt2x00_rf(rt2x00dev, RF5390)) 1880 rt2x00_rf(rt2x00dev, RF5390))
1756 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 1881 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
@@ -1777,7 +1902,10 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1777 } 1902 }
1778 } 1903 }
1779 } else { 1904 } else {
1780 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 1905 if (rt2x00_rt(rt2x00dev, RT3572))
1906 rt2800_bbp_write(rt2x00dev, 82, 0x94);
1907 else
1908 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1781 1909
1782 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) 1910 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
1783 rt2800_bbp_write(rt2x00dev, 75, 0x46); 1911 rt2800_bbp_write(rt2x00dev, 75, 0x46);
@@ -1791,12 +1919,17 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1791 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14); 1919 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1792 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 1920 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1793 1921
1922 if (rt2x00_rt(rt2x00dev, RT3572))
1923 rt2800_rfcsr_write(rt2x00dev, 8, 0);
1924
1794 tx_pin = 0; 1925 tx_pin = 0;
1795 1926
1796 /* Turn on unused PA or LNA when not using 1T or 1R */ 1927 /* Turn on unused PA or LNA when not using 1T or 1R */
1797 if (rt2x00dev->default_ant.tx_chain_num == 2) { 1928 if (rt2x00dev->default_ant.tx_chain_num == 2) {
1798 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 1929 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
1799 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 1930 rf->channel > 14);
1931 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
1932 rf->channel <= 14);
1800 } 1933 }
1801 1934
1802 /* Turn on unused PA or LNA when not using 1T or 1R */ 1935 /* Turn on unused PA or LNA when not using 1T or 1R */
@@ -1809,11 +1942,18 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1809 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); 1942 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1810 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); 1943 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1811 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); 1944 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1812 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14); 1945 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1946 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
1947 else
1948 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
1949 rf->channel <= 14);
1813 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); 1950 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1814 1951
1815 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); 1952 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1816 1953
1954 if (rt2x00_rt(rt2x00dev, RT3572))
1955 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
1956
1817 rt2800_bbp_read(rt2x00dev, 4, &bbp); 1957 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1818 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 1958 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1819 rt2800_bbp_write(rt2x00dev, 4, bbp); 1959 rt2800_bbp_write(rt2x00dev, 4, bbp);
@@ -2413,6 +2553,9 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2413 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 2553 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2414 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 2554 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2415 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 2555 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2556 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2557 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2558 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2416 } else if (rt2x00_rt(rt2x00dev, RT5390)) { 2559 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2417 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 2560 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2418 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 2561 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -2799,6 +2942,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2799 } 2942 }
2800 2943
2801 if (rt2800_is_305x_soc(rt2x00dev) || 2944 if (rt2800_is_305x_soc(rt2x00dev) ||
2945 rt2x00_rt(rt2x00dev, RT3572) ||
2802 rt2x00_rt(rt2x00dev, RT5390)) 2946 rt2x00_rt(rt2x00dev, RT5390))
2803 rt2800_bbp_write(rt2x00dev, 31, 0x08); 2947 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2804 2948
@@ -2828,6 +2972,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2828 rt2x00_rt(rt2x00dev, RT3071) || 2972 rt2x00_rt(rt2x00dev, RT3071) ||
2829 rt2x00_rt(rt2x00dev, RT3090) || 2973 rt2x00_rt(rt2x00dev, RT3090) ||
2830 rt2x00_rt(rt2x00dev, RT3390) || 2974 rt2x00_rt(rt2x00dev, RT3390) ||
2975 rt2x00_rt(rt2x00dev, RT3572) ||
2831 rt2x00_rt(rt2x00dev, RT5390)) { 2976 rt2x00_rt(rt2x00dev, RT5390)) {
2832 rt2800_bbp_write(rt2x00dev, 79, 0x13); 2977 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2833 rt2800_bbp_write(rt2x00dev, 80, 0x05); 2978 rt2800_bbp_write(rt2x00dev, 80, 0x05);
@@ -2868,6 +3013,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2868 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 3013 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2869 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 3014 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2870 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 3015 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3016 rt2x00_rt(rt2x00dev, RT3572) ||
2871 rt2x00_rt(rt2x00dev, RT5390) || 3017 rt2x00_rt(rt2x00dev, RT5390) ||
2872 rt2800_is_305x_soc(rt2x00dev)) 3018 rt2800_is_305x_soc(rt2x00dev))
2873 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 3019 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
@@ -2895,6 +3041,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2895 if (rt2x00_rt(rt2x00dev, RT3071) || 3041 if (rt2x00_rt(rt2x00dev, RT3071) ||
2896 rt2x00_rt(rt2x00dev, RT3090) || 3042 rt2x00_rt(rt2x00dev, RT3090) ||
2897 rt2x00_rt(rt2x00dev, RT3390) || 3043 rt2x00_rt(rt2x00dev, RT3390) ||
3044 rt2x00_rt(rt2x00dev, RT3572) ||
2898 rt2x00_rt(rt2x00dev, RT5390)) { 3045 rt2x00_rt(rt2x00dev, RT5390)) {
2899 rt2800_bbp_read(rt2x00dev, 138, &value); 3046 rt2800_bbp_read(rt2x00dev, 138, &value);
2900 3047
@@ -3031,6 +3178,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3031 !rt2x00_rt(rt2x00dev, RT3071) && 3178 !rt2x00_rt(rt2x00dev, RT3071) &&
3032 !rt2x00_rt(rt2x00dev, RT3090) && 3179 !rt2x00_rt(rt2x00dev, RT3090) &&
3033 !rt2x00_rt(rt2x00dev, RT3390) && 3180 !rt2x00_rt(rt2x00dev, RT3390) &&
3181 !rt2x00_rt(rt2x00dev, RT3572) &&
3034 !rt2x00_rt(rt2x00dev, RT5390) && 3182 !rt2x00_rt(rt2x00dev, RT5390) &&
3035 !rt2800_is_305x_soc(rt2x00dev)) 3183 !rt2800_is_305x_soc(rt2x00dev))
3036 return 0; 3184 return 0;
@@ -3109,6 +3257,38 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3109 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 3257 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3110 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 3258 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3111 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 3259 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3260 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3261 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3262 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3263 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3264 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3265 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3266 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3267 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3268 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3269 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3270 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3271 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3272 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3273 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3274 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3275 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3276 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3277 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3278 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3279 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3280 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3281 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3282 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3283 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3284 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3285 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3286 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3287 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3288 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3289 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3290 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3291 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3112 } else if (rt2800_is_305x_soc(rt2x00dev)) { 3292 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3113 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 3293 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3114 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 3294 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
@@ -3258,6 +3438,19 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3258 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg); 3438 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3259 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0); 3439 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3260 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); 3440 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3441 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3442 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3443 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3444 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3445
3446 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3447 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3448 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3449 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3450 msleep(1);
3451 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3452 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3453 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3261 } 3454 }
3262 3455
3263 /* 3456 /*
@@ -3270,7 +3463,8 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3270 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 3463 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3271 } else if (rt2x00_rt(rt2x00dev, RT3071) || 3464 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3272 rt2x00_rt(rt2x00dev, RT3090) || 3465 rt2x00_rt(rt2x00dev, RT3090) ||
3273 rt2x00_rt(rt2x00dev, RT3390)) { 3466 rt2x00_rt(rt2x00dev, RT3390) ||
3467 rt2x00_rt(rt2x00dev, RT3572)) {
3274 rt2x00dev->calibration[0] = 3468 rt2x00dev->calibration[0] =
3275 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13); 3469 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3276 rt2x00dev->calibration[1] = 3470 rt2x00dev->calibration[1] =
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
index f2d15941c71a..69deb3148ae7 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.h
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -152,7 +152,6 @@ void rt2800_write_tx_data(struct queue_entry *entry,
152 struct txentry_desc *txdesc); 152 struct txentry_desc *txdesc);
153void rt2800_process_rxwi(struct queue_entry *entry, struct rxdone_entry_desc *txdesc); 153void rt2800_process_rxwi(struct queue_entry *entry, struct rxdone_entry_desc *txdesc);
154 154
155void rt2800_txdone(struct rt2x00_dev *rt2x00dev);
156void rt2800_txdone_entry(struct queue_entry *entry, u32 status); 155void rt2800_txdone_entry(struct queue_entry *entry, u32 status);
157 156
158void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc); 157void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc);
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index cc4a54f571b8..ebc17ad61dec 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -219,7 +219,7 @@ static void rt2800pci_start_queue(struct data_queue *queue)
219 break; 219 break;
220 default: 220 default:
221 break; 221 break;
222 }; 222 }
223} 223}
224 224
225static void rt2800pci_kick_queue(struct data_queue *queue) 225static void rt2800pci_kick_queue(struct data_queue *queue)
@@ -501,7 +501,9 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 501 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
502 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 502 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
503 503
504 if (rt2x00_rt(rt2x00dev, RT5390)) { 504 if (rt2x00_is_pcie(rt2x00dev) &&
505 (rt2x00_rt(rt2x00dev, RT3572) ||
506 rt2x00_rt(rt2x00dev, RT5390))) {
505 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg); 507 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
506 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1); 508 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
507 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1); 509 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
@@ -1029,6 +1031,7 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1029 .flush = rt2x00mac_flush, 1031 .flush = rt2x00mac_flush,
1030 .get_survey = rt2800_get_survey, 1032 .get_survey = rt2800_get_survey,
1031 .get_ringparam = rt2x00mac_get_ringparam, 1033 .get_ringparam = rt2x00mac_get_ringparam,
1034 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1032}; 1035};
1033 1036
1034static const struct rt2800_ops rt2800pci_rt2800_ops = { 1037static const struct rt2800_ops rt2800pci_rt2800_ops = {
@@ -1158,6 +1161,7 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1158#endif 1161#endif
1159#ifdef CONFIG_RT2800PCI_RT53XX 1162#ifdef CONFIG_RT2800PCI_RT53XX
1160 { PCI_DEVICE(0x1814, 0x5390) }, 1163 { PCI_DEVICE(0x1814, 0x5390) },
1164 { PCI_DEVICE(0x1814, 0x539f) },
1161#endif 1165#endif
1162 { 0, } 1166 { 0, }
1163}; 1167};
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index ba82c972703a..507559361d87 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -457,6 +457,87 @@ static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
457/* 457/*
458 * TX control handlers 458 * TX control handlers
459 */ 459 */
460static bool rt2800usb_txdone_entry_check(struct queue_entry *entry, u32 reg)
461{
462 __le32 *txwi;
463 u32 word;
464 int wcid, ack, pid;
465 int tx_wcid, tx_ack, tx_pid;
466
467 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
468 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
469 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
470
471 /*
472 * This frames has returned with an IO error,
473 * so the status report is not intended for this
474 * frame.
475 */
476 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
477 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
478 return false;
479 }
480
481 /*
482 * Validate if this TX status report is intended for
483 * this entry by comparing the WCID/ACK/PID fields.
484 */
485 txwi = rt2800usb_get_txwi(entry);
486
487 rt2x00_desc_read(txwi, 1, &word);
488 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
489 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
490 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
491
492 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
493 WARNING(entry->queue->rt2x00dev,
494 "TX status report missed for queue %d entry %d\n",
495 entry->queue->qid, entry->entry_idx);
496 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
497 return false;
498 }
499
500 return true;
501}
502
503static void rt2800usb_txdone(struct rt2x00_dev *rt2x00dev)
504{
505 struct data_queue *queue;
506 struct queue_entry *entry;
507 u32 reg;
508 u8 qid;
509
510 while (kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
511
512 /* TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus
513 * qid is guaranteed to be one of the TX QIDs
514 */
515 qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
516 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
517 if (unlikely(!queue)) {
518 WARNING(rt2x00dev, "Got TX status for an unavailable "
519 "queue %u, dropping\n", qid);
520 continue;
521 }
522
523 /*
524 * Inside each queue, we process each entry in a chronological
525 * order. We first check that the queue is not empty.
526 */
527 entry = NULL;
528 while (!rt2x00queue_empty(queue)) {
529 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
530 if (rt2800usb_txdone_entry_check(entry, reg))
531 break;
532 }
533
534 if (!entry || rt2x00queue_empty(queue))
535 break;
536
537 rt2800_txdone_entry(entry, reg);
538 }
539}
540
460static void rt2800usb_work_txdone(struct work_struct *work) 541static void rt2800usb_work_txdone(struct work_struct *work)
461{ 542{
462 struct rt2x00_dev *rt2x00dev = 543 struct rt2x00_dev *rt2x00dev =
@@ -464,7 +545,7 @@ static void rt2800usb_work_txdone(struct work_struct *work)
464 struct data_queue *queue; 545 struct data_queue *queue;
465 struct queue_entry *entry; 546 struct queue_entry *entry;
466 547
467 rt2800_txdone(rt2x00dev); 548 rt2800usb_txdone(rt2x00dev);
468 549
469 /* 550 /*
470 * Process any trailing TX status reports for IO failures, 551 * Process any trailing TX status reports for IO failures,
@@ -676,6 +757,7 @@ static const struct ieee80211_ops rt2800usb_mac80211_ops = {
676 .flush = rt2x00mac_flush, 757 .flush = rt2x00mac_flush,
677 .get_survey = rt2800_get_survey, 758 .get_survey = rt2800_get_survey,
678 .get_ringparam = rt2x00mac_get_ringparam, 759 .get_ringparam = rt2x00mac_get_ringparam,
760 .tx_frames_pending = rt2x00mac_tx_frames_pending,
679}; 761};
680 762
681static const struct rt2800_ops rt2800usb_rt2800_ops = { 763static const struct rt2800_ops rt2800usb_rt2800_ops = {
@@ -939,6 +1021,7 @@ static struct usb_device_id rt2800usb_device_table[] = {
939 { USB_DEVICE(0x0df6, 0x0048) }, 1021 { USB_DEVICE(0x0df6, 0x0048) },
940 { USB_DEVICE(0x0df6, 0x0051) }, 1022 { USB_DEVICE(0x0df6, 0x0051) },
941 { USB_DEVICE(0x0df6, 0x005f) }, 1023 { USB_DEVICE(0x0df6, 0x005f) },
1024 { USB_DEVICE(0x0df6, 0x0060) },
942 /* SMC */ 1025 /* SMC */
943 { USB_DEVICE(0x083a, 0x6618) }, 1026 { USB_DEVICE(0x083a, 0x6618) },
944 { USB_DEVICE(0x083a, 0x7511) }, 1027 { USB_DEVICE(0x083a, 0x7511) },
@@ -971,6 +1054,8 @@ static struct usb_device_id rt2800usb_device_table[] = {
971 { USB_DEVICE(0x0586, 0x341e) }, 1054 { USB_DEVICE(0x0586, 0x341e) },
972 { USB_DEVICE(0x0586, 0x343e) }, 1055 { USB_DEVICE(0x0586, 0x343e) },
973#ifdef CONFIG_RT2800USB_RT33XX 1056#ifdef CONFIG_RT2800USB_RT33XX
1057 /* Belkin */
1058 { USB_DEVICE(0x050d, 0x945b) },
974 /* Ralink */ 1059 /* Ralink */
975 { USB_DEVICE(0x148f, 0x3370) }, 1060 { USB_DEVICE(0x148f, 0x3370) },
976 { USB_DEVICE(0x148f, 0x8070) }, 1061 { USB_DEVICE(0x148f, 0x8070) },
@@ -995,6 +1080,7 @@ static struct usb_device_id rt2800usb_device_table[] = {
995 { USB_DEVICE(0x148f, 0x3572) }, 1080 { USB_DEVICE(0x148f, 0x3572) },
996 /* Sitecom */ 1081 /* Sitecom */
997 { USB_DEVICE(0x0df6, 0x0041) }, 1082 { USB_DEVICE(0x0df6, 0x0041) },
1083 { USB_DEVICE(0x0df6, 0x0062) },
998 /* Toshiba */ 1084 /* Toshiba */
999 { USB_DEVICE(0x0930, 0x0a07) }, 1085 { USB_DEVICE(0x0930, 0x0a07) },
1000 /* Zinwell */ 1086 /* Zinwell */
@@ -1093,8 +1179,6 @@ static struct usb_device_id rt2800usb_device_table[] = {
1093 { USB_DEVICE(0x0df6, 0x004a) }, 1179 { USB_DEVICE(0x0df6, 0x004a) },
1094 { USB_DEVICE(0x0df6, 0x004d) }, 1180 { USB_DEVICE(0x0df6, 0x004d) },
1095 { USB_DEVICE(0x0df6, 0x0053) }, 1181 { USB_DEVICE(0x0df6, 0x0053) },
1096 { USB_DEVICE(0x0df6, 0x0060) },
1097 { USB_DEVICE(0x0df6, 0x0062) },
1098 /* SMC */ 1182 /* SMC */
1099 { USB_DEVICE(0x083a, 0xa512) }, 1183 { USB_DEVICE(0x083a, 0xa512) },
1100 { USB_DEVICE(0x083a, 0xc522) }, 1184 { USB_DEVICE(0x083a, 0xc522) },
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index c446db69bd3c..f82bfeb79ebb 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -29,6 +29,7 @@
29#define RT2X00_H 29#define RT2X00_H
30 30
31#include <linux/bitops.h> 31#include <linux/bitops.h>
32#include <linux/interrupt.h>
32#include <linux/skbuff.h> 33#include <linux/skbuff.h>
33#include <linux/workqueue.h> 34#include <linux/workqueue.h>
34#include <linux/firmware.h> 35#include <linux/firmware.h>
@@ -1276,6 +1277,7 @@ int rt2x00mac_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant);
1276int rt2x00mac_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1277int rt2x00mac_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
1277void rt2x00mac_get_ringparam(struct ieee80211_hw *hw, 1278void rt2x00mac_get_ringparam(struct ieee80211_hw *hw,
1278 u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max); 1279 u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max);
1280bool rt2x00mac_tx_frames_pending(struct ieee80211_hw *hw);
1279 1281
1280/* 1282/*
1281 * Driver allocation handlers. 1283 * Driver allocation handlers.
diff --git a/drivers/net/wireless/rt2x00/rt2x00crypto.c b/drivers/net/wireless/rt2x00/rt2x00crypto.c
index 1bb9d46077ff..1ca4c7ffc189 100644
--- a/drivers/net/wireless/rt2x00/rt2x00crypto.c
+++ b/drivers/net/wireless/rt2x00/rt2x00crypto.c
@@ -45,11 +45,11 @@ enum cipher rt2x00crypto_key_to_cipher(struct ieee80211_key_conf *key)
45 } 45 }
46} 46}
47 47
48void rt2x00crypto_create_tx_descriptor(struct queue_entry *entry, 48void rt2x00crypto_create_tx_descriptor(struct rt2x00_dev *rt2x00dev,
49 struct sk_buff *skb,
49 struct txentry_desc *txdesc) 50 struct txentry_desc *txdesc)
50{ 51{
51 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 52 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
52 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
53 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 53 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
54 54
55 if (!test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags) || !hw_key) 55 if (!test_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags) || !hw_key)
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
index 939821b4af2f..0955c941317f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dev.c
+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
@@ -583,6 +583,18 @@ void rt2x00lib_rxdone(struct queue_entry *entry)
583 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc); 583 rt2x00dev->ops->lib->fill_rxdone(entry, &rxdesc);
584 584
585 /* 585 /*
586 * Check for valid size in case we get corrupted descriptor from
587 * hardware.
588 */
589 if (unlikely(rxdesc.size == 0 ||
590 rxdesc.size > entry->queue->data_size)) {
591 WARNING(rt2x00dev, "Wrong frame size %d max %d.\n",
592 rxdesc.size, entry->queue->data_size);
593 dev_kfree_skb(entry->skb);
594 goto renew_skb;
595 }
596
597 /*
586 * The data behind the ieee80211 header must be 598 * The data behind the ieee80211 header must be
587 * aligned on a 4 byte boundary. 599 * aligned on a 4 byte boundary.
588 */ 600 */
@@ -642,6 +654,7 @@ void rt2x00lib_rxdone(struct queue_entry *entry)
642 654
643 ieee80211_rx_ni(rt2x00dev->hw, entry->skb); 655 ieee80211_rx_ni(rt2x00dev->hw, entry->skb);
644 656
657renew_skb:
645 /* 658 /*
646 * Replace the skb with the freshly allocated one. 659 * Replace the skb with the freshly allocated one.
647 */ 660 */
diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h
index 322cc4f3de5d..15cdc7e57fc4 100644
--- a/drivers/net/wireless/rt2x00/rt2x00lib.h
+++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
@@ -336,7 +336,8 @@ static inline void rt2x00debug_update_crypto(struct rt2x00_dev *rt2x00dev,
336 */ 336 */
337#ifdef CONFIG_RT2X00_LIB_CRYPTO 337#ifdef CONFIG_RT2X00_LIB_CRYPTO
338enum cipher rt2x00crypto_key_to_cipher(struct ieee80211_key_conf *key); 338enum cipher rt2x00crypto_key_to_cipher(struct ieee80211_key_conf *key);
339void rt2x00crypto_create_tx_descriptor(struct queue_entry *entry, 339void rt2x00crypto_create_tx_descriptor(struct rt2x00_dev *rt2x00dev,
340 struct sk_buff *skb,
340 struct txentry_desc *txdesc); 341 struct txentry_desc *txdesc);
341unsigned int rt2x00crypto_tx_overhead(struct rt2x00_dev *rt2x00dev, 342unsigned int rt2x00crypto_tx_overhead(struct rt2x00_dev *rt2x00dev,
342 struct sk_buff *skb); 343 struct sk_buff *skb);
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c
index 93bec140e598..8efab3983528 100644
--- a/drivers/net/wireless/rt2x00/rt2x00mac.c
+++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
@@ -818,3 +818,17 @@ void rt2x00mac_get_ringparam(struct ieee80211_hw *hw,
818 *rx_max = rt2x00dev->rx->limit; 818 *rx_max = rt2x00dev->rx->limit;
819} 819}
820EXPORT_SYMBOL_GPL(rt2x00mac_get_ringparam); 820EXPORT_SYMBOL_GPL(rt2x00mac_get_ringparam);
821
822bool rt2x00mac_tx_frames_pending(struct ieee80211_hw *hw)
823{
824 struct rt2x00_dev *rt2x00dev = hw->priv;
825 struct data_queue *queue;
826
827 tx_queue_for_each(rt2x00dev, queue) {
828 if (!rt2x00queue_empty(queue))
829 return true;
830 }
831
832 return false;
833}
834EXPORT_SYMBOL_GPL(rt2x00mac_tx_frames_pending);
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index ab8c16f8bcaf..29edb9fbe6f1 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -200,20 +200,20 @@ void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
200 skb_pull(skb, l2pad); 200 skb_pull(skb, l2pad);
201} 201}
202 202
203static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry, 203static void rt2x00queue_create_tx_descriptor_seq(struct rt2x00_dev *rt2x00dev,
204 struct sk_buff *skb,
204 struct txentry_desc *txdesc) 205 struct txentry_desc *txdesc)
205{ 206{
206 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 207 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
207 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data; 208 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
208 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif); 209 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
209 unsigned long irqflags;
210 210
211 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 211 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
212 return; 212 return;
213 213
214 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); 214 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
215 215
216 if (!test_bit(REQUIRE_SW_SEQNO, &entry->queue->rt2x00dev->cap_flags)) 216 if (!test_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags))
217 return; 217 return;
218 218
219 /* 219 /*
@@ -227,23 +227,23 @@ static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
227 * sequence counting per-frame, since those will override the 227 * sequence counting per-frame, since those will override the
228 * sequence counter given by mac80211. 228 * sequence counter given by mac80211.
229 */ 229 */
230 spin_lock_irqsave(&intf->seqlock, irqflags); 230 spin_lock(&intf->seqlock);
231 231
232 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) 232 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
233 intf->seqno += 0x10; 233 intf->seqno += 0x10;
234 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 234 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
235 hdr->seq_ctrl |= cpu_to_le16(intf->seqno); 235 hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
236 236
237 spin_unlock_irqrestore(&intf->seqlock, irqflags); 237 spin_unlock(&intf->seqlock);
238 238
239} 239}
240 240
241static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry, 241static void rt2x00queue_create_tx_descriptor_plcp(struct rt2x00_dev *rt2x00dev,
242 struct sk_buff *skb,
242 struct txentry_desc *txdesc, 243 struct txentry_desc *txdesc,
243 const struct rt2x00_rate *hwrate) 244 const struct rt2x00_rate *hwrate)
244{ 245{
245 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 246 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
246 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
247 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; 247 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
248 unsigned int data_length; 248 unsigned int data_length;
249 unsigned int duration; 249 unsigned int duration;
@@ -260,8 +260,8 @@ static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
260 txdesc->u.plcp.ifs = IFS_SIFS; 260 txdesc->u.plcp.ifs = IFS_SIFS;
261 261
262 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */ 262 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
263 data_length = entry->skb->len + 4; 263 data_length = skb->len + 4;
264 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb); 264 data_length += rt2x00crypto_tx_overhead(rt2x00dev, skb);
265 265
266 /* 266 /*
267 * PLCP setup 267 * PLCP setup
@@ -302,13 +302,14 @@ static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
302 } 302 }
303} 303}
304 304
305static void rt2x00queue_create_tx_descriptor_ht(struct queue_entry *entry, 305static void rt2x00queue_create_tx_descriptor_ht(struct rt2x00_dev *rt2x00dev,
306 struct sk_buff *skb,
306 struct txentry_desc *txdesc, 307 struct txentry_desc *txdesc,
307 const struct rt2x00_rate *hwrate) 308 const struct rt2x00_rate *hwrate)
308{ 309{
309 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 310 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
310 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; 311 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
311 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data; 312 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
312 313
313 if (tx_info->control.sta) 314 if (tx_info->control.sta)
314 txdesc->u.ht.mpdu_density = 315 txdesc->u.ht.mpdu_density =
@@ -381,12 +382,12 @@ static void rt2x00queue_create_tx_descriptor_ht(struct queue_entry *entry,
381 txdesc->u.ht.txop = TXOP_HTTXOP; 382 txdesc->u.ht.txop = TXOP_HTTXOP;
382} 383}
383 384
384static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry, 385static void rt2x00queue_create_tx_descriptor(struct rt2x00_dev *rt2x00dev,
386 struct sk_buff *skb,
385 struct txentry_desc *txdesc) 387 struct txentry_desc *txdesc)
386{ 388{
387 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 389 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
388 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 390 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
389 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
390 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; 391 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
391 struct ieee80211_rate *rate; 392 struct ieee80211_rate *rate;
392 const struct rt2x00_rate *hwrate = NULL; 393 const struct rt2x00_rate *hwrate = NULL;
@@ -396,8 +397,8 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
396 /* 397 /*
397 * Header and frame information. 398 * Header and frame information.
398 */ 399 */
399 txdesc->length = entry->skb->len; 400 txdesc->length = skb->len;
400 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb); 401 txdesc->header_length = ieee80211_get_hdrlen_from_skb(skb);
401 402
402 /* 403 /*
403 * Check whether this frame is to be acked. 404 * Check whether this frame is to be acked.
@@ -472,13 +473,15 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
472 /* 473 /*
473 * Apply TX descriptor handling by components 474 * Apply TX descriptor handling by components
474 */ 475 */
475 rt2x00crypto_create_tx_descriptor(entry, txdesc); 476 rt2x00crypto_create_tx_descriptor(rt2x00dev, skb, txdesc);
476 rt2x00queue_create_tx_descriptor_seq(entry, txdesc); 477 rt2x00queue_create_tx_descriptor_seq(rt2x00dev, skb, txdesc);
477 478
478 if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags)) 479 if (test_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags))
479 rt2x00queue_create_tx_descriptor_ht(entry, txdesc, hwrate); 480 rt2x00queue_create_tx_descriptor_ht(rt2x00dev, skb, txdesc,
481 hwrate);
480 else 482 else
481 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate); 483 rt2x00queue_create_tx_descriptor_plcp(rt2x00dev, skb, txdesc,
484 hwrate);
482} 485}
483 486
484static int rt2x00queue_write_tx_data(struct queue_entry *entry, 487static int rt2x00queue_write_tx_data(struct queue_entry *entry,
@@ -556,33 +559,18 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
556 bool local) 559 bool local)
557{ 560{
558 struct ieee80211_tx_info *tx_info; 561 struct ieee80211_tx_info *tx_info;
559 struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX); 562 struct queue_entry *entry;
560 struct txentry_desc txdesc; 563 struct txentry_desc txdesc;
561 struct skb_frame_desc *skbdesc; 564 struct skb_frame_desc *skbdesc;
562 u8 rate_idx, rate_flags; 565 u8 rate_idx, rate_flags;
563 566 int ret = 0;
564 if (unlikely(rt2x00queue_full(queue))) {
565 ERROR(queue->rt2x00dev,
566 "Dropping frame due to full tx queue %d.\n", queue->qid);
567 return -ENOBUFS;
568 }
569
570 if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
571 &entry->flags))) {
572 ERROR(queue->rt2x00dev,
573 "Arrived at non-free entry in the non-full queue %d.\n"
574 "Please file bug report to %s.\n",
575 queue->qid, DRV_PROJECT);
576 return -EINVAL;
577 }
578 567
579 /* 568 /*
580 * Copy all TX descriptor information into txdesc, 569 * Copy all TX descriptor information into txdesc,
581 * after that we are free to use the skb->cb array 570 * after that we are free to use the skb->cb array
582 * for our information. 571 * for our information.
583 */ 572 */
584 entry->skb = skb; 573 rt2x00queue_create_tx_descriptor(queue->rt2x00dev, skb, &txdesc);
585 rt2x00queue_create_tx_descriptor(entry, &txdesc);
586 574
587 /* 575 /*
588 * All information is retrieved from the skb->cb array, 576 * All information is retrieved from the skb->cb array,
@@ -594,7 +582,6 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
594 rate_flags = tx_info->control.rates[0].flags; 582 rate_flags = tx_info->control.rates[0].flags;
595 skbdesc = get_skb_frame_desc(skb); 583 skbdesc = get_skb_frame_desc(skb);
596 memset(skbdesc, 0, sizeof(*skbdesc)); 584 memset(skbdesc, 0, sizeof(*skbdesc));
597 skbdesc->entry = entry;
598 skbdesc->tx_rate_idx = rate_idx; 585 skbdesc->tx_rate_idx = rate_idx;
599 skbdesc->tx_rate_flags = rate_flags; 586 skbdesc->tx_rate_flags = rate_flags;
600 587
@@ -623,9 +610,33 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
623 * for PCI devices. 610 * for PCI devices.
624 */ 611 */
625 if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags)) 612 if (test_bit(REQUIRE_L2PAD, &queue->rt2x00dev->cap_flags))
626 rt2x00queue_insert_l2pad(entry->skb, txdesc.header_length); 613 rt2x00queue_insert_l2pad(skb, txdesc.header_length);
627 else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags)) 614 else if (test_bit(REQUIRE_DMA, &queue->rt2x00dev->cap_flags))
628 rt2x00queue_align_frame(entry->skb); 615 rt2x00queue_align_frame(skb);
616
617 spin_lock(&queue->tx_lock);
618
619 if (unlikely(rt2x00queue_full(queue))) {
620 ERROR(queue->rt2x00dev,
621 "Dropping frame due to full tx queue %d.\n", queue->qid);
622 ret = -ENOBUFS;
623 goto out;
624 }
625
626 entry = rt2x00queue_get_entry(queue, Q_INDEX);
627
628 if (unlikely(test_and_set_bit(ENTRY_OWNER_DEVICE_DATA,
629 &entry->flags))) {
630 ERROR(queue->rt2x00dev,
631 "Arrived at non-free entry in the non-full queue %d.\n"
632 "Please file bug report to %s.\n",
633 queue->qid, DRV_PROJECT);
634 ret = -EINVAL;
635 goto out;
636 }
637
638 skbdesc->entry = entry;
639 entry->skb = skb;
629 640
630 /* 641 /*
631 * It could be possible that the queue was corrupted and this 642 * It could be possible that the queue was corrupted and this
@@ -635,7 +646,8 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
635 if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) { 646 if (unlikely(rt2x00queue_write_tx_data(entry, &txdesc))) {
636 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); 647 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
637 entry->skb = NULL; 648 entry->skb = NULL;
638 return -EIO; 649 ret = -EIO;
650 goto out;
639 } 651 }
640 652
641 set_bit(ENTRY_DATA_PENDING, &entry->flags); 653 set_bit(ENTRY_DATA_PENDING, &entry->flags);
@@ -644,7 +656,9 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
644 rt2x00queue_write_tx_descriptor(entry, &txdesc); 656 rt2x00queue_write_tx_descriptor(entry, &txdesc);
645 rt2x00queue_kick_tx_queue(queue, &txdesc); 657 rt2x00queue_kick_tx_queue(queue, &txdesc);
646 658
647 return 0; 659out:
660 spin_unlock(&queue->tx_lock);
661 return ret;
648} 662}
649 663
650int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev, 664int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
@@ -698,7 +712,7 @@ int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev,
698 * after that we are free to use the skb->cb array 712 * after that we are free to use the skb->cb array
699 * for our information. 713 * for our information.
700 */ 714 */
701 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc); 715 rt2x00queue_create_tx_descriptor(rt2x00dev, intf->beacon->skb, &txdesc);
702 716
703 /* 717 /*
704 * Fill in skb descriptor 718 * Fill in skb descriptor
@@ -1185,6 +1199,7 @@ static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
1185 struct data_queue *queue, enum data_queue_qid qid) 1199 struct data_queue *queue, enum data_queue_qid qid)
1186{ 1200{
1187 mutex_init(&queue->status_lock); 1201 mutex_init(&queue->status_lock);
1202 spin_lock_init(&queue->tx_lock);
1188 spin_lock_init(&queue->index_lock); 1203 spin_lock_init(&queue->index_lock);
1189 1204
1190 queue->rt2x00dev = rt2x00dev; 1205 queue->rt2x00dev = rt2x00dev;
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index 167d45873dca..f2100f4ddcff 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -54,7 +54,7 @@
54 * @QID_RX: RX queue 54 * @QID_RX: RX queue
55 * @QID_OTHER: None of the above (don't use, only present for completeness) 55 * @QID_OTHER: None of the above (don't use, only present for completeness)
56 * @QID_BEACON: Beacon queue (value unspecified, don't send it to device) 56 * @QID_BEACON: Beacon queue (value unspecified, don't send it to device)
57 * @QID_ATIM: Atim queue (value unspeficied, don't send it to device) 57 * @QID_ATIM: Atim queue (value unspecified, don't send it to device)
58 */ 58 */
59enum data_queue_qid { 59enum data_queue_qid {
60 QID_AC_VO = 0, 60 QID_AC_VO = 0,
@@ -432,6 +432,7 @@ enum data_queue_flags {
432 * @flags: Entry flags, see &enum queue_entry_flags. 432 * @flags: Entry flags, see &enum queue_entry_flags.
433 * @status_lock: The mutex for protecting the start/stop/flush 433 * @status_lock: The mutex for protecting the start/stop/flush
434 * handling on this queue. 434 * handling on this queue.
435 * @tx_lock: Spinlock to serialize tx operations on this queue.
435 * @index_lock: Spinlock to protect index handling. Whenever @index, @index_done or 436 * @index_lock: Spinlock to protect index handling. Whenever @index, @index_done or
436 * @index_crypt needs to be changed this lock should be grabbed to prevent 437 * @index_crypt needs to be changed this lock should be grabbed to prevent
437 * index corruption due to concurrency. 438 * index corruption due to concurrency.
@@ -458,6 +459,7 @@ struct data_queue {
458 unsigned long flags; 459 unsigned long flags;
459 460
460 struct mutex status_lock; 461 struct mutex status_lock;
462 spinlock_t tx_lock;
461 spinlock_t index_lock; 463 spinlock_t index_lock;
462 464
463 unsigned int count; 465 unsigned int count;
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index 8f90f6268077..b6b4542c2460 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -802,6 +802,7 @@ int rt2x00usb_probe(struct usb_interface *usb_intf,
802 int retval; 802 int retval;
803 803
804 usb_dev = usb_get_dev(usb_dev); 804 usb_dev = usb_get_dev(usb_dev);
805 usb_reset_device(usb_dev);
805 806
806 hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw); 807 hw = ieee80211_alloc_hw(sizeof(struct rt2x00_dev), ops->hw);
807 if (!hw) { 808 if (!hw) {
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 9d35ec16a3a5..53110b83bf6e 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -2982,6 +2982,7 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
2982 .set_antenna = rt2x00mac_set_antenna, 2982 .set_antenna = rt2x00mac_set_antenna,
2983 .get_antenna = rt2x00mac_get_antenna, 2983 .get_antenna = rt2x00mac_get_antenna,
2984 .get_ringparam = rt2x00mac_get_ringparam, 2984 .get_ringparam = rt2x00mac_get_ringparam,
2985 .tx_frames_pending = rt2x00mac_tx_frames_pending,
2985}; 2986};
2986 2987
2987static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { 2988static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index ad20953cbf05..6a93939f44e8 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -2314,6 +2314,7 @@ static const struct ieee80211_ops rt73usb_mac80211_ops = {
2314 .set_antenna = rt2x00mac_set_antenna, 2314 .set_antenna = rt2x00mac_set_antenna,
2315 .get_antenna = rt2x00mac_get_antenna, 2315 .get_antenna = rt2x00mac_get_antenna,
2316 .get_ringparam = rt2x00mac_get_ringparam, 2316 .get_ringparam = rt2x00mac_get_ringparam,
2317 .tx_frames_pending = rt2x00mac_tx_frames_pending,
2317}; 2318};
2318 2319
2319static const struct rt2x00lib_ops rt73usb_rt2x00_ops = { 2320static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
diff --git a/drivers/net/wireless/rtl818x/rtl8180/dev.c b/drivers/net/wireless/rtl818x/rtl8180/dev.c
index 80db5cabc9b9..66b29dc07cc3 100644
--- a/drivers/net/wireless/rtl818x/rtl8180/dev.c
+++ b/drivers/net/wireless/rtl818x/rtl8180/dev.c
@@ -16,6 +16,7 @@
16 */ 16 */
17 17
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/interrupt.h>
19#include <linux/pci.h> 20#include <linux/pci.h>
20#include <linux/slab.h> 21#include <linux/slab.h>
21#include <linux/delay.h> 22#include <linux/delay.h>
diff --git a/drivers/net/wireless/rtlwifi/Kconfig b/drivers/net/wireless/rtlwifi/Kconfig
index 5aee8b22d74e..45e14760c16e 100644
--- a/drivers/net/wireless/rtlwifi/Kconfig
+++ b/drivers/net/wireless/rtlwifi/Kconfig
@@ -21,6 +21,17 @@ config RTL8192SE
21 21
22 If you choose to build it as a module, it will be called rtl8192se 22 If you choose to build it as a module, it will be called rtl8192se
23 23
24config RTL8192DE
25 tristate "Realtek RTL8192DE/RTL8188DE PCIe Wireless Network Adapter"
26 depends on MAC80211 && EXPERIMENTAL
27 select FW_LOADER
28 select RTLWIFI
29 ---help---
30 This is the driver for Realtek RTL8192DE/RTL8188DE 802.11n PCIe
31 wireless network adapters.
32
33 If you choose to build it as a module, it will be called rtl8192de
34
24config RTL8192CU 35config RTL8192CU
25 tristate "Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter" 36 tristate "Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter"
26 depends on MAC80211 && USB && EXPERIMENTAL 37 depends on MAC80211 && USB && EXPERIMENTAL
@@ -35,10 +46,10 @@ config RTL8192CU
35 46
36config RTLWIFI 47config RTLWIFI
37 tristate 48 tristate
38 depends on RTL8192CE || RTL8192CU || RTL8192SE 49 depends on RTL8192CE || RTL8192CU || RTL8192SE || RTL8192DE
39 default m 50 default m
40 51
41config RTL8192C_COMMON 52config RTL8192C_COMMON
42 tristate 53 tristate
43 depends on RTL8192CE || RTL8192CU || RTL8192SE 54 depends on RTL8192CE || RTL8192CU
44 default m 55 default m
diff --git a/drivers/net/wireless/rtlwifi/Makefile b/drivers/net/wireless/rtlwifi/Makefile
index 7acce83c3785..97935c565bab 100644
--- a/drivers/net/wireless/rtlwifi/Makefile
+++ b/drivers/net/wireless/rtlwifi/Makefile
@@ -23,5 +23,6 @@ obj-$(CONFIG_RTL8192C_COMMON) += rtl8192c/
23obj-$(CONFIG_RTL8192CE) += rtl8192ce/ 23obj-$(CONFIG_RTL8192CE) += rtl8192ce/
24obj-$(CONFIG_RTL8192CU) += rtl8192cu/ 24obj-$(CONFIG_RTL8192CU) += rtl8192cu/
25obj-$(CONFIG_RTL8192SE) += rtl8192se/ 25obj-$(CONFIG_RTL8192SE) += rtl8192se/
26obj-$(CONFIG_RTL8192DE) += rtl8192de/
26 27
27ccflags-y += -D__CHECK_ENDIAN__ 28ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/base.c b/drivers/net/wireless/rtlwifi/base.c
index ccb6da38fe22..0b598db38da9 100644
--- a/drivers/net/wireless/rtlwifi/base.c
+++ b/drivers/net/wireless/rtlwifi/base.c
@@ -27,6 +27,8 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include <linux/ip.h> 32#include <linux/ip.h>
31#include "wifi.h" 33#include "wifi.h"
32#include "rc.h" 34#include "rc.h"
@@ -397,8 +399,8 @@ void rtl_init_rfkill(struct ieee80211_hw *hw)
397 radio_state = rtlpriv->cfg->ops->radio_onoff_checking(hw, &valid); 399 radio_state = rtlpriv->cfg->ops->radio_onoff_checking(hw, &valid);
398 400
399 if (valid) { 401 if (valid) {
400 printk(KERN_INFO "rtlwifi: wireless switch is %s\n", 402 pr_info("wireless switch is %s\n",
401 rtlpriv->rfkill.rfkill_state ? "on" : "off"); 403 rtlpriv->rfkill.rfkill_state ? "on" : "off");
402 404
403 rtlpriv->rfkill.rfkill_state = radio_state; 405 rtlpriv->rfkill.rfkill_state = radio_state;
404 406
@@ -523,7 +525,7 @@ static void _rtl_query_shortgi(struct ieee80211_hw *hw,
523 mac->opmode == NL80211_IFTYPE_ADHOC) 525 mac->opmode == NL80211_IFTYPE_ADHOC)
524 bw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40; 526 bw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
525 527
526 if ((bw_40 == true) && sgi_40) 528 if (bw_40 && sgi_40)
527 tcb_desc->use_shortgi = true; 529 tcb_desc->use_shortgi = true;
528 else if ((bw_40 == false) && sgi_20) 530 else if ((bw_40 == false) && sgi_20)
529 tcb_desc->use_shortgi = true; 531 tcb_desc->use_shortgi = true;
@@ -756,18 +758,17 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
756 return false; 758 return false;
757 759
758 RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, 760 RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
759 ("%s ACT_ADDBAREQ From :" MAC_FMT "\n", 761 ("%s ACT_ADDBAREQ From :%pM\n",
760 is_tx ? "Tx" : "Rx", MAC_ARG(hdr->addr2))); 762 is_tx ? "Tx" : "Rx", hdr->addr2));
761 break; 763 break;
762 case ACT_ADDBARSP: 764 case ACT_ADDBARSP:
763 RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, 765 RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
764 ("%s ACT_ADDBARSP From :" MAC_FMT "\n", 766 ("%s ACT_ADDBARSP From :%pM\n",
765 is_tx ? "Tx" : "Rx", MAC_ARG(hdr->addr2))); 767 is_tx ? "Tx" : "Rx", hdr->addr2));
766 break; 768 break;
767 case ACT_DELBA: 769 case ACT_DELBA:
768 RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, 770 RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
769 ("ACT_ADDBADEL From :" MAC_FMT "\n", 771 ("ACT_ADDBADEL From :%pM\n", hdr->addr2));
770 MAC_ARG(hdr->addr2)));
771 break; 772 break;
772 } 773 }
773 break; 774 break;
@@ -888,7 +889,6 @@ int rtl_tx_agg_stop(struct ieee80211_hw *hw,
888{ 889{
889 struct rtl_priv *rtlpriv = rtl_priv(hw); 890 struct rtl_priv *rtlpriv = rtl_priv(hw);
890 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 891 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
891 struct rtl_tid_data *tid_data;
892 struct rtl_sta_info *sta_entry = NULL; 892 struct rtl_sta_info *sta_entry = NULL;
893 893
894 if (sta == NULL) 894 if (sta == NULL)
@@ -906,7 +906,6 @@ int rtl_tx_agg_stop(struct ieee80211_hw *hw,
906 return -EINVAL; 906 return -EINVAL;
907 907
908 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 908 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
909 tid_data = &sta_entry->tids[tid];
910 sta_entry->tids[tid].agg.agg_state = RTL_AGG_STOP; 909 sta_entry->tids[tid].agg.agg_state = RTL_AGG_STOP;
911 910
912 ieee80211_stop_tx_ba_cb_irqsafe(mac->vif, sta->addr, tid); 911 ieee80211_stop_tx_ba_cb_irqsafe(mac->vif, sta->addr, tid);
@@ -918,7 +917,6 @@ int rtl_tx_agg_oper(struct ieee80211_hw *hw,
918 struct ieee80211_sta *sta, u16 tid) 917 struct ieee80211_sta *sta, u16 tid)
919{ 918{
920 struct rtl_priv *rtlpriv = rtl_priv(hw); 919 struct rtl_priv *rtlpriv = rtl_priv(hw);
921 struct rtl_tid_data *tid_data;
922 struct rtl_sta_info *sta_entry = NULL; 920 struct rtl_sta_info *sta_entry = NULL;
923 921
924 if (sta == NULL) 922 if (sta == NULL)
@@ -936,7 +934,6 @@ int rtl_tx_agg_oper(struct ieee80211_hw *hw,
936 return -EINVAL; 934 return -EINVAL;
937 935
938 sta_entry = (struct rtl_sta_info *)sta->drv_priv; 936 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
939 tid_data = &sta_entry->tids[tid];
940 sta_entry->tids[tid].agg.agg_state = RTL_AGG_OPERATIONAL; 937 sta_entry->tids[tid].agg.agg_state = RTL_AGG_OPERATIONAL;
941 938
942 return 0; 939 return 0;
@@ -1406,8 +1403,7 @@ MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
1406static int __init rtl_core_module_init(void) 1403static int __init rtl_core_module_init(void)
1407{ 1404{
1408 if (rtl_rate_control_register()) 1405 if (rtl_rate_control_register())
1409 printk(KERN_ERR "rtlwifi: Unable to register rtl_rc," 1406 pr_err("Unable to register rtl_rc, use default RC !!\n");
1410 "use default RC !!\n");
1411 1407
1412 return 0; 1408 return 0;
1413} 1409}
diff --git a/drivers/net/wireless/rtlwifi/cam.c b/drivers/net/wireless/rtlwifi/cam.c
index 7295af0536b7..7babb6acd957 100644
--- a/drivers/net/wireless/rtlwifi/cam.c
+++ b/drivers/net/wireless/rtlwifi/cam.c
@@ -27,6 +27,8 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include "wifi.h" 32#include "wifi.h"
31#include "cam.h" 33#include "cam.h"
32 34
@@ -131,9 +133,9 @@ u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
131 133
132 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, 134 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
133 ("EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, " 135 ("EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, "
134 "ulUseDK=%x MacAddr" MAC_FMT "\n", 136 "ulUseDK=%x MacAddr %pM\n",
135 ul_entry_idx, ul_key_id, ul_enc_alg, 137 ul_entry_idx, ul_key_id, ul_enc_alg,
136 ul_default_key, MAC_ARG(mac_addr))); 138 ul_default_key, mac_addr));
137 139
138 if (ul_key_id == TOTAL_CAM_ENTRY) { 140 if (ul_key_id == TOTAL_CAM_ENTRY) {
139 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 141 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
@@ -347,7 +349,7 @@ void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr)
347 /* Remove from HW Security CAM */ 349 /* Remove from HW Security CAM */
348 memset(rtlpriv->sec.hwsec_cam_sta_addr[i], 0, ETH_ALEN); 350 memset(rtlpriv->sec.hwsec_cam_sta_addr[i], 0, ETH_ALEN);
349 rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i); 351 rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i);
350 printk(KERN_INFO "&&&&&&&&&del entry %d\n", i); 352 pr_info("&&&&&&&&&del entry %d\n", i);
351 } 353 }
352 } 354 }
353 return; 355 return;
diff --git a/drivers/net/wireless/rtlwifi/core.c b/drivers/net/wireless/rtlwifi/core.c
index d2ec2535aa3c..1bdc1aa305c0 100644
--- a/drivers/net/wireless/rtlwifi/core.c
+++ b/drivers/net/wireless/rtlwifi/core.c
@@ -335,8 +335,8 @@ static int rtl_op_config(struct ieee80211_hw *hw, u32 changed)
335 * before going offchannel, or dis-association or delete BA will 335 * before going offchannel, or dis-association or delete BA will
336 * happen by AP 336 * happen by AP
337 */ 337 */
338 if (rtlpriv->mac80211.offchan_deley) { 338 if (rtlpriv->mac80211.offchan_delay) {
339 rtlpriv->mac80211.offchan_deley = false; 339 rtlpriv->mac80211.offchan_delay = false;
340 mdelay(50); 340 mdelay(50);
341 } 341 }
342 rtlphy->current_channel = wide_chan; 342 rtlphy->current_channel = wide_chan;
@@ -443,11 +443,11 @@ static int rtl_op_sta_add(struct ieee80211_hw *hw,
443 sta_entry->wireless_mode = WIRELESS_MODE_G; 443 sta_entry->wireless_mode = WIRELESS_MODE_G;
444 if (sta->supp_rates[0] <= 0xf) 444 if (sta->supp_rates[0] <= 0xf)
445 sta_entry->wireless_mode = WIRELESS_MODE_B; 445 sta_entry->wireless_mode = WIRELESS_MODE_B;
446 if (sta->ht_cap.ht_supported == true) 446 if (sta->ht_cap.ht_supported)
447 sta_entry->wireless_mode = WIRELESS_MODE_N_24G; 447 sta_entry->wireless_mode = WIRELESS_MODE_N_24G;
448 } else if (rtlhal->current_bandtype == BAND_ON_5G) { 448 } else if (rtlhal->current_bandtype == BAND_ON_5G) {
449 sta_entry->wireless_mode = WIRELESS_MODE_A; 449 sta_entry->wireless_mode = WIRELESS_MODE_A;
450 if (sta->ht_cap.ht_supported == true) 450 if (sta->ht_cap.ht_supported)
451 sta_entry->wireless_mode = WIRELESS_MODE_N_24G; 451 sta_entry->wireless_mode = WIRELESS_MODE_N_24G;
452 } 452 }
453 453
@@ -456,7 +456,7 @@ static int rtl_op_sta_add(struct ieee80211_hw *hw,
456 sta_entry->wireless_mode = WIRELESS_MODE_G; 456 sta_entry->wireless_mode = WIRELESS_MODE_G;
457 457
458 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, 458 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
459 ("Add sta addr is "MAC_FMT"\n", MAC_ARG(sta->addr))); 459 ("Add sta addr is %pM\n", sta->addr));
460 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0); 460 rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0);
461 } 461 }
462 return 0; 462 return 0;
@@ -469,7 +469,7 @@ static int rtl_op_sta_remove(struct ieee80211_hw *hw,
469 struct rtl_sta_info *sta_entry; 469 struct rtl_sta_info *sta_entry;
470 if (sta) { 470 if (sta) {
471 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, 471 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
472 ("Remove sta addr is "MAC_FMT"\n", MAC_ARG(sta->addr))); 472 ("Remove sta addr is %pM\n", sta->addr));
473 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 473 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
474 sta_entry->wireless_mode = 0; 474 sta_entry->wireless_mode = 0;
475 sta_entry->ratr_index = 0; 475 sta_entry->ratr_index = 0;
@@ -650,7 +650,7 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
650 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, 650 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
651 ("BSS_CHANGED_HT\n")); 651 ("BSS_CHANGED_HT\n"));
652 rcu_read_lock(); 652 rcu_read_lock();
653 sta = get_sta(hw, vif, (u8 *)bss_conf->bssid); 653 sta = get_sta(hw, vif, bss_conf->bssid);
654 if (sta) { 654 if (sta) {
655 if (sta->ht_cap.ampdu_density > 655 if (sta->ht_cap.ampdu_density >
656 mac->current_ampdu_density) 656 mac->current_ampdu_density)
@@ -678,14 +678,14 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
678 (u8 *) bss_conf->bssid); 678 (u8 *) bss_conf->bssid);
679 679
680 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, 680 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
681 (MAC_FMT "\n", MAC_ARG(bss_conf->bssid))); 681 ("%pM\n", bss_conf->bssid));
682 682
683 mac->vendor = PEER_UNKNOWN; 683 mac->vendor = PEER_UNKNOWN;
684 memcpy(mac->bssid, bss_conf->bssid, 6); 684 memcpy(mac->bssid, bss_conf->bssid, 6);
685 rtlpriv->cfg->ops->set_network_type(hw, vif->type); 685 rtlpriv->cfg->ops->set_network_type(hw, vif->type);
686 686
687 rcu_read_lock(); 687 rcu_read_lock();
688 sta = get_sta(hw, vif, (u8 *)bss_conf->bssid); 688 sta = get_sta(hw, vif, bss_conf->bssid);
689 if (!sta) { 689 if (!sta) {
690 rcu_read_unlock(); 690 rcu_read_unlock();
691 goto out; 691 goto out;
diff --git a/drivers/net/wireless/rtlwifi/core.h b/drivers/net/wireless/rtlwifi/core.h
index 4b247db2861d..f02824a3b747 100644
--- a/drivers/net/wireless/rtlwifi/core.h
+++ b/drivers/net/wireless/rtlwifi/core.h
@@ -30,6 +30,8 @@
30#ifndef __RTL_CORE_H__ 30#ifndef __RTL_CORE_H__
31#define __RTL_CORE_H__ 31#define __RTL_CORE_H__
32 32
33#include <net/mac80211.h>
34
33#define RTL_SUPPORTED_FILTERS \ 35#define RTL_SUPPORTED_FILTERS \
34 (FIF_PROMISC_IN_BSS | \ 36 (FIF_PROMISC_IN_BSS | \
35 FIF_ALLMULTI | FIF_CONTROL | \ 37 FIF_ALLMULTI | FIF_CONTROL | \
diff --git a/drivers/net/wireless/rtlwifi/debug.h b/drivers/net/wireless/rtlwifi/debug.h
index e4aa8687408c..160dd0685213 100644
--- a/drivers/net/wireless/rtlwifi/debug.h
+++ b/drivers/net/wireless/rtlwifi/debug.h
@@ -204,10 +204,5 @@ enum dbgp_flag_e {
204 } \ 204 } \
205 } while (0); 205 } while (0);
206 206
207#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
208#define MAC_ARG(x) \
209 ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2],\
210 ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
211
212void rtl_dbgp_flag_init(struct ieee80211_hw *hw); 207void rtl_dbgp_flag_init(struct ieee80211_hw *hw);
213#endif 208#endif
diff --git a/drivers/net/wireless/rtlwifi/efuse.c b/drivers/net/wireless/rtlwifi/efuse.c
index 50de6f5d8a56..3fc21f60bb04 100644
--- a/drivers/net/wireless/rtlwifi/efuse.c
+++ b/drivers/net/wireless/rtlwifi/efuse.c
@@ -382,7 +382,7 @@ bool efuse_shadow_update_chk(struct ieee80211_hw *hw)
382 } 382 }
383 } 383 }
384 384
385 if (wordchanged == true) 385 if (wordchanged)
386 hdr_num++; 386 hdr_num++;
387 } 387 }
388 388
@@ -453,7 +453,7 @@ bool efuse_shadow_update(struct ieee80211_hw *hw)
453 base = offset * 8; 453 base = offset * 8;
454 454
455 for (i = 0; i < 8; i++) { 455 for (i = 0; i < 8; i++) {
456 if (first_pg == true) { 456 if (first_pg) {
457 457
458 word_en &= ~(BIT(i / 2)); 458 word_en &= ~(BIT(i / 2));
459 459
@@ -505,7 +505,7 @@ void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw)
505 struct rtl_priv *rtlpriv = rtl_priv(hw); 505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); 506 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
507 507
508 if (rtlefuse->autoload_failflag == true) 508 if (rtlefuse->autoload_failflag)
509 memset(&rtlefuse->efuse_map[EFUSE_INIT_MAP][0], 0xFF, 509 memset(&rtlefuse->efuse_map[EFUSE_INIT_MAP][0], 0xFF,
510 rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]); 510 rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
511 else 511 else
@@ -690,7 +690,7 @@ static void efuse_read_data_case1(struct ieee80211_hw *hw, u16 *efuse_addr,
690 } 690 }
691 } 691 }
692 692
693 if (dataempty == true) { 693 if (dataempty) {
694 *readstate = PG_STATE_DATA; 694 *readstate = PG_STATE_DATA;
695 } else { 695 } else {
696 *efuse_addr = *efuse_addr + (word_cnts * 2) + 1; 696 *efuse_addr = *efuse_addr + (word_cnts * 2) + 1;
@@ -925,7 +925,7 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw,
925 struct rtl_priv *rtlpriv = rtl_priv(hw); 925 struct rtl_priv *rtlpriv = rtl_priv(hw);
926 struct pgpkt_struct target_pkt; 926 struct pgpkt_struct target_pkt;
927 u8 write_state = PG_STATE_HEADER; 927 u8 write_state = PG_STATE_HEADER;
928 int continual = true, dataempty = true, result = true; 928 int continual = true, result = true;
929 u16 efuse_addr = 0; 929 u16 efuse_addr = 0;
930 u8 efuse_data; 930 u8 efuse_data;
931 u8 target_word_cnts = 0; 931 u8 target_word_cnts = 0;
@@ -953,7 +953,6 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw,
953 (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES))) { 953 (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES))) {
954 954
955 if (write_state == PG_STATE_HEADER) { 955 if (write_state == PG_STATE_HEADER) {
956 dataempty = true;
957 badworden = 0x0F; 956 badworden = 0x0F;
958 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, 957 RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
959 ("efuse PG_STATE_HEADER\n")); 958 ("efuse PG_STATE_HEADER\n"));
@@ -1176,13 +1175,12 @@ static u16 efuse_get_current_size(struct ieee80211_hw *hw)
1176{ 1175{
1177 int continual = true; 1176 int continual = true;
1178 u16 efuse_addr = 0; 1177 u16 efuse_addr = 0;
1179 u8 hoffset, hworden; 1178 u8 hworden;
1180 u8 efuse_data, word_cnts; 1179 u8 efuse_data, word_cnts;
1181 1180
1182 while (continual && efuse_one_byte_read(hw, efuse_addr, &efuse_data) 1181 while (continual && efuse_one_byte_read(hw, efuse_addr, &efuse_data)
1183 && (efuse_addr < EFUSE_MAX_SIZE)) { 1182 && (efuse_addr < EFUSE_MAX_SIZE)) {
1184 if (efuse_data != 0xFF) { 1183 if (efuse_data != 0xFF) {
1185 hoffset = (efuse_data >> 4) & 0x0F;
1186 hworden = efuse_data & 0x0F; 1184 hworden = efuse_data & 0x0F;
1187 word_cnts = efuse_calculate_word_cnts(hworden); 1185 word_cnts = efuse_calculate_word_cnts(hworden);
1188 efuse_addr = efuse_addr + (word_cnts * 2) + 1; 1186 efuse_addr = efuse_addr + (word_cnts * 2) + 1;
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 254b64ba4bf6..5efd57833489 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -35,10 +35,10 @@
35#include "efuse.h" 35#include "efuse.h"
36 36
37static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { 37static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
38 INTEL_VENDOR_ID, 38 PCI_VENDOR_ID_INTEL,
39 ATI_VENDOR_ID, 39 PCI_VENDOR_ID_ATI,
40 AMD_VENDOR_ID, 40 PCI_VENDOR_ID_AMD,
41 SIS_VENDOR_ID 41 PCI_VENDOR_ID_SI
42}; 42};
43 43
44static const u8 ac_to_hwq[] = { 44static const u8 ac_to_hwq[] = {
@@ -390,7 +390,7 @@ static void rtl_pci_parse_configuration(struct pci_dev *pdev,
390 u8 linkctrl_reg; 390 u8 linkctrl_reg;
391 391
392 /*Link Control Register */ 392 /*Link Control Register */
393 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 393 pos = pci_pcie_cap(pdev);
394 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg); 394 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
395 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg; 395 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
396 396
@@ -581,7 +581,7 @@ static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
581 fc = rtl_get_fc(skb); 581 fc = rtl_get_fc(skb);
582 if (ieee80211_is_nullfunc(fc)) { 582 if (ieee80211_is_nullfunc(fc)) {
583 if (ieee80211_has_pm(fc)) { 583 if (ieee80211_has_pm(fc)) {
584 rtlpriv->mac80211.offchan_deley = true; 584 rtlpriv->mac80211.offchan_delay = true;
585 rtlpriv->psc.state_inap = 1; 585 rtlpriv->psc.state_inap = 1;
586 } else { 586 } else {
587 rtlpriv->psc.state_inap = 0; 587 rtlpriv->psc.state_inap = 0;
@@ -622,10 +622,60 @@ tx_status_ok:
622 if (((rtlpriv->link_info.num_rx_inperiod + 622 if (((rtlpriv->link_info.num_rx_inperiod +
623 rtlpriv->link_info.num_tx_inperiod) > 8) || 623 rtlpriv->link_info.num_tx_inperiod) > 8) ||
624 (rtlpriv->link_info.num_rx_inperiod > 2)) { 624 (rtlpriv->link_info.num_rx_inperiod > 2)) {
625 rtl_lps_leave(hw); 625 tasklet_schedule(&rtlpriv->works.ips_leave_tasklet);
626 } 626 }
627} 627}
628 628
629static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
630 struct ieee80211_rx_status rx_status)
631{
632 struct rtl_priv *rtlpriv = rtl_priv(hw);
633 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
634 __le16 fc = rtl_get_fc(skb);
635 bool unicast = false;
636 struct sk_buff *uskb = NULL;
637 u8 *pdata;
638
639
640 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
641
642 if (is_broadcast_ether_addr(hdr->addr1)) {
643 ;/*TODO*/
644 } else if (is_multicast_ether_addr(hdr->addr1)) {
645 ;/*TODO*/
646 } else {
647 unicast = true;
648 rtlpriv->stats.rxbytesunicast += skb->len;
649 }
650
651 rtl_is_special_data(hw, skb, false);
652
653 if (ieee80211_is_data(fc)) {
654 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
655
656 if (unicast)
657 rtlpriv->link_info.num_rx_inperiod++;
658 }
659
660 /* for sw lps */
661 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
662 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
663 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
664 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
665 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
666 return;
667
668 if (unlikely(!rtl_action_proc(hw, skb, false)))
669 return;
670
671 uskb = dev_alloc_skb(skb->len + 128);
672 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
673 pdata = (u8 *)skb_put(uskb, skb->len);
674 memcpy(pdata, skb->data, skb->len);
675
676 ieee80211_rx_irqsafe(hw, uskb);
677}
678
629static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) 679static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
630{ 680{
631 struct rtl_priv *rtlpriv = rtl_priv(hw); 681 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -637,185 +687,112 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
637 u8 own; 687 u8 own;
638 u8 tmp_one; 688 u8 tmp_one;
639 u32 bufferaddress; 689 u32 bufferaddress;
640 bool unicast = false;
641 690
642 struct rtl_stats stats = { 691 struct rtl_stats stats = {
643 .signal = 0, 692 .signal = 0,
644 .noise = -98, 693 .noise = -98,
645 .rate = 0, 694 .rate = 0,
646 }; 695 };
696 int index = rtlpci->rx_ring[rx_queue_idx].idx;
647 697
648 /*RX NORMAL PKT */ 698 /*RX NORMAL PKT */
649 while (count--) { 699 while (count--) {
650 /*rx descriptor */ 700 /*rx descriptor */
651 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[ 701 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
652 rtlpci->rx_ring[rx_queue_idx].idx]; 702 index];
653 /*rx pkt */ 703 /*rx pkt */
654 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[ 704 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
655 rtlpci->rx_ring[rx_queue_idx].idx]; 705 index];
706 struct sk_buff *new_skb = NULL;
656 707
657 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc, 708 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
658 false, HW_DESC_OWN); 709 false, HW_DESC_OWN);
659 710
660 if (own) { 711 /*wait data to be filled by hardware */
661 /*wait data to be filled by hardware */ 712 if (own)
662 return; 713 break;
663 } else {
664 struct ieee80211_hdr *hdr;
665 __le16 fc;
666 struct sk_buff *new_skb = NULL;
667
668 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
669 &rx_status,
670 (u8 *) pdesc, skb);
671
672 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
673 if (unlikely(!new_skb)) {
674 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
675 DBG_DMESG,
676 ("can't alloc skb for rx\n"));
677 goto done;
678 }
679 714
680 pci_unmap_single(rtlpci->pdev, 715 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
681 *((dma_addr_t *) skb->cb), 716 &rx_status,
682 rtlpci->rxbuffersize, 717 (u8 *) pdesc, skb);
683 PCI_DMA_FROMDEVICE);
684 718
685 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, 719 if (stats.crc || stats.hwerror)
686 false, 720 goto done;
687 HW_DESC_RXPKT_LEN));
688 skb_reserve(skb,
689 stats.rx_drvinfo_size + stats.rx_bufshift);
690 721
691 /* 722 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
692 *NOTICE This can not be use for mac80211, 723 if (unlikely(!new_skb)) {
693 *this is done in mac80211 code, 724 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
694 *if you done here sec DHCP will fail 725 DBG_DMESG,
695 *skb_trim(skb, skb->len - 4); 726 ("can't alloc skb for rx\n"));
696 */ 727 goto done;
728 }
697 729
698 hdr = rtl_get_hdr(skb); 730 pci_unmap_single(rtlpci->pdev,
699 fc = rtl_get_fc(skb); 731 *((dma_addr_t *) skb->cb),
700 732 rtlpci->rxbuffersize,
701 if (!stats.crc && !stats.hwerror) { 733 PCI_DMA_FROMDEVICE);
702 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
703 sizeof(rx_status));
704
705 if (is_broadcast_ether_addr(hdr->addr1)) {
706 ;/*TODO*/
707 } else if (is_multicast_ether_addr(hdr->addr1)) {
708 ;/*TODO*/
709 } else {
710 unicast = true;
711 rtlpriv->stats.rxbytesunicast +=
712 skb->len;
713 }
714
715 rtl_is_special_data(hw, skb, false);
716
717 if (ieee80211_is_data(fc)) {
718 rtlpriv->cfg->ops->led_control(hw,
719 LED_CTL_RX);
720
721 if (unicast)
722 rtlpriv->link_info.
723 num_rx_inperiod++;
724 }
725
726 /* for sw lps */
727 rtl_swlps_beacon(hw, (void *)skb->data,
728 skb->len);
729 rtl_recognize_peer(hw, (void *)skb->data,
730 skb->len);
731 if ((rtlpriv->mac80211.opmode ==
732 NL80211_IFTYPE_AP) &&
733 (rtlpriv->rtlhal.current_bandtype ==
734 BAND_ON_2_4G) &&
735 (ieee80211_is_beacon(fc) ||
736 ieee80211_is_probe_resp(fc))) {
737 dev_kfree_skb_any(skb);
738 } else {
739 if (unlikely(!rtl_action_proc(hw, skb,
740 false))) {
741 dev_kfree_skb_any(skb);
742 } else {
743 struct sk_buff *uskb = NULL;
744 u8 *pdata;
745 uskb = dev_alloc_skb(skb->len
746 + 128);
747 memcpy(IEEE80211_SKB_RXCB(uskb),
748 &rx_status,
749 sizeof(rx_status));
750 pdata = (u8 *)skb_put(uskb,
751 skb->len);
752 memcpy(pdata, skb->data,
753 skb->len);
754 dev_kfree_skb_any(skb);
755
756 ieee80211_rx_irqsafe(hw, uskb);
757 }
758 }
759 } else {
760 dev_kfree_skb_any(skb);
761 }
762 734
763 if (((rtlpriv->link_info.num_rx_inperiod + 735 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
764 rtlpriv->link_info.num_tx_inperiod) > 8) || 736 HW_DESC_RXPKT_LEN));
765 (rtlpriv->link_info.num_rx_inperiod > 2)) { 737 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
766 rtl_lps_leave(hw);
767 }
768 738
769 skb = new_skb; 739 /*
740 * NOTICE This can not be use for mac80211,
741 * this is done in mac80211 code,
742 * if you done here sec DHCP will fail
743 * skb_trim(skb, skb->len - 4);
744 */
770 745
771 rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci-> 746 _rtl_receive_one(hw, skb, rx_status);
772 rx_ring 747
773 [rx_queue_idx]. 748 if (((rtlpriv->link_info.num_rx_inperiod +
774 idx] = skb; 749 rtlpriv->link_info.num_tx_inperiod) > 8) ||
775 *((dma_addr_t *) skb->cb) = 750 (rtlpriv->link_info.num_rx_inperiod > 2)) {
751 tasklet_schedule(&rtlpriv->works.ips_leave_tasklet);
752 }
753
754 dev_kfree_skb_any(skb);
755 skb = new_skb;
756
757 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
758 *((dma_addr_t *) skb->cb) =
776 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), 759 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
777 rtlpci->rxbuffersize, 760 rtlpci->rxbuffersize,
778 PCI_DMA_FROMDEVICE); 761 PCI_DMA_FROMDEVICE);
779 762
780 }
781done: 763done:
782 bufferaddress = (*((dma_addr_t *)skb->cb)); 764 bufferaddress = (*((dma_addr_t *)skb->cb));
783 tmp_one = 1; 765 tmp_one = 1;
784 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false, 766 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
785 HW_DESC_RXBUFF_ADDR, 767 HW_DESC_RXBUFF_ADDR,
786 (u8 *)&bufferaddress); 768 (u8 *)&bufferaddress);
787 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
788 (u8 *)&tmp_one);
789 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, 769 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
790 HW_DESC_RXPKT_LEN, 770 HW_DESC_RXPKT_LEN,
791 (u8 *)&rtlpci->rxbuffersize); 771 (u8 *)&rtlpci->rxbuffersize);
792 772
793 if (rtlpci->rx_ring[rx_queue_idx].idx == 773 if (index == rtlpci->rxringcount - 1)
794 rtlpci->rxringcount - 1)
795 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, 774 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
796 HW_DESC_RXERO, 775 HW_DESC_RXERO,
797 (u8 *)&tmp_one); 776 (u8 *)&tmp_one);
798 777
799 rtlpci->rx_ring[rx_queue_idx].idx = 778 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
800 (rtlpci->rx_ring[rx_queue_idx].idx + 1) % 779 (u8 *)&tmp_one);
801 rtlpci->rxringcount; 780
781 index = (index + 1) % rtlpci->rxringcount;
802 } 782 }
803 783
784 rtlpci->rx_ring[rx_queue_idx].idx = index;
804} 785}
805 786
806static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 787static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
807{ 788{
808 struct ieee80211_hw *hw = dev_id; 789 struct ieee80211_hw *hw = dev_id;
809 struct rtl_priv *rtlpriv = rtl_priv(hw); 790 struct rtl_priv *rtlpriv = rtl_priv(hw);
810 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
811 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 791 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
812 unsigned long flags; 792 unsigned long flags;
813 u32 inta = 0; 793 u32 inta = 0;
814 u32 intb = 0; 794 u32 intb = 0;
815 795
816 if (rtlpci->irq_enabled == 0)
817 return IRQ_HANDLED;
818
819 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 796 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
820 797
821 /*read ISR: 4/8bytes */ 798 /*read ISR: 4/8bytes */
@@ -938,6 +915,11 @@ static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
938 _rtl_pci_tx_chk_waitq(hw); 915 _rtl_pci_tx_chk_waitq(hw);
939} 916}
940 917
918static void _rtl_pci_ips_leave_tasklet(struct ieee80211_hw *hw)
919{
920 rtl_lps_leave(hw);
921}
922
941static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) 923static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
942{ 924{
943 struct rtl_priv *rtlpriv = rtl_priv(hw); 925 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -1036,6 +1018,9 @@ static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1036 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, 1018 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1037 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, 1019 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1038 (unsigned long)hw); 1020 (unsigned long)hw);
1021 tasklet_init(&rtlpriv->works.ips_leave_tasklet,
1022 (void (*)(unsigned long))_rtl_pci_ips_leave_tasklet,
1023 (unsigned long)hw);
1039} 1024}
1040 1025
1041static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, 1026static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
@@ -1505,6 +1490,7 @@ static void rtl_pci_deinit(struct ieee80211_hw *hw)
1505 1490
1506 synchronize_irq(rtlpci->pdev->irq); 1491 synchronize_irq(rtlpci->pdev->irq);
1507 tasklet_kill(&rtlpriv->works.irq_tasklet); 1492 tasklet_kill(&rtlpriv->works.irq_tasklet);
1493 tasklet_kill(&rtlpriv->works.ips_leave_tasklet);
1508 1494
1509 flush_workqueue(rtlpriv->works.rtl_wq); 1495 flush_workqueue(rtlpriv->works.rtl_wq);
1510 destroy_workqueue(rtlpriv->works.rtl_wq); 1496 destroy_workqueue(rtlpriv->works.rtl_wq);
@@ -1579,6 +1565,7 @@ static void rtl_pci_stop(struct ieee80211_hw *hw)
1579 set_hal_stop(rtlhal); 1565 set_hal_stop(rtlhal);
1580 1566
1581 rtlpriv->cfg->ops->disable_interrupt(hw); 1567 rtlpriv->cfg->ops->disable_interrupt(hw);
1568 tasklet_kill(&rtlpriv->works.ips_leave_tasklet);
1582 1569
1583 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); 1570 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1584 while (ppsc->rfchange_inprogress) { 1571 while (ppsc->rfchange_inprogress) {
diff --git a/drivers/net/wireless/rtlwifi/pci.h b/drivers/net/wireless/rtlwifi/pci.h
index 671b1f5aa0cf..c53c62046747 100644
--- a/drivers/net/wireless/rtlwifi/pci.h
+++ b/drivers/net/wireless/rtlwifi/pci.h
@@ -62,12 +62,6 @@
62 .subdevice = PCI_ANY_ID,\ 62 .subdevice = PCI_ANY_ID,\
63 .driver_data = (kernel_ulong_t)&(cfg) 63 .driver_data = (kernel_ulong_t)&(cfg)
64 64
65#define INTEL_VENDOR_ID 0x8086
66#define SIS_VENDOR_ID 0x1039
67#define ATI_VENDOR_ID 0x1002
68#define ATI_DEVICE_ID 0x7914
69#define AMD_VENDOR_ID 0x1022
70
71#define PCI_MAX_BRIDGE_NUMBER 255 65#define PCI_MAX_BRIDGE_NUMBER 255
72#define PCI_MAX_DEVICES 32 66#define PCI_MAX_DEVICES 32
73#define PCI_MAX_FUNCTION 8 67#define PCI_MAX_FUNCTION 8
@@ -75,11 +69,6 @@
75#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */ 69#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
76#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */ 70#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
77 71
78#define PCI_CLASS_BRIDGE_DEV 0x06
79#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
80#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
81#define PCI_CAP_ID_EXP 0x10
82
83#define U1DONTCARE 0xFF 72#define U1DONTCARE 0xFF
84#define U2DONTCARE 0xFFFF 73#define U2DONTCARE 0xFFFF
85#define U4DONTCARE 0xFFFFFFFF 74#define U4DONTCARE 0xFFFFFFFF
@@ -169,7 +158,6 @@ struct rtl_pci {
169 bool first_init; 158 bool first_init;
170 bool being_init_adapter; 159 bool being_init_adapter;
171 bool init_ready; 160 bool init_ready;
172 bool irq_enabled;
173 161
174 /*Tx */ 162 /*Tx */
175 struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT]; 163 struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
diff --git a/drivers/net/wireless/rtlwifi/ps.c b/drivers/net/wireless/rtlwifi/ps.c
index 39b0297ce925..a693feffbe72 100644
--- a/drivers/net/wireless/rtlwifi/ps.c
+++ b/drivers/net/wireless/rtlwifi/ps.c
@@ -68,6 +68,7 @@ bool rtl_ps_disable_nic(struct ieee80211_hw *hw)
68 68
69 /*<2> Disable Interrupt */ 69 /*<2> Disable Interrupt */
70 rtlpriv->cfg->ops->disable_interrupt(hw); 70 rtlpriv->cfg->ops->disable_interrupt(hw);
71 tasklet_kill(&rtlpriv->works.irq_tasklet);
71 72
72 /*<3> Disable Adapter */ 73 /*<3> Disable Adapter */
73 rtlpriv->cfg->ops->hw_disable(hw); 74 rtlpriv->cfg->ops->hw_disable(hw);
@@ -78,65 +79,18 @@ EXPORT_SYMBOL(rtl_ps_disable_nic);
78 79
79bool rtl_ps_set_rf_state(struct ieee80211_hw *hw, 80bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
80 enum rf_pwrstate state_toset, 81 enum rf_pwrstate state_toset,
81 u32 changesource, bool protect_or_not) 82 u32 changesource)
82{ 83{
83 struct rtl_priv *rtlpriv = rtl_priv(hw); 84 struct rtl_priv *rtlpriv = rtl_priv(hw);
84 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 85 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
85 enum rf_pwrstate rtstate;
86 bool actionallowed = false; 86 bool actionallowed = false;
87 u16 rfwait_cnt = 0;
88 unsigned long flag;
89
90 /*protect_or_not = true; */
91
92 if (protect_or_not)
93 goto no_protect;
94
95 /*
96 *Only one thread can change
97 *the RF state at one time, and others
98 *should wait to be executed.
99 */
100 while (true) {
101 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
102 if (ppsc->rfchange_inprogress) {
103 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock,
104 flag);
105
106 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
107 ("RF Change in progress!"
108 "Wait to set..state_toset(%d).\n",
109 state_toset));
110
111 /* Set RF after the previous action is done. */
112 while (ppsc->rfchange_inprogress) {
113 rfwait_cnt++;
114 mdelay(1);
115
116 /*
117 *Wait too long, return false to avoid
118 *to be stuck here.
119 */
120 if (rfwait_cnt > 100)
121 return false;
122 }
123 } else {
124 ppsc->rfchange_inprogress = true;
125 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock,
126 flag);
127 break;
128 }
129 }
130
131no_protect:
132 rtstate = ppsc->rfpwr_state;
133 87
134 switch (state_toset) { 88 switch (state_toset) {
135 case ERFON: 89 case ERFON:
136 ppsc->rfoff_reason &= (~changesource); 90 ppsc->rfoff_reason &= (~changesource);
137 91
138 if ((changesource == RF_CHANGE_BY_HW) && 92 if ((changesource == RF_CHANGE_BY_HW) &&
139 (ppsc->hwradiooff == true)) { 93 (ppsc->hwradiooff)) {
140 ppsc->hwradiooff = false; 94 ppsc->hwradiooff = false;
141 } 95 }
142 96
@@ -172,12 +126,6 @@ no_protect:
172 if (actionallowed) 126 if (actionallowed)
173 rtlpriv->cfg->ops->set_rf_power_state(hw, state_toset); 127 rtlpriv->cfg->ops->set_rf_power_state(hw, state_toset);
174 128
175 if (!protect_or_not) {
176 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
177 ppsc->rfchange_inprogress = false;
178 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
179 }
180
181 return actionallowed; 129 return actionallowed;
182} 130}
183EXPORT_SYMBOL(rtl_ps_set_rf_state); 131EXPORT_SYMBOL(rtl_ps_set_rf_state);
@@ -200,8 +148,7 @@ static void _rtl_ps_inactive_ps(struct ieee80211_hw *hw)
200 } 148 }
201 } 149 }
202 150
203 rtl_ps_set_rf_state(hw, ppsc->inactive_pwrstate, 151 rtl_ps_set_rf_state(hw, ppsc->inactive_pwrstate, RF_CHANGE_BY_IPS);
204 RF_CHANGE_BY_IPS, false);
205 152
206 if (ppsc->inactive_pwrstate == ERFOFF && 153 if (ppsc->inactive_pwrstate == ERFOFF &&
207 rtlhal->interface == INTF_PCI) { 154 rtlhal->interface == INTF_PCI) {
@@ -289,12 +236,11 @@ void rtl_ips_nic_on(struct ieee80211_hw *hw)
289 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 236 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
290 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 237 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
291 enum rf_pwrstate rtstate; 238 enum rf_pwrstate rtstate;
292 unsigned long flags;
293 239
294 if (mac->opmode != NL80211_IFTYPE_STATION) 240 if (mac->opmode != NL80211_IFTYPE_STATION)
295 return; 241 return;
296 242
297 spin_lock_irqsave(&rtlpriv->locks.ips_lock, flags); 243 spin_lock(&rtlpriv->locks.ips_lock);
298 244
299 if (ppsc->inactiveps) { 245 if (ppsc->inactiveps) {
300 rtstate = ppsc->rfpwr_state; 246 rtstate = ppsc->rfpwr_state;
@@ -310,7 +256,7 @@ void rtl_ips_nic_on(struct ieee80211_hw *hw)
310 } 256 }
311 } 257 }
312 258
313 spin_unlock_irqrestore(&rtlpriv->locks.ips_lock, flags); 259 spin_unlock(&rtlpriv->locks.ips_lock);
314} 260}
315 261
316/*for FW LPS*/ 262/*for FW LPS*/
@@ -428,7 +374,6 @@ void rtl_lps_enter(struct ieee80211_hw *hw)
428 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 374 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
429 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 375 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
430 struct rtl_priv *rtlpriv = rtl_priv(hw); 376 struct rtl_priv *rtlpriv = rtl_priv(hw);
431 unsigned long flag;
432 377
433 if (!ppsc->fwctrl_lps) 378 if (!ppsc->fwctrl_lps)
434 return; 379 return;
@@ -449,7 +394,7 @@ void rtl_lps_enter(struct ieee80211_hw *hw)
449 if (mac->link_state != MAC80211_LINKED) 394 if (mac->link_state != MAC80211_LINKED)
450 return; 395 return;
451 396
452 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag); 397 spin_lock(&rtlpriv->locks.lps_lock);
453 398
454 /* Idle for a while if we connect to AP a while ago. */ 399 /* Idle for a while if we connect to AP a while ago. */
455 if (mac->cnt_after_linked >= 2) { 400 if (mac->cnt_after_linked >= 2) {
@@ -461,7 +406,7 @@ void rtl_lps_enter(struct ieee80211_hw *hw)
461 } 406 }
462 } 407 }
463 408
464 spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag); 409 spin_unlock(&rtlpriv->locks.lps_lock);
465} 410}
466 411
467/*Leave the leisure power save mode.*/ 412/*Leave the leisure power save mode.*/
@@ -470,9 +415,8 @@ void rtl_lps_leave(struct ieee80211_hw *hw)
470 struct rtl_priv *rtlpriv = rtl_priv(hw); 415 struct rtl_priv *rtlpriv = rtl_priv(hw);
471 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 416 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
472 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 417 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
473 unsigned long flag;
474 418
475 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag); 419 spin_lock(&rtlpriv->locks.lps_lock);
476 420
477 if (ppsc->fwctrl_lps) { 421 if (ppsc->fwctrl_lps) {
478 if (ppsc->dot11_psmode != EACTIVE) { 422 if (ppsc->dot11_psmode != EACTIVE) {
@@ -493,7 +437,7 @@ void rtl_lps_leave(struct ieee80211_hw *hw)
493 rtl_lps_set_psmode(hw, EACTIVE); 437 rtl_lps_set_psmode(hw, EACTIVE);
494 } 438 }
495 } 439 }
496 spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag); 440 spin_unlock(&rtlpriv->locks.lps_lock);
497} 441}
498 442
499/* For sw LPS*/ 443/* For sw LPS*/
@@ -582,7 +526,6 @@ void rtl_swlps_rf_awake(struct ieee80211_hw *hw)
582 struct rtl_priv *rtlpriv = rtl_priv(hw); 526 struct rtl_priv *rtlpriv = rtl_priv(hw);
583 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 527 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
584 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 528 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
585 unsigned long flag;
586 529
587 if (!rtlpriv->psc.swctrl_lps) 530 if (!rtlpriv->psc.swctrl_lps)
588 return; 531 return;
@@ -595,9 +538,9 @@ void rtl_swlps_rf_awake(struct ieee80211_hw *hw)
595 RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM); 538 RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM);
596 } 539 }
597 540
598 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag); 541 spin_lock(&rtlpriv->locks.lps_lock);
599 rtl_ps_set_rf_state(hw, ERFON, RF_CHANGE_BY_PS, false); 542 rtl_ps_set_rf_state(hw, ERFON, RF_CHANGE_BY_PS);
600 spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag); 543 spin_unlock(&rtlpriv->locks.lps_lock);
601} 544}
602 545
603void rtl_swlps_rfon_wq_callback(void *data) 546void rtl_swlps_rfon_wq_callback(void *data)
@@ -614,7 +557,6 @@ void rtl_swlps_rf_sleep(struct ieee80211_hw *hw)
614 struct rtl_priv *rtlpriv = rtl_priv(hw); 557 struct rtl_priv *rtlpriv = rtl_priv(hw);
615 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 558 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
616 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 559 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
617 unsigned long flag;
618 u8 sleep_intv; 560 u8 sleep_intv;
619 561
620 if (!rtlpriv->psc.sw_ps_enabled) 562 if (!rtlpriv->psc.sw_ps_enabled)
@@ -631,16 +573,9 @@ void rtl_swlps_rf_sleep(struct ieee80211_hw *hw)
631 if (rtlpriv->link_info.busytraffic) 573 if (rtlpriv->link_info.busytraffic)
632 return; 574 return;
633 575
634 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 576 spin_lock(&rtlpriv->locks.lps_lock);
635 if (rtlpriv->psc.rfchange_inprogress) { 577 rtl_ps_set_rf_state(hw, ERFSLEEP, RF_CHANGE_BY_PS);
636 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 578 spin_unlock(&rtlpriv->locks.lps_lock);
637 return;
638 }
639 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
640
641 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
642 rtl_ps_set_rf_state(hw, ERFSLEEP, RF_CHANGE_BY_PS, false);
643 spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
644 579
645 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM && 580 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM &&
646 !RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) { 581 !RT_IN_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM)) {
diff --git a/drivers/net/wireless/rtlwifi/ps.h b/drivers/net/wireless/rtlwifi/ps.h
index e3bf89840370..84628e6041c7 100644
--- a/drivers/net/wireless/rtlwifi/ps.h
+++ b/drivers/net/wireless/rtlwifi/ps.h
@@ -33,8 +33,7 @@
33#define MAX_SW_LPS_SLEEP_INTV 5 33#define MAX_SW_LPS_SLEEP_INTV 5
34 34
35bool rtl_ps_set_rf_state(struct ieee80211_hw *hw, 35bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
36 enum rf_pwrstate state_toset, u32 changesource, 36 enum rf_pwrstate state_toset, u32 changesource);
37 bool protect_or_not);
38bool rtl_ps_enable_nic(struct ieee80211_hw *hw); 37bool rtl_ps_enable_nic(struct ieee80211_hw *hw);
39bool rtl_ps_disable_nic(struct ieee80211_hw *hw); 38bool rtl_ps_disable_nic(struct ieee80211_hw *hw);
40void rtl_ips_nic_off(struct ieee80211_hw *hw); 39void rtl_ips_nic_off(struct ieee80211_hw *hw);
diff --git a/drivers/net/wireless/rtlwifi/rc.c b/drivers/net/wireless/rtlwifi/rc.c
index 30da68a77786..539df66dce0a 100644
--- a/drivers/net/wireless/rtlwifi/rc.c
+++ b/drivers/net/wireless/rtlwifi/rc.c
@@ -200,7 +200,7 @@ static void rtl_tx_status(void *ppriv,
200 if (sta) { 200 if (sta) {
201 /* Check if aggregation has to be enabled for this tid */ 201 /* Check if aggregation has to be enabled for this tid */
202 sta_entry = (struct rtl_sta_info *) sta->drv_priv; 202 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
203 if ((sta->ht_cap.ht_supported == true) && 203 if ((sta->ht_cap.ht_supported) &&
204 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 204 !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
205 if (ieee80211_is_data_qos(fc)) { 205 if (ieee80211_is_data_qos(fc)) {
206 u8 tid = rtl_get_tid(skb); 206 u8 tid = rtl_get_tid(skb);
diff --git a/drivers/net/wireless/rtlwifi/regd.c b/drivers/net/wireless/rtlwifi/regd.c
index 8f6718f163e5..9fedb1f70919 100644
--- a/drivers/net/wireless/rtlwifi/regd.c
+++ b/drivers/net/wireless/rtlwifi/regd.c
@@ -303,22 +303,6 @@ static void _rtl_reg_apply_world_flags(struct wiphy *wiphy,
303 return; 303 return;
304} 304}
305 305
306static void _rtl_dump_channel_map(struct wiphy *wiphy)
307{
308 enum ieee80211_band band;
309 struct ieee80211_supported_band *sband;
310 struct ieee80211_channel *ch;
311 unsigned int i;
312
313 for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
314 if (!wiphy->bands[band])
315 continue;
316 sband = wiphy->bands[band];
317 for (i = 0; i < sband->n_channels; i++)
318 ch = &sband->channels[i];
319 }
320}
321
322static int _rtl_reg_notifier_apply(struct wiphy *wiphy, 306static int _rtl_reg_notifier_apply(struct wiphy *wiphy,
323 struct regulatory_request *request, 307 struct regulatory_request *request,
324 struct rtl_regulatory *reg) 308 struct rtl_regulatory *reg)
@@ -336,8 +320,6 @@ static int _rtl_reg_notifier_apply(struct wiphy *wiphy,
336 break; 320 break;
337 } 321 }
338 322
339 _rtl_dump_channel_map(wiphy);
340
341 return 0; 323 return 0;
342} 324}
343 325
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c b/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c
index 97183829b9be..a00774e7090d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c
@@ -474,7 +474,7 @@ static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
474{ 474{
475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 475 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
476 476
477 if (mac->act_scanning == true) 477 if (mac->act_scanning)
478 return; 478 return;
479 479
480 if (mac->link_state >= MAC80211_LINKED) 480 if (mac->link_state >= MAC80211_LINKED)
@@ -670,7 +670,7 @@ static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
670 u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0; 670 u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0;
671 int i; 671 int i;
672 bool is2t = IS_92C_SERIAL(rtlhal->version); 672 bool is2t = IS_92C_SERIAL(rtlhal->version);
673 u8 txpwr_level[2] = {0, 0}; 673 s8 txpwr_level[2] = {0, 0};
674 u8 ofdm_min_index = 6, rf; 674 u8 ofdm_min_index = 6, rf;
675 675
676 rtlpriv->dm.txpower_trackinginit = true; 676 rtlpriv->dm.txpower_trackinginit = true;
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c b/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c
index 50303e1adff1..49a064bdbce6 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c
@@ -27,6 +27,8 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include <linux/firmware.h> 32#include <linux/firmware.h>
31#include "../wifi.h" 33#include "../wifi.h"
32#include "../pci.h" 34#include "../pci.h"
@@ -224,8 +226,7 @@ int rtl92c_download_fw(struct ieee80211_hw *hw)
224 u32 fwsize; 226 u32 fwsize;
225 enum version_8192c version = rtlhal->version; 227 enum version_8192c version = rtlhal->version;
226 228
227 printk(KERN_INFO "rtl8192c: Loading firmware file %s\n", 229 pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name);
228 rtlpriv->cfg->fw_name);
229 if (!rtlhal->pfirmware) 230 if (!rtlhal->pfirmware)
230 return 1; 231 return 1;
231 232
@@ -546,7 +547,6 @@ static bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw,
546 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 547 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
547 struct rtl8192_tx_ring *ring; 548 struct rtl8192_tx_ring *ring;
548 struct rtl_tx_desc *pdesc; 549 struct rtl_tx_desc *pdesc;
549 u8 own;
550 unsigned long flags; 550 unsigned long flags;
551 struct sk_buff *pskb = NULL; 551 struct sk_buff *pskb = NULL;
552 552
@@ -559,7 +559,6 @@ static bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw,
559 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); 559 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
560 560
561 pdesc = &ring->desc[0]; 561 pdesc = &ring->desc[0];
562 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
563 562
564 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb); 563 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
565 564
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
index d2cc81586a6a..3b11642d3f7d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
@@ -1253,10 +1253,9 @@ static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1253 1253
1254 const u32 retrycount = 2; 1254 const u32 retrycount = 2;
1255 1255
1256 u32 bbvalue;
1257
1258 if (t == 0) { 1256 if (t == 0) {
1259 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD); 1257 /* dummy read */
1258 rtl_get_bbreg(hw, 0x800, MASKDWORD);
1260 1259
1261 _rtl92c_phy_save_adda_registers(hw, adda_reg, 1260 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1262 rtlphy->adda_backup, 16); 1261 rtlphy->adda_backup, 16);
@@ -1762,8 +1761,7 @@ void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1762 long result[4][8]; 1761 long result[4][8];
1763 u8 i, final_candidate; 1762 u8 i, final_candidate;
1764 bool patha_ok, pathb_ok; 1763 bool patha_ok, pathb_ok;
1765 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, 1764 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4, reg_tmp = 0;
1766 reg_ecc, reg_tmp = 0;
1767 bool is12simular, is13simular, is23simular; 1765 bool is12simular, is13simular, is23simular;
1768 bool start_conttx = false, singletone = false; 1766 bool start_conttx = false, singletone = false;
1769 u32 iqk_bb_reg[10] = { 1767 u32 iqk_bb_reg[10] = {
@@ -1841,21 +1839,17 @@ void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1841 reg_e94 = result[i][0]; 1839 reg_e94 = result[i][0];
1842 reg_e9c = result[i][1]; 1840 reg_e9c = result[i][1];
1843 reg_ea4 = result[i][2]; 1841 reg_ea4 = result[i][2];
1844 reg_eac = result[i][3];
1845 reg_eb4 = result[i][4]; 1842 reg_eb4 = result[i][4];
1846 reg_ebc = result[i][5]; 1843 reg_ebc = result[i][5];
1847 reg_ec4 = result[i][6]; 1844 reg_ec4 = result[i][6];
1848 reg_ecc = result[i][7];
1849 } 1845 }
1850 if (final_candidate != 0xff) { 1846 if (final_candidate != 0xff) {
1851 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; 1847 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1852 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1]; 1848 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1853 reg_ea4 = result[final_candidate][2]; 1849 reg_ea4 = result[final_candidate][2];
1854 reg_eac = result[final_candidate][3];
1855 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4]; 1850 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1856 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5]; 1851 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1857 reg_ec4 = result[final_candidate][6]; 1852 reg_ec4 = result[final_candidate][6];
1858 reg_ecc = result[final_candidate][7];
1859 patha_ok = pathb_ok = true; 1853 patha_ok = pathb_ok = true;
1860 } else { 1854 } else {
1861 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; 1855 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
index defb4370cf74..a3deaefa788c 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
@@ -488,7 +488,7 @@ void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
488 case HW_VAR_CORRECT_TSF:{ 488 case HW_VAR_CORRECT_TSF:{
489 u8 btype_ibss = ((u8 *) (val))[0]; 489 u8 btype_ibss = ((u8 *) (val))[0];
490 490
491 if (btype_ibss == true) 491 if (btype_ibss)
492 _rtl92ce_stop_tx_beacon(hw); 492 _rtl92ce_stop_tx_beacon(hw);
493 493
494 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3)); 494 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
@@ -500,7 +500,7 @@ void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
500 500
501 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 501 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
502 502
503 if (btype_ibss == true) 503 if (btype_ibss)
504 _rtl92ce_resume_tx_beacon(hw); 504 _rtl92ce_resume_tx_beacon(hw);
505 505
506 break; 506 break;
@@ -763,11 +763,9 @@ static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
763 struct rtl_priv *rtlpriv = rtl_priv(hw); 763 struct rtl_priv *rtlpriv = rtl_priv(hw);
764 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); 764 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
765 u8 reg_bw_opmode; 765 u8 reg_bw_opmode;
766 u32 reg_ratr, reg_prsr; 766 u32 reg_prsr;
767 767
768 reg_bw_opmode = BW_OPMODE_20MHZ; 768 reg_bw_opmode = BW_OPMODE_20MHZ;
769 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
770 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
771 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 769 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
772 770
773 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8); 771 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
@@ -1123,7 +1121,7 @@ void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1123 if (rtlpriv->psc.rfpwr_state != ERFON) 1121 if (rtlpriv->psc.rfpwr_state != ERFON)
1124 return; 1122 return;
1125 1123
1126 if (check_bssid == true) { 1124 if (check_bssid) {
1127 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN); 1125 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1128 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, 1126 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1129 (u8 *) (&reg_rcr)); 1127 (u8 *) (&reg_rcr));
@@ -1185,7 +1183,6 @@ void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1185 1183
1186 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); 1184 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1187 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); 1185 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1188 rtlpci->irq_enabled = true;
1189} 1186}
1190 1187
1191void rtl92ce_disable_interrupt(struct ieee80211_hw *hw) 1188void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
@@ -1195,7 +1192,7 @@ void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1195 1192
1196 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 1193 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1197 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 1194 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1198 rtlpci->irq_enabled = false; 1195 synchronize_irq(rtlpci->pdev->irq);
1199} 1196}
1200 1197
1201static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw) 1198static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
@@ -1586,7 +1583,7 @@ static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1586 rtlefuse->autoload_failflag = false; 1583 rtlefuse->autoload_failflag = false;
1587 } 1584 }
1588 1585
1589 if (rtlefuse->autoload_failflag == true) 1586 if (rtlefuse->autoload_failflag)
1590 return; 1587 return;
1591 1588
1592 for (i = 0; i < 6; i += 2) { 1589 for (i = 0; i < 6; i += 2) {
@@ -1595,7 +1592,7 @@ static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1595 } 1592 }
1596 1593
1597 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1594 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1598 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr))); 1595 ("%pM\n", rtlefuse->dev_addr));
1599 1596
1600 _rtl92ce_read_txpower_info_from_hwpg(hw, 1597 _rtl92ce_read_txpower_info_from_hwpg(hw,
1601 rtlefuse->autoload_failflag, 1598 rtlefuse->autoload_failflag,
@@ -1969,7 +1966,7 @@ bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1969 struct rtl_priv *rtlpriv = rtl_priv(hw); 1966 struct rtl_priv *rtlpriv = rtl_priv(hw);
1970 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 1967 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1971 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1968 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1972 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 1969 enum rf_pwrstate e_rfpowerstate_toset;
1973 u8 u1tmp; 1970 u8 u1tmp;
1974 bool actuallyset = false; 1971 bool actuallyset = false;
1975 unsigned long flag; 1972 unsigned long flag;
@@ -1989,15 +1986,13 @@ bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
1989 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 1986 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1990 } 1987 }
1991 1988
1992 cur_rfstate = ppsc->rfpwr_state;
1993
1994 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, 1989 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1995 REG_MAC_PINMUX_CFG)&~(BIT(3))); 1990 REG_MAC_PINMUX_CFG)&~(BIT(3)));
1996 1991
1997 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 1992 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1998 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; 1993 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1999 1994
2000 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) { 1995 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2001 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1996 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2002 ("GPIOChangeRF - HW Radio ON, RF ON\n")); 1997 ("GPIOChangeRF - HW Radio ON, RF ON\n"));
2003 1998
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/led.c b/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
index 9dd1ed7b6422..28a1a707d09c 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
@@ -84,7 +84,7 @@ void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
84 break; 84 break;
85 case LED_PIN_LED0: 85 case LED_PIN_LED0:
86 ledcfg &= 0xf0; 86 ledcfg &= 0xf0;
87 if (pcipriv->ledctl.led_opendrain == true) 87 if (pcipriv->ledctl.led_opendrain)
88 rtl_write_byte(rtlpriv, REG_LEDCFG2, 88 rtl_write_byte(rtlpriv, REG_LEDCFG2,
89 (ledcfg | BIT(1) | BIT(5) | BIT(6))); 89 (ledcfg | BIT(1) | BIT(5) | BIT(6)));
90 else 90 else
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
index abe0fcc75368..592a10ac5929 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
@@ -46,13 +46,12 @@ u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
46 struct rtl_priv *rtlpriv = rtl_priv(hw); 46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 u32 original_value, readback_value, bitshift; 47 u32 original_value, readback_value, bitshift;
48 struct rtl_phy *rtlphy = &(rtlpriv->phy); 48 struct rtl_phy *rtlphy = &(rtlpriv->phy);
49 unsigned long flags;
50 49
51 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), " 50 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
52 "rfpath(%#x), bitmask(%#x)\n", 51 "rfpath(%#x), bitmask(%#x)\n",
53 regaddr, rfpath, bitmask)); 52 regaddr, rfpath, bitmask));
54 53
55 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 54 spin_lock(&rtlpriv->locks.rf_lock);
56 55
57 if (rtlphy->rf_mode != RF_OP_BY_FW) { 56 if (rtlphy->rf_mode != RF_OP_BY_FW) {
58 original_value = _rtl92c_phy_rf_serial_read(hw, 57 original_value = _rtl92c_phy_rf_serial_read(hw,
@@ -65,7 +64,7 @@ u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
65 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); 64 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
66 readback_value = (original_value & bitmask) >> bitshift; 65 readback_value = (original_value & bitmask) >> bitshift;
67 66
68 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 67 spin_unlock(&rtlpriv->locks.rf_lock);
69 68
70 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 69 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
71 ("regaddr(%#x), rfpath(%#x), " 70 ("regaddr(%#x), rfpath(%#x), "
@@ -120,13 +119,12 @@ void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
120 struct rtl_priv *rtlpriv = rtl_priv(hw); 119 struct rtl_priv *rtlpriv = rtl_priv(hw);
121 struct rtl_phy *rtlphy = &(rtlpriv->phy); 120 struct rtl_phy *rtlphy = &(rtlpriv->phy);
122 u32 original_value, bitshift; 121 u32 original_value, bitshift;
123 unsigned long flags;
124 122
125 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 123 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
126 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", 124 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
127 regaddr, bitmask, data, rfpath)); 125 regaddr, bitmask, data, rfpath));
128 126
129 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 127 spin_lock(&rtlpriv->locks.rf_lock);
130 128
131 if (rtlphy->rf_mode != RF_OP_BY_FW) { 129 if (rtlphy->rf_mode != RF_OP_BY_FW) {
132 if (bitmask != RFREG_OFFSET_MASK) { 130 if (bitmask != RFREG_OFFSET_MASK) {
@@ -153,7 +151,7 @@ void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
153 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data); 151 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
154 } 152 }
155 153
156 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 154 spin_unlock(&rtlpriv->locks.rf_lock);
157 155
158 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), " 156 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
159 "bitmask(%#x), data(%#x), " 157 "bitmask(%#x), data(%#x), "
@@ -281,7 +279,6 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
281{ 279{
282 280
283 int i; 281 int i;
284 bool rtstatus = true;
285 u32 *radioa_array_table; 282 u32 *radioa_array_table;
286 u32 *radiob_array_table; 283 u32 *radiob_array_table;
287 u16 radioa_arraylen, radiob_arraylen; 284 u16 radioa_arraylen, radiob_arraylen;
@@ -308,7 +305,6 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
308 ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n")); 305 ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
309 } 306 }
310 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath)); 307 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
311 rtstatus = true;
312 switch (rfpath) { 308 switch (rfpath) {
313 case RF90_PATH_A: 309 case RF90_PATH_A:
314 for (i = 0; i < radioa_arraylen; i = i + 2) { 310 for (i = 0; i < radioa_arraylen; i = i + 2) {
@@ -521,7 +517,6 @@ static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
521 u8 i, queue_id; 517 u8 i, queue_id;
522 struct rtl8192_tx_ring *ring = NULL; 518 struct rtl8192_tx_ring *ring = NULL;
523 519
524 ppsc->set_rfpowerstate_inprogress = true;
525 switch (rfpwr_state) { 520 switch (rfpwr_state) {
526 case ERFON:{ 521 case ERFON:{
527 if ((ppsc->rfpwr_state == ERFOFF) && 522 if ((ppsc->rfpwr_state == ERFOFF) &&
@@ -617,7 +612,6 @@ static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
617 } 612 }
618 if (bresult) 613 if (bresult)
619 ppsc->rfpwr_state = rfpwr_state; 614 ppsc->rfpwr_state = rfpwr_state;
620 ppsc->set_rfpowerstate_inprogress = false;
621 return bresult; 615 return bresult;
622} 616}
623 617
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
index 598cecc63f41..72a3d5497547 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
@@ -1203,7 +1203,9 @@
1203#define EPROM_CMD_CONFIG 0x3 1203#define EPROM_CMD_CONFIG 0x3
1204#define EPROM_CMD_LOAD 1 1204#define EPROM_CMD_LOAD 1
1205 1205
1206#define HWSET_MAX_SIZE 128
1206#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1207#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE
1208#define EFUSE_MAX_SECTION 16
1207 1209
1208#define WL_HWPDN_EN BIT(0) 1210#define WL_HWPDN_EN BIT(0)
1209 1211
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
index 90d0f2cf3b27..d3b01e6023ba 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
@@ -76,7 +76,7 @@ void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
76 if (rtlefuse->eeprom_regulatory != 0) 76 if (rtlefuse->eeprom_regulatory != 0)
77 turbo_scanoff = true; 77 turbo_scanoff = true;
78 78
79 if (mac->act_scanning == true) { 79 if (mac->act_scanning) {
80 tx_agc[RF90_PATH_A] = 0x3f3f3f3f; 80 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
81 tx_agc[RF90_PATH_B] = 0x3f3f3f3f; 81 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
82 82
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
index 54b2bd53d36a..230bbe900d8d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
@@ -225,7 +225,7 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
225{ 225{
226 struct rtl_priv *rtlpriv = rtl_priv(hw); 226 struct rtl_priv *rtlpriv = rtl_priv(hw);
227 struct phy_sts_cck_8192s_t *cck_buf; 227 struct phy_sts_cck_8192s_t *cck_buf;
228 s8 rx_pwr_all, rx_pwr[4]; 228 s8 rx_pwr_all = 0, rx_pwr[4];
229 u8 evm, pwdb_all, rf_rx_num = 0; 229 u8 evm, pwdb_all, rf_rx_num = 0;
230 u8 i, max_spatial_stream; 230 u8 i, max_spatial_stream;
231 u32 rssi, total_rssi = 0; 231 u32 rssi, total_rssi = 0;
@@ -592,7 +592,6 @@ static void _rtl92ce_translate_rx_signal_stuff(struct ieee80211_hw *hw,
592 struct ieee80211_hdr *hdr; 592 struct ieee80211_hdr *hdr;
593 u8 *tmp_buf; 593 u8 *tmp_buf;
594 u8 *praddr; 594 u8 *praddr;
595 u8 *psaddr;
596 __le16 fc; 595 __le16 fc;
597 u16 type, c_fc; 596 u16 type, c_fc;
598 bool packet_matchbssid, packet_toself, packet_beacon; 597 bool packet_matchbssid, packet_toself, packet_beacon;
@@ -604,7 +603,6 @@ static void _rtl92ce_translate_rx_signal_stuff(struct ieee80211_hw *hw,
604 c_fc = le16_to_cpu(fc); 603 c_fc = le16_to_cpu(fc);
605 type = WLAN_FC_GET_TYPE(fc); 604 type = WLAN_FC_GET_TYPE(fc);
606 praddr = hdr->addr1; 605 praddr = hdr->addr1;
607 psaddr = hdr->addr2;
608 606
609 packet_matchbssid = 607 packet_matchbssid =
610 ((IEEE80211_FTYPE_CTL != type) && 608 ((IEEE80211_FTYPE_CTL != type) &&
@@ -680,7 +678,7 @@ bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
680 GET_RX_DESC_PAGGR(pdesc)); 678 GET_RX_DESC_PAGGR(pdesc));
681 679
682 rx_status->mactime = GET_RX_DESC_TSFL(pdesc); 680 rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
683 if (phystatus == true) { 681 if (phystatus) {
684 p_drvinfo = (struct rx_fwinfo_92c *)(skb->data + 682 p_drvinfo = (struct rx_fwinfo_92c *)(skb->data +
685 stats->rx_bufshift); 683 stats->rx_bufshift);
686 684
@@ -929,9 +927,10 @@ void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
929 927
930void rtl92ce_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val) 928void rtl92ce_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
931{ 929{
932 if (istx == true) { 930 if (istx) {
933 switch (desc_name) { 931 switch (desc_name) {
934 case HW_DESC_OWN: 932 case HW_DESC_OWN:
933 wmb();
935 SET_TX_DESC_OWN(pdesc, 1); 934 SET_TX_DESC_OWN(pdesc, 1);
936 break; 935 break;
937 case HW_DESC_TX_NEXTDESC_ADDR: 936 case HW_DESC_TX_NEXTDESC_ADDR:
@@ -945,6 +944,7 @@ void rtl92ce_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
945 } else { 944 } else {
946 switch (desc_name) { 945 switch (desc_name) {
947 case HW_DESC_RXOWN: 946 case HW_DESC_RXOWN:
947 wmb();
948 SET_RX_DESC_OWN(pdesc, 1); 948 SET_RX_DESC_OWN(pdesc, 1);
949 break; 949 break;
950 case HW_DESC_RXBUFF_ADDR: 950 case HW_DESC_RXBUFF_ADDR:
@@ -968,7 +968,7 @@ u32 rtl92ce_get_desc(u8 *p_desc, bool istx, u8 desc_name)
968{ 968{
969 u32 ret = 0; 969 u32 ret = 0;
970 970
971 if (istx == true) { 971 if (istx) {
972 switch (desc_name) { 972 switch (desc_name) {
973 case HW_DESC_OWN: 973 case HW_DESC_OWN:
974 ret = GET_TX_DESC_OWN(p_desc); 974 ret = GET_TX_DESC_OWN(p_desc);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
index 52e2af58c1ed..814c05df51e8 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
@@ -27,6 +27,8 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include "../wifi.h" 32#include "../wifi.h"
31#include "../efuse.h" 33#include "../efuse.h"
32#include "../base.h" 34#include "../base.h"
@@ -337,7 +339,7 @@ static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
337 rtlefuse->board_type = boardType; 339 rtlefuse->board_type = boardType;
338 if (IS_HIGHT_PA(rtlefuse->board_type)) 340 if (IS_HIGHT_PA(rtlefuse->board_type))
339 rtlefuse->external_pa = 1; 341 rtlefuse->external_pa = 1;
340 printk(KERN_INFO "rtl8192cu: Board Type %x\n", rtlefuse->board_type); 342 pr_info("Board Type %x\n", rtlefuse->board_type);
341 343
342#ifdef CONFIG_ANTENNA_DIVERSITY 344#ifdef CONFIG_ANTENNA_DIVERSITY
343 /* Antenna Diversity setting. */ 345 /* Antenna Diversity setting. */
@@ -346,8 +348,7 @@ static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
346 else 348 else
347 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */ 349 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
348 350
349 printk(KERN_INFO "rtl8192cu: Antenna Config %x\n", 351 pr_info("Antenna Config %x\n", rtl_efuse->antenna_cfg);
350 rtl_efuse->antenna_cfg);
351#endif 352#endif
352} 353}
353 354
@@ -384,71 +385,57 @@ static void _update_bt_param(_adapter *padapter)
384 pbtpriv->bBTNonTrafficModeSet = _FALSE; 385 pbtpriv->bBTNonTrafficModeSet = _FALSE;
385 pbtpriv->CurrentState = 0; 386 pbtpriv->CurrentState = 0;
386 pbtpriv->PreviousState = 0; 387 pbtpriv->PreviousState = 0;
387 printk(KERN_INFO "rtl8192cu: BT Coexistance = %s\n", 388 pr_info("BT Coexistance = %s\n",
388 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable"); 389 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
389 if (pbtpriv->BT_Coexist) { 390 if (pbtpriv->BT_Coexist) {
390 if (pbtpriv->BT_Ant_Num == Ant_x2) 391 if (pbtpriv->BT_Ant_Num == Ant_x2)
391 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 392 pr_info("BlueTooth BT_Ant_Num = Antx2\n");
392 "Ant_Num = Antx2\n");
393 else if (pbtpriv->BT_Ant_Num == Ant_x1) 393 else if (pbtpriv->BT_Ant_Num == Ant_x1)
394 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 394 pr_info("BlueTooth BT_Ant_Num = Antx1\n");
395 "Ant_Num = Antx1\n");
396 switch (pbtpriv->BT_CoexistType) { 395 switch (pbtpriv->BT_CoexistType) {
397 case BT_2Wire: 396 case BT_2Wire:
398 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 397 pr_info("BlueTooth BT_CoexistType = BT_2Wire\n");
399 "CoexistType = BT_2Wire\n");
400 break; 398 break;
401 case BT_ISSC_3Wire: 399 case BT_ISSC_3Wire:
402 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 400 pr_info("BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
403 "CoexistType = BT_ISSC_3Wire\n");
404 break; 401 break;
405 case BT_Accel: 402 case BT_Accel:
406 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 403 pr_info("BlueTooth BT_CoexistType = BT_Accel\n");
407 "CoexistType = BT_Accel\n");
408 break; 404 break;
409 case BT_CSR_BC4: 405 case BT_CSR_BC4:
410 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 406 pr_info("BlueTooth BT_CoexistType = BT_CSR_BC4\n");
411 "CoexistType = BT_CSR_BC4\n");
412 break; 407 break;
413 case BT_CSR_BC8: 408 case BT_CSR_BC8:
414 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 409 pr_info("BlueTooth BT_CoexistType = BT_CSR_BC8\n");
415 "CoexistType = BT_CSR_BC8\n");
416 break; 410 break;
417 case BT_RTL8756: 411 case BT_RTL8756:
418 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 412 pr_info("BlueTooth BT_CoexistType = BT_RTL8756\n");
419 "CoexistType = BT_RTL8756\n");
420 break; 413 break;
421 default: 414 default:
422 printk(KERN_INFO "rtl8192cu: BlueTooth BT_" 415 pr_info("BlueTooth BT_CoexistType = Unknown\n");
423 "CoexistType = Unknown\n");
424 break; 416 break;
425 } 417 }
426 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Ant_isolation = %d\n", 418 pr_info("BlueTooth BT_Ant_isolation = %d\n",
427 pbtpriv->BT_Ant_isolation); 419 pbtpriv->BT_Ant_isolation);
428 switch (pbtpriv->BT_Service) { 420 switch (pbtpriv->BT_Service) {
429 case BT_OtherAction: 421 case BT_OtherAction:
430 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = " 422 pr_info("BlueTooth BT_Service = BT_OtherAction\n");
431 "BT_OtherAction\n");
432 break; 423 break;
433 case BT_SCO: 424 case BT_SCO:
434 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = " 425 pr_info("BlueTooth BT_Service = BT_SCO\n");
435 "BT_SCO\n");
436 break; 426 break;
437 case BT_Busy: 427 case BT_Busy:
438 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = " 428 pr_info("BlueTooth BT_Service = BT_Busy\n");
439 "BT_Busy\n");
440 break; 429 break;
441 case BT_OtherBusy: 430 case BT_OtherBusy:
442 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = " 431 pr_info("BlueTooth BT_Service = BT_OtherBusy\n");
443 "BT_OtherBusy\n");
444 break; 432 break;
445 default: 433 default:
446 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = " 434 pr_info("BlueTooth BT_Service = BT_Idle\n");
447 "BT_Idle\n");
448 break; 435 break;
449 } 436 }
450 printk(KERN_INFO "rtl8192cu: BT_RadioSharedType = 0x%x\n", 437 pr_info("BT_RadioSharedType = 0x%x\n",
451 pbtpriv->BT_RadioSharedType); 438 pbtpriv->BT_RadioSharedType);
452 } 439 }
453} 440}
454 441
@@ -520,13 +507,13 @@ static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
520 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n")); 507 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
521 rtlefuse->autoload_failflag = false; 508 rtlefuse->autoload_failflag = false;
522 } 509 }
523 if (rtlefuse->autoload_failflag == true) 510 if (rtlefuse->autoload_failflag)
524 return; 511 return;
525 for (i = 0; i < 6; i += 2) { 512 for (i = 0; i < 6; i += 2) {
526 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i]; 513 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
527 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; 514 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
528 } 515 }
529 printk(KERN_INFO "rtl8192cu: MAC address: %pM\n", rtlefuse->dev_addr); 516 pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
530 _rtl92cu_read_txpower_info_from_hwpg(hw, 517 _rtl92cu_read_txpower_info_from_hwpg(hw,
531 rtlefuse->autoload_failflag, hwinfo); 518 rtlefuse->autoload_failflag, hwinfo);
532 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID]; 519 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
@@ -665,7 +652,7 @@ static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
665 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16); 652 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
666 do { 653 do {
667 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) { 654 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
668 printk(KERN_INFO "rtl8192cu: MAC auto ON okay!\n"); 655 pr_info("MAC auto ON okay!\n");
669 break; 656 break;
670 } 657 }
671 if (pollingCount++ > 100) { 658 if (pollingCount++ > 100) {
@@ -819,7 +806,7 @@ static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
819 } 806 }
820 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value, 807 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
821 value, value); 808 value, value);
822 printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel); 809 pr_info("Tx queue select: 0x%02x\n", queue_sel);
823} 810}
824 811
825static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw, 812static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
@@ -863,7 +850,7 @@ static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
863 hiQ = valueHi; 850 hiQ = valueHi;
864 } 851 }
865 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 852 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
866 printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel); 853 pr_info("Tx queue select: 0x%02x\n", queue_sel);
867} 854}
868 855
869static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw, 856static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
@@ -1594,7 +1581,7 @@ static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1594 default: 1581 default:
1595 break; 1582 break;
1596 } 1583 }
1597 if (filterout_non_associated_bssid == true) { 1584 if (filterout_non_associated_bssid) {
1598 if (IS_NORMAL_CHIP(rtlhal->version)) { 1585 if (IS_NORMAL_CHIP(rtlhal->version)) {
1599 switch (rtlphy->current_io_type) { 1586 switch (rtlphy->current_io_type) {
1600 case IO_CMD_RESUME_DM_BY_SCAN: 1587 case IO_CMD_RESUME_DM_BY_SCAN:
@@ -2155,7 +2142,7 @@ void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
2155 case HW_VAR_CORRECT_TSF:{ 2142 case HW_VAR_CORRECT_TSF:{
2156 u8 btype_ibss = ((u8 *) (val))[0]; 2143 u8 btype_ibss = ((u8 *) (val))[0];
2157 2144
2158 if (btype_ibss == true) 2145 if (btype_ibss)
2159 _rtl92cu_stop_tx_beacon(hw); 2146 _rtl92cu_stop_tx_beacon(hw);
2160 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3)); 2147 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2161 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf & 2148 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
@@ -2163,7 +2150,7 @@ void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
2163 rtl_write_dword(rtlpriv, REG_TSFTR + 4, 2150 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2164 (u32)((mac->tsf >> 32) & 0xffffffff)); 2151 (u32)((mac->tsf >> 32) & 0xffffffff));
2165 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0); 2152 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2166 if (btype_ibss == true) 2153 if (btype_ibss)
2167 _rtl92cu_resume_tx_beacon(hw); 2154 _rtl92cu_resume_tx_beacon(hw);
2168 break; 2155 break;
2169 } 2156 }
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/led.c b/drivers/net/wireless/rtlwifi/rtl8192cu/led.c
index 332c74348a69..2ff9d8314e7b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/led.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/led.c
@@ -82,7 +82,7 @@ void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
82 break; 82 break;
83 case LED_PIN_LED0: 83 case LED_PIN_LED0:
84 ledcfg &= 0xf0; 84 ledcfg &= 0xf0;
85 if (usbpriv->ledctl.led_opendrain == true) 85 if (usbpriv->ledctl.led_opendrain)
86 rtl_write_byte(rtlpriv, REG_LEDCFG2, 86 rtl_write_byte(rtlpriv, REG_LEDCFG2,
87 (ledcfg | BIT(1) | BIT(5) | BIT(6))); 87 (ledcfg | BIT(1) | BIT(5) | BIT(6)));
88 else 88 else
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
index f8514cba17b6..194fc693c1fa 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -26,6 +26,9 @@
26 * Larry Finger <Larry.Finger@lwfinger.net> 26 * Larry Finger <Larry.Finger@lwfinger.net>
27 * 27 *
28****************************************************************************/ 28****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
29#include <linux/module.h> 32#include <linux/module.h>
30 33
31#include "../wifi.h" 34#include "../wifi.h"
@@ -213,14 +216,14 @@ bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
213 for (i = 0; i < (boundary - 1); i++) { 216 for (i = 0; i < (boundary - 1); i++) {
214 rst = rtl92c_llt_write(hw, i , i + 1); 217 rst = rtl92c_llt_write(hw, i , i + 1);
215 if (true != rst) { 218 if (true != rst) {
216 printk(KERN_ERR "===> %s #1 fail\n", __func__); 219 pr_err("===> %s #1 fail\n", __func__);
217 return rst; 220 return rst;
218 } 221 }
219 } 222 }
220 /* end of list */ 223 /* end of list */
221 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF); 224 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
222 if (true != rst) { 225 if (true != rst) {
223 printk(KERN_ERR "===> %s #2 fail\n", __func__); 226 pr_err("===> %s #2 fail\n", __func__);
224 return rst; 227 return rst;
225 } 228 }
226 /* Make the other pages as ring buffer 229 /* Make the other pages as ring buffer
@@ -231,14 +234,14 @@ bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
231 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) { 234 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
232 rst = rtl92c_llt_write(hw, i, (i + 1)); 235 rst = rtl92c_llt_write(hw, i, (i + 1));
233 if (true != rst) { 236 if (true != rst) {
234 printk(KERN_ERR "===> %s #3 fail\n", __func__); 237 pr_err("===> %s #3 fail\n", __func__);
235 return rst; 238 return rst;
236 } 239 }
237 } 240 }
238 /* Let last entry point to the start entry of ring buffer */ 241 /* Let last entry point to the start entry of ring buffer */
239 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary); 242 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
240 if (true != rst) { 243 if (true != rst) {
241 printk(KERN_ERR "===> %s #4 fail\n", __func__); 244 pr_err("===> %s #4 fail\n", __func__);
242 return rst; 245 return rst;
243 } 246 }
244 return rst; 247 return rst;
@@ -380,13 +383,11 @@ void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
380 0xFFFFFFFF); 383 0xFFFFFFFF);
381 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 384 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
382 0xFFFFFFFF); 385 0xFFFFFFFF);
383 rtlpci->irq_enabled = true;
384 } else { 386 } else {
385 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] & 387 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
386 0xFFFFFFFF); 388 0xFFFFFFFF);
387 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] & 389 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
388 0xFFFFFFFF); 390 0xFFFFFFFF);
389 rtlusb->irq_enabled = true;
390 } 391 }
391} 392}
392 393
@@ -398,16 +399,9 @@ void rtl92c_init_interrupt(struct ieee80211_hw *hw)
398void rtl92c_disable_interrupt(struct ieee80211_hw *hw) 399void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
399{ 400{
400 struct rtl_priv *rtlpriv = rtl_priv(hw); 401 struct rtl_priv *rtlpriv = rtl_priv(hw);
401 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
402 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
403 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
404 402
405 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED); 403 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
406 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED); 404 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
407 if (IS_HARDWARE_TYPE_8192CE(rtlhal))
408 rtlpci->irq_enabled = false;
409 else if (IS_HARDWARE_TYPE_8192CU(rtlhal))
410 rtlusb->irq_enabled = false;
411} 405}
412 406
413void rtl92c_set_qos(struct ieee80211_hw *hw, int aci) 407void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
@@ -1113,7 +1107,6 @@ void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
1113 struct ieee80211_hdr *hdr; 1107 struct ieee80211_hdr *hdr;
1114 u8 *tmp_buf; 1108 u8 *tmp_buf;
1115 u8 *praddr; 1109 u8 *praddr;
1116 u8 *psaddr;
1117 __le16 fc; 1110 __le16 fc;
1118 u16 type, cpu_fc; 1111 u16 type, cpu_fc;
1119 bool packet_matchbssid, packet_toself, packet_beacon; 1112 bool packet_matchbssid, packet_toself, packet_beacon;
@@ -1124,7 +1117,6 @@ void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
1124 cpu_fc = le16_to_cpu(fc); 1117 cpu_fc = le16_to_cpu(fc);
1125 type = WLAN_FC_GET_TYPE(fc); 1118 type = WLAN_FC_GET_TYPE(fc);
1126 praddr = hdr->addr1; 1119 praddr = hdr->addr1;
1127 psaddr = hdr->addr2;
1128 packet_matchbssid = 1120 packet_matchbssid =
1129 ((IEEE80211_FTYPE_CTL != type) && 1121 ((IEEE80211_FTYPE_CTL != type) &&
1130 (!compare_ether_addr(mac->bssid, 1122 (!compare_ether_addr(mac->bssid,
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
index 9a3d0239e27e..72852900df84 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
@@ -470,7 +470,6 @@ static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
470 u8 i, queue_id; 470 u8 i, queue_id;
471 struct rtl8192_tx_ring *ring = NULL; 471 struct rtl8192_tx_ring *ring = NULL;
472 472
473 ppsc->set_rfpowerstate_inprogress = true;
474 switch (rfpwr_state) { 473 switch (rfpwr_state) {
475 case ERFON: 474 case ERFON:
476 if ((ppsc->rfpwr_state == ERFOFF) && 475 if ((ppsc->rfpwr_state == ERFOFF) &&
@@ -590,7 +589,6 @@ static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
590 } 589 }
591 if (bresult) 590 if (bresult)
592 ppsc->rfpwr_state = rfpwr_state; 591 ppsc->rfpwr_state = rfpwr_state;
593 ppsc->set_rfpowerstate_inprogress = false;
594 return bresult; 592 return bresult;
595} 593}
596 594
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
index c7576ec4744e..17a8e9628512 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
@@ -82,7 +82,7 @@ void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
82 (rtlefuse->external_pa)) 82 (rtlefuse->external_pa))
83 turbo_scanoff = true; 83 turbo_scanoff = true;
84 } 84 }
85 if (mac->act_scanning == true) { 85 if (mac->act_scanning) {
86 tx_agc[RF90_PATH_A] = 0x3f3f3f3f; 86 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
87 tx_agc[RF90_PATH_B] = 0x3f3f3f3f; 87 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
88 if (turbo_scanoff) { 88 if (turbo_scanoff) {
@@ -104,7 +104,7 @@ void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
104 tx_agc[RF90_PATH_A] = 0x10101010; 104 tx_agc[RF90_PATH_A] = 0x10101010;
105 tx_agc[RF90_PATH_B] = 0x10101010; 105 tx_agc[RF90_PATH_B] = 0x10101010;
106 } else if (rtlpriv->dm.dynamic_txhighpower_lvl == 106 } else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
107 TXHIGHPWRLEVEL_LEVEL1) { 107 TXHIGHPWRLEVEL_LEVEL2) {
108 tx_agc[RF90_PATH_A] = 0x00000000; 108 tx_agc[RF90_PATH_A] = 0x00000000;
109 tx_agc[RF90_PATH_B] = 0x00000000; 109 tx_agc[RF90_PATH_B] = 0x00000000;
110 } else{ 110 } else{
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
index 092e342c19df..942f7a3969a7 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -298,6 +298,7 @@ static struct usb_device_id rtl8192c_usb_ids[] = {
298 {RTL_USB_DEVICE(0x06f8, 0xe033, rtl92cu_hal_cfg)}, /*Hercules - Edimax*/ 298 {RTL_USB_DEVICE(0x06f8, 0xe033, rtl92cu_hal_cfg)}, /*Hercules - Edimax*/
299 {RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/ 299 {RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/
300 {RTL_USB_DEVICE(0x07b8, 0x8189, rtl92cu_hal_cfg)}, /*Funai - Abocom*/ 300 {RTL_USB_DEVICE(0x07b8, 0x8189, rtl92cu_hal_cfg)}, /*Funai - Abocom*/
301 {RTL_USB_DEVICE(0x0846, 0x9041, rtl92cu_hal_cfg)}, /*NetGear WNA1000M*/
301 {RTL_USB_DEVICE(0x0Df6, 0x0052, rtl92cu_hal_cfg)}, /*Sitecom - Edimax*/ 302 {RTL_USB_DEVICE(0x0Df6, 0x0052, rtl92cu_hal_cfg)}, /*Sitecom - Edimax*/
302 {RTL_USB_DEVICE(0x0eb0, 0x9071, rtl92cu_hal_cfg)}, /*NO Brand - Etop*/ 303 {RTL_USB_DEVICE(0x0eb0, 0x9071, rtl92cu_hal_cfg)}, /*NO Brand - Etop*/
303 /* HP - Lite-On ,8188CUS Slim Combo */ 304 /* HP - Lite-On ,8188CUS Slim Combo */
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
index 3a92ba3c4a1e..906e7aa55bc3 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
@@ -342,7 +342,7 @@ bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
342 (u8)GET_RX_DESC_RX_MCS(pdesc), 342 (u8)GET_RX_DESC_RX_MCS(pdesc),
343 (bool)GET_RX_DESC_PAGGR(pdesc)); 343 (bool)GET_RX_DESC_PAGGR(pdesc));
344 rx_status->mactime = GET_RX_DESC_TSFL(pdesc); 344 rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
345 if (phystatus == true) { 345 if (phystatus) {
346 p_drvinfo = (struct rx_fwinfo_92c *)(pdesc + RTL_RX_DESC_SIZE); 346 p_drvinfo = (struct rx_fwinfo_92c *)(pdesc + RTL_RX_DESC_SIZE);
347 rtl92c_translate_rx_signal_stuff(hw, skb, stats, pdesc, 347 rtl92c_translate_rx_signal_stuff(hw, skb, stats, pdesc,
348 p_drvinfo); 348 p_drvinfo);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/Makefile b/drivers/net/wireless/rtlwifi/rtl8192de/Makefile
new file mode 100644
index 000000000000..e3213c8264b6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/Makefile
@@ -0,0 +1,14 @@
1rtl8192de-objs := \
2 dm.o \
3 fw.o \
4 hw.o \
5 led.o \
6 phy.o \
7 rf.o \
8 sw.o \
9 table.o \
10 trx.o
11
12obj-$(CONFIG_RTL8192DE) += rtl8192de.o
13
14ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/def.h b/drivers/net/wireless/rtlwifi/rtl8192de/def.h
new file mode 100644
index 000000000000..f0f5f9bfbb7b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/def.h
@@ -0,0 +1,269 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_DEF_H__
31#define __RTL92D_DEF_H__
32
33/* Min Spacing related settings. */
34#define MAX_MSS_DENSITY_2T 0x13
35#define MAX_MSS_DENSITY_1T 0x0A
36
37#define RF6052_MAX_TX_PWR 0x3F
38#define RF6052_MAX_REG 0x3F
39#define RF6052_MAX_PATH 2
40
41#define HAL_RETRY_LIMIT_INFRA 48
42#define HAL_RETRY_LIMIT_AP_ADHOC 7
43
44#define PHY_RSSI_SLID_WIN_MAX 100
45#define PHY_LINKQUALITY_SLID_WIN_MAX 20
46#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
47
48#define RESET_DELAY_8185 20
49
50#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
51#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
52
53#define NUM_OF_FIRMWARE_QUEUE 10
54#define NUM_OF_PAGES_IN_FW 0x100
55#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
56#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
57#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
58#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
59#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
60#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
61#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
62#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
63#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
64#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
65
66#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
67#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
68#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
69#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
70#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
71
72#define MAX_LINES_HWCONFIG_TXT 1000
73#define MAX_BYTES_LINE_HWCONFIG_TXT 256
74
75#define SW_THREE_WIRE 0
76#define HW_THREE_WIRE 2
77
78#define BT_DEMO_BOARD 0
79#define BT_QA_BOARD 1
80#define BT_FPGA 2
81
82#define RX_SMOOTH_FACTOR 20
83
84#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
85#define HAL_PRIME_CHNL_OFFSET_LOWER 1
86#define HAL_PRIME_CHNL_OFFSET_UPPER 2
87
88#define MAX_H2C_QUEUE_NUM 10
89
90#define RX_MPDU_QUEUE 0
91#define RX_CMD_QUEUE 1
92#define RX_MAX_QUEUE 2
93
94#define C2H_RX_CMD_HDR_LEN 8
95#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
96 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
97#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
98 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
99#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
100 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
101#define GET_C2H_CMD_CONTINUE(__prxhdr) \
102 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
103#define GET_C2H_CMD_CONTENT(__prxhdr) \
104 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
105
106#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
107 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
108#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
109 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
110#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
111 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
112#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
113 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
114#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
115 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
116#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
117 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
118#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
119 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
120#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
121 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
122#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
123 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
124
125/*
126 * 92D chip ver:
127 * BIT8: IS 92D
128 * BIT9: single phy
129 * BIT10: C-cut
130 * BIT11: D-cut
131 */
132
133/* Chip specific */
134#define CHIP_92C BIT(0)
135#define CHIP_92C_1T2R BIT(1)
136#define CHIP_8723 BIT(2) /* RTL8723 With BT feature */
137#define CHIP_8723_DRV_REV BIT(3) /* RTL8723 Driver Revised */
138#define NORMAL_CHIP BIT(4)
139#define CHIP_VENDOR_UMC BIT(5)
140#define CHIP_VENDOR_UMC_B_CUT BIT(6) /* Chip version for ECO */
141
142/* for 92D */
143#define CHIP_92D BIT(8)
144#define CHIP_92D_SINGLEPHY BIT(9)
145#define CHIP_92D_C_CUT BIT(10)
146#define CHIP_92D_D_CUT BIT(11)
147
148enum version_8192d {
149 VERSION_TEST_CHIP_88C = 0x00,
150 VERSION_TEST_CHIP_92C = 0x01,
151 VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
152 VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
153 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
154 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
155 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
156 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
157 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
158 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
159 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
160 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
161 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
162 VERSION_TEST_CHIP_92D_SINGLEPHY = 0x300,
163 VERSION_TEST_CHIP_92D_DUALPHY = 0x100,
164 VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x310,
165 VERSION_NORMAL_CHIP_92D_DUALPHY = 0x110,
166 VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x710,
167 VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x510,
168 VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0xB10,
169 VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x910,
170};
171
172#define IS_92D_SINGLEPHY(version) \
173 ((version & CHIP_92D_SINGLEPHY) ? true : false)
174#define IS_92D_C_CUT(version) \
175 ((version & CHIP_92D_C_CUT) ? true : false)
176#define IS_92D_D_CUT(version) \
177 ((version & CHIP_92D_D_CUT) ? true : false)
178
179enum rf_optype {
180 RF_OP_BY_SW_3WIRE = 0,
181 RF_OP_BY_FW,
182 RF_OP_MAX
183};
184
185enum rtl_desc_qsel {
186 QSLT_BK = 0x2,
187 QSLT_BE = 0x0,
188 QSLT_VI = 0x5,
189 QSLT_VO = 0x7,
190 QSLT_BEACON = 0x10,
191 QSLT_HIGH = 0x11,
192 QSLT_MGNT = 0x12,
193 QSLT_CMD = 0x13,
194};
195
196enum rtl_desc92d_rate {
197 DESC92D_RATE1M = 0x00,
198 DESC92D_RATE2M = 0x01,
199 DESC92D_RATE5_5M = 0x02,
200 DESC92D_RATE11M = 0x03,
201
202 DESC92D_RATE6M = 0x04,
203 DESC92D_RATE9M = 0x05,
204 DESC92D_RATE12M = 0x06,
205 DESC92D_RATE18M = 0x07,
206 DESC92D_RATE24M = 0x08,
207 DESC92D_RATE36M = 0x09,
208 DESC92D_RATE48M = 0x0a,
209 DESC92D_RATE54M = 0x0b,
210
211 DESC92D_RATEMCS0 = 0x0c,
212 DESC92D_RATEMCS1 = 0x0d,
213 DESC92D_RATEMCS2 = 0x0e,
214 DESC92D_RATEMCS3 = 0x0f,
215 DESC92D_RATEMCS4 = 0x10,
216 DESC92D_RATEMCS5 = 0x11,
217 DESC92D_RATEMCS6 = 0x12,
218 DESC92D_RATEMCS7 = 0x13,
219 DESC92D_RATEMCS8 = 0x14,
220 DESC92D_RATEMCS9 = 0x15,
221 DESC92D_RATEMCS10 = 0x16,
222 DESC92D_RATEMCS11 = 0x17,
223 DESC92D_RATEMCS12 = 0x18,
224 DESC92D_RATEMCS13 = 0x19,
225 DESC92D_RATEMCS14 = 0x1a,
226 DESC92D_RATEMCS15 = 0x1b,
227 DESC92D_RATEMCS15_SG = 0x1c,
228 DESC92D_RATEMCS32 = 0x20,
229};
230
231enum channel_plan {
232 CHPL_FCC = 0,
233 CHPL_IC = 1,
234 CHPL_ETSI = 2,
235 CHPL_SPAIN = 3,
236 CHPL_FRANCE = 4,
237 CHPL_MKK = 5,
238 CHPL_MKK1 = 6,
239 CHPL_ISRAEL = 7,
240 CHPL_TELEC = 8,
241 CHPL_GLOBAL = 9,
242 CHPL_WORLD = 10,
243};
244
245struct phy_sts_cck_8192d {
246 u8 adc_pwdb_X[4];
247 u8 sq_rpt;
248 u8 cck_agc_rpt;
249};
250
251struct h2c_cmd_8192c {
252 u8 element_id;
253 u32 cmd_len;
254 u8 *p_cmdbuffer;
255};
256
257struct txpower_info {
258 u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
259 u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
260 u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
261 u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
262 u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
263 u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
264 u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
265 u8 tssi_a[3]; /* 5GL/5GM/5GH */
266 u8 tssi_b[3];
267};
268
269#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/dm.c b/drivers/net/wireless/rtlwifi/rtl8192de/dm.c
new file mode 100644
index 000000000000..3cd0736fe8e1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/dm.c
@@ -0,0 +1,1355 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../base.h"
32#include "reg.h"
33#include "def.h"
34#include "phy.h"
35#include "dm.h"
36#include "fw.h"
37
38#define UNDEC_SM_PWDB entry_min_undecoratedsmoothed_pwdb
39
40struct dig_t de_digtable;
41
42static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = {
43 0x7f8001fe, /* 0, +6.0dB */
44 0x788001e2, /* 1, +5.5dB */
45 0x71c001c7, /* 2, +5.0dB */
46 0x6b8001ae, /* 3, +4.5dB */
47 0x65400195, /* 4, +4.0dB */
48 0x5fc0017f, /* 5, +3.5dB */
49 0x5a400169, /* 6, +3.0dB */
50 0x55400155, /* 7, +2.5dB */
51 0x50800142, /* 8, +2.0dB */
52 0x4c000130, /* 9, +1.5dB */
53 0x47c0011f, /* 10, +1.0dB */
54 0x43c0010f, /* 11, +0.5dB */
55 0x40000100, /* 12, +0dB */
56 0x3c8000f2, /* 13, -0.5dB */
57 0x390000e4, /* 14, -1.0dB */
58 0x35c000d7, /* 15, -1.5dB */
59 0x32c000cb, /* 16, -2.0dB */
60 0x300000c0, /* 17, -2.5dB */
61 0x2d4000b5, /* 18, -3.0dB */
62 0x2ac000ab, /* 19, -3.5dB */
63 0x288000a2, /* 20, -4.0dB */
64 0x26000098, /* 21, -4.5dB */
65 0x24000090, /* 22, -5.0dB */
66 0x22000088, /* 23, -5.5dB */
67 0x20000080, /* 24, -6.0dB */
68 0x1e400079, /* 25, -6.5dB */
69 0x1c800072, /* 26, -7.0dB */
70 0x1b00006c, /* 27. -7.5dB */
71 0x19800066, /* 28, -8.0dB */
72 0x18000060, /* 29, -8.5dB */
73 0x16c0005b, /* 30, -9.0dB */
74 0x15800056, /* 31, -9.5dB */
75 0x14400051, /* 32, -10.0dB */
76 0x1300004c, /* 33, -10.5dB */
77 0x12000048, /* 34, -11.0dB */
78 0x11000044, /* 35, -11.5dB */
79 0x10000040, /* 36, -12.0dB */
80 0x0f00003c, /* 37, -12.5dB */
81 0x0e400039, /* 38, -13.0dB */
82 0x0d800036, /* 39, -13.5dB */
83 0x0cc00033, /* 40, -14.0dB */
84 0x0c000030, /* 41, -14.5dB */
85 0x0b40002d, /* 42, -15.0dB */
86};
87
88static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
89 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
90 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
91 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
92 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
93 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
94 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
95 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
96 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
97 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
98 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
99 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
100 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
101 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
102 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
103 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
104 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
105 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
106 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
107 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
108 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
109 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
110 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
111 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
112 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
113 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
114 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
115 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
116 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
117 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
118 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
119 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
120 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
121 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
122};
123
124static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
125 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
126 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
127 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
128 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
129 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
130 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
131 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
132 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
133 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
134 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
135 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
136 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
137 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
138 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
139 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
140 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
141 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
142 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
143 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
144 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
145 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
146 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
147 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
148 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
149 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
150 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
151 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
152 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
153 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
154 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
155 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
156 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
157 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
158};
159
160static void rtl92d_dm_diginit(struct ieee80211_hw *hw)
161{
162 de_digtable.dig_enable_flag = true;
163 de_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
164 de_digtable.cur_igvalue = 0x20;
165 de_digtable.pre_igvalue = 0x0;
166 de_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
167 de_digtable.presta_connectstate = DIG_STA_DISCONNECT;
168 de_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
169 de_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
170 de_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
171 de_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
172 de_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
173 de_digtable.rx_gain_range_max = DM_DIG_FA_UPPER;
174 de_digtable.rx_gain_range_min = DM_DIG_FA_LOWER;
175 de_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
176 de_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
177 de_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
178 de_digtable.pre_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
179 de_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
180 de_digtable.large_fa_hit = 0;
181 de_digtable.recover_cnt = 0;
182 de_digtable.forbidden_igi = DM_DIG_FA_LOWER;
183}
184
185static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
186{
187 u32 ret_value;
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
190 unsigned long flag = 0;
191
192 /* hold ofdm counter */
193 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */
194 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */
195
196 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, BMASKDWORD);
197 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
198 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
199 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, BMASKDWORD);
200 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
201 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, BMASKDWORD);
202 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
203 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
204 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, BMASKDWORD);
205 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
206 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
207 falsealm_cnt->cnt_rate_illegal +
208 falsealm_cnt->cnt_crc8_fail +
209 falsealm_cnt->cnt_mcs_fail +
210 falsealm_cnt->cnt_fast_fsync_fail +
211 falsealm_cnt->cnt_sb_search_fail;
212
213 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
214 /* hold cck counter */
215 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
216 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, BMASKBYTE0);
217 falsealm_cnt->cnt_cck_fail = ret_value;
218 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, BMASKBYTE3);
219 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
220 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
221 } else {
222 falsealm_cnt->cnt_cck_fail = 0;
223 }
224
225 /* reset false alarm counter registers */
226 falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
227 falsealm_cnt->cnt_sb_search_fail +
228 falsealm_cnt->cnt_parity_fail +
229 falsealm_cnt->cnt_rate_illegal +
230 falsealm_cnt->cnt_crc8_fail +
231 falsealm_cnt->cnt_mcs_fail +
232 falsealm_cnt->cnt_cck_fail;
233
234 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
235 /* update ofdm counter */
236 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
237 /* update page C counter */
238 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
239 /* update page D counter */
240 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
241 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
242 /* reset cck counter */
243 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
244 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
245 /* enable cck counter */
246 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
247 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
248 }
249 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("Cnt_Fast_Fsync_fail = %x, "
250 "Cnt_SB_Search_fail = %x\n",
251 falsealm_cnt->cnt_fast_fsync_fail,
252 falsealm_cnt->cnt_sb_search_fail));
253 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("Cnt_Parity_Fail = %x, "
254 "Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, "
255 "Cnt_Mcs_fail = %x\n",
256 falsealm_cnt->cnt_parity_fail,
257 falsealm_cnt->cnt_rate_illegal,
258 falsealm_cnt->cnt_crc8_fail,
259 falsealm_cnt->cnt_mcs_fail));
260 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
261 ("Cnt_Ofdm_fail = %x, " "Cnt_Cck_fail = %x, "
262 "Cnt_all = %x\n",
263 falsealm_cnt->cnt_ofdm_fail,
264 falsealm_cnt->cnt_cck_fail,
265 falsealm_cnt->cnt_all));
266}
267
268static void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw)
269{
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_mac *mac = rtl_mac(rtlpriv);
272
273 /* Determine the minimum RSSI */
274 if ((mac->link_state < MAC80211_LINKED) &&
275 (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
276 de_digtable.min_undecorated_pwdb_for_dm = 0;
277 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
278 ("Not connected to any\n"));
279 }
280 if (mac->link_state >= MAC80211_LINKED) {
281 if (mac->opmode == NL80211_IFTYPE_AP ||
282 mac->opmode == NL80211_IFTYPE_ADHOC) {
283 de_digtable.min_undecorated_pwdb_for_dm =
284 rtlpriv->dm.UNDEC_SM_PWDB;
285 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
286 ("AP Client PWDB = 0x%lx\n",
287 rtlpriv->dm.UNDEC_SM_PWDB));
288 } else {
289 de_digtable.min_undecorated_pwdb_for_dm =
290 rtlpriv->dm.undecorated_smoothed_pwdb;
291 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
292 ("STA Default Port PWDB = 0x%x\n",
293 de_digtable.min_undecorated_pwdb_for_dm));
294 }
295 } else {
296 de_digtable.min_undecorated_pwdb_for_dm =
297 rtlpriv->dm.UNDEC_SM_PWDB;
298 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
299 ("AP Ext Port or disconnet PWDB = 0x%x\n",
300 de_digtable.min_undecorated_pwdb_for_dm));
301 }
302
303 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",
304 de_digtable.min_undecorated_pwdb_for_dm));
305}
306
307static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
308{
309 struct rtl_priv *rtlpriv = rtl_priv(hw);
310 unsigned long flag = 0;
311
312 if (de_digtable.cursta_connectctate == DIG_STA_CONNECT) {
313 if (de_digtable.pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
314 if (de_digtable.min_undecorated_pwdb_for_dm <= 25)
315 de_digtable.cur_cck_pd_state =
316 CCK_PD_STAGE_LOWRSSI;
317 else
318 de_digtable.cur_cck_pd_state =
319 CCK_PD_STAGE_HIGHRSSI;
320 } else {
321 if (de_digtable.min_undecorated_pwdb_for_dm <= 20)
322 de_digtable.cur_cck_pd_state =
323 CCK_PD_STAGE_LOWRSSI;
324 else
325 de_digtable.cur_cck_pd_state =
326 CCK_PD_STAGE_HIGHRSSI;
327 }
328 } else {
329 de_digtable.cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
330 }
331 if (de_digtable.pre_cck_pd_state != de_digtable.cur_cck_pd_state) {
332 if (de_digtable.cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
333 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
334 rtl_set_bbreg(hw, RCCK0_CCA, BMASKBYTE2, 0x83);
335 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
336 } else {
337 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
338 rtl_set_bbreg(hw, RCCK0_CCA, BMASKBYTE2, 0xcd);
339 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
340 }
341 de_digtable.pre_cck_pd_state = de_digtable.cur_cck_pd_state;
342 }
343 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("CurSTAConnectState=%s\n",
344 (de_digtable.cursta_connectctate == DIG_STA_CONNECT ?
345 "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT")));
346 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("CCKPDStage=%s\n",
347 (de_digtable.cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ?
348 "Low RSSI " : "High RSSI ")));
349 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("is92d single phy =%x\n",
350 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)));
351
352}
353
354void rtl92d_dm_write_dig(struct ieee80211_hw *hw)
355{
356 struct rtl_priv *rtlpriv = rtl_priv(hw);
357
358 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("cur_igvalue = 0x%x, "
359 "pre_igvalue = 0x%x, backoff_val = %d\n",
360 de_digtable.cur_igvalue, de_digtable.pre_igvalue,
361 de_digtable.backoff_val));
362 if (de_digtable.dig_enable_flag == false) {
363 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("DIG is disabled\n"));
364 de_digtable.pre_igvalue = 0x17;
365 return;
366 }
367 if (de_digtable.pre_igvalue != de_digtable.cur_igvalue) {
368 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
369 de_digtable.cur_igvalue);
370 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
371 de_digtable.cur_igvalue);
372 de_digtable.pre_igvalue = de_digtable.cur_igvalue;
373 }
374}
375
376static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv)
377{
378 if ((rtlpriv->mac80211.link_state >= MAC80211_LINKED) &&
379 (rtlpriv->mac80211.vendor == PEER_CISCO)) {
380 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
381 ("IOT_PEER = CISCO\n"));
382 if (de_digtable.last_min_undecorated_pwdb_for_dm >= 50
383 && de_digtable.min_undecorated_pwdb_for_dm < 50) {
384 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00);
385 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
386 ("Early Mode Off\n"));
387 } else if (de_digtable.last_min_undecorated_pwdb_for_dm <= 55 &&
388 de_digtable.min_undecorated_pwdb_for_dm > 55) {
389 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
390 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
391 ("Early Mode On\n"));
392 }
393 } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) {
394 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
395 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("Early Mode On\n"));
396 }
397}
398
399static void rtl92d_dm_dig(struct ieee80211_hw *hw)
400{
401 struct rtl_priv *rtlpriv = rtl_priv(hw);
402 u8 value_igi = de_digtable.cur_igvalue;
403 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
404
405 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("==>\n"));
406 if (rtlpriv->rtlhal.earlymode_enable) {
407 rtl92d_early_mode_enabled(rtlpriv);
408 de_digtable.last_min_undecorated_pwdb_for_dm =
409 de_digtable.min_undecorated_pwdb_for_dm;
410 }
411 if (rtlpriv->dm.dm_initialgain_enable == false)
412 return;
413
414 /* because we will send data pkt when scanning
415 * this will cause some ap like gear-3700 wep TP
416 * lower if we retrun here, this is the diff of
417 * mac80211 driver vs ieee80211 driver */
418 /* if (rtlpriv->mac80211.act_scanning)
419 * return; */
420
421 /* Not STA mode return tmp */
422 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
423 return;
424 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("progress\n"));
425 /* Decide the current status and if modify initial gain or not */
426 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
427 de_digtable.cursta_connectctate = DIG_STA_CONNECT;
428 else
429 de_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
430
431 /* adjust initial gain according to false alarm counter */
432 if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0)
433 value_igi--;
434 else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1)
435 value_igi += 0;
436 else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2)
437 value_igi++;
438 else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2)
439 value_igi += 2;
440 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
441 ("dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n",
442 de_digtable.large_fa_hit, de_digtable.forbidden_igi));
443 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
444 ("dm_DIG() Before: Recover_cnt=%d, rx_gain_range_min=%x\n",
445 de_digtable.recover_cnt, de_digtable.rx_gain_range_min));
446
447 /* deal with abnorally large false alarm */
448 if (falsealm_cnt->cnt_all > 10000) {
449 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
450 ("dm_DIG(): Abnornally false alarm case.\n"));
451
452 de_digtable.large_fa_hit++;
453 if (de_digtable.forbidden_igi < de_digtable.cur_igvalue) {
454 de_digtable.forbidden_igi = de_digtable.cur_igvalue;
455 de_digtable.large_fa_hit = 1;
456 }
457 if (de_digtable.large_fa_hit >= 3) {
458 if ((de_digtable.forbidden_igi + 1) > DM_DIG_MAX)
459 de_digtable.rx_gain_range_min = DM_DIG_MAX;
460 else
461 de_digtable.rx_gain_range_min =
462 (de_digtable.forbidden_igi + 1);
463 de_digtable.recover_cnt = 3600; /* 3600=2hr */
464 }
465 } else {
466 /* Recovery mechanism for IGI lower bound */
467 if (de_digtable.recover_cnt != 0) {
468 de_digtable.recover_cnt--;
469 } else {
470 if (de_digtable.large_fa_hit == 0) {
471 if ((de_digtable.forbidden_igi - 1) <
472 DM_DIG_FA_LOWER) {
473 de_digtable.forbidden_igi =
474 DM_DIG_FA_LOWER;
475 de_digtable.rx_gain_range_min =
476 DM_DIG_FA_LOWER;
477
478 } else {
479 de_digtable.forbidden_igi--;
480 de_digtable.rx_gain_range_min =
481 (de_digtable.forbidden_igi + 1);
482 }
483 } else if (de_digtable.large_fa_hit == 3) {
484 de_digtable.large_fa_hit = 0;
485 }
486 }
487 }
488 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
489 ("dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n",
490 de_digtable.large_fa_hit, de_digtable.forbidden_igi));
491 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
492 ("dm_DIG() After: recover_cnt=%d, rx_gain_range_min=%x\n",
493 de_digtable.recover_cnt, de_digtable.rx_gain_range_min));
494
495 if (value_igi > DM_DIG_MAX)
496 value_igi = DM_DIG_MAX;
497 else if (value_igi < de_digtable.rx_gain_range_min)
498 value_igi = de_digtable.rx_gain_range_min;
499 de_digtable.cur_igvalue = value_igi;
500 rtl92d_dm_write_dig(hw);
501 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G)
502 rtl92d_dm_cck_packet_detection_thresh(hw);
503 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, ("<<==\n"));
504}
505
506static void rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
507{
508 struct rtl_priv *rtlpriv = rtl_priv(hw);
509
510 rtlpriv->dm.dynamic_txpower_enable = true;
511 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
512 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
513}
514
515static void rtl92d_dm_dynamic_txpower(struct ieee80211_hw *hw)
516{
517 struct rtl_priv *rtlpriv = rtl_priv(hw);
518 struct rtl_phy *rtlphy = &(rtlpriv->phy);
519 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
520 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
521 long undecorated_smoothed_pwdb;
522
523 if ((!rtlpriv->dm.dynamic_txpower_enable)
524 || rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
525 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
526 return;
527 }
528 if ((mac->link_state < MAC80211_LINKED) &&
529 (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
530 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
531 ("Not connected to any\n"));
532 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
533 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
534 return;
535 }
536 if (mac->link_state >= MAC80211_LINKED) {
537 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
538 undecorated_smoothed_pwdb =
539 rtlpriv->dm.UNDEC_SM_PWDB;
540 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
541 ("IBSS Client PWDB = 0x%lx\n",
542 undecorated_smoothed_pwdb));
543 } else {
544 undecorated_smoothed_pwdb =
545 rtlpriv->dm.undecorated_smoothed_pwdb;
546 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
547 ("STA Default Port PWDB = 0x%lx\n",
548 undecorated_smoothed_pwdb));
549 }
550 } else {
551 undecorated_smoothed_pwdb =
552 rtlpriv->dm.UNDEC_SM_PWDB;
553
554 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
555 ("AP Ext Port PWDB = 0x%lx\n",
556 undecorated_smoothed_pwdb));
557 }
558 if (rtlhal->current_bandtype == BAND_ON_5G) {
559 if (undecorated_smoothed_pwdb >= 0x33) {
560 rtlpriv->dm.dynamic_txhighpower_lvl =
561 TXHIGHPWRLEVEL_LEVEL2;
562 RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
563 ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
564 } else if ((undecorated_smoothed_pwdb < 0x33)
565 && (undecorated_smoothed_pwdb >= 0x2b)) {
566 rtlpriv->dm.dynamic_txhighpower_lvl =
567 TXHIGHPWRLEVEL_LEVEL1;
568 RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
569 ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
570 } else if (undecorated_smoothed_pwdb < 0x2b) {
571 rtlpriv->dm.dynamic_txhighpower_lvl =
572 TXHIGHPWRLEVEL_NORMAL;
573 RT_TRACE(rtlpriv, COMP_HIPWR, DBG_LOUD,
574 ("5G:TxHighPwrLevel_Normal\n"));
575 }
576 } else {
577 if (undecorated_smoothed_pwdb >=
578 TX_POWER_NEAR_FIELD_THRESH_LVL2) {
579 rtlpriv->dm.dynamic_txhighpower_lvl =
580 TXHIGHPWRLEVEL_LEVEL2;
581 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
582 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
583 } else
584 if ((undecorated_smoothed_pwdb <
585 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3))
586 && (undecorated_smoothed_pwdb >=
587 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
588
589 rtlpriv->dm.dynamic_txhighpower_lvl =
590 TXHIGHPWRLEVEL_LEVEL1;
591 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
592 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
593 } else if (undecorated_smoothed_pwdb <
594 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
595 rtlpriv->dm.dynamic_txhighpower_lvl =
596 TXHIGHPWRLEVEL_NORMAL;
597 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
598 ("TXHIGHPWRLEVEL_NORMAL\n"));
599 }
600 }
601 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
602 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
603 ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
604 rtlphy->current_channel));
605 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
606 }
607 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
608}
609
610static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw)
611{
612 struct rtl_priv *rtlpriv = rtl_priv(hw);
613
614 /* AP & ADHOC & MESH will return tmp */
615 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
616 return;
617 /* Indicate Rx signal strength to FW. */
618 if (rtlpriv->dm.useramask) {
619 u32 temp = rtlpriv->dm.undecorated_smoothed_pwdb;
620
621 temp <<= 16;
622 temp |= 0x100;
623 /* fw v12 cmdid 5:use max macid ,for nic ,
624 * default macid is 0 ,max macid is 1 */
625 rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *) (&temp));
626 } else {
627 rtl_write_byte(rtlpriv, 0x4fe,
628 (u8) rtlpriv->dm.undecorated_smoothed_pwdb);
629 }
630}
631
632void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw)
633{
634 struct rtl_priv *rtlpriv = rtl_priv(hw);
635
636 rtlpriv->dm.current_turbo_edca = false;
637 rtlpriv->dm.is_any_nonbepkts = false;
638 rtlpriv->dm.is_cur_rdlstate = false;
639}
640
641static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw)
642{
643 struct rtl_priv *rtlpriv = rtl_priv(hw);
644 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
645 static u64 last_txok_cnt;
646 static u64 last_rxok_cnt;
647 u64 cur_txok_cnt;
648 u64 cur_rxok_cnt;
649 u32 edca_be_ul = 0x5ea42b;
650 u32 edca_be_dl = 0x5ea42b;
651
652 if (mac->link_state != MAC80211_LINKED) {
653 rtlpriv->dm.current_turbo_edca = false;
654 goto exit;
655 }
656
657 /* Enable BEQ TxOP limit configuration in wireless G-mode. */
658 /* To check whether we shall force turn on TXOP configuration. */
659 if ((!rtlpriv->dm.disable_framebursting) &&
660 (rtlpriv->sec.pairwise_enc_algorithm == WEP40_ENCRYPTION ||
661 rtlpriv->sec.pairwise_enc_algorithm == WEP104_ENCRYPTION ||
662 rtlpriv->sec.pairwise_enc_algorithm == TKIP_ENCRYPTION)) {
663 /* Force TxOP limit to 0x005e for UL. */
664 if (!(edca_be_ul & 0xffff0000))
665 edca_be_ul |= 0x005e0000;
666 /* Force TxOP limit to 0x005e for DL. */
667 if (!(edca_be_dl & 0xffff0000))
668 edca_be_dl |= 0x005e0000;
669 }
670
671 if ((!rtlpriv->dm.is_any_nonbepkts) &&
672 (!rtlpriv->dm.disable_framebursting)) {
673 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
674 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
675 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
676 if (!rtlpriv->dm.is_cur_rdlstate ||
677 !rtlpriv->dm.current_turbo_edca) {
678 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
679 edca_be_dl);
680 rtlpriv->dm.is_cur_rdlstate = true;
681 }
682 } else {
683 if (rtlpriv->dm.is_cur_rdlstate ||
684 !rtlpriv->dm.current_turbo_edca) {
685 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
686 edca_be_ul);
687 rtlpriv->dm.is_cur_rdlstate = false;
688 }
689 }
690 rtlpriv->dm.current_turbo_edca = true;
691 } else {
692 if (rtlpriv->dm.current_turbo_edca) {
693 u8 tmp = AC0_BE;
694 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
695 (u8 *) (&tmp));
696 rtlpriv->dm.current_turbo_edca = false;
697 }
698 }
699
700exit:
701 rtlpriv->dm.is_any_nonbepkts = false;
702 last_txok_cnt = rtlpriv->stats.txbytesunicast;
703 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
704}
705
706static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw)
707{
708 struct rtl_priv *rtlpriv = rtl_priv(hw);
709 u8 index_mapping[RX_INDEX_MAPPING_NUM] = {
710 0x0f, 0x0f, 0x0d, 0x0c, 0x0b,
711 0x0a, 0x09, 0x08, 0x07, 0x06,
712 0x05, 0x04, 0x04, 0x03, 0x02
713 };
714 int i;
715 u32 u4tmp;
716
717 u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter -
718 rtlpriv->dm.thermalvalue_rxgain)]) << 12;
719 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
720 ("===> Rx Gain %x\n", u4tmp));
721 for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++)
722 rtl_set_rfreg(hw, i, 0x3C, BRFREGOFFSETMASK,
723 (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp);
724}
725
726static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg,
727 u8 *cck_index_old)
728{
729 struct rtl_priv *rtlpriv = rtl_priv(hw);
730 int i;
731 unsigned long flag = 0;
732 long temp_cck;
733
734 /* Query CCK default setting From 0xa24 */
735 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
736 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2,
737 BMASKDWORD) & BMASKCCK;
738 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
739 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
740 if (rtlpriv->dm.cck_inch14) {
741 if (!memcmp((void *)&temp_cck,
742 (void *)&cckswing_table_ch14[i][2], 4)) {
743 *cck_index_old = (u8) i;
744 RT_TRACE(rtlpriv,
745 COMP_POWER_TRACKING,
746 DBG_LOUD,
747 ("Initial reg0x%x = 0x%lx, "
748 "cck_index=0x%x, ch 14 %d\n",
749 RCCK0_TXFILTER2,
750 temp_cck, *cck_index_old,
751 rtlpriv->dm.cck_inch14));
752 break;
753 }
754 } else {
755 if (!memcmp((void *) &temp_cck,
756 &cckswing_table_ch1ch13[i][2], 4)) {
757 *cck_index_old = (u8) i;
758 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
759 DBG_LOUD,
760 ("Initial reg0x%x = 0x%lx, "
761 "cck_index = 0x%x, ch14 %d\n",
762 RCCK0_TXFILTER2,
763 temp_cck, *cck_index_old,
764 rtlpriv->dm.cck_inch14));
765 break;
766 }
767 }
768 }
769 *temp_cckg = temp_cck;
770}
771
772static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index,
773 bool *internal_pa, u8 thermalvalue, u8 delta,
774 u8 rf, struct rtl_efuse *rtlefuse,
775 struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy,
776 u8 index_mapping[5][INDEX_MAPPING_NUM],
777 u8 index_mapping_pa[8][INDEX_MAPPING_NUM])
778{
779 int i;
780 u8 index;
781 u8 offset = 0;
782
783 for (i = 0; i < rf; i++) {
784 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
785 rtlhal->interfaceindex == 1) /* MAC 1 5G */
786 *internal_pa = rtlefuse->internal_pa_5g[1];
787 else
788 *internal_pa = rtlefuse->internal_pa_5g[i];
789 if (*internal_pa) {
790 if (rtlhal->interfaceindex == 1 || i == rf)
791 offset = 4;
792 else
793 offset = 0;
794 if (rtlphy->current_channel >= 100 &&
795 rtlphy->current_channel <= 165)
796 offset += 2;
797 } else {
798 if (rtlhal->interfaceindex == 1 || i == rf)
799 offset = 2;
800 else
801 offset = 0;
802 }
803 if (thermalvalue > rtlefuse->eeprom_thermalmeter)
804 offset++;
805 if (*internal_pa) {
806 if (delta > INDEX_MAPPING_NUM - 1)
807 index = index_mapping_pa[offset]
808 [INDEX_MAPPING_NUM - 1];
809 else
810 index =
811 index_mapping_pa[offset][delta];
812 } else {
813 if (delta > INDEX_MAPPING_NUM - 1)
814 index =
815 index_mapping[offset][INDEX_MAPPING_NUM - 1];
816 else
817 index = index_mapping[offset][delta];
818 }
819 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
820 if (*internal_pa && thermalvalue > 0x12) {
821 ofdm_index[i] = rtlpriv->dm.ofdm_index[i] -
822 ((delta / 2) * 3 + (delta % 2));
823 } else {
824 ofdm_index[i] -= index;
825 }
826 } else {
827 ofdm_index[i] += index;
828 }
829 }
830}
831
832static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
833 struct ieee80211_hw *hw)
834{
835 struct rtl_priv *rtlpriv = rtl_priv(hw);
836 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
837 struct rtl_phy *rtlphy = &(rtlpriv->phy);
838 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
839 u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain;
840 u8 offset, thermalvalue_avg_count = 0;
841 u32 thermalvalue_avg = 0;
842 bool internal_pa = false;
843 long ele_a = 0, ele_d, temp_cck, val_x, value32;
844 long val_y, ele_c = 0;
845 u8 ofdm_index[2];
846 u8 cck_index = 0;
847 u8 ofdm_index_old[2];
848 u8 cck_index_old = 0;
849 u8 index;
850 int i;
851 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
852 u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf;
853 u8 indexforchannel =
854 rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel);
855 u8 index_mapping[5][INDEX_MAPPING_NUM] = {
856 /* 5G, path A/MAC 0, decrease power */
857 {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
858 /* 5G, path A/MAC 0, increase power */
859 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
860 /* 5G, path B/MAC 1, decrease power */
861 {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
862 /* 5G, path B/MAC 1, increase power */
863 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
864 /* 2.4G, for decreas power */
865 {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10},
866 };
867 u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = {
868 /* 5G, path A/MAC 0, ch36-64, decrease power */
869 {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
870 /* 5G, path A/MAC 0, ch36-64, increase power */
871 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
872 /* 5G, path A/MAC 0, ch100-165, decrease power */
873 {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15},
874 /* 5G, path A/MAC 0, ch100-165, increase power */
875 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
876 /* 5G, path B/MAC 1, ch36-64, decrease power */
877 {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
878 /* 5G, path B/MAC 1, ch36-64, increase power */
879 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
880 /* 5G, path B/MAC 1, ch100-165, decrease power */
881 {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14},
882 /* 5G, path B/MAC 1, ch100-165, increase power */
883 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
884 };
885
886 rtlpriv->dm.txpower_trackinginit = true;
887 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("\n"));
888 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800);
889 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
890 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
891 "eeprom_thermalmeter 0x%x\n", thermalvalue,
892 rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter));
893 rtl92d_phy_ap_calibrate(hw, (thermalvalue -
894 rtlefuse->eeprom_thermalmeter));
895 if (is2t)
896 rf = 2;
897 else
898 rf = 1;
899 if (thermalvalue) {
900 ele_d = rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
901 BMASKDWORD) & BMASKOFDM_D;
902 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
903 if (ele_d == (ofdmswing_table[i] & BMASKOFDM_D)) {
904 ofdm_index_old[0] = (u8) i;
905
906 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
907 ("Initial pathA ele_d reg0x%x = 0x%lx,"
908 " ofdm_index=0x%x\n",
909 ROFDM0_XATxIQIMBALANCE,
910 ele_d, ofdm_index_old[0]));
911 break;
912 }
913 }
914 if (is2t) {
915 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
916 BMASKDWORD) & BMASKOFDM_D;
917 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
918 if (ele_d ==
919 (ofdmswing_table[i] & BMASKOFDM_D)) {
920 ofdm_index_old[1] = (u8) i;
921 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
922 DBG_LOUD,
923 ("Initial pathB ele_d reg "
924 "0x%x = 0x%lx, ofdm_index "
925 "= 0x%x\n",
926 ROFDM0_XBTxIQIMBALANCE, ele_d,
927 ofdm_index_old[1]));
928 break;
929 }
930 }
931 }
932 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
933 rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old);
934 } else {
935 temp_cck = 0x090e1317;
936 cck_index_old = 12;
937 }
938
939 if (!rtlpriv->dm.thermalvalue) {
940 rtlpriv->dm.thermalvalue =
941 rtlefuse->eeprom_thermalmeter;
942 rtlpriv->dm.thermalvalue_lck = thermalvalue;
943 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
944 rtlpriv->dm.thermalvalue_rxgain =
945 rtlefuse->eeprom_thermalmeter;
946 for (i = 0; i < rf; i++)
947 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
948 rtlpriv->dm.cck_index = cck_index_old;
949 }
950 if (rtlhal->reloadtxpowerindex) {
951 for (i = 0; i < rf; i++)
952 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
953 rtlpriv->dm.cck_index = cck_index_old;
954 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
955 ("reload ofdm index for band switch\n"));
956 }
957 rtlpriv->dm.thermalvalue_avg
958 [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue;
959 rtlpriv->dm.thermalvalue_avg_index++;
960 if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM)
961 rtlpriv->dm.thermalvalue_avg_index = 0;
962 for (i = 0; i < AVG_THERMAL_NUM; i++) {
963 if (rtlpriv->dm.thermalvalue_avg[i]) {
964 thermalvalue_avg +=
965 rtlpriv->dm.thermalvalue_avg[i];
966 thermalvalue_avg_count++;
967 }
968 }
969 if (thermalvalue_avg_count)
970 thermalvalue = (u8) (thermalvalue_avg /
971 thermalvalue_avg_count);
972 if (rtlhal->reloadtxpowerindex) {
973 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
974 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
975 (rtlefuse->eeprom_thermalmeter - thermalvalue);
976 rtlhal->reloadtxpowerindex = false;
977 rtlpriv->dm.done_txpower = false;
978 } else if (rtlpriv->dm.done_txpower) {
979 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
980 (thermalvalue - rtlpriv->dm.thermalvalue) :
981 (rtlpriv->dm.thermalvalue - thermalvalue);
982 } else {
983 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
984 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
985 (rtlefuse->eeprom_thermalmeter - thermalvalue);
986 }
987 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
988 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
989 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
990 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
991 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
992 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
993 delta_rxgain =
994 (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ?
995 (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) :
996 (rtlpriv->dm.thermalvalue_rxgain - thermalvalue);
997 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
998 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x"
999 " eeprom_thermalmeter 0x%x delta 0x%x "
1000 "delta_lck 0x%x delta_iqk 0x%x\n",
1001 thermalvalue, rtlpriv->dm.thermalvalue,
1002 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
1003 delta_iqk));
1004 if ((delta_lck > rtlefuse->delta_lck) &&
1005 (rtlefuse->delta_lck != 0)) {
1006 rtlpriv->dm.thermalvalue_lck = thermalvalue;
1007 rtl92d_phy_lc_calibrate(hw);
1008 }
1009 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
1010 rtlpriv->dm.done_txpower = true;
1011 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
1012 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
1013 (rtlefuse->eeprom_thermalmeter - thermalvalue);
1014 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1015 offset = 4;
1016 if (delta > INDEX_MAPPING_NUM - 1)
1017 index = index_mapping[offset]
1018 [INDEX_MAPPING_NUM - 1];
1019 else
1020 index = index_mapping[offset][delta];
1021 if (thermalvalue > rtlpriv->dm.thermalvalue) {
1022 for (i = 0; i < rf; i++)
1023 ofdm_index[i] -= delta;
1024 cck_index -= delta;
1025 } else {
1026 for (i = 0; i < rf; i++)
1027 ofdm_index[i] += index;
1028 cck_index += index;
1029 }
1030 } else if (rtlhal->current_bandtype == BAND_ON_5G) {
1031 rtl92d_bandtype_5G(rtlhal, ofdm_index,
1032 &internal_pa, thermalvalue,
1033 delta, rf, rtlefuse, rtlpriv,
1034 rtlphy, index_mapping,
1035 index_mapping_internal_pa);
1036 }
1037 if (is2t) {
1038 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1039 ("temp OFDM_A_index=0x%x, OFDM_B_index"
1040 " = 0x%x,cck_index=0x%x\n",
1041 rtlpriv->dm.ofdm_index[0],
1042 rtlpriv->dm.ofdm_index[1],
1043 rtlpriv->dm.cck_index));
1044 } else {
1045 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1046 ("temp OFDM_A_index=0x%x,cck_index = "
1047 "0x%x\n",
1048 rtlpriv->dm.ofdm_index[0],
1049 rtlpriv->dm.cck_index));
1050 }
1051 for (i = 0; i < rf; i++) {
1052 if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1)
1053 ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1;
1054 else if (ofdm_index[i] < ofdm_min_index)
1055 ofdm_index[i] = ofdm_min_index;
1056 }
1057 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1058 if (cck_index > CCK_TABLE_SIZE - 1) {
1059 cck_index = CCK_TABLE_SIZE - 1;
1060 } else if (internal_pa ||
1061 rtlhal->current_bandtype ==
1062 BAND_ON_2_4G) {
1063 if (ofdm_index[i] <
1064 ofdm_min_index_internal_pa)
1065 ofdm_index[i] =
1066 ofdm_min_index_internal_pa;
1067 } else if (cck_index < 0) {
1068 cck_index = 0;
1069 }
1070 }
1071 if (is2t) {
1072 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1073 ("new OFDM_A_index=0x%x, OFDM_B_index "
1074 "= 0x%x, cck_index=0x%x\n",
1075 ofdm_index[0], ofdm_index[1],
1076 cck_index));
1077 } else {
1078 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1079 ("new OFDM_A_index=0x%x,cck_index = "
1080 "0x%x\n",
1081 ofdm_index[0], cck_index));
1082 }
1083 ele_d = (ofdmswing_table[(u8) ofdm_index[0]] &
1084 0xFFC00000) >> 22;
1085 val_x = rtlphy->iqk_matrix_regsetting
1086 [indexforchannel].value[0][0];
1087 val_y = rtlphy->iqk_matrix_regsetting
1088 [indexforchannel].value[0][1];
1089 if (val_x != 0) {
1090 if ((val_x & 0x00000200) != 0)
1091 val_x = val_x | 0xFFFFFC00;
1092 ele_a =
1093 ((val_x * ele_d) >> 8) & 0x000003FF;
1094
1095 /* new element C = element D x Y */
1096 if ((val_y & 0x00000200) != 0)
1097 val_y = val_y | 0xFFFFFC00;
1098 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
1099
1100 /* wirte new elements A, C, D to regC80 and
1101 * regC94, element B is always 0 */
1102 value32 = (ele_d << 22) | ((ele_c & 0x3F) <<
1103 16) | ele_a;
1104 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
1105 BMASKDWORD, value32);
1106
1107 value32 = (ele_c & 0x000003C0) >> 6;
1108 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, BMASKH4BITS,
1109 value32);
1110
1111 value32 = ((val_x * ele_d) >> 7) & 0x01;
1112 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
1113 value32);
1114
1115 } else {
1116 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
1117 BMASKDWORD,
1118 ofdmswing_table
1119 [(u8)ofdm_index[0]]);
1120 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, BMASKH4BITS,
1121 0x00);
1122 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1123 BIT(24), 0x00);
1124 }
1125
1126 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1127 ("TxPwrTracking for interface %d path A: X ="
1128 " 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = "
1129 "0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = "
1130 "0x%lx\n", rtlhal->interfaceindex,
1131 val_x, val_y, ele_a, ele_c, ele_d,
1132 val_x, val_y));
1133
1134 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1135 /* Adjust CCK according to IQK result */
1136 if (!rtlpriv->dm.cck_inch14) {
1137 rtl_write_byte(rtlpriv, 0xa22,
1138 cckswing_table_ch1ch13
1139 [(u8)cck_index][0]);
1140 rtl_write_byte(rtlpriv, 0xa23,
1141 cckswing_table_ch1ch13
1142 [(u8)cck_index][1]);
1143 rtl_write_byte(rtlpriv, 0xa24,
1144 cckswing_table_ch1ch13
1145 [(u8)cck_index][2]);
1146 rtl_write_byte(rtlpriv, 0xa25,
1147 cckswing_table_ch1ch13
1148 [(u8)cck_index][3]);
1149 rtl_write_byte(rtlpriv, 0xa26,
1150 cckswing_table_ch1ch13
1151 [(u8)cck_index][4]);
1152 rtl_write_byte(rtlpriv, 0xa27,
1153 cckswing_table_ch1ch13
1154 [(u8)cck_index][5]);
1155 rtl_write_byte(rtlpriv, 0xa28,
1156 cckswing_table_ch1ch13
1157 [(u8)cck_index][6]);
1158 rtl_write_byte(rtlpriv, 0xa29,
1159 cckswing_table_ch1ch13
1160 [(u8)cck_index][7]);
1161 } else {
1162 rtl_write_byte(rtlpriv, 0xa22,
1163 cckswing_table_ch14
1164 [(u8)cck_index][0]);
1165 rtl_write_byte(rtlpriv, 0xa23,
1166 cckswing_table_ch14
1167 [(u8)cck_index][1]);
1168 rtl_write_byte(rtlpriv, 0xa24,
1169 cckswing_table_ch14
1170 [(u8)cck_index][2]);
1171 rtl_write_byte(rtlpriv, 0xa25,
1172 cckswing_table_ch14
1173 [(u8)cck_index][3]);
1174 rtl_write_byte(rtlpriv, 0xa26,
1175 cckswing_table_ch14
1176 [(u8)cck_index][4]);
1177 rtl_write_byte(rtlpriv, 0xa27,
1178 cckswing_table_ch14
1179 [(u8)cck_index][5]);
1180 rtl_write_byte(rtlpriv, 0xa28,
1181 cckswing_table_ch14
1182 [(u8)cck_index][6]);
1183 rtl_write_byte(rtlpriv, 0xa29,
1184 cckswing_table_ch14
1185 [(u8)cck_index][7]);
1186 }
1187 }
1188 if (is2t) {
1189 ele_d = (ofdmswing_table[(u8) ofdm_index[1]] &
1190 0xFFC00000) >> 22;
1191 val_x = rtlphy->iqk_matrix_regsetting
1192 [indexforchannel].value[0][4];
1193 val_y = rtlphy->iqk_matrix_regsetting
1194 [indexforchannel].value[0][5];
1195 if (val_x != 0) {
1196 if ((val_x & 0x00000200) != 0)
1197 /* consider minus */
1198 val_x = val_x | 0xFFFFFC00;
1199 ele_a = ((val_x * ele_d) >> 8) &
1200 0x000003FF;
1201 /* new element C = element D x Y */
1202 if ((val_y & 0x00000200) != 0)
1203 val_y =
1204 val_y | 0xFFFFFC00;
1205 ele_c =
1206 ((val_y *
1207 ele_d) >> 8) & 0x00003FF;
1208 /* write new elements A, C, D to regC88
1209 * and regC9C, element B is always 0
1210 */
1211 value32 = (ele_d << 22) |
1212 ((ele_c & 0x3F) << 16) |
1213 ele_a;
1214 rtl_set_bbreg(hw,
1215 ROFDM0_XBTxIQIMBALANCE,
1216 BMASKDWORD, value32);
1217 value32 = (ele_c & 0x000003C0) >> 6;
1218 rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
1219 BMASKH4BITS, value32);
1220 value32 = ((val_x * ele_d) >> 7) & 0x01;
1221 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1222 BIT(28), value32);
1223 } else {
1224 rtl_set_bbreg(hw,
1225 ROFDM0_XBTxIQIMBALANCE,
1226 BMASKDWORD,
1227 ofdmswing_table
1228 [(u8) ofdm_index[1]]);
1229 rtl_set_bbreg(hw, ROFDM0_XDTxAFE,
1230 BMASKH4BITS, 0x00);
1231 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1232 BIT(28), 0x00);
1233 }
1234 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1235 ("TxPwrTracking path B: X = 0x%lx, "
1236 "Y = 0x%lx ele_A = 0x%lx ele_C = 0x"
1237 "%lx ele_D = 0x%lx 0xeb4 = 0x%lx "
1238 "0xebc = 0x%lx\n",
1239 val_x, val_y, ele_a, ele_c,
1240 ele_d, val_x, val_y));
1241 }
1242 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1243 ("TxPwrTracking 0xc80 = 0x%x, 0xc94 = "
1244 "0x%x RF 0x24 = 0x%x\n",
1245 rtl_get_bbreg(hw, 0xc80, BMASKDWORD),
1246 rtl_get_bbreg(hw, 0xc94, BMASKDWORD),
1247 rtl_get_rfreg(hw, RF90_PATH_A, 0x24,
1248 BRFREGOFFSETMASK)));
1249 }
1250 if ((delta_iqk > rtlefuse->delta_iqk) &&
1251 (rtlefuse->delta_iqk != 0)) {
1252 rtl92d_phy_reset_iqk_result(hw);
1253 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1254 rtl92d_phy_iq_calibrate(hw);
1255 }
1256 if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G
1257 && thermalvalue <= rtlefuse->eeprom_thermalmeter) {
1258 rtlpriv->dm.thermalvalue_rxgain = thermalvalue;
1259 rtl92d_dm_rxgain_tracking_thermalmeter(hw);
1260 }
1261 if (rtlpriv->dm.txpower_track_control)
1262 rtlpriv->dm.thermalvalue = thermalvalue;
1263 }
1264
1265 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
1266}
1267
1268static void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1269{
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271
1272 rtlpriv->dm.txpower_tracking = true;
1273 rtlpriv->dm.txpower_trackinginit = false;
1274 rtlpriv->dm.txpower_track_control = true;
1275 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1276 ("pMgntInfo->txpower_tracking = %d\n",
1277 rtlpriv->dm.txpower_tracking));
1278}
1279
1280void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw)
1281{
1282 struct rtl_priv *rtlpriv = rtl_priv(hw);
1283 static u8 tm_trigger;
1284
1285 if (!rtlpriv->dm.txpower_tracking)
1286 return;
1287
1288 if (!tm_trigger) {
1289 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) |
1290 BIT(16), 0x03);
1291 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1292 ("Trigger 92S Thermal Meter!!\n"));
1293 tm_trigger = 1;
1294 return;
1295 } else {
1296 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1297 ("Schedule TxPowerTracking direct call!!\n"));
1298 rtl92d_dm_txpower_tracking_callback_thermalmeter(hw);
1299 tm_trigger = 0;
1300 }
1301}
1302
1303void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1304{
1305 struct rtl_priv *rtlpriv = rtl_priv(hw);
1306 struct rate_adaptive *ra = &(rtlpriv->ra);
1307
1308 ra->ratr_state = DM_RATR_STA_INIT;
1309 ra->pre_ratr_state = DM_RATR_STA_INIT;
1310 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1311 rtlpriv->dm.useramask = true;
1312 else
1313 rtlpriv->dm.useramask = false;
1314}
1315
1316void rtl92d_dm_init(struct ieee80211_hw *hw)
1317{
1318 struct rtl_priv *rtlpriv = rtl_priv(hw);
1319
1320 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1321 rtl92d_dm_diginit(hw);
1322 rtl92d_dm_init_dynamic_txpower(hw);
1323 rtl92d_dm_init_edca_turbo(hw);
1324 rtl92d_dm_init_rate_adaptive_mask(hw);
1325 rtl92d_dm_initialize_txpower_tracking(hw);
1326}
1327
1328void rtl92d_dm_watchdog(struct ieee80211_hw *hw)
1329{
1330 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1331 bool fw_current_inpsmode = false;
1332 bool fwps_awake = true;
1333
1334 /* 1. RF is OFF. (No need to do DM.)
1335 * 2. Fw is under power saving mode for FwLPS.
1336 * (Prevent from SW/FW I/O racing.)
1337 * 3. IPS workitem is scheduled. (Prevent from IPS sequence
1338 * to be swapped with DM.
1339 * 4. RFChangeInProgress is TRUE.
1340 * (Prevent from broken by IPS/HW/SW Rf off.) */
1341
1342 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1343 fwps_awake) && (!ppsc->rfchange_inprogress)) {
1344 rtl92d_dm_pwdb_monitor(hw);
1345 rtl92d_dm_false_alarm_counter_statistics(hw);
1346 rtl92d_dm_find_minimum_rssi(hw);
1347 rtl92d_dm_dig(hw);
1348 /* rtl92d_dm_dynamic_bb_powersaving(hw); */
1349 rtl92d_dm_dynamic_txpower(hw);
1350 /* rtl92d_dm_check_txpower_tracking_thermal_meter(hw); */
1351 /* rtl92d_dm_refresh_rate_adaptive_mask(hw); */
1352 /* rtl92d_dm_interrupt_migration(hw); */
1353 rtl92d_dm_check_edca_turbo(hw);
1354 }
1355}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/dm.h b/drivers/net/wireless/rtlwifi/rtl8192de/dm.h
new file mode 100644
index 000000000000..69354657f0f5
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/dm.h
@@ -0,0 +1,212 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_DM_H__
31#define __RTL92C_DM_H__
32
33#define HAL_DM_DIG_DISABLE BIT(0)
34#define HAL_DM_HIPWR_DISABLE BIT(1)
35
36#define OFDM_TABLE_LENGTH 37
37#define OFDM_TABLE_SIZE_92D 43
38#define CCK_TABLE_LENGTH 33
39
40#define CCK_TABLE_SIZE 33
41
42#define BW_AUTO_SWITCH_HIGH_LOW 25
43#define BW_AUTO_SWITCH_LOW_HIGH 30
44
45#define DM_DIG_THRESH_HIGH 40
46#define DM_DIG_THRESH_LOW 35
47
48#define DM_FALSEALARM_THRESH_LOW 400
49#define DM_FALSEALARM_THRESH_HIGH 1000
50
51#define DM_DIG_MAX 0x3e
52#define DM_DIG_MIN 0x1c
53
54#define DM_DIG_FA_UPPER 0x32
55#define DM_DIG_FA_LOWER 0x20
56#define DM_DIG_FA_TH0 0x100
57#define DM_DIG_FA_TH1 0x400
58#define DM_DIG_FA_TH2 0x600
59
60#define DM_DIG_BACKOFF_MAX 12
61#define DM_DIG_BACKOFF_MIN -4
62#define DM_DIG_BACKOFF_DEFAULT 10
63
64#define RXPATHSELECTION_SS_TH_lOW 30
65#define RXPATHSELECTION_DIFF_TH 18
66
67#define DM_RATR_STA_INIT 0
68#define DM_RATR_STA_HIGH 1
69#define DM_RATR_STA_MIDDLE 2
70#define DM_RATR_STA_LOW 3
71
72#define CTS2SELF_THVAL 30
73#define REGC38_TH 20
74
75#define WAIOTTHVAL 25
76
77#define TXHIGHPWRLEVEL_NORMAL 0
78#define TXHIGHPWRLEVEL_LEVEL1 1
79#define TXHIGHPWRLEVEL_LEVEL2 2
80#define TXHIGHPWRLEVEL_BT1 3
81#define TXHIGHPWRLEVEL_BT2 4
82
83#define DM_TYPE_BYFW 0
84#define DM_TYPE_BYDRIVER 1
85
86#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
87#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
88#define INDEX_MAPPING_NUM 13
89
90struct ps_t {
91 u8 pre_ccastate;
92 u8 cur_ccasate;
93
94 u8 pre_rfstate;
95 u8 cur_rfstate;
96
97 long rssi_val_min;
98};
99
100struct dig_t {
101 u8 dig_enable_flag;
102 u8 dig_ext_port_stage;
103
104 u32 rssi_lowthresh;
105 u32 rssi_highthresh;
106
107 u32 fa_lowthresh;
108 u32 fa_highthresh;
109
110 u8 cursta_connectctate;
111 u8 presta_connectstate;
112 u8 curmultista_connectstate;
113
114 u8 pre_igvalue;
115 u8 cur_igvalue;
116
117 char backoff_val;
118 char backoff_val_range_max;
119 char backoff_val_range_min;
120 u8 rx_gain_range_max;
121 u8 rx_gain_range_min;
122 u8 min_undecorated_pwdb_for_dm;
123 long last_min_undecorated_pwdb_for_dm;
124
125 u8 pre_cck_pd_state;
126 u8 cur_cck_pd_state;
127
128 u8 pre_cck_fa_state;
129 u8 cur_cck_fa_state;
130
131 u8 pre_ccastate;
132 u8 cur_ccasate;
133
134 u8 large_fa_hit;
135 u8 forbidden_igi;
136 u32 recover_cnt;
137};
138
139struct swat {
140 u8 failure_cnt;
141 u8 try_flag;
142 u8 stop_trying;
143 long pre_rssi;
144 long trying_threshold;
145 u8 cur_antenna;
146 u8 pre_antenna;
147};
148
149enum tag_dynamic_init_gain_operation_type_definition {
150 DIG_TYPE_THRESH_HIGH = 0,
151 DIG_TYPE_THRESH_LOW = 1,
152 DIG_TYPE_BACKOFF = 2,
153 DIG_TYPE_RX_GAIN_MIN = 3,
154 DIG_TYPE_RX_GAIN_MAX = 4,
155 DIG_TYPE_ENABLE = 5,
156 DIG_TYPE_DISABLE = 6,
157 DIG_OP_TYPE_MAX
158};
159
160enum tag_cck_packet_detection_threshold_type_definition {
161 CCK_PD_STAGE_LOWRSSI = 0,
162 CCK_PD_STAGE_HIGHRSSI = 1,
163 CCK_FA_STAGE_LOW = 2,
164 CCK_FA_STAGE_HIGH = 3,
165 CCK_PD_STAGE_MAX = 4,
166};
167
168enum dm_1r_cca {
169 CCA_1R = 0,
170 CCA_2R = 1,
171 CCA_MAX = 2,
172};
173
174enum dm_rf {
175 RF_SAVE = 0,
176 RF_NORMAL = 1,
177 RF_MAX = 2,
178};
179
180enum dm_sw_ant_switch {
181 ANS_ANTENNA_B = 1,
182 ANS_ANTENNA_A = 2,
183 ANS_ANTENNA_MAX = 3,
184};
185
186enum dm_dig_ext_port_alg {
187 DIG_EXT_PORT_STAGE_0 = 0,
188 DIG_EXT_PORT_STAGE_1 = 1,
189 DIG_EXT_PORT_STAGE_2 = 2,
190 DIG_EXT_PORT_STAGE_3 = 3,
191 DIG_EXT_PORT_STAGE_MAX = 4,
192};
193
194enum dm_dig_connect {
195 DIG_STA_DISCONNECT = 0,
196 DIG_STA_CONNECT = 1,
197 DIG_STA_BEFORE_CONNECT = 2,
198 DIG_MULTISTA_DISCONNECT = 3,
199 DIG_MULTISTA_CONNECT = 4,
200 DIG_CONNECT_MAX
201};
202
203extern struct dig_t de_digtable;
204
205void rtl92d_dm_init(struct ieee80211_hw *hw);
206void rtl92d_dm_watchdog(struct ieee80211_hw *hw);
207void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw);
208void rtl92d_dm_write_dig(struct ieee80211_hw *hw);
209void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw);
210void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
211
212#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/fw.c b/drivers/net/wireless/rtlwifi/rtl8192de/fw.c
new file mode 100644
index 000000000000..82f060bdbc0b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/fw.c
@@ -0,0 +1,790 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "reg.h"
34#include "def.h"
35#include "fw.h"
36#include "sw.h"
37
38static bool _rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv)
39{
40 return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ?
41 true : false;
42}
43
44static void _rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable)
45{
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 u8 tmp;
48
49 if (enable) {
50 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
51 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04);
52 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
53 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
54 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
55 rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
56 } else {
57 tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
58 rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
59 /* Reserved for fw extension.
60 * 0x81[7] is used for mac0 status ,
61 * so don't write this reg here
62 * rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);*/
63 }
64}
65
66static void _rtl92d_fw_block_write(struct ieee80211_hw *hw,
67 const u8 *buffer, u32 size)
68{
69 struct rtl_priv *rtlpriv = rtl_priv(hw);
70 u32 blocksize = sizeof(u32);
71 u8 *bufferptr = (u8 *) buffer;
72 u32 *pu4BytePtr = (u32 *) buffer;
73 u32 i, offset, blockCount, remainSize;
74
75 blockCount = size / blocksize;
76 remainSize = size % blocksize;
77 for (i = 0; i < blockCount; i++) {
78 offset = i * blocksize;
79 rtl_write_dword(rtlpriv, (FW_8192D_START_ADDRESS + offset),
80 *(pu4BytePtr + i));
81 }
82 if (remainSize) {
83 offset = blockCount * blocksize;
84 bufferptr += offset;
85 for (i = 0; i < remainSize; i++) {
86 rtl_write_byte(rtlpriv, (FW_8192D_START_ADDRESS +
87 offset + i), *(bufferptr + i));
88 }
89 }
90}
91
92static void _rtl92d_fw_page_write(struct ieee80211_hw *hw,
93 u32 page, const u8 *buffer, u32 size)
94{
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
96 u8 value8;
97 u8 u8page = (u8) (page & 0x07);
98
99 value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
100 rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
101 _rtl92d_fw_block_write(hw, buffer, size);
102}
103
104static void _rtl92d_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
105{
106 u32 fwlen = *pfwlen;
107 u8 remain = (u8) (fwlen % 4);
108
109 remain = (remain == 0) ? 0 : (4 - remain);
110 while (remain > 0) {
111 pfwbuf[fwlen] = 0;
112 fwlen++;
113 remain--;
114 }
115 *pfwlen = fwlen;
116}
117
118static void _rtl92d_write_fw(struct ieee80211_hw *hw,
119 enum version_8192d version, u8 *buffer, u32 size)
120{
121 struct rtl_priv *rtlpriv = rtl_priv(hw);
122 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
123 u8 *bufferPtr = (u8 *) buffer;
124 u32 pagenums, remainSize;
125 u32 page, offset;
126
127 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, ("FW size is %d bytes,\n", size));
128 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
129 _rtl92d_fill_dummy(bufferPtr, &size);
130 pagenums = size / FW_8192D_PAGE_SIZE;
131 remainSize = size % FW_8192D_PAGE_SIZE;
132 if (pagenums > 8) {
133 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
134 ("Page numbers should not greater then 8\n"));
135 }
136 for (page = 0; page < pagenums; page++) {
137 offset = page * FW_8192D_PAGE_SIZE;
138 _rtl92d_fw_page_write(hw, page, (bufferPtr + offset),
139 FW_8192D_PAGE_SIZE);
140 }
141 if (remainSize) {
142 offset = pagenums * FW_8192D_PAGE_SIZE;
143 page = pagenums;
144 _rtl92d_fw_page_write(hw, page, (bufferPtr + offset),
145 remainSize);
146 }
147}
148
149static int _rtl92d_fw_free_to_go(struct ieee80211_hw *hw)
150{
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 u32 counter = 0;
153 u32 value32;
154
155 do {
156 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
157 } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) &&
158 (!(value32 & FWDL_ChkSum_rpt)));
159 if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) {
160 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
161 ("chksum report faill ! REG_MCUFWDL:0x%08x .\n",
162 value32));
163 return -EIO;
164 }
165 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
166 ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32));
167 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
168 value32 |= MCUFWDL_RDY;
169 rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
170 return 0;
171}
172
173void rtl92d_firmware_selfreset(struct ieee80211_hw *hw)
174{
175 struct rtl_priv *rtlpriv = rtl_priv(hw);
176 u8 u1b_tmp;
177 u8 delay = 100;
178
179 /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */
180 rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
181 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
182 while (u1b_tmp & BIT(2)) {
183 delay--;
184 if (delay == 0)
185 break;
186 udelay(50);
187 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
188 }
189 RT_ASSERT((delay > 0), ("8051 reset failed!\n"));
190 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
191 ("=====> 8051 reset success (%d) .\n", delay));
192}
193
194static int _rtl92d_fw_init(struct ieee80211_hw *hw)
195{
196 struct rtl_priv *rtlpriv = rtl_priv(hw);
197 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
198 u32 counter;
199
200 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG, ("FW already have download\n"));
201 /* polling for FW ready */
202 counter = 0;
203 do {
204 if (rtlhal->interfaceindex == 0) {
205 if (rtl_read_byte(rtlpriv, FW_MAC0_READY) &
206 MAC0_READY) {
207 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
208 ("Polling FW ready success!! "
209 "REG_MCUFWDL: 0x%x .\n",
210 rtl_read_byte(rtlpriv,
211 FW_MAC0_READY)));
212 return 0;
213 }
214 udelay(5);
215 } else {
216 if (rtl_read_byte(rtlpriv, FW_MAC1_READY) &
217 MAC1_READY) {
218 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
219 ("Polling FW ready success!! "
220 "REG_MCUFWDL: 0x%x .\n",
221 rtl_read_byte(rtlpriv,
222 FW_MAC1_READY)));
223 return 0;
224 }
225 udelay(5);
226 }
227 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
228
229 if (rtlhal->interfaceindex == 0) {
230 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
231 ("Polling FW ready fail!! MAC0 FW init not ready: "
232 "0x%x .\n",
233 rtl_read_byte(rtlpriv, FW_MAC0_READY)));
234 } else {
235 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
236 ("Polling FW ready fail!! MAC1 FW init not ready: "
237 "0x%x .\n",
238 rtl_read_byte(rtlpriv, FW_MAC1_READY)));
239 }
240 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
241 ("Polling FW ready fail!! REG_MCUFWDL:0x%08ul .\n",
242 rtl_read_dword(rtlpriv, REG_MCUFWDL)));
243 return -1;
244}
245
246int rtl92d_download_fw(struct ieee80211_hw *hw)
247{
248 struct rtl_priv *rtlpriv = rtl_priv(hw);
249 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
250 u8 *pfwheader;
251 u8 *pfwdata;
252 u32 fwsize;
253 int err;
254 enum version_8192d version = rtlhal->version;
255 u8 value;
256 u32 count;
257 bool fw_downloaded = false, fwdl_in_process = false;
258 unsigned long flags;
259
260 if (!rtlhal->pfirmware)
261 return 1;
262 fwsize = rtlhal->fwsize;
263 pfwheader = (u8 *) rtlhal->pfirmware;
264 pfwdata = (u8 *) rtlhal->pfirmware;
265 rtlhal->fw_version = (u16) GET_FIRMWARE_HDR_VERSION(pfwheader);
266 rtlhal->fw_subversion = (u16) GET_FIRMWARE_HDR_SUB_VER(pfwheader);
267 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, (" FirmwareVersion(%d),"
268 "FirmwareSubVersion(%d), Signature(%#x)\n",
269 rtlhal->fw_version, rtlhal->fw_subversion,
270 GET_FIRMWARE_HDR_SIGNATURE(pfwheader)));
271 if (IS_FW_HEADER_EXIST(pfwheader)) {
272 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
273 ("Shift 32 bytes for FW header!!\n"));
274 pfwdata = pfwdata + 32;
275 fwsize = fwsize - 32;
276 }
277
278 spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
279 fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv);
280 if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5))
281 fwdl_in_process = true;
282 else
283 fwdl_in_process = false;
284 if (fw_downloaded) {
285 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
286 goto exit;
287 } else if (fwdl_in_process) {
288 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
289 for (count = 0; count < 5000; count++) {
290 udelay(500);
291 spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
292 fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv);
293 if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5))
294 fwdl_in_process = true;
295 else
296 fwdl_in_process = false;
297 spin_unlock_irqrestore(&globalmutex_for_fwdownload,
298 flags);
299 if (fw_downloaded)
300 goto exit;
301 else if (!fwdl_in_process)
302 break;
303 else
304 RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
305 ("Wait for another mac "
306 "download fw\n"));
307 }
308 spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
309 value = rtl_read_byte(rtlpriv, 0x1f);
310 value |= BIT(5);
311 rtl_write_byte(rtlpriv, 0x1f, value);
312 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
313 } else {
314 value = rtl_read_byte(rtlpriv, 0x1f);
315 value |= BIT(5);
316 rtl_write_byte(rtlpriv, 0x1f, value);
317 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
318 }
319
320 /* If 8051 is running in RAM code, driver should
321 * inform Fw to reset by itself, or it will cause
322 * download Fw fail.*/
323 /* 8051 RAM code */
324 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
325 rtl92d_firmware_selfreset(hw);
326 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
327 }
328 _rtl92d_enable_fw_download(hw, true);
329 _rtl92d_write_fw(hw, version, pfwdata, fwsize);
330 _rtl92d_enable_fw_download(hw, false);
331 spin_lock_irqsave(&globalmutex_for_fwdownload, flags);
332 err = _rtl92d_fw_free_to_go(hw);
333 /* download fw over,clear 0x1f[5] */
334 value = rtl_read_byte(rtlpriv, 0x1f);
335 value &= (~BIT(5));
336 rtl_write_byte(rtlpriv, 0x1f, value);
337 spin_unlock_irqrestore(&globalmutex_for_fwdownload, flags);
338 if (err) {
339 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
340 ("fw is not ready to run!\n"));
341 goto exit;
342 } else {
343 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
344 ("fw is ready to run!\n"));
345 }
346exit:
347 err = _rtl92d_fw_init(hw);
348 return err;
349}
350
351static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
352{
353 struct rtl_priv *rtlpriv = rtl_priv(hw);
354 u8 val_hmetfr;
355 bool result = false;
356
357 val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
358 if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
359 result = true;
360 return result;
361}
362
363static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw,
364 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
365{
366 struct rtl_priv *rtlpriv = rtl_priv(hw);
367 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
368 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
369 u8 boxnum;
370 u16 box_reg = 0, box_extreg = 0;
371 u8 u1b_tmp;
372 bool isfw_read = false;
373 u8 buf_index = 0;
374 bool bwrite_sucess = false;
375 u8 wait_h2c_limmit = 100;
376 u8 wait_writeh2c_limmit = 100;
377 u8 boxcontent[4], boxextcontent[2];
378 u32 h2c_waitcounter = 0;
379 unsigned long flag;
380 u8 idx;
381
382 if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) {
383 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
384 ("Return as RF is off!!!\n"));
385 return;
386 }
387 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("come in\n"));
388 while (true) {
389 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
390 if (rtlhal->h2c_setinprogress) {
391 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
392 ("H2C set in progress! Wait to set.."
393 "element_id(%d).\n", element_id));
394
395 while (rtlhal->h2c_setinprogress) {
396 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
397 flag);
398 h2c_waitcounter++;
399 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
400 ("Wait 100 us (%d times)...\n",
401 h2c_waitcounter));
402 udelay(100);
403
404 if (h2c_waitcounter > 1000)
405 return;
406
407 spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
408 flag);
409 }
410 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
411 } else {
412 rtlhal->h2c_setinprogress = true;
413 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
414 break;
415 }
416 }
417 while (!bwrite_sucess) {
418 wait_writeh2c_limmit--;
419 if (wait_writeh2c_limmit == 0) {
420 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
421 ("Write H2C fail because no trigger "
422 "for FW INT!\n"));
423 break;
424 }
425 boxnum = rtlhal->last_hmeboxnum;
426 switch (boxnum) {
427 case 0:
428 box_reg = REG_HMEBOX_0;
429 box_extreg = REG_HMEBOX_EXT_0;
430 break;
431 case 1:
432 box_reg = REG_HMEBOX_1;
433 box_extreg = REG_HMEBOX_EXT_1;
434 break;
435 case 2:
436 box_reg = REG_HMEBOX_2;
437 box_extreg = REG_HMEBOX_EXT_2;
438 break;
439 case 3:
440 box_reg = REG_HMEBOX_3;
441 box_extreg = REG_HMEBOX_EXT_3;
442 break;
443 default:
444 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
445 ("switch case not process\n"));
446 break;
447 }
448 isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
449 while (!isfw_read) {
450 wait_h2c_limmit--;
451 if (wait_h2c_limmit == 0) {
452 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
453 ("Wating too long for FW read "
454 "clear HMEBox(%d)!\n", boxnum));
455 break;
456 }
457 udelay(10);
458 isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum);
459 u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
460 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
461 ("Wating for FW read clear HMEBox(%d)!!! "
462 "0x1BF = %2x\n", boxnum, u1b_tmp));
463 }
464 if (!isfw_read) {
465 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
466 ("Write H2C register BOX[%d] fail!!!!! "
467 "Fw do not read.\n", boxnum));
468 break;
469 }
470 memset(boxcontent, 0, sizeof(boxcontent));
471 memset(boxextcontent, 0, sizeof(boxextcontent));
472 boxcontent[0] = element_id;
473 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
474 ("Write element_id box_reg(%4x) = %2x\n",
475 box_reg, element_id));
476 switch (cmd_len) {
477 case 1:
478 boxcontent[0] &= ~(BIT(7));
479 memcpy(boxcontent + 1, cmdbuffer + buf_index, 1);
480 for (idx = 0; idx < 4; idx++)
481 rtl_write_byte(rtlpriv, box_reg + idx,
482 boxcontent[idx]);
483 break;
484 case 2:
485 boxcontent[0] &= ~(BIT(7));
486 memcpy(boxcontent + 1, cmdbuffer + buf_index, 2);
487 for (idx = 0; idx < 4; idx++)
488 rtl_write_byte(rtlpriv, box_reg + idx,
489 boxcontent[idx]);
490 break;
491 case 3:
492 boxcontent[0] &= ~(BIT(7));
493 memcpy(boxcontent + 1, cmdbuffer + buf_index, 3);
494 for (idx = 0; idx < 4; idx++)
495 rtl_write_byte(rtlpriv, box_reg + idx,
496 boxcontent[idx]);
497 break;
498 case 4:
499 boxcontent[0] |= (BIT(7));
500 memcpy(boxextcontent, cmdbuffer + buf_index, 2);
501 memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2);
502 for (idx = 0; idx < 2; idx++)
503 rtl_write_byte(rtlpriv, box_extreg + idx,
504 boxextcontent[idx]);
505 for (idx = 0; idx < 4; idx++)
506 rtl_write_byte(rtlpriv, box_reg + idx,
507 boxcontent[idx]);
508 break;
509 case 5:
510 boxcontent[0] |= (BIT(7));
511 memcpy(boxextcontent, cmdbuffer + buf_index, 2);
512 memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3);
513 for (idx = 0; idx < 2; idx++)
514 rtl_write_byte(rtlpriv, box_extreg + idx,
515 boxextcontent[idx]);
516 for (idx = 0; idx < 4; idx++)
517 rtl_write_byte(rtlpriv, box_reg + idx,
518 boxcontent[idx]);
519 break;
520 default:
521 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
522 ("switch case not process\n"));
523 break;
524 }
525 bwrite_sucess = true;
526 rtlhal->last_hmeboxnum = boxnum + 1;
527 if (rtlhal->last_hmeboxnum == 4)
528 rtlhal->last_hmeboxnum = 0;
529 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
530 ("pHalData->last_hmeboxnum = %d\n",
531 rtlhal->last_hmeboxnum));
532 }
533 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
534 rtlhal->h2c_setinprogress = false;
535 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
536 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("go out\n"));
537}
538
539void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw,
540 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
541{
542 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
543 u32 tmp_cmdbuf[2];
544
545 if (rtlhal->fw_ready == false) {
546 RT_ASSERT(false, ("return H2C cmd because of Fw "
547 "download fail!!!\n"));
548 return;
549 }
550 memset(tmp_cmdbuf, 0, 8);
551 memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
552 _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
553 return;
554}
555
556void rtl92d_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
557{
558 struct rtl_priv *rtlpriv = rtl_priv(hw);
559 u8 u1_h2c_set_pwrmode[3] = { 0 };
560 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
561
562 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("FW LPS mode = %d\n", mode));
563 SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
564 SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, 1);
565 SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
566 ppsc->reg_max_lps_awakeintvl);
567 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
568 "rtl92d_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
569 u1_h2c_set_pwrmode, 3);
570 rtl92d_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
571}
572
573static bool _rtl92d_cmd_send_packet(struct ieee80211_hw *hw,
574 struct sk_buff *skb)
575{
576 struct rtl_priv *rtlpriv = rtl_priv(hw);
577 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
578 struct rtl8192_tx_ring *ring;
579 struct rtl_tx_desc *pdesc;
580 u8 idx = 0;
581 unsigned long flags;
582 struct sk_buff *pskb;
583
584 ring = &rtlpci->tx_ring[BEACON_QUEUE];
585 pskb = __skb_dequeue(&ring->queue);
586 if (pskb)
587 kfree_skb(pskb);
588 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
589 pdesc = &ring->desc[idx];
590 /* discard output from call below */
591 rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
592 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
593 __skb_queue_tail(&ring->queue, skb);
594 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
595 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
596 return true;
597}
598
599#define BEACON_PG 0 /*->1 */
600#define PSPOLL_PG 2
601#define NULL_PG 3
602#define PROBERSP_PG 4 /*->5 */
603#define TOTAL_RESERVED_PKT_LEN 768
604
605static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
606 /* page 0 beacon */
607 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
608 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
609 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
610 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
611 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
612 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
613 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
614 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
615 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
616 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
617 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
618 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
619 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
620 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
621 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
622 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
623
624 /* page 1 beacon */
625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
626 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
627 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
628 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
629 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
631 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
632 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
633 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
634 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
635 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
636 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
637 0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
638 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
639 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
640 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
641
642 /* page 2 ps-poll */
643 0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
644 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
645 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
646 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
647 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
648 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
649 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
650 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
651 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
652 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
653 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
654 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
655 0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
656 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
657 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
658 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
659
660 /* page 3 null */
661 0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
662 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
663 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
664 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
666 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
667 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
668 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
669 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
670 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
671 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
672 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
673 0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
674 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
675 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
676 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
677
678 /* page 4 probe_resp */
679 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
680 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
681 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
682 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
683 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
684 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
685 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
686 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
687 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
688 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
689 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
690 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
691 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
692 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
693 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
694 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
695
696 /* page 5 probe_resp */
697 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
698 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
699 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
700 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
701 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
702 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
703 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
704 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
705 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
706 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
707 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
708 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
709 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
710 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
711 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
712 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
713};
714
715void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished)
716{
717 struct rtl_priv *rtlpriv = rtl_priv(hw);
718 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
719 struct sk_buff *skb = NULL;
720 u32 totalpacketlen;
721 bool rtstatus;
722 u8 u1RsvdPageLoc[3] = { 0 };
723 bool dlok = false;
724 u8 *beacon;
725 u8 *p_pspoll;
726 u8 *nullfunc;
727 u8 *p_probersp;
728 /*---------------------------------------------------------
729 (1) beacon
730 ---------------------------------------------------------*/
731 beacon = &reserved_page_packet[BEACON_PG * 128];
732 SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
733 SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
734 /*-------------------------------------------------------
735 (2) ps-poll
736 --------------------------------------------------------*/
737 p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
738 SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
739 SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
740 SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
741 SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
742 /*--------------------------------------------------------
743 (3) null data
744 ---------------------------------------------------------*/
745 nullfunc = &reserved_page_packet[NULL_PG * 128];
746 SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
747 SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
748 SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
749 SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
750 /*---------------------------------------------------------
751 (4) probe response
752 ----------------------------------------------------------*/
753 p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
754 SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
755 SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
756 SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
757 SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
758 totalpacketlen = TOTAL_RESERVED_PKT_LEN;
759 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
760 "rtl92d_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
761 &reserved_page_packet[0], totalpacketlen);
762 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
763 "rtl92d_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
764 u1RsvdPageLoc, 3);
765 skb = dev_alloc_skb(totalpacketlen);
766 memcpy((u8 *) skb_put(skb, totalpacketlen), &reserved_page_packet,
767 totalpacketlen);
768 rtstatus = _rtl92d_cmd_send_packet(hw, skb);
769
770 if (rtstatus)
771 dlok = true;
772 if (dlok) {
773 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
774 ("Set RSVD page location to Fw.\n"));
775 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
776 "H2C_RSVDPAGE:\n", u1RsvdPageLoc, 3);
777 rtl92d_fill_h2c_cmd(hw, H2C_RSVDPAGE,
778 sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
779 } else
780 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
781 ("Set RSVD page location to Fw FAIL!!!!!!.\n"));
782}
783
784void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
785{
786 u8 u1_joinbssrpt_parm[1] = {0};
787
788 SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
789 rtl92d_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
790}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/fw.h b/drivers/net/wireless/rtlwifi/rtl8192de/fw.h
new file mode 100644
index 000000000000..0c4d489eaa48
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/fw.h
@@ -0,0 +1,155 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D__FW__H__
31#define __RTL92D__FW__H__
32
33#define FW_8192D_START_ADDRESS 0x1000
34#define FW_8192D_PAGE_SIZE 4096
35#define FW_8192D_POLLING_TIMEOUT_COUNT 1000
36
37#define IS_FW_HEADER_EXIST(_pfwhdr) \
38 ((GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x92C0 || \
39 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x88C0 || \
40 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D0 || \
41 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D1 || \
42 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D2 || \
43 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D3)
44
45/* Define a macro that takes an le32 word, converts it to host ordering,
46 * right shifts by a specified count, creates a mask of the specified
47 * bit count, and extracts that number of bits.
48 */
49
50#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
51 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
52 BIT_LEN_MASK_32(__mask))
53
54/* Firmware Header(8-byte alinment required) */
55/* --- LONG WORD 0 ---- */
56#define GET_FIRMWARE_HDR_SIGNATURE(__fwhdr) \
57 SHIFT_AND_MASK_LE(__fwhdr, 0, 16)
58#define GET_FIRMWARE_HDR_CATEGORY(__fwhdr) \
59 SHIFT_AND_MASK_LE(__fwhdr, 16, 8)
60#define GET_FIRMWARE_HDR_FUNCTION(__fwhdr) \
61 SHIFT_AND_MASK_LE(__fwhdr, 24, 8)
62#define GET_FIRMWARE_HDR_VERSION(__fwhdr) \
63 SHIFT_AND_MASK_LE(__fwhdr + 4, 0, 16)
64#define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \
65 SHIFT_AND_MASK_LE(__fwhdr + 4, 16, 8)
66#define GET_FIRMWARE_HDR_RSVD1(__fwhdr) \
67 SHIFT_AND_MASK_LE(__fwhdr + 4, 24, 8)
68
69/* --- LONG WORD 1 ---- */
70#define GET_FIRMWARE_HDR_MONTH(__fwhdr) \
71 SHIFT_AND_MASK_LE(__fwhdr + 8, 0, 8)
72#define GET_FIRMWARE_HDR_DATE(__fwhdr) \
73 SHIFT_AND_MASK_LE(__fwhdr + 8, 8, 8)
74#define GET_FIRMWARE_HDR_HOUR(__fwhdr) \
75 SHIFT_AND_MASK_LE(__fwhdr + 8, 16, 8)
76#define GET_FIRMWARE_HDR_MINUTE(__fwhdr) \
77 SHIFT_AND_MASK_LE(__fwhdr + 8, 24, 8)
78#define GET_FIRMWARE_HDR_ROMCODE_SIZE(__fwhdr) \
79 SHIFT_AND_MASK_LE(__fwhdr + 12, 0, 16)
80#define GET_FIRMWARE_HDR_RSVD2(__fwhdr) \
81 SHIFT_AND_MASK_LE(__fwhdr + 12, 16, 16)
82
83/* --- LONG WORD 2 ---- */
84#define GET_FIRMWARE_HDR_SVN_IDX(__fwhdr) \
85 SHIFT_AND_MASK_LE(__fwhdr + 16, 0, 32)
86#define GET_FIRMWARE_HDR_RSVD3(__fwhdr) \
87 SHIFT_AND_MASK_LE(__fwhdr + 20, 0, 32)
88
89/* --- LONG WORD 3 ---- */
90#define GET_FIRMWARE_HDR_RSVD4(__fwhdr) \
91 SHIFT_AND_MASK_LE(__fwhdr + 24, 0, 32)
92#define GET_FIRMWARE_HDR_RSVD5(__fwhdr) \
93 SHIFT_AND_MASK_LE(__fwhdr + 28, 0, 32)
94
95#define pagenum_128(_len) \
96 (u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0))
97
98#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
99 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
100#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val) \
101 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 0, 8, __val)
102#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__ph2ccmd, __val) \
103 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 2, 0, 8, __val)
104#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
105 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
106#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
107 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
108#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
109 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 0, 8, __val)
110#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
111 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 2, 0, 8, __val)
112
113struct rtl92d_firmware_header {
114 u16 signature;
115 u8 category;
116 u8 function;
117 u16 version;
118 u8 subversion;
119 u8 rsvd1;
120
121 u8 month;
122 u8 date;
123 u8 hour;
124 u8 minute;
125 u16 ramcodeSize;
126 u16 rsvd2;
127
128 u32 svnindex;
129 u32 rsvd3;
130
131 u32 rsvd4;
132 u32 rsvd5;
133};
134
135enum rtl8192d_h2c_cmd {
136 H2C_AP_OFFLOAD = 0,
137 H2C_SETPWRMODE = 1,
138 H2C_JOINBSSRPT = 2,
139 H2C_RSVDPAGE = 3,
140 H2C_RSSI_REPORT = 5,
141 H2C_RA_MASK = 6,
142 H2C_MAC_MODE_SEL = 9,
143 H2C_PWRM = 15,
144 MAX_H2CCMD
145};
146
147int rtl92d_download_fw(struct ieee80211_hw *hw);
148void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
149 u32 cmd_len, u8 *p_cmdbuffer);
150void rtl92d_firmware_selfreset(struct ieee80211_hw *hw);
151void rtl92d_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
152void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
153void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
154
155#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
new file mode 100644
index 000000000000..0073cf106af2
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/hw.c
@@ -0,0 +1,2329 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../regd.h"
34#include "../cam.h"
35#include "../ps.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "fw.h"
42#include "led.h"
43#include "sw.h"
44#include "hw.h"
45
46u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
47{
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49 u32 value;
50
51 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
52 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
53 udelay(10);
54 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
55 return value;
56}
57
58void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
59 u16 offset, u32 value, u8 direct)
60{
61 struct rtl_priv *rtlpriv = rtl_priv(hw);
62
63 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
64 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
65 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
66}
67
68static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
69 u8 set_bits, u8 clear_bits)
70{
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73
74 rtlpci->reg_bcn_ctrl_val |= set_bits;
75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
76 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
77}
78
79static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
80{
81 struct rtl_priv *rtlpriv = rtl_priv(hw);
82 u8 tmp1byte;
83
84 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
85 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
86 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
89 tmp1byte &= ~(BIT(0));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
91}
92
93static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
94{
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
96 u8 tmp1byte;
97
98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
100 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
101 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
102 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
103 tmp1byte |= BIT(0);
104 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
105}
106
107static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
108{
109 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
110}
111
112static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
113{
114 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
115}
116
117void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
118{
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
121 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
122
123 switch (variable) {
124 case HW_VAR_RCR:
125 *((u32 *) (val)) = rtlpci->receive_config;
126 break;
127 case HW_VAR_RF_STATE:
128 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
129 break;
130 case HW_VAR_FWLPS_RF_ON:{
131 enum rf_pwrstate rfState;
132 u32 val_rcr;
133
134 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
135 (u8 *) (&rfState));
136 if (rfState == ERFOFF) {
137 *((bool *) (val)) = true;
138 } else {
139 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
140 val_rcr &= 0x00070000;
141 if (val_rcr)
142 *((bool *) (val)) = false;
143 else
144 *((bool *) (val)) = true;
145 }
146 break;
147 }
148 case HW_VAR_FW_PSMODE_STATUS:
149 *((bool *) (val)) = ppsc->fw_current_inpsmode;
150 break;
151 case HW_VAR_CORRECT_TSF:{
152 u64 tsf;
153 u32 *ptsf_low = (u32 *)&tsf;
154 u32 *ptsf_high = ((u32 *)&tsf) + 1;
155
156 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
157 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
158 *((u64 *) (val)) = tsf;
159 break;
160 }
161 case HW_VAR_INT_MIGRATION:
162 *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
163 break;
164 case HW_VAR_INT_AC:
165 *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
166 break;
167 default:
168 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
169 ("switch case not process\n"));
170 break;
171 }
172}
173
174void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
175{
176 struct rtl_priv *rtlpriv = rtl_priv(hw);
177 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
178 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
180 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
181 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
182 u8 idx;
183
184 switch (variable) {
185 case HW_VAR_ETHER_ADDR:
186 for (idx = 0; idx < ETH_ALEN; idx++) {
187 rtl_write_byte(rtlpriv, (REG_MACID + idx),
188 val[idx]);
189 }
190 break;
191 case HW_VAR_BASIC_RATE: {
192 u16 rate_cfg = ((u16 *) val)[0];
193 u8 rate_index = 0;
194
195 rate_cfg = rate_cfg & 0x15f;
196 if (mac->vendor == PEER_CISCO &&
197 ((rate_cfg & 0x150) == 0))
198 rate_cfg |= 0x01;
199 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
200 rtl_write_byte(rtlpriv, REG_RRSR + 1,
201 (rate_cfg >> 8) & 0xff);
202 while (rate_cfg > 0x1) {
203 rate_cfg = (rate_cfg >> 1);
204 rate_index++;
205 }
206 if (rtlhal->fw_version > 0xe)
207 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
208 rate_index);
209 break;
210 }
211 case HW_VAR_BSSID:
212 for (idx = 0; idx < ETH_ALEN; idx++) {
213 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
214 val[idx]);
215 }
216 break;
217 case HW_VAR_SIFS:
218 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
219 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
220 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
221 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
222 if (!mac->ht_enable)
223 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
224 0x0e0e);
225 else
226 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
227 *((u16 *) val));
228 break;
229 case HW_VAR_SLOT_TIME: {
230 u8 e_aci;
231
232 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
233 ("HW_VAR_SLOT_TIME %x\n", val[0]));
234 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
235 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
236 rtlpriv->cfg->ops->set_hw_reg(hw,
237 HW_VAR_AC_PARAM,
238 (u8 *) (&e_aci));
239 break;
240 }
241 case HW_VAR_ACK_PREAMBLE: {
242 u8 reg_tmp;
243 u8 short_preamble = (bool) (*(u8 *) val);
244
245 reg_tmp = (mac->cur_40_prime_sc) << 5;
246 if (short_preamble)
247 reg_tmp |= 0x80;
248 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
249 break;
250 }
251 case HW_VAR_AMPDU_MIN_SPACE: {
252 u8 min_spacing_to_set;
253 u8 sec_min_space;
254
255 min_spacing_to_set = *((u8 *) val);
256 if (min_spacing_to_set <= 7) {
257 sec_min_space = 0;
258 if (min_spacing_to_set < sec_min_space)
259 min_spacing_to_set = sec_min_space;
260 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
261 min_spacing_to_set);
262 *val = min_spacing_to_set;
263 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
264 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
265 mac->min_space_cfg));
266 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
267 mac->min_space_cfg);
268 }
269 break;
270 }
271 case HW_VAR_SHORTGI_DENSITY: {
272 u8 density_to_set;
273
274 density_to_set = *((u8 *) val);
275 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
276 mac->min_space_cfg |= (density_to_set << 3);
277 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
278 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
279 mac->min_space_cfg));
280 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
281 mac->min_space_cfg);
282 break;
283 }
284 case HW_VAR_AMPDU_FACTOR: {
285 u8 factor_toset;
286 u32 regtoSet;
287 u8 *ptmp_byte = NULL;
288 u8 index;
289
290 if (rtlhal->macphymode == DUALMAC_DUALPHY)
291 regtoSet = 0xb9726641;
292 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
293 regtoSet = 0x66626641;
294 else
295 regtoSet = 0xb972a841;
296 factor_toset = *((u8 *) val);
297 if (factor_toset <= 3) {
298 factor_toset = (1 << (factor_toset + 2));
299 if (factor_toset > 0xf)
300 factor_toset = 0xf;
301 for (index = 0; index < 4; index++) {
302 ptmp_byte = (u8 *) (&regtoSet) + index;
303 if ((*ptmp_byte & 0xf0) >
304 (factor_toset << 4))
305 *ptmp_byte = (*ptmp_byte & 0x0f)
306 | (factor_toset << 4);
307 if ((*ptmp_byte & 0x0f) > factor_toset)
308 *ptmp_byte = (*ptmp_byte & 0xf0)
309 | (factor_toset);
310 }
311 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
314 factor_toset));
315 }
316 break;
317 }
318 case HW_VAR_AC_PARAM: {
319 u8 e_aci = *((u8 *) val);
320 rtl92d_dm_init_edca_turbo(hw);
321 if (rtlpci->acm_method != eAcmWay2_SW)
322 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
323 (u8 *) (&e_aci));
324 break;
325 }
326 case HW_VAR_ACM_CTRL: {
327 u8 e_aci = *((u8 *) val);
328 union aci_aifsn *p_aci_aifsn =
329 (union aci_aifsn *)(&(mac->ac[0].aifs));
330 u8 acm = p_aci_aifsn->f.acm;
331 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
332
333 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
334 if (acm) {
335 switch (e_aci) {
336 case AC0_BE:
337 acm_ctrl |= ACMHW_BEQEN;
338 break;
339 case AC2_VI:
340 acm_ctrl |= ACMHW_VIQEN;
341 break;
342 case AC3_VO:
343 acm_ctrl |= ACMHW_VOQEN;
344 break;
345 default:
346 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
347 ("HW_VAR_ACM_CTRL acm set "
348 "failed: eACI is %d\n", acm));
349 break;
350 }
351 } else {
352 switch (e_aci) {
353 case AC0_BE:
354 acm_ctrl &= (~ACMHW_BEQEN);
355 break;
356 case AC2_VI:
357 acm_ctrl &= (~ACMHW_VIQEN);
358 break;
359 case AC3_VO:
360 acm_ctrl &= (~ACMHW_VOQEN);
361 break;
362 default:
363 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
364 ("switch case not process\n"));
365 break;
366 }
367 }
368 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
369 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
370 "Write 0x%X\n", acm_ctrl));
371 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
372 break;
373 }
374 case HW_VAR_RCR:
375 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
376 rtlpci->receive_config = ((u32 *) (val))[0];
377 break;
378 case HW_VAR_RETRY_LIMIT: {
379 u8 retry_limit = ((u8 *) (val))[0];
380
381 rtl_write_word(rtlpriv, REG_RL,
382 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
383 retry_limit << RETRY_LIMIT_LONG_SHIFT);
384 break;
385 }
386 case HW_VAR_DUAL_TSF_RST:
387 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
388 break;
389 case HW_VAR_EFUSE_BYTES:
390 rtlefuse->efuse_usedbytes = *((u16 *) val);
391 break;
392 case HW_VAR_EFUSE_USAGE:
393 rtlefuse->efuse_usedpercentage = *((u8 *) val);
394 break;
395 case HW_VAR_IO_CMD:
396 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
397 break;
398 case HW_VAR_WPA_CONFIG:
399 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
400 break;
401 case HW_VAR_SET_RPWM:
402 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (u8 *) (val));
403 break;
404 case HW_VAR_H2C_FW_PWRMODE:
405 break;
406 case HW_VAR_FW_PSMODE_STATUS:
407 ppsc->fw_current_inpsmode = *((bool *) val);
408 break;
409 case HW_VAR_H2C_FW_JOINBSSRPT: {
410 u8 mstatus = (*(u8 *) val);
411 u8 tmp_regcr, tmp_reg422;
412 bool recover = false;
413
414 if (mstatus == RT_MEDIA_CONNECT) {
415 rtlpriv->cfg->ops->set_hw_reg(hw,
416 HW_VAR_AID, NULL);
417 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
418 rtl_write_byte(rtlpriv, REG_CR + 1,
419 (tmp_regcr | BIT(0)));
420 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
421 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
422 tmp_reg422 = rtl_read_byte(rtlpriv,
423 REG_FWHW_TXQ_CTRL + 2);
424 if (tmp_reg422 & BIT(6))
425 recover = true;
426 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
427 tmp_reg422 & (~BIT(6)));
428 rtl92d_set_fw_rsvdpagepkt(hw, 0);
429 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
430 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
431 if (recover)
432 rtl_write_byte(rtlpriv,
433 REG_FWHW_TXQ_CTRL + 2,
434 tmp_reg422);
435 rtl_write_byte(rtlpriv, REG_CR + 1,
436 (tmp_regcr & ~(BIT(0))));
437 }
438 rtl92d_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
439 break;
440 }
441 case HW_VAR_AID: {
442 u16 u2btmp;
443 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
444 u2btmp &= 0xC000;
445 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
446 mac->assoc_id));
447 break;
448 }
449 case HW_VAR_CORRECT_TSF: {
450 u8 btype_ibss = ((u8 *) (val))[0];
451
452 if (btype_ibss)
453 _rtl92de_stop_tx_beacon(hw);
454 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
455 rtl_write_dword(rtlpriv, REG_TSFTR,
456 (u32) (mac->tsf & 0xffffffff));
457 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
458 (u32) ((mac->tsf >> 32) & 0xffffffff));
459 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
460 if (btype_ibss)
461 _rtl92de_resume_tx_beacon(hw);
462
463 break;
464 }
465 case HW_VAR_INT_MIGRATION: {
466 bool int_migration = *(bool *) (val);
467
468 if (int_migration) {
469 /* Set interrrupt migration timer and
470 * corresponging Tx/Rx counter.
471 * timer 25ns*0xfa0=100us for 0xf packets.
472 * 0x306:Rx, 0x307:Tx */
473 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
474 rtlpriv->dm.interrupt_migration = int_migration;
475 } else {
476 /* Reset all interrupt migration settings. */
477 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
478 rtlpriv->dm.interrupt_migration = int_migration;
479 }
480 break;
481 }
482 case HW_VAR_INT_AC: {
483 bool disable_ac_int = *((bool *) val);
484
485 /* Disable four ACs interrupts. */
486 if (disable_ac_int) {
487 /* Disable VO, VI, BE and BK four AC interrupts
488 * to gain more efficient CPU utilization.
489 * When extremely highly Rx OK occurs,
490 * we will disable Tx interrupts.
491 */
492 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
493 RT_AC_INT_MASKS);
494 rtlpriv->dm.disable_tx_int = disable_ac_int;
495 /* Enable four ACs interrupts. */
496 } else {
497 rtlpriv->cfg->ops->update_interrupt_mask(hw,
498 RT_AC_INT_MASKS, 0);
499 rtlpriv->dm.disable_tx_int = disable_ac_int;
500 }
501 break;
502 }
503 default:
504 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
505 ("switch case not process\n"));
506 break;
507 }
508}
509
510static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
511{
512 struct rtl_priv *rtlpriv = rtl_priv(hw);
513 bool status = true;
514 long count = 0;
515 u32 value = _LLT_INIT_ADDR(address) |
516 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
517
518 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
519 do {
520 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
521 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
522 break;
523 if (count > POLLING_LLT_THRESHOLD) {
524 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
525 ("Failed to polling write LLT done at "
526 "address %d!\n", address));
527 status = false;
528 break;
529 }
530 } while (++count);
531 return status;
532}
533
534static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
535{
536 struct rtl_priv *rtlpriv = rtl_priv(hw);
537 unsigned short i;
538 u8 txpktbuf_bndy;
539 u8 maxPage;
540 bool status;
541 u32 value32; /* High+low page number */
542 u8 value8; /* normal page number */
543
544 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
545 maxPage = 255;
546 txpktbuf_bndy = 246;
547 value8 = 0;
548 value32 = 0x80bf0d29;
549 } else if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
550 maxPage = 127;
551 txpktbuf_bndy = 123;
552 value8 = 0;
553 value32 = 0x80750005;
554 }
555
556 /* Set reserved page for each queue */
557 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */
558 /* load RQPN */
559 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
560 rtl_write_dword(rtlpriv, REG_RQPN, value32);
561
562 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
563 /* TXRKTBUG_PG_BNDY */
564 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
565 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
566 txpktbuf_bndy));
567
568 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */
569 /* Beacon Head for TXDMA */
570 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
571
572 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */
573 /* BCNQ_PGBNDY */
574 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
575 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
576
577 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */
578 /* WMAC_LBK_BF_HD */
579 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
580
581 /* Set Tx/Rx page size (Tx must be 128 Bytes, */
582 /* Rx can be 64,128,256,512,1024 bytes) */
583 /* 16. PBP [7:0] = 0x11 */
584 /* TRX page size */
585 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
586
587 /* 17. DRV_INFO_SZ = 0x04 */
588 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
589
590 /* 18. LLT_table_init(Adapter); */
591 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
592 status = _rtl92de_llt_write(hw, i, i + 1);
593 if (true != status)
594 return status;
595 }
596
597 /* end of list */
598 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
599 if (true != status)
600 return status;
601
602 /* Make the other pages as ring buffer */
603 /* This ring buffer is used as beacon buffer if we */
604 /* config this MAC as two MAC transfer. */
605 /* Otherwise used as local loopback buffer. */
606 for (i = txpktbuf_bndy; i < maxPage; i++) {
607 status = _rtl92de_llt_write(hw, i, (i + 1));
608 if (true != status)
609 return status;
610 }
611
612 /* Let last entry point to the start entry of ring buffer */
613 status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
614 if (true != status)
615 return status;
616
617 return true;
618}
619
620static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
621{
622 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
623 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
624 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
625 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
626
627 if (rtlpci->up_first_time)
628 return;
629 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
630 rtl92de_sw_led_on(hw, pLed0);
631 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
632 rtl92de_sw_led_on(hw, pLed0);
633 else
634 rtl92de_sw_led_off(hw, pLed0);
635}
636
637static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
638{
639 struct rtl_priv *rtlpriv = rtl_priv(hw);
640 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
641 unsigned char bytetmp;
642 unsigned short wordtmp;
643 u16 retry;
644
645 rtl92d_phy_set_poweron(hw);
646 /* Add for resume sequence of power domain according
647 * to power document V11. Chapter V.11.... */
648 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */
649 /* unlock ISO/CLK/Power control register */
650 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
651 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
652
653 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */
654 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */
655 /* 3. delay (1ms) this is not necessary when initially power on */
656
657 /* C. Resume Sequence */
658 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */
659 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
660
661 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */
662 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
663
664 /* c. DRV runs power on init flow */
665
666 /* auto enable WLAN */
667 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */
668 /* Power On Reset for MAC Block */
669 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
670 udelay(2);
671 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
672 udelay(2);
673
674 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
675 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
676 udelay(50);
677 retry = 0;
678 while ((bytetmp & BIT(0)) && retry < 1000) {
679 retry++;
680 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
681 udelay(50);
682 }
683
684 /* Enable Radio off, GPIO, and LED function */
685 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */
686 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
687
688 /* release RF digital isolation */
689 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */
690 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
691 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
692 udelay(2);
693
694 /* make sure that BB reset OK. */
695 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
696
697 /* Disable REG_CR before enable it to assure reset */
698 rtl_write_word(rtlpriv, REG_CR, 0x0);
699
700 /* Release MAC IO register reset */
701 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
702
703 /* clear stopping tx/rx dma */
704 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
705
706 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
707
708 /* System init */
709 /* 18. LLT_table_init(Adapter); */
710 if (_rtl92de_llt_table_init(hw) == false)
711 return false;
712
713 /* Clear interrupt and enable interrupt */
714 /* 19. HISR 0x124[31:0] = 0xffffffff; */
715 /* HISRE 0x12C[7:0] = 0xFF */
716 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
717 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
718
719 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */
720 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */
721 /* The IMR should be enabled later after all init sequence
722 * is finished. */
723
724 /* 22. PCIE configuration space configuration */
725 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */
726 /* and PCIe gated clock function is enabled. */
727 /* PCIE configuration space will be written after
728 * all init sequence.(Or by BIOS) */
729
730 rtl92d_phy_config_maccoexist_rfpage(hw);
731
732 /* THe below section is not related to power document Vxx . */
733 /* This is only useful for driver and OS setting. */
734 /* -------------------Software Relative Setting---------------------- */
735 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
736 wordtmp &= 0xf;
737 wordtmp |= 0xF771;
738 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
739
740 /* Reported Tx status from HW for rate adaptive. */
741 /* This should be realtive to power on step 14. But in document V11 */
742 /* still not contain the description.!!! */
743 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
744
745 /* Set Tx/Rx page size (Tx must be 128 Bytes,
746 * Rx can be 64,128,256,512,1024 bytes) */
747 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
748
749 /* Set RCR register */
750 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
751 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
752
753 /* Set TCR register */
754 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
755
756 /* disable earlymode */
757 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
758
759 /* Set TX/RX descriptor physical address(from OS API). */
760 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
761 rtlpci->tx_ring[BEACON_QUEUE].dma);
762 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
763 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
764 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
765 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
766 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
767 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
768 /* Set RX Desc Address */
769 rtl_write_dword(rtlpriv, REG_RX_DESA,
770 rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
771
772 /* if we want to support 64 bit DMA, we should set it here,
773 * but now we do not support 64 bit DMA*/
774
775 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
776
777 /* Reset interrupt migration setting when initialization */
778 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
779
780 /* Reconsider when to do this operation after asking HWSD. */
781 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
782 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
783 do {
784 retry++;
785 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
786 } while ((retry < 200) && !(bytetmp & BIT(7)));
787
788 /* After MACIO reset,we must refresh LED state. */
789 _rtl92de_gen_refresh_led_state(hw);
790
791 /* Reset H2C protection register */
792 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
793
794 return true;
795}
796
797static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
798{
799 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
800 struct rtl_priv *rtlpriv = rtl_priv(hw);
801 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
802 u8 reg_bw_opmode = BW_OPMODE_20MHZ;
803 u32 reg_rrsr;
804
805 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
806 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
807 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
808 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
809 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
810 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
811 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
812 rtl_write_word(rtlpriv, REG_RL, 0x0707);
813 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
814 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
815 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
816 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
817 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
818 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
819 /* Aggregation threshold */
820 if (rtlhal->macphymode == DUALMAC_DUALPHY)
821 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
822 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
823 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
824 else
825 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
826 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
827 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
828 rtlpci->reg_bcn_ctrl_val = 0x1f;
829 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
830 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
831 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
832 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
833 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
834 /* For throughput */
835 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
836 /* ACKTO for IOT issue. */
837 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
838 /* Set Spec SIFS (used in NAV) */
839 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
840 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
841 /* Set SIFS for CCK */
842 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
843 /* Set SIFS for OFDM */
844 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
845 /* Set Multicast Address. */
846 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
847 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
848 switch (rtlpriv->phy.rf_type) {
849 case RF_1T2R:
850 case RF_1T1R:
851 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
852 break;
853 case RF_2T2R:
854 case RF_2T2R_GREEN:
855 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
856 break;
857 }
858}
859
860static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
861{
862 struct rtl_priv *rtlpriv = rtl_priv(hw);
863 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
864
865 rtl_write_byte(rtlpriv, 0x34b, 0x93);
866 rtl_write_word(rtlpriv, 0x350, 0x870c);
867 rtl_write_byte(rtlpriv, 0x352, 0x1);
868 if (ppsc->support_backdoor)
869 rtl_write_byte(rtlpriv, 0x349, 0x1b);
870 else
871 rtl_write_byte(rtlpriv, 0x349, 0x03);
872 rtl_write_word(rtlpriv, 0x350, 0x2718);
873 rtl_write_byte(rtlpriv, 0x352, 0x1);
874}
875
876void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
877{
878 struct rtl_priv *rtlpriv = rtl_priv(hw);
879 u8 sec_reg_value;
880
881 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
882 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
883 rtlpriv->sec.pairwise_enc_algorithm,
884 rtlpriv->sec.group_enc_algorithm));
885 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
886 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
887 ("not open hw encryption\n"));
888 return;
889 }
890 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
891 if (rtlpriv->sec.use_defaultkey) {
892 sec_reg_value |= SCR_TXUSEDK;
893 sec_reg_value |= SCR_RXUSEDK;
894 }
895 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
896 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
897 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
898 ("The SECR-value %x\n", sec_reg_value));
899 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
900}
901
902int rtl92de_hw_init(struct ieee80211_hw *hw)
903{
904 struct rtl_priv *rtlpriv = rtl_priv(hw);
905 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
906 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
907 struct rtl_phy *rtlphy = &(rtlpriv->phy);
908 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
909 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
910 bool rtstatus = true;
911 u8 tmp_u1b;
912 int i;
913 int err;
914 unsigned long flags;
915
916 rtlpci->being_init_adapter = true;
917 rtlpci->init_ready = false;
918 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
919 /* we should do iqk after disable/enable */
920 rtl92d_phy_reset_iqk_result(hw);
921 /* rtlpriv->intf_ops->disable_aspm(hw); */
922 rtstatus = _rtl92de_init_mac(hw);
923 if (rtstatus != true) {
924 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
925 err = 1;
926 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
927 return err;
928 }
929 err = rtl92d_download_fw(hw);
930 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
931 if (err) {
932 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
933 ("Failed to download FW. Init HW "
934 "without FW..\n"));
935 rtlhal->fw_ready = false;
936 return 1;
937 } else {
938 rtlhal->fw_ready = true;
939 }
940 rtlhal->last_hmeboxnum = 0;
941 rtlpriv->psc.fw_current_inpsmode = false;
942
943 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
944 tmp_u1b = tmp_u1b | 0x30;
945 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
946
947 if (rtlhal->earlymode_enable) {
948 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
949 ("EarlyMode Enabled!!!\n"));
950
951 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
952 tmp_u1b = tmp_u1b | 0x1f;
953 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
954
955 rtl_write_byte(rtlpriv, 0x4d3, 0x80);
956
957 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
958 tmp_u1b = tmp_u1b | 0x40;
959 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
960 }
961
962 if (mac->rdg_en) {
963 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
964 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
965 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
966 }
967
968 rtl92d_phy_mac_config(hw);
969 /* because last function modify RCR, so we update
970 * rcr var here, or TP will unstable for receive_config
971 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
972 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
973 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
974 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
975
976 rtl92d_phy_bb_config(hw);
977
978 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
979 /* set before initialize RF */
980 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
981
982 /* config RF */
983 rtl92d_phy_rf_config(hw);
984
985 /* After read predefined TXT, we must set BB/MAC/RF
986 * register as our requirement */
987 /* After load BB,RF params,we need do more for 92D. */
988 rtl92d_update_bbrf_configuration(hw);
989 /* set default value after initialize RF, */
990 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
991 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
992 RF_CHNLBW, BRFREGOFFSETMASK);
993 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
994 RF_CHNLBW, BRFREGOFFSETMASK);
995
996 /*---- Set CCK and OFDM Block "ON"----*/
997 if (rtlhal->current_bandtype == BAND_ON_2_4G)
998 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
999 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1000 if (rtlhal->interfaceindex == 0) {
1001 /* RFPGA0_ANALOGPARAMETER2: cck clock select,
1002 * set to 20MHz by default */
1003 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1004 BIT(11), 3);
1005 } else {
1006 /* Mac1 */
1007 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
1008 BIT(10), 3);
1009 }
1010
1011 _rtl92de_hw_configure(hw);
1012
1013 /* reset hw sec */
1014 rtl_cam_reset_all_entry(hw);
1015 rtl92de_enable_hw_security_config(hw);
1016
1017 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1018 /* TX power index for different rate set. */
1019 rtl92d_phy_get_hw_reg_originalvalue(hw);
1020 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
1021
1022 ppsc->rfpwr_state = ERFON;
1023
1024 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1025
1026 _rtl92de_enable_aspm_back_door(hw);
1027 /* rtlpriv->intf_ops->enable_aspm(hw); */
1028
1029 rtl92d_dm_init(hw);
1030 rtlpci->being_init_adapter = false;
1031
1032 if (ppsc->rfpwr_state == ERFON) {
1033 rtl92d_phy_lc_calibrate(hw);
1034 /* 5G and 2.4G must wait sometime to let RF LO ready */
1035 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1036 u32 tmp_rega;
1037 for (i = 0; i < 10000; i++) {
1038 udelay(MAX_STALL_TIME);
1039
1040 tmp_rega = rtl_get_rfreg(hw,
1041 (enum radio_path)RF90_PATH_A,
1042 0x2a, BMASKDWORD);
1043
1044 if (((tmp_rega & BIT(11)) == BIT(11)))
1045 break;
1046 }
1047 /* check that loop was successful. If not, exit now */
1048 if (i == 10000) {
1049 rtlpci->init_ready = false;
1050 return 1;
1051 }
1052 }
1053 }
1054 rtlpci->init_ready = true;
1055 return err;
1056}
1057
1058static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1059{
1060 struct rtl_priv *rtlpriv = rtl_priv(hw);
1061 enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1062 u32 value32;
1063
1064 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1065 if (!(value32 & 0x000f0000)) {
1066 version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1067 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("TEST CHIP!!!\n"));
1068 } else {
1069 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1070 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Normal CHIP!!!\n"));
1071 }
1072 return version;
1073}
1074
1075static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1076 enum nl80211_iftype type)
1077{
1078 struct rtl_priv *rtlpriv = rtl_priv(hw);
1079 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1080 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1081 u8 bcnfunc_enable;
1082
1083 bt_msr &= 0xfc;
1084
1085 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1086 type == NL80211_IFTYPE_STATION) {
1087 _rtl92de_stop_tx_beacon(hw);
1088 _rtl92de_enable_bcn_sub_func(hw);
1089 } else if (type == NL80211_IFTYPE_ADHOC ||
1090 type == NL80211_IFTYPE_AP) {
1091 _rtl92de_resume_tx_beacon(hw);
1092 _rtl92de_disable_bcn_sub_func(hw);
1093 } else {
1094 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1095 ("Set HW_VAR_MEDIA_STATUS: No such media "
1096 "status(%x).\n", type));
1097 }
1098 bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1099 switch (type) {
1100 case NL80211_IFTYPE_UNSPECIFIED:
1101 bt_msr |= MSR_NOLINK;
1102 ledaction = LED_CTL_LINK;
1103 bcnfunc_enable &= 0xF7;
1104 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1105 ("Set Network type to NO LINK!\n"));
1106 break;
1107 case NL80211_IFTYPE_ADHOC:
1108 bt_msr |= MSR_ADHOC;
1109 bcnfunc_enable |= 0x08;
1110 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1111 ("Set Network type to Ad Hoc!\n"));
1112 break;
1113 case NL80211_IFTYPE_STATION:
1114 bt_msr |= MSR_INFRA;
1115 ledaction = LED_CTL_LINK;
1116 bcnfunc_enable &= 0xF7;
1117 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1118 ("Set Network type to STA!\n"));
1119 break;
1120 case NL80211_IFTYPE_AP:
1121 bt_msr |= MSR_AP;
1122 bcnfunc_enable |= 0x08;
1123 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1124 ("Set Network type to AP!\n"));
1125 break;
1126 default:
1127 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1128 ("Network type %d not support!\n", type));
1129 return 1;
1130 break;
1131
1132 }
1133 rtl_write_byte(rtlpriv, REG_CR + 2, bt_msr);
1134 rtlpriv->cfg->ops->led_control(hw, ledaction);
1135 if ((bt_msr & 0xfc) == MSR_AP)
1136 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1137 else
1138 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1139 return 0;
1140}
1141
1142void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1143{
1144 struct rtl_priv *rtlpriv = rtl_priv(hw);
1145 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1146 u32 reg_rcr = rtlpci->receive_config;
1147
1148 if (rtlpriv->psc.rfpwr_state != ERFON)
1149 return;
1150 if (check_bssid) {
1151 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1152 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1153 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1154 } else if (check_bssid == false) {
1155 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1156 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1157 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1158 }
1159}
1160
1161int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1162{
1163 struct rtl_priv *rtlpriv = rtl_priv(hw);
1164
1165 if (_rtl92de_set_media_status(hw, type))
1166 return -EOPNOTSUPP;
1167
1168 /* check bssid */
1169 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1170 if (type != NL80211_IFTYPE_AP)
1171 rtl92de_set_check_bssid(hw, true);
1172 } else {
1173 rtl92de_set_check_bssid(hw, false);
1174 }
1175 return 0;
1176}
1177
1178/* do iqk or reload iqk */
1179/* windows just rtl92d_phy_reload_iqk_setting in set channel,
1180 * but it's very strict for time sequence so we add
1181 * rtl92d_phy_reload_iqk_setting here */
1182void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1183{
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1186 u8 indexforchannel;
1187 u8 channel = rtlphy->current_channel;
1188
1189 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1190 if (!rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done) {
1191 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1192 ("Do IQK for channel:%d.\n", channel));
1193 rtl92d_phy_iq_calibrate(hw);
1194 }
1195}
1196
1197/* don't set REG_EDCA_BE_PARAM here because
1198 * mac80211 will send pkt when scan */
1199void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1200{
1201 struct rtl_priv *rtlpriv = rtl_priv(hw);
1202 rtl92d_dm_init_edca_turbo(hw);
1203 return;
1204 switch (aci) {
1205 case AC1_BK:
1206 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1207 break;
1208 case AC0_BE:
1209 break;
1210 case AC2_VI:
1211 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1212 break;
1213 case AC3_VO:
1214 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1215 break;
1216 default:
1217 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1218 break;
1219 }
1220}
1221
1222void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1223{
1224 struct rtl_priv *rtlpriv = rtl_priv(hw);
1225 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1226
1227 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1228 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1229}
1230
1231void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1232{
1233 struct rtl_priv *rtlpriv = rtl_priv(hw);
1234 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1235
1236 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1237 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1238 synchronize_irq(rtlpci->pdev->irq);
1239}
1240
1241static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1242{
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1244 u8 u1b_tmp;
1245 unsigned long flags;
1246
1247 rtlpriv->intf_ops->enable_aspm(hw);
1248 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1249 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1250 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1251
1252 /* 0x20:value 05-->04 */
1253 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1254
1255 /* ==== Reset digital sequence ====== */
1256 rtl92d_firmware_selfreset(hw);
1257
1258 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1259 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1260
1261 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1262 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1263
1264 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1265
1266 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */
1267 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1268
1269 /* i. Value = GPIO_PIN_CTRL[7:0] */
1270 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1271
1272 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1273 /* write external PIN level */
1274 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1275 0x00FF0000 | (u1b_tmp << 8));
1276
1277 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1278 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1279
1280 /* l. LEDCFG 0x4C[15:0] = 0x8080 */
1281 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1282
1283 /* ==== Disable analog sequence === */
1284
1285 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */
1286 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1287
1288 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */
1289 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1290
1291 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */
1292 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1293
1294 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1295 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1296
1297 /* ==== interface into suspend === */
1298
1299 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1300 /* According to power document V11, we need to set this */
1301 /* value as 0x18. Otherwise, we may not L0s sometimes. */
1302 /* This indluences power consumption. Bases on SD1's test, */
1303 /* set as 0x00 do not affect power current. And if it */
1304 /* is set as 0x18, they had ever met auto load fail problem. */
1305 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1306
1307 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1308 ("In PowerOff,reg0x%x=%X\n", REG_SPS0_CTRL,
1309 rtl_read_byte(rtlpriv, REG_SPS0_CTRL)));
1310 /* r. Note: for PCIe interface, PON will not turn */
1311 /* off m-bias and BandGap in PCIe suspend mode. */
1312
1313 /* 0x17[7] 1b': power off in process 0b' : power off over */
1314 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1315 spin_lock_irqsave(&globalmutex_power, flags);
1316 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1317 u1b_tmp &= (~BIT(7));
1318 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1319 spin_unlock_irqrestore(&globalmutex_power, flags);
1320 }
1321
1322 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<=======\n"));
1323}
1324
1325void rtl92de_card_disable(struct ieee80211_hw *hw)
1326{
1327 struct rtl_priv *rtlpriv = rtl_priv(hw);
1328 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1329 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1330 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1331 enum nl80211_iftype opmode;
1332
1333 mac->link_state = MAC80211_NOLINK;
1334 opmode = NL80211_IFTYPE_UNSPECIFIED;
1335 _rtl92de_set_media_status(hw, opmode);
1336
1337 if (rtlpci->driver_is_goingto_unload ||
1338 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1339 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1340 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1341 /* Power sequence for each MAC. */
1342 /* a. stop tx DMA */
1343 /* b. close RF */
1344 /* c. clear rx buf */
1345 /* d. stop rx DMA */
1346 /* e. reset MAC */
1347
1348 /* a. stop tx DMA */
1349 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1350 udelay(50);
1351
1352 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1353
1354 /* c. ========RF OFF sequence========== */
1355 /* 0x88c[23:20] = 0xf. */
1356 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1357 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
1358
1359 /* APSD_CTRL 0x600[7:0] = 0x40 */
1360 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1361
1362 /* Close antenna 0,0xc04,0xd04 */
1363 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0);
1364 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1365
1366 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
1367 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1368
1369 /* Mac0 can not do Global reset. Mac1 can do. */
1370 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */
1371 if (rtlpriv->rtlhal.interfaceindex == 1)
1372 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1373 udelay(50);
1374
1375 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */
1376 /* dma hang issue when disable/enable device. */
1377 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1378 udelay(50);
1379 rtl_write_byte(rtlpriv, REG_CR, 0x0);
1380 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==> Do power off.......\n"));
1381 if (rtl92d_phy_check_poweroff(hw))
1382 _rtl92de_poweroff_adapter(hw);
1383 return;
1384}
1385
1386void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1387 u32 *p_inta, u32 *p_intb)
1388{
1389 struct rtl_priv *rtlpriv = rtl_priv(hw);
1390 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1391
1392 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1393 rtl_write_dword(rtlpriv, ISR, *p_inta);
1394
1395 /*
1396 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1397 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1398 */
1399}
1400
1401void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1402{
1403 struct rtl_priv *rtlpriv = rtl_priv(hw);
1404 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1405 u16 bcn_interval, atim_window;
1406
1407 bcn_interval = mac->beacon_interval;
1408 atim_window = 2;
1409 /*rtl92de_disable_interrupt(hw); */
1410 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1411 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1412 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1413 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1414 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1415 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1416 else
1417 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1418 rtl_write_byte(rtlpriv, 0x606, 0x30);
1419}
1420
1421void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1422{
1423 struct rtl_priv *rtlpriv = rtl_priv(hw);
1424 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1425 u16 bcn_interval = mac->beacon_interval;
1426
1427 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1428 ("beacon_interval:%d\n", bcn_interval));
1429 /* rtl92de_disable_interrupt(hw); */
1430 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1431 /* rtl92de_enable_interrupt(hw); */
1432}
1433
1434void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1435 u32 add_msr, u32 rm_msr)
1436{
1437 struct rtl_priv *rtlpriv = rtl_priv(hw);
1438 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1439
1440 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1441 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1442 if (add_msr)
1443 rtlpci->irq_mask[0] |= add_msr;
1444 if (rm_msr)
1445 rtlpci->irq_mask[0] &= (~rm_msr);
1446 rtl92de_disable_interrupt(hw);
1447 rtl92de_enable_interrupt(hw);
1448}
1449
1450static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1451 u8 *rom_content, bool autoLoadfail)
1452{
1453 u32 rfpath, eeaddr, group, offset1, offset2;
1454 u8 i;
1455
1456 memset(pwrinfo, 0, sizeof(struct txpower_info));
1457 if (autoLoadfail) {
1458 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1459 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1460 if (group < CHANNEL_GROUP_MAX_2G) {
1461 pwrinfo->cck_index[rfpath][group] =
1462 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1463 pwrinfo->ht40_1sindex[rfpath][group] =
1464 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1465 } else {
1466 pwrinfo->ht40_1sindex[rfpath][group] =
1467 EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1468 }
1469 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1470 EEPROM_DEFAULT_HT40_2SDIFF;
1471 pwrinfo->ht20indexdiff[rfpath][group] =
1472 EEPROM_DEFAULT_HT20_DIFF;
1473 pwrinfo->ofdmindexdiff[rfpath][group] =
1474 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1475 pwrinfo->ht40maxoffset[rfpath][group] =
1476 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1477 pwrinfo->ht20maxoffset[rfpath][group] =
1478 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1479 }
1480 }
1481 for (i = 0; i < 3; i++) {
1482 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1483 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1484 }
1485 return;
1486 }
1487
1488 /* Maybe autoload OK,buf the tx power index value is not filled.
1489 * If we find it, we set it to default value. */
1490 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1491 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1492 eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1493 + group;
1494 pwrinfo->cck_index[rfpath][group] =
1495 (rom_content[eeaddr] == 0xFF) ?
1496 (eeaddr > 0x7B ?
1497 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1498 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1499 rom_content[eeaddr];
1500 }
1501 }
1502 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1503 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1504 offset1 = group / 3;
1505 offset2 = group % 3;
1506 eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1507 offset2 + offset1 * 21;
1508 pwrinfo->ht40_1sindex[rfpath][group] =
1509 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1510 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1511 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1512 rom_content[eeaddr];
1513 }
1514 }
1515 /* These just for 92D efuse offset. */
1516 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1517 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1518 int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1519
1520 offset1 = group / 3;
1521 offset2 = group % 3;
1522
1523 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1524 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1525 (rom_content[base1 +
1526 offset2 + offset1 * 21] >> (rfpath * 4))
1527 & 0xF;
1528 else
1529 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1530 EEPROM_DEFAULT_HT40_2SDIFF;
1531 if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1532 + offset1 * 21] != 0xFF)
1533 pwrinfo->ht20indexdiff[rfpath][group] =
1534 (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1535 + offset2 + offset1 * 21] >> (rfpath * 4))
1536 & 0xF;
1537 else
1538 pwrinfo->ht20indexdiff[rfpath][group] =
1539 EEPROM_DEFAULT_HT20_DIFF;
1540 if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1541 + offset1 * 21] != 0xFF)
1542 pwrinfo->ofdmindexdiff[rfpath][group] =
1543 (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1544 + offset2 + offset1 * 21] >> (rfpath * 4))
1545 & 0xF;
1546 else
1547 pwrinfo->ofdmindexdiff[rfpath][group] =
1548 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1549 if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1550 + offset1 * 21] != 0xFF)
1551 pwrinfo->ht40maxoffset[rfpath][group] =
1552 (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1553 + offset2 + offset1 * 21] >> (rfpath * 4))
1554 & 0xF;
1555 else
1556 pwrinfo->ht40maxoffset[rfpath][group] =
1557 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1558 if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1559 + offset1 * 21] != 0xFF)
1560 pwrinfo->ht20maxoffset[rfpath][group] =
1561 (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1562 offset2 + offset1 * 21] >> (rfpath * 4)) &
1563 0xF;
1564 else
1565 pwrinfo->ht20maxoffset[rfpath][group] =
1566 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1567 }
1568 }
1569 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1570 /* 5GL */
1571 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1572 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1573 /* 5GM */
1574 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1575 pwrinfo->tssi_b[1] =
1576 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1577 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1578 /* 5GH */
1579 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1580 0xF0) >> 4 |
1581 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1582 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1583 0xFC) >> 2;
1584 } else {
1585 for (i = 0; i < 3; i++) {
1586 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1587 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1588 }
1589 }
1590}
1591
1592static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1593 bool autoload_fail, u8 *hwinfo)
1594{
1595 struct rtl_priv *rtlpriv = rtl_priv(hw);
1596 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1597 struct txpower_info pwrinfo;
1598 u8 tempval[2], i, pwr, diff;
1599 u32 ch, rfPath, group;
1600
1601 _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1602 if (!autoload_fail) {
1603 /* bit0~2 */
1604 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1605 rtlefuse->eeprom_thermalmeter =
1606 hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1607 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1608 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1609 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1610 rtlefuse->txpwr_fromeprom = true;
1611 if (IS_92D_D_CUT(rtlpriv->rtlhal.version)) {
1612 rtlefuse->internal_pa_5g[0] =
1613 !((hwinfo[EEPROM_TSSI_A_5G] &
1614 BIT(6)) >> 6);
1615 rtlefuse->internal_pa_5g[1] =
1616 !((hwinfo[EEPROM_TSSI_B_5G] &
1617 BIT(6)) >> 6);
1618 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1619 ("Is D cut,Internal PA0 %d Internal PA1 %d\n",
1620 rtlefuse->internal_pa_5g[0],
1621 rtlefuse->internal_pa_5g[1]))
1622 }
1623 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1624 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1625 } else {
1626 rtlefuse->eeprom_regulatory = 0;
1627 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1628 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1629 tempval[0] = tempval[1] = 3;
1630 }
1631
1632 /* Use default value to fill parameters if
1633 * efuse is not filled on some place. */
1634
1635 /* ThermalMeter from EEPROM */
1636 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1637 rtlefuse->eeprom_thermalmeter > 0x1c)
1638 rtlefuse->eeprom_thermalmeter = 0x12;
1639 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1640
1641 /* check XTAL_K */
1642 if (rtlefuse->crystalcap == 0xFF)
1643 rtlefuse->crystalcap = 0;
1644 if (rtlefuse->eeprom_regulatory > 3)
1645 rtlefuse->eeprom_regulatory = 0;
1646
1647 for (i = 0; i < 2; i++) {
1648 switch (tempval[i]) {
1649 case 0:
1650 tempval[i] = 5;
1651 break;
1652 case 1:
1653 tempval[i] = 4;
1654 break;
1655 case 2:
1656 tempval[i] = 3;
1657 break;
1658 case 3:
1659 default:
1660 tempval[i] = 0;
1661 break;
1662 }
1663 }
1664
1665 rtlefuse->delta_iqk = tempval[0];
1666 if (tempval[1] > 0)
1667 rtlefuse->delta_lck = tempval[1] - 1;
1668 if (rtlefuse->eeprom_c9 == 0xFF)
1669 rtlefuse->eeprom_c9 = 0x00;
1670 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1671 ("EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1672 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1673 ("ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1674 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1675 ("CrystalCap = 0x%x\n", rtlefuse->crystalcap));
1676 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1677 ("Delta_IQK = 0x%x Delta_LCK = 0x%x\n", rtlefuse->delta_iqk,
1678 rtlefuse->delta_lck));
1679
1680 for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1681 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1682 group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1683 if (ch < CHANNEL_MAX_NUMBER_2G)
1684 rtlefuse->txpwrlevel_cck[rfPath][ch] =
1685 pwrinfo.cck_index[rfPath][group];
1686 rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1687 pwrinfo.ht40_1sindex[rfPath][group];
1688 rtlefuse->txpwr_ht20diff[rfPath][ch] =
1689 pwrinfo.ht20indexdiff[rfPath][group];
1690 rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1691 pwrinfo.ofdmindexdiff[rfPath][group];
1692 rtlefuse->pwrgroup_ht20[rfPath][ch] =
1693 pwrinfo.ht20maxoffset[rfPath][group];
1694 rtlefuse->pwrgroup_ht40[rfPath][ch] =
1695 pwrinfo.ht40maxoffset[rfPath][group];
1696 pwr = pwrinfo.ht40_1sindex[rfPath][group];
1697 diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1698 rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1699 (pwr > diff) ? (pwr - diff) : 0;
1700 }
1701 }
1702}
1703
1704static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1705 u8 *content)
1706{
1707 struct rtl_priv *rtlpriv = rtl_priv(hw);
1708 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1709 u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1710
1711 if (macphy_crvalue & BIT(3)) {
1712 rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1713 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1714 ("MacPhyMode SINGLEMAC_SINGLEPHY\n"));
1715 } else {
1716 rtlhal->macphymode = DUALMAC_DUALPHY;
1717 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1718 ("MacPhyMode DUALMAC_DUALPHY\n"));
1719 }
1720}
1721
1722static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1723 u8 *content)
1724{
1725 _rtl92de_read_macphymode_from_prom(hw, content);
1726 rtl92d_phy_config_macphymode(hw);
1727 rtl92d_phy_config_macphymode_info(hw);
1728}
1729
1730static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1731{
1732 struct rtl_priv *rtlpriv = rtl_priv(hw);
1733 enum version_8192d chipver = rtlpriv->rtlhal.version;
1734 u8 cutvalue[2];
1735 u16 chipvalue;
1736
1737 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1738 &cutvalue[1]);
1739 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1740 &cutvalue[0]);
1741 chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1742 switch (chipvalue) {
1743 case 0xAA55:
1744 chipver |= CHIP_92D_C_CUT;
1745 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("C-CUT!!!\n"));
1746 break;
1747 case 0x9966:
1748 chipver |= CHIP_92D_D_CUT;
1749 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("D-CUT!!!\n"));
1750 break;
1751 default:
1752 chipver |= CHIP_92D_D_CUT;
1753 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, ("Unkown CUT!\n"));
1754 break;
1755 }
1756 rtlpriv->rtlhal.version = chipver;
1757}
1758
1759static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1760{
1761 struct rtl_priv *rtlpriv = rtl_priv(hw);
1762 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1763 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1764 u16 i, usvalue;
1765 u8 hwinfo[HWSET_MAX_SIZE];
1766 u16 eeprom_id;
1767 unsigned long flags;
1768
1769 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1770 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
1771 rtl_efuse_shadow_map_update(hw);
1772 _rtl92de_efuse_update_chip_version(hw);
1773 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
1774 memcpy((void *)hwinfo, (void *)&rtlefuse->efuse_map
1775 [EFUSE_INIT_MAP][0],
1776 HWSET_MAX_SIZE);
1777 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1778 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1779 ("RTL819X Not boot from eeprom, check it !!"));
1780 }
1781 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1782 hwinfo, HWSET_MAX_SIZE);
1783
1784 eeprom_id = *((u16 *)&hwinfo[0]);
1785 if (eeprom_id != RTL8190_EEPROM_ID) {
1786 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1787 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1788 rtlefuse->autoload_failflag = true;
1789 } else {
1790 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1791 rtlefuse->autoload_failflag = false;
1792 }
1793 if (rtlefuse->autoload_failflag) {
1794 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1795 ("RTL819X Not boot from eeprom, check it !!"));
1796 return;
1797 }
1798 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1799 _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1800
1801 /* VID, DID SE 0xA-D */
1802 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1803 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1804 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1805 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1806 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1807 ("EEPROMId = 0x%4x\n", eeprom_id));
1808 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1809 ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
1810 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1811 ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
1812 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1813 ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
1814 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1815 ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
1816
1817 /* Read Permanent MAC address */
1818 if (rtlhal->interfaceindex == 0) {
1819 for (i = 0; i < 6; i += 2) {
1820 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC0_92D + i];
1821 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1822 }
1823 } else {
1824 for (i = 0; i < 6; i += 2) {
1825 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1826 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1827 }
1828 }
1829 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1830 rtlefuse->dev_addr);
1831 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1832 ("%pM\n", rtlefuse->dev_addr));
1833 _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1834
1835 /* Read Channel Plan */
1836 switch (rtlhal->bandset) {
1837 case BAND_ON_2_4G:
1838 rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1839 break;
1840 case BAND_ON_5G:
1841 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1842 break;
1843 case BAND_ON_BOTH:
1844 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1845 break;
1846 default:
1847 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1848 break;
1849 }
1850 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1851 rtlefuse->txpwr_fromeprom = true;
1852 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1853 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1854}
1855
1856void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1857{
1858 struct rtl_priv *rtlpriv = rtl_priv(hw);
1859 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1860 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1861 u8 tmp_u1b;
1862
1863 rtlhal->version = _rtl92de_read_chip_version(hw);
1864 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1865 rtlefuse->autoload_status = tmp_u1b;
1866 if (tmp_u1b & BIT(4)) {
1867 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1868 rtlefuse->epromtype = EEPROM_93C46;
1869 } else {
1870 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1871 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1872 }
1873 if (tmp_u1b & BIT(5)) {
1874 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1875
1876 rtlefuse->autoload_failflag = false;
1877 _rtl92de_read_adapter_info(hw);
1878 } else {
1879 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1880 }
1881 return;
1882}
1883
1884static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1885 struct ieee80211_sta *sta)
1886{
1887 struct rtl_priv *rtlpriv = rtl_priv(hw);
1888 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1889 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1890 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1891 u32 ratr_value;
1892 u8 ratr_index = 0;
1893 u8 nmode = mac->ht_enable;
1894 u8 mimo_ps = IEEE80211_SMPS_OFF;
1895 u16 shortgi_rate;
1896 u32 tmp_ratr_value;
1897 u8 curtxbw_40mhz = mac->bw_40;
1898 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1899 1 : 0;
1900 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1901 1 : 0;
1902 enum wireless_mode wirelessmode = mac->mode;
1903
1904 if (rtlhal->current_bandtype == BAND_ON_5G)
1905 ratr_value = sta->supp_rates[1] << 4;
1906 else
1907 ratr_value = sta->supp_rates[0];
1908 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1909 sta->ht_cap.mcs.rx_mask[0] << 12);
1910 switch (wirelessmode) {
1911 case WIRELESS_MODE_A:
1912 ratr_value &= 0x00000FF0;
1913 break;
1914 case WIRELESS_MODE_B:
1915 if (ratr_value & 0x0000000c)
1916 ratr_value &= 0x0000000d;
1917 else
1918 ratr_value &= 0x0000000f;
1919 break;
1920 case WIRELESS_MODE_G:
1921 ratr_value &= 0x00000FF5;
1922 break;
1923 case WIRELESS_MODE_N_24G:
1924 case WIRELESS_MODE_N_5G:
1925 nmode = 1;
1926 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1927 ratr_value &= 0x0007F005;
1928 } else {
1929 u32 ratr_mask;
1930
1931 if (get_rf_type(rtlphy) == RF_1T2R ||
1932 get_rf_type(rtlphy) == RF_1T1R) {
1933 ratr_mask = 0x000ff005;
1934 } else {
1935 ratr_mask = 0x0f0ff005;
1936 }
1937
1938 ratr_value &= ratr_mask;
1939 }
1940 break;
1941 default:
1942 if (rtlphy->rf_type == RF_1T2R)
1943 ratr_value &= 0x000ff0ff;
1944 else
1945 ratr_value &= 0x0f0ff0ff;
1946
1947 break;
1948 }
1949 ratr_value &= 0x0FFFFFFF;
1950 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1951 (!curtxbw_40mhz && curshortgi_20mhz))) {
1952 ratr_value |= 0x10000000;
1953 tmp_ratr_value = (ratr_value >> 12);
1954 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1955 if ((1 << shortgi_rate) & tmp_ratr_value)
1956 break;
1957 }
1958 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1959 (shortgi_rate << 4) | (shortgi_rate);
1960 }
1961 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1962 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1963 ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1964}
1965
1966static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1967 struct ieee80211_sta *sta, u8 rssi_level)
1968{
1969 struct rtl_priv *rtlpriv = rtl_priv(hw);
1970 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1971 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1972 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1973 struct rtl_sta_info *sta_entry = NULL;
1974 u32 ratr_bitmap;
1975 u8 ratr_index;
1976 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1977 ? 1 : 0;
1978 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1979 1 : 0;
1980 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1981 1 : 0;
1982 enum wireless_mode wirelessmode = 0;
1983 bool shortgi = false;
1984 u32 value[2];
1985 u8 macid = 0;
1986 u8 mimo_ps = IEEE80211_SMPS_OFF;
1987
1988 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1989 mimo_ps = sta_entry->mimo_ps;
1990 wirelessmode = sta_entry->wireless_mode;
1991 if (mac->opmode == NL80211_IFTYPE_STATION)
1992 curtxbw_40mhz = mac->bw_40;
1993 else if (mac->opmode == NL80211_IFTYPE_AP ||
1994 mac->opmode == NL80211_IFTYPE_ADHOC)
1995 macid = sta->aid + 1;
1996
1997 if (rtlhal->current_bandtype == BAND_ON_5G)
1998 ratr_bitmap = sta->supp_rates[1] << 4;
1999 else
2000 ratr_bitmap = sta->supp_rates[0];
2001 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2002 sta->ht_cap.mcs.rx_mask[0] << 12);
2003 switch (wirelessmode) {
2004 case WIRELESS_MODE_B:
2005 ratr_index = RATR_INX_WIRELESS_B;
2006 if (ratr_bitmap & 0x0000000c)
2007 ratr_bitmap &= 0x0000000d;
2008 else
2009 ratr_bitmap &= 0x0000000f;
2010 break;
2011 case WIRELESS_MODE_G:
2012 ratr_index = RATR_INX_WIRELESS_GB;
2013
2014 if (rssi_level == 1)
2015 ratr_bitmap &= 0x00000f00;
2016 else if (rssi_level == 2)
2017 ratr_bitmap &= 0x00000ff0;
2018 else
2019 ratr_bitmap &= 0x00000ff5;
2020 break;
2021 case WIRELESS_MODE_A:
2022 ratr_index = RATR_INX_WIRELESS_G;
2023 ratr_bitmap &= 0x00000ff0;
2024 break;
2025 case WIRELESS_MODE_N_24G:
2026 case WIRELESS_MODE_N_5G:
2027 if (wirelessmode == WIRELESS_MODE_N_24G)
2028 ratr_index = RATR_INX_WIRELESS_NGB;
2029 else
2030 ratr_index = RATR_INX_WIRELESS_NG;
2031 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2032 if (rssi_level == 1)
2033 ratr_bitmap &= 0x00070000;
2034 else if (rssi_level == 2)
2035 ratr_bitmap &= 0x0007f000;
2036 else
2037 ratr_bitmap &= 0x0007f005;
2038 } else {
2039 if (rtlphy->rf_type == RF_1T2R ||
2040 rtlphy->rf_type == RF_1T1R) {
2041 if (curtxbw_40mhz) {
2042 if (rssi_level == 1)
2043 ratr_bitmap &= 0x000f0000;
2044 else if (rssi_level == 2)
2045 ratr_bitmap &= 0x000ff000;
2046 else
2047 ratr_bitmap &= 0x000ff015;
2048 } else {
2049 if (rssi_level == 1)
2050 ratr_bitmap &= 0x000f0000;
2051 else if (rssi_level == 2)
2052 ratr_bitmap &= 0x000ff000;
2053 else
2054 ratr_bitmap &= 0x000ff005;
2055 }
2056 } else {
2057 if (curtxbw_40mhz) {
2058 if (rssi_level == 1)
2059 ratr_bitmap &= 0x0f0f0000;
2060 else if (rssi_level == 2)
2061 ratr_bitmap &= 0x0f0ff000;
2062 else
2063 ratr_bitmap &= 0x0f0ff015;
2064 } else {
2065 if (rssi_level == 1)
2066 ratr_bitmap &= 0x0f0f0000;
2067 else if (rssi_level == 2)
2068 ratr_bitmap &= 0x0f0ff000;
2069 else
2070 ratr_bitmap &= 0x0f0ff005;
2071 }
2072 }
2073 }
2074 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2075 (!curtxbw_40mhz && curshortgi_20mhz)) {
2076
2077 if (macid == 0)
2078 shortgi = true;
2079 else if (macid == 1)
2080 shortgi = false;
2081 }
2082 break;
2083 default:
2084 ratr_index = RATR_INX_WIRELESS_NGB;
2085
2086 if (rtlphy->rf_type == RF_1T2R)
2087 ratr_bitmap &= 0x000ff0ff;
2088 else
2089 ratr_bitmap &= 0x0f0ff0ff;
2090 break;
2091 }
2092
2093 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2094 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2095 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2096 ("ratr_bitmap :%x value0:%x value1:%x\n",
2097 ratr_bitmap, value[0], value[1]));
2098 rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2099 if (macid != 0)
2100 sta_entry->ratr_index = ratr_index;
2101}
2102
2103void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2104 struct ieee80211_sta *sta, u8 rssi_level)
2105{
2106 struct rtl_priv *rtlpriv = rtl_priv(hw);
2107
2108 if (rtlpriv->dm.useramask)
2109 rtl92de_update_hal_rate_mask(hw, sta, rssi_level);
2110 else
2111 rtl92de_update_hal_rate_table(hw, sta);
2112}
2113
2114void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2115{
2116 struct rtl_priv *rtlpriv = rtl_priv(hw);
2117 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2118 u16 sifs_timer;
2119
2120 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2121 (u8 *)&mac->slot_time);
2122 if (!mac->ht_enable)
2123 sifs_timer = 0x0a0a;
2124 else
2125 sifs_timer = 0x1010;
2126 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2127}
2128
2129bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2130{
2131 struct rtl_priv *rtlpriv = rtl_priv(hw);
2132 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2133 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2134 enum rf_pwrstate e_rfpowerstate_toset;
2135 u8 u1tmp;
2136 bool actuallyset = false;
2137 unsigned long flag;
2138
2139 if (rtlpci->being_init_adapter)
2140 return false;
2141 if (ppsc->swrf_processing)
2142 return false;
2143 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2144 if (ppsc->rfchange_inprogress) {
2145 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2146 return false;
2147 } else {
2148 ppsc->rfchange_inprogress = true;
2149 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2150 }
2151 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2152 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2153 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2154 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2155 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2156 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2157 ("GPIOChangeRF - HW Radio ON, RF ON\n"));
2158 e_rfpowerstate_toset = ERFON;
2159 ppsc->hwradiooff = false;
2160 actuallyset = true;
2161 } else if ((ppsc->hwradiooff == false)
2162 && (e_rfpowerstate_toset == ERFOFF)) {
2163 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2164 ("GPIOChangeRF - HW Radio OFF, RF OFF\n"));
2165 e_rfpowerstate_toset = ERFOFF;
2166 ppsc->hwradiooff = true;
2167 actuallyset = true;
2168 }
2169 if (actuallyset) {
2170 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2171 ppsc->rfchange_inprogress = false;
2172 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2173 } else {
2174 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2175 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2176 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2177 ppsc->rfchange_inprogress = false;
2178 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2179 }
2180 *valid = 1;
2181 return !ppsc->hwradiooff;
2182}
2183
2184void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2185 u8 *p_macaddr, bool is_group, u8 enc_algo,
2186 bool is_wepkey, bool clear_all)
2187{
2188 struct rtl_priv *rtlpriv = rtl_priv(hw);
2189 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2190 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2191 u8 *macaddr = p_macaddr;
2192 u32 entry_id;
2193 bool is_pairwise = false;
2194 static u8 cam_const_addr[4][6] = {
2195 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2196 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2197 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2198 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2199 };
2200 static u8 cam_const_broad[] = {
2201 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2202 };
2203
2204 if (clear_all) {
2205 u8 idx;
2206 u8 cam_offset = 0;
2207 u8 clear_number = 5;
2208 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2209 for (idx = 0; idx < clear_number; idx++) {
2210 rtl_cam_mark_invalid(hw, cam_offset + idx);
2211 rtl_cam_empty_entry(hw, cam_offset + idx);
2212
2213 if (idx < 5) {
2214 memset(rtlpriv->sec.key_buf[idx], 0,
2215 MAX_KEY_LEN);
2216 rtlpriv->sec.key_len[idx] = 0;
2217 }
2218 }
2219 } else {
2220 switch (enc_algo) {
2221 case WEP40_ENCRYPTION:
2222 enc_algo = CAM_WEP40;
2223 break;
2224 case WEP104_ENCRYPTION:
2225 enc_algo = CAM_WEP104;
2226 break;
2227 case TKIP_ENCRYPTION:
2228 enc_algo = CAM_TKIP;
2229 break;
2230 case AESCCMP_ENCRYPTION:
2231 enc_algo = CAM_AES;
2232 break;
2233 default:
2234 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2235 "not process\n"));
2236 enc_algo = CAM_TKIP;
2237 break;
2238 }
2239 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2240 macaddr = cam_const_addr[key_index];
2241 entry_id = key_index;
2242 } else {
2243 if (is_group) {
2244 macaddr = cam_const_broad;
2245 entry_id = key_index;
2246 } else {
2247 if (mac->opmode == NL80211_IFTYPE_AP) {
2248 entry_id = rtl_cam_get_free_entry(hw,
2249 p_macaddr);
2250 if (entry_id >= TOTAL_CAM_ENTRY) {
2251 RT_TRACE(rtlpriv, COMP_SEC,
2252 DBG_EMERG, ("Can not "
2253 "find free hw security"
2254 " cam entry\n"));
2255 return;
2256 }
2257 } else {
2258 entry_id = CAM_PAIRWISE_KEY_POSITION;
2259 }
2260 key_index = PAIRWISE_KEYIDX;
2261 is_pairwise = true;
2262 }
2263 }
2264 if (rtlpriv->sec.key_len[key_index] == 0) {
2265 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2266 ("delete one entry, entry_id is %d\n",
2267 entry_id));
2268 if (mac->opmode == NL80211_IFTYPE_AP)
2269 rtl_cam_del_entry(hw, p_macaddr);
2270 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2271 } else {
2272 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2273 ("The insert KEY length is %d\n",
2274 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2275 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2276 ("The insert KEY is %x %x\n",
2277 rtlpriv->sec.key_buf[0][0],
2278 rtlpriv->sec.key_buf[0][1]));
2279 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2280 ("add one entry\n"));
2281 if (is_pairwise) {
2282 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2283 "Pairwiase Key content :",
2284 rtlpriv->sec.pairwise_key,
2285 rtlpriv->
2286 sec.key_len[PAIRWISE_KEYIDX]);
2287 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2288 ("set Pairwiase key\n"));
2289 rtl_cam_add_one_entry(hw, macaddr, key_index,
2290 entry_id, enc_algo,
2291 CAM_CONFIG_NO_USEDK,
2292 rtlpriv->
2293 sec.key_buf[key_index]);
2294 } else {
2295 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2296 ("set group key\n"));
2297 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2298 rtl_cam_add_one_entry(hw,
2299 rtlefuse->dev_addr,
2300 PAIRWISE_KEYIDX,
2301 CAM_PAIRWISE_KEY_POSITION,
2302 enc_algo, CAM_CONFIG_NO_USEDK,
2303 rtlpriv->sec.key_buf[entry_id]);
2304 }
2305 rtl_cam_add_one_entry(hw, macaddr, key_index,
2306 entry_id, enc_algo,
2307 CAM_CONFIG_NO_USEDK,
2308 rtlpriv->sec.key_buf
2309 [entry_id]);
2310 }
2311 }
2312 }
2313}
2314
2315void rtl92de_suspend(struct ieee80211_hw *hw)
2316{
2317 struct rtl_priv *rtlpriv = rtl_priv(hw);
2318
2319 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2320 REG_MAC_PHY_CTRL_NORMAL);
2321}
2322
2323void rtl92de_resume(struct ieee80211_hw *hw)
2324{
2325 struct rtl_priv *rtlpriv = rtl_priv(hw);
2326
2327 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2328 rtlpriv->rtlhal.macphyctl_reg);
2329}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/hw.h b/drivers/net/wireless/rtlwifi/rtl8192de/hw.h
new file mode 100644
index 000000000000..ad44ffa520e6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/hw.h
@@ -0,0 +1,66 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92DE_HW_H__
31#define __RTL92DE_HW_H__
32
33void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
34void rtl92de_read_eeprom_info(struct ieee80211_hw *hw);
35void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
36 u32 *p_inta, u32 *p_intb);
37int rtl92de_hw_init(struct ieee80211_hw *hw);
38void rtl92de_card_disable(struct ieee80211_hw *hw);
39void rtl92de_enable_interrupt(struct ieee80211_hw *hw);
40void rtl92de_disable_interrupt(struct ieee80211_hw *hw);
41int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
42void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
43void rtl92de_set_qos(struct ieee80211_hw *hw, int aci);
44void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw);
45void rtl92de_set_beacon_interval(struct ieee80211_hw *hw);
46void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
47 u32 add_msr, u32 rm_msr);
48void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
49void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
50 struct ieee80211_sta *sta, u8 rssi_level);
51void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw);
52bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
53void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw);
54void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
55 u8 *p_macaddr, bool is_group, u8 enc_algo,
56 bool is_wepkey, bool clear_all);
57
58extern void rtl92de_write_dword_dbi(struct ieee80211_hw *hw, u16 offset,
59 u32 value, u8 direct);
60extern u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset,
61 u8 direct);
62void rtl92de_suspend(struct ieee80211_hw *hw);
63void rtl92de_resume(struct ieee80211_hw *hw);
64void rtl92d_linked_set_reg(struct ieee80211_hw *hw);
65
66#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/led.c b/drivers/net/wireless/rtlwifi/rtl8192de/led.c
new file mode 100644
index 000000000000..f1552f4df658
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/led.c
@@ -0,0 +1,159 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "reg.h"
33#include "led.h"
34
35static void _rtl92ce_init_led(struct ieee80211_hw *hw,
36 struct rtl_led *pled, enum rtl_led_pin ledpin)
37{
38 pled->hw = hw;
39 pled->ledpin = ledpin;
40 pled->ledon = false;
41}
42
43void rtl92de_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
44{
45 u8 ledcfg;
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47
48 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
49 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
50
51 switch (pled->ledpin) {
52 case LED_PIN_GPIO0:
53 break;
54 case LED_PIN_LED0:
55 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
56
57 if ((rtlpriv->efuse.eeprom_did == 0x8176) ||
58 (rtlpriv->efuse.eeprom_did == 0x8193))
59 /* BIT7 of REG_LEDCFG2 should be set to
60 * make sure we could emit the led2. */
61 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0xf0) |
62 BIT(7) | BIT(5) | BIT(6));
63 else
64 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0xf0) |
65 BIT(7) | BIT(5));
66 break;
67 case LED_PIN_LED1:
68 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
69
70 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
71 break;
72 default:
73 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
74 ("switch case not process\n"));
75 break;
76 }
77 pled->ledon = true;
78}
79
80void rtl92de_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
81{
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
83 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
84 u8 ledcfg;
85
86 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
87 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
88
89 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
90
91 switch (pled->ledpin) {
92 case LED_PIN_GPIO0:
93 break;
94 case LED_PIN_LED0:
95 ledcfg &= 0xf0;
96 if (pcipriv->ledctl.led_opendrain)
97 rtl_write_byte(rtlpriv, REG_LEDCFG2,
98 (ledcfg | BIT(1) | BIT(5) | BIT(6)));
99 else
100 rtl_write_byte(rtlpriv, REG_LEDCFG2,
101 (ledcfg | BIT(3) | BIT(5) | BIT(6)));
102 break;
103 case LED_PIN_LED1:
104 ledcfg &= 0x0f;
105 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
106 break;
107 default:
108 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
109 ("switch case not process\n"));
110 break;
111 }
112 pled->ledon = false;
113}
114
115void rtl92de_init_sw_leds(struct ieee80211_hw *hw)
116{
117 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
118 _rtl92ce_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
119 _rtl92ce_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
120}
121
122static void _rtl92ce_sw_led_control(struct ieee80211_hw *hw,
123 enum led_ctl_mode ledaction)
124{
125 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
126 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
127 switch (ledaction) {
128 case LED_CTL_POWER_ON:
129 case LED_CTL_LINK:
130 case LED_CTL_NO_LINK:
131 rtl92de_sw_led_on(hw, pLed0);
132 break;
133 case LED_CTL_POWER_OFF:
134 rtl92de_sw_led_off(hw, pLed0);
135 break;
136 default:
137 break;
138 }
139}
140
141void rtl92de_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction)
142{
143 struct rtl_priv *rtlpriv = rtl_priv(hw);
144 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
145
146 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
147 (ledaction == LED_CTL_TX ||
148 ledaction == LED_CTL_RX ||
149 ledaction == LED_CTL_SITE_SURVEY ||
150 ledaction == LED_CTL_LINK ||
151 ledaction == LED_CTL_NO_LINK ||
152 ledaction == LED_CTL_START_TO_LINK ||
153 ledaction == LED_CTL_POWER_ON)) {
154 return;
155 }
156 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, ("ledaction %d,\n", ledaction));
157
158 _rtl92ce_sw_led_control(hw, ledaction);
159}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/led.h b/drivers/net/wireless/rtlwifi/rtl8192de/led.h
new file mode 100644
index 000000000000..57f4a3c583d4
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/led.h
@@ -0,0 +1,38 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CE_LED_H__
31#define __RTL92CE_LED_H__
32
33void rtl92de_init_sw_leds(struct ieee80211_hw *hw);
34void rtl92de_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
35void rtl92de_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
36void rtl92de_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
37
38#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
new file mode 100644
index 000000000000..3ac7af1c5509
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
@@ -0,0 +1,3831 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39#include "sw.h"
40#include "hw.h"
41
42#define MAX_RF_IMR_INDEX 12
43#define MAX_RF_IMR_INDEX_NORMAL 13
44#define RF_REG_NUM_FOR_C_CUT_5G 6
45#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7
46#define RF_REG_NUM_FOR_C_CUT_2G 5
47#define RF_CHNL_NUM_5G 19
48#define RF_CHNL_NUM_5G_40M 17
49#define TARGET_CHNL_NUM_5G 221
50#define TARGET_CHNL_NUM_2G 14
51#define CV_CURVE_CNT 64
52
53static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
54 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
55};
56
57static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
58 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
59};
60
61static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
62 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
63};
64
65static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
66 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
67};
68
69static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
70 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
71 BIT(10) | BIT(9),
72 BIT(18) | BIT(17) | BIT(16) | BIT(1),
73 BIT(2) | BIT(1),
74 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
75};
76
77static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
78 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
79 112, 116, 120, 124, 128, 132, 136, 140
80};
81
82static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
83 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
84 118, 122, 126, 130, 134, 138
85};
86static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
87 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
88 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
89 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
90 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
91 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
92};
93
94static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
95 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
96 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
97 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
98};
99
100static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
101
102static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
103 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
104 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
106};
107
108/* [mode][patha+b][reg] */
109static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
110 {
111 /* channel 1-14. */
112 {
113 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
114 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
115 },
116 /* path 36-64 */
117 {
118 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
119 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
120 0x32c9a
121 },
122 /* 100 -165 */
123 {
124 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
125 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
126 }
127 }
128};
129
130static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
131
132static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
133
134static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
135 25141, 25116, 25091, 25066, 25041,
136 25016, 24991, 24966, 24941, 24917,
137 24892, 24867, 24843, 24818, 24794,
138 24770, 24765, 24721, 24697, 24672,
139 24648, 24624, 24600, 24576, 24552,
140 24528, 24504, 24480, 24457, 24433,
141 24409, 24385, 24362, 24338, 24315,
142 24291, 24268, 24245, 24221, 24198,
143 24175, 24151, 24128, 24105, 24082,
144 24059, 24036, 24013, 23990, 23967,
145 23945, 23922, 23899, 23876, 23854,
146 23831, 23809, 23786, 23764, 23741,
147 23719, 23697, 23674, 23652, 23630,
148 23608, 23586, 23564, 23541, 23519,
149 23498, 23476, 23454, 23432, 23410,
150 23388, 23367, 23345, 23323, 23302,
151 23280, 23259, 23237, 23216, 23194,
152 23173, 23152, 23130, 23109, 23088,
153 23067, 23046, 23025, 23003, 22982,
154 22962, 22941, 22920, 22899, 22878,
155 22857, 22837, 22816, 22795, 22775,
156 22754, 22733, 22713, 22692, 22672,
157 22652, 22631, 22611, 22591, 22570,
158 22550, 22530, 22510, 22490, 22469,
159 22449, 22429, 22409, 22390, 22370,
160 22350, 22336, 22310, 22290, 22271,
161 22251, 22231, 22212, 22192, 22173,
162 22153, 22134, 22114, 22095, 22075,
163 22056, 22037, 22017, 21998, 21979,
164 21960, 21941, 21921, 21902, 21883,
165 21864, 21845, 21826, 21807, 21789,
166 21770, 21751, 21732, 21713, 21695,
167 21676, 21657, 21639, 21620, 21602,
168 21583, 21565, 21546, 21528, 21509,
169 21491, 21473, 21454, 21436, 21418,
170 21400, 21381, 21363, 21345, 21327,
171 21309, 21291, 21273, 21255, 21237,
172 21219, 21201, 21183, 21166, 21148,
173 21130, 21112, 21095, 21077, 21059,
174 21042, 21024, 21007, 20989, 20972,
175 25679, 25653, 25627, 25601, 25575,
176 25549, 25523, 25497, 25471, 25446,
177 25420, 25394, 25369, 25343, 25318,
178 25292, 25267, 25242, 25216, 25191,
179 25166
180};
181
182/* channel 1~14 */
183static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
184 26084, 26030, 25976, 25923, 25869, 25816, 25764,
185 25711, 25658, 25606, 25554, 25502, 25451, 25328
186};
187
188static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
189{
190 u32 i;
191
192 for (i = 0; i <= 31; i++) {
193 if (((bitmask >> i) & 0x1) == 1)
194 break;
195 }
196
197 return i;
198}
199
200u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
201{
202 struct rtl_priv *rtlpriv = rtl_priv(hw);
203 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
204 u32 returnvalue, originalvalue, bitshift;
205 u8 dbi_direct;
206
207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
208 "bitmask(%#x)\n", regaddr, bitmask));
209 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
210 /* mac1 use phy0 read radio_b. */
211 /* mac0 use phy1 read radio_b. */
212 if (rtlhal->during_mac1init_radioa)
213 dbi_direct = BIT(3);
214 else if (rtlhal->during_mac0init_radiob)
215 dbi_direct = BIT(3) | BIT(2);
216 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
217 dbi_direct);
218 } else {
219 originalvalue = rtl_read_dword(rtlpriv, regaddr);
220 }
221 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
222 returnvalue = (originalvalue & bitmask) >> bitshift;
223 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
224 "Addr[0x%x]=0x%x\n", bitmask, regaddr, originalvalue));
225 return returnvalue;
226}
227
228void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
229 u32 regaddr, u32 bitmask, u32 data)
230{
231 struct rtl_priv *rtlpriv = rtl_priv(hw);
232 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
233 u8 dbi_direct = 0;
234 u32 originalvalue, bitshift;
235
236 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
237 " data(%#x)\n", regaddr, bitmask, data));
238 if (rtlhal->during_mac1init_radioa)
239 dbi_direct = BIT(3);
240 else if (rtlhal->during_mac0init_radiob)
241 /* mac0 use phy1 write radio_b. */
242 dbi_direct = BIT(3) | BIT(2);
243 if (bitmask != BMASKDWORD) {
244 if (rtlhal->during_mac1init_radioa ||
245 rtlhal->during_mac0init_radiob)
246 originalvalue = rtl92de_read_dword_dbi(hw,
247 (u16) regaddr,
248 dbi_direct);
249 else
250 originalvalue = rtl_read_dword(rtlpriv, regaddr);
251 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
252 data = ((originalvalue & (~bitmask)) | (data << bitshift));
253 }
254 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
255 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
256 else
257 rtl_write_dword(rtlpriv, regaddr, data);
258 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
259 " data(%#x)\n", regaddr, bitmask, data));
260}
261
262static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
263 enum radio_path rfpath, u32 offset)
264{
265
266 struct rtl_priv *rtlpriv = rtl_priv(hw);
267 struct rtl_phy *rtlphy = &(rtlpriv->phy);
268 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
269 u32 newoffset;
270 u32 tmplong, tmplong2;
271 u8 rfpi_enable = 0;
272 u32 retvalue;
273
274 newoffset = offset;
275 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD);
276 if (rfpath == RF90_PATH_A)
277 tmplong2 = tmplong;
278 else
279 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD);
280 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
281 (newoffset << 23) | BLSSIREADEDGE;
282 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
283 tmplong & (~BLSSIREADEDGE));
284 udelay(10);
285 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2);
286 udelay(50);
287 udelay(50);
288 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
289 tmplong | BLSSIREADEDGE);
290 udelay(10);
291 if (rfpath == RF90_PATH_A)
292 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
293 BIT(8));
294 else if (rfpath == RF90_PATH_B)
295 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
296 BIT(8));
297 if (rfpi_enable)
298 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
299 BLSSIREADBACKDATA);
300 else
301 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
302 BLSSIREADBACKDATA);
303 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x] = 0x%x\n",
304 rfpath, pphyreg->rflssi_readback, retvalue));
305 return retvalue;
306}
307
308static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
309 enum radio_path rfpath,
310 u32 offset, u32 data)
311{
312 u32 data_and_addr;
313 u32 newoffset;
314 struct rtl_priv *rtlpriv = rtl_priv(hw);
315 struct rtl_phy *rtlphy = &(rtlpriv->phy);
316 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
317
318 newoffset = offset;
319 /* T65 RF */
320 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
321 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr);
322 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
323 rfpath, pphyreg->rf3wire_offset, data_and_addr));
324}
325
326u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
327 enum radio_path rfpath, u32 regaddr, u32 bitmask)
328{
329 struct rtl_priv *rtlpriv = rtl_priv(hw);
330 u32 original_value, readback_value, bitshift;
331 unsigned long flags;
332
333 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
334 "rfpath(%#x), bitmask(%#x)\n",
335 regaddr, rfpath, bitmask));
336 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
337 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
338 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
339 readback_value = (original_value & bitmask) >> bitshift;
340 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
341 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
342 "bitmask(%#x), original_value(%#x)\n",
343 regaddr, rfpath, bitmask, original_value));
344 return readback_value;
345}
346
347void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
348 u32 regaddr, u32 bitmask, u32 data)
349{
350 struct rtl_priv *rtlpriv = rtl_priv(hw);
351 struct rtl_phy *rtlphy = &(rtlpriv->phy);
352 u32 original_value, bitshift;
353 unsigned long flags;
354
355 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
356 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
357 regaddr, bitmask, data, rfpath));
358 if (bitmask == 0)
359 return;
360 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
361 if (rtlphy->rf_mode != RF_OP_BY_FW) {
362 if (bitmask != BRFREGOFFSETMASK) {
363 original_value = _rtl92d_phy_rf_serial_read(hw,
364 rfpath, regaddr);
365 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
366 data = ((original_value & (~bitmask)) |
367 (data << bitshift));
368 }
369 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
370 }
371 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
372 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
373 "bitmask(%#x), data(%#x), rfpath(%#x)\n",
374 regaddr, bitmask, data, rfpath));
375}
376
377bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
378{
379 struct rtl_priv *rtlpriv = rtl_priv(hw);
380 u32 i;
381 u32 arraylength;
382 u32 *ptrarray;
383
384 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
385 arraylength = MAC_2T_ARRAYLENGTH;
386 ptrarray = rtl8192de_mac_2tarray;
387 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Img:Rtl819XMAC_Array\n"));
388 for (i = 0; i < arraylength; i = i + 2)
389 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
390 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
391 /* improve 2-stream TX EVM */
392 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
393 /* AMPDU aggregation number 9 */
394 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
395 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
396 } else {
397 /* 92D need to test to decide the num. */
398 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
399 }
400 return true;
401}
402
403static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
404{
405 struct rtl_priv *rtlpriv = rtl_priv(hw);
406 struct rtl_phy *rtlphy = &(rtlpriv->phy);
407
408 /* RF Interface Sowrtware Control */
409 /* 16 LSBs if read 32-bit from 0x870 */
410 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
411 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
412 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
413 /* 16 LSBs if read 32-bit from 0x874 */
414 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
415 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
416
417 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
418 /* RF Interface Readback Value */
419 /* 16 LSBs if read 32-bit from 0x8E0 */
420 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
421 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
422 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
423 /* 16 LSBs if read 32-bit from 0x8E4 */
424 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
425 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
426 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
427
428 /* RF Interface Output (and Enable) */
429 /* 16 LSBs if read 32-bit from 0x860 */
430 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
431 /* 16 LSBs if read 32-bit from 0x864 */
432 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
433
434 /* RF Interface (Output and) Enable */
435 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
436 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
437 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
438 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
439
440 /* Addr of LSSI. Wirte RF register by driver */
441 /* LSSI Parameter */
442 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
443 RFPGA0_XA_LSSIPARAMETER;
444 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
445 RFPGA0_XB_LSSIPARAMETER;
446
447 /* RF parameter */
448 /* BB Band Select */
449 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
450 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
451 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
452 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
453
454 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
455 /* Tx gain stage */
456 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
457 /* Tx gain stage */
458 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
459 /* Tx gain stage */
460 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
461 /* Tx gain stage */
462 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
463
464 /* Tranceiver A~D HSSI Parameter-1 */
465 /* wire control parameter1 */
466 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
467 /* wire control parameter1 */
468 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
469
470 /* Tranceiver A~D HSSI Parameter-2 */
471 /* wire control parameter2 */
472 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
473 /* wire control parameter2 */
474 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
475
476 /* RF switch Control */
477 /* TR/Ant switch control */
478 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
479 RFPGA0_XAB_SWITCHCONTROL;
480 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
481 RFPGA0_XAB_SWITCHCONTROL;
482 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
483 RFPGA0_XCD_SWITCHCONTROL;
484 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
485 RFPGA0_XCD_SWITCHCONTROL;
486
487 /* AGC control 1 */
488 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
489 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
490 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
491 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
492
493 /* AGC control 2 */
494 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
495 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
496 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
497 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
498
499 /* RX AFE control 1 */
500 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
501 ROFDM0_XARXIQIMBALANCE;
502 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
503 ROFDM0_XBRXIQIMBALANCE;
504 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
505 ROFDM0_XCRXIQIMBALANCE;
506 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
507 ROFDM0_XDRXIQIMBALANCE;
508
509 /*RX AFE control 1 */
510 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
511 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
512 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
513 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
514
515 /* Tx AFE control 1 */
516 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
517 ROFDM0_XATxIQIMBALANCE;
518 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
519 ROFDM0_XBTxIQIMBALANCE;
520 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
521 ROFDM0_XCTxIQIMBALANCE;
522 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
523 ROFDM0_XDTxIQIMBALANCE;
524
525 /* Tx AFE control 2 */
526 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
527 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
528 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
529 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
530
531 /* Tranceiver LSSI Readback SI mode */
532 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
533 RFPGA0_XA_LSSIREADBACK;
534 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
535 RFPGA0_XB_LSSIREADBACK;
536 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
537 RFPGA0_XC_LSSIREADBACK;
538 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
539 RFPGA0_XD_LSSIREADBACK;
540
541 /* Tranceiver LSSI Readback PI mode */
542 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
543 TRANSCEIVERA_HSPI_READBACK;
544 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
545 TRANSCEIVERB_HSPI_READBACK;
546}
547
548static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
549 u8 configtype)
550{
551 int i;
552 u32 *phy_regarray_table;
553 u32 *agctab_array_table = NULL;
554 u32 *agctab_5garray_table;
555 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
558
559 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
560 if (rtlhal->interfaceindex == 0) {
561 agctab_arraylen = AGCTAB_ARRAYLENGTH;
562 agctab_array_table = rtl8192de_agctab_array;
563 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
564 (" ===> phy:MAC0, Rtl819XAGCTAB_Array\n"));
565 } else {
566 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
567 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
568 agctab_array_table = rtl8192de_agctab_2garray;
569 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
570 (" ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"));
571 } else {
572 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
573 agctab_5garray_table = rtl8192de_agctab_5garray;
574 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
575 (" ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"));
576
577 }
578 }
579 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
580 phy_regarray_table = rtl8192de_phy_reg_2tarray;
581 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
582 (" ===> phy:Rtl819XPHY_REG_Array_PG\n"));
583 if (configtype == BASEBAND_CONFIG_PHY_REG) {
584 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
585 if (phy_regarray_table[i] == 0xfe)
586 mdelay(50);
587 else if (phy_regarray_table[i] == 0xfd)
588 mdelay(5);
589 else if (phy_regarray_table[i] == 0xfc)
590 mdelay(1);
591 else if (phy_regarray_table[i] == 0xfb)
592 udelay(50);
593 else if (phy_regarray_table[i] == 0xfa)
594 udelay(5);
595 else if (phy_regarray_table[i] == 0xf9)
596 udelay(1);
597 rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
598 phy_regarray_table[i + 1]);
599 udelay(1);
600 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
601 ("The phy_regarray_table[0] is %x"
602 " Rtl819XPHY_REGArray[1] is %x\n",
603 phy_regarray_table[i],
604 phy_regarray_table[i + 1]));
605 }
606 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
607 if (rtlhal->interfaceindex == 0) {
608 for (i = 0; i < agctab_arraylen; i = i + 2) {
609 rtl_set_bbreg(hw, agctab_array_table[i],
610 BMASKDWORD,
611 agctab_array_table[i + 1]);
612 /* Add 1us delay between BB/RF register
613 * setting. */
614 udelay(1);
615 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
616 ("The Rtl819XAGCTAB_Array_"
617 "Table[0] is %ul "
618 "Rtl819XPHY_REGArray[1] is %ul\n",
619 agctab_array_table[i],
620 agctab_array_table[i + 1]));
621 }
622 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
623 ("Normal Chip, MAC0, load "
624 "Rtl819XAGCTAB_Array\n"));
625 } else {
626 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
627 for (i = 0; i < agctab_arraylen; i = i + 2) {
628 rtl_set_bbreg(hw, agctab_array_table[i],
629 BMASKDWORD,
630 agctab_array_table[i + 1]);
631 /* Add 1us delay between BB/RF register
632 * setting. */
633 udelay(1);
634 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
635 ("The Rtl819XAGCTAB_Array_"
636 "Table[0] is %ul Rtl819XPHY_"
637 "REGArray[1] is %ul\n",
638 agctab_array_table[i],
639 agctab_array_table[i + 1]));
640 }
641 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
642 ("Load Rtl819XAGCTAB_2GArray\n"));
643 } else {
644 for (i = 0; i < agctab_5garraylen; i = i + 2) {
645 rtl_set_bbreg(hw,
646 agctab_5garray_table[i],
647 BMASKDWORD,
648 agctab_5garray_table[i + 1]);
649 /* Add 1us delay between BB/RF registeri
650 * setting. */
651 udelay(1);
652 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
653 ("The Rtl819XAGCTAB_5GArray_"
654 "Table[0] is %ul Rtl819XPHY_"
655 "REGArray[1] is %ul\n",
656 agctab_5garray_table[i],
657 agctab_5garray_table[i + 1]));
658 }
659 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
660 ("Load Rtl819XAGCTAB_5GArray\n"));
661 }
662 }
663 }
664 return true;
665}
666
667static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
668 u32 regaddr, u32 bitmask,
669 u32 data)
670{
671 struct rtl_priv *rtlpriv = rtl_priv(hw);
672 struct rtl_phy *rtlphy = &(rtlpriv->phy);
673
674 if (regaddr == RTXAGC_A_RATE18_06) {
675 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
676 data;
677 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
678 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%ulx\n",
679 rtlphy->pwrgroup_cnt,
680 rtlphy->mcs_txpwrlevel_origoffset
681 [rtlphy->pwrgroup_cnt][0]));
682 }
683 if (regaddr == RTXAGC_A_RATE54_24) {
684 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
685 data;
686 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
687 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%ulx\n",
688 rtlphy->pwrgroup_cnt,
689 rtlphy->mcs_txpwrlevel_origoffset
690 [rtlphy->pwrgroup_cnt][1]));
691 }
692 if (regaddr == RTXAGC_A_CCK1_MCS32) {
693 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
694 data;
695 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
696 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%ulx\n",
697 rtlphy->pwrgroup_cnt,
698 rtlphy->mcs_txpwrlevel_origoffset
699 [rtlphy->pwrgroup_cnt][6]));
700 }
701 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
702 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
703 data;
704 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
705 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%ulx\n",
706 rtlphy->pwrgroup_cnt,
707 rtlphy->mcs_txpwrlevel_origoffset
708 [rtlphy->pwrgroup_cnt][7]));
709 }
710 if (regaddr == RTXAGC_A_MCS03_MCS00) {
711 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
712 data;
713 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
714 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%ulx\n",
715 rtlphy->pwrgroup_cnt,
716 rtlphy->mcs_txpwrlevel_origoffset
717 [rtlphy->pwrgroup_cnt][2]));
718 }
719 if (regaddr == RTXAGC_A_MCS07_MCS04) {
720 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
721 data;
722 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
723 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%ulx\n",
724 rtlphy->pwrgroup_cnt,
725 rtlphy->mcs_txpwrlevel_origoffset
726 [rtlphy->pwrgroup_cnt][3]));
727 }
728 if (regaddr == RTXAGC_A_MCS11_MCS08) {
729 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
730 data;
731 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
732 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%ulx\n",
733 rtlphy->pwrgroup_cnt,
734 rtlphy->mcs_txpwrlevel_origoffset
735 [rtlphy->pwrgroup_cnt][4]));
736 }
737 if (regaddr == RTXAGC_A_MCS15_MCS12) {
738 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
739 data;
740 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
741 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%ulx\n",
742 rtlphy->pwrgroup_cnt,
743 rtlphy->mcs_txpwrlevel_origoffset
744 [rtlphy->pwrgroup_cnt][5]));
745 }
746 if (regaddr == RTXAGC_B_RATE18_06) {
747 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
748 data;
749 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
750 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%ulx\n",
751 rtlphy->pwrgroup_cnt,
752 rtlphy->mcs_txpwrlevel_origoffset
753 [rtlphy->pwrgroup_cnt][8]));
754 }
755 if (regaddr == RTXAGC_B_RATE54_24) {
756 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
757 data;
758 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
759 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%ulx\n",
760 rtlphy->pwrgroup_cnt,
761 rtlphy->mcs_txpwrlevel_origoffset
762 [rtlphy->pwrgroup_cnt][9]));
763 }
764 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
765 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
766 data;
767 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
768 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%ulx\n",
769 rtlphy->pwrgroup_cnt,
770 rtlphy->mcs_txpwrlevel_origoffset
771 [rtlphy->pwrgroup_cnt][14]));
772 }
773 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
774 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
775 data;
776 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
777 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%ulx\n",
778 rtlphy->pwrgroup_cnt,
779 rtlphy->mcs_txpwrlevel_origoffset
780 [rtlphy->pwrgroup_cnt][15]));
781 }
782 if (regaddr == RTXAGC_B_MCS03_MCS00) {
783 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
784 data;
785 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
786 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%ulx\n",
787 rtlphy->pwrgroup_cnt,
788 rtlphy->mcs_txpwrlevel_origoffset
789 [rtlphy->pwrgroup_cnt][10]));
790 }
791 if (regaddr == RTXAGC_B_MCS07_MCS04) {
792 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
793 data;
794 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
795 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%ulx\n",
796 rtlphy->pwrgroup_cnt,
797 rtlphy->mcs_txpwrlevel_origoffset
798 [rtlphy->pwrgroup_cnt][11]));
799 }
800 if (regaddr == RTXAGC_B_MCS11_MCS08) {
801 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
802 data;
803 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
804 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%ulx\n",
805 rtlphy->pwrgroup_cnt,
806 rtlphy->mcs_txpwrlevel_origoffset
807 [rtlphy->pwrgroup_cnt][12]));
808 }
809 if (regaddr == RTXAGC_B_MCS15_MCS12) {
810 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
811 data;
812 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
813 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%ulx\n",
814 rtlphy->pwrgroup_cnt,
815 rtlphy->mcs_txpwrlevel_origoffset
816 [rtlphy->pwrgroup_cnt][13]));
817 rtlphy->pwrgroup_cnt++;
818 }
819}
820
821static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
822 u8 configtype)
823{
824 struct rtl_priv *rtlpriv = rtl_priv(hw);
825 int i;
826 u32 *phy_regarray_table_pg;
827 u16 phy_regarray_pg_len;
828
829 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
830 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
831 if (configtype == BASEBAND_CONFIG_PHY_REG) {
832 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
833 if (phy_regarray_table_pg[i] == 0xfe)
834 mdelay(50);
835 else if (phy_regarray_table_pg[i] == 0xfd)
836 mdelay(5);
837 else if (phy_regarray_table_pg[i] == 0xfc)
838 mdelay(1);
839 else if (phy_regarray_table_pg[i] == 0xfb)
840 udelay(50);
841 else if (phy_regarray_table_pg[i] == 0xfa)
842 udelay(5);
843 else if (phy_regarray_table_pg[i] == 0xf9)
844 udelay(1);
845 _rtl92d_store_pwrindex_diffrate_offset(hw,
846 phy_regarray_table_pg[i],
847 phy_regarray_table_pg[i + 1],
848 phy_regarray_table_pg[i + 2]);
849 }
850 } else {
851 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
852 ("configtype != BaseBand_Config_PHY_REG\n"));
853 }
854 return true;
855}
856
857static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
858{
859 struct rtl_priv *rtlpriv = rtl_priv(hw);
860 struct rtl_phy *rtlphy = &(rtlpriv->phy);
861 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
862 bool rtstatus = true;
863
864 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
865 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
866 BASEBAND_CONFIG_PHY_REG);
867 if (rtstatus != true) {
868 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
869 return false;
870 }
871
872 /* if (rtlphy->rf_type == RF_1T2R) {
873 * _rtl92c_phy_bb_config_1t(hw);
874 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
875 *} */
876
877 if (rtlefuse->autoload_failflag == false) {
878 rtlphy->pwrgroup_cnt = 0;
879 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
880 BASEBAND_CONFIG_PHY_REG);
881 }
882 if (rtstatus != true) {
883 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
884 return false;
885 }
886 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
887 BASEBAND_CONFIG_AGC_TAB);
888 if (rtstatus != true) {
889 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
890 return false;
891 }
892 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
893 RFPGA0_XA_HSSIPARAMETER2, 0x200));
894
895 return true;
896}
897
898bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
899{
900 struct rtl_priv *rtlpriv = rtl_priv(hw);
901 u16 regval;
902 u32 regvaldw;
903 u8 value;
904
905 _rtl92d_phy_init_bb_rf_register_definition(hw);
906 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
907 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
908 regval | BIT(13) | BIT(0) | BIT(1));
909 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
910 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
911 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
912 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
913 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
914 RF_SDMRSTB);
915 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
916 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
917 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
918 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
919 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
920 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
921 }
922
923 return _rtl92d_phy_bb_config(hw);
924}
925
926bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
927{
928 return rtl92d_phy_rf6052_config(hw);
929}
930
931bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
932 enum rf_content content,
933 enum radio_path rfpath)
934{
935 int i;
936 u32 *radioa_array_table;
937 u32 *radiob_array_table;
938 u16 radioa_arraylen, radiob_arraylen;
939 struct rtl_priv *rtlpriv = rtl_priv(hw);
940
941 radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
942 radioa_array_table = rtl8192de_radioa_2tarray;
943 radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
944 radiob_array_table = rtl8192de_radiob_2tarray;
945 if (rtlpriv->efuse.internal_pa_5g[0]) {
946 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
947 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
948 }
949 if (rtlpriv->efuse.internal_pa_5g[1]) {
950 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
951 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
952 }
953 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
954 ("PHY_ConfigRFWithHeaderFile() "
955 "Radio_A:Rtl819XRadioA_1TArray\n"));
956 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
957 ("PHY_ConfigRFWithHeaderFile() "
958 "Radio_B:Rtl819XRadioB_1TArray\n"));
959 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
960
961 /* this only happens when DMDP, mac0 start on 2.4G,
962 * mac1 start on 5G, mac 0 has to set phy0&phy1
963 * pathA or mac1 has to set phy0&phy1 pathA */
964 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
965 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
966 (" ===> althougth Path A, we load radiob.txt\n"));
967 radioa_arraylen = radiob_arraylen;
968 radioa_array_table = radiob_array_table;
969 }
970 switch (rfpath) {
971 case RF90_PATH_A:
972 for (i = 0; i < radioa_arraylen; i = i + 2) {
973 if (radioa_array_table[i] == 0xfe) {
974 mdelay(50);
975 } else if (radioa_array_table[i] == 0xfd) {
976 /* delay_ms(5); */
977 mdelay(5);
978 } else if (radioa_array_table[i] == 0xfc) {
979 /* delay_ms(1); */
980 mdelay(1);
981 } else if (radioa_array_table[i] == 0xfb) {
982 udelay(50);
983 } else if (radioa_array_table[i] == 0xfa) {
984 udelay(5);
985 } else if (radioa_array_table[i] == 0xf9) {
986 udelay(1);
987 } else {
988 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
989 BRFREGOFFSETMASK,
990 radioa_array_table[i + 1]);
991 /* Add 1us delay between BB/RF register set. */
992 udelay(1);
993 }
994 }
995 break;
996 case RF90_PATH_B:
997 for (i = 0; i < radiob_arraylen; i = i + 2) {
998 if (radiob_array_table[i] == 0xfe) {
999 /* Delay specific ms. Only RF configuration
1000 * requires delay. */
1001 mdelay(50);
1002 } else if (radiob_array_table[i] == 0xfd) {
1003 /* delay_ms(5); */
1004 mdelay(5);
1005 } else if (radiob_array_table[i] == 0xfc) {
1006 /* delay_ms(1); */
1007 mdelay(1);
1008 } else if (radiob_array_table[i] == 0xfb) {
1009 udelay(50);
1010 } else if (radiob_array_table[i] == 0xfa) {
1011 udelay(5);
1012 } else if (radiob_array_table[i] == 0xf9) {
1013 udelay(1);
1014 } else {
1015 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
1016 BRFREGOFFSETMASK,
1017 radiob_array_table[i + 1]);
1018 /* Add 1us delay between BB/RF register set. */
1019 udelay(1);
1020 }
1021 }
1022 break;
1023 case RF90_PATH_C:
1024 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1025 ("switch case not process\n"));
1026 break;
1027 case RF90_PATH_D:
1028 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1029 ("switch case not process\n"));
1030 break;
1031 }
1032 return true;
1033}
1034
1035void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1036{
1037 struct rtl_priv *rtlpriv = rtl_priv(hw);
1038 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1039
1040 rtlphy->default_initialgain[0] =
1041 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0);
1042 rtlphy->default_initialgain[1] =
1043 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0);
1044 rtlphy->default_initialgain[2] =
1045 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0);
1046 rtlphy->default_initialgain[3] =
1047 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0);
1048 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1049 ("Default initial gain (c50=0x%x, "
1050 "c58=0x%x, c60=0x%x, c68=0x%x\n",
1051 rtlphy->default_initialgain[0],
1052 rtlphy->default_initialgain[1],
1053 rtlphy->default_initialgain[2],
1054 rtlphy->default_initialgain[3]));
1055 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
1056 BMASKBYTE0);
1057 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1058 BMASKDWORD);
1059 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1060 ("Default framesync (0x%x) = 0x%x\n",
1061 ROFDM0_RXDETECTOR3, rtlphy->framesync));
1062}
1063
1064static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1065 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1066{
1067 struct rtl_priv *rtlpriv = rtl_priv(hw);
1068 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1069 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1070 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1071 u8 index = (channel - 1);
1072
1073 /* 1. CCK */
1074 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1075 /* RF-A */
1076 cckpowerlevel[RF90_PATH_A] =
1077 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
1078 /* RF-B */
1079 cckpowerlevel[RF90_PATH_B] =
1080 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
1081 } else {
1082 cckpowerlevel[RF90_PATH_A] = 0;
1083 cckpowerlevel[RF90_PATH_B] = 0;
1084 }
1085 /* 2. OFDM for 1S or 2S */
1086 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1087 /* Read HT 40 OFDM TX power */
1088 ofdmpowerlevel[RF90_PATH_A] =
1089 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
1090 ofdmpowerlevel[RF90_PATH_B] =
1091 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
1092 } else if (rtlphy->rf_type == RF_2T2R) {
1093 /* Read HT 40 OFDM TX power */
1094 ofdmpowerlevel[RF90_PATH_A] =
1095 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
1096 ofdmpowerlevel[RF90_PATH_B] =
1097 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
1098 }
1099}
1100
1101static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
1102 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1103{
1104 struct rtl_priv *rtlpriv = rtl_priv(hw);
1105 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1106
1107 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1108 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1109}
1110
1111static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
1112{
1113 u8 channel_5g[59] = {
1114 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1115 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1116 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1117 114, 116, 118, 120, 122, 124, 126, 128,
1118 130, 132, 134, 136, 138, 140, 149, 151,
1119 153, 155, 157, 159, 161, 163, 165
1120 };
1121 u8 place = chnl;
1122
1123 if (chnl > 14) {
1124 for (place = 14; place < sizeof(channel_5g); place++) {
1125 if (channel_5g[place] == chnl) {
1126 place++;
1127 break;
1128 }
1129 }
1130 }
1131 return place;
1132}
1133
1134void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1135{
1136 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1137 struct rtl_priv *rtlpriv = rtl_priv(hw);
1138 u8 cckpowerlevel[2], ofdmpowerlevel[2];
1139
1140 if (rtlefuse->txpwr_fromeprom == false)
1141 return;
1142 channel = _rtl92c_phy_get_rightchnlplace(channel);
1143 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
1144 &ofdmpowerlevel[0]);
1145 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1146 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
1147 &ofdmpowerlevel[0]);
1148 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1149 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1150 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
1151}
1152
1153void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1154{
1155 struct rtl_priv *rtlpriv = rtl_priv(hw);
1156 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1157 enum io_type iotype;
1158
1159 if (!is_hal_stop(rtlhal)) {
1160 switch (operation) {
1161 case SCAN_OPT_BACKUP:
1162 rtlhal->current_bandtypebackup =
1163 rtlhal->current_bandtype;
1164 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
1165 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1166 (u8 *)&iotype);
1167 break;
1168 case SCAN_OPT_RESTORE:
1169 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1170 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1171 (u8 *)&iotype);
1172 break;
1173 default:
1174 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1175 ("Unknown Scan Backup operation.\n"));
1176 break;
1177 }
1178 }
1179}
1180
1181void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
1182 enum nl80211_channel_type ch_type)
1183{
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1186 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1187 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1188 unsigned long flag = 0;
1189 u8 reg_prsr_rsc;
1190 u8 reg_bw_opmode;
1191
1192 if (rtlphy->set_bwmode_inprogress)
1193 return;
1194 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
1195 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1196 ("FALSE driver sleep or unload\n"));
1197 return;
1198 }
1199 rtlphy->set_bwmode_inprogress = true;
1200 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1201 ("Switch to %s bandwidth\n",
1202 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1203 "20MHz" : "40MHz"));
1204 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1205 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1206 switch (rtlphy->current_chan_bw) {
1207 case HT_CHANNEL_WIDTH_20:
1208 reg_bw_opmode |= BW_OPMODE_20MHZ;
1209 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1210 break;
1211 case HT_CHANNEL_WIDTH_20_40:
1212 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1213 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1214
1215 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1216 (mac->cur_40_prime_sc << 5);
1217 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1218 break;
1219 default:
1220 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1221 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1222 break;
1223 }
1224 switch (rtlphy->current_chan_bw) {
1225 case HT_CHANNEL_WIDTH_20:
1226 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1227 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1228 /* SET BIT10 BIT11 for receive cck */
1229 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1230 BIT(11), 3);
1231 break;
1232 case HT_CHANNEL_WIDTH_20_40:
1233 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1234 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1235 /* Set Control channel to upper or lower.
1236 * These settings are required only for 40MHz */
1237 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1238 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1239 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1240 (mac->cur_40_prime_sc >> 1));
1241 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1242 }
1243 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1244 /* SET BIT10 BIT11 for receive cck */
1245 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1246 BIT(11), 0);
1247 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1248 (mac->cur_40_prime_sc ==
1249 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1250 break;
1251 default:
1252 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1253 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1254 break;
1255
1256 }
1257 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1258 rtlphy->set_bwmode_inprogress = false;
1259 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
1260}
1261
1262static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1263{
1264 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1265 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1266 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00);
1267 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1268}
1269
1270static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1271{
1272 struct rtl_priv *rtlpriv = rtl_priv(hw);
1273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1274 u8 value8;
1275
1276 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==>\n"));
1277 rtlhal->bandset = band;
1278 rtlhal->current_bandtype = band;
1279 if (IS_92D_SINGLEPHY(rtlhal->version))
1280 rtlhal->bandset = BAND_ON_BOTH;
1281 /* stop RX/Tx */
1282 _rtl92d_phy_stop_trx_before_changeband(hw);
1283 /* reconfig BB/RF according to wireless mode */
1284 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1285 /* BB & RF Config */
1286 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("====>2.4G\n"));
1287 if (rtlhal->interfaceindex == 1)
1288 _rtl92d_phy_config_bb_with_headerfile(hw,
1289 BASEBAND_CONFIG_AGC_TAB);
1290 } else {
1291 /* 5G band */
1292 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("====>5G\n"));
1293 if (rtlhal->interfaceindex == 1)
1294 _rtl92d_phy_config_bb_with_headerfile(hw,
1295 BASEBAND_CONFIG_AGC_TAB);
1296 }
1297 rtl92d_update_bbrf_configuration(hw);
1298 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1299 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1300 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1301
1302 /* 20M BW. */
1303 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1304 rtlhal->reloadtxpowerindex = true;
1305 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1306 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1307 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1308 0 ? REG_MAC0 : REG_MAC1));
1309 value8 |= BIT(1);
1310 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1311 0 ? REG_MAC0 : REG_MAC1), value8);
1312 } else {
1313 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1314 0 ? REG_MAC0 : REG_MAC1));
1315 value8 &= (~BIT(1));
1316 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1317 0 ? REG_MAC0 : REG_MAC1), value8);
1318 }
1319 mdelay(1);
1320 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<==Switch Band OK.\n"));
1321}
1322
1323static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1324 u8 channel, u8 rfpath)
1325{
1326 struct rtl_priv *rtlpriv = rtl_priv(hw);
1327 u32 imr_num = MAX_RF_IMR_INDEX;
1328 u32 rfmask = BRFREGOFFSETMASK;
1329 u8 group, i;
1330 unsigned long flag = 0;
1331
1332 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>path %d\n", rfpath));
1333 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1334 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>5G\n"));
1335 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1336 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1337 /* fc area 0xd2c */
1338 if (channel > 99)
1339 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1340 BIT(14), 2);
1341 else
1342 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1343 BIT(14), 1);
1344 /* leave 0 for channel1-14. */
1345 group = channel <= 64 ? 1 : 2;
1346 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1347 for (i = 0; i < imr_num; i++)
1348 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1349 rf_reg_for_5g_swchnl_normal[i], rfmask,
1350 rf_imr_param_normal[0][group][i]);
1351 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1352 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1353 } else {
1354 /* G band. */
1355 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1356 ("Load RF IMR parameters for G band. IMR already "
1357 "setting %d\n",
1358 rtlpriv->rtlhal.load_imrandiqk_setting_for2g));
1359 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>2.4G\n"));
1360 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1361 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1362 ("Load RF IMR parameters "
1363 "for G band. %d\n", rfpath));
1364 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1365 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1366 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1367 0x00f00000, 0xf);
1368 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1369 for (i = 0; i < imr_num; i++) {
1370 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1371 rf_reg_for_5g_swchnl_normal[i],
1372 BRFREGOFFSETMASK,
1373 rf_imr_param_normal[0][0][i]);
1374 }
1375 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1376 0x00f00000, 0);
1377 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1378 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1379 }
1380 }
1381 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
1382}
1383
1384static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1385 u8 rfpath, u32 *pu4_regval)
1386{
1387 struct rtl_priv *rtlpriv = rtl_priv(hw);
1388 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1389 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1390
1391 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("====>\n"));
1392 /*----Store original RFENV control type----*/
1393 switch (rfpath) {
1394 case RF90_PATH_A:
1395 case RF90_PATH_C:
1396 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1397 break;
1398 case RF90_PATH_B:
1399 case RF90_PATH_D:
1400 *pu4_regval =
1401 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1402 break;
1403 }
1404 /*----Set RF_ENV enable----*/
1405 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1406 udelay(1);
1407 /*----Set RF_ENV output high----*/
1408 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1409 udelay(1);
1410 /* Set bit number of Address and Data for RF register */
1411 /* Set 1 to 4 bits for 8255 */
1412 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1413 udelay(1);
1414 /*Set 0 to 12 bits for 8255 */
1415 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1416 udelay(1);
1417 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<====\n"));
1418}
1419
1420static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1421 u32 *pu4_regval)
1422{
1423 struct rtl_priv *rtlpriv = rtl_priv(hw);
1424 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1425 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1426
1427 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("=====>\n"));
1428 /*----Restore RFENV control type----*/ ;
1429 switch (rfpath) {
1430 case RF90_PATH_A:
1431 case RF90_PATH_C:
1432 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1433 break;
1434 case RF90_PATH_B:
1435 case RF90_PATH_D:
1436 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1437 *pu4_regval);
1438 break;
1439 }
1440 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<=====\n"));
1441}
1442
1443static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1444{
1445 struct rtl_priv *rtlpriv = rtl_priv(hw);
1446 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1447 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1448 u8 path = rtlhal->current_bandtype ==
1449 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1450 u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1451 bool need_pwr_down = false, internal_pa = false;
1452 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1453
1454 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>\n"));
1455 /* config path A for 5G */
1456 if (rtlhal->current_bandtype == BAND_ON_5G) {
1457 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>5G\n"));
1458 u4tmp = curveindex_5g[channel - 1];
1459 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 1 set RF-A, 5G, "
1460 "0x28 = 0x%x !!\n", u4tmp));
1461 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1462 if (channel == rf_chnl_5g[i] && channel <= 140)
1463 index = 0;
1464 }
1465 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1466 if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1467 index = 1;
1468 }
1469 if (channel == 149 || channel == 155 || channel == 161)
1470 index = 2;
1471 else if (channel == 151 || channel == 153 || channel == 163
1472 || channel == 165)
1473 index = 3;
1474 else if (channel == 157 || channel == 159)
1475 index = 4;
1476
1477 if (rtlhal->macphymode == DUALMAC_DUALPHY
1478 && rtlhal->interfaceindex == 1) {
1479 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1480 rtlhal->during_mac1init_radioa = true;
1481 /* asume no this case */
1482 if (need_pwr_down)
1483 _rtl92d_phy_enable_rf_env(hw, path,
1484 &u4regvalue);
1485 }
1486 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1487 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1488 rtl_set_rfreg(hw, (enum radio_path)path,
1489 rf_reg_for_c_cut_5g[i],
1490 BRFREGOFFSETMASK, 0xE439D);
1491 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1492 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1493 0x7FF) | (u4tmp << 11);
1494 if (channel == 36)
1495 u4tmp2 &= ~(BIT(7) | BIT(6));
1496 rtl_set_rfreg(hw, (enum radio_path)path,
1497 rf_reg_for_c_cut_5g[i],
1498 BRFREGOFFSETMASK, u4tmp2);
1499 } else {
1500 rtl_set_rfreg(hw, (enum radio_path)path,
1501 rf_reg_for_c_cut_5g[i],
1502 BRFREGOFFSETMASK,
1503 rf_reg_pram_c_5g[index][i]);
1504 }
1505 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1506 ("offset 0x%x value 0x%x "
1507 "path %d index %d readback 0x%x\n",
1508 rf_reg_for_c_cut_5g[i],
1509 rf_reg_pram_c_5g[index][i], path,
1510 index, rtl_get_rfreg(hw, (enum radio_path)path,
1511 rf_reg_for_c_cut_5g[i], BRFREGOFFSETMASK)));
1512 }
1513 if (need_pwr_down)
1514 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1515 if (rtlhal->during_mac1init_radioa)
1516 rtl92d_phy_powerdown_anotherphy(hw, false);
1517 if (channel < 149)
1518 value = 0x07;
1519 else if (channel >= 149)
1520 value = 0x02;
1521 if (channel >= 36 && channel <= 64)
1522 index = 0;
1523 else if (channel >= 100 && channel <= 140)
1524 index = 1;
1525 else
1526 index = 2;
1527 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1528 rfpath++) {
1529 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1530 rtlhal->interfaceindex == 1) /* MAC 1 5G */
1531 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1532 else
1533 internal_pa =
1534 rtlpriv->efuse.internal_pa_5g[rfpath];
1535 if (internal_pa) {
1536 for (i = 0;
1537 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1538 i++) {
1539 rtl_set_rfreg(hw, rfpath,
1540 rf_for_c_cut_5g_internal_pa[i],
1541 BRFREGOFFSETMASK,
1542 rf_pram_c_5g_int_pa[index][i]);
1543 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1544 ("offset 0x%x value 0x%x "
1545 "path %d index %d\n",
1546 rf_for_c_cut_5g_internal_pa[i],
1547 rf_pram_c_5g_int_pa[index][i],
1548 rfpath, index));
1549 }
1550 } else {
1551 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1552 mask, value);
1553 }
1554 }
1555 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1556 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>2.4G\n"));
1557 u4tmp = curveindex_2g[channel - 1];
1558 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 3 set RF-B, 2G, "
1559 "0x28 = 0x%x !!\n", u4tmp));
1560 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1561 || channel == 10 || channel == 11 || channel == 12)
1562 index = 0;
1563 else if (channel == 3 || channel == 13 || channel == 14)
1564 index = 1;
1565 else if (channel >= 5 && channel <= 8)
1566 index = 2;
1567 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1568 path = RF90_PATH_A;
1569 if (rtlhal->interfaceindex == 0) {
1570 need_pwr_down =
1571 rtl92d_phy_enable_anotherphy(hw, true);
1572 rtlhal->during_mac0init_radiob = true;
1573
1574 if (need_pwr_down)
1575 _rtl92d_phy_enable_rf_env(hw, path,
1576 &u4regvalue);
1577 }
1578 }
1579 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1580 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1581 rtl_set_rfreg(hw, (enum radio_path)path,
1582 rf_reg_for_c_cut_2g[i],
1583 BRFREGOFFSETMASK,
1584 (rf_reg_param_for_c_cut_2g[index][i] |
1585 BIT(17)));
1586 else
1587 rtl_set_rfreg(hw, (enum radio_path)path,
1588 rf_reg_for_c_cut_2g[i],
1589 BRFREGOFFSETMASK,
1590 rf_reg_param_for_c_cut_2g
1591 [index][i]);
1592 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1593 ("offset 0x%x value 0x%x mak 0x%x path %d "
1594 "index %d readback 0x%x\n",
1595 rf_reg_for_c_cut_2g[i],
1596 rf_reg_param_for_c_cut_2g[index][i],
1597 rf_reg_mask_for_c_cut_2g[i], path, index,
1598 rtl_get_rfreg(hw, (enum radio_path)path,
1599 rf_reg_for_c_cut_2g[i],
1600 BRFREGOFFSETMASK)));
1601 }
1602 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1603 ("cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1604 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)));
1605
1606 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1607 BRFREGOFFSETMASK,
1608 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1609 if (need_pwr_down)
1610 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1611 if (rtlhal->during_mac0init_radiob)
1612 rtl92d_phy_powerdown_anotherphy(hw, true);
1613 }
1614 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
1615}
1616
1617u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1618{
1619 u8 channel_all[59] = {
1620 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1621 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1622 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1623 114, 116, 118, 120, 122, 124, 126, 128, 130,
1624 132, 134, 136, 138, 140, 149, 151, 153, 155,
1625 157, 159, 161, 163, 165
1626 };
1627 u8 place = chnl;
1628
1629 if (chnl > 14) {
1630 for (place = 14; place < sizeof(channel_all); place++) {
1631 if (channel_all[place] == chnl)
1632 return place - 13;
1633 }
1634 }
1635
1636 return 0;
1637}
1638
1639#define MAX_TOLERANCE 5
1640#define IQK_DELAY_TIME 1 /* ms */
1641#define MAX_TOLERANCE_92D 3
1642
1643/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1644static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1645{
1646 struct rtl_priv *rtlpriv = rtl_priv(hw);
1647 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1648 u32 regeac, rege94, rege9c, regea4;
1649 u8 result = 0;
1650
1651 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n"));
1652 /* path-A IQK setting */
1653 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1654 if (rtlhal->interfaceindex == 0) {
1655 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f);
1656 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f);
1657 } else {
1658 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22);
1659 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22);
1660 }
1661 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102);
1662 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206);
1663 /* path-B IQK setting */
1664 if (configpathb) {
1665 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22);
1666 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22);
1667 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102);
1668 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206);
1669 }
1670 /* LO calibration setting */
1671 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1672 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1673 /* One shot, path A LOK & IQK */
1674 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
1675 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1676 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1677 /* delay x ms */
1678 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1679 ("Delay %d ms for One shot, path A LOK & IQK.\n",
1680 IQK_DELAY_TIME));
1681 mdelay(IQK_DELAY_TIME);
1682 /* Check failed */
1683 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1684 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1685 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1686 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94));
1687 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1688 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c));
1689 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1690 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4));
1691 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1692 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1693 result |= 0x01;
1694 else /* if Tx not OK, ignore Rx */
1695 return result;
1696 /* if Tx is OK, check whether Rx is OK */
1697 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1698 (((regeac & 0x03FF0000) >> 16) != 0x36))
1699 result |= 0x02;
1700 else
1701 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
1702 return result;
1703}
1704
1705/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1706static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1707 bool configpathb)
1708{
1709 struct rtl_priv *rtlpriv = rtl_priv(hw);
1710 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1711 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1712 u32 regeac, rege94, rege9c, regea4;
1713 u8 result = 0;
1714 u8 i;
1715 u8 retrycount = 2;
1716 u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1717
1718 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1719 TxOKBit = BIT(31);
1720 RxOKBit = BIT(30);
1721 }
1722 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n"));
1723 /* path-A IQK setting */
1724 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1725 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1726 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1727 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307);
1728 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960);
1729 /* path-B IQK setting */
1730 if (configpathb) {
1731 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1732 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1733 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000);
1734 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000);
1735 }
1736 /* LO calibration setting */
1737 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1738 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1739 /* path-A PA on */
1740 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60);
1741 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30);
1742 for (i = 0; i < retrycount; i++) {
1743 /* One shot, path A LOK & IQK */
1744 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1745 ("One shot, path A LOK & IQK!\n"));
1746 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1747 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1748 /* delay x ms */
1749 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1750 ("Delay %d ms for One shot, path A LOK & IQK.\n",
1751 IQK_DELAY_TIME));
1752 mdelay(IQK_DELAY_TIME * 10);
1753 /* Check failed */
1754 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1755 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1756 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1757 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94));
1758 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1759 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c));
1760 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1761 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4));
1762 if (!(regeac & TxOKBit) &&
1763 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1764 result |= 0x01;
1765 } else { /* if Tx not OK, ignore Rx */
1766 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1767 ("Path A Tx IQK fail!!\n"));
1768 continue;
1769 }
1770
1771 /* if Tx is OK, check whether Rx is OK */
1772 if (!(regeac & RxOKBit) &&
1773 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1774 result |= 0x02;
1775 break;
1776 } else {
1777 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1778 ("Path A Rx IQK fail!!\n"));
1779 }
1780 }
1781 /* path A PA off */
1782 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1783 rtlphy->iqk_bb_backup[0]);
1784 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD,
1785 rtlphy->iqk_bb_backup[1]);
1786 return result;
1787}
1788
1789/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1790static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1791{
1792 struct rtl_priv *rtlpriv = rtl_priv(hw);
1793 u32 regeac, regeb4, regebc, regec4, regecc;
1794 u8 result = 0;
1795
1796 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n"));
1797 /* One shot, path B LOK & IQK */
1798 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
1799 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002);
1800 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000);
1801 /* delay x ms */
1802 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1803 ("Delay %d ms for One shot, path B LOK & IQK.\n",
1804 IQK_DELAY_TIME));
1805 mdelay(IQK_DELAY_TIME);
1806 /* Check failed */
1807 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1808 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1809 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1810 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4));
1811 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1812 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc));
1813 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1814 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4));
1815 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1816 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc));
1817 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1818 (((regebc & 0x03FF0000) >> 16) != 0x42))
1819 result |= 0x01;
1820 else
1821 return result;
1822 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1823 (((regecc & 0x03FF0000) >> 16) != 0x36))
1824 result |= 0x02;
1825 else
1826 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n"));
1827 return result;
1828}
1829
1830/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1831static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1832{
1833 struct rtl_priv *rtlpriv = rtl_priv(hw);
1834 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1835 u32 regeac, regeb4, regebc, regec4, regecc;
1836 u8 result = 0;
1837 u8 i;
1838 u8 retrycount = 2;
1839
1840 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n"));
1841 /* path-A IQK setting */
1842 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1843 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1844 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1845 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000);
1846 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000);
1847
1848 /* path-B IQK setting */
1849 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1850 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1851 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307);
1852 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960);
1853
1854 /* LO calibration setting */
1855 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1856 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1857
1858 /* path-B PA on */
1859 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700);
1860 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30);
1861
1862 for (i = 0; i < retrycount; i++) {
1863 /* One shot, path B LOK & IQK */
1864 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1865 ("One shot, path A LOK & IQK!\n"));
1866 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000);
1867 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1868
1869 /* delay x ms */
1870 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1871 ("Delay %d ms for One shot, path B LOK & IQK.\n", 10));
1872 mdelay(IQK_DELAY_TIME * 10);
1873
1874 /* Check failed */
1875 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1876 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1877 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1878 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4));
1879 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1880 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc));
1881 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1882 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4));
1883 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1884 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc));
1885 if (!(regeac & BIT(31)) &&
1886 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1887 result |= 0x01;
1888 else
1889 continue;
1890 if (!(regeac & BIT(30)) &&
1891 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1892 result |= 0x02;
1893 break;
1894 } else {
1895 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1896 ("Path B Rx IQK fail!!\n"));
1897 }
1898 }
1899
1900 /* path B PA off */
1901 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1902 rtlphy->iqk_bb_backup[0]);
1903 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD,
1904 rtlphy->iqk_bb_backup[2]);
1905 return result;
1906}
1907
1908static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1909 u32 *adda_reg, u32 *adda_backup,
1910 u32 regnum)
1911{
1912 struct rtl_priv *rtlpriv = rtl_priv(hw);
1913 u32 i;
1914
1915 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
1916 for (i = 0; i < regnum; i++)
1917 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD);
1918}
1919
1920static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1921 u32 *macreg, u32 *macbackup)
1922{
1923 struct rtl_priv *rtlpriv = rtl_priv(hw);
1924 u32 i;
1925
1926 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save MAC parameters.\n"));
1927 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1928 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1929 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1930}
1931
1932static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1933 u32 *adda_reg, u32 *adda_backup,
1934 u32 regnum)
1935{
1936 struct rtl_priv *rtlpriv = rtl_priv(hw);
1937 u32 i;
1938
1939 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1940 ("Reload ADDA power saving parameters !\n"));
1941 for (i = 0; i < regnum; i++)
1942 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]);
1943}
1944
1945static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1946 u32 *macreg, u32 *macbackup)
1947{
1948 struct rtl_priv *rtlpriv = rtl_priv(hw);
1949 u32 i;
1950
1951 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Reload MAC parameters !\n"));
1952 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1953 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1954 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1955}
1956
1957static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1958 u32 *adda_reg, bool patha_on, bool is2t)
1959{
1960 struct rtl_priv *rtlpriv = rtl_priv(hw);
1961 u32 pathon;
1962 u32 i;
1963
1964 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ADDA ON.\n"));
1965 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1966 if (patha_on)
1967 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1968 0x04db25a4 : 0x0b1b25a4;
1969 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1970 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon);
1971}
1972
1973static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1974 u32 *macreg, u32 *macbackup)
1975{
1976 struct rtl_priv *rtlpriv = rtl_priv(hw);
1977 u32 i;
1978
1979 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("MAC settings for Calibration.\n"));
1980 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1981
1982 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1983 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1984 (~BIT(3))));
1985 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1986}
1987
1988static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1989{
1990 struct rtl_priv *rtlpriv = rtl_priv(hw);
1991 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A standby mode!\n"));
1992
1993 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0);
1994 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000);
1995 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
1996}
1997
1998static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1999{
2000 struct rtl_priv *rtlpriv = rtl_priv(hw);
2001 u32 mode;
2002
2003 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2004 ("BB Switch to %s mode!\n", (pi_mode ? "PI" : "SI")));
2005 mode = pi_mode ? 0x01000100 : 0x01000000;
2006 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode);
2007 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode);
2008}
2009
2010static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2011 u8 t, bool is2t)
2012{
2013 struct rtl_priv *rtlpriv = rtl_priv(hw);
2014 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2015 u32 i;
2016 u8 patha_ok, pathb_ok;
2017 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2018 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2019 0xe78, 0xe7c, 0xe80, 0xe84,
2020 0xe88, 0xe8c, 0xed0, 0xed4,
2021 0xed8, 0xedc, 0xee0, 0xeec
2022 };
2023 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2024 0x522, 0x550, 0x551, 0x040
2025 };
2026 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2027 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2028 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2029 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2030 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2031 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2032 };
2033 const u32 retrycount = 2;
2034 u32 bbvalue;
2035
2036 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 2.4G :Start!!!\n"));
2037 if (t == 0) {
2038 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2039 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue));
2040 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n",
2041 (is2t ? "2T2R" : "1T1R")));
2042
2043 /* Save ADDA parameters, turn Path A ADDA on */
2044 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2045 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2046 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2047 rtlphy->iqk_mac_backup);
2048 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2049 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
2050 }
2051 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2052 if (t == 0)
2053 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2054 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2055
2056 /* Switch BB to PI mode to do IQ Calibration. */
2057 if (!rtlphy->rfpi_enable)
2058 _rtl92d_phy_pimode_switch(hw, true);
2059
2060 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2061 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2062 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2063 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000);
2064 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2065 if (is2t) {
2066 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD,
2067 0x00010000);
2068 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD,
2069 0x00010000);
2070 }
2071 /* MAC settings */
2072 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2073 rtlphy->iqk_mac_backup);
2074 /* Page B init */
2075 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2076 if (is2t)
2077 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2078 /* IQ calibration setting */
2079 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n"));
2080 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2081 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00);
2082 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2083 for (i = 0; i < retrycount; i++) {
2084 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
2085 if (patha_ok == 0x03) {
2086 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2087 ("Path A IQK Success!!\n"));
2088 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2089 0x3FF0000) >> 16;
2090 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2091 0x3FF0000) >> 16;
2092 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2093 0x3FF0000) >> 16;
2094 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2095 0x3FF0000) >> 16;
2096 break;
2097 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
2098 /* Tx IQK OK */
2099 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2100 ("Path A IQK Only Tx Success!!\n"));
2101
2102 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2103 0x3FF0000) >> 16;
2104 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2105 0x3FF0000) >> 16;
2106 }
2107 }
2108 if (0x00 == patha_ok)
2109 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK failed!!\n"));
2110 if (is2t) {
2111 _rtl92d_phy_patha_standby(hw);
2112 /* Turn Path B ADDA on */
2113 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2114 for (i = 0; i < retrycount; i++) {
2115 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
2116 if (pathb_ok == 0x03) {
2117 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2118 ("Path B IQK Success!!\n"));
2119 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2120 BMASKDWORD) & 0x3FF0000) >> 16;
2121 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2122 BMASKDWORD) & 0x3FF0000) >> 16;
2123 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
2124 BMASKDWORD) & 0x3FF0000) >> 16;
2125 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
2126 BMASKDWORD) & 0x3FF0000) >> 16;
2127 break;
2128 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
2129 /* Tx IQK OK */
2130 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2131 ("Path B Only Tx IQK Success!!\n"));
2132 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2133 BMASKDWORD) & 0x3FF0000) >> 16;
2134 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2135 BMASKDWORD) & 0x3FF0000) >> 16;
2136 }
2137 }
2138 if (0x00 == pathb_ok)
2139 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2140 ("Path B IQK failed!!\n"));
2141 }
2142
2143 /* Back to BB mode, load original value */
2144 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2145 ("IQK:Back to BB mode, load original value!\n"));
2146
2147 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2148 if (t != 0) {
2149 /* Switch back BB to SI mode after finish IQ Calibration. */
2150 if (!rtlphy->rfpi_enable)
2151 _rtl92d_phy_pimode_switch(hw, false);
2152 /* Reload ADDA power saving parameters */
2153 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2154 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2155 /* Reload MAC parameters */
2156 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2157 rtlphy->iqk_mac_backup);
2158 if (is2t)
2159 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2160 rtlphy->iqk_bb_backup,
2161 IQK_BB_REG_NUM);
2162 else
2163 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2164 rtlphy->iqk_bb_backup,
2165 IQK_BB_REG_NUM - 1);
2166 /* load 0xe30 IQC default value */
2167 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00);
2168 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00);
2169 }
2170 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n"));
2171}
2172
2173static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2174 long result[][8], u8 t)
2175{
2176 struct rtl_priv *rtlpriv = rtl_priv(hw);
2177 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2178 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2179 u8 patha_ok, pathb_ok;
2180 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2181 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2182 0xe78, 0xe7c, 0xe80, 0xe84,
2183 0xe88, 0xe8c, 0xed0, 0xed4,
2184 0xed8, 0xedc, 0xee0, 0xeec
2185 };
2186 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2187 0x522, 0x550, 0x551, 0x040
2188 };
2189 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2190 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2191 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2192 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2193 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2194 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2195 };
2196 u32 bbvalue;
2197 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2198
2199 /* Note: IQ calibration must be performed after loading
2200 * PHY_REG.txt , and radio_a, radio_b.txt */
2201
2202 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 5G NORMAL:Start!!!\n"));
2203 mdelay(IQK_DELAY_TIME * 20);
2204 if (t == 0) {
2205 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2206 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue));
2207 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n",
2208 (is2t ? "2T2R" : "1T1R")));
2209 /* Save ADDA parameters, turn Path A ADDA on */
2210 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2211 rtlphy->adda_backup,
2212 IQK_ADDA_REG_NUM);
2213 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2214 rtlphy->iqk_mac_backup);
2215 if (is2t)
2216 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2217 rtlphy->iqk_bb_backup,
2218 IQK_BB_REG_NUM);
2219 else
2220 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2221 rtlphy->iqk_bb_backup,
2222 IQK_BB_REG_NUM - 1);
2223 }
2224 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2225 /* MAC settings */
2226 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2227 rtlphy->iqk_mac_backup);
2228 if (t == 0)
2229 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2230 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2231 /* Switch BB to PI mode to do IQ Calibration. */
2232 if (!rtlphy->rfpi_enable)
2233 _rtl92d_phy_pimode_switch(hw, true);
2234 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2235 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2236 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2237 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000);
2238 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2239
2240 /* Page B init */
2241 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2242 if (is2t)
2243 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2244 /* IQ calibration setting */
2245 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n"));
2246 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2247 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00);
2248 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2249 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2250 if (patha_ok == 0x03) {
2251 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Success!!\n"));
2252 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2253 0x3FF0000) >> 16;
2254 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2255 0x3FF0000) >> 16;
2256 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2257 0x3FF0000) >> 16;
2258 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2259 0x3FF0000) >> 16;
2260 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2261 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2262 ("Path A IQK Only Tx Success!!\n"));
2263
2264 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2265 0x3FF0000) >> 16;
2266 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2267 0x3FF0000) >> 16;
2268 } else {
2269 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Fail!!\n"));
2270 }
2271 if (is2t) {
2272 /* _rtl92d_phy_patha_standby(hw); */
2273 /* Turn Path B ADDA on */
2274 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2275 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2276 if (pathb_ok == 0x03) {
2277 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2278 ("Path B IQK Success!!\n"));
2279 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2280 0x3FF0000) >> 16;
2281 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2282 0x3FF0000) >> 16;
2283 result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) &
2284 0x3FF0000) >> 16;
2285 result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) &
2286 0x3FF0000) >> 16;
2287 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2288 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2289 ("Path B Only Tx IQK Success!!\n"));
2290 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2291 0x3FF0000) >> 16;
2292 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2293 0x3FF0000) >> 16;
2294 } else {
2295 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2296 ("Path B IQK failed!!\n"));
2297 }
2298 }
2299
2300 /* Back to BB mode, load original value */
2301 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2302 ("IQK:Back to BB mode, load original value!\n"));
2303 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2304 if (t != 0) {
2305 if (is2t)
2306 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2307 rtlphy->iqk_bb_backup,
2308 IQK_BB_REG_NUM);
2309 else
2310 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2311 rtlphy->iqk_bb_backup,
2312 IQK_BB_REG_NUM - 1);
2313 /* Reload MAC parameters */
2314 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2315 rtlphy->iqk_mac_backup);
2316 /* Switch back BB to SI mode after finish IQ Calibration. */
2317 if (!rtlphy->rfpi_enable)
2318 _rtl92d_phy_pimode_switch(hw, false);
2319 /* Reload ADDA power saving parameters */
2320 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2321 rtlphy->adda_backup,
2322 IQK_ADDA_REG_NUM);
2323 }
2324 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n"));
2325}
2326
2327static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2328 long result[][8], u8 c1, u8 c2)
2329{
2330 struct rtl_priv *rtlpriv = rtl_priv(hw);
2331 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2332 u32 i, j, diff, sim_bitmap, bound;
2333 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
2334 bool bresult = true;
2335 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2336
2337 if (is2t)
2338 bound = 8;
2339 else
2340 bound = 4;
2341 sim_bitmap = 0;
2342 for (i = 0; i < bound; i++) {
2343 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2344 result[c2][i]) : (result[c2][i] - result[c1][i]);
2345 if (diff > MAX_TOLERANCE_92D) {
2346 if ((i == 2 || i == 6) && !sim_bitmap) {
2347 if (result[c1][i] + result[c1][i + 1] == 0)
2348 final_candidate[(i / 4)] = c2;
2349 else if (result[c2][i] + result[c2][i + 1] == 0)
2350 final_candidate[(i / 4)] = c1;
2351 else
2352 sim_bitmap = sim_bitmap | (1 << i);
2353 } else {
2354 sim_bitmap = sim_bitmap | (1 << i);
2355 }
2356 }
2357 }
2358 if (sim_bitmap == 0) {
2359 for (i = 0; i < (bound / 4); i++) {
2360 if (final_candidate[i] != 0xFF) {
2361 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2362 result[3][j] =
2363 result[final_candidate[i]][j];
2364 bresult = false;
2365 }
2366 }
2367 return bresult;
2368 }
2369 if (!(sim_bitmap & 0x0F)) { /* path A OK */
2370 for (i = 0; i < 4; i++)
2371 result[3][i] = result[c1][i];
2372 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2373 for (i = 0; i < 2; i++)
2374 result[3][i] = result[c1][i];
2375 }
2376 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2377 for (i = 4; i < 8; i++)
2378 result[3][i] = result[c1][i];
2379 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2380 for (i = 4; i < 6; i++)
2381 result[3][i] = result[c1][i];
2382 }
2383 return false;
2384}
2385
2386static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2387 bool iqk_ok, long result[][8],
2388 u8 final_candidate, bool txonly)
2389{
2390 struct rtl_priv *rtlpriv = rtl_priv(hw);
2391 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2392 u32 oldval_0, val_x, tx0_a, reg;
2393 long val_y, tx0_c;
2394 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2395 rtlhal->macphymode == DUALMAC_DUALPHY;
2396
2397 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2398 ("Path A IQ Calibration %s !\n",
2399 (iqk_ok) ? "Success" : "Failed"));
2400 if (final_candidate == 0xFF) {
2401 return;
2402 } else if (iqk_ok) {
2403 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2404 BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2405 val_x = result[final_candidate][0];
2406 if ((val_x & 0x00000200) != 0)
2407 val_x = val_x | 0xFFFFFC00;
2408 tx0_a = (val_x * oldval_0) >> 8;
2409 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx0_a = 0x%x,"
2410 " oldval_0 0x%x\n", val_x, tx0_a, oldval_0));
2411 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2412 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2413 ((val_x * oldval_0 >> 7) & 0x1));
2414 val_y = result[final_candidate][1];
2415 if ((val_y & 0x00000200) != 0)
2416 val_y = val_y | 0xFFFFFC00;
2417 /* path B IQK result + 3 */
2418 if (rtlhal->interfaceindex == 1 &&
2419 rtlhal->current_bandtype == BAND_ON_5G)
2420 val_y += 3;
2421 tx0_c = (val_y * oldval_0) >> 8;
2422 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx0_c = 0x%lx\n",
2423 val_y, tx0_c));
2424 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2425 ((tx0_c & 0x3C0) >> 6));
2426 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2427 (tx0_c & 0x3F));
2428 if (is2t)
2429 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2430 ((val_y * oldval_0 >> 7) & 0x1));
2431 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xC80 = 0x%x\n",
2432 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2433 BMASKDWORD)));
2434 if (txonly) {
2435 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("only Tx OK\n"));
2436 return;
2437 }
2438 reg = result[final_candidate][2];
2439 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2440 reg = result[final_candidate][3] & 0x3F;
2441 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2442 reg = (result[final_candidate][3] >> 6) & 0xF;
2443 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2444 }
2445}
2446
2447static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2448 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2449{
2450 struct rtl_priv *rtlpriv = rtl_priv(hw);
2451 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2452 u32 oldval_1, val_x, tx1_a, reg;
2453 long val_y, tx1_c;
2454
2455 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",
2456 (iqk_ok) ? "Success" : "Failed"));
2457 if (final_candidate == 0xFF) {
2458 return;
2459 } else if (iqk_ok) {
2460 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2461 BMASKDWORD) >> 22) & 0x3FF;
2462 val_x = result[final_candidate][4];
2463 if ((val_x & 0x00000200) != 0)
2464 val_x = val_x | 0xFFFFFC00;
2465 tx1_a = (val_x * oldval_1) >> 8;
2466 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx1_a = 0x%x\n",
2467 val_x, tx1_a));
2468 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2469 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2470 ((val_x * oldval_1 >> 7) & 0x1));
2471 val_y = result[final_candidate][5];
2472 if ((val_y & 0x00000200) != 0)
2473 val_y = val_y | 0xFFFFFC00;
2474 if (rtlhal->current_bandtype == BAND_ON_5G)
2475 val_y += 3;
2476 tx1_c = (val_y * oldval_1) >> 8;
2477 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx1_c = 0x%lx\n",
2478 val_y, tx1_c));
2479 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2480 ((tx1_c & 0x3C0) >> 6));
2481 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2482 (tx1_c & 0x3F));
2483 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2484 ((val_y * oldval_1 >> 7) & 0x1));
2485 if (txonly)
2486 return;
2487 reg = result[final_candidate][6];
2488 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2489 reg = result[final_candidate][7] & 0x3F;
2490 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2491 reg = (result[final_candidate][7] >> 6) & 0xF;
2492 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2493 }
2494}
2495
2496void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2497{
2498 struct rtl_priv *rtlpriv = rtl_priv(hw);
2499 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2500 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2501 long result[4][8];
2502 u8 i, final_candidate, indexforchannel;
2503 bool patha_ok, pathb_ok;
2504 long rege94, rege9c, regea4, regeac, regeb4;
2505 long regebc, regec4, regecc, regtmp = 0;
2506 bool is12simular, is13simular, is23simular;
2507 unsigned long flag = 0;
2508
2509 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2510 ("IQK:Start!!!channel %d\n", rtlphy->current_channel));
2511 for (i = 0; i < 8; i++) {
2512 result[0][i] = 0;
2513 result[1][i] = 0;
2514 result[2][i] = 0;
2515 result[3][i] = 0;
2516 }
2517 final_candidate = 0xff;
2518 patha_ok = false;
2519 pathb_ok = false;
2520 is12simular = false;
2521 is23simular = false;
2522 is13simular = false;
2523 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2524 ("IQK !!!currentband %d\n", rtlhal->current_bandtype));
2525 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2526 for (i = 0; i < 3; i++) {
2527 if (rtlhal->current_bandtype == BAND_ON_5G) {
2528 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2529 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2530 if (IS_92D_SINGLEPHY(rtlhal->version))
2531 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2532 else
2533 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2534 }
2535 if (i == 1) {
2536 is12simular = _rtl92d_phy_simularity_compare(hw, result,
2537 0, 1);
2538 if (is12simular) {
2539 final_candidate = 0;
2540 break;
2541 }
2542 }
2543 if (i == 2) {
2544 is13simular = _rtl92d_phy_simularity_compare(hw, result,
2545 0, 2);
2546 if (is13simular) {
2547 final_candidate = 0;
2548 break;
2549 }
2550 is23simular = _rtl92d_phy_simularity_compare(hw, result,
2551 1, 2);
2552 if (is23simular) {
2553 final_candidate = 1;
2554 } else {
2555 for (i = 0; i < 8; i++)
2556 regtmp += result[3][i];
2557
2558 if (regtmp != 0)
2559 final_candidate = 3;
2560 else
2561 final_candidate = 0xFF;
2562 }
2563 }
2564 }
2565 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2566 for (i = 0; i < 4; i++) {
2567 rege94 = result[i][0];
2568 rege9c = result[i][1];
2569 regea4 = result[i][2];
2570 regeac = result[i][3];
2571 regeb4 = result[i][4];
2572 regebc = result[i][5];
2573 regec4 = result[i][6];
2574 regecc = result[i][7];
2575 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2576 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx "
2577 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2578 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2579 regecc));
2580 }
2581 if (final_candidate != 0xff) {
2582 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2583 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2584 regea4 = result[final_candidate][2];
2585 regeac = result[final_candidate][3];
2586 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2587 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2588 regec4 = result[final_candidate][6];
2589 regecc = result[final_candidate][7];
2590 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2591 ("IQK: final_candidate is %x\n", final_candidate));
2592 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2593 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx "
2594 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2595 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2596 regecc));
2597 patha_ok = pathb_ok = true;
2598 } else {
2599 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2600 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */
2601 }
2602 if ((rege94 != 0) /*&&(regea4 != 0) */)
2603 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2604 final_candidate, (regea4 == 0));
2605 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2606 if ((regeb4 != 0) /*&&(regec4 != 0) */)
2607 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2608 final_candidate, (regec4 == 0));
2609 }
2610 if (final_candidate != 0xFF) {
2611 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2612 rtlphy->current_channel);
2613
2614 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2615 rtlphy->iqk_matrix_regsetting[indexforchannel].
2616 value[0][i] = result[final_candidate][i];
2617 rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done =
2618 true;
2619
2620 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2621 ("\nIQK OK indexforchannel %d.\n", indexforchannel));
2622 }
2623}
2624
2625void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2626{
2627 struct rtl_priv *rtlpriv = rtl_priv(hw);
2628 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2629 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2630 u8 indexforchannel;
2631
2632 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("channel %d\n", channel));
2633 /*------Do IQK for normal chip and test chip 5G band------- */
2634 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2635 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
2636 ("indexforchannel %d done %d\n", indexforchannel,
2637 rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done));
2638 if (0 && !rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done &&
2639 rtlphy->need_iqk) {
2640 /* Re Do IQK. */
2641 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2642 ("Do IQK Matrix reg for channel:%d....\n", channel));
2643 rtl92d_phy_iq_calibrate(hw);
2644 } else {
2645 /* Just load the value. */
2646 /* 2G band just load once. */
2647 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2648 indexforchannel == 0) || indexforchannel > 0) {
2649 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2650 ("Just Read IQK Matrix reg for channel:%d"
2651 "....\n", channel));
2652 if ((rtlphy->iqk_matrix_regsetting[indexforchannel].
2653 value[0] != NULL)
2654 /*&&(regea4 != 0) */)
2655 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2656 rtlphy->iqk_matrix_regsetting[
2657 indexforchannel].value, 0,
2658 (rtlphy->iqk_matrix_regsetting[
2659 indexforchannel].value[0][2] == 0));
2660 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2661 if ((rtlphy->iqk_matrix_regsetting[
2662 indexforchannel].value[0][4] != 0)
2663 /*&&(regec4 != 0) */)
2664 _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2665 true,
2666 rtlphy->iqk_matrix_regsetting[
2667 indexforchannel].value, 0,
2668 (rtlphy->iqk_matrix_regsetting[
2669 indexforchannel].value[0][6]
2670 == 0));
2671 }
2672 }
2673 }
2674 rtlphy->need_iqk = false;
2675 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
2676}
2677
2678static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2679{
2680 u32 ret;
2681
2682 if (val1 >= val2)
2683 ret = val1 - val2;
2684 else
2685 ret = val2 - val1;
2686 return ret;
2687}
2688
2689static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2690{
2691
2692 int i;
2693 u8 channel_5g[45] = {
2694 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2695 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2696 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
2697 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
2698 161, 163, 165
2699 };
2700
2701 for (i = 0; i < sizeof(channel_5g); i++)
2702 if (channel == channel_5g[i])
2703 return true;
2704 return false;
2705}
2706
2707static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2708 u32 *targetchnl, u32 * curvecount_val,
2709 bool is5g, u32 *curveindex)
2710{
2711 struct rtl_priv *rtlpriv = rtl_priv(hw);
2712 u32 smallest_abs_val = 0xffffffff, u4tmp;
2713 u8 i, j;
2714 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2715
2716 for (i = 0; i < chnl_num; i++) {
2717 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2718 continue;
2719 curveindex[i] = 0;
2720 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2721 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2722 curvecount_val[j]);
2723
2724 if (u4tmp < smallest_abs_val) {
2725 curveindex[i] = j;
2726 smallest_abs_val = u4tmp;
2727 }
2728 }
2729 smallest_abs_val = 0xffffffff;
2730 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("curveindex[%d] = %x\n", i,
2731 curveindex[i]));
2732 }
2733}
2734
2735static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2736 u8 channel)
2737{
2738 struct rtl_priv *rtlpriv = rtl_priv(hw);
2739 u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2740 BAND_ON_5G ? RF90_PATH_A :
2741 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2742 RF90_PATH_B : RF90_PATH_A;
2743 u32 u4tmp = 0, u4regvalue = 0;
2744 bool bneed_powerdown_radio = false;
2745
2746 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("path %d\n", erfpath));
2747 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("band type = %d\n",
2748 rtlpriv->rtlhal.current_bandtype));
2749 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("channel = %d\n", channel));
2750 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2751 u4tmp = curveindex_5g[channel-1];
2752 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2753 ("ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp));
2754 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2755 rtlpriv->rtlhal.interfaceindex == 1) {
2756 bneed_powerdown_radio =
2757 rtl92d_phy_enable_anotherphy(hw, false);
2758 rtlpriv->rtlhal.during_mac1init_radioa = true;
2759 /* asume no this case */
2760 if (bneed_powerdown_radio)
2761 _rtl92d_phy_enable_rf_env(hw, erfpath,
2762 &u4regvalue);
2763 }
2764 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2765 if (bneed_powerdown_radio)
2766 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2767 if (rtlpriv->rtlhal.during_mac1init_radioa)
2768 rtl92d_phy_powerdown_anotherphy(hw, false);
2769 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2770 u4tmp = curveindex_2g[channel-1];
2771 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2772 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp));
2773 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2774 rtlpriv->rtlhal.interfaceindex == 0) {
2775 bneed_powerdown_radio =
2776 rtl92d_phy_enable_anotherphy(hw, true);
2777 rtlpriv->rtlhal.during_mac0init_radiob = true;
2778 if (bneed_powerdown_radio)
2779 _rtl92d_phy_enable_rf_env(hw, erfpath,
2780 &u4regvalue);
2781 }
2782 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2783 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2784 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n",
2785 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)));
2786 if (bneed_powerdown_radio)
2787 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2788 if (rtlpriv->rtlhal.during_mac0init_radiob)
2789 rtl92d_phy_powerdown_anotherphy(hw, true);
2790 }
2791 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
2792}
2793
2794static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2795{
2796 struct rtl_priv *rtlpriv = rtl_priv(hw);
2797 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2798 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2799 u8 tmpreg, index, rf_mode[2];
2800 u8 path = is2t ? 2 : 1;
2801 u8 i;
2802 u32 u4tmp, offset;
2803 u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2804 u16 timeout = 800, timecount = 0;
2805
2806 /* Check continuous TX and Packet TX */
2807 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2808 /* if Deal with contisuous TX case, disable all continuous TX */
2809 /* if Deal with Packet TX case, block all queues */
2810 if ((tmpreg & 0x70) != 0)
2811 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2812 else
2813 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2814 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2815 for (index = 0; index < path; index++) {
2816 /* 1. Read original RF mode */
2817 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2818 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2819 /* 2. Set RF mode = standby mode */
2820 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2821 BRFREGOFFSETMASK, 0x010000);
2822 if (rtlpci->init_ready) {
2823 /* switch CV-curve control by LC-calibration */
2824 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2825 BIT(17), 0x0);
2826 /* 4. Set LC calibration begin */
2827 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2828 0x08000, 0x01);
2829 }
2830 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2831 BRFREGOFFSETMASK);
2832 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2833 mdelay(50);
2834 timecount += 50;
2835 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2836 RF_SYN_G6, BRFREGOFFSETMASK);
2837 }
2838 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2839 ("PHY_LCK finish delay for %d ms=2\n", timecount));
2840 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK);
2841 if (index == 0 && rtlhal->interfaceindex == 0) {
2842 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2843 ("path-A / 5G LCK\n"));
2844 } else {
2845 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2846 ("path-B / 2.4G LCK\n"));
2847 }
2848 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2849 /* Set LC calibration off */
2850 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2851 0x08000, 0x0);
2852 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("set RF 0x18[15] = 0\n"));
2853 /* save Curve-counting number */
2854 for (i = 0; i < CV_CURVE_CNT; i++) {
2855 u32 readval = 0, readval2 = 0;
2856 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2857 0x7f, i);
2858
2859 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2860 BRFREGOFFSETMASK, 0x0);
2861 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2862 0x4F, BRFREGOFFSETMASK);
2863 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2864 /* reg 0x4f [4:0] */
2865 /* reg 0x50 [19:10] */
2866 readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2867 0x50, 0xffc00);
2868 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2869 readval2);
2870 }
2871 if (index == 0 && rtlhal->interfaceindex == 0)
2872 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2873 curvecount_val,
2874 true, curveindex_5g);
2875 else
2876 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2877 curvecount_val,
2878 false, curveindex_2g);
2879 /* switch CV-curve control mode */
2880 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2881 BIT(17), 0x1);
2882 }
2883
2884 /* Restore original situation */
2885 for (index = 0; index < path; index++) {
2886 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2887 rtl_write_byte(rtlpriv, offset, 0x50);
2888 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2889 }
2890 if ((tmpreg & 0x70) != 0)
2891 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2892 else /*Deal with Packet TX case */
2893 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2894 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2895 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2896}
2897
2898static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2899{
2900 struct rtl_priv *rtlpriv = rtl_priv(hw);
2901
2902 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("cosa PHY_LCK ver=2\n"));
2903 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2904}
2905
2906void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2907{
2908 struct rtl_priv *rtlpriv = rtl_priv(hw);
2909 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2910 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2911 u32 timeout = 2000, timecount = 0;
2912
2913 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2914 udelay(50);
2915 timecount += 50;
2916 }
2917
2918 rtlphy->lck_inprogress = true;
2919 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2920 ("LCK:Start!!! currentband %x delay %d ms\n",
2921 rtlhal->current_bandtype, timecount));
2922 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2923 _rtl92d_phy_lc_calibrate(hw, true);
2924 } else {
2925 /* For 1T1R */
2926 _rtl92d_phy_lc_calibrate(hw, false);
2927 }
2928 rtlphy->lck_inprogress = false;
2929 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LCK:Finish!!!\n"));
2930}
2931
2932void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2933{
2934 return;
2935}
2936
2937static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2938 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2939 u32 para1, u32 para2, u32 msdelay)
2940{
2941 struct swchnlcmd *pcmd;
2942
2943 if (cmdtable == NULL) {
2944 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
2945 return false;
2946 }
2947 if (cmdtableidx >= cmdtablesz)
2948 return false;
2949
2950 pcmd = cmdtable + cmdtableidx;
2951 pcmd->cmdid = cmdid;
2952 pcmd->para1 = para1;
2953 pcmd->para2 = para2;
2954 pcmd->msdelay = msdelay;
2955 return true;
2956}
2957
2958void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2959{
2960 struct rtl_priv *rtlpriv = rtl_priv(hw);
2961 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2962 u8 i;
2963
2964 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2965 ("settings regs %d default regs %d\n",
2966 (int)(sizeof(rtlphy->iqk_matrix_regsetting) /
2967 sizeof(struct iqk_matrix_regs)),
2968 IQK_MATRIX_REG_NUM));
2969 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2970 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2971 rtlphy->iqk_matrix_regsetting[i].value[0][0] = 0x100;
2972 rtlphy->iqk_matrix_regsetting[i].value[0][2] = 0x100;
2973 rtlphy->iqk_matrix_regsetting[i].value[0][4] = 0x100;
2974 rtlphy->iqk_matrix_regsetting[i].value[0][6] = 0x100;
2975 rtlphy->iqk_matrix_regsetting[i].value[0][1] = 0x0;
2976 rtlphy->iqk_matrix_regsetting[i].value[0][3] = 0x0;
2977 rtlphy->iqk_matrix_regsetting[i].value[0][5] = 0x0;
2978 rtlphy->iqk_matrix_regsetting[i].value[0][7] = 0x0;
2979 rtlphy->iqk_matrix_regsetting[i].iqk_done = false;
2980 }
2981}
2982
2983static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2984 u8 channel, u8 *stage, u8 *step,
2985 u32 *delay)
2986{
2987 struct rtl_priv *rtlpriv = rtl_priv(hw);
2988 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2989 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2990 u32 precommoncmdcnt;
2991 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2992 u32 postcommoncmdcnt;
2993 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2994 u32 rfdependcmdcnt;
2995 struct swchnlcmd *currentcmd = NULL;
2996 u8 rfpath;
2997 u8 num_total_rfpath = rtlphy->num_total_rfpath;
2998
2999 precommoncmdcnt = 0;
3000 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
3001 MAX_PRECMD_CNT,
3002 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
3003 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
3004 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
3005 postcommoncmdcnt = 0;
3006 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
3007 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
3008 rfdependcmdcnt = 0;
3009 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
3010 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
3011 RF_CHNLBW, channel, 0);
3012 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
3013 MAX_RFDEPENDCMD_CNT, CMDID_END,
3014 0, 0, 0);
3015
3016 do {
3017 switch (*stage) {
3018 case 0:
3019 currentcmd = &precommoncmd[*step];
3020 break;
3021 case 1:
3022 currentcmd = &rfdependcmd[*step];
3023 break;
3024 case 2:
3025 currentcmd = &postcommoncmd[*step];
3026 break;
3027 }
3028 if (currentcmd->cmdid == CMDID_END) {
3029 if ((*stage) == 2) {
3030 return true;
3031 } else {
3032 (*stage)++;
3033 (*step) = 0;
3034 continue;
3035 }
3036 }
3037 switch (currentcmd->cmdid) {
3038 case CMDID_SET_TXPOWEROWER_LEVEL:
3039 rtl92d_phy_set_txpower_level(hw, channel);
3040 break;
3041 case CMDID_WRITEPORT_ULONG:
3042 rtl_write_dword(rtlpriv, currentcmd->para1,
3043 currentcmd->para2);
3044 break;
3045 case CMDID_WRITEPORT_USHORT:
3046 rtl_write_word(rtlpriv, currentcmd->para1,
3047 (u16)currentcmd->para2);
3048 break;
3049 case CMDID_WRITEPORT_UCHAR:
3050 rtl_write_byte(rtlpriv, currentcmd->para1,
3051 (u8)currentcmd->para2);
3052 break;
3053 case CMDID_RF_WRITEREG:
3054 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
3055 rtlphy->rfreg_chnlval[rfpath] =
3056 ((rtlphy->rfreg_chnlval[rfpath] &
3057 0xffffff00) | currentcmd->para2);
3058 if (rtlpriv->rtlhal.current_bandtype ==
3059 BAND_ON_5G) {
3060 if (currentcmd->para2 > 99)
3061 rtlphy->rfreg_chnlval[rfpath] =
3062 rtlphy->rfreg_chnlval
3063 [rfpath] | (BIT(18));
3064 else
3065 rtlphy->rfreg_chnlval[rfpath] =
3066 rtlphy->rfreg_chnlval
3067 [rfpath] & (~BIT(18));
3068 rtlphy->rfreg_chnlval[rfpath] |=
3069 (BIT(16) | BIT(8));
3070 } else {
3071 rtlphy->rfreg_chnlval[rfpath] &=
3072 ~(BIT(8) | BIT(16) | BIT(18));
3073 }
3074 rtl_set_rfreg(hw, (enum radio_path)rfpath,
3075 currentcmd->para1,
3076 BRFREGOFFSETMASK,
3077 rtlphy->rfreg_chnlval[rfpath]);
3078 _rtl92d_phy_reload_imr_setting(hw, channel,
3079 rfpath);
3080 }
3081 _rtl92d_phy_switch_rf_setting(hw, channel);
3082 /* do IQK when all parameters are ready */
3083 rtl92d_phy_reload_iqk_setting(hw, channel);
3084 break;
3085 default:
3086 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3087 ("switch case not process\n"));
3088 break;
3089 }
3090 break;
3091 } while (true);
3092 (*delay) = currentcmd->msdelay;
3093 (*step)++;
3094 return false;
3095}
3096
3097u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
3098{
3099 struct rtl_priv *rtlpriv = rtl_priv(hw);
3100 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3101 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3102 u32 delay;
3103 u32 timeout = 1000, timecount = 0;
3104 u8 channel = rtlphy->current_channel;
3105 u32 ret_value;
3106
3107 if (rtlphy->sw_chnl_inprogress)
3108 return 0;
3109 if (rtlphy->set_bwmode_inprogress)
3110 return 0;
3111
3112 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3113 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
3114 ("sw_chnl_inprogress false driver sleep or unload\n"));
3115 return 0;
3116 }
3117 while (rtlphy->lck_inprogress && timecount < timeout) {
3118 mdelay(50);
3119 timecount += 50;
3120 }
3121 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
3122 rtlhal->bandset == BAND_ON_BOTH) {
3123 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3124 BMASKDWORD);
3125 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
3126 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
3127 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
3128 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3129 }
3130 switch (rtlhal->current_bandtype) {
3131 case BAND_ON_5G:
3132 /* Get first channel error when change between
3133 * 5G and 2.4G band. */
3134 if (channel <= 14)
3135 return 0;
3136 RT_ASSERT((channel > 14), ("5G but channel<=14"));
3137 break;
3138 case BAND_ON_2_4G:
3139 /* Get first channel error when change between
3140 * 5G and 2.4G band. */
3141 if (channel > 14)
3142 return 0;
3143 RT_ASSERT((channel <= 14), ("2G but channel>14"));
3144 break;
3145 default:
3146 RT_ASSERT(false,
3147 ("Invalid WirelessMode(%#x)!!\n",
3148 rtlpriv->mac80211.mode));
3149 break;
3150 }
3151 rtlphy->sw_chnl_inprogress = true;
3152 if (channel == 0)
3153 channel = 1;
3154 rtlphy->sw_chnl_stage = 0;
3155 rtlphy->sw_chnl_step = 0;
3156 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
3157 ("switch to channel%d\n", rtlphy->current_channel));
3158
3159 do {
3160 if (!rtlphy->sw_chnl_inprogress)
3161 break;
3162 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
3163 rtlphy->current_channel,
3164 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
3165 if (delay > 0)
3166 mdelay(delay);
3167 else
3168 continue;
3169 } else {
3170 rtlphy->sw_chnl_inprogress = false;
3171 }
3172 break;
3173 } while (true);
3174 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
3175 rtlphy->sw_chnl_inprogress = false;
3176 return 1;
3177}
3178
3179static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
3180{
3181 struct rtl_priv *rtlpriv = rtl_priv(hw);
3182 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3183
3184 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3185 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
3186 rtlphy->current_io_type, rtlphy->set_io_inprogress));
3187 switch (rtlphy->current_io_type) {
3188 case IO_CMD_RESUME_DM_BY_SCAN:
3189 de_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
3190 rtl92d_dm_write_dig(hw);
3191 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
3192 break;
3193 case IO_CMD_PAUSE_DM_BY_SCAN:
3194 rtlphy->initgain_backup.xaagccore1 = de_digtable.cur_igvalue;
3195 de_digtable.cur_igvalue = 0x17;
3196 rtl92d_dm_write_dig(hw);
3197 break;
3198 default:
3199 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3200 ("switch case not process\n"));
3201 break;
3202 }
3203 rtlphy->set_io_inprogress = false;
3204 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3205 ("<---(%#x)\n", rtlphy->current_io_type));
3206}
3207
3208bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
3209{
3210 struct rtl_priv *rtlpriv = rtl_priv(hw);
3211 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3212 bool postprocessing = false;
3213
3214 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3215 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
3216 iotype, rtlphy->set_io_inprogress));
3217 do {
3218 switch (iotype) {
3219 case IO_CMD_RESUME_DM_BY_SCAN:
3220 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3221 ("[IO CMD] Resume DM after scan.\n"));
3222 postprocessing = true;
3223 break;
3224 case IO_CMD_PAUSE_DM_BY_SCAN:
3225 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3226 ("[IO CMD] Pause DM before scan.\n"));
3227 postprocessing = true;
3228 break;
3229 default:
3230 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3231 ("switch case not process\n"));
3232 break;
3233 }
3234 } while (false);
3235 if (postprocessing && !rtlphy->set_io_inprogress) {
3236 rtlphy->set_io_inprogress = true;
3237 rtlphy->current_io_type = iotype;
3238 } else {
3239 return false;
3240 }
3241 rtl92d_phy_set_io(hw);
3242 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
3243 return true;
3244}
3245
3246static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3247{
3248 struct rtl_priv *rtlpriv = rtl_priv(hw);
3249
3250 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */
3251 /* b. SPS_CTRL 0x11[7:0] = 0x2b */
3252 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3253 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3254 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
3255 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3256 /* RF_ON_EXCEP(d~g): */
3257 /* d. APSD_CTRL 0x600[7:0] = 0x00 */
3258 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3259 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */
3260 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/
3261 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3262 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3263 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */
3264 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3265}
3266
3267static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3268{
3269 struct rtl_priv *rtlpriv = rtl_priv(hw);
3270 u32 u4btmp;
3271 u8 delay = 5;
3272
3273 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
3274 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3275 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
3276 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3277 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
3278 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3279 /* d. APSD_CTRL 0x600[7:0] = 0x00
3280 * APSD_CTRL 0x600[7:0] = 0x00
3281 * RF path 0 offset 0x00 = 0x00
3282 * APSD_CTRL 0x600[7:0] = 0x40
3283 * */
3284 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3285 while (u4btmp != 0 && delay > 0) {
3286 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3287 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3288 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3289 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3290 delay--;
3291 }
3292 if (delay == 0) {
3293 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3294 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3295
3296 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3297 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3298 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3299 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3300 ("Fail !!! Switch RF timeout.\n"));
3301 return;
3302 }
3303 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3304 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3305 /* f. SPS_CTRL 0x11[7:0] = 0x22 */
3306 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3307 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3308 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */
3309}
3310
3311bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3312 enum rf_pwrstate rfpwr_state)
3313{
3314
3315 bool bresult = true;
3316 struct rtl_priv *rtlpriv = rtl_priv(hw);
3317 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3318 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3319 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3320 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3321 u8 i, queue_id;
3322 struct rtl8192_tx_ring *ring = NULL;
3323
3324 if (rfpwr_state == ppsc->rfpwr_state)
3325 return false;
3326 switch (rfpwr_state) {
3327 case ERFON:
3328 if ((ppsc->rfpwr_state == ERFOFF) &&
3329 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3330 bool rtstatus;
3331 u32 InitializeCount = 0;
3332 do {
3333 InitializeCount++;
3334 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3335 ("IPS Set eRf nic enable\n"));
3336 rtstatus = rtl_ps_enable_nic(hw);
3337 } while ((rtstatus != true) &&
3338 (InitializeCount < 10));
3339
3340 RT_CLEAR_PS_LEVEL(ppsc,
3341 RT_RF_OFF_LEVL_HALT_NIC);
3342 } else {
3343 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3344 ("awake, sleeped:%d ms state_"
3345 "inap:%x\n",
3346 jiffies_to_msecs(jiffies -
3347 ppsc->last_sleep_jiffies),
3348 rtlpriv->psc.state_inap));
3349 ppsc->last_awake_jiffies = jiffies;
3350 _rtl92d_phy_set_rfon(hw);
3351 }
3352
3353 if (mac->link_state == MAC80211_LINKED)
3354 rtlpriv->cfg->ops->led_control(hw,
3355 LED_CTL_LINK);
3356 else
3357 rtlpriv->cfg->ops->led_control(hw,
3358 LED_CTL_NO_LINK);
3359 break;
3360 case ERFOFF:
3361 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3362 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3363 ("IPS Set eRf nic disable\n"));
3364 rtl_ps_disable_nic(hw);
3365 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3366 } else {
3367 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3368 rtlpriv->cfg->ops->led_control(hw,
3369 LED_CTL_NO_LINK);
3370 else
3371 rtlpriv->cfg->ops->led_control(hw,
3372 LED_CTL_POWER_OFF);
3373 }
3374 break;
3375 case ERFSLEEP:
3376 if (ppsc->rfpwr_state == ERFOFF)
3377 break;
3378
3379 for (queue_id = 0, i = 0;
3380 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3381 ring = &pcipriv->dev.tx_ring[queue_id];
3382 if (skb_queue_len(&ring->queue) == 0 ||
3383 queue_id == BEACON_QUEUE) {
3384 queue_id++;
3385 continue;
3386 } else if (rtlpci->pdev->current_state != PCI_D0) {
3387 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3388 ("eRf Off/Sleep: %d times TcbBusyQueu"
3389 "e[%d] !=0 but lower power state!\n",
3390 (i + 1), queue_id));
3391 break;
3392 } else {
3393 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3394 ("eRf Off/Sleep: %d times TcbBusyQueu"
3395 "e[%d] =%d "
3396 "before doze!\n", (i + 1), queue_id,
3397 skb_queue_len(&ring->queue)));
3398 udelay(10);
3399 i++;
3400 }
3401
3402 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3403 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3404 ("\nERFOFF: %d times TcbBusyQueue[%d] "
3405 "= %d !\n",
3406 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3407 skb_queue_len(&ring->queue)));
3408 break;
3409 }
3410 }
3411 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3412 ("Set rfsleep awaked:%d ms\n",
3413 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)));
3414 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, ("sleep awaked:%d ms "
3415 "state_inap:%x\n", jiffies_to_msecs(jiffies -
3416 ppsc->last_awake_jiffies), rtlpriv->psc.state_inap));
3417 ppsc->last_sleep_jiffies = jiffies;
3418 _rtl92d_phy_set_rfsleep(hw);
3419 break;
3420 default:
3421 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3422 ("switch case not process\n"));
3423 bresult = false;
3424 break;
3425 }
3426 if (bresult)
3427 ppsc->rfpwr_state = rfpwr_state;
3428 return bresult;
3429}
3430
3431void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3432{
3433 struct rtl_priv *rtlpriv = rtl_priv(hw);
3434 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3435 u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3436
3437 switch (rtlhal->macphymode) {
3438 case DUALMAC_DUALPHY:
3439 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3440 ("MacPhyMode: DUALMAC_DUALPHY\n"));
3441 rtl_write_byte(rtlpriv, offset, 0xF3);
3442 break;
3443 case SINGLEMAC_SINGLEPHY:
3444 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3445 ("MacPhyMode: SINGLEMAC_SINGLEPHY\n"));
3446 rtl_write_byte(rtlpriv, offset, 0xF4);
3447 break;
3448 case DUALMAC_SINGLEPHY:
3449 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3450 ("MacPhyMode: DUALMAC_SINGLEPHY\n"));
3451 rtl_write_byte(rtlpriv, offset, 0xF1);
3452 break;
3453 }
3454}
3455
3456void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3457{
3458 struct rtl_priv *rtlpriv = rtl_priv(hw);
3459 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3460 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3461
3462 switch (rtlhal->macphymode) {
3463 case DUALMAC_SINGLEPHY:
3464 rtlphy->rf_type = RF_2T2R;
3465 rtlhal->version |= CHIP_92D_SINGLEPHY;
3466 rtlhal->bandset = BAND_ON_BOTH;
3467 rtlhal->current_bandtype = BAND_ON_2_4G;
3468 break;
3469
3470 case SINGLEMAC_SINGLEPHY:
3471 rtlphy->rf_type = RF_2T2R;
3472 rtlhal->version |= CHIP_92D_SINGLEPHY;
3473 rtlhal->bandset = BAND_ON_BOTH;
3474 rtlhal->current_bandtype = BAND_ON_2_4G;
3475 break;
3476
3477 case DUALMAC_DUALPHY:
3478 rtlphy->rf_type = RF_1T1R;
3479 rtlhal->version &= (~CHIP_92D_SINGLEPHY);
3480 /* Now we let MAC0 run on 5G band. */
3481 if (rtlhal->interfaceindex == 0) {
3482 rtlhal->bandset = BAND_ON_5G;
3483 rtlhal->current_bandtype = BAND_ON_5G;
3484 } else {
3485 rtlhal->bandset = BAND_ON_2_4G;
3486 rtlhal->current_bandtype = BAND_ON_2_4G;
3487 }
3488 break;
3489 default:
3490 break;
3491 }
3492}
3493
3494u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3495{
3496 u8 group;
3497 u8 channel_info[59] = {
3498 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3499 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3500 58, 60, 62, 64, 100, 102, 104, 106, 108,
3501 110, 112, 114, 116, 118, 120, 122, 124,
3502 126, 128, 130, 132, 134, 136, 138, 140,
3503 149, 151, 153, 155, 157, 159, 161, 163,
3504 165
3505 };
3506
3507 if (channel_info[chnl] <= 3)
3508 group = 0;
3509 else if (channel_info[chnl] <= 9)
3510 group = 1;
3511 else if (channel_info[chnl] <= 14)
3512 group = 2;
3513 else if (channel_info[chnl] <= 44)
3514 group = 3;
3515 else if (channel_info[chnl] <= 54)
3516 group = 4;
3517 else if (channel_info[chnl] <= 64)
3518 group = 5;
3519 else if (channel_info[chnl] <= 112)
3520 group = 6;
3521 else if (channel_info[chnl] <= 126)
3522 group = 7;
3523 else if (channel_info[chnl] <= 140)
3524 group = 8;
3525 else if (channel_info[chnl] <= 153)
3526 group = 9;
3527 else if (channel_info[chnl] <= 159)
3528 group = 10;
3529 else
3530 group = 11;
3531 return group;
3532}
3533
3534void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3535{
3536 struct rtl_priv *rtlpriv = rtl_priv(hw);
3537 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3538 unsigned long flags;
3539 u8 value8;
3540 u16 i;
3541 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3542
3543 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3544 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3545 value8 = rtl_read_byte(rtlpriv, mac_reg);
3546 value8 |= BIT(1);
3547 rtl_write_byte(rtlpriv, mac_reg, value8);
3548 } else {
3549 value8 = rtl_read_byte(rtlpriv, mac_reg);
3550 value8 &= (~BIT(1));
3551 rtl_write_byte(rtlpriv, mac_reg, value8);
3552 }
3553
3554 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3555 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3556 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3557 } else {
3558 spin_lock_irqsave(&globalmutex_power, flags);
3559 if (rtlhal->interfaceindex == 0) {
3560 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3561 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3562 } else {
3563 value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3564 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3565 }
3566 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3567 spin_unlock_irqrestore(&globalmutex_power, flags);
3568 for (i = 0; i < 200; i++) {
3569 if ((value8 & BIT(7)) == 0) {
3570 break;
3571 } else {
3572 udelay(500);
3573 spin_lock_irqsave(&globalmutex_power, flags);
3574 value8 = rtl_read_byte(rtlpriv,
3575 REG_POWER_OFF_IN_PROCESS);
3576 spin_unlock_irqrestore(&globalmutex_power,
3577 flags);
3578 }
3579 }
3580 if (i == 200)
3581 RT_ASSERT(false, ("Another mac power off over time\n"));
3582 }
3583}
3584
3585void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3586{
3587 struct rtl_priv *rtlpriv = rtl_priv(hw);
3588
3589 switch (rtlpriv->rtlhal.macphymode) {
3590 case DUALMAC_DUALPHY:
3591 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3592 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3593 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3594 break;
3595 case DUALMAC_SINGLEPHY:
3596 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3597 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3598 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3599 break;
3600 case SINGLEMAC_SINGLEPHY:
3601 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3602 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3603 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3604 break;
3605 default:
3606 break;
3607 }
3608}
3609
3610void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3611{
3612 struct rtl_priv *rtlpriv = rtl_priv(hw);
3613 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3614 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3615 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3616 u8 rfpath, i;
3617
3618 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==>\n"));
3619 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3620 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3621 /* r_select_5G for path_A/B,0x878 */
3622 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3623 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3624 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3625 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3626 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3627 }
3628 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3629 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3630 /* fc_area 0xd2c */
3631 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3632 /* 5G LAN ON */
3633 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3634 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3635 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3636 0x40000100);
3637 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3638 0x40000100);
3639 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3640 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3641 BIT(10) | BIT(6) | BIT(5),
3642 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3643 (rtlefuse->eeprom_c9 & BIT(1)) |
3644 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3645 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3646 BIT(10) | BIT(6) | BIT(5),
3647 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3648 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3649 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3650 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3651 } else {
3652 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3653 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3654 BIT(6) | BIT(5),
3655 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3656 (rtlefuse->eeprom_c9 & BIT(1)) |
3657 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3658 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3659 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3660 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3661 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3662 BIT(10) | BIT(6) | BIT(5),
3663 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3664 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3665 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3666 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3667 BIT(10) | BIT(6) | BIT(5),
3668 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3669 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3670 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3671 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3672 BIT(31) | BIT(15), 0);
3673 }
3674 /* 1.5V_LDO */
3675 } else {
3676 /* r_select_5G for path_A/B */
3677 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3678 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3679 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3680 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3681 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3682 }
3683 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3684 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3685 /* fc_area */
3686 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3687 /* 5G LAN ON */
3688 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3689 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3690 if (rtlefuse->internal_pa_5g[0])
3691 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3692 0x2d4000b5);
3693 else
3694 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3695 0x20000080);
3696 if (rtlefuse->internal_pa_5g[1])
3697 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3698 0x2d4000b5);
3699 else
3700 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3701 0x20000080);
3702 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3703 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3704 BIT(10) | BIT(6) | BIT(5),
3705 (rtlefuse->eeprom_cc & BIT(5)));
3706 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3707 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3708 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3709 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3710 } else {
3711 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3712 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3713 BIT(6) | BIT(5),
3714 (rtlefuse->eeprom_cc & BIT(5)) |
3715 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3716 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3717 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3718 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3719 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3720 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3721 BIT(31) | BIT(15),
3722 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3723 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3724 }
3725 }
3726 /* update IQK related settings */
3727 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100);
3728 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100);
3729 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3730 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3731 BIT(26) | BIT(24), 0x00);
3732 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3733 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3734 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3735
3736 /* Update RF */
3737 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3738 rfpath++) {
3739 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3740 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3741 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3742 BIT(18), 0);
3743 /* RF0x0b[16:14] =3b'111 */
3744 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3745 0x1c000, 0x07);
3746 } else {
3747 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3748 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3749 BIT(16) | BIT(18),
3750 (BIT(16) | BIT(8)) >> 8);
3751 }
3752 }
3753 /* Update for all band. */
3754 /* DMDP */
3755 if (rtlphy->rf_type == RF_1T1R) {
3756 /* Use antenna 0,0xc04,0xd04 */
3757 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11);
3758 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3759
3760 /* enable ad/da clock1 for dual-phy reg0x888 */
3761 if (rtlhal->interfaceindex == 0) {
3762 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3763 BIT(13), 0x3);
3764 } else {
3765 rtl92d_phy_enable_anotherphy(hw, false);
3766 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3767 ("MAC1 use DBI to update 0x888"));
3768 /* 0x888 */
3769 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3770 rtl92de_read_dword_dbi(hw,
3771 RFPGA0_ADDALLOCKEN,
3772 BIT(3)) | BIT(12) | BIT(13),
3773 BIT(3));
3774 rtl92d_phy_powerdown_anotherphy(hw, false);
3775 }
3776 } else {
3777 /* Single PHY */
3778 /* Use antenna 0 & 1,0xc04,0xd04 */
3779 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33);
3780 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3781 /* disable ad/da clock1,0x888 */
3782 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3783 }
3784 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3785 rfpath++) {
3786 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3787 RF_CHNLBW, BRFREGOFFSETMASK);
3788 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3789 BRFREGOFFSETMASK);
3790 }
3791 for (i = 0; i < 2; i++)
3792 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("RF 0x18 = 0x%x\n",
3793 rtlphy->rfreg_chnlval[i]));
3794 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<==\n"));
3795
3796}
3797
3798bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3799{
3800 struct rtl_priv *rtlpriv = rtl_priv(hw);
3801 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3802 u8 u1btmp;
3803 unsigned long flags;
3804
3805 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3806 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3807 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3808 return true;
3809 }
3810 spin_lock_irqsave(&globalmutex_power, flags);
3811 if (rtlhal->interfaceindex == 0) {
3812 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3813 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3814 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3815 u1btmp &= MAC1_ON;
3816 } else {
3817 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3818 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3819 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3820 u1btmp &= MAC0_ON;
3821 }
3822 if (u1btmp) {
3823 spin_unlock_irqrestore(&globalmutex_power, flags);
3824 return false;
3825 }
3826 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3827 u1btmp |= BIT(7);
3828 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3829 spin_unlock_irqrestore(&globalmutex_power, flags);
3830 return true;
3831}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/phy.h b/drivers/net/wireless/rtlwifi/rtl8192de/phy.h
new file mode 100644
index 000000000000..a52c824b41e3
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/phy.h
@@ -0,0 +1,178 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_PHY_H__
31#define __RTL92D_PHY_H__
32
33#define MAX_PRECMD_CNT 16
34#define MAX_RFDEPENDCMD_CNT 16
35#define MAX_POSTCMD_CNT 16
36
37#define MAX_DOZE_WAITING_TIMES_9x 64
38
39#define RT_CANNOT_IO(hw) false
40#define HIGHPOWER_RADIOA_ARRAYLEN 22
41
42#define IQK_ADDA_REG_NUM 16
43#define MAX_TOLERANCE 5
44#define IQK_DELAY_TIME 1
45
46#define APK_BB_REG_NUM 5
47#define APK_AFE_REG_NUM 16
48#define APK_CURVE_REG_NUM 4
49#define PATH_NUM 2
50
51#define LOOP_LIMIT 5
52#define MAX_STALL_TIME 50
53#define ANTENNA_DIVERSITY_VALUE 0x80
54#define MAX_TXPWR_IDX_NMODE_92S 63
55#define RESET_CNT_LIMIT 3
56
57#define IQK_ADDA_REG_NUM 16
58#define IQK_BB_REG_NUM 10
59#define IQK_BB_REG_NUM_test 6
60#define IQK_MAC_REG_NUM 4
61#define RX_INDEX_MAPPING_NUM 15
62
63#define IQK_DELAY_TIME 1
64
65#define CT_OFFSET_MAC_ADDR 0X16
66
67#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
68#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
69#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
70#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
71#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
72
73#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
74#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
75
76#define CT_OFFSET_CHANNEL_PLAH 0x75
77#define CT_OFFSET_THERMAL_METER 0x78
78#define CT_OFFSET_RF_OPTION 0x79
79#define CT_OFFSET_VERSION 0x7E
80#define CT_OFFSET_CUSTOMER_ID 0x7F
81
82enum swchnlcmd_id {
83 CMDID_END,
84 CMDID_SET_TXPOWEROWER_LEVEL,
85 CMDID_BBREGWRITE10,
86 CMDID_WRITEPORT_ULONG,
87 CMDID_WRITEPORT_USHORT,
88 CMDID_WRITEPORT_UCHAR,
89 CMDID_RF_WRITEREG,
90};
91
92struct swchnlcmd {
93 enum swchnlcmd_id cmdid;
94 u32 para1;
95 u32 para2;
96 u32 msdelay;
97};
98
99enum baseband_config_type {
100 BASEBAND_CONFIG_PHY_REG = 0,
101 BASEBAND_CONFIG_AGC_TAB = 1,
102};
103
104enum rf_content {
105 radioa_txt = 0,
106 radiob_txt = 1,
107 radioc_txt = 2,
108 radiod_txt = 3
109};
110
111static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
112 unsigned long *flag)
113{
114 struct rtl_priv *rtlpriv = rtl_priv(hw);
115
116 if (rtlpriv->rtlhal.interfaceindex == 1)
117 spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
118}
119
120static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
121 unsigned long *flag)
122{
123 struct rtl_priv *rtlpriv = rtl_priv(hw);
124
125 if (rtlpriv->rtlhal.interfaceindex == 1)
126 spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
127 *flag);
128}
129
130extern u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
131 u32 regaddr, u32 bitmask);
132extern void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
133 u32 regaddr, u32 bitmask, u32 data);
134extern u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
135 enum radio_path rfpath, u32 regaddr,
136 u32 bitmask);
137extern void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
138 enum radio_path rfpath, u32 regaddr,
139 u32 bitmask, u32 data);
140extern bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
141extern bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
142extern bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
143extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
144 enum radio_path rfpath);
145extern void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
146extern void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
147extern void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw,
148 u8 operation);
149extern void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
150 enum nl80211_channel_type ch_type);
151extern u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
152bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
153 enum rf_content content,
154 enum radio_path rfpath);
155bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
156extern bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
157 enum rf_pwrstate rfpwr_state);
158
159void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
160void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
161u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
162void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
163void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
164bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
165void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
166void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
167void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
168void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
169void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
170void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
171 unsigned long *flag);
172void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
173 unsigned long *flag);
174u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
175void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
176void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
177
178#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/reg.h b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
new file mode 100644
index 000000000000..131acc306fcc
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/reg.h
@@ -0,0 +1,1313 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_REG_H__
31#define __RTL92D_REG_H__
32
33/* ----------------------------------------------------- */
34/* 0x0000h ~ 0x00FFh System Configuration */
35/* ----------------------------------------------------- */
36#define REG_SYS_ISO_CTRL 0x0000
37#define REG_SYS_FUNC_EN 0x0002
38#define REG_APS_FSMCO 0x0004
39#define REG_SYS_CLKR 0x0008
40#define REG_9346CR 0x000A
41#define REG_EE_VPD 0x000C
42#define REG_AFE_MISC 0x0010
43#define REG_SPS0_CTRL 0x0011
44#define REG_POWER_OFF_IN_PROCESS 0x0017
45#define REG_SPS_OCP_CFG 0x0018
46#define REG_RSV_CTRL 0x001C
47#define REG_RF_CTRL 0x001F
48#define REG_LDOA15_CTRL 0x0020
49#define REG_LDOV12D_CTRL 0x0021
50#define REG_LDOHCI12_CTRL 0x0022
51#define REG_LPLDO_CTRL 0x0023
52#define REG_AFE_XTAL_CTRL 0x0024
53#define REG_AFE_PLL_CTRL 0x0028
54/* for 92d, DMDP,SMSP,DMSP contrl */
55#define REG_MAC_PHY_CTRL 0x002c
56#define REG_EFUSE_CTRL 0x0030
57#define REG_EFUSE_TEST 0x0034
58#define REG_PWR_DATA 0x0038
59#define REG_CAL_TIMER 0x003C
60#define REG_ACLK_MON 0x003E
61#define REG_GPIO_MUXCFG 0x0040
62#define REG_GPIO_IO_SEL 0x0042
63#define REG_MAC_PINMUX_CFG 0x0043
64#define REG_GPIO_PIN_CTRL 0x0044
65#define REG_GPIO_INTM 0x0048
66#define REG_LEDCFG0 0x004C
67#define REG_LEDCFG1 0x004D
68#define REG_LEDCFG2 0x004E
69#define REG_LEDCFG3 0x004F
70#define REG_FSIMR 0x0050
71#define REG_FSISR 0x0054
72
73#define REG_MCUFWDL 0x0080
74
75#define REG_HMEBOX_EXT_0 0x0088
76#define REG_HMEBOX_EXT_1 0x008A
77#define REG_HMEBOX_EXT_2 0x008C
78#define REG_HMEBOX_EXT_3 0x008E
79
80#define REG_BIST_SCAN 0x00D0
81#define REG_BIST_RPT 0x00D4
82#define REG_BIST_ROM_RPT 0x00D8
83#define REG_USB_SIE_INTF 0x00E0
84#define REG_PCIE_MIO_INTF 0x00E4
85#define REG_PCIE_MIO_INTD 0x00E8
86#define REG_HPON_FSM 0x00EC
87#define REG_SYS_CFG 0x00F0
88#define REG_MAC_PHY_CTRL_NORMAL 0x00f8
89
90#define REG_MAC0 0x0081
91#define REG_MAC1 0x0053
92#define FW_MAC0_READY 0x18
93#define FW_MAC1_READY 0x1A
94#define MAC0_ON BIT(7)
95#define MAC1_ON BIT(0)
96#define MAC0_READY BIT(0)
97#define MAC1_READY BIT(0)
98
99/* ----------------------------------------------------- */
100/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
101/* ----------------------------------------------------- */
102#define REG_CR 0x0100
103#define REG_PBP 0x0104
104#define REG_TRXDMA_CTRL 0x010C
105#define REG_TRXFF_BNDY 0x0114
106#define REG_TRXFF_STATUS 0x0118
107#define REG_RXFF_PTR 0x011C
108#define REG_HIMR 0x0120
109#define REG_HISR 0x0124
110#define REG_HIMRE 0x0128
111#define REG_HISRE 0x012C
112#define REG_CPWM 0x012F
113#define REG_FWIMR 0x0130
114#define REG_FWISR 0x0134
115#define REG_PKTBUF_DBG_CTRL 0x0140
116#define REG_PKTBUF_DBG_DATA_L 0x0144
117#define REG_PKTBUF_DBG_DATA_H 0x0148
118
119#define REG_TC0_CTRL 0x0150
120#define REG_TC1_CTRL 0x0154
121#define REG_TC2_CTRL 0x0158
122#define REG_TC3_CTRL 0x015C
123#define REG_TC4_CTRL 0x0160
124#define REG_TCUNIT_BASE 0x0164
125#define REG_MBIST_START 0x0174
126#define REG_MBIST_DONE 0x0178
127#define REG_MBIST_FAIL 0x017C
128#define REG_C2HEVT_MSG_NORMAL 0x01A0
129#define REG_C2HEVT_MSG_TEST 0x01B8
130#define REG_C2HEVT_CLEAR 0x01BF
131#define REG_MCUTST_1 0x01c0
132#define REG_FMETHR 0x01C8
133#define REG_HMETFR 0x01CC
134#define REG_HMEBOX_0 0x01D0
135#define REG_HMEBOX_1 0x01D4
136#define REG_HMEBOX_2 0x01D8
137#define REG_HMEBOX_3 0x01DC
138
139#define REG_LLT_INIT 0x01E0
140#define REG_BB_ACCEESS_CTRL 0x01E8
141#define REG_BB_ACCESS_DATA 0x01EC
142
143
144/* ----------------------------------------------------- */
145/* 0x0200h ~ 0x027Fh TXDMA Configuration */
146/* ----------------------------------------------------- */
147#define REG_RQPN 0x0200
148#define REG_FIFOPAGE 0x0204
149#define REG_TDECTRL 0x0208
150#define REG_TXDMA_OFFSET_CHK 0x020C
151#define REG_TXDMA_STATUS 0x0210
152#define REG_RQPN_NPQ 0x0214
153
154/* ----------------------------------------------------- */
155/* 0x0280h ~ 0x02FFh RXDMA Configuration */
156/* ----------------------------------------------------- */
157#define REG_RXDMA_AGG_PG_TH 0x0280
158#define REG_RXPKT_NUM 0x0284
159#define REG_RXDMA_STATUS 0x0288
160
161/* ----------------------------------------------------- */
162/* 0x0300h ~ 0x03FFh PCIe */
163/* ----------------------------------------------------- */
164#define REG_PCIE_CTRL_REG 0x0300
165#define REG_INT_MIG 0x0304
166#define REG_BCNQ_DESA 0x0308
167#define REG_HQ_DESA 0x0310
168#define REG_MGQ_DESA 0x0318
169#define REG_VOQ_DESA 0x0320
170#define REG_VIQ_DESA 0x0328
171#define REG_BEQ_DESA 0x0330
172#define REG_BKQ_DESA 0x0338
173#define REG_RX_DESA 0x0340
174#define REG_DBI 0x0348
175#define REG_DBI_WDATA 0x0348
176#define REG_DBI_RDATA 0x034C
177#define REG_DBI_CTRL 0x0350
178#define REG_DBI_FLAG 0x0352
179#define REG_MDIO 0x0354
180#define REG_DBG_SEL 0x0360
181#define REG_PCIE_HRPWM 0x0361
182#define REG_PCIE_HCPWM 0x0363
183#define REG_UART_CTRL 0x0364
184#define REG_UART_TX_DESA 0x0370
185#define REG_UART_RX_DESA 0x0378
186
187/* ----------------------------------------------------- */
188/* 0x0400h ~ 0x047Fh Protocol Configuration */
189/* ----------------------------------------------------- */
190#define REG_VOQ_INFORMATION 0x0400
191#define REG_VIQ_INFORMATION 0x0404
192#define REG_BEQ_INFORMATION 0x0408
193#define REG_BKQ_INFORMATION 0x040C
194#define REG_MGQ_INFORMATION 0x0410
195#define REG_HGQ_INFORMATION 0x0414
196#define REG_BCNQ_INFORMATION 0x0418
197
198
199#define REG_CPU_MGQ_INFORMATION 0x041C
200#define REG_FWHW_TXQ_CTRL 0x0420
201#define REG_HWSEQ_CTRL 0x0423
202#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
203#define REG_TXPKTBUF_MGQ_BDNY 0x0425
204#define REG_MULTI_BCNQ_EN 0x0426
205#define REG_MULTI_BCNQ_OFFSET 0x0427
206#define REG_SPEC_SIFS 0x0428
207#define REG_RL 0x042A
208#define REG_DARFRC 0x0430
209#define REG_RARFRC 0x0438
210#define REG_RRSR 0x0440
211#define REG_ARFR0 0x0444
212#define REG_ARFR1 0x0448
213#define REG_ARFR2 0x044C
214#define REG_ARFR3 0x0450
215#define REG_AGGLEN_LMT 0x0458
216#define REG_AMPDU_MIN_SPACE 0x045C
217#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
218#define REG_FAST_EDCA_CTRL 0x0460
219#define REG_RD_RESP_PKT_TH 0x0463
220#define REG_INIRTS_RATE_SEL 0x0480
221#define REG_INIDATA_RATE_SEL 0x0484
222#define REG_POWER_STATUS 0x04A4
223#define REG_POWER_STAGE1 0x04B4
224#define REG_POWER_STAGE2 0x04B8
225#define REG_PKT_LIFE_TIME 0x04C0
226#define REG_STBC_SETTING 0x04C4
227#define REG_PROT_MODE_CTRL 0x04C8
228#define REG_MAX_AGGR_NUM 0x04CA
229#define REG_RTS_MAX_AGGR_NUM 0x04CB
230#define REG_BAR_MODE_CTRL 0x04CC
231#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
232#define REG_EARLY_MODE_CONTROL 0x4D0
233#define REG_NQOS_SEQ 0x04DC
234#define REG_QOS_SEQ 0x04DE
235#define REG_NEED_CPU_HANDLE 0x04E0
236#define REG_PKT_LOSE_RPT 0x04E1
237#define REG_PTCL_ERR_STATUS 0x04E2
238#define REG_DUMMY 0x04FC
239
240/* ----------------------------------------------------- */
241/* 0x0500h ~ 0x05FFh EDCA Configuration */
242/* ----------------------------------------------------- */
243#define REG_EDCA_VO_PARAM 0x0500
244#define REG_EDCA_VI_PARAM 0x0504
245#define REG_EDCA_BE_PARAM 0x0508
246#define REG_EDCA_BK_PARAM 0x050C
247#define REG_BCNTCFG 0x0510
248#define REG_PIFS 0x0512
249#define REG_RDG_PIFS 0x0513
250#define REG_SIFS_CTX 0x0514
251#define REG_SIFS_TRX 0x0516
252#define REG_AGGR_BREAK_TIME 0x051A
253#define REG_SLOT 0x051B
254#define REG_TX_PTCL_CTRL 0x0520
255#define REG_TXPAUSE 0x0522
256#define REG_DIS_TXREQ_CLR 0x0523
257#define REG_RD_CTRL 0x0524
258#define REG_TBTT_PROHIBIT 0x0540
259#define REG_RD_NAV_NXT 0x0544
260#define REG_NAV_PROT_LEN 0x0546
261#define REG_BCN_CTRL 0x0550
262#define REG_USTIME_TSF 0x0551
263#define REG_MBID_NUM 0x0552
264#define REG_DUAL_TSF_RST 0x0553
265#define REG_BCN_INTERVAL 0x0554
266#define REG_MBSSID_BCN_SPACE 0x0554
267#define REG_DRVERLYINT 0x0558
268#define REG_BCNDMATIM 0x0559
269#define REG_ATIMWND 0x055A
270#define REG_BCN_MAX_ERR 0x055D
271#define REG_RXTSF_OFFSET_CCK 0x055E
272#define REG_RXTSF_OFFSET_OFDM 0x055F
273#define REG_TSFTR 0x0560
274#define REG_INIT_TSFTR 0x0564
275#define REG_PSTIMER 0x0580
276#define REG_TIMER0 0x0584
277#define REG_TIMER1 0x0588
278#define REG_ACMHWCTRL 0x05C0
279#define REG_ACMRSTCTRL 0x05C1
280#define REG_ACMAVG 0x05C2
281#define REG_VO_ADMTIME 0x05C4
282#define REG_VI_ADMTIME 0x05C6
283#define REG_BE_ADMTIME 0x05C8
284#define REG_EDCA_RANDOM_GEN 0x05CC
285#define REG_SCH_TXCMD 0x05D0
286
287/* Dual MAC Co-Existence Register */
288#define REG_DMC 0x05F0
289
290/* ----------------------------------------------------- */
291/* 0x0600h ~ 0x07FFh WMAC Configuration */
292/* ----------------------------------------------------- */
293#define REG_APSD_CTRL 0x0600
294#define REG_BWOPMODE 0x0603
295#define REG_TCR 0x0604
296#define REG_RCR 0x0608
297#define REG_RX_PKT_LIMIT 0x060C
298#define REG_RX_DLK_TIME 0x060D
299#define REG_RX_DRVINFO_SZ 0x060F
300
301#define REG_MACID 0x0610
302#define REG_BSSID 0x0618
303#define REG_MAR 0x0620
304#define REG_MBIDCAMCFG 0x0628
305
306#define REG_USTIME_EDCA 0x0638
307#define REG_MAC_SPEC_SIFS 0x063A
308#define REG_RESP_SIFS_CCK 0x063C
309#define REG_RESP_SIFS_OFDM 0x063E
310#define REG_ACKTO 0x0640
311#define REG_CTS2TO 0x0641
312#define REG_EIFS 0x0642
313
314
315/* WMA, BA, CCX */
316#define REG_NAV_CTRL 0x0650
317#define REG_BACAMCMD 0x0654
318#define REG_BACAMCONTENT 0x0658
319#define REG_LBDLY 0x0660
320#define REG_FWDLY 0x0661
321#define REG_RXERR_RPT 0x0664
322#define REG_WMAC_TRXPTCL_CTL 0x0668
323
324
325/* Security */
326#define REG_CAMCMD 0x0670
327#define REG_CAMWRITE 0x0674
328#define REG_CAMREAD 0x0678
329#define REG_CAMDBG 0x067C
330#define REG_SECCFG 0x0680
331
332/* Power */
333#define REG_WOW_CTRL 0x0690
334#define REG_PSSTATUS 0x0691
335#define REG_PS_RX_INFO 0x0692
336#define REG_LPNAV_CTRL 0x0694
337#define REG_WKFMCAM_CMD 0x0698
338#define REG_WKFMCAM_RWD 0x069C
339#define REG_RXFLTMAP0 0x06A0
340#define REG_RXFLTMAP1 0x06A2
341#define REG_RXFLTMAP2 0x06A4
342#define REG_BCN_PSR_RPT 0x06A8
343#define REG_CALB32K_CTRL 0x06AC
344#define REG_PKT_MON_CTRL 0x06B4
345#define REG_BT_COEX_TABLE 0x06C0
346#define REG_WMAC_RESP_TXINFO 0x06D8
347
348
349/* ----------------------------------------------------- */
350/* Redifine 8192C register definition for compatibility */
351/* ----------------------------------------------------- */
352#define CR9346 REG_9346CR
353#define MSR (REG_CR + 2)
354#define ISR REG_HISR
355#define TSFR REG_TSFTR
356
357#define MACIDR0 REG_MACID
358#define MACIDR4 (REG_MACID + 4)
359
360#define PBP REG_PBP
361
362#define IDR0 MACIDR0
363#define IDR4 MACIDR4
364
365/* ----------------------------------------------------- */
366/* 8192C (MSR) Media Status Register(Offset 0x4C, 8 bits)*/
367/* ----------------------------------------------------- */
368#define MSR_NOLINK 0x00
369#define MSR_ADHOC 0x01
370#define MSR_INFRA 0x02
371#define MSR_AP 0x03
372
373/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
374/* ----------------------------------------------------- */
375/* 8192C Response Rate Set Register(offset 0x181, 24bits)*/
376/* ----------------------------------------------------- */
377#define RRSR_RSC_OFFSET 21
378#define RRSR_SHORT_OFFSET 23
379#define RRSR_RSC_BW_40M 0x600000
380#define RRSR_RSC_UPSUBCHNL 0x400000
381#define RRSR_RSC_LOWSUBCHNL 0x200000
382#define RRSR_SHORT 0x800000
383#define RRSR_1M BIT0
384#define RRSR_2M BIT1
385#define RRSR_5_5M BIT2
386#define RRSR_11M BIT3
387#define RRSR_6M BIT4
388#define RRSR_9M BIT5
389#define RRSR_12M BIT6
390#define RRSR_18M BIT7
391#define RRSR_24M BIT8
392#define RRSR_36M BIT9
393#define RRSR_48M BIT10
394#define RRSR_54M BIT11
395#define RRSR_MCS0 BIT12
396#define RRSR_MCS1 BIT13
397#define RRSR_MCS2 BIT14
398#define RRSR_MCS3 BIT15
399#define RRSR_MCS4 BIT16
400#define RRSR_MCS5 BIT17
401#define RRSR_MCS6 BIT18
402#define RRSR_MCS7 BIT19
403#define BRSR_ACKSHORTPMB BIT23
404
405/* ----------------------------------------------------- */
406/* 8192C Rate Definition */
407/* ----------------------------------------------------- */
408/* CCK */
409#define RATR_1M 0x00000001
410#define RATR_2M 0x00000002
411#define RATR_55M 0x00000004
412#define RATR_11M 0x00000008
413/* OFDM */
414#define RATR_6M 0x00000010
415#define RATR_9M 0x00000020
416#define RATR_12M 0x00000040
417#define RATR_18M 0x00000080
418#define RATR_24M 0x00000100
419#define RATR_36M 0x00000200
420#define RATR_48M 0x00000400
421#define RATR_54M 0x00000800
422/* MCS 1 Spatial Stream */
423#define RATR_MCS0 0x00001000
424#define RATR_MCS1 0x00002000
425#define RATR_MCS2 0x00004000
426#define RATR_MCS3 0x00008000
427#define RATR_MCS4 0x00010000
428#define RATR_MCS5 0x00020000
429#define RATR_MCS6 0x00040000
430#define RATR_MCS7 0x00080000
431/* MCS 2 Spatial Stream */
432#define RATR_MCS8 0x00100000
433#define RATR_MCS9 0x00200000
434#define RATR_MCS10 0x00400000
435#define RATR_MCS11 0x00800000
436#define RATR_MCS12 0x01000000
437#define RATR_MCS13 0x02000000
438#define RATR_MCS14 0x04000000
439#define RATR_MCS15 0x08000000
440
441/* CCK */
442#define RATE_1M BIT(0)
443#define RATE_2M BIT(1)
444#define RATE_5_5M BIT(2)
445#define RATE_11M BIT(3)
446/* OFDM */
447#define RATE_6M BIT(4)
448#define RATE_9M BIT(5)
449#define RATE_12M BIT(6)
450#define RATE_18M BIT(7)
451#define RATE_24M BIT(8)
452#define RATE_36M BIT(9)
453#define RATE_48M BIT(10)
454#define RATE_54M BIT(11)
455/* MCS 1 Spatial Stream */
456#define RATE_MCS0 BIT(12)
457#define RATE_MCS1 BIT(13)
458#define RATE_MCS2 BIT(14)
459#define RATE_MCS3 BIT(15)
460#define RATE_MCS4 BIT(16)
461#define RATE_MCS5 BIT(17)
462#define RATE_MCS6 BIT(18)
463#define RATE_MCS7 BIT(19)
464/* MCS 2 Spatial Stream */
465#define RATE_MCS8 BIT(20)
466#define RATE_MCS9 BIT(21)
467#define RATE_MCS10 BIT(22)
468#define RATE_MCS11 BIT(23)
469#define RATE_MCS12 BIT(24)
470#define RATE_MCS13 BIT(25)
471#define RATE_MCS14 BIT(26)
472#define RATE_MCS15 BIT(27)
473
474/* ALL CCK Rate */
475#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | \
476 RATR_11M)
477#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | \
478 RATR_18M | RATR_24M | \
479 RATR_36M | RATR_48M | RATR_54M)
480#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
481 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
482 RATR_MCS6 | RATR_MCS7)
483#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
484 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
485 RATR_MCS14 | RATR_MCS15)
486
487/* ----------------------------------------------------- */
488/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
489/* ----------------------------------------------------- */
490#define BW_OPMODE_20MHZ BIT(2)
491#define BW_OPMODE_5G BIT(1)
492#define BW_OPMODE_11J BIT(0)
493
494
495/* ----------------------------------------------------- */
496/* 8192C CAM Config Setting (offset 0x250, 1 byte) */
497/* ----------------------------------------------------- */
498#define CAM_VALID BIT(15)
499#define CAM_NOTVALID 0x0000
500#define CAM_USEDK BIT(5)
501
502#define CAM_NONE 0x0
503#define CAM_WEP40 0x01
504#define CAM_TKIP 0x02
505#define CAM_AES 0x04
506#define CAM_WEP104 0x05
507#define CAM_SMS4 0x6
508
509
510#define TOTAL_CAM_ENTRY 32
511#define HALF_CAM_ENTRY 16
512
513#define CAM_WRITE BIT(16)
514#define CAM_READ 0x00000000
515#define CAM_POLLINIG BIT(31)
516
517/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
518#define WOW_PMEN BIT0 /* Power management Enable. */
519#define WOW_WOMEN BIT1 /* WoW function on or off. */
520#define WOW_MAGIC BIT2 /* Magic packet */
521#define WOW_UWF BIT3 /* Unicast Wakeup frame. */
522
523/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
524/* ----------------------------------------------------- */
525/* 8190 IMR/ISR bits (offset 0xfd, 8bits) */
526/* ----------------------------------------------------- */
527#define IMR8190_DISABLED 0x0
528#define IMR_BCNDMAINT6 BIT(31)
529#define IMR_BCNDMAINT5 BIT(30)
530#define IMR_BCNDMAINT4 BIT(29)
531#define IMR_BCNDMAINT3 BIT(28)
532#define IMR_BCNDMAINT2 BIT(27)
533#define IMR_BCNDMAINT1 BIT(26)
534#define IMR_BCNDOK8 BIT(25)
535#define IMR_BCNDOK7 BIT(24)
536#define IMR_BCNDOK6 BIT(23)
537#define IMR_BCNDOK5 BIT(22)
538#define IMR_BCNDOK4 BIT(21)
539#define IMR_BCNDOK3 BIT(20)
540#define IMR_BCNDOK2 BIT(19)
541#define IMR_BCNDOK1 BIT(18)
542#define IMR_TIMEOUT2 BIT(17)
543#define IMR_TIMEOUT1 BIT(16)
544#define IMR_TXFOVW BIT(15)
545#define IMR_PSTIMEOUT BIT(14)
546#define IMR_BcnInt BIT(13)
547#define IMR_RXFOVW BIT(12)
548#define IMR_RDU BIT(11)
549#define IMR_ATIMEND BIT(10)
550#define IMR_BDOK BIT(9)
551#define IMR_HIGHDOK BIT(8)
552#define IMR_TBDOK BIT(7)
553#define IMR_MGNTDOK BIT(6)
554#define IMR_TBDER BIT(5)
555#define IMR_BKDOK BIT(4)
556#define IMR_BEDOK BIT(3)
557#define IMR_VIDOK BIT(2)
558#define IMR_VODOK BIT(1)
559#define IMR_ROK BIT(0)
560
561#define IMR_TXERR BIT(11)
562#define IMR_RXERR BIT(10)
563#define IMR_C2HCMD BIT(9)
564#define IMR_CPWM BIT(8)
565#define IMR_OCPINT BIT(1)
566#define IMR_WLANOFF BIT(0)
567
568/* ----------------------------------------------------- */
569/* 8192C EFUSE */
570/* ----------------------------------------------------- */
571#define HWSET_MAX_SIZE 256
572#define EFUSE_MAX_SECTION 32
573#define EFUSE_REAL_CONTENT_LEN 512
574
575/* ----------------------------------------------------- */
576/* 8192C EEPROM/EFUSE share register definition. */
577/* ----------------------------------------------------- */
578#define EEPROM_DEFAULT_TSSI 0x0
579#define EEPROM_DEFAULT_CRYSTALCAP 0x0
580#define EEPROM_DEFAULT_THERMALMETER 0x12
581
582#define EEPROM_DEFAULT_TXPOWERLEVEL_2G 0x2C
583#define EEPROM_DEFAULT_TXPOWERLEVEL_5G 0x22
584
585#define EEPROM_DEFAULT_HT40_2SDIFF 0x0
586/* HT20<->40 default Tx Power Index Difference */
587#define EEPROM_DEFAULT_HT20_DIFF 2
588/* OFDM Tx Power index diff */
589#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x4
590#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0
591#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0
592
593#define EEPROM_CHANNEL_PLAN_FCC 0x0
594#define EEPROM_CHANNEL_PLAN_IC 0x1
595#define EEPROM_CHANNEL_PLAN_ETSI 0x2
596#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
597#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
598#define EEPROM_CHANNEL_PLAN_MKK 0x5
599#define EEPROM_CHANNEL_PLAN_MKK1 0x6
600#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
601#define EEPROM_CHANNEL_PLAN_TELEC 0x8
602#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
603#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
604#define EEPROM_CHANNEL_PLAN_NCC 0xB
605#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
606
607#define EEPROM_CID_DEFAULT 0x0
608#define EEPROM_CID_TOSHIBA 0x4
609#define EEPROM_CID_CCX 0x10
610#define EEPROM_CID_QMI 0x0D
611#define EEPROM_CID_WHQL 0xFE
612
613
614#define RTL8192_EEPROM_ID 0x8129
615#define EEPROM_WAPI_SUPPORT 0x78
616
617
618#define RTL8190_EEPROM_ID 0x8129 /* 0-1 */
619#define EEPROM_HPON 0x02 /* LDO settings.2-5 */
620#define EEPROM_CLK 0x06 /* Clock settings.6-7 */
621#define EEPROM_MAC_FUNCTION 0x08 /* SE Test mode.8 */
622
623#define EEPROM_VID 0x28 /* SE Vendor ID.A-B */
624#define EEPROM_DID 0x2A /* SE Device ID. C-D */
625#define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */
626#define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */
627
628#define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */
629#define EEPROM_MAC_ADDR_MAC0_92D 0x55
630#define EEPROM_MAC_ADDR_MAC1_92D 0x5B
631
632/* 2.4G band Tx power index setting */
633#define EEPROM_CCK_TX_PWR_INX_2G 0x61
634#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67
635#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D
636#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70
637#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73
638#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76
639#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79
640
641/*5GL channel 32-64 */
642#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C
643#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82
644#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85
645#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88
646#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B
647#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E
648
649/* 5GM channel 100-140 */
650#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91
651#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97
652#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A
653#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D
654#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0
655#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3
656
657/* 5GH channel 149-165 */
658#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6
659#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC
660#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF
661#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2
662#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5
663#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8
664
665/* Map of supported channels. */
666#define EEPROM_CHANNEL_PLAN 0xBB
667#define EEPROM_IQK_DELTA 0xBC
668#define EEPROM_LCK_DELTA 0xBC
669#define EEPROM_XTAL_K 0xBD /* [7:5] */
670#define EEPROM_TSSI_A_5G 0xBE
671#define EEPROM_TSSI_B_5G 0xBF
672#define EEPROM_TSSI_AB_5G 0xC0
673#define EEPROM_THERMAL_METER 0xC3 /* [4:0] */
674#define EEPROM_RF_OPT1 0xC4
675#define EEPROM_RF_OPT2 0xC5
676#define EEPROM_RF_OPT3 0xC6
677#define EEPROM_RF_OPT4 0xC7
678#define EEPROM_RF_OPT5 0xC8
679#define EEPROM_RF_OPT6 0xC9
680#define EEPROM_VERSION 0xCA
681#define EEPROM_CUSTOMER_ID 0xCB
682#define EEPROM_RF_OPT7 0xCC
683
684#define EEPROM_DEF_PART_NO 0x3FD /* Byte */
685#define EEPROME_CHIP_VERSION_L 0x3FF
686#define EEPROME_CHIP_VERSION_H 0x3FE
687
688/*
689 * Current IOREG MAP
690 * 0x0000h ~ 0x00FFh System Configuration (256 Bytes)
691 * 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
692 * 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
693 * 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
694 * 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
695 * 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
696 * 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
697 * 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
698 * 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
699 */
700
701/* ----------------------------------------------------- */
702/* 8192C (RCR) (Offset 0x608, 32 bits) */
703/* ----------------------------------------------------- */
704#define RCR_APPFCS BIT(31)
705#define RCR_APP_MIC BIT(30)
706#define RCR_APP_ICV BIT(29)
707#define RCR_APP_PHYST_RXFF BIT(28)
708#define RCR_APP_BA_SSN BIT(27)
709#define RCR_ENMBID BIT(24)
710#define RCR_LSIGEN BIT(23)
711#define RCR_MFBEN BIT(22)
712#define RCR_HTC_LOC_CTRL BIT(14)
713#define RCR_AMF BIT(13)
714#define RCR_ACF BIT(12)
715#define RCR_ADF BIT(11)
716#define RCR_AICV BIT(9)
717#define RCR_ACRC32 BIT(8)
718#define RCR_CBSSID_BCN BIT(7)
719#define RCR_CBSSID_DATA BIT(6)
720#define RCR_APWRMGT BIT(5)
721#define RCR_ADD3 BIT(4)
722#define RCR_AB BIT(3)
723#define RCR_AM BIT(2)
724#define RCR_APM BIT(1)
725#define RCR_AAP BIT(0)
726#define RCR_MXDMA_OFFSET 8
727#define RCR_FIFO_OFFSET 13
728
729/* ----------------------------------------------------- */
730/* 8192C Regsiter Bit and Content definition */
731/* ----------------------------------------------------- */
732/* ----------------------------------------------------- */
733/* 0x0000h ~ 0x00FFh System Configuration */
734/* ----------------------------------------------------- */
735
736/* SPS0_CTRL */
737#define SW18_FPWM BIT(3)
738
739
740/* SYS_ISO_CTRL */
741#define ISO_MD2PP BIT(0)
742#define ISO_UA2USB BIT(1)
743#define ISO_UD2CORE BIT(2)
744#define ISO_PA2PCIE BIT(3)
745#define ISO_PD2CORE BIT(4)
746#define ISO_IP2MAC BIT(5)
747#define ISO_DIOP BIT(6)
748#define ISO_DIOE BIT(7)
749#define ISO_EB2CORE BIT(8)
750#define ISO_DIOR BIT(9)
751
752#define PWC_EV25V BIT(14)
753#define PWC_EV12V BIT(15)
754
755
756/* SYS_FUNC_EN */
757#define FEN_BBRSTB BIT(0)
758#define FEN_BB_GLB_RSTn BIT(1)
759#define FEN_USBA BIT(2)
760#define FEN_UPLL BIT(3)
761#define FEN_USBD BIT(4)
762#define FEN_DIO_PCIE BIT(5)
763#define FEN_PCIEA BIT(6)
764#define FEN_PPLL BIT(7)
765#define FEN_PCIED BIT(8)
766#define FEN_DIOE BIT(9)
767#define FEN_CPUEN BIT(10)
768#define FEN_DCORE BIT(11)
769#define FEN_ELDR BIT(12)
770#define FEN_DIO_RF BIT(13)
771#define FEN_HWPDN BIT(14)
772#define FEN_MREGEN BIT(15)
773
774/* APS_FSMCO */
775#define PFM_LDALL BIT(0)
776#define PFM_ALDN BIT(1)
777#define PFM_LDKP BIT(2)
778#define PFM_WOWL BIT(3)
779#define EnPDN BIT(4)
780#define PDN_PL BIT(5)
781#define APFM_ONMAC BIT(8)
782#define APFM_OFF BIT(9)
783#define APFM_RSM BIT(10)
784#define AFSM_HSUS BIT(11)
785#define AFSM_PCIE BIT(12)
786#define APDM_MAC BIT(13)
787#define APDM_HOST BIT(14)
788#define APDM_HPDN BIT(15)
789#define RDY_MACON BIT(16)
790#define SUS_HOST BIT(17)
791#define ROP_ALD BIT(20)
792#define ROP_PWR BIT(21)
793#define ROP_SPS BIT(22)
794#define SOP_MRST BIT(25)
795#define SOP_FUSE BIT(26)
796#define SOP_ABG BIT(27)
797#define SOP_AMB BIT(28)
798#define SOP_RCK BIT(29)
799#define SOP_A8M BIT(30)
800#define XOP_BTCK BIT(31)
801
802/* SYS_CLKR */
803#define ANAD16V_EN BIT(0)
804#define ANA8M BIT(1)
805#define MACSLP BIT(4)
806#define LOADER_CLK_EN BIT(5)
807#define _80M_SSC_DIS BIT(7)
808#define _80M_SSC_EN_HO BIT(8)
809#define PHY_SSC_RSTB BIT(9)
810#define SEC_CLK_EN BIT(10)
811#define MAC_CLK_EN BIT(11)
812#define SYS_CLK_EN BIT(12)
813#define RING_CLK_EN BIT(13)
814
815
816/* 9346CR */
817#define BOOT_FROM_EEPROM BIT(4)
818#define EEPROM_EN BIT(5)
819
820/* AFE_MISC */
821#define AFE_BGEN BIT(0)
822#define AFE_MBEN BIT(1)
823#define MAC_ID_EN BIT(7)
824
825/* RSV_CTRL */
826#define WLOCK_ALL BIT(0)
827#define WLOCK_00 BIT(1)
828#define WLOCK_04 BIT(2)
829#define WLOCK_08 BIT(3)
830#define WLOCK_40 BIT(4)
831#define R_DIS_PRST_0 BIT(5)
832#define R_DIS_PRST_1 BIT(6)
833#define LOCK_ALL_EN BIT(7)
834
835/* RF_CTRL */
836#define RF_EN BIT(0)
837#define RF_RSTB BIT(1)
838#define RF_SDMRSTB BIT(2)
839
840
841
842/* LDOA15_CTRL */
843#define LDA15_EN BIT(0)
844#define LDA15_STBY BIT(1)
845#define LDA15_OBUF BIT(2)
846#define LDA15_REG_VOS BIT(3)
847#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
848
849
850
851/* LDOV12D_CTRL */
852#define LDV12_EN BIT(0)
853#define LDV12_SDBY BIT(1)
854#define LPLDO_HSM BIT(2)
855#define LPLDO_LSM_DIS BIT(3)
856#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
857
858
859/* AFE_XTAL_CTRL */
860#define XTAL_EN BIT(0)
861#define XTAL_BSEL BIT(1)
862#define _XTAL_BOSC(x) (((x) & 0x3) << 2)
863#define _XTAL_CADJ(x) (((x) & 0xF) << 4)
864#define XTAL_GATE_USB BIT(8)
865#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
866#define XTAL_GATE_AFE BIT(11)
867#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
868#define XTAL_RF_GATE BIT(14)
869#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
870#define XTAL_GATE_DIG BIT(17)
871#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
872#define XTAL_BT_GATE BIT(20)
873#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
874#define _XTAL_GPIO(x) (((x) & 0x7) << 23)
875
876
877#define CKDLY_AFE BIT(26)
878#define CKDLY_USB BIT(27)
879#define CKDLY_DIG BIT(28)
880#define CKDLY_BT BIT(29)
881
882
883/* AFE_PLL_CTRL */
884#define APLL_EN BIT(0)
885#define APLL_320_EN BIT(1)
886#define APLL_FREF_SEL BIT(2)
887#define APLL_EDGE_SEL BIT(3)
888#define APLL_WDOGB BIT(4)
889#define APLL_LPFEN BIT(5)
890
891#define APLL_REF_CLK_13MHZ 0x1
892#define APLL_REF_CLK_19_2MHZ 0x2
893#define APLL_REF_CLK_20MHZ 0x3
894#define APLL_REF_CLK_25MHZ 0x4
895#define APLL_REF_CLK_26MHZ 0x5
896#define APLL_REF_CLK_38_4MHZ 0x6
897#define APLL_REF_CLK_40MHZ 0x7
898
899#define APLL_320EN BIT(14)
900#define APLL_80EN BIT(15)
901#define APLL_1MEN BIT(24)
902
903
904/* EFUSE_CTRL */
905#define ALD_EN BIT(18)
906#define EF_PD BIT(19)
907#define EF_FLAG BIT(31)
908
909/* EFUSE_TEST */
910#define EF_TRPT BIT(7)
911#define LDOE25_EN BIT(31)
912
913/* MCUFWDL */
914#define MCUFWDL_EN BIT(0)
915#define MCUFWDL_RDY BIT(1)
916#define FWDL_ChkSum_rpt BIT(2)
917#define MACINI_RDY BIT(3)
918#define BBINI_RDY BIT(4)
919#define RFINI_RDY BIT(5)
920#define WINTINI_RDY BIT(6)
921#define MAC1_WINTINI_RDY BIT(11)
922#define CPRST BIT(23)
923
924/* REG_SYS_CFG */
925#define XCLK_VLD BIT(0)
926#define ACLK_VLD BIT(1)
927#define UCLK_VLD BIT(2)
928#define PCLK_VLD BIT(3)
929#define PCIRSTB BIT(4)
930#define V15_VLD BIT(5)
931#define TRP_B15V_EN BIT(7)
932#define SIC_IDLE BIT(8)
933#define BD_MAC2 BIT(9)
934#define BD_MAC1 BIT(10)
935#define IC_MACPHY_MODE BIT(11)
936#define PAD_HWPD_IDN BIT(22)
937#define TRP_VAUX_EN BIT(23)
938#define TRP_BT_EN BIT(24)
939#define BD_PKG_SEL BIT(25)
940#define BD_HCI_SEL BIT(26)
941#define TYPE_ID BIT(27)
942
943/* LLT_INIT */
944#define _LLT_NO_ACTIVE 0x0
945#define _LLT_WRITE_ACCESS 0x1
946#define _LLT_READ_ACCESS 0x2
947
948#define _LLT_INIT_DATA(x) ((x) & 0xFF)
949#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
950#define _LLT_OP(x) (((x) & 0x3) << 30)
951#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
952
953
954/* ----------------------------------------------------- */
955/* 0x0400h ~ 0x047Fh Protocol Configuration */
956/* ----------------------------------------------------- */
957#define RETRY_LIMIT_SHORT_SHIFT 8
958#define RETRY_LIMIT_LONG_SHIFT 0
959
960
961/* ----------------------------------------------------- */
962/* 0x0500h ~ 0x05FFh EDCA Configuration */
963/* ----------------------------------------------------- */
964/* EDCA setting */
965#define AC_PARAM_TXOP_LIMIT_OFFSET 16
966#define AC_PARAM_ECW_MAX_OFFSET 12
967#define AC_PARAM_ECW_MIN_OFFSET 8
968#define AC_PARAM_AIFS_OFFSET 0
969
970/* ACMHWCTRL */
971#define ACMHW_HWEN BIT(0)
972#define ACMHW_BEQEN BIT(1)
973#define ACMHW_VIQEN BIT(2)
974#define ACMHW_VOQEN BIT(3)
975
976/* ----------------------------------------------------- */
977/* 0x0600h ~ 0x07FFh WMAC Configuration */
978/* ----------------------------------------------------- */
979
980/* TCR */
981#define TSFRST BIT(0)
982#define DIS_GCLK BIT(1)
983#define PAD_SEL BIT(2)
984#define PWR_ST BIT(6)
985#define PWRBIT_OW_EN BIT(7)
986#define ACRC BIT(8)
987#define CFENDFORM BIT(9)
988#define ICV BIT(10)
989
990/* SECCFG */
991#define SCR_TXUSEDK BIT(0)
992#define SCR_RXUSEDK BIT(1)
993#define SCR_TXENCENABLE BIT(2)
994#define SCR_RXENCENABLE BIT(3)
995#define SCR_SKBYA2 BIT(4)
996#define SCR_NOSKMC BIT(5)
997#define SCR_TXBCUSEDK BIT(6)
998#define SCR_RXBCUSEDK BIT(7)
999
1000/* General definitions */
1001#define MAC_ADDR_LEN 6
1002#define LAST_ENTRY_OF_TX_PKT_BUFFER 255
1003#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127
1004
1005#define POLLING_LLT_THRESHOLD 20
1006#define POLLING_READY_TIMEOUT_COUNT 1000
1007
1008/* Min Spacing related settings. */
1009#define MAX_MSS_DENSITY_2T 0x13
1010#define MAX_MSS_DENSITY_1T 0x0A
1011
1012
1013/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
1014/* 1. PMAC duplicate register due to connection: */
1015/* RF_Mode, TRxRN, NumOf L-STF */
1016/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
1017/* 3. RF register 0x00-2E */
1018/* 4. Bit Mask for BB/RF register */
1019/* 5. Other defintion for BB/RF R/W */
1020
1021/* 3. Page8(0x800) */
1022#define RFPGA0_RFMOD 0x800
1023
1024#define RFPGA0_TXINFO 0x804
1025#define RFPGA0_PSDFUNCTION 0x808
1026
1027#define RFPGA0_TXGAINSTAGE 0x80c
1028
1029#define RFPGA0_RFTIMING1 0x810
1030#define RFPGA0_RFTIMING2 0x814
1031
1032#define RFPGA0_XA_HSSIPARAMETER1 0x820
1033#define RFPGA0_XA_HSSIPARAMETER2 0x824
1034#define RFPGA0_XB_HSSIPARAMETER1 0x828
1035#define RFPGA0_XB_HSSIPARAMETER2 0x82c
1036
1037#define RFPGA0_XA_LSSIPARAMETER 0x840
1038#define RFPGA0_XB_LSSIPARAMETER 0x844
1039
1040#define RFPGA0_RFWAkEUPPARAMETER 0x850
1041#define RFPGA0_RFSLEEPUPPARAMETER 0x854
1042
1043#define RFPGA0_XAB_SWITCHCONTROL 0x858
1044#define RFPGA0_XCD_SWITCHCONTROL 0x85c
1045
1046#define RFPGA0_XA_RFINTERFACEOE 0x860
1047#define RFPGA0_XB_RFINTERFACEOE 0x864
1048
1049#define RFPGA0_XAB_RFINTERFACESW 0x870
1050#define RFPGA0_XCD_RFINTERFACESW 0x874
1051
1052#define RFPGA0_XAB_RFPARAMETER 0x878
1053#define RFPGA0_XCD_RFPARAMETER 0x87c
1054
1055#define RFPGA0_ANALOGPARAMETER1 0x880
1056#define RFPGA0_ANALOGPARAMETER2 0x884
1057#define RFPGA0_ANALOGPARAMETER3 0x888
1058#define RFPGA0_ADDALLOCKEN 0x888
1059#define RFPGA0_ANALOGPARAMETER4 0x88c
1060
1061#define RFPGA0_XA_LSSIREADBACK 0x8a0
1062#define RFPGA0_XB_LSSIREADBACK 0x8a4
1063#define RFPGA0_XC_LSSIREADBACK 0x8a8
1064#define RFPGA0_XD_LSSIREADBACK 0x8ac
1065
1066#define RFPGA0_PSDREPORT 0x8b4
1067#define TRANSCEIVERA_HSPI_READBACK 0x8b8
1068#define TRANSCEIVERB_HSPI_READBACK 0x8bc
1069#define RFPGA0_XAB_RFINTERFACERB 0x8e0
1070#define RFPGA0_XCD_RFINTERFACERB 0x8e4
1071
1072/* 4. Page9(0x900) */
1073#define RFPGA1_RFMOD 0x900
1074
1075#define RFPGA1_TXBLOCK 0x904
1076#define RFPGA1_DEBUGSELECT 0x908
1077#define RFPGA1_TXINFO 0x90c
1078
1079/* 5. PageA(0xA00) */
1080#define RCCK0_SYSTEM 0xa00
1081
1082#define RCCK0_AFESSTTING 0xa04
1083#define RCCK0_CCA 0xa08
1084
1085#define RCCK0_RXAGC1 0xa0c
1086#define RCCK0_RXAGC2 0xa10
1087
1088#define RCCK0_RXHP 0xa14
1089
1090#define RCCK0_DSPPARAMETER1 0xa18
1091#define RCCK0_DSPPARAMETER2 0xa1c
1092
1093#define RCCK0_TXFILTER1 0xa20
1094#define RCCK0_TXFILTER2 0xa24
1095#define RCCK0_DEBUGPORT 0xa28
1096#define RCCK0_FALSEALARMREPORT 0xa2c
1097#define RCCK0_TRSSIREPORT 0xa50
1098#define RCCK0_RXREPORT 0xa54
1099#define RCCK0_FACOUNTERLOWER 0xa5c
1100#define RCCK0_FACOUNTERUPPER 0xa58
1101
1102/* 6. PageC(0xC00) */
1103#define ROFDM0_LSTF 0xc00
1104
1105#define ROFDM0_TRXPATHENABLE 0xc04
1106#define ROFDM0_TRMUXPAR 0xc08
1107#define ROFDM0_TRSWISOLATION 0xc0c
1108
1109#define ROFDM0_XARXAFE 0xc10
1110#define ROFDM0_XARXIQIMBALANCE 0xc14
1111#define ROFDM0_XBRXAFE 0xc18
1112#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1113#define ROFDM0_XCRXAFE 0xc20
1114#define ROFDM0_XCRXIQIMBALANCE 0xc24
1115#define ROFDM0_XDRXAFE 0xc28
1116#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1117
1118#define ROFDM0_RXDETECTOR1 0xc30
1119#define ROFDM0_RXDETECTOR2 0xc34
1120#define ROFDM0_RXDETECTOR3 0xc38
1121#define ROFDM0_RXDETECTOR4 0xc3c
1122
1123#define ROFDM0_RXDSP 0xc40
1124#define ROFDM0_CFOANDDAGC 0xc44
1125#define ROFDM0_CCADROPTHRESHOLD 0xc48
1126#define ROFDM0_ECCATHRESHOLD 0xc4c
1127
1128#define ROFDM0_XAAGCCORE1 0xc50
1129#define ROFDM0_XAAGCCORE2 0xc54
1130#define ROFDM0_XBAGCCORE1 0xc58
1131#define ROFDM0_XBAGCCORE2 0xc5c
1132#define ROFDM0_XCAGCCORE1 0xc60
1133#define ROFDM0_XCAGCCORE2 0xc64
1134#define ROFDM0_XDAGCCORE1 0xc68
1135#define ROFDM0_XDAGCCORE2 0xc6c
1136
1137#define ROFDM0_AGCPARAMETER1 0xc70
1138#define ROFDM0_AGCPARAMETER2 0xc74
1139#define ROFDM0_AGCRSSITABLE 0xc78
1140#define ROFDM0_HTSTFAGC 0xc7c
1141
1142#define ROFDM0_XATxIQIMBALANCE 0xc80
1143#define ROFDM0_XATxAFE 0xc84
1144#define ROFDM0_XBTxIQIMBALANCE 0xc88
1145#define ROFDM0_XBTxAFE 0xc8c
1146#define ROFDM0_XCTxIQIMBALANCE 0xc90
1147#define ROFDM0_XCTxAFE 0xc94
1148#define ROFDM0_XDTxIQIMBALANCE 0xc98
1149#define ROFDM0_XDTxAFE 0xc9c
1150
1151#define ROFDM0_RXHPPARAMETER 0xce0
1152#define ROFDM0_TXPSEUDONOISEWGT 0xce4
1153#define ROFDM0_FRAMESYNC 0xcf0
1154#define ROFDM0_DFSREPORT 0xcf4
1155#define ROFDM0_TXCOEFF1 0xca4
1156#define ROFDM0_TXCOEFF2 0xca8
1157#define ROFDM0_TXCOEFF3 0xcac
1158#define ROFDM0_TXCOEFF4 0xcb0
1159#define ROFDM0_TXCOEFF5 0xcb4
1160#define ROFDM0_TXCOEFF6 0xcb8
1161
1162/* 7. PageD(0xD00) */
1163#define ROFDM1_LSTF 0xd00
1164#define ROFDM1_TRXPATHENABLE 0xd04
1165
1166#define ROFDM1_CFO 0xd08
1167#define ROFDM1_CSI1 0xd10
1168#define ROFDM1_SBD 0xd14
1169#define ROFDM1_CSI2 0xd18
1170#define ROFDM1_CFOTRACKING 0xd2c
1171#define ROFDM1_TRXMESAURE1 0xd34
1172#define ROFDM1_INTFDET 0xd3c
1173#define ROFDM1_PSEUDONOISESTATEAB 0xd50
1174#define ROFDM1_PSEUDONOISESTATECD 0xd54
1175#define ROFDM1_RXPSEUDONOISEWGT 0xd58
1176
1177#define ROFDM_PHYCOUNTER1 0xda0
1178#define ROFDM_PHYCOUNTER2 0xda4
1179#define ROFDM_PHYCOUNTER3 0xda8
1180
1181#define ROFDM_SHORTCFOAB 0xdac
1182#define ROFDM_SHORTCFOCD 0xdb0
1183#define ROFDM_LONGCFOAB 0xdb4
1184#define ROFDM_LONGCFOCD 0xdb8
1185#define ROFDM_TAILCFOAB 0xdbc
1186#define ROFDM_TAILCFOCD 0xdc0
1187#define ROFDM_PWMEASURE1 0xdc4
1188#define ROFDM_PWMEASURE2 0xdc8
1189#define ROFDM_BWREPORT 0xdcc
1190#define ROFDM_AGCREPORT 0xdd0
1191#define ROFDM_RXSNR 0xdd4
1192#define ROFDM_RXEVMCSI 0xdd8
1193#define ROFDM_SIGReport 0xddc
1194
1195/* 8. PageE(0xE00) */
1196#define RTXAGC_A_RATE18_06 0xe00
1197#define RTXAGC_A_RATE54_24 0xe04
1198#define RTXAGC_A_CCK1_MCS32 0xe08
1199#define RTXAGC_A_MCS03_MCS00 0xe10
1200#define RTXAGC_A_MCS07_MCS04 0xe14
1201#define RTXAGC_A_MCS11_MCS08 0xe18
1202#define RTXAGC_A_MCS15_MCS12 0xe1c
1203
1204#define RTXAGC_B_RATE18_06 0x830
1205#define RTXAGC_B_RATE54_24 0x834
1206#define RTXAGC_B_CCK1_55_MCS32 0x838
1207#define RTXAGC_B_MCS03_MCS00 0x83c
1208#define RTXAGC_B_MCS07_MCS04 0x848
1209#define RTXAGC_B_MCS11_MCS08 0x84c
1210#define RTXAGC_B_MCS15_MCS12 0x868
1211#define RTXAGC_B_CCK11_A_CCK2_11 0x86c
1212
1213/* RL6052 Register definition */
1214#define RF_AC 0x00
1215
1216#define RF_IQADJ_G1 0x01
1217#define RF_IQADJ_G2 0x02
1218#define RF_POW_TRSW 0x05
1219
1220#define RF_GAIN_RX 0x06
1221#define RF_GAIN_TX 0x07
1222
1223#define RF_TXM_IDAC 0x08
1224#define RF_BS_IQGEN 0x0F
1225
1226#define RF_MODE1 0x10
1227#define RF_MODE2 0x11
1228
1229#define RF_RX_AGC_HP 0x12
1230#define RF_TX_AGC 0x13
1231#define RF_BIAS 0x14
1232#define RF_IPA 0x15
1233#define RF_POW_ABILITY 0x17
1234#define RF_MODE_AG 0x18
1235#define rRfChannel 0x18
1236#define RF_CHNLBW 0x18
1237#define RF_TOP 0x19
1238
1239#define RF_RX_G1 0x1A
1240#define RF_RX_G2 0x1B
1241
1242#define RF_RX_BB2 0x1C
1243#define RF_RX_BB1 0x1D
1244
1245#define RF_RCK1 0x1E
1246#define RF_RCK2 0x1F
1247
1248#define RF_TX_G1 0x20
1249#define RF_TX_G2 0x21
1250#define RF_TX_G3 0x22
1251
1252#define RF_TX_BB1 0x23
1253
1254#define RF_T_METER 0x42
1255
1256#define RF_SYN_G1 0x25
1257#define RF_SYN_G2 0x26
1258#define RF_SYN_G3 0x27
1259#define RF_SYN_G4 0x28
1260#define RF_SYN_G5 0x29
1261#define RF_SYN_G6 0x2A
1262#define RF_SYN_G7 0x2B
1263#define RF_SYN_G8 0x2C
1264
1265#define RF_RCK_OS 0x30
1266
1267#define RF_TXPA_G1 0x31
1268#define RF_TXPA_G2 0x32
1269#define RF_TXPA_G3 0x33
1270
1271/* Bit Mask */
1272
1273/* 2. Page8(0x800) */
1274#define BRFMOD 0x1
1275#define BCCKTXSC 0x30
1276#define BCCKEN 0x1000000
1277#define BOFDMEN 0x2000000
1278
1279#define B3WIREDATALENGTH 0x800
1280#define B3WIREADDRESSLENGTH 0x400
1281
1282#define BRFSI_RFENV 0x10
1283
1284#define BLSSIREADADDRESS 0x7f800000
1285#define BLSSIREADEDGE 0x80000000
1286#define BLSSIREADBACKDATA 0xfffff
1287/* 4. PageA(0xA00) */
1288#define BCCKSIDEBAND 0x10
1289
1290/* Other Definition */
1291#define BBYTE0 0x1
1292#define BBYTE1 0x2
1293#define BBYTE2 0x4
1294#define BBYTE3 0x8
1295#define BWORD0 0x3
1296#define BWORD1 0xc
1297#define BDWORD 0xf
1298
1299#define BMASKBYTE0 0xff
1300#define BMASKBYTE1 0xff00
1301#define BMASKBYTE2 0xff0000
1302#define BMASKBYTE3 0xff000000
1303#define BMASKHWORD 0xffff0000
1304#define BMASKLWORD 0x0000ffff
1305#define BMASKDWORD 0xffffffff
1306#define BMASK12BITS 0xfff
1307#define BMASKH4BITS 0xf0000000
1308#define BMASKOFDM_D 0xffc00000
1309#define BMASKCCK 0x3f3f3f3f
1310
1311#define BRFREGOFFSETMASK 0xfffff
1312
1313#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/rf.c b/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
new file mode 100644
index 000000000000..db27cebaac2c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/rf.c
@@ -0,0 +1,628 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "reg.h"
32#include "def.h"
33#include "phy.h"
34#include "rf.h"
35#include "dm.h"
36#include "hw.h"
37
38void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
39{
40 struct rtl_priv *rtlpriv = rtl_priv(hw);
41 struct rtl_phy *rtlphy = &(rtlpriv->phy);
42 u8 rfpath;
43
44 switch (bandwidth) {
45 case HT_CHANNEL_WIDTH_20:
46 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
47 rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval
48 [rfpath] & 0xfffff3ff) | 0x0400);
49 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) |
50 BIT(11), 0x01);
51
52 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
53 ("20M RF 0x18 = 0x%x\n",
54 rtlphy->rfreg_chnlval[rfpath]));
55 }
56
57 break;
58 case HT_CHANNEL_WIDTH_20_40:
59 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
60 rtlphy->rfreg_chnlval[rfpath] =
61 ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff));
62 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11),
63 0x00);
64 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
65 ("40M RF 0x18 = 0x%x\n",
66 rtlphy->rfreg_chnlval[rfpath]));
67 }
68 break;
69 default:
70 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
71 ("unknown bandwidth: %#X\n", bandwidth));
72 break;
73 }
74}
75
76void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
77 u8 *ppowerlevel)
78{
79 struct rtl_priv *rtlpriv = rtl_priv(hw);
80 struct rtl_phy *rtlphy = &(rtlpriv->phy);
81 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
82 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
83 u32 tx_agc[2] = {0, 0}, tmpval;
84 bool turbo_scanoff = false;
85 u8 idx1, idx2;
86 u8 *ptr;
87
88 if (rtlefuse->eeprom_regulatory != 0)
89 turbo_scanoff = true;
90 if (mac->act_scanning) {
91 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
92 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
93 if (turbo_scanoff) {
94 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
95 tx_agc[idx1] = ppowerlevel[idx1] |
96 (ppowerlevel[idx1] << 8) |
97 (ppowerlevel[idx1] << 16) |
98 (ppowerlevel[idx1] << 24);
99 }
100 }
101 } else {
102 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
103 tx_agc[idx1] = ppowerlevel[idx1] |
104 (ppowerlevel[idx1] << 8) |
105 (ppowerlevel[idx1] << 16) |
106 (ppowerlevel[idx1] << 24);
107 }
108 if (rtlefuse->eeprom_regulatory == 0) {
109 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
110 (rtlphy->mcs_txpwrlevel_origoffset[0][7] << 8);
111 tx_agc[RF90_PATH_A] += tmpval;
112 tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
113 (rtlphy->mcs_txpwrlevel_origoffset[0][15] << 24);
114 tx_agc[RF90_PATH_B] += tmpval;
115 }
116 }
117
118 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
119 ptr = (u8 *) (&(tx_agc[idx1]));
120 for (idx2 = 0; idx2 < 4; idx2++) {
121 if (*ptr > RF6052_MAX_TX_PWR)
122 *ptr = RF6052_MAX_TX_PWR;
123 ptr++;
124 }
125 }
126
127 tmpval = tx_agc[RF90_PATH_A] & 0xff;
128 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, BMASKBYTE1, tmpval);
129 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
130 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
131 RTXAGC_A_CCK1_MCS32));
132 tmpval = tx_agc[RF90_PATH_A] >> 8;
133 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
134 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
135 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
136 RTXAGC_B_CCK11_A_CCK2_11));
137 tmpval = tx_agc[RF90_PATH_B] >> 24;
138 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, BMASKBYTE0, tmpval);
139 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
140 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
141 RTXAGC_B_CCK11_A_CCK2_11));
142 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
143 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
144 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
145 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
146 RTXAGC_B_CCK1_55_MCS32));
147}
148
149static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw,
150 u8 *ppowerlevel, u8 channel,
151 u32 *ofdmbase, u32 *mcsbase)
152{
153 struct rtl_priv *rtlpriv = rtl_priv(hw);
154 struct rtl_phy *rtlphy = &(rtlpriv->phy);
155 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
156 u32 powerbase0, powerbase1;
157 u8 legacy_pwrdiff, ht20_pwrdiff;
158 u8 i, powerlevel[2];
159
160 for (i = 0; i < 2; i++) {
161 powerlevel[i] = ppowerlevel[i];
162 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
163 powerbase0 = powerlevel[i] + legacy_pwrdiff;
164 powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
165 (powerbase0 << 8) | powerbase0;
166 *(ofdmbase + i) = powerbase0;
167 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
168 (" [OFDM power base index rf(%c) = 0x%x]\n",
169 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
170 }
171
172 for (i = 0; i < 2; i++) {
173 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
174 ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
175 powerlevel[i] += ht20_pwrdiff;
176 }
177 powerbase1 = powerlevel[i];
178 powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
179 (powerbase1 << 8) | powerbase1;
180 *(mcsbase + i) = powerbase1;
181 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
182 (" [MCS power base index rf(%c) = 0x%x]\n",
183 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
184 }
185}
186
187static u8 _rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex)
188{
189 u8 group;
190 u8 channel_info[59] = {
191 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
192 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
193 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
194 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
195 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
196 161, 163, 165
197 };
198
199 if (channel_info[chnlindex] <= 3) /* Chanel 1-3 */
200 group = 0;
201 else if (channel_info[chnlindex] <= 9) /* Channel 4-9 */
202 group = 1;
203 else if (channel_info[chnlindex] <= 14) /* Channel 10-14 */
204 group = 2;
205 else if (channel_info[chnlindex] <= 64)
206 group = 6;
207 else if (channel_info[chnlindex] <= 140)
208 group = 7;
209 else
210 group = 8;
211 return group;
212}
213
214static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
215 u8 channel, u8 index,
216 u32 *powerbase0,
217 u32 *powerbase1,
218 u32 *p_outwriteval)
219{
220 struct rtl_priv *rtlpriv = rtl_priv(hw);
221 struct rtl_phy *rtlphy = &(rtlpriv->phy);
222 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
223 u8 i, chnlgroup = 0, pwr_diff_limit[4];
224 u32 writeval = 0, customer_limit, rf;
225
226 for (rf = 0; rf < 2; rf++) {
227 switch (rtlefuse->eeprom_regulatory) {
228 case 0:
229 chnlgroup = 0;
230 writeval = rtlphy->mcs_txpwrlevel_origoffset
231 [chnlgroup][index +
232 (rf ? 8 : 0)] + ((index < 2) ?
233 powerbase0[rf] :
234 powerbase1[rf]);
235 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("RTK better "
236 "performance, writeval(%c) = 0x%x\n",
237 ((rf == 0) ? 'A' : 'B'), writeval));
238 break;
239 case 1:
240 if (rtlphy->pwrgroup_cnt == 1)
241 chnlgroup = 0;
242 if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) {
243 chnlgroup = _rtl92d_phy_get_chnlgroup_bypg(
244 channel - 1);
245 if (rtlphy->current_chan_bw ==
246 HT_CHANNEL_WIDTH_20)
247 chnlgroup++;
248 else
249 chnlgroup += 4;
250 writeval = rtlphy->mcs_txpwrlevel_origoffset
251 [chnlgroup][index +
252 (rf ? 8 : 0)] + ((index < 2) ?
253 powerbase0[rf] :
254 powerbase1[rf]);
255 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
256 ("Realtek regulatory, "
257 "20MHz, writeval(%c) = 0x%x\n",
258 ((rf == 0) ? 'A' : 'B'),
259 writeval));
260 }
261 break;
262 case 2:
263 writeval = ((index < 2) ? powerbase0[rf] :
264 powerbase1[rf]);
265 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("Better regulatory, "
266 "writeval(%c) = 0x%x\n",
267 ((rf == 0) ? 'A' : 'B'), writeval));
268 break;
269 case 3:
270 chnlgroup = 0;
271 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
272 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
273 ("customer's limit, 40MHz rf(%c) = "
274 "0x%x\n", ((rf == 0) ? 'A' : 'B'),
275 rtlefuse->pwrgroup_ht40[rf]
276 [channel - 1]));
277 } else {
278 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
279 ("customer's limit, 20MHz rf(%c) = "
280 "0x%x\n", ((rf == 0) ? 'A' : 'B'),
281 rtlefuse->pwrgroup_ht20[rf]
282 [channel - 1]));
283 }
284 for (i = 0; i < 4; i++) {
285 pwr_diff_limit[i] =
286 (u8)((rtlphy->mcs_txpwrlevel_origoffset
287 [chnlgroup][index + (rf ? 8 : 0)] &
288 (0x7f << (i * 8))) >> (i * 8));
289 if (rtlphy->current_chan_bw ==
290 HT_CHANNEL_WIDTH_20_40) {
291 if (pwr_diff_limit[i] >
292 rtlefuse->pwrgroup_ht40[rf]
293 [channel - 1])
294 pwr_diff_limit[i] =
295 rtlefuse->pwrgroup_ht40
296 [rf][channel - 1];
297 } else {
298 if (pwr_diff_limit[i] >
299 rtlefuse->pwrgroup_ht20[rf][
300 channel - 1])
301 pwr_diff_limit[i] =
302 rtlefuse->pwrgroup_ht20[rf]
303 [channel - 1];
304 }
305 }
306 customer_limit = (pwr_diff_limit[3] << 24) |
307 (pwr_diff_limit[2] << 16) |
308 (pwr_diff_limit[1] << 8) |
309 (pwr_diff_limit[0]);
310 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
311 ("Customer's limit rf(%c) = 0x%x\n",
312 ((rf == 0) ? 'A' : 'B'), customer_limit));
313 writeval = customer_limit + ((index < 2) ?
314 powerbase0[rf] : powerbase1[rf]);
315 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
316 ("Customer, writeval rf(%c)= 0x%x\n",
317 ((rf == 0) ? 'A' : 'B'), writeval));
318 break;
319 default:
320 chnlgroup = 0;
321 writeval = rtlphy->mcs_txpwrlevel_origoffset
322 [chnlgroup][index +
323 (rf ? 8 : 0)] + ((index < 2) ?
324 powerbase0[rf] : powerbase1[rf]);
325 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
326 ("RTK better performance, writeval "
327 "rf(%c) = 0x%x\n",
328 ((rf == 0) ? 'A' : 'B'), writeval));
329 break;
330 }
331 *(p_outwriteval + rf) = writeval;
332 }
333}
334
335static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw,
336 u8 index, u32 *pvalue)
337{
338 struct rtl_priv *rtlpriv = rtl_priv(hw);
339 struct rtl_phy *rtlphy = &(rtlpriv->phy);
340 static u16 regoffset_a[6] = {
341 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
342 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
343 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
344 };
345 static u16 regoffset_b[6] = {
346 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
347 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
348 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
349 };
350 u8 i, rf, pwr_val[4];
351 u32 writeval;
352 u16 regoffset;
353
354 for (rf = 0; rf < 2; rf++) {
355 writeval = pvalue[rf];
356 for (i = 0; i < 4; i++) {
357 pwr_val[i] = (u8) ((writeval & (0x7f <<
358 (i * 8))) >> (i * 8));
359 if (pwr_val[i] > RF6052_MAX_TX_PWR)
360 pwr_val[i] = RF6052_MAX_TX_PWR;
361 }
362 writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
363 (pwr_val[1] << 8) | pwr_val[0];
364 if (rf == 0)
365 regoffset = regoffset_a[index];
366 else
367 regoffset = regoffset_b[index];
368 rtl_set_bbreg(hw, regoffset, BMASKDWORD, writeval);
369 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
370 ("Set 0x%x = %08x\n", regoffset, writeval));
371 if (((get_rf_type(rtlphy) == RF_2T2R) &&
372 (regoffset == RTXAGC_A_MCS15_MCS12 ||
373 regoffset == RTXAGC_B_MCS15_MCS12)) ||
374 ((get_rf_type(rtlphy) != RF_2T2R) &&
375 (regoffset == RTXAGC_A_MCS07_MCS04 ||
376 regoffset == RTXAGC_B_MCS07_MCS04))) {
377 writeval = pwr_val[3];
378 if (regoffset == RTXAGC_A_MCS15_MCS12 ||
379 regoffset == RTXAGC_A_MCS07_MCS04)
380 regoffset = 0xc90;
381 if (regoffset == RTXAGC_B_MCS15_MCS12 ||
382 regoffset == RTXAGC_B_MCS07_MCS04)
383 regoffset = 0xc98;
384 for (i = 0; i < 3; i++) {
385 if (i != 2)
386 writeval = (writeval > 8) ?
387 (writeval - 8) : 0;
388 else
389 writeval = (writeval > 6) ?
390 (writeval - 6) : 0;
391 rtl_write_byte(rtlpriv, (u32) (regoffset + i),
392 (u8) writeval);
393 }
394 }
395 }
396}
397
398void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
399 u8 *ppowerlevel, u8 channel)
400{
401 u32 writeval[2], powerbase0[2], powerbase1[2];
402 u8 index;
403
404 _rtl92d_phy_get_power_base(hw, ppowerlevel, channel,
405 &powerbase0[0], &powerbase1[0]);
406 for (index = 0; index < 6; index++) {
407 _rtl92d_get_txpower_writeval_by_regulatory(hw,
408 channel, index, &powerbase0[0],
409 &powerbase1[0], &writeval[0]);
410 _rtl92d_write_ofdm_power_reg(hw, index, &writeval[0]);
411 }
412}
413
414bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0)
415{
416 struct rtl_priv *rtlpriv = rtl_priv(hw);
417 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
418 u8 u1btmp;
419 u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3);
420 u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0;
421 u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON;
422 bool bresult = true; /* true: need to enable BB/RF power */
423
424 rtlhal->during_mac0init_radiob = false;
425 rtlhal->during_mac1init_radioa = false;
426 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("===>\n"));
427 /* MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write. */
428 u1btmp = rtl_read_byte(rtlpriv, mac_reg);
429 if (!(u1btmp & mac_on_bit)) {
430 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable BB & RF\n"));
431 /* Enable BB and RF power */
432 rtl92de_write_dword_dbi(hw, REG_SYS_ISO_CTRL,
433 rtl92de_read_dword_dbi(hw, REG_SYS_ISO_CTRL, direct) |
434 BIT(29) | BIT(16) | BIT(17), direct);
435 } else {
436 /* We think if MAC1 is ON,then radio_a.txt
437 * and radio_b.txt has been load. */
438 bresult = false;
439 }
440 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<===\n"));
441 return bresult;
442
443}
444
445void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0)
446{
447 struct rtl_priv *rtlpriv = rtl_priv(hw);
448 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
449 u8 u1btmp;
450 u8 direct = bmac0 ? BIT(3) | BIT(2) : BIT(3);
451 u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0;
452 u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON;
453
454 rtlhal->during_mac0init_radiob = false;
455 rtlhal->during_mac1init_radioa = false;
456 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("====>\n"));
457 /* check MAC0 enable or not again now, if
458 * enabled, not power down radio A. */
459 u1btmp = rtl_read_byte(rtlpriv, mac_reg);
460 if (!(u1btmp & mac_on_bit)) {
461 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("power down\n"));
462 /* power down RF radio A according to YuNan's advice. */
463 rtl92de_write_dword_dbi(hw, RFPGA0_XA_LSSIPARAMETER,
464 0x00000000, direct);
465 }
466 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<====\n"));
467}
468
469bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw)
470{
471 struct rtl_priv *rtlpriv = rtl_priv(hw);
472 struct rtl_phy *rtlphy = &(rtlpriv->phy);
473 bool rtstatus = true;
474 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
475 u32 u4_regvalue = 0;
476 u8 rfpath;
477 struct bb_reg_def *pphyreg;
478 bool mac1_initradioa_first = false, mac0_initradiob_first = false;
479 bool need_pwrdown_radioa = false, need_pwrdown_radiob = false;
480 bool true_bpath = false;
481
482 if (rtlphy->rf_type == RF_1T1R)
483 rtlphy->num_total_rfpath = 1;
484 else
485 rtlphy->num_total_rfpath = 2;
486
487 /* Single phy mode: use radio_a radio_b config path_A path_B */
488 /* seperately by MAC0, and MAC1 needn't configure RF; */
489 /* Dual PHY mode:MAC0 use radio_a config 1st phy path_A, */
490 /* MAC1 use radio_b config 2nd PHY path_A. */
491 /* DMDP,MAC0 on G band,MAC1 on A band. */
492 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
493 if (rtlhal->current_bandtype == BAND_ON_2_4G &&
494 rtlhal->interfaceindex == 0) {
495 /* MAC0 needs PHY1 load radio_b.txt.
496 * Driver use DBI to write. */
497 if (rtl92d_phy_enable_anotherphy(hw, true)) {
498 rtlphy->num_total_rfpath = 2;
499 mac0_initradiob_first = true;
500 } else {
501 /* We think if MAC1 is ON,then radio_a.txt and
502 * radio_b.txt has been load. */
503 return rtstatus;
504 }
505 } else if (rtlhal->current_bandtype == BAND_ON_5G &&
506 rtlhal->interfaceindex == 1) {
507 /* MAC1 needs PHY0 load radio_a.txt.
508 * Driver use DBI to write. */
509 if (rtl92d_phy_enable_anotherphy(hw, false)) {
510 rtlphy->num_total_rfpath = 2;
511 mac1_initradioa_first = true;
512 } else {
513 /* We think if MAC0 is ON,then radio_a.txt and
514 * radio_b.txt has been load. */
515 return rtstatus;
516 }
517 } else if (rtlhal->interfaceindex == 1) {
518 /* MAC0 enabled, only init radia B. */
519 true_bpath = true;
520 }
521 }
522
523 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
524 /* Mac1 use PHY0 write */
525 if (mac1_initradioa_first) {
526 if (rfpath == RF90_PATH_A) {
527 rtlhal->during_mac1init_radioa = true;
528 need_pwrdown_radioa = true;
529 } else if (rfpath == RF90_PATH_B) {
530 rtlhal->during_mac1init_radioa = false;
531 mac1_initradioa_first = false;
532 rfpath = RF90_PATH_A;
533 true_bpath = true;
534 rtlphy->num_total_rfpath = 1;
535 }
536 } else if (mac0_initradiob_first) {
537 /* Mac0 use PHY1 write */
538 if (rfpath == RF90_PATH_A)
539 rtlhal->during_mac0init_radiob = false;
540 if (rfpath == RF90_PATH_B) {
541 rtlhal->during_mac0init_radiob = true;
542 mac0_initradiob_first = false;
543 need_pwrdown_radiob = true;
544 rfpath = RF90_PATH_A;
545 true_bpath = true;
546 rtlphy->num_total_rfpath = 1;
547 }
548 }
549 pphyreg = &rtlphy->phyreg_def[rfpath];
550 switch (rfpath) {
551 case RF90_PATH_A:
552 case RF90_PATH_C:
553 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
554 BRFSI_RFENV);
555 break;
556 case RF90_PATH_B:
557 case RF90_PATH_D:
558 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
559 BRFSI_RFENV << 16);
560 break;
561 }
562 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
563 udelay(1);
564 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
565 udelay(1);
566 /* Set bit number of Address and Data for RF register */
567 /* Set 1 to 4 bits for 8255 */
568 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
569 B3WIREADDRESSLENGTH, 0x0);
570 udelay(1);
571 /* Set 0 to 12 bits for 8255 */
572 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
573 udelay(1);
574 switch (rfpath) {
575 case RF90_PATH_A:
576 if (true_bpath)
577 rtstatus = rtl92d_phy_config_rf_with_headerfile(
578 hw, radiob_txt,
579 (enum radio_path)rfpath);
580 else
581 rtstatus = rtl92d_phy_config_rf_with_headerfile(
582 hw, radioa_txt,
583 (enum radio_path)rfpath);
584 break;
585 case RF90_PATH_B:
586 rtstatus =
587 rtl92d_phy_config_rf_with_headerfile(hw, radiob_txt,
588 (enum radio_path) rfpath);
589 break;
590 case RF90_PATH_C:
591 break;
592 case RF90_PATH_D:
593 break;
594 }
595 switch (rfpath) {
596 case RF90_PATH_A:
597 case RF90_PATH_C:
598 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV,
599 u4_regvalue);
600 break;
601 case RF90_PATH_B:
602 case RF90_PATH_D:
603 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
604 u4_regvalue);
605 break;
606 }
607 if (rtstatus != true) {
608 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
609 ("Radio[%d] Fail!!", rfpath));
610 goto phy_rf_cfg_fail;
611 }
612
613 }
614
615 /* check MAC0 enable or not again, if enabled,
616 * not power down radio A. */
617 /* check MAC1 enable or not again, if enabled,
618 * not power down radio B. */
619 if (need_pwrdown_radioa)
620 rtl92d_phy_powerdown_anotherphy(hw, false);
621 else if (need_pwrdown_radiob)
622 rtl92d_phy_powerdown_anotherphy(hw, true);
623 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
624 return rtstatus;
625
626phy_rf_cfg_fail:
627 return rtstatus;
628}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/rf.h b/drivers/net/wireless/rtlwifi/rtl8192de/rf.h
new file mode 100644
index 000000000000..74b9cfc39a83
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/rf.h
@@ -0,0 +1,44 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92D_RF_H__
31#define __RTL92D_RF_H__
32
33extern void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
34 u8 bandwidth);
35extern void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
36 u8 *ppowerlevel);
37extern void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
38 u8 *ppowerlevel, u8 channel);
39extern bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw);
40extern bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0);
41extern void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw,
42 bool bmac0);
43
44#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/rtlwifi/rtl8192de/sw.c
new file mode 100644
index 000000000000..351765df517d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/sw.c
@@ -0,0 +1,423 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32#include <linux/vmalloc.h>
33
34#include "../wifi.h"
35#include "../core.h"
36#include "../pci.h"
37#include "reg.h"
38#include "def.h"
39#include "phy.h"
40#include "dm.h"
41#include "hw.h"
42#include "sw.h"
43#include "trx.h"
44#include "led.h"
45
46static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
47{
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
49
50 /*close ASPM for AMD defaultly */
51 rtlpci->const_amdpci_aspm = 0;
52
53 /*
54 * ASPM PS mode.
55 * 0 - Disable ASPM,
56 * 1 - Enable ASPM without Clock Req,
57 * 2 - Enable ASPM with Clock Req,
58 * 3 - Alwyas Enable ASPM with Clock Req,
59 * 4 - Always Enable ASPM without Clock Req.
60 * set defult to RTL8192CE:3 RTL8192E:2
61 * */
62 rtlpci->const_pci_aspm = 3;
63
64 /*Setting for PCI-E device */
65 rtlpci->const_devicepci_aspm_setting = 0x03;
66
67 /*Setting for PCI-E bridge */
68 rtlpci->const_hostpci_aspm_setting = 0x02;
69
70 /*
71 * In Hw/Sw Radio Off situation.
72 * 0 - Default,
73 * 1 - From ASPM setting without low Mac Pwr,
74 * 2 - From ASPM setting with low Mac Pwr,
75 * 3 - Bus D3
76 * set default to RTL8192CE:0 RTL8192SE:2
77 */
78 rtlpci->const_hwsw_rfoff_d3 = 0;
79
80 /*
81 * This setting works for those device with
82 * backdoor ASPM setting such as EPHY setting.
83 * 0 - Not support ASPM,
84 * 1 - Support ASPM,
85 * 2 - According to chipset.
86 */
87 rtlpci->const_support_pciaspm = 1;
88}
89
90static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
91{
92 int err;
93 u8 tid;
94 struct rtl_priv *rtlpriv = rtl_priv(hw);
95 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
96 const struct firmware *firmware;
97 static int header_print;
98
99 rtlpriv->dm.dm_initialgain_enable = true;
100 rtlpriv->dm.dm_flag = 0;
101 rtlpriv->dm.disable_framebursting = 0;
102 rtlpriv->dm.thermalvalue = 0;
103 rtlpriv->dm.useramask = 1;
104
105 /* dual mac */
106 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
107 rtlpriv->phy.current_channel = 36;
108 else
109 rtlpriv->phy.current_channel = 1;
110
111 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
112 rtlpriv->rtlhal.disable_amsdu_8k = true;
113 /* No long RX - reduce fragmentation */
114 rtlpci->rxbuffersize = 4096;
115 }
116
117 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
118
119 rtlpci->receive_config = (
120 RCR_APPFCS
121 | RCR_AMF
122 | RCR_ADF
123 | RCR_APP_MIC
124 | RCR_APP_ICV
125 | RCR_AICV
126 | RCR_ACRC32
127 | RCR_AB
128 | RCR_AM
129 | RCR_APM
130 | RCR_APP_PHYST_RXFF
131 | RCR_HTC_LOC_CTRL
132 );
133
134 rtlpci->irq_mask[0] = (u32) (
135 IMR_ROK
136 | IMR_VODOK
137 | IMR_VIDOK
138 | IMR_BEDOK
139 | IMR_BKDOK
140 | IMR_MGNTDOK
141 | IMR_HIGHDOK
142 | IMR_BDOK
143 | IMR_RDU
144 | IMR_RXFOVW
145 );
146
147 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
148
149 /* for LPS & IPS */
150 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
151 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
152 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
153 rtlpriv->psc.reg_fwctrl_lps = 3;
154 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
155 /* for ASPM, you can close aspm through
156 * set const_support_pciaspm = 0 */
157 rtl92d_init_aspm_vars(hw);
158
159 if (rtlpriv->psc.reg_fwctrl_lps == 1)
160 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
161 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
162 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
163 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
164 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
165
166 /* for firmware buf */
167 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
168 if (!rtlpriv->rtlhal.pfirmware) {
169 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
170 ("Can't alloc buffer for fw.\n"));
171 return 1;
172 }
173
174 if (!header_print) {
175 pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
176 pr_info("Loading firmware file %s\n", rtlpriv->cfg->fw_name);
177 header_print++;
178 }
179 /* request fw */
180 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
181 rtlpriv->io.dev);
182 if (err) {
183 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
184 ("Failed to request firmware!\n"));
185 return 1;
186 }
187 if (firmware->size > 0x8000) {
188 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
189 ("Firmware is too big!\n"));
190 release_firmware(firmware);
191 return 1;
192 }
193 memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
194 rtlpriv->rtlhal.fwsize = firmware->size;
195 release_firmware(firmware);
196
197 /* for early mode */
198 rtlpriv->rtlhal.earlymode_enable = true;
199 for (tid = 0; tid < 8; tid++)
200 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
201 return 0;
202}
203
204static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
205{
206 struct rtl_priv *rtlpriv = rtl_priv(hw);
207 u8 tid;
208
209 if (rtlpriv->rtlhal.pfirmware) {
210 vfree(rtlpriv->rtlhal.pfirmware);
211 rtlpriv->rtlhal.pfirmware = NULL;
212 }
213 for (tid = 0; tid < 8; tid++)
214 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
215}
216
217static struct rtl_hal_ops rtl8192de_hal_ops = {
218 .init_sw_vars = rtl92d_init_sw_vars,
219 .deinit_sw_vars = rtl92d_deinit_sw_vars,
220 .read_eeprom_info = rtl92de_read_eeprom_info,
221 .interrupt_recognized = rtl92de_interrupt_recognized,
222 .hw_init = rtl92de_hw_init,
223 .hw_disable = rtl92de_card_disable,
224 .hw_suspend = rtl92de_suspend,
225 .hw_resume = rtl92de_resume,
226 .enable_interrupt = rtl92de_enable_interrupt,
227 .disable_interrupt = rtl92de_disable_interrupt,
228 .set_network_type = rtl92de_set_network_type,
229 .set_chk_bssid = rtl92de_set_check_bssid,
230 .set_qos = rtl92de_set_qos,
231 .set_bcn_reg = rtl92de_set_beacon_related_registers,
232 .set_bcn_intv = rtl92de_set_beacon_interval,
233 .update_interrupt_mask = rtl92de_update_interrupt_mask,
234 .get_hw_reg = rtl92de_get_hw_reg,
235 .set_hw_reg = rtl92de_set_hw_reg,
236 .update_rate_tbl = rtl92de_update_hal_rate_tbl,
237 .fill_tx_desc = rtl92de_tx_fill_desc,
238 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
239 .query_rx_desc = rtl92de_rx_query_desc,
240 .set_channel_access = rtl92de_update_channel_access_setting,
241 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
242 .set_bw_mode = rtl92d_phy_set_bw_mode,
243 .switch_channel = rtl92d_phy_sw_chnl,
244 .dm_watchdog = rtl92d_dm_watchdog,
245 .scan_operation_backup = rtl92d_phy_scan_operation_backup,
246 .set_rf_power_state = rtl92d_phy_set_rf_power_state,
247 .led_control = rtl92de_led_control,
248 .set_desc = rtl92de_set_desc,
249 .get_desc = rtl92de_get_desc,
250 .tx_polling = rtl92de_tx_polling,
251 .enable_hw_sec = rtl92de_enable_hw_security_config,
252 .set_key = rtl92de_set_key,
253 .init_sw_leds = rtl92de_init_sw_leds,
254 .get_bbreg = rtl92d_phy_query_bb_reg,
255 .set_bbreg = rtl92d_phy_set_bb_reg,
256 .get_rfreg = rtl92d_phy_query_rf_reg,
257 .set_rfreg = rtl92d_phy_set_rf_reg,
258 .linked_set_reg = rtl92d_linked_set_reg,
259};
260
261static struct rtl_mod_params rtl92de_mod_params = {
262 .sw_crypto = false,
263 .inactiveps = true,
264 .swctrl_lps = true,
265 .fwctrl_lps = false,
266};
267
268static struct rtl_hal_cfg rtl92de_hal_cfg = {
269 .bar_id = 2,
270 .write_readback = true,
271 .name = "rtl8192de",
272 .fw_name = "rtlwifi/rtl8192defw.bin",
273 .ops = &rtl8192de_hal_ops,
274 .mod_params = &rtl92de_mod_params,
275
276 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
277 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
278 .maps[SYS_CLK] = REG_SYS_CLKR,
279 .maps[MAC_RCR_AM] = RCR_AM,
280 .maps[MAC_RCR_AB] = RCR_AB,
281 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
282 .maps[MAC_RCR_ACF] = RCR_ACF,
283 .maps[MAC_RCR_AAP] = RCR_AAP,
284
285 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
286 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
287 .maps[EFUSE_CLK] = 0, /* just for 92se */
288 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
289 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
290 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
291 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
292 .maps[EFUSE_ANA8M] = 0, /* just for 92se */
293 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
294 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
295 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
296
297 .maps[RWCAM] = REG_CAMCMD,
298 .maps[WCAMI] = REG_CAMWRITE,
299 .maps[RCAMO] = REG_CAMREAD,
300 .maps[CAMDBG] = REG_CAMDBG,
301 .maps[SECR] = REG_SECCFG,
302 .maps[SEC_CAM_NONE] = CAM_NONE,
303 .maps[SEC_CAM_WEP40] = CAM_WEP40,
304 .maps[SEC_CAM_TKIP] = CAM_TKIP,
305 .maps[SEC_CAM_AES] = CAM_AES,
306 .maps[SEC_CAM_WEP104] = CAM_WEP104,
307
308 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
309 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
310 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
311 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
312 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
313 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
314 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
315 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
316 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
317 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
318 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
319 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
320 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
321 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
322 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
323 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
324
325 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
326 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
327 .maps[RTL_IMR_BcnInt] = IMR_BcnInt,
328 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
329 .maps[RTL_IMR_RDU] = IMR_RDU,
330 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
331 .maps[RTL_IMR_BDOK] = IMR_BDOK,
332 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
333 .maps[RTL_IMR_TBDER] = IMR_TBDER,
334 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
335 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
336 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
337 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
338 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
339 .maps[RTL_IMR_VODOK] = IMR_VODOK,
340 .maps[RTL_IMR_ROK] = IMR_ROK,
341 .maps[RTL_IBSS_INT_MASKS] = (IMR_BcnInt | IMR_TBDOK | IMR_TBDER),
342
343 .maps[RTL_RC_CCK_RATE1M] = DESC92D_RATE1M,
344 .maps[RTL_RC_CCK_RATE2M] = DESC92D_RATE2M,
345 .maps[RTL_RC_CCK_RATE5_5M] = DESC92D_RATE5_5M,
346 .maps[RTL_RC_CCK_RATE11M] = DESC92D_RATE11M,
347 .maps[RTL_RC_OFDM_RATE6M] = DESC92D_RATE6M,
348 .maps[RTL_RC_OFDM_RATE9M] = DESC92D_RATE9M,
349 .maps[RTL_RC_OFDM_RATE12M] = DESC92D_RATE12M,
350 .maps[RTL_RC_OFDM_RATE18M] = DESC92D_RATE18M,
351 .maps[RTL_RC_OFDM_RATE24M] = DESC92D_RATE24M,
352 .maps[RTL_RC_OFDM_RATE36M] = DESC92D_RATE36M,
353 .maps[RTL_RC_OFDM_RATE48M] = DESC92D_RATE48M,
354 .maps[RTL_RC_OFDM_RATE54M] = DESC92D_RATE54M,
355
356 .maps[RTL_RC_HT_RATEMCS7] = DESC92D_RATEMCS7,
357 .maps[RTL_RC_HT_RATEMCS15] = DESC92D_RATEMCS15,
358};
359
360static struct pci_device_id rtl92de_pci_ids[] __devinitdata = {
361 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
362 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
363 {},
364};
365
366MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
367
368MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
369MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
370MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
371MODULE_LICENSE("GPL");
372MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
373MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
374
375module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
376module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
377module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
378module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
379MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
380MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
381MODULE_PARM_DESC(swlps, "using linked sw control power save (default 1"
382 " is open)\n");
383
384static struct pci_driver rtl92de_driver = {
385 .name = KBUILD_MODNAME,
386 .id_table = rtl92de_pci_ids,
387 .probe = rtl_pci_probe,
388 .remove = rtl_pci_disconnect,
389
390#ifdef CONFIG_PM
391 .suspend = rtl_pci_suspend,
392 .resume = rtl_pci_resume,
393#endif
394
395};
396
397/* add global spin lock to solve the problem that
398 * Dul mac register operation on the same time */
399spinlock_t globalmutex_power;
400spinlock_t globalmutex_for_fwdownload;
401spinlock_t globalmutex_for_power_and_efuse;
402
403static int __init rtl92de_module_init(void)
404{
405 int ret = 0;
406
407 spin_lock_init(&globalmutex_power);
408 spin_lock_init(&globalmutex_for_fwdownload);
409 spin_lock_init(&globalmutex_for_power_and_efuse);
410
411 ret = pci_register_driver(&rtl92de_driver);
412 if (ret)
413 RT_ASSERT(false, (": No device found\n"));
414 return ret;
415}
416
417static void __exit rtl92de_module_exit(void)
418{
419 pci_unregister_driver(&rtl92de_driver);
420}
421
422module_init(rtl92de_module_init);
423module_exit(rtl92de_module_exit);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/sw.h b/drivers/net/wireless/rtlwifi/rtl8192de/sw.h
new file mode 100644
index 000000000000..c95e47de1346
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/sw.h
@@ -0,0 +1,37 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92DE_SW_H__
31#define __RTL92DE_SW_H__
32
33extern spinlock_t globalmutex_power;
34extern spinlock_t globalmutex_for_fwdownload;
35extern spinlock_t globalmutex_for_power_and_efuse;
36
37#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/table.c b/drivers/net/wireless/rtlwifi/rtl8192de/table.c
new file mode 100644
index 000000000000..bad7f9449ecf
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/table.c
@@ -0,0 +1,1690 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 * Created on 2010/12/23, 6:38
29 *****************************************************************************/
30
31#include <linux/types.h>
32
33#include "table.h"
34
35u32 rtl8192de_phy_reg_2tarray[PHY_REG_2T_ARRAYLENGTH] = {
36 0x024, 0x0011800d,
37 0x028, 0x00ffdb83,
38 0x014, 0x088ba955,
39 0x010, 0x49022b03,
40 0x800, 0x80040002,
41 0x804, 0x00000003,
42 0x808, 0x0000fc00,
43 0x80c, 0x0000000a,
44 0x810, 0x80706388,
45 0x814, 0x020c3d10,
46 0x818, 0x02200385,
47 0x81c, 0x00000000,
48 0x820, 0x01000100,
49 0x824, 0x00390004,
50 0x828, 0x01000100,
51 0x82c, 0x00390004,
52 0x830, 0x27272727,
53 0x834, 0x27272727,
54 0x838, 0x27272727,
55 0x83c, 0x27272727,
56 0x840, 0x00010000,
57 0x844, 0x00010000,
58 0x848, 0x27272727,
59 0x84c, 0x27272727,
60 0x850, 0x00000000,
61 0x854, 0x00000000,
62 0x858, 0x569a569a,
63 0x85c, 0x0c1b25a4,
64 0x860, 0x66e60230,
65 0x864, 0x061f0130,
66 0x868, 0x27272727,
67 0x86c, 0x272b2b2b,
68 0x870, 0x07000700,
69 0x874, 0x22188000,
70 0x878, 0x08080808,
71 0x87c, 0x00007ff8,
72 0x880, 0xc0083070,
73 0x884, 0x00000cd5,
74 0x888, 0x00000000,
75 0x88c, 0xcc0000c0,
76 0x890, 0x00000800,
77 0x894, 0xfffffffe,
78 0x898, 0x40302010,
79 0x89c, 0x00706050,
80 0x900, 0x00000000,
81 0x904, 0x00000023,
82 0x908, 0x00000000,
83 0x90c, 0x81121313,
84 0xa00, 0x00d047c8,
85 0xa04, 0x80ff000c,
86 0xa08, 0x8c838300,
87 0xa0c, 0x2e68120f,
88 0xa10, 0x9500bb78,
89 0xa14, 0x11144028,
90 0xa18, 0x00881117,
91 0xa1c, 0x89140f00,
92 0xa20, 0x1a1b0000,
93 0xa24, 0x090e1317,
94 0xa28, 0x00000204,
95 0xa2c, 0x00d30000,
96 0xa70, 0x101fbf00,
97 0xa74, 0x00000007,
98 0xc00, 0x40071d40,
99 0xc04, 0x03a05633,
100 0xc08, 0x001000e4,
101 0xc0c, 0x6c6c6c6c,
102 0xc10, 0x08800000,
103 0xc14, 0x40000100,
104 0xc18, 0x08800000,
105 0xc1c, 0x40000100,
106 0xc20, 0x00000000,
107 0xc24, 0x00000000,
108 0xc28, 0x00000000,
109 0xc2c, 0x00000000,
110 0xc30, 0x69e9ac44,
111 0xc34, 0x469652cf,
112 0xc38, 0x49795994,
113 0xc3c, 0x0a979718,
114 0xc40, 0x1f7c403f,
115 0xc44, 0x000100b7,
116 0xc48, 0xec020107,
117 0xc4c, 0x007f037f,
118 0xc50, 0x69543420,
119 0xc54, 0x43bc009e,
120 0xc58, 0x69543420,
121 0xc5c, 0x433c00a8,
122 0xc60, 0x00000000,
123 0xc64, 0x5116848b,
124 0xc68, 0x47c00bff,
125 0xc6c, 0x00000036,
126 0xc70, 0x2c7f000d,
127 0xc74, 0x058610db,
128 0xc78, 0x0000001f,
129 0xc7c, 0x40b95612,
130 0xc80, 0x40000100,
131 0xc84, 0x20f60000,
132 0xc88, 0x40000100,
133 0xc8c, 0x20e00000,
134 0xc90, 0x00121820,
135 0xc94, 0x00000007,
136 0xc98, 0x00121820,
137 0xc9c, 0x00007f7f,
138 0xca0, 0x00000000,
139 0xca4, 0x00000080,
140 0xca8, 0x00000000,
141 0xcac, 0x00000000,
142 0xcb0, 0x00000000,
143 0xcb4, 0x00000000,
144 0xcb8, 0x00000000,
145 0xcbc, 0x28000000,
146 0xcc0, 0x00000000,
147 0xcc4, 0x00000000,
148 0xcc8, 0x00000000,
149 0xccc, 0x00000000,
150 0xcd0, 0x00000000,
151 0xcd4, 0x00000000,
152 0xcd8, 0x64b11e20,
153 0xcdc, 0xe8767533,
154 0xce0, 0x00222222,
155 0xce4, 0x00000000,
156 0xce8, 0x37644302,
157 0xcec, 0x2f97d40c,
158 0xd00, 0x00080740,
159 0xd04, 0x00020403,
160 0xd08, 0x0000907f,
161 0xd0c, 0x20010201,
162 0xd10, 0xa0633333,
163 0xd14, 0x3333bc43,
164 0xd18, 0x7a8f5b6b,
165 0xd2c, 0xcc979975,
166 0xd30, 0x00000000,
167 0xd34, 0x80608404,
168 0xd38, 0x00000000,
169 0xd3c, 0x00027293,
170 0xd40, 0x00000000,
171 0xd44, 0x00000000,
172 0xd48, 0x00000000,
173 0xd4c, 0x00000000,
174 0xd50, 0x6437140a,
175 0xd54, 0x00000000,
176 0xd58, 0x00000000,
177 0xd5c, 0x30032064,
178 0xd60, 0x4653de68,
179 0xd64, 0x04518a3c,
180 0xd68, 0x00002101,
181 0xd6c, 0x2a201c16,
182 0xd70, 0x1812362e,
183 0xd74, 0x322c2220,
184 0xd78, 0x000e3c24,
185 0xe00, 0x2a2a2a2a,
186 0xe04, 0x2a2a2a2a,
187 0xe08, 0x03902a2a,
188 0xe10, 0x2a2a2a2a,
189 0xe14, 0x2a2a2a2a,
190 0xe18, 0x2a2a2a2a,
191 0xe1c, 0x2a2a2a2a,
192 0xe28, 0x00000000,
193 0xe30, 0x1000dc1f,
194 0xe34, 0x10008c1f,
195 0xe38, 0x02140102,
196 0xe3c, 0x681604c2,
197 0xe40, 0x01007c00,
198 0xe44, 0x01004800,
199 0xe48, 0xfb000000,
200 0xe4c, 0x000028d1,
201 0xe50, 0x1000dc1f,
202 0xe54, 0x10008c1f,
203 0xe58, 0x02140102,
204 0xe5c, 0x28160d05,
205 0xe60, 0x00000010,
206 0xe68, 0x001b25a4,
207 0xe6c, 0x63db25a4,
208 0xe70, 0x63db25a4,
209 0xe74, 0x0c126da4,
210 0xe78, 0x0c126da4,
211 0xe7c, 0x0c126da4,
212 0xe80, 0x0c126da4,
213 0xe84, 0x63db25a4,
214 0xe88, 0x0c126da4,
215 0xe8c, 0x63db25a4,
216 0xed0, 0x63db25a4,
217 0xed4, 0x63db25a4,
218 0xed8, 0x63db25a4,
219 0xedc, 0x001b25a4,
220 0xee0, 0x001b25a4,
221 0xeec, 0x6fdb25a4,
222 0xf14, 0x00000003,
223 0xf1c, 0x00000064,
224 0xf4c, 0x00000004,
225 0xf00, 0x00000300,
226};
227
228u32 rtl8192de_phy_reg_array_pg[PHY_REG_ARRAY_PG_LENGTH] = {
229 0xe00, 0xffffffff, 0x07090c0c,
230 0xe04, 0xffffffff, 0x01020405,
231 0xe08, 0x0000ff00, 0x00000000,
232 0x86c, 0xffffff00, 0x00000000,
233 0xe10, 0xffffffff, 0x0b0c0c0e,
234 0xe14, 0xffffffff, 0x01030506,
235 0xe18, 0xffffffff, 0x0b0c0d0e,
236 0xe1c, 0xffffffff, 0x01030509,
237 0x830, 0xffffffff, 0x07090c0c,
238 0x834, 0xffffffff, 0x01020405,
239 0x838, 0xffffff00, 0x00000000,
240 0x86c, 0x000000ff, 0x00000000,
241 0x83c, 0xffffffff, 0x0b0c0c0e,
242 0x848, 0xffffffff, 0x01030506,
243 0x84c, 0xffffffff, 0x0b0c0d0e,
244 0x868, 0xffffffff, 0x01030509,
245 0xe00, 0xffffffff, 0x00000000,
246 0xe04, 0xffffffff, 0x00000000,
247 0xe08, 0x0000ff00, 0x00000000,
248 0x86c, 0xffffff00, 0x00000000,
249 0xe10, 0xffffffff, 0x00000000,
250 0xe14, 0xffffffff, 0x00000000,
251 0xe18, 0xffffffff, 0x00000000,
252 0xe1c, 0xffffffff, 0x00000000,
253 0x830, 0xffffffff, 0x00000000,
254 0x834, 0xffffffff, 0x00000000,
255 0x838, 0xffffff00, 0x00000000,
256 0x86c, 0x000000ff, 0x00000000,
257 0x83c, 0xffffffff, 0x00000000,
258 0x848, 0xffffffff, 0x00000000,
259 0x84c, 0xffffffff, 0x00000000,
260 0x868, 0xffffffff, 0x00000000,
261 0xe00, 0xffffffff, 0x04040404,
262 0xe04, 0xffffffff, 0x00020204,
263 0xe08, 0x0000ff00, 0x00000000,
264 0x86c, 0xffffff00, 0x00000000,
265 0xe10, 0xffffffff, 0x06060606,
266 0xe14, 0xffffffff, 0x00020406,
267 0xe18, 0xffffffff, 0x00000000,
268 0xe1c, 0xffffffff, 0x00000000,
269 0x830, 0xffffffff, 0x04040404,
270 0x834, 0xffffffff, 0x00020204,
271 0x838, 0xffffff00, 0x00000000,
272 0x86c, 0x000000ff, 0x00000000,
273 0x83c, 0xffffffff, 0x06060606,
274 0x848, 0xffffffff, 0x00020406,
275 0x84c, 0xffffffff, 0x00000000,
276 0x868, 0xffffffff, 0x00000000,
277 0xe00, 0xffffffff, 0x00000000,
278 0xe04, 0xffffffff, 0x00000000,
279 0xe08, 0x0000ff00, 0x00000000,
280 0x86c, 0xffffff00, 0x00000000,
281 0xe10, 0xffffffff, 0x00000000,
282 0xe14, 0xffffffff, 0x00000000,
283 0xe18, 0xffffffff, 0x00000000,
284 0xe1c, 0xffffffff, 0x00000000,
285 0x830, 0xffffffff, 0x00000000,
286 0x834, 0xffffffff, 0x00000000,
287 0x838, 0xffffff00, 0x00000000,
288 0x86c, 0x000000ff, 0x00000000,
289 0x83c, 0xffffffff, 0x00000000,
290 0x848, 0xffffffff, 0x00000000,
291 0x84c, 0xffffffff, 0x00000000,
292 0x868, 0xffffffff, 0x00000000,
293 0xe00, 0xffffffff, 0x00000000,
294 0xe04, 0xffffffff, 0x00000000,
295 0xe08, 0x0000ff00, 0x00000000,
296 0x86c, 0xffffff00, 0x00000000,
297 0xe10, 0xffffffff, 0x00000000,
298 0xe14, 0xffffffff, 0x00000000,
299 0xe18, 0xffffffff, 0x00000000,
300 0xe1c, 0xffffffff, 0x00000000,
301 0x830, 0xffffffff, 0x00000000,
302 0x834, 0xffffffff, 0x00000000,
303 0x838, 0xffffff00, 0x00000000,
304 0x86c, 0x000000ff, 0x00000000,
305 0x83c, 0xffffffff, 0x00000000,
306 0x848, 0xffffffff, 0x00000000,
307 0x84c, 0xffffffff, 0x00000000,
308 0x868, 0xffffffff, 0x00000000,
309 0xe00, 0xffffffff, 0x04040404,
310 0xe04, 0xffffffff, 0x00020204,
311 0xe08, 0x0000ff00, 0x00000000,
312 0x86c, 0xffffff00, 0x00000000,
313 0xe10, 0xffffffff, 0x00000000,
314 0xe14, 0xffffffff, 0x00000000,
315 0xe18, 0xffffffff, 0x00000000,
316 0xe1c, 0xffffffff, 0x00000000,
317 0x830, 0xffffffff, 0x04040404,
318 0x834, 0xffffffff, 0x00020204,
319 0x838, 0xffffff00, 0x00000000,
320 0x86c, 0x000000ff, 0x00000000,
321 0x83c, 0xffffffff, 0x00000000,
322 0x848, 0xffffffff, 0x00000000,
323 0x84c, 0xffffffff, 0x00000000,
324 0x868, 0xffffffff, 0x00000000,
325 0xe00, 0xffffffff, 0x00000000,
326 0xe04, 0xffffffff, 0x00000000,
327 0xe08, 0x0000ff00, 0x00000000,
328 0x86c, 0xffffff00, 0x00000000,
329 0xe10, 0xffffffff, 0x00000000,
330 0xe14, 0xffffffff, 0x00000000,
331 0xe18, 0xffffffff, 0x00000000,
332 0xe1c, 0xffffffff, 0x00000000,
333 0x830, 0xffffffff, 0x00000000,
334 0x834, 0xffffffff, 0x00000000,
335 0x838, 0xffffff00, 0x00000000,
336 0x86c, 0x000000ff, 0x00000000,
337 0x83c, 0xffffffff, 0x00000000,
338 0x848, 0xffffffff, 0x00000000,
339 0x84c, 0xffffffff, 0x00000000,
340 0x868, 0xffffffff, 0x00000000,
341 0xe00, 0xffffffff, 0x04040404,
342 0xe04, 0xffffffff, 0x00020204,
343 0xe08, 0x0000ff00, 0x00000000,
344 0x86c, 0xffffff00, 0x00000000,
345 0xe10, 0xffffffff, 0x08080808,
346 0xe14, 0xffffffff, 0x00040408,
347 0xe18, 0xffffffff, 0x00000000,
348 0xe1c, 0xffffffff, 0x00000000,
349 0x830, 0xffffffff, 0x04040404,
350 0x834, 0xffffffff, 0x00020204,
351 0x838, 0xffffff00, 0x00000000,
352 0x86c, 0x000000ff, 0x00000000,
353 0x83c, 0xffffffff, 0x08080808,
354 0x848, 0xffffffff, 0x00040408,
355 0x84c, 0xffffffff, 0x00000000,
356 0x868, 0xffffffff, 0x00000000,
357 0xe00, 0xffffffff, 0x04040404,
358 0xe04, 0xffffffff, 0x00020204,
359 0xe08, 0x0000ff00, 0x00000000,
360 0x86c, 0xffffff00, 0x00000000,
361 0xe10, 0xffffffff, 0x08080808,
362 0xe14, 0xffffffff, 0x00040408,
363 0xe18, 0xffffffff, 0x00000000,
364 0xe1c, 0xffffffff, 0x00000000,
365 0x830, 0xffffffff, 0x04040404,
366 0x834, 0xffffffff, 0x00020204,
367 0x838, 0xffffff00, 0x00000000,
368 0x86c, 0x000000ff, 0x00000000,
369 0x83c, 0xffffffff, 0x08080808,
370 0x848, 0xffffffff, 0x00040408,
371 0x84c, 0xffffffff, 0x00000000,
372 0x868, 0xffffffff, 0x00000000,
373 0xe00, 0xffffffff, 0x04040404,
374 0xe04, 0xffffffff, 0x00020204,
375 0xe08, 0x0000ff00, 0x00000000,
376 0x86c, 0xffffff00, 0x00000000,
377 0xe10, 0xffffffff, 0x08080808,
378 0xe14, 0xffffffff, 0x00040408,
379 0xe18, 0xffffffff, 0x00000000,
380 0xe1c, 0xffffffff, 0x00000000,
381 0x830, 0xffffffff, 0x04040404,
382 0x834, 0xffffffff, 0x00020204,
383 0x838, 0xffffff00, 0x00000000,
384 0x86c, 0x000000ff, 0x00000000,
385 0x83c, 0xffffffff, 0x08080808,
386 0x848, 0xffffffff, 0x00040408,
387 0x84c, 0xffffffff, 0x00000000,
388 0x868, 0xffffffff, 0x00000000,
389 0xe00, 0xffffffff, 0x04040404,
390 0xe04, 0xffffffff, 0x00020204,
391 0xe08, 0x0000ff00, 0x00000000,
392 0x86c, 0xffffff00, 0x00000000,
393 0xe10, 0xffffffff, 0x08080808,
394 0xe14, 0xffffffff, 0x00040408,
395 0xe18, 0xffffffff, 0x00000000,
396 0xe1c, 0xffffffff, 0x00000000,
397 0x830, 0xffffffff, 0x04040404,
398 0x834, 0xffffffff, 0x00020204,
399 0x838, 0xffffff00, 0x00000000,
400 0x86c, 0x000000ff, 0x00000000,
401 0x83c, 0xffffffff, 0x08080808,
402 0x848, 0xffffffff, 0x00040408,
403 0x84c, 0xffffffff, 0x00000000,
404 0x868, 0xffffffff, 0x00000000,
405 0xe00, 0xffffffff, 0x04040404,
406 0xe04, 0xffffffff, 0x00020204,
407 0xe08, 0x0000ff00, 0x00000000,
408 0x86c, 0xffffff00, 0x00000000,
409 0xe10, 0xffffffff, 0x08080808,
410 0xe14, 0xffffffff, 0x00040408,
411 0xe18, 0xffffffff, 0x00000000,
412 0xe1c, 0xffffffff, 0x00000000,
413 0x830, 0xffffffff, 0x04040404,
414 0x834, 0xffffffff, 0x00020204,
415 0x838, 0xffffff00, 0x00000000,
416 0x86c, 0x000000ff, 0x00000000,
417 0x83c, 0xffffffff, 0x08080808,
418 0x848, 0xffffffff, 0x00040408,
419 0x84c, 0xffffffff, 0x00000000,
420 0x868, 0xffffffff, 0x00000000,
421 0xe00, 0xffffffff, 0x04040404,
422 0xe04, 0xffffffff, 0x00020204,
423 0xe08, 0x0000ff00, 0x00000000,
424 0x86c, 0xffffff00, 0x00000000,
425 0xe10, 0xffffffff, 0x08080808,
426 0xe14, 0xffffffff, 0x00040408,
427 0xe18, 0xffffffff, 0x00000000,
428 0xe1c, 0xffffffff, 0x00000000,
429 0x830, 0xffffffff, 0x04040404,
430 0x834, 0xffffffff, 0x00020204,
431 0x838, 0xffffff00, 0x00000000,
432 0x86c, 0x000000ff, 0x00000000,
433 0x83c, 0xffffffff, 0x08080808,
434 0x848, 0xffffffff, 0x00040408,
435 0x84c, 0xffffffff, 0x00000000,
436 0x868, 0xffffffff, 0x00000000,
437};
438
439u32 rtl8192de_radioa_2tarray[RADIOA_2T_ARRAYLENGTH] = {
440 0x000, 0x00030000,
441 0x001, 0x00030000,
442 0x002, 0x00000000,
443 0x003, 0x00018c63,
444 0x004, 0x00018c63,
445 0x008, 0x00084000,
446 0x00b, 0x0001c000,
447 0x00e, 0x00018c67,
448 0x00f, 0x00000851,
449 0x014, 0x00021440,
450 0x018, 0x00017524,
451 0x019, 0x00000000,
452 0x01d, 0x000a1290,
453 0x023, 0x00001558,
454 0x01a, 0x00030a99,
455 0x01b, 0x00040b00,
456 0x01c, 0x000fc339,
457 0x03a, 0x000a57eb,
458 0x03b, 0x00020000,
459 0x03c, 0x000ff454,
460 0x020, 0x0000aa52,
461 0x021, 0x00054000,
462 0x040, 0x0000aa52,
463 0x041, 0x00014000,
464 0x025, 0x000803be,
465 0x026, 0x000fc638,
466 0x027, 0x00077c18,
467 0x028, 0x000de471,
468 0x029, 0x000d7110,
469 0x02a, 0x0008cb04,
470 0x02b, 0x0004128b,
471 0x02c, 0x00001840,
472 0x043, 0x0002444f,
473 0x044, 0x0001adb0,
474 0x045, 0x00056467,
475 0x046, 0x0008992c,
476 0x047, 0x0000452c,
477 0x048, 0x000f9c43,
478 0x049, 0x00002e0c,
479 0x04a, 0x000546eb,
480 0x04b, 0x0008966c,
481 0x04c, 0x0000dde9,
482 0x018, 0x00007401,
483 0x000, 0x00070000,
484 0x012, 0x000dc000,
485 0x012, 0x00090000,
486 0x012, 0x00051000,
487 0x012, 0x00012000,
488 0x013, 0x000287b7,
489 0x013, 0x000247ab,
490 0x013, 0x0002079f,
491 0x013, 0x0001c793,
492 0x013, 0x0001839b,
493 0x013, 0x00014392,
494 0x013, 0x0001019a,
495 0x013, 0x0000c191,
496 0x013, 0x00008194,
497 0x013, 0x000040a0,
498 0x013, 0x00000018,
499 0x015, 0x0000f424,
500 0x015, 0x0004f424,
501 0x015, 0x0008f424,
502 0x016, 0x000e1330,
503 0x016, 0x000a1330,
504 0x016, 0x00061330,
505 0x016, 0x00021330,
506 0x018, 0x00017524,
507 0x000, 0x00070000,
508 0x012, 0x000cf000,
509 0x012, 0x000bc000,
510 0x012, 0x00078000,
511 0x012, 0x00000000,
512 0x013, 0x000287bc,
513 0x013, 0x000247b0,
514 0x013, 0x000203b4,
515 0x013, 0x0001c3a8,
516 0x013, 0x000181b4,
517 0x013, 0x000141a8,
518 0x013, 0x000100b0,
519 0x013, 0x0000c0a4,
520 0x013, 0x0000b02c,
521 0x013, 0x00004020,
522 0x013, 0x00000014,
523 0x015, 0x0000f4c3,
524 0x015, 0x0004f4c3,
525 0x015, 0x0008f4c3,
526 0x016, 0x000e085f,
527 0x016, 0x000a085f,
528 0x016, 0x0006085f,
529 0x016, 0x0002085f,
530 0x018, 0x00037524,
531 0x000, 0x00070000,
532 0x012, 0x000cf000,
533 0x012, 0x000bc000,
534 0x012, 0x00078000,
535 0x012, 0x00000000,
536 0x013, 0x000287bc,
537 0x013, 0x000247b0,
538 0x013, 0x000203b4,
539 0x013, 0x0001c3a8,
540 0x013, 0x000181b4,
541 0x013, 0x000141a8,
542 0x013, 0x000100b0,
543 0x013, 0x0000c0a4,
544 0x013, 0x0000b02c,
545 0x013, 0x00004020,
546 0x013, 0x00000014,
547 0x015, 0x0000f4c3,
548 0x015, 0x0004f4c3,
549 0x015, 0x0008f4c3,
550 0x016, 0x000e085f,
551 0x016, 0x000a085f,
552 0x016, 0x0006085f,
553 0x016, 0x0002085f,
554 0x018, 0x00057568,
555 0x000, 0x00070000,
556 0x012, 0x000cf000,
557 0x012, 0x000bc000,
558 0x012, 0x00078000,
559 0x012, 0x00000000,
560 0x013, 0x000287bc,
561 0x013, 0x000247b0,
562 0x013, 0x000203b4,
563 0x013, 0x0001c3a8,
564 0x013, 0x000181b4,
565 0x013, 0x000141a8,
566 0x013, 0x000100b0,
567 0x013, 0x0000c0a4,
568 0x013, 0x0000b02c,
569 0x013, 0x00004020,
570 0x013, 0x00000014,
571 0x015, 0x0000f4c3,
572 0x015, 0x0004f4c3,
573 0x015, 0x0008f4c3,
574 0x016, 0x000e085f,
575 0x016, 0x000a085f,
576 0x016, 0x0006085f,
577 0x016, 0x0002085f,
578 0x030, 0x0004470f,
579 0x031, 0x00044ff0,
580 0x032, 0x00000070,
581 0x033, 0x000dd480,
582 0x034, 0x000ffac0,
583 0x035, 0x000b80c0,
584 0x036, 0x00077000,
585 0x037, 0x00064ff2,
586 0x038, 0x000e7661,
587 0x039, 0x00000e90,
588 0x000, 0x00030000,
589 0x018, 0x0000f401,
590 0x0fe, 0x00000000,
591 0x0fe, 0x00000000,
592 0x01e, 0x00088009,
593 0x01f, 0x00080003,
594 0x0fe, 0x00000000,
595 0x01e, 0x00088001,
596 0x01f, 0x00080000,
597 0x0fe, 0x00000000,
598 0x018, 0x00097524,
599 0x0fe, 0x00000000,
600 0x0fe, 0x00000000,
601 0x0fe, 0x00000000,
602 0x0fe, 0x00000000,
603 0x02b, 0x00041289,
604 0x0fe, 0x00000000,
605 0x02d, 0x0006aaaa,
606 0x02e, 0x000b4d01,
607 0x02d, 0x00080000,
608 0x02e, 0x00004d02,
609 0x02d, 0x00095555,
610 0x02e, 0x00054d03,
611 0x02d, 0x000aaaaa,
612 0x02e, 0x000b4d04,
613 0x02d, 0x000c0000,
614 0x02e, 0x00004d05,
615 0x02d, 0x000d5555,
616 0x02e, 0x00054d06,
617 0x02d, 0x000eaaaa,
618 0x02e, 0x000b4d07,
619 0x02d, 0x00000000,
620 0x02e, 0x00005108,
621 0x02d, 0x00015555,
622 0x02e, 0x00055109,
623 0x02d, 0x0002aaaa,
624 0x02e, 0x000b510a,
625 0x02d, 0x00040000,
626 0x02e, 0x0000510b,
627 0x02d, 0x00055555,
628 0x02e, 0x0005510c,
629};
630
631u32 rtl8192de_radiob_2tarray[RADIOB_2T_ARRAYLENGTH] = {
632 0x000, 0x00030000,
633 0x001, 0x00030000,
634 0x002, 0x00000000,
635 0x003, 0x00018c63,
636 0x004, 0x00018c63,
637 0x008, 0x00084000,
638 0x00b, 0x0001c000,
639 0x00e, 0x00018c67,
640 0x00f, 0x00000851,
641 0x014, 0x00021440,
642 0x018, 0x00007401,
643 0x019, 0x00000060,
644 0x01d, 0x000a1290,
645 0x023, 0x00001558,
646 0x01a, 0x00030a99,
647 0x01b, 0x00040b00,
648 0x01c, 0x000fc339,
649 0x03a, 0x000a57eb,
650 0x03b, 0x00020000,
651 0x03c, 0x000ff454,
652 0x020, 0x0000aa52,
653 0x021, 0x00054000,
654 0x040, 0x0000aa52,
655 0x041, 0x00014000,
656 0x025, 0x000803be,
657 0x026, 0x000fc638,
658 0x027, 0x00077c18,
659 0x028, 0x000d1c31,
660 0x029, 0x000d7110,
661 0x02a, 0x000aeb04,
662 0x02b, 0x0004128b,
663 0x02c, 0x00001840,
664 0x043, 0x0002444f,
665 0x044, 0x0001adb0,
666 0x045, 0x00056467,
667 0x046, 0x0008992c,
668 0x047, 0x0000452c,
669 0x048, 0x000f9c43,
670 0x049, 0x00002e0c,
671 0x04a, 0x000546eb,
672 0x04b, 0x0008966c,
673 0x04c, 0x0000dde9,
674 0x018, 0x00007401,
675 0x000, 0x00070000,
676 0x012, 0x000dc000,
677 0x012, 0x00090000,
678 0x012, 0x00051000,
679 0x012, 0x00012000,
680 0x013, 0x000287b7,
681 0x013, 0x000247ab,
682 0x013, 0x0002079f,
683 0x013, 0x0001c793,
684 0x013, 0x0001839b,
685 0x013, 0x00014392,
686 0x013, 0x0001019a,
687 0x013, 0x0000c191,
688 0x013, 0x00008194,
689 0x013, 0x000040a0,
690 0x013, 0x00000018,
691 0x015, 0x0000f424,
692 0x015, 0x0004f424,
693 0x015, 0x0008f424,
694 0x016, 0x000e1330,
695 0x016, 0x000a1330,
696 0x016, 0x00061330,
697 0x016, 0x00021330,
698 0x018, 0x00017524,
699 0x000, 0x00070000,
700 0x012, 0x000cf000,
701 0x012, 0x000bc000,
702 0x012, 0x00078000,
703 0x012, 0x00000000,
704 0x013, 0x000287bc,
705 0x013, 0x000247b0,
706 0x013, 0x000203b4,
707 0x013, 0x0001c3a8,
708 0x013, 0x000181b4,
709 0x013, 0x000141a8,
710 0x013, 0x000100b0,
711 0x013, 0x0000c0a4,
712 0x013, 0x0000b02c,
713 0x013, 0x00004020,
714 0x013, 0x00000014,
715 0x015, 0x0000f4c3,
716 0x015, 0x0004f4c3,
717 0x015, 0x0008f4c3,
718 0x016, 0x000e085f,
719 0x016, 0x000a085f,
720 0x016, 0x0006085f,
721 0x016, 0x0002085f,
722 0x018, 0x00037524,
723 0x000, 0x00070000,
724 0x012, 0x000cf000,
725 0x012, 0x000bc000,
726 0x012, 0x00078000,
727 0x012, 0x00000000,
728 0x013, 0x000287bc,
729 0x013, 0x000247b0,
730 0x013, 0x000203b4,
731 0x013, 0x0001c3a8,
732 0x013, 0x000181b4,
733 0x013, 0x000141a8,
734 0x013, 0x000100b0,
735 0x013, 0x0000c0a4,
736 0x013, 0x0000b02c,
737 0x013, 0x00004020,
738 0x013, 0x00000014,
739 0x015, 0x0000f4c3,
740 0x015, 0x0004f4c3,
741 0x015, 0x0008f4c3,
742 0x016, 0x000e085f,
743 0x016, 0x000a085f,
744 0x016, 0x0006085f,
745 0x016, 0x0002085f,
746 0x018, 0x00057524,
747 0x000, 0x00070000,
748 0x012, 0x000cf000,
749 0x012, 0x000bc000,
750 0x012, 0x00078000,
751 0x012, 0x00000000,
752 0x013, 0x000287bc,
753 0x013, 0x000247b0,
754 0x013, 0x000203b4,
755 0x013, 0x0001c3a8,
756 0x013, 0x000181b4,
757 0x013, 0x000141a8,
758 0x013, 0x000100b0,
759 0x013, 0x0000c0a4,
760 0x013, 0x0000b02c,
761 0x013, 0x00004020,
762 0x013, 0x00000014,
763 0x015, 0x0000f4c3,
764 0x015, 0x0004f4c3,
765 0x015, 0x0008f4c3,
766 0x016, 0x000e085f,
767 0x016, 0x000a085f,
768 0x016, 0x0006085f,
769 0x016, 0x0002085f,
770 0x030, 0x0004470f,
771 0x031, 0x00044ff0,
772 0x032, 0x00000070,
773 0x033, 0x000dd480,
774 0x034, 0x000ffac0,
775 0x035, 0x000b80c0,
776 0x036, 0x00077000,
777 0x037, 0x00064ff2,
778 0x038, 0x000e7661,
779 0x039, 0x00000e90,
780 0x000, 0x00030000,
781 0x018, 0x0000f401,
782 0x0fe, 0x00000000,
783 0x0fe, 0x00000000,
784 0x01e, 0x00088009,
785 0x01f, 0x00080003,
786 0x0fe, 0x00000000,
787 0x01e, 0x00088001,
788 0x01f, 0x00080000,
789 0x0fe, 0x00000000,
790 0x018, 0x00087401,
791 0x0fe, 0x00000000,
792 0x0fe, 0x00000000,
793 0x0fe, 0x00000000,
794 0x02b, 0x00041289,
795 0x0fe, 0x00000000,
796 0x02d, 0x00066666,
797 0x02e, 0x00064001,
798 0x02d, 0x00091111,
799 0x02e, 0x00014002,
800 0x02d, 0x000bbbbb,
801 0x02e, 0x000b4003,
802 0x02d, 0x000e6666,
803 0x02e, 0x00064004,
804 0x02d, 0x00088888,
805 0x02e, 0x00084005,
806 0x02d, 0x0009dddd,
807 0x02e, 0x000d4006,
808 0x02d, 0x000b3333,
809 0x02e, 0x00034007,
810 0x02d, 0x00048888,
811 0x02e, 0x00084408,
812 0x02d, 0x000bbbbb,
813 0x02e, 0x000b4409,
814 0x02d, 0x000e6666,
815 0x02e, 0x0006440a,
816 0x02d, 0x00011111,
817 0x02e, 0x0001480b,
818 0x02d, 0x0003bbbb,
819 0x02e, 0x000b480c,
820 0x02d, 0x00066666,
821 0x02e, 0x0006480d,
822 0x02d, 0x000ccccc,
823 0x02e, 0x000c480e,
824};
825
826u32 rtl8192de_radioa_2t_int_paarray[RADIOA_2T_INT_PA_ARRAYLENGTH] = {
827 0x000, 0x00030000,
828 0x001, 0x00030000,
829 0x002, 0x00000000,
830 0x003, 0x00018c63,
831 0x004, 0x00018c63,
832 0x008, 0x00084000,
833 0x00b, 0x0001c000,
834 0x00e, 0x00018c67,
835 0x00f, 0x00000851,
836 0x014, 0x00021440,
837 0x018, 0x00017524,
838 0x019, 0x00000000,
839 0x01d, 0x000a1290,
840 0x023, 0x00001558,
841 0x01a, 0x00030a99,
842 0x01b, 0x00040b00,
843 0x01c, 0x000fc339,
844 0x03a, 0x000a57eb,
845 0x03b, 0x00020000,
846 0x03c, 0x000ff454,
847 0x020, 0x0000aa52,
848 0x021, 0x00054000,
849 0x040, 0x0000aa52,
850 0x041, 0x00014000,
851 0x025, 0x000803be,
852 0x026, 0x000fc638,
853 0x027, 0x00077c18,
854 0x028, 0x000de471,
855 0x029, 0x000d7110,
856 0x02a, 0x0008eb04,
857 0x02b, 0x0004128b,
858 0x02c, 0x00001840,
859 0x043, 0x0002444f,
860 0x044, 0x0001adb0,
861 0x045, 0x00056467,
862 0x046, 0x0008992c,
863 0x047, 0x0000452c,
864 0x048, 0x000c0443,
865 0x049, 0x00000730,
866 0x04a, 0x00050f0f,
867 0x04b, 0x000896ee,
868 0x04c, 0x0000ddee,
869 0x018, 0x00007401,
870 0x000, 0x00070000,
871 0x012, 0x000dc000,
872 0x012, 0x00090000,
873 0x012, 0x00051000,
874 0x012, 0x00012000,
875 0x013, 0x000287b7,
876 0x013, 0x000247ab,
877 0x013, 0x0002079f,
878 0x013, 0x0001c793,
879 0x013, 0x0001839b,
880 0x013, 0x00014392,
881 0x013, 0x0001019a,
882 0x013, 0x0000c191,
883 0x013, 0x00008194,
884 0x013, 0x000040a0,
885 0x013, 0x00000018,
886 0x015, 0x0000f424,
887 0x015, 0x0004f424,
888 0x015, 0x0008f424,
889 0x016, 0x000e1330,
890 0x016, 0x000a1330,
891 0x016, 0x00061330,
892 0x016, 0x00021330,
893 0x018, 0x00017524,
894 0x000, 0x00070000,
895 0x012, 0x000cf000,
896 0x012, 0x000bc000,
897 0x012, 0x00078000,
898 0x012, 0x00000000,
899 0x013, 0x000287bf,
900 0x013, 0x000247b3,
901 0x013, 0x000207a7,
902 0x013, 0x0001c79b,
903 0x013, 0x0001839f,
904 0x013, 0x00014393,
905 0x013, 0x00010399,
906 0x013, 0x0000c38d,
907 0x013, 0x00008199,
908 0x013, 0x0000418d,
909 0x013, 0x00000099,
910 0x015, 0x0000f495,
911 0x015, 0x0004f495,
912 0x015, 0x0008f495,
913 0x016, 0x000e1874,
914 0x016, 0x000a1874,
915 0x016, 0x00061874,
916 0x016, 0x00021874,
917 0x018, 0x00037564,
918 0x000, 0x00070000,
919 0x012, 0x000cf000,
920 0x012, 0x000bc000,
921 0x012, 0x00078000,
922 0x012, 0x00000000,
923 0x013, 0x000287bf,
924 0x013, 0x000247b3,
925 0x013, 0x000207a7,
926 0x013, 0x0001c79b,
927 0x013, 0x0001839f,
928 0x013, 0x00014393,
929 0x013, 0x00010399,
930 0x013, 0x0000c38d,
931 0x013, 0x00008199,
932 0x013, 0x0000418d,
933 0x013, 0x00000099,
934 0x015, 0x0000f495,
935 0x015, 0x0004f495,
936 0x015, 0x0008f495,
937 0x016, 0x000e1874,
938 0x016, 0x000a1874,
939 0x016, 0x00061874,
940 0x016, 0x00021874,
941 0x018, 0x00057595,
942 0x000, 0x00070000,
943 0x012, 0x000cf000,
944 0x012, 0x000bc000,
945 0x012, 0x00078000,
946 0x012, 0x00000000,
947 0x013, 0x000287bf,
948 0x013, 0x000247b3,
949 0x013, 0x000207a7,
950 0x013, 0x0001c79b,
951 0x013, 0x0001839f,
952 0x013, 0x00014393,
953 0x013, 0x00010399,
954 0x013, 0x0000c38d,
955 0x013, 0x00008199,
956 0x013, 0x0000418d,
957 0x013, 0x00000099,
958 0x015, 0x0000f495,
959 0x015, 0x0004f495,
960 0x015, 0x0008f495,
961 0x016, 0x000e1874,
962 0x016, 0x000a1874,
963 0x016, 0x00061874,
964 0x016, 0x00021874,
965 0x030, 0x0004470f,
966 0x031, 0x00044ff0,
967 0x032, 0x00000070,
968 0x033, 0x000dd480,
969 0x034, 0x000ffac0,
970 0x035, 0x000b80c0,
971 0x036, 0x00077000,
972 0x037, 0x00064ff2,
973 0x038, 0x000e7661,
974 0x039, 0x00000e90,
975 0x000, 0x00030000,
976 0x018, 0x0000f401,
977 0x0fe, 0x00000000,
978 0x0fe, 0x00000000,
979 0x01e, 0x00088009,
980 0x01f, 0x00080003,
981 0x0fe, 0x00000000,
982 0x01e, 0x00088001,
983 0x01f, 0x00080000,
984 0x0fe, 0x00000000,
985 0x018, 0x00097524,
986 0x0fe, 0x00000000,
987 0x0fe, 0x00000000,
988 0x0fe, 0x00000000,
989 0x0fe, 0x00000000,
990 0x02b, 0x00041289,
991 0x0fe, 0x00000000,
992 0x02d, 0x0006aaaa,
993 0x02e, 0x000b4d01,
994 0x02d, 0x00080000,
995 0x02e, 0x00004d02,
996 0x02d, 0x00095555,
997 0x02e, 0x00054d03,
998 0x02d, 0x000aaaaa,
999 0x02e, 0x000b4d04,
1000 0x02d, 0x000c0000,
1001 0x02e, 0x00004d05,
1002 0x02d, 0x000d5555,
1003 0x02e, 0x00054d06,
1004 0x02d, 0x000eaaaa,
1005 0x02e, 0x000b4d07,
1006 0x02d, 0x00000000,
1007 0x02e, 0x00005108,
1008 0x02d, 0x00015555,
1009 0x02e, 0x00055109,
1010 0x02d, 0x0002aaaa,
1011 0x02e, 0x000b510a,
1012 0x02d, 0x00040000,
1013 0x02e, 0x0000510b,
1014 0x02d, 0x00055555,
1015 0x02e, 0x0005510c,
1016};
1017
1018u32 rtl8192de_radiob_2t_int_paarray[RADIOB_2T_INT_PA_ARRAYLENGTH] = {
1019 0x000, 0x00030000,
1020 0x001, 0x00030000,
1021 0x002, 0x00000000,
1022 0x003, 0x00018c63,
1023 0x004, 0x00018c63,
1024 0x008, 0x00084000,
1025 0x00b, 0x0001c000,
1026 0x00e, 0x00018c67,
1027 0x00f, 0x00000851,
1028 0x014, 0x00021440,
1029 0x018, 0x00007401,
1030 0x019, 0x00000060,
1031 0x01d, 0x000a1290,
1032 0x023, 0x00001558,
1033 0x01a, 0x00030a99,
1034 0x01b, 0x00040b00,
1035 0x01c, 0x000fc339,
1036 0x03a, 0x000a57eb,
1037 0x03b, 0x00020000,
1038 0x03c, 0x000ff454,
1039 0x020, 0x0000aa52,
1040 0x021, 0x00054000,
1041 0x040, 0x0000aa52,
1042 0x041, 0x00014000,
1043 0x025, 0x000803be,
1044 0x026, 0x000fc638,
1045 0x027, 0x00077c18,
1046 0x028, 0x000d1c31,
1047 0x029, 0x000d7110,
1048 0x02a, 0x000aeb04,
1049 0x02b, 0x0004128b,
1050 0x02c, 0x00001840,
1051 0x043, 0x0002444f,
1052 0x044, 0x0001adb0,
1053 0x045, 0x00056467,
1054 0x046, 0x0008992c,
1055 0x047, 0x0000452c,
1056 0x048, 0x000c0443,
1057 0x049, 0x00000730,
1058 0x04a, 0x00050f0f,
1059 0x04b, 0x000896ee,
1060 0x04c, 0x0000ddee,
1061 0x018, 0x00007401,
1062 0x000, 0x00070000,
1063 0x012, 0x000dc000,
1064 0x012, 0x00090000,
1065 0x012, 0x00051000,
1066 0x012, 0x00012000,
1067 0x013, 0x000287b7,
1068 0x013, 0x000247ab,
1069 0x013, 0x0002079f,
1070 0x013, 0x0001c793,
1071 0x013, 0x0001839b,
1072 0x013, 0x00014392,
1073 0x013, 0x0001019a,
1074 0x013, 0x0000c191,
1075 0x013, 0x00008194,
1076 0x013, 0x000040a0,
1077 0x013, 0x00000018,
1078 0x015, 0x0000f424,
1079 0x015, 0x0004f424,
1080 0x015, 0x0008f424,
1081 0x016, 0x000e1330,
1082 0x016, 0x000a1330,
1083 0x016, 0x00061330,
1084 0x016, 0x00021330,
1085 0x018, 0x00017524,
1086 0x000, 0x00070000,
1087 0x012, 0x000cf000,
1088 0x012, 0x000bc000,
1089 0x012, 0x00078000,
1090 0x012, 0x00000000,
1091 0x013, 0x000287bf,
1092 0x013, 0x000247b3,
1093 0x013, 0x000207a7,
1094 0x013, 0x0001c79b,
1095 0x013, 0x0001839f,
1096 0x013, 0x00014393,
1097 0x013, 0x00010399,
1098 0x013, 0x0000c38d,
1099 0x013, 0x00008199,
1100 0x013, 0x0000418d,
1101 0x013, 0x00000099,
1102 0x015, 0x0000f495,
1103 0x015, 0x0004f495,
1104 0x015, 0x0008f495,
1105 0x016, 0x000e1874,
1106 0x016, 0x000a1874,
1107 0x016, 0x00061874,
1108 0x016, 0x00021874,
1109 0x018, 0x00037564,
1110 0x000, 0x00070000,
1111 0x012, 0x000cf000,
1112 0x012, 0x000bc000,
1113 0x012, 0x00078000,
1114 0x012, 0x00000000,
1115 0x013, 0x000287bf,
1116 0x013, 0x000247b3,
1117 0x013, 0x000207a7,
1118 0x013, 0x0001c79b,
1119 0x013, 0x0001839f,
1120 0x013, 0x00014393,
1121 0x013, 0x00010399,
1122 0x013, 0x0000c38d,
1123 0x013, 0x00008199,
1124 0x013, 0x0000418d,
1125 0x013, 0x00000099,
1126 0x015, 0x0000f495,
1127 0x015, 0x0004f495,
1128 0x015, 0x0008f495,
1129 0x016, 0x000e1874,
1130 0x016, 0x000a1874,
1131 0x016, 0x00061874,
1132 0x016, 0x00021874,
1133 0x018, 0x00057595,
1134 0x000, 0x00070000,
1135 0x012, 0x000cf000,
1136 0x012, 0x000bc000,
1137 0x012, 0x00078000,
1138 0x012, 0x00000000,
1139 0x013, 0x000287bf,
1140 0x013, 0x000247b3,
1141 0x013, 0x000207a7,
1142 0x013, 0x0001c79b,
1143 0x013, 0x0001839f,
1144 0x013, 0x00014393,
1145 0x013, 0x00010399,
1146 0x013, 0x0000c38d,
1147 0x013, 0x00008199,
1148 0x013, 0x0000418d,
1149 0x013, 0x00000099,
1150 0x015, 0x0000f495,
1151 0x015, 0x0004f495,
1152 0x015, 0x0008f495,
1153 0x016, 0x000e1874,
1154 0x016, 0x000a1874,
1155 0x016, 0x00061874,
1156 0x016, 0x00021874,
1157 0x030, 0x0004470f,
1158 0x031, 0x00044ff0,
1159 0x032, 0x00000070,
1160 0x033, 0x000dd480,
1161 0x034, 0x000ffac0,
1162 0x035, 0x000b80c0,
1163 0x036, 0x00077000,
1164 0x037, 0x00064ff2,
1165 0x038, 0x000e7661,
1166 0x039, 0x00000e90,
1167 0x000, 0x00030000,
1168 0x018, 0x0000f401,
1169 0x0fe, 0x00000000,
1170 0x0fe, 0x00000000,
1171 0x01e, 0x00088009,
1172 0x01f, 0x00080003,
1173 0x0fe, 0x00000000,
1174 0x01e, 0x00088001,
1175 0x01f, 0x00080000,
1176 0x0fe, 0x00000000,
1177 0x018, 0x00087401,
1178 0x0fe, 0x00000000,
1179 0x0fe, 0x00000000,
1180 0x0fe, 0x00000000,
1181 0x02b, 0x00041289,
1182 0x0fe, 0x00000000,
1183 0x02d, 0x00066666,
1184 0x02e, 0x00064001,
1185 0x02d, 0x00091111,
1186 0x02e, 0x00014002,
1187 0x02d, 0x000bbbbb,
1188 0x02e, 0x000b4003,
1189 0x02d, 0x000e6666,
1190 0x02e, 0x00064004,
1191 0x02d, 0x00088888,
1192 0x02e, 0x00084005,
1193 0x02d, 0x0009dddd,
1194 0x02e, 0x000d4006,
1195 0x02d, 0x000b3333,
1196 0x02e, 0x00034007,
1197 0x02d, 0x00048888,
1198 0x02e, 0x00084408,
1199 0x02d, 0x000bbbbb,
1200 0x02e, 0x000b4409,
1201 0x02d, 0x000e6666,
1202 0x02e, 0x0006440a,
1203 0x02d, 0x00011111,
1204 0x02e, 0x0001480b,
1205 0x02d, 0x0003bbbb,
1206 0x02e, 0x000b480c,
1207 0x02d, 0x00066666,
1208 0x02e, 0x0006480d,
1209 0x02d, 0x000ccccc,
1210 0x02e, 0x000c480e,
1211};
1212
1213u32 rtl8192de_mac_2tarray[MAC_2T_ARRAYLENGTH] = {
1214 0x420, 0x00000080,
1215 0x423, 0x00000000,
1216 0x430, 0x00000000,
1217 0x431, 0x00000000,
1218 0x432, 0x00000000,
1219 0x433, 0x00000001,
1220 0x434, 0x00000004,
1221 0x435, 0x00000005,
1222 0x436, 0x00000006,
1223 0x437, 0x00000007,
1224 0x438, 0x00000000,
1225 0x439, 0x00000000,
1226 0x43a, 0x00000000,
1227 0x43b, 0x00000001,
1228 0x43c, 0x00000004,
1229 0x43d, 0x00000005,
1230 0x43e, 0x00000006,
1231 0x43f, 0x00000007,
1232 0x440, 0x00000050,
1233 0x441, 0x00000001,
1234 0x442, 0x00000000,
1235 0x444, 0x00000015,
1236 0x445, 0x000000f0,
1237 0x446, 0x0000000f,
1238 0x447, 0x00000000,
1239 0x462, 0x00000008,
1240 0x463, 0x00000003,
1241 0x4c8, 0x000000ff,
1242 0x4c9, 0x00000008,
1243 0x4cc, 0x000000ff,
1244 0x4cd, 0x000000ff,
1245 0x4ce, 0x00000001,
1246 0x500, 0x00000026,
1247 0x501, 0x000000a2,
1248 0x502, 0x0000002f,
1249 0x503, 0x00000000,
1250 0x504, 0x00000028,
1251 0x505, 0x000000a3,
1252 0x506, 0x0000005e,
1253 0x507, 0x00000000,
1254 0x508, 0x0000002b,
1255 0x509, 0x000000a4,
1256 0x50a, 0x0000005e,
1257 0x50b, 0x00000000,
1258 0x50c, 0x0000004f,
1259 0x50d, 0x000000a4,
1260 0x50e, 0x00000000,
1261 0x50f, 0x00000000,
1262 0x512, 0x0000001c,
1263 0x514, 0x0000000a,
1264 0x515, 0x00000010,
1265 0x516, 0x0000000a,
1266 0x517, 0x00000010,
1267 0x51a, 0x00000016,
1268 0x524, 0x0000000f,
1269 0x525, 0x0000004f,
1270 0x546, 0x00000040,
1271 0x547, 0x00000000,
1272 0x550, 0x00000010,
1273 0x551, 0x00000010,
1274 0x559, 0x00000002,
1275 0x55a, 0x00000002,
1276 0x55d, 0x000000ff,
1277 0x605, 0x00000030,
1278 0x608, 0x0000000e,
1279 0x609, 0x0000002a,
1280 0x652, 0x00000020,
1281 0x63c, 0x0000000a,
1282 0x63d, 0x0000000a,
1283 0x63e, 0x0000000e,
1284 0x63f, 0x0000000e,
1285 0x66e, 0x00000005,
1286 0x700, 0x00000021,
1287 0x701, 0x00000043,
1288 0x702, 0x00000065,
1289 0x703, 0x00000087,
1290 0x708, 0x00000021,
1291 0x709, 0x00000043,
1292 0x70a, 0x00000065,
1293 0x70b, 0x00000087,
1294};
1295
1296u32 rtl8192de_agctab_array[AGCTAB_ARRAYLENGTH] = {
1297 0xc78, 0x7b000001,
1298 0xc78, 0x7b010001,
1299 0xc78, 0x7b020001,
1300 0xc78, 0x7b030001,
1301 0xc78, 0x7b040001,
1302 0xc78, 0x7b050001,
1303 0xc78, 0x7b060001,
1304 0xc78, 0x7a070001,
1305 0xc78, 0x79080001,
1306 0xc78, 0x78090001,
1307 0xc78, 0x770a0001,
1308 0xc78, 0x760b0001,
1309 0xc78, 0x750c0001,
1310 0xc78, 0x740d0001,
1311 0xc78, 0x730e0001,
1312 0xc78, 0x720f0001,
1313 0xc78, 0x71100001,
1314 0xc78, 0x70110001,
1315 0xc78, 0x6f120001,
1316 0xc78, 0x6e130001,
1317 0xc78, 0x6d140001,
1318 0xc78, 0x6c150001,
1319 0xc78, 0x6b160001,
1320 0xc78, 0x6a170001,
1321 0xc78, 0x69180001,
1322 0xc78, 0x68190001,
1323 0xc78, 0x671a0001,
1324 0xc78, 0x661b0001,
1325 0xc78, 0x651c0001,
1326 0xc78, 0x641d0001,
1327 0xc78, 0x631e0001,
1328 0xc78, 0x621f0001,
1329 0xc78, 0x61200001,
1330 0xc78, 0x60210001,
1331 0xc78, 0x49220001,
1332 0xc78, 0x48230001,
1333 0xc78, 0x47240001,
1334 0xc78, 0x46250001,
1335 0xc78, 0x45260001,
1336 0xc78, 0x44270001,
1337 0xc78, 0x43280001,
1338 0xc78, 0x42290001,
1339 0xc78, 0x412a0001,
1340 0xc78, 0x402b0001,
1341 0xc78, 0x262c0001,
1342 0xc78, 0x252d0001,
1343 0xc78, 0x242e0001,
1344 0xc78, 0x232f0001,
1345 0xc78, 0x22300001,
1346 0xc78, 0x21310001,
1347 0xc78, 0x20320001,
1348 0xc78, 0x06330001,
1349 0xc78, 0x05340001,
1350 0xc78, 0x04350001,
1351 0xc78, 0x03360001,
1352 0xc78, 0x02370001,
1353 0xc78, 0x01380001,
1354 0xc78, 0x00390001,
1355 0xc78, 0x003a0001,
1356 0xc78, 0x003b0001,
1357 0xc78, 0x003c0001,
1358 0xc78, 0x003d0001,
1359 0xc78, 0x003e0001,
1360 0xc78, 0x003f0001,
1361 0xc78, 0x7b400001,
1362 0xc78, 0x7b410001,
1363 0xc78, 0x7a420001,
1364 0xc78, 0x79430001,
1365 0xc78, 0x78440001,
1366 0xc78, 0x77450001,
1367 0xc78, 0x76460001,
1368 0xc78, 0x75470001,
1369 0xc78, 0x74480001,
1370 0xc78, 0x73490001,
1371 0xc78, 0x724a0001,
1372 0xc78, 0x714b0001,
1373 0xc78, 0x704c0001,
1374 0xc78, 0x6f4d0001,
1375 0xc78, 0x6e4e0001,
1376 0xc78, 0x6d4f0001,
1377 0xc78, 0x6c500001,
1378 0xc78, 0x6b510001,
1379 0xc78, 0x6a520001,
1380 0xc78, 0x69530001,
1381 0xc78, 0x68540001,
1382 0xc78, 0x67550001,
1383 0xc78, 0x66560001,
1384 0xc78, 0x65570001,
1385 0xc78, 0x64580001,
1386 0xc78, 0x63590001,
1387 0xc78, 0x625a0001,
1388 0xc78, 0x615b0001,
1389 0xc78, 0x605c0001,
1390 0xc78, 0x485d0001,
1391 0xc78, 0x475e0001,
1392 0xc78, 0x465f0001,
1393 0xc78, 0x45600001,
1394 0xc78, 0x44610001,
1395 0xc78, 0x43620001,
1396 0xc78, 0x42630001,
1397 0xc78, 0x41640001,
1398 0xc78, 0x40650001,
1399 0xc78, 0x27660001,
1400 0xc78, 0x26670001,
1401 0xc78, 0x25680001,
1402 0xc78, 0x24690001,
1403 0xc78, 0x236a0001,
1404 0xc78, 0x226b0001,
1405 0xc78, 0x216c0001,
1406 0xc78, 0x206d0001,
1407 0xc78, 0x206e0001,
1408 0xc78, 0x206f0001,
1409 0xc78, 0x20700001,
1410 0xc78, 0x20710001,
1411 0xc78, 0x20720001,
1412 0xc78, 0x20730001,
1413 0xc78, 0x20740001,
1414 0xc78, 0x20750001,
1415 0xc78, 0x20760001,
1416 0xc78, 0x20770001,
1417 0xc78, 0x20780001,
1418 0xc78, 0x20790001,
1419 0xc78, 0x207a0001,
1420 0xc78, 0x207b0001,
1421 0xc78, 0x207c0001,
1422 0xc78, 0x207d0001,
1423 0xc78, 0x207e0001,
1424 0xc78, 0x207f0001,
1425 0xc78, 0x38000002,
1426 0xc78, 0x38010002,
1427 0xc78, 0x38020002,
1428 0xc78, 0x38030002,
1429 0xc78, 0x38040002,
1430 0xc78, 0x38050002,
1431 0xc78, 0x38060002,
1432 0xc78, 0x38070002,
1433 0xc78, 0x38080002,
1434 0xc78, 0x3c090002,
1435 0xc78, 0x3e0a0002,
1436 0xc78, 0x400b0002,
1437 0xc78, 0x440c0002,
1438 0xc78, 0x480d0002,
1439 0xc78, 0x4c0e0002,
1440 0xc78, 0x500f0002,
1441 0xc78, 0x52100002,
1442 0xc78, 0x56110002,
1443 0xc78, 0x5a120002,
1444 0xc78, 0x5e130002,
1445 0xc78, 0x60140002,
1446 0xc78, 0x60150002,
1447 0xc78, 0x60160002,
1448 0xc78, 0x62170002,
1449 0xc78, 0x62180002,
1450 0xc78, 0x62190002,
1451 0xc78, 0x621a0002,
1452 0xc78, 0x621b0002,
1453 0xc78, 0x621c0002,
1454 0xc78, 0x621d0002,
1455 0xc78, 0x621e0002,
1456 0xc78, 0x621f0002,
1457 0xc78, 0x32000044,
1458 0xc78, 0x32010044,
1459 0xc78, 0x32020044,
1460 0xc78, 0x32030044,
1461 0xc78, 0x32040044,
1462 0xc78, 0x32050044,
1463 0xc78, 0x32060044,
1464 0xc78, 0x32070044,
1465 0xc78, 0x32080044,
1466 0xc78, 0x34090044,
1467 0xc78, 0x350a0044,
1468 0xc78, 0x360b0044,
1469 0xc78, 0x370c0044,
1470 0xc78, 0x380d0044,
1471 0xc78, 0x390e0044,
1472 0xc78, 0x3a0f0044,
1473 0xc78, 0x3e100044,
1474 0xc78, 0x42110044,
1475 0xc78, 0x44120044,
1476 0xc78, 0x46130044,
1477 0xc78, 0x4a140044,
1478 0xc78, 0x4e150044,
1479 0xc78, 0x50160044,
1480 0xc78, 0x55170044,
1481 0xc78, 0x5a180044,
1482 0xc78, 0x5e190044,
1483 0xc78, 0x641a0044,
1484 0xc78, 0x6e1b0044,
1485 0xc78, 0x6e1c0044,
1486 0xc78, 0x6e1d0044,
1487 0xc78, 0x6e1e0044,
1488 0xc78, 0x6e1f0044,
1489 0xc78, 0x6e1f0000,
1490};
1491
1492u32 rtl8192de_agctab_5garray[AGCTAB_5G_ARRAYLENGTH] = {
1493 0xc78, 0x7b000001,
1494 0xc78, 0x7b010001,
1495 0xc78, 0x7a020001,
1496 0xc78, 0x79030001,
1497 0xc78, 0x78040001,
1498 0xc78, 0x77050001,
1499 0xc78, 0x76060001,
1500 0xc78, 0x75070001,
1501 0xc78, 0x74080001,
1502 0xc78, 0x73090001,
1503 0xc78, 0x720a0001,
1504 0xc78, 0x710b0001,
1505 0xc78, 0x700c0001,
1506 0xc78, 0x6f0d0001,
1507 0xc78, 0x6e0e0001,
1508 0xc78, 0x6d0f0001,
1509 0xc78, 0x6c100001,
1510 0xc78, 0x6b110001,
1511 0xc78, 0x6a120001,
1512 0xc78, 0x69130001,
1513 0xc78, 0x68140001,
1514 0xc78, 0x67150001,
1515 0xc78, 0x66160001,
1516 0xc78, 0x65170001,
1517 0xc78, 0x64180001,
1518 0xc78, 0x63190001,
1519 0xc78, 0x621a0001,
1520 0xc78, 0x611b0001,
1521 0xc78, 0x601c0001,
1522 0xc78, 0x481d0001,
1523 0xc78, 0x471e0001,
1524 0xc78, 0x461f0001,
1525 0xc78, 0x45200001,
1526 0xc78, 0x44210001,
1527 0xc78, 0x43220001,
1528 0xc78, 0x42230001,
1529 0xc78, 0x41240001,
1530 0xc78, 0x40250001,
1531 0xc78, 0x27260001,
1532 0xc78, 0x26270001,
1533 0xc78, 0x25280001,
1534 0xc78, 0x24290001,
1535 0xc78, 0x232a0001,
1536 0xc78, 0x222b0001,
1537 0xc78, 0x212c0001,
1538 0xc78, 0x202d0001,
1539 0xc78, 0x202e0001,
1540 0xc78, 0x202f0001,
1541 0xc78, 0x20300001,
1542 0xc78, 0x20310001,
1543 0xc78, 0x20320001,
1544 0xc78, 0x20330001,
1545 0xc78, 0x20340001,
1546 0xc78, 0x20350001,
1547 0xc78, 0x20360001,
1548 0xc78, 0x20370001,
1549 0xc78, 0x20380001,
1550 0xc78, 0x20390001,
1551 0xc78, 0x203a0001,
1552 0xc78, 0x203b0001,
1553 0xc78, 0x203c0001,
1554 0xc78, 0x203d0001,
1555 0xc78, 0x203e0001,
1556 0xc78, 0x203f0001,
1557 0xc78, 0x32000044,
1558 0xc78, 0x32010044,
1559 0xc78, 0x32020044,
1560 0xc78, 0x32030044,
1561 0xc78, 0x32040044,
1562 0xc78, 0x32050044,
1563 0xc78, 0x32060044,
1564 0xc78, 0x32070044,
1565 0xc78, 0x32080044,
1566 0xc78, 0x34090044,
1567 0xc78, 0x350a0044,
1568 0xc78, 0x360b0044,
1569 0xc78, 0x370c0044,
1570 0xc78, 0x380d0044,
1571 0xc78, 0x390e0044,
1572 0xc78, 0x3a0f0044,
1573 0xc78, 0x3e100044,
1574 0xc78, 0x42110044,
1575 0xc78, 0x44120044,
1576 0xc78, 0x46130044,
1577 0xc78, 0x4a140044,
1578 0xc78, 0x4e150044,
1579 0xc78, 0x50160044,
1580 0xc78, 0x55170044,
1581 0xc78, 0x5a180044,
1582 0xc78, 0x5e190044,
1583 0xc78, 0x641a0044,
1584 0xc78, 0x6e1b0044,
1585 0xc78, 0x6e1c0044,
1586 0xc78, 0x6e1d0044,
1587 0xc78, 0x6e1e0044,
1588 0xc78, 0x6e1f0044,
1589 0xc78, 0x6e1f0000,
1590};
1591
1592u32 rtl8192de_agctab_2garray[AGCTAB_2G_ARRAYLENGTH] = {
1593 0xc78, 0x7b000001,
1594 0xc78, 0x7b010001,
1595 0xc78, 0x7b020001,
1596 0xc78, 0x7b030001,
1597 0xc78, 0x7b040001,
1598 0xc78, 0x7b050001,
1599 0xc78, 0x7b060001,
1600 0xc78, 0x7a070001,
1601 0xc78, 0x79080001,
1602 0xc78, 0x78090001,
1603 0xc78, 0x770a0001,
1604 0xc78, 0x760b0001,
1605 0xc78, 0x750c0001,
1606 0xc78, 0x740d0001,
1607 0xc78, 0x730e0001,
1608 0xc78, 0x720f0001,
1609 0xc78, 0x71100001,
1610 0xc78, 0x70110001,
1611 0xc78, 0x6f120001,
1612 0xc78, 0x6e130001,
1613 0xc78, 0x6d140001,
1614 0xc78, 0x6c150001,
1615 0xc78, 0x6b160001,
1616 0xc78, 0x6a170001,
1617 0xc78, 0x69180001,
1618 0xc78, 0x68190001,
1619 0xc78, 0x671a0001,
1620 0xc78, 0x661b0001,
1621 0xc78, 0x651c0001,
1622 0xc78, 0x641d0001,
1623 0xc78, 0x631e0001,
1624 0xc78, 0x621f0001,
1625 0xc78, 0x61200001,
1626 0xc78, 0x60210001,
1627 0xc78, 0x49220001,
1628 0xc78, 0x48230001,
1629 0xc78, 0x47240001,
1630 0xc78, 0x46250001,
1631 0xc78, 0x45260001,
1632 0xc78, 0x44270001,
1633 0xc78, 0x43280001,
1634 0xc78, 0x42290001,
1635 0xc78, 0x412a0001,
1636 0xc78, 0x402b0001,
1637 0xc78, 0x262c0001,
1638 0xc78, 0x252d0001,
1639 0xc78, 0x242e0001,
1640 0xc78, 0x232f0001,
1641 0xc78, 0x22300001,
1642 0xc78, 0x21310001,
1643 0xc78, 0x20320001,
1644 0xc78, 0x06330001,
1645 0xc78, 0x05340001,
1646 0xc78, 0x04350001,
1647 0xc78, 0x03360001,
1648 0xc78, 0x02370001,
1649 0xc78, 0x01380001,
1650 0xc78, 0x00390001,
1651 0xc78, 0x003a0001,
1652 0xc78, 0x003b0001,
1653 0xc78, 0x003c0001,
1654 0xc78, 0x003d0001,
1655 0xc78, 0x003e0001,
1656 0xc78, 0x003f0001,
1657 0xc78, 0x38000002,
1658 0xc78, 0x38010002,
1659 0xc78, 0x38020002,
1660 0xc78, 0x38030002,
1661 0xc78, 0x38040002,
1662 0xc78, 0x38050002,
1663 0xc78, 0x38060002,
1664 0xc78, 0x38070002,
1665 0xc78, 0x38080002,
1666 0xc78, 0x3c090002,
1667 0xc78, 0x3e0a0002,
1668 0xc78, 0x400b0002,
1669 0xc78, 0x440c0002,
1670 0xc78, 0x480d0002,
1671 0xc78, 0x4c0e0002,
1672 0xc78, 0x500f0002,
1673 0xc78, 0x52100002,
1674 0xc78, 0x56110002,
1675 0xc78, 0x5a120002,
1676 0xc78, 0x5e130002,
1677 0xc78, 0x60140002,
1678 0xc78, 0x60150002,
1679 0xc78, 0x60160002,
1680 0xc78, 0x62170002,
1681 0xc78, 0x62180002,
1682 0xc78, 0x62190002,
1683 0xc78, 0x621a0002,
1684 0xc78, 0x621b0002,
1685 0xc78, 0x621c0002,
1686 0xc78, 0x621d0002,
1687 0xc78, 0x621e0002,
1688 0xc78, 0x621f0002,
1689 0xc78, 0x6e1f0000,
1690};
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/table.h b/drivers/net/wireless/rtlwifi/rtl8192de/table.h
new file mode 100644
index 000000000000..93f30ca62d8f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/table.h
@@ -0,0 +1,57 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 * Created on 2010/ 5/18, 1:41
29 *****************************************************************************/
30
31#ifndef __RTL92DE_TABLE__H_
32#define __RTL92DE_TABLE__H_
33
34/*Created on 2011/ 1/14, 1:35*/
35
36#define PHY_REG_2T_ARRAYLENGTH 380
37extern u32 rtl8192de_phy_reg_2tarray[PHY_REG_2T_ARRAYLENGTH];
38#define PHY_REG_ARRAY_PG_LENGTH 624
39extern u32 rtl8192de_phy_reg_array_pg[PHY_REG_ARRAY_PG_LENGTH];
40#define RADIOA_2T_ARRAYLENGTH 378
41extern u32 rtl8192de_radioa_2tarray[RADIOA_2T_ARRAYLENGTH];
42#define RADIOB_2T_ARRAYLENGTH 384
43extern u32 rtl8192de_radiob_2tarray[RADIOB_2T_ARRAYLENGTH];
44#define RADIOA_2T_INT_PA_ARRAYLENGTH 378
45extern u32 rtl8192de_radioa_2t_int_paarray[RADIOA_2T_INT_PA_ARRAYLENGTH];
46#define RADIOB_2T_INT_PA_ARRAYLENGTH 384
47extern u32 rtl8192de_radiob_2t_int_paarray[RADIOB_2T_INT_PA_ARRAYLENGTH];
48#define MAC_2T_ARRAYLENGTH 160
49extern u32 rtl8192de_mac_2tarray[MAC_2T_ARRAYLENGTH];
50#define AGCTAB_ARRAYLENGTH 386
51extern u32 rtl8192de_agctab_array[AGCTAB_ARRAYLENGTH];
52#define AGCTAB_5G_ARRAYLENGTH 194
53extern u32 rtl8192de_agctab_5garray[AGCTAB_5G_ARRAYLENGTH];
54#define AGCTAB_2G_ARRAYLENGTH 194
55extern u32 rtl8192de_agctab_2garray[AGCTAB_2G_ARRAYLENGTH];
56
57#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
new file mode 100644
index 000000000000..dc86fcb0b3a3
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.c
@@ -0,0 +1,959 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../base.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "trx.h"
37#include "led.h"
38
39static u8 _rtl92de_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
40{
41 __le16 fc = rtl_get_fc(skb);
42
43 if (unlikely(ieee80211_is_beacon(fc)))
44 return QSLT_BEACON;
45 if (ieee80211_is_mgmt(fc))
46 return QSLT_MGNT;
47
48 return skb->priority;
49}
50
51static int _rtl92de_rate_mapping(bool isht, u8 desc_rate)
52{
53 int rate_idx;
54
55 if (false == isht) {
56 switch (desc_rate) {
57 case DESC92D_RATE1M:
58 rate_idx = 0;
59 break;
60 case DESC92D_RATE2M:
61 rate_idx = 1;
62 break;
63 case DESC92D_RATE5_5M:
64 rate_idx = 2;
65 break;
66 case DESC92D_RATE11M:
67 rate_idx = 3;
68 break;
69 case DESC92D_RATE6M:
70 rate_idx = 4;
71 break;
72 case DESC92D_RATE9M:
73 rate_idx = 5;
74 break;
75 case DESC92D_RATE12M:
76 rate_idx = 6;
77 break;
78 case DESC92D_RATE18M:
79 rate_idx = 7;
80 break;
81 case DESC92D_RATE24M:
82 rate_idx = 8;
83 break;
84 case DESC92D_RATE36M:
85 rate_idx = 9;
86 break;
87 case DESC92D_RATE48M:
88 rate_idx = 10;
89 break;
90 case DESC92D_RATE54M:
91 rate_idx = 11;
92 break;
93 default:
94 rate_idx = 0;
95 break;
96 }
97 return rate_idx;
98 } else {
99 switch (desc_rate) {
100 case DESC92D_RATE1M:
101 rate_idx = 0;
102 break;
103 case DESC92D_RATE2M:
104 rate_idx = 1;
105 break;
106 case DESC92D_RATE5_5M:
107 rate_idx = 2;
108 break;
109 case DESC92D_RATE11M:
110 rate_idx = 3;
111 break;
112 case DESC92D_RATE6M:
113 rate_idx = 4;
114 break;
115 case DESC92D_RATE9M:
116 rate_idx = 5;
117 break;
118 case DESC92D_RATE12M:
119 rate_idx = 6;
120 break;
121 case DESC92D_RATE18M:
122 rate_idx = 7;
123 break;
124 case DESC92D_RATE24M:
125 rate_idx = 8;
126 break;
127 case DESC92D_RATE36M:
128 rate_idx = 9;
129 break;
130 case DESC92D_RATE48M:
131 rate_idx = 10;
132 break;
133 case DESC92D_RATE54M:
134 rate_idx = 11;
135 break;
136 default:
137 rate_idx = 11;
138 break;
139 }
140 return rate_idx;
141 }
142}
143
144static u8 _rtl92d_query_rxpwrpercentage(char antpower)
145{
146 if ((antpower <= -100) || (antpower >= 20))
147 return 0;
148 else if (antpower >= 0)
149 return 100;
150 else
151 return 100 + antpower;
152}
153
154static u8 _rtl92d_evm_db_to_percentage(char value)
155{
156 char ret_val = value;
157
158 if (ret_val >= 0)
159 ret_val = 0;
160 if (ret_val <= -33)
161 ret_val = -33;
162 ret_val = 0 - ret_val;
163 ret_val *= 3;
164 if (ret_val == 99)
165 ret_val = 100;
166 return ret_val;
167}
168
169static long _rtl92de_translate_todbm(struct ieee80211_hw *hw,
170 u8 signal_strength_index)
171{
172 long signal_power;
173
174 signal_power = (long)((signal_strength_index + 1) >> 1);
175 signal_power -= 95;
176 return signal_power;
177}
178
179static long _rtl92de_signal_scale_mapping(struct ieee80211_hw *hw, long currsig)
180{
181 long retsig;
182
183 if (currsig >= 61 && currsig <= 100)
184 retsig = 90 + ((currsig - 60) / 4);
185 else if (currsig >= 41 && currsig <= 60)
186 retsig = 78 + ((currsig - 40) / 2);
187 else if (currsig >= 31 && currsig <= 40)
188 retsig = 66 + (currsig - 30);
189 else if (currsig >= 21 && currsig <= 30)
190 retsig = 54 + (currsig - 20);
191 else if (currsig >= 5 && currsig <= 20)
192 retsig = 42 + (((currsig - 5) * 2) / 3);
193 else if (currsig == 4)
194 retsig = 36;
195 else if (currsig == 3)
196 retsig = 27;
197 else if (currsig == 2)
198 retsig = 18;
199 else if (currsig == 1)
200 retsig = 9;
201 else
202 retsig = currsig;
203 return retsig;
204}
205
206static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw,
207 struct rtl_stats *pstats,
208 struct rx_desc_92d *pdesc,
209 struct rx_fwinfo_92d *p_drvinfo,
210 bool packet_match_bssid,
211 bool packet_toself,
212 bool packet_beacon)
213{
214 struct rtl_priv *rtlpriv = rtl_priv(hw);
215 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
216 struct phy_sts_cck_8192d *cck_buf;
217 s8 rx_pwr_all, rx_pwr[4];
218 u8 rf_rx_num = 0, evm, pwdb_all;
219 u8 i, max_spatial_stream;
220 u32 rssi, total_rssi = 0;
221 bool is_cck_rate;
222
223 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
224 pstats->packet_matchbssid = packet_match_bssid;
225 pstats->packet_toself = packet_toself;
226 pstats->packet_beacon = packet_beacon;
227 pstats->is_cck = is_cck_rate;
228 pstats->rx_mimo_signalquality[0] = -1;
229 pstats->rx_mimo_signalquality[1] = -1;
230
231 if (is_cck_rate) {
232 u8 report, cck_highpwr;
233 cck_buf = (struct phy_sts_cck_8192d *)p_drvinfo;
234 if (ppsc->rfpwr_state == ERFON)
235 cck_highpwr = (u8) rtl_get_bbreg(hw,
236 RFPGA0_XA_HSSIPARAMETER2,
237 BIT(9));
238 else
239 cck_highpwr = false;
240 if (!cck_highpwr) {
241 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
242 report = cck_buf->cck_agc_rpt & 0xc0;
243 report = report >> 6;
244 switch (report) {
245 case 0x3:
246 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
247 break;
248 case 0x2:
249 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
250 break;
251 case 0x1:
252 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
253 break;
254 case 0x0:
255 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
256 break;
257 }
258 } else {
259 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
260 report = p_drvinfo->cfosho[0] & 0x60;
261 report = report >> 5;
262 switch (report) {
263 case 0x3:
264 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
265 break;
266 case 0x2:
267 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
268 break;
269 case 0x1:
270 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
271 break;
272 case 0x0:
273 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
274 break;
275 }
276 }
277 pwdb_all = _rtl92d_query_rxpwrpercentage(rx_pwr_all);
278 /* CCK gain is smaller than OFDM/MCS gain, */
279 /* so we add gain diff by experiences, the val is 6 */
280 pwdb_all += 6;
281 if (pwdb_all > 100)
282 pwdb_all = 100;
283 /* modify the offset to make the same gain index with OFDM. */
284 if (pwdb_all > 34 && pwdb_all <= 42)
285 pwdb_all -= 2;
286 else if (pwdb_all > 26 && pwdb_all <= 34)
287 pwdb_all -= 6;
288 else if (pwdb_all > 14 && pwdb_all <= 26)
289 pwdb_all -= 8;
290 else if (pwdb_all > 4 && pwdb_all <= 14)
291 pwdb_all -= 4;
292 pstats->rx_pwdb_all = pwdb_all;
293 pstats->recvsignalpower = rx_pwr_all;
294 if (packet_match_bssid) {
295 u8 sq;
296 if (pstats->rx_pwdb_all > 40) {
297 sq = 100;
298 } else {
299 sq = cck_buf->sq_rpt;
300 if (sq > 64)
301 sq = 0;
302 else if (sq < 20)
303 sq = 100;
304 else
305 sq = ((64 - sq) * 100) / 44;
306 }
307 pstats->signalquality = sq;
308 pstats->rx_mimo_signalquality[0] = sq;
309 pstats->rx_mimo_signalquality[1] = -1;
310 }
311 } else {
312 rtlpriv->dm.rfpath_rxenable[0] = true;
313 rtlpriv->dm.rfpath_rxenable[1] = true;
314 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
315 if (rtlpriv->dm.rfpath_rxenable[i])
316 rf_rx_num++;
317 rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2)
318 - 110;
319 rssi = _rtl92d_query_rxpwrpercentage(rx_pwr[i]);
320 total_rssi += rssi;
321 rtlpriv->stats.rx_snr_db[i] =
322 (long)(p_drvinfo->rxsnr[i] / 2);
323 if (packet_match_bssid)
324 pstats->rx_mimo_signalstrength[i] = (u8) rssi;
325 }
326 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 106;
327 pwdb_all = _rtl92d_query_rxpwrpercentage(rx_pwr_all);
328 pstats->rx_pwdb_all = pwdb_all;
329 pstats->rxpower = rx_pwr_all;
330 pstats->recvsignalpower = rx_pwr_all;
331 if (pdesc->rxht && pdesc->rxmcs >= DESC92D_RATEMCS8 &&
332 pdesc->rxmcs <= DESC92D_RATEMCS15)
333 max_spatial_stream = 2;
334 else
335 max_spatial_stream = 1;
336 for (i = 0; i < max_spatial_stream; i++) {
337 evm = _rtl92d_evm_db_to_percentage(p_drvinfo->rxevm[i]);
338 if (packet_match_bssid) {
339 if (i == 0)
340 pstats->signalquality =
341 (u8)(evm & 0xff);
342 pstats->rx_mimo_signalquality[i] =
343 (u8)(evm & 0xff);
344 }
345 }
346 }
347 if (is_cck_rate)
348 pstats->signalstrength = (u8)(_rtl92de_signal_scale_mapping(hw,
349 pwdb_all));
350 else if (rf_rx_num != 0)
351 pstats->signalstrength = (u8)(_rtl92de_signal_scale_mapping(hw,
352 total_rssi /= rf_rx_num));
353}
354
355static void rtl92d_loop_over_paths(struct ieee80211_hw *hw,
356 struct rtl_stats *pstats)
357{
358 struct rtl_priv *rtlpriv = rtl_priv(hw);
359 struct rtl_phy *rtlphy = &(rtlpriv->phy);
360 u8 rfpath;
361
362 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
363 rfpath++) {
364 if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
365 rtlpriv->stats.rx_rssi_percentage[rfpath] =
366 pstats->rx_mimo_signalstrength[rfpath];
367
368 }
369 if (pstats->rx_mimo_signalstrength[rfpath] >
370 rtlpriv->stats.rx_rssi_percentage[rfpath]) {
371 rtlpriv->stats.rx_rssi_percentage[rfpath] =
372 ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
373 (RX_SMOOTH_FACTOR - 1)) +
374 (pstats->rx_mimo_signalstrength[rfpath])) /
375 (RX_SMOOTH_FACTOR);
376 rtlpriv->stats.rx_rssi_percentage[rfpath] =
377 rtlpriv->stats.rx_rssi_percentage[rfpath] + 1;
378 } else {
379 rtlpriv->stats.rx_rssi_percentage[rfpath] =
380 ((rtlpriv->stats.rx_rssi_percentage[rfpath] *
381 (RX_SMOOTH_FACTOR - 1)) +
382 (pstats->rx_mimo_signalstrength[rfpath])) /
383 (RX_SMOOTH_FACTOR);
384 }
385 }
386}
387
388static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw,
389 struct rtl_stats *pstats)
390{
391 struct rtl_priv *rtlpriv = rtl_priv(hw);
392 u32 last_rssi, tmpval;
393
394 if (pstats->packet_toself || pstats->packet_beacon) {
395 rtlpriv->stats.rssi_calculate_cnt++;
396 if (rtlpriv->stats.ui_rssi.total_num++ >=
397 PHY_RSSI_SLID_WIN_MAX) {
398 rtlpriv->stats.ui_rssi.total_num =
399 PHY_RSSI_SLID_WIN_MAX;
400 last_rssi = rtlpriv->stats.ui_rssi.elements[
401 rtlpriv->stats.ui_rssi.index];
402 rtlpriv->stats.ui_rssi.total_val -= last_rssi;
403 }
404 rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength;
405 rtlpriv->stats.ui_rssi.elements
406 [rtlpriv->stats.ui_rssi.index++] =
407 pstats->signalstrength;
408 if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
409 rtlpriv->stats.ui_rssi.index = 0;
410 tmpval = rtlpriv->stats.ui_rssi.total_val /
411 rtlpriv->stats.ui_rssi.total_num;
412 rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw,
413 (u8) tmpval);
414 pstats->rssi = rtlpriv->stats.signal_strength;
415 }
416 if (!pstats->is_cck && pstats->packet_toself)
417 rtl92d_loop_over_paths(hw, pstats);
418}
419
420static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw,
421 struct rtl_stats *pstats)
422{
423 struct rtl_priv *rtlpriv = rtl_priv(hw);
424 int weighting = 0;
425
426 if (rtlpriv->stats.recv_signal_power == 0)
427 rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
428 if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power)
429 weighting = 5;
430 else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power)
431 weighting = (-5);
432 rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power *
433 5 + pstats->recvsignalpower + weighting) / 6;
434}
435
436static void _rtl92de_process_pwdb(struct ieee80211_hw *hw,
437 struct rtl_stats *pstats)
438{
439 struct rtl_priv *rtlpriv = rtl_priv(hw);
440 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
441 long undecorated_smoothed_pwdb;
442
443 if (mac->opmode == NL80211_IFTYPE_ADHOC ||
444 mac->opmode == NL80211_IFTYPE_AP)
445 return;
446 else
447 undecorated_smoothed_pwdb =
448 rtlpriv->dm.undecorated_smoothed_pwdb;
449
450 if (pstats->packet_toself || pstats->packet_beacon) {
451 if (undecorated_smoothed_pwdb < 0)
452 undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
453 if (pstats->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
454 undecorated_smoothed_pwdb =
455 (((undecorated_smoothed_pwdb) *
456 (RX_SMOOTH_FACTOR - 1)) +
457 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
458 undecorated_smoothed_pwdb =
459 undecorated_smoothed_pwdb + 1;
460 } else {
461 undecorated_smoothed_pwdb =
462 (((undecorated_smoothed_pwdb) *
463 (RX_SMOOTH_FACTOR - 1)) +
464 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
465 }
466 rtlpriv->dm.undecorated_smoothed_pwdb =
467 undecorated_smoothed_pwdb;
468 _rtl92de_update_rxsignalstatistics(hw, pstats);
469 }
470}
471
472static void rtl92d_loop_over_streams(struct ieee80211_hw *hw,
473 struct rtl_stats *pstats)
474{
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 int stream;
477
478 for (stream = 0; stream < 2; stream++) {
479 if (pstats->rx_mimo_signalquality[stream] != -1) {
480 if (rtlpriv->stats.rx_evm_percentage[stream] == 0) {
481 rtlpriv->stats.rx_evm_percentage[stream] =
482 pstats->rx_mimo_signalquality[stream];
483 }
484 rtlpriv->stats.rx_evm_percentage[stream] =
485 ((rtlpriv->stats.rx_evm_percentage[stream]
486 * (RX_SMOOTH_FACTOR - 1)) +
487 (pstats->rx_mimo_signalquality[stream] * 1)) /
488 (RX_SMOOTH_FACTOR);
489 }
490 }
491}
492
493static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw,
494 struct rtl_stats *pstats)
495{
496 struct rtl_priv *rtlpriv = rtl_priv(hw);
497 u32 last_evm, tmpval;
498
499 if (pstats->signalquality == 0)
500 return;
501 if (pstats->packet_toself || pstats->packet_beacon) {
502 if (rtlpriv->stats.ui_link_quality.total_num++ >=
503 PHY_LINKQUALITY_SLID_WIN_MAX) {
504 rtlpriv->stats.ui_link_quality.total_num =
505 PHY_LINKQUALITY_SLID_WIN_MAX;
506 last_evm = rtlpriv->stats.ui_link_quality.elements[
507 rtlpriv->stats.ui_link_quality.index];
508 rtlpriv->stats.ui_link_quality.total_val -= last_evm;
509 }
510 rtlpriv->stats.ui_link_quality.total_val +=
511 pstats->signalquality;
512 rtlpriv->stats.ui_link_quality.elements[
513 rtlpriv->stats.ui_link_quality.index++] =
514 pstats->signalquality;
515 if (rtlpriv->stats.ui_link_quality.index >=
516 PHY_LINKQUALITY_SLID_WIN_MAX)
517 rtlpriv->stats.ui_link_quality.index = 0;
518 tmpval = rtlpriv->stats.ui_link_quality.total_val /
519 rtlpriv->stats.ui_link_quality.total_num;
520 rtlpriv->stats.signal_quality = tmpval;
521 rtlpriv->stats.last_sigstrength_inpercent = tmpval;
522 rtl92d_loop_over_streams(hw, pstats);
523 }
524}
525
526static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw,
527 u8 *buffer,
528 struct rtl_stats *pcurrent_stats)
529{
530
531 if (!pcurrent_stats->packet_matchbssid &&
532 !pcurrent_stats->packet_beacon)
533 return;
534
535 _rtl92de_process_ui_rssi(hw, pcurrent_stats);
536 _rtl92de_process_pwdb(hw, pcurrent_stats);
537 _rtl92de_process_ui_link_quality(hw, pcurrent_stats);
538}
539
540static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw,
541 struct sk_buff *skb,
542 struct rtl_stats *pstats,
543 struct rx_desc_92d *pdesc,
544 struct rx_fwinfo_92d *p_drvinfo)
545{
546 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
547 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
548 struct ieee80211_hdr *hdr;
549 u8 *tmp_buf;
550 u8 *praddr;
551 u16 type, cfc;
552 __le16 fc;
553 bool packet_matchbssid, packet_toself, packet_beacon;
554
555 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
556 hdr = (struct ieee80211_hdr *)tmp_buf;
557 fc = hdr->frame_control;
558 cfc = le16_to_cpu(fc);
559 type = WLAN_FC_GET_TYPE(fc);
560 praddr = hdr->addr1;
561 packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
562 (!compare_ether_addr(mac->bssid, (cfc & IEEE80211_FCTL_TODS) ?
563 hdr->addr1 : (cfc & IEEE80211_FCTL_FROMDS) ?
564 hdr->addr2 : hdr->addr3)) && (!pstats->hwerror) &&
565 (!pstats->crc) && (!pstats->icv));
566 packet_toself = packet_matchbssid &&
567 (!compare_ether_addr(praddr, rtlefuse->dev_addr));
568 if (ieee80211_is_beacon(fc))
569 packet_beacon = true;
570 _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
571 packet_matchbssid, packet_toself,
572 packet_beacon);
573 _rtl92de_process_phyinfo(hw, tmp_buf, pstats);
574}
575
576bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats,
577 struct ieee80211_rx_status *rx_status,
578 u8 *p_desc, struct sk_buff *skb)
579{
580 struct rx_fwinfo_92d *p_drvinfo;
581 struct rx_desc_92d *pdesc = (struct rx_desc_92d *)p_desc;
582 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
583
584 stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
585 stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
586 RX_DRV_INFO_SIZE_UNIT;
587 stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
588 stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
589 stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
590 stats->hwerror = (stats->crc | stats->icv);
591 stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
592 stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
593 stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
594 stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
595 stats->isfirst_ampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
596 && (GET_RX_DESC_FAGGR(pdesc) == 1));
597 stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
598 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
599 rx_status->freq = hw->conf.channel->center_freq;
600 rx_status->band = hw->conf.channel->band;
601 if (GET_RX_DESC_CRC32(pdesc))
602 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
603 if (!GET_RX_DESC_SWDEC(pdesc))
604 rx_status->flag |= RX_FLAG_DECRYPTED;
605 if (GET_RX_DESC_BW(pdesc))
606 rx_status->flag |= RX_FLAG_40MHZ;
607 if (GET_RX_DESC_RXHT(pdesc))
608 rx_status->flag |= RX_FLAG_HT;
609 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
610 if (stats->decrypted)
611 rx_status->flag |= RX_FLAG_DECRYPTED;
612 rx_status->rate_idx = _rtl92de_rate_mapping((bool)
613 GET_RX_DESC_RXHT(pdesc),
614 (u8)
615 GET_RX_DESC_RXMCS(pdesc));
616 rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
617 if (phystatus) {
618 p_drvinfo = (struct rx_fwinfo_92d *)(skb->data +
619 stats->rx_bufshift);
620 _rtl92de_translate_rx_signal_stuff(hw,
621 skb, stats, pdesc,
622 p_drvinfo);
623 }
624 /*rx_status->qual = stats->signal; */
625 rx_status->signal = stats->rssi + 10;
626 /*rx_status->noise = -stats->noise; */
627 return true;
628}
629
630static void _rtl92de_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
631 u8 *virtualaddress)
632{
633 memset(virtualaddress, 0, 8);
634
635 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
636 SET_EARLYMODE_LEN0(virtualaddress, ptcb_desc->empkt_len[0]);
637 SET_EARLYMODE_LEN1(virtualaddress, ptcb_desc->empkt_len[1]);
638 SET_EARLYMODE_LEN2_1(virtualaddress, ptcb_desc->empkt_len[2] & 0xF);
639 SET_EARLYMODE_LEN2_2(virtualaddress, ptcb_desc->empkt_len[2] >> 4);
640 SET_EARLYMODE_LEN3(virtualaddress, ptcb_desc->empkt_len[3]);
641 SET_EARLYMODE_LEN4(virtualaddress, ptcb_desc->empkt_len[4]);
642}
643
644void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
645 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
646 struct ieee80211_tx_info *info, struct sk_buff *skb,
647 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
648{
649 struct rtl_priv *rtlpriv = rtl_priv(hw);
650 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
651 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
652 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
653 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
654 struct ieee80211_sta *sta = info->control.sta;
655 u8 *pdesc = (u8 *) pdesc_tx;
656 u16 seq_number;
657 __le16 fc = hdr->frame_control;
658 unsigned int buf_len = 0;
659 unsigned int skb_len = skb->len;
660 u8 fw_qsel = _rtl92de_map_hwqueue_to_fwqueue(skb, hw_queue);
661 bool firstseg = ((hdr->seq_ctrl &
662 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
663 bool lastseg = ((hdr->frame_control &
664 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
665 dma_addr_t mapping;
666 u8 bw_40 = 0;
667
668 if (mac->opmode == NL80211_IFTYPE_STATION) {
669 bw_40 = mac->bw_40;
670 } else if (mac->opmode == NL80211_IFTYPE_AP ||
671 mac->opmode == NL80211_IFTYPE_ADHOC) {
672 if (sta)
673 bw_40 = sta->ht_cap.cap &
674 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
675 }
676 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
677 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
678 /* reserve 8 byte for AMPDU early mode */
679 if (rtlhal->earlymode_enable) {
680 skb_push(skb, EM_HDR_LEN);
681 memset(skb->data, 0, EM_HDR_LEN);
682 }
683 buf_len = skb->len;
684 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
685 PCI_DMA_TODEVICE);
686 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92d));
687 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
688 firstseg = true;
689 lastseg = true;
690 }
691 if (firstseg) {
692 if (rtlhal->earlymode_enable) {
693 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
694 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN +
695 EM_HDR_LEN);
696 if (ptcb_desc->empkt_num) {
697 RT_TRACE(rtlpriv, COMP_SEND, DBG_LOUD,
698 ("Insert 8 byte.pTcb->EMPktNum:%d\n",
699 ptcb_desc->empkt_num));
700 _rtl92de_insert_emcontent(ptcb_desc,
701 (u8 *)(skb->data));
702 }
703 } else {
704 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
705 }
706 /* 5G have no CCK rate */
707 if (rtlhal->current_bandtype == BAND_ON_5G)
708 if (ptcb_desc->hw_rate < DESC92D_RATE6M)
709 ptcb_desc->hw_rate = DESC92D_RATE6M;
710 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
711 if (ptcb_desc->use_shortgi || ptcb_desc->use_shortpreamble)
712 SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
713
714 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
715 ptcb_desc->hw_rate == DESC92D_RATEMCS7)
716 SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
717
718 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
719 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
720 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
721 }
722 SET_TX_DESC_SEQ(pdesc, seq_number);
723 SET_TX_DESC_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable &&
724 !ptcb_desc->cts_enable) ? 1 : 0));
725 SET_TX_DESC_HW_RTS_ENABLE(pdesc, ((ptcb_desc->rts_enable
726 || ptcb_desc->cts_enable) ? 1 : 0));
727 SET_TX_DESC_CTS2SELF(pdesc, ((ptcb_desc->cts_enable) ? 1 : 0));
728 SET_TX_DESC_RTS_STBC(pdesc, ((ptcb_desc->rts_stbc) ? 1 : 0));
729 /* 5G have no CCK rate */
730 if (rtlhal->current_bandtype == BAND_ON_5G)
731 if (ptcb_desc->rts_rate < DESC92D_RATE6M)
732 ptcb_desc->rts_rate = DESC92D_RATE6M;
733 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
734 SET_TX_DESC_RTS_BW(pdesc, 0);
735 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
736 SET_TX_DESC_RTS_SHORT(pdesc, ((ptcb_desc->rts_rate <=
737 DESC92D_RATE54M) ?
738 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
739 (ptcb_desc->rts_use_shortgi ? 1 : 0)));
740 if (bw_40) {
741 if (ptcb_desc->packet_bw) {
742 SET_TX_DESC_DATA_BW(pdesc, 1);
743 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
744 } else {
745 SET_TX_DESC_DATA_BW(pdesc, 0);
746 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
747 mac->cur_40_prime_sc);
748 }
749 } else {
750 SET_TX_DESC_DATA_BW(pdesc, 0);
751 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
752 }
753 SET_TX_DESC_LINIP(pdesc, 0);
754 SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb_len);
755 if (sta) {
756 u8 ampdu_density = sta->ht_cap.ampdu_density;
757 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
758 }
759 if (info->control.hw_key) {
760 struct ieee80211_key_conf *keyconf;
761
762 keyconf = info->control.hw_key;
763 switch (keyconf->cipher) {
764 case WLAN_CIPHER_SUITE_WEP40:
765 case WLAN_CIPHER_SUITE_WEP104:
766 case WLAN_CIPHER_SUITE_TKIP:
767 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
768 break;
769 case WLAN_CIPHER_SUITE_CCMP:
770 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
771 break;
772 default:
773 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
774 break;
775
776 }
777 }
778 SET_TX_DESC_PKT_ID(pdesc, 0);
779 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
780 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
781 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
782 SET_TX_DESC_DISABLE_FB(pdesc, ptcb_desc->disable_ratefallback ?
783 1 : 0);
784 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
785
786 /* Set TxRate and RTSRate in TxDesc */
787 /* This prevent Tx initial rate of new-coming packets */
788 /* from being overwritten by retried packet rate.*/
789 if (!ptcb_desc->use_driver_rate) {
790 SET_TX_DESC_RTS_RATE(pdesc, 0x08);
791 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
792 }
793 if (ieee80211_is_data_qos(fc)) {
794 if (mac->rdg_en) {
795 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
796 ("Enable RDG function.\n"));
797 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
798 SET_TX_DESC_HTC(pdesc, 1);
799 }
800 }
801 }
802
803 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
804 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
805 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) buf_len);
806 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
807 if (rtlpriv->dm.useramask) {
808 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
809 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
810 } else {
811 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
812 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
813 }
814 if (ieee80211_is_data_qos(fc))
815 SET_TX_DESC_QOS(pdesc, 1);
816
817 if ((!ieee80211_is_data_qos(fc)) && ppsc->fwctrl_lps) {
818 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
819 SET_TX_DESC_PKT_ID(pdesc, 8);
820 }
821 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
822 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, ("\n"));
823}
824
825void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw,
826 u8 *pdesc, bool firstseg,
827 bool lastseg, struct sk_buff *skb)
828{
829 struct rtl_priv *rtlpriv = rtl_priv(hw);
830 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
831 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
832 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
833 u8 fw_queue = QSLT_BEACON;
834 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
835 skb->data, skb->len, PCI_DMA_TODEVICE);
836 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
837 __le16 fc = hdr->frame_control;
838
839 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
840 if (firstseg)
841 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
842 /* 5G have no CCK rate
843 * Caution: The macros below are multi-line expansions.
844 * The braces are needed no matter what checkpatch says
845 */
846 if (rtlhal->current_bandtype == BAND_ON_5G) {
847 SET_TX_DESC_TX_RATE(pdesc, DESC92D_RATE6M);
848 } else {
849 SET_TX_DESC_TX_RATE(pdesc, DESC92D_RATE1M);
850 }
851 SET_TX_DESC_SEQ(pdesc, 0);
852 SET_TX_DESC_LINIP(pdesc, 0);
853 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
854 SET_TX_DESC_FIRST_SEG(pdesc, 1);
855 SET_TX_DESC_LAST_SEG(pdesc, 1);
856 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) (skb->len));
857 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
858 SET_TX_DESC_RATE_ID(pdesc, 7);
859 SET_TX_DESC_MACID(pdesc, 0);
860 SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
861 SET_TX_DESC_FIRST_SEG(pdesc, 1);
862 SET_TX_DESC_LAST_SEG(pdesc, 1);
863 SET_TX_DESC_OFFSET(pdesc, 0x20);
864 SET_TX_DESC_USE_RATE(pdesc, 1);
865
866 if (!ieee80211_is_data_qos(fc) && ppsc->fwctrl_lps) {
867 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
868 SET_TX_DESC_PKT_ID(pdesc, 8);
869 }
870
871 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
872 "H2C Tx Cmd Content\n", pdesc, TX_DESC_SIZE);
873 wmb();
874 SET_TX_DESC_OWN(pdesc, 1);
875}
876
877void rtl92de_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
878{
879 if (istx) {
880 switch (desc_name) {
881 case HW_DESC_OWN:
882 wmb();
883 SET_TX_DESC_OWN(pdesc, 1);
884 break;
885 case HW_DESC_TX_NEXTDESC_ADDR:
886 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val);
887 break;
888 default:
889 RT_ASSERT(false, ("ERR txdesc :%d"
890 " not process\n", desc_name));
891 break;
892 }
893 } else {
894 switch (desc_name) {
895 case HW_DESC_RXOWN:
896 wmb();
897 SET_RX_DESC_OWN(pdesc, 1);
898 break;
899 case HW_DESC_RXBUFF_ADDR:
900 SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val);
901 break;
902 case HW_DESC_RXPKT_LEN:
903 SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val);
904 break;
905 case HW_DESC_RXERO:
906 SET_RX_DESC_EOR(pdesc, 1);
907 break;
908 default:
909 RT_ASSERT(false, ("ERR rxdesc :%d "
910 "not process\n", desc_name));
911 break;
912 }
913 }
914}
915
916u32 rtl92de_get_desc(u8 *p_desc, bool istx, u8 desc_name)
917{
918 u32 ret = 0;
919
920 if (istx) {
921 switch (desc_name) {
922 case HW_DESC_OWN:
923 ret = GET_TX_DESC_OWN(p_desc);
924 break;
925 case HW_DESC_TXBUFF_ADDR:
926 ret = GET_TX_DESC_TX_BUFFER_ADDRESS(p_desc);
927 break;
928 default:
929 RT_ASSERT(false, ("ERR txdesc :%d "
930 "not process\n", desc_name));
931 break;
932 }
933 } else {
934 struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
935 switch (desc_name) {
936 case HW_DESC_OWN:
937 ret = GET_RX_DESC_OWN(pdesc);
938 break;
939 case HW_DESC_RXPKT_LEN:
940 ret = GET_RX_DESC_PKT_LEN(pdesc);
941 break;
942 default:
943 RT_ASSERT(false, ("ERR rxdesc :%d "
944 "not process\n", desc_name));
945 break;
946 }
947 }
948 return ret;
949}
950
951void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
952{
953 struct rtl_priv *rtlpriv = rtl_priv(hw);
954 if (hw_queue == BEACON_QUEUE)
955 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
956 else
957 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
958 BIT(0) << (hw_queue));
959}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
new file mode 100644
index 000000000000..992d6766e667
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/trx.h
@@ -0,0 +1,756 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92DE_TRX_H__
31#define __RTL92DE_TRX_H__
32
33#define TX_DESC_SIZE 64
34#define TX_DESC_AGGR_SUBFRAME_SIZE 32
35
36#define RX_DESC_SIZE 32
37#define RX_DRV_INFO_SIZE_UNIT 8
38
39#define TX_DESC_NEXT_DESC_OFFSET 40
40#define USB_HWDESC_HEADER_LEN 32
41#define CRCLENGTH 4
42
43/* Define a macro that takes a le32 word, converts it to host ordering,
44 * right shifts by a specified count, creates a mask of the specified
45 * bit count, and extracts that number of bits.
46 */
47
48#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
49 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
50 BIT_LEN_MASK_32(__mask))
51
52/* Define a macro that clears a bit field in an le32 word and
53 * sets the specified value into that bit field. The resulting
54 * value remains in le32 ordering; however, it is properly converted
55 * to host ordering for the clear and set operations before conversion
56 * back to le32.
57 */
58
59#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
60 (*(__le32 *)(__pdesc) = \
61 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
62 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
63 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
64
65/* macros to read/write various fields in RX or TX descriptors */
66
67#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
68 SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
69#define SET_TX_DESC_OFFSET(__pdesc, __val) \
70 SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
71#define SET_TX_DESC_BMC(__pdesc, __val) \
72 SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
73#define SET_TX_DESC_HTC(__pdesc, __val) \
74 SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
75#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
76 SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
77#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
78 SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
79#define SET_TX_DESC_LINIP(__pdesc, __val) \
80 SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
81#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
82 SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
83#define SET_TX_DESC_GF(__pdesc, __val) \
84 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
85#define SET_TX_DESC_OWN(__pdesc, __val) \
86 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
87
88#define GET_TX_DESC_PKT_SIZE(__pdesc) \
89 SHIFT_AND_MASK_LE(__pdesc, 0, 16)
90#define GET_TX_DESC_OFFSET(__pdesc) \
91 SHIFT_AND_MASK_LE(__pdesc, 16, 8)
92#define GET_TX_DESC_BMC(__pdesc) \
93 SHIFT_AND_MASK_LE(__pdesc, 24, 1)
94#define GET_TX_DESC_HTC(__pdesc) \
95 SHIFT_AND_MASK_LE(__pdesc, 25, 1)
96#define GET_TX_DESC_LAST_SEG(__pdesc) \
97 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
98#define GET_TX_DESC_FIRST_SEG(__pdesc) \
99 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
100#define GET_TX_DESC_LINIP(__pdesc) \
101 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
102#define GET_TX_DESC_NO_ACM(__pdesc) \
103 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
104#define GET_TX_DESC_GF(__pdesc) \
105 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
106#define GET_TX_DESC_OWN(__pdesc) \
107 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
108
109#define SET_TX_DESC_MACID(__pdesc, __val) \
110 SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
111#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
112 SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
113#define SET_TX_DESC_BK(__pdesc, __val) \
114 SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
115#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
116 SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
117#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
118 SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
119#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
120 SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
121#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
122 SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
123#define SET_TX_DESC_PIFS(__pdesc, __val) \
124 SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
125#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
126 SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
127#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
128 SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
129#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
130 SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
131#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
132 SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
133#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
134 SET_BITS_OFFSET_LE(__pdesc+4, 26, 8, __val)
135
136#define GET_TX_DESC_MACID(__pdesc) \
137 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
138#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
139 SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
140#define GET_TX_DESC_AGG_BREAK(__pdesc) \
141 SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
142#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
143 SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
144#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
145 SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
146#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
147 SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
148#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
149 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
150#define GET_TX_DESC_PIFS(__pdesc) \
151 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
152#define GET_TX_DESC_RATE_ID(__pdesc) \
153 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
154#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
155 SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
156#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
157 SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
158#define GET_TX_DESC_SEC_TYPE(__pdesc) \
159 SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
160#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
161 SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
162
163#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
164 SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
165#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
166 SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
167#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
168 SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
169#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
170 SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
171#define SET_TX_DESC_RAW(__pdesc, __val) \
172 SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
173#define SET_TX_DESC_CCX(__pdesc, __val) \
174 SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
175#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
176 SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
177#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
178 SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
179#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
180 SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
181#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
182 SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
183#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
184 SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
185#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
186 SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
187
188#define GET_TX_DESC_RTS_RC(__pdesc) \
189 SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
190#define GET_TX_DESC_DATA_RC(__pdesc) \
191 SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
192#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
193 SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
194#define GET_TX_DESC_MORE_FRAG(__pdesc) \
195 SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
196#define GET_TX_DESC_RAW(__pdesc) \
197 SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
198#define GET_TX_DESC_CCX(__pdesc) \
199 SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
200#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
201 SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
202#define GET_TX_DESC_ANTSEL_A(__pdesc) \
203 SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
204#define GET_TX_DESC_ANTSEL_B(__pdesc) \
205 SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
206#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
207 SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
208#define GET_TX_DESC_TX_ANTL(__pdesc) \
209 SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
210#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
211 SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
212
213#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
214 SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
215#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
216 SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
217#define SET_TX_DESC_SEQ(__pdesc, __val) \
218 SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
219#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
220 SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
221
222#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
223 SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
224#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
225 SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
226#define GET_TX_DESC_SEQ(__pdesc) \
227 SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
228#define GET_TX_DESC_PKT_ID(__pdesc) \
229 SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
230
231#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
232 SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
233#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
234 SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
235#define SET_TX_DESC_QOS(__pdesc, __val) \
236 SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
237#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
238 SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
239#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
240 SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
241#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
242 SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
243#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
244 SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
245#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
246 SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
247#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
248 SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
249#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
250 SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
251#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
252 SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
253#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
254 SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
255#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
256 SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
257#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
258 SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
259#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
260 SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
261#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
262 SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
263#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
264 SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
265#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
266 SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
267#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
268 SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
269#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
270 SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
271#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
272 SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
273
274#define GET_TX_DESC_RTS_RATE(__pdesc) \
275 SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
276#define GET_TX_DESC_AP_DCFE(__pdesc) \
277 SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
278#define GET_TX_DESC_QOS(__pdesc) \
279 SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
280#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
281 SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
282#define GET_TX_DESC_USE_RATE(__pdesc) \
283 SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
284#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
285 SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
286#define GET_TX_DESC_DISABLE_FB(__pdesc) \
287 SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
288#define GET_TX_DESC_CTS2SELF(__pdesc) \
289 SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
290#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
291 SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
292#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
293 SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
294#define GET_TX_DESC_PORT_ID(__pdesc) \
295 SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
296#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
297 SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
298#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
299 SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
300#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
301 SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
302#define GET_TX_DESC_TX_STBC(__pdesc) \
303 SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
304#define GET_TX_DESC_DATA_SHORT(__pdesc) \
305 SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
306#define GET_TX_DESC_DATA_BW(__pdesc) \
307 SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
308#define GET_TX_DESC_RTS_SHORT(__pdesc) \
309 SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
310#define GET_TX_DESC_RTS_BW(__pdesc) \
311 SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
312#define GET_TX_DESC_RTS_SC(__pdesc) \
313 SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
314#define GET_TX_DESC_RTS_STBC(__pdesc) \
315 SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
316
317#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
318 SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
319#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
320 SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
321#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
322 SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
323#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
324 SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
325#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
326 SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
327#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
328 SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
329#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
330 SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
331#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
332 SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
333
334#define GET_TX_DESC_TX_RATE(__pdesc) \
335 SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
336#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
337 SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
338#define GET_TX_DESC_CCX_TAG(__pdesc) \
339 SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
340#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
341 SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
342#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
343 SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
344#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
345 SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
346#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
347 SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
348#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
349 SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
350
351#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
352 SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
353#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
354 SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
355#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
356 SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
357#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
358 SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
359#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
360 SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
361#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
362 SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
363#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
364 SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
365#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
366 SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
367
368#define GET_TX_DESC_TXAGC_A(__pdesc) \
369 SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
370#define GET_TX_DESC_TXAGC_B(__pdesc) \
371 SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
372#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
373 SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
374#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
375 SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
376#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
377 SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
378#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
379 SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
380#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
381 SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
382#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
383 SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
384
385#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
386 SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
387#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
388 SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
389#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
390 SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
391#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
392 SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
393#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
394 SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
395
396#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
397 SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
398#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
399 SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
400#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
401 SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
402#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
403 SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
404#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
405 SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
406
407#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
408 SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
409#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
410 SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
411
412#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
413 SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
414#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
415 SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
416
417#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
418 SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
419#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
420 SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
421
422#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
423 SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
424#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
425 SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
426
427#define GET_RX_DESC_PKT_LEN(__pdesc) \
428 SHIFT_AND_MASK_LE(__pdesc, 0, 14)
429#define GET_RX_DESC_CRC32(__pdesc) \
430 SHIFT_AND_MASK_LE(__pdesc, 14, 1)
431#define GET_RX_DESC_ICV(__pdesc) \
432 SHIFT_AND_MASK_LE(__pdesc, 15, 1)
433#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
434 SHIFT_AND_MASK_LE(__pdesc, 16, 4)
435#define GET_RX_DESC_SECURITY(__pdesc) \
436 SHIFT_AND_MASK_LE(__pdesc, 20, 3)
437#define GET_RX_DESC_QOS(__pdesc) \
438 SHIFT_AND_MASK_LE(__pdesc, 23, 1)
439#define GET_RX_DESC_SHIFT(__pdesc) \
440 SHIFT_AND_MASK_LE(__pdesc, 24, 2)
441#define GET_RX_DESC_PHYST(__pdesc) \
442 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
443#define GET_RX_DESC_SWDEC(__pdesc) \
444 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
445#define GET_RX_DESC_LS(__pdesc) \
446 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
447#define GET_RX_DESC_FS(__pdesc) \
448 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
449#define GET_RX_DESC_EOR(__pdesc) \
450 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
451#define GET_RX_DESC_OWN(__pdesc) \
452 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
453
454#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
455 SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
456#define SET_RX_DESC_EOR(__pdesc, __val) \
457 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
458#define SET_RX_DESC_OWN(__pdesc, __val) \
459 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
460
461#define GET_RX_DESC_MACID(__pdesc) \
462 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
463#define GET_RX_DESC_TID(__pdesc) \
464 SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
465#define GET_RX_DESC_HWRSVD(__pdesc) \
466 SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
467#define GET_RX_DESC_PAGGR(__pdesc) \
468 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
469#define GET_RX_DESC_FAGGR(__pdesc) \
470 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
471#define GET_RX_DESC_A1_FIT(__pdesc) \
472 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
473#define GET_RX_DESC_A2_FIT(__pdesc) \
474 SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
475#define GET_RX_DESC_PAM(__pdesc) \
476 SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
477#define GET_RX_DESC_PWR(__pdesc) \
478 SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
479#define GET_RX_DESC_MD(__pdesc) \
480 SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
481#define GET_RX_DESC_MF(__pdesc) \
482 SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
483#define GET_RX_DESC_TYPE(__pdesc) \
484 SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
485#define GET_RX_DESC_MC(__pdesc) \
486 SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
487#define GET_RX_DESC_BC(__pdesc) \
488 SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
489#define GET_RX_DESC_SEQ(__pdesc) \
490 SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
491#define GET_RX_DESC_FRAG(__pdesc) \
492 SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
493#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
494 SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
495#define GET_RX_DESC_NEXT_IND(__pdesc) \
496 SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
497#define GET_RX_DESC_RSVD(__pdesc) \
498 SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
499
500#define GET_RX_DESC_RXMCS(__pdesc) \
501 SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
502#define GET_RX_DESC_RXHT(__pdesc) \
503 SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
504#define GET_RX_DESC_SPLCP(__pdesc) \
505 SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
506#define GET_RX_DESC_BW(__pdesc) \
507 SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
508#define GET_RX_DESC_HTC(__pdesc) \
509 SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
510#define GET_RX_DESC_HWPC_ERR(__pdesc) \
511 SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
512#define GET_RX_DESC_HWPC_IND(__pdesc) \
513 SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
514#define GET_RX_DESC_IV0(__pdesc) \
515 SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
516
517#define GET_RX_DESC_IV1(__pdesc) \
518 SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
519#define GET_RX_DESC_TSFL(__pdesc) \
520 SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
521
522#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
523 SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
524#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
525 SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
526
527#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
528 SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
529#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
530 SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
531
532#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
533do { \
534 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
535 memset((void *)__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
536 else \
537 memset((void *)__pdesc, 0, _size); \
538} while (0);
539
540#define RX_HAL_IS_CCK_RATE(_pdesc)\
541 (_pdesc->rxmcs == DESC92D_RATE1M || \
542 _pdesc->rxmcs == DESC92D_RATE2M || \
543 _pdesc->rxmcs == DESC92D_RATE5_5M || \
544 _pdesc->rxmcs == DESC92D_RATE11M)
545
546/* For 92D early mode */
547#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
548 SET_BITS_OFFSET_LE(__paddr, 0, 3, __value)
549#define SET_EARLYMODE_LEN0(__paddr, __value) \
550 SET_BITS_OFFSET_LE(__paddr, 4, 12, __value)
551#define SET_EARLYMODE_LEN1(__paddr, __value) \
552 SET_BITS_OFFSET_LE(__paddr, 16, 12, __value)
553#define SET_EARLYMODE_LEN2_1(__paddr, __value) \
554 SET_BITS_OFFSET_LE(__paddr, 28, 4, __value)
555#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
556 SET_BITS_OFFSET_LE(__paddr+4, 0, 8, __value)
557#define SET_EARLYMODE_LEN3(__paddr, __value) \
558 SET_BITS_OFFSET_LE(__paddr+4, 8, 12, __value)
559#define SET_EARLYMODE_LEN4(__paddr, __value) \
560 SET_BITS_OFFSET_LE(__paddr+4, 20, 12, __value)
561
562struct rx_fwinfo_92d {
563 u8 gain_trsw[4];
564 u8 pwdb_all;
565 u8 cfosho[4];
566 u8 cfotail[4];
567 char rxevm[2];
568 char rxsnr[4];
569 u8 pdsnr[2];
570 u8 csi_current[2];
571 u8 csi_target[2];
572 u8 sigevm;
573 u8 max_ex_pwr;
574 u8 ex_intf_flag:1;
575 u8 sgi_en:1;
576 u8 rxsc:2;
577 u8 reserve:4;
578} __packed;
579
580struct tx_desc_92d {
581 u32 pktsize:16;
582 u32 offset:8;
583 u32 bmc:1;
584 u32 htc:1;
585 u32 lastseg:1;
586 u32 firstseg:1;
587 u32 linip:1;
588 u32 noacm:1;
589 u32 gf:1;
590 u32 own:1;
591
592 u32 macid:5;
593 u32 agg_en:1;
594 u32 bk:1;
595 u32 rdg_en:1;
596 u32 queuesel:5;
597 u32 rd_nav_ext:1;
598 u32 lsig_txop_en:1;
599 u32 pifs:1;
600 u32 rateid:4;
601 u32 nav_usehdr:1;
602 u32 en_descid:1;
603 u32 sectype:2;
604 u32 pktoffset:8;
605
606 u32 rts_rc:6;
607 u32 data_rc:6;
608 u32 rsvd0:2;
609 u32 bar_retryht:2;
610 u32 rsvd1:1;
611 u32 morefrag:1;
612 u32 raw:1;
613 u32 ccx:1;
614 u32 ampdudensity:3;
615 u32 rsvd2:1;
616 u32 ant_sela:1;
617 u32 ant_selb:1;
618 u32 txant_cck:2;
619 u32 txant_l:2;
620 u32 txant_ht:2;
621
622 u32 nextheadpage:8;
623 u32 tailpage:8;
624 u32 seq:12;
625 u32 pktid:4;
626
627 u32 rtsrate:5;
628 u32 apdcfe:1;
629 u32 qos:1;
630 u32 hwseq_enable:1;
631 u32 userrate:1;
632 u32 dis_rtsfb:1;
633 u32 dis_datafb:1;
634 u32 cts2self:1;
635 u32 rts_en:1;
636 u32 hwrts_en:1;
637 u32 portid:1;
638 u32 rsvd3:3;
639 u32 waitdcts:1;
640 u32 cts2ap_en:1;
641 u32 txsc:2;
642 u32 stbc:2;
643 u32 txshort:1;
644 u32 txbw:1;
645 u32 rtsshort:1;
646 u32 rtsbw:1;
647 u32 rtssc:2;
648 u32 rtsstbc:2;
649
650 u32 txrate:6;
651 u32 shortgi:1;
652 u32 ccxt:1;
653 u32 txrate_fb_lmt:5;
654 u32 rtsrate_fb_lmt:4;
655 u32 retrylmt_en:1;
656 u32 txretrylmt:6;
657 u32 usb_txaggnum:8;
658
659 u32 txagca:5;
660 u32 txagcb:5;
661 u32 usemaxlen:1;
662 u32 maxaggnum:5;
663 u32 mcsg1maxlen:4;
664 u32 mcsg2maxlen:4;
665 u32 mcsg3maxlen:4;
666 u32 mcs7sgimaxlen:4;
667
668 u32 txbuffersize:16;
669 u32 mcsg4maxlen:4;
670 u32 mcsg5maxlen:4;
671 u32 mcsg6maxlen:4;
672 u32 mcsg15sgimaxlen:4;
673
674 u32 txbuffaddr;
675 u32 txbufferaddr64;
676 u32 nextdescaddress;
677 u32 nextdescaddress64;
678
679 u32 reserve_pass_pcie_mm_limit[4];
680} __packed;
681
682struct rx_desc_92d {
683 u32 length:14;
684 u32 crc32:1;
685 u32 icverror:1;
686 u32 drv_infosize:4;
687 u32 security:3;
688 u32 qos:1;
689 u32 shift:2;
690 u32 phystatus:1;
691 u32 swdec:1;
692 u32 lastseg:1;
693 u32 firstseg:1;
694 u32 eor:1;
695 u32 own:1;
696
697 u32 macid:5;
698 u32 tid:4;
699 u32 hwrsvd:5;
700 u32 paggr:1;
701 u32 faggr:1;
702 u32 a1_fit:4;
703 u32 a2_fit:4;
704 u32 pam:1;
705 u32 pwr:1;
706 u32 moredata:1;
707 u32 morefrag:1;
708 u32 type:2;
709 u32 mc:1;
710 u32 bc:1;
711
712 u32 seq:12;
713 u32 frag:4;
714 u32 nextpktlen:14;
715 u32 nextind:1;
716 u32 rsvd:1;
717
718 u32 rxmcs:6;
719 u32 rxht:1;
720 u32 amsdu:1;
721 u32 splcp:1;
722 u32 bandwidth:1;
723 u32 htc:1;
724 u32 tcpchk_rpt:1;
725 u32 ipcchk_rpt:1;
726 u32 tcpchk_valid:1;
727 u32 hwpcerr:1;
728 u32 hwpcind:1;
729 u32 iv0:16;
730
731 u32 iv1;
732
733 u32 tsfl;
734
735 u32 bufferaddress;
736 u32 bufferaddress64;
737
738} __packed;
739
740void rtl92de_tx_fill_desc(struct ieee80211_hw *hw,
741 struct ieee80211_hdr *hdr,
742 u8 *pdesc, struct ieee80211_tx_info *info,
743 struct sk_buff *skb, u8 hw_queue,
744 struct rtl_tcb_desc *ptcb_desc);
745bool rtl92de_rx_query_desc(struct ieee80211_hw *hw,
746 struct rtl_stats *stats,
747 struct ieee80211_rx_status *rx_status,
748 u8 *pdesc, struct sk_buff *skb);
749void rtl92de_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val);
750u32 rtl92de_get_desc(u8 *pdesc, bool istx, u8 desc_name);
751void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
752void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
753 bool b_firstseg, bool b_lastseg,
754 struct sk_buff *skb);
755
756#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/dm.c b/drivers/net/wireless/rtlwifi/rtl8192se/dm.c
index da86db86fa4a..4203a8531ca0 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/dm.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/dm.c
@@ -222,7 +222,6 @@ static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
222 u32 low_rssi_thresh = 0; 222 u32 low_rssi_thresh = 0;
223 u32 middle_rssi_thresh = 0; 223 u32 middle_rssi_thresh = 0;
224 u32 high_rssi_thresh = 0; 224 u32 high_rssi_thresh = 0;
225 u8 rssi_level;
226 struct ieee80211_sta *sta = NULL; 225 struct ieee80211_sta *sta = NULL;
227 226
228 if (is_hal_stop(rtlhal)) 227 if (is_hal_stop(rtlhal))
@@ -272,18 +271,14 @@ static void _rtl92s_dm_refresh_rateadaptive_mask(struct ieee80211_hw *hw)
272 if (rtlpriv->dm.undecorated_smoothed_pwdb > 271 if (rtlpriv->dm.undecorated_smoothed_pwdb >
273 (long)high_rssi_thresh) { 272 (long)high_rssi_thresh) {
274 ra->ratr_state = DM_RATR_STA_HIGH; 273 ra->ratr_state = DM_RATR_STA_HIGH;
275 rssi_level = 1;
276 } else if (rtlpriv->dm.undecorated_smoothed_pwdb > 274 } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
277 (long)middle_rssi_thresh) { 275 (long)middle_rssi_thresh) {
278 ra->ratr_state = DM_RATR_STA_LOW; 276 ra->ratr_state = DM_RATR_STA_LOW;
279 rssi_level = 3;
280 } else if (rtlpriv->dm.undecorated_smoothed_pwdb > 277 } else if (rtlpriv->dm.undecorated_smoothed_pwdb >
281 (long)low_rssi_thresh) { 278 (long)low_rssi_thresh) {
282 ra->ratr_state = DM_RATR_STA_LOW; 279 ra->ratr_state = DM_RATR_STA_LOW;
283 rssi_level = 5;
284 } else { 280 } else {
285 ra->ratr_state = DM_RATR_STA_ULTRALOW; 281 ra->ratr_state = DM_RATR_STA_ULTRALOW;
286 rssi_level = 6;
287 } 282 }
288 283
289 if (ra->pre_ratr_state != ra->ratr_state) { 284 if (ra->pre_ratr_state != ra->ratr_state) {
@@ -457,7 +452,7 @@ static void _rtl92s_dm_initial_gain_sta_beforeconnect(struct ieee80211_hw *hw)
457 if (rtlpriv->psc.rfpwr_state != ERFON) 452 if (rtlpriv->psc.rfpwr_state != ERFON)
458 return; 453 return;
459 454
460 if (digtable.backoff_enable_flag == true) 455 if (digtable.backoff_enable_flag)
461 rtl92s_backoff_enable_flag(hw); 456 rtl92s_backoff_enable_flag(hw);
462 else 457 else
463 digtable.backoff_val = DM_DIG_BACKOFF; 458 digtable.backoff_val = DM_DIG_BACKOFF;
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/fw.c b/drivers/net/wireless/rtlwifi/rtl8192se/fw.c
index 3b5af0113d7f..6f91a148c222 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/fw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/fw.c
@@ -358,7 +358,6 @@ int rtl92s_download_fw(struct ieee80211_hw *hw)
358 struct fw_priv *pfw_priv = NULL; 358 struct fw_priv *pfw_priv = NULL;
359 u8 *puc_mappedfile = NULL; 359 u8 *puc_mappedfile = NULL;
360 u32 ul_filelength = 0; 360 u32 ul_filelength = 0;
361 u32 file_length = 0;
362 u8 fwhdr_size = RT_8192S_FIRMWARE_HDR_SIZE; 361 u8 fwhdr_size = RT_8192S_FIRMWARE_HDR_SIZE;
363 u8 fwstatus = FW_STATUS_INIT; 362 u8 fwstatus = FW_STATUS_INIT;
364 bool rtstatus = true; 363 bool rtstatus = true;
@@ -370,7 +369,6 @@ int rtl92s_download_fw(struct ieee80211_hw *hw)
370 firmware->fwstatus = FW_STATUS_INIT; 369 firmware->fwstatus = FW_STATUS_INIT;
371 370
372 puc_mappedfile = firmware->sz_fw_tmpbuffer; 371 puc_mappedfile = firmware->sz_fw_tmpbuffer;
373 file_length = firmware->sz_fw_tmpbufferlen;
374 372
375 /* 1. Retrieve FW header. */ 373 /* 1. Retrieve FW header. */
376 firmware->pfwheader = (struct fw_hdr *) puc_mappedfile; 374 firmware->pfwheader = (struct fw_hdr *) puc_mappedfile;
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/hw.c b/drivers/net/wireless/rtlwifi/rtl8192se/hw.c
index 2e9005d0454b..d59f66cb7768 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/hw.c
@@ -27,6 +27,8 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include "../wifi.h" 32#include "../wifi.h"
31#include "../efuse.h" 33#include "../efuse.h"
32#include "../base.h" 34#include "../base.h"
@@ -465,8 +467,7 @@ static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
465 if ((tmpvalue & BIT(6))) 467 if ((tmpvalue & BIT(6)))
466 break; 468 break;
467 469
468 printk(KERN_ERR "wait for BIT(6) return value %x\n", 470 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
469 tmpvalue);
470 if (waitcount == 0) 471 if (waitcount == 0)
471 break; 472 break;
472 473
@@ -516,7 +517,7 @@ static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
516 mdelay(10); 517 mdelay(10);
517 518
518 /* check GPIO3 */ 519 /* check GPIO3 */
519 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN); 520 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
520 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF; 521 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
521 522
522 return retval; 523 return retval;
@@ -884,12 +885,10 @@ static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
884 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 885 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
885 886
886 u8 reg_bw_opmode = 0; 887 u8 reg_bw_opmode = 0;
887 u32 reg_ratr = 0, reg_rrsr = 0; 888 u32 reg_rrsr = 0;
888 u8 regtmp = 0; 889 u8 regtmp = 0;
889 890
890 reg_bw_opmode = BW_OPMODE_20MHZ; 891 reg_bw_opmode = BW_OPMODE_20MHZ;
891 reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
892 RATE_ALL_OFDM_2SS;
893 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG; 892 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
894 893
895 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL); 894 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
@@ -996,7 +995,8 @@ int rtl92se_hw_init(struct ieee80211_hw *hw)
996 995
997 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT; 996 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
998 rtlpriv->psc.rfpwr_state = ERFON; 997 rtlpriv->psc.rfpwr_state = ERFON;
999 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason, true); 998 /* FIXME: check spinlocks if this block is uncommented */
999 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason);
1000 } else { 1000 } else {
1001 /* gpio radio on/off is out of adapter start */ 1001 /* gpio radio on/off is out of adapter start */
1002 if (rtlpriv->psc.hwradiooff == false) { 1002 if (rtlpriv->psc.hwradiooff == false) {
@@ -1107,7 +1107,7 @@ void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1107 if (rtlpriv->psc.rfpwr_state != ERFON) 1107 if (rtlpriv->psc.rfpwr_state != ERFON)
1108 return; 1108 return;
1109 1109
1110 if (check_bssid == true) { 1110 if (check_bssid) {
1111 reg_rcr |= (RCR_CBSSID); 1111 reg_rcr |= (RCR_CBSSID);
1112 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr)); 1112 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1113 } else if (check_bssid == false) { 1113 } else if (check_bssid == false) {
@@ -1122,14 +1122,12 @@ static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1122{ 1122{
1123 struct rtl_priv *rtlpriv = rtl_priv(hw); 1123 struct rtl_priv *rtlpriv = rtl_priv(hw);
1124 u8 bt_msr = rtl_read_byte(rtlpriv, MSR); 1124 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1125 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1126 u32 temp; 1125 u32 temp;
1127 bt_msr &= ~MSR_LINK_MASK; 1126 bt_msr &= ~MSR_LINK_MASK;
1128 1127
1129 switch (type) { 1128 switch (type) {
1130 case NL80211_IFTYPE_UNSPECIFIED: 1129 case NL80211_IFTYPE_UNSPECIFIED:
1131 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT); 1130 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1132 ledaction = LED_CTL_LINK;
1133 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1131 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1134 ("Set Network type to NO LINK!\n")); 1132 ("Set Network type to NO LINK!\n"));
1135 break; 1133 break;
@@ -1140,7 +1138,6 @@ static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1140 break; 1138 break;
1141 case NL80211_IFTYPE_STATION: 1139 case NL80211_IFTYPE_STATION:
1142 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT); 1140 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1143 ledaction = LED_CTL_LINK;
1144 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 1141 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1145 ("Set Network type to STA!\n")); 1142 ("Set Network type to STA!\n"));
1146 break; 1143 break;
@@ -1218,8 +1215,6 @@ void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1218 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]); 1215 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1219 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */ 1216 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1220 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F); 1217 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1221
1222 rtlpci->irq_enabled = true;
1223} 1218}
1224 1219
1225void rtl92se_disable_interrupt(struct ieee80211_hw *hw) 1220void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
@@ -1230,7 +1225,7 @@ void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1230 rtl_write_dword(rtlpriv, INTA_MASK, 0); 1225 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1231 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0); 1226 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1232 1227
1233 rtlpci->irq_enabled = false; 1228 synchronize_irq(rtlpci->pdev->irq);
1234} 1229}
1235 1230
1236 1231
@@ -1261,8 +1256,7 @@ static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1261 if ((tmp & BIT(6))) 1256 if ((tmp & BIT(6)))
1262 break; 1257 break;
1263 1258
1264 printk(KERN_ERR "wait for BIT(6) return value %x\n", 1259 pr_err("wait for BIT(6) return value %x\n", tmp);
1265 tmp);
1266 1260
1267 if (waitcnt == 0) 1261 if (waitcnt == 0)
1268 break; 1262 break;
@@ -1321,7 +1315,7 @@ static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1321 if (u1btmp & BIT(7)) { 1315 if (u1btmp & BIT(7)) {
1322 u1btmp &= ~(BIT(6) | BIT(7)); 1316 u1btmp &= ~(BIT(6) | BIT(7));
1323 if (!_rtl92s_set_sysclk(hw, u1btmp)) { 1317 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1324 printk(KERN_ERR "Switch ctrl path fail\n"); 1318 pr_err("Switch ctrl path fail\n");
1325 return; 1319 return;
1326 } 1320 }
1327 } 1321 }
@@ -1655,7 +1649,7 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1655 rtlefuse->autoload_failflag = false; 1649 rtlefuse->autoload_failflag = false;
1656 } 1650 }
1657 1651
1658 if (rtlefuse->autoload_failflag == true) 1652 if (rtlefuse->autoload_failflag)
1659 return; 1653 return;
1660 1654
1661 _rtl8192se_get_IC_Inferiority(hw); 1655 _rtl8192se_get_IC_Inferiority(hw);
@@ -1688,7 +1682,7 @@ static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1688 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); 1682 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1689 1683
1690 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1684 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1691 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr))); 1685 ("%pM\n", rtlefuse->dev_addr));
1692 1686
1693 /* Get Tx Power Level by Channel */ 1687 /* Get Tx Power Level by Channel */
1694 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */ 1688 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
@@ -2271,7 +2265,7 @@ bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2271 struct rtl_priv *rtlpriv = rtl_priv(hw); 2265 struct rtl_priv *rtlpriv = rtl_priv(hw);
2272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 2266 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 2267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2274 enum rf_pwrstate rfpwr_toset, cur_rfstate; 2268 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2275 unsigned long flag = 0; 2269 unsigned long flag = 0;
2276 bool actuallyset = false; 2270 bool actuallyset = false;
2277 bool turnonbypowerdomain = false; 2271 bool turnonbypowerdomain = false;
@@ -2292,7 +2286,7 @@ bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2292 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 2286 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2293 } 2287 }
2294 2288
2295 cur_rfstate = ppsc->rfpwr_state; 2289 /* cur_rfstate = ppsc->rfpwr_state;*/
2296 2290
2297 /* because after _rtl92s_phy_set_rfhalt, all power 2291 /* because after _rtl92s_phy_set_rfhalt, all power
2298 * closed, so we must open some power for GPIO check, 2292 * closed, so we must open some power for GPIO check,
@@ -2305,7 +2299,7 @@ bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2305 2299
2306 rfpwr_toset = _rtl92se_rf_onoff_detect(hw); 2300 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2307 2301
2308 if ((ppsc->hwradiooff == true) && (rfpwr_toset == ERFON)) { 2302 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2309 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 2303 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2310 ("RFKILL-HW Radio ON, RF ON\n")); 2304 ("RFKILL-HW Radio ON, RF ON\n"));
2311 2305
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/led.c b/drivers/net/wireless/rtlwifi/rtl8192se/led.c
index 6d4f66616680..e3fe7c90ebf4 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/led.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/led.c
@@ -90,7 +90,7 @@ void rtl92se_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
90 break; 90 break;
91 case LED_PIN_LED0: 91 case LED_PIN_LED0:
92 ledcfg &= 0xf0; 92 ledcfg &= 0xf0;
93 if (pcipriv->ledctl.led_opendrain == true) 93 if (pcipriv->ledctl.led_opendrain)
94 rtl_write_byte(rtlpriv, LEDCFG, (ledcfg | BIT(1))); 94 rtl_write_byte(rtlpriv, LEDCFG, (ledcfg | BIT(1)));
95 else 95 else
96 rtl_write_byte(rtlpriv, LEDCFG, (ledcfg | BIT(3))); 96 rtl_write_byte(rtlpriv, LEDCFG, (ledcfg | BIT(3)));
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/phy.c b/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
index 63b45e60a95e..f27171af979c 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
@@ -27,6 +27,8 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include "../wifi.h" 32#include "../wifi.h"
31#include "../pci.h" 33#include "../pci.h"
32#include "../ps.h" 34#include "../ps.h"
@@ -180,19 +182,18 @@ u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
180{ 182{
181 struct rtl_priv *rtlpriv = rtl_priv(hw); 183 struct rtl_priv *rtlpriv = rtl_priv(hw);
182 u32 original_value, readback_value, bitshift; 184 u32 original_value, readback_value, bitshift;
183 unsigned long flags;
184 185
185 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), " 186 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
186 "bitmask(%#x)\n", regaddr, rfpath, bitmask)); 187 "bitmask(%#x)\n", regaddr, rfpath, bitmask));
187 188
188 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 189 spin_lock(&rtlpriv->locks.rf_lock);
189 190
190 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr); 191 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
191 192
192 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); 193 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
193 readback_value = (original_value & bitmask) >> bitshift; 194 readback_value = (original_value & bitmask) >> bitshift;
194 195
195 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 196 spin_unlock(&rtlpriv->locks.rf_lock);
196 197
197 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), " 198 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
198 "bitmask(%#x), original_value(%#x)\n", regaddr, rfpath, 199 "bitmask(%#x), original_value(%#x)\n", regaddr, rfpath,
@@ -207,7 +208,6 @@ void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
207 struct rtl_priv *rtlpriv = rtl_priv(hw); 208 struct rtl_priv *rtlpriv = rtl_priv(hw);
208 struct rtl_phy *rtlphy = &(rtlpriv->phy); 209 struct rtl_phy *rtlphy = &(rtlpriv->phy);
209 u32 original_value, bitshift; 210 u32 original_value, bitshift;
210 unsigned long flags;
211 211
212 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1)) 212 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
213 return; 213 return;
@@ -215,7 +215,7 @@ void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
215 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x)," 215 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
216 " data(%#x), rfpath(%#x)\n", regaddr, bitmask, data, rfpath)); 216 " data(%#x), rfpath(%#x)\n", regaddr, bitmask, data, rfpath));
217 217
218 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 218 spin_lock(&rtlpriv->locks.rf_lock);
219 219
220 if (bitmask != RFREG_OFFSET_MASK) { 220 if (bitmask != RFREG_OFFSET_MASK) {
221 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, 221 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
@@ -226,7 +226,7 @@ void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
226 226
227 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data); 227 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
228 228
229 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 229 spin_unlock(&rtlpriv->locks.rf_lock);
230 230
231 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x), " 231 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x), "
232 "data(%#x), rfpath(%#x)\n", regaddr, bitmask, data, rfpath)); 232 "data(%#x), rfpath(%#x)\n", regaddr, bitmask, data, rfpath));
@@ -263,7 +263,6 @@ void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
263 struct rtl_phy *rtlphy = &(rtlpriv->phy); 263 struct rtl_phy *rtlphy = &(rtlpriv->phy);
264 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 264 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
265 u8 reg_bw_opmode; 265 u8 reg_bw_opmode;
266 u8 reg_prsr_rsc;
267 266
268 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("Switch to %s bandwidth\n", 267 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("Switch to %s bandwidth\n",
269 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? 268 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
@@ -277,7 +276,8 @@ void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
277 rtlphy->set_bwmode_inprogress = true; 276 rtlphy->set_bwmode_inprogress = true;
278 277
279 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE); 278 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
280 reg_prsr_rsc = rtl_read_byte(rtlpriv, RRSR + 2); 279 /* dummy read */
280 rtl_read_byte(rtlpriv, RRSR + 2);
281 281
282 switch (rtlphy->current_chan_bw) { 282 switch (rtlphy->current_chan_bw) {
283 case HT_CHANNEL_WIDTH_20: 283 case HT_CHANNEL_WIDTH_20:
@@ -546,8 +546,6 @@ bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
546 if (rfpwr_state == ppsc->rfpwr_state) 546 if (rfpwr_state == ppsc->rfpwr_state)
547 return false; 547 return false;
548 548
549 ppsc->set_rfpowerstate_inprogress = true;
550
551 switch (rfpwr_state) { 549 switch (rfpwr_state) {
552 case ERFON:{ 550 case ERFON:{
553 if ((ppsc->rfpwr_state == ERFOFF) && 551 if ((ppsc->rfpwr_state == ERFOFF) &&
@@ -659,8 +657,6 @@ bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
659 if (bresult) 657 if (bresult)
660 ppsc->rfpwr_state = rfpwr_state; 658 ppsc->rfpwr_state = rfpwr_state;
661 659
662 ppsc->set_rfpowerstate_inprogress = false;
663
664 return bresult; 660 return bresult;
665} 661}
666 662
@@ -1022,8 +1018,7 @@ static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
1022 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); 1018 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
1023 1019
1024 if (rtstatus != true) { 1020 if (rtstatus != true) {
1025 printk(KERN_ERR "_rtl92s_phy_bb_config_parafile(): " 1021 pr_err("%s(): AGC Table Fail\n", __func__);
1026 "AGC Table Fail\n");
1027 goto phy_BB8190_Config_ParaFile_Fail; 1022 goto phy_BB8190_Config_ParaFile_Fail;
1028 } 1023 }
1029 1024
@@ -1422,7 +1417,7 @@ static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1422 break; 1417 break;
1423 case FW_CMD_HIGH_PWR_ENABLE: 1418 case FW_CMD_HIGH_PWR_ENABLE:
1424 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1419 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1425 (rtlpriv->dm.dynamic_txpower_enable == true)) 1420 rtlpriv->dm.dynamic_txpower_enable)
1426 break; 1421 break;
1427 1422
1428 /* CCA threshold */ 1423 /* CCA threshold */
@@ -1614,7 +1609,7 @@ bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1614 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1609 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1615 1610
1616 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1611 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1617 (rtlpriv->dm.dynamic_txpower_enable == true)) 1612 rtlpriv->dm.dynamic_txpower_enable)
1618 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1613 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1619 1614
1620 if ((digtable.dig_ext_port_stage == 1615 if ((digtable.dig_ext_port_stage ==
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/reg.h b/drivers/net/wireless/rtlwifi/rtl8192se/reg.h
index 0116eaddbfac..ea32ef2d4098 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/reg.h
@@ -248,12 +248,8 @@
248#define PSTIME 0x02E0 248#define PSTIME 0x02E0
249#define TIMER0 0x02E4 249#define TIMER0 0x02E4
250#define TIMER1 0x02E8 250#define TIMER1 0x02E8
251#define GPIO_CTRL 0x02EC 251#define GPIO_IN_SE 0x02EC
252#define GPIO_IN 0x02EC
253#define GPIO_OUT 0x02ED
254#define GPIO_IO_SEL 0x02EE 252#define GPIO_IO_SEL 0x02EE
255#define GPIO_MOD 0x02EF
256#define GPIO_INTCTRL 0x02F0
257#define MAC_PINMUX_CFG 0x02F1 253#define MAC_PINMUX_CFG 0x02F1
258#define LEDCFG 0x02F2 254#define LEDCFG 0x02F2
259#define PHY_REG 0x02F3 255#define PHY_REG 0x02F3
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/rf.c b/drivers/net/wireless/rtlwifi/rtl8192se/rf.c
index 1d3a48330399..0ad50fe44aa2 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/rf.c
@@ -27,6 +27,8 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include "../wifi.h" 32#include "../wifi.h"
31#include "reg.h" 33#include "reg.h"
32#include "def.h" 34#include "def.h"
@@ -410,7 +412,7 @@ void rtl92s_phy_rf6052_set_ccktxpower(struct ieee80211_hw *hw, u8 pwrlevel)
410 (rtlefuse->eeprom_regulatory != 0))) 412 (rtlefuse->eeprom_regulatory != 0)))
411 dont_inc_cck_or_turboscanoff = true; 413 dont_inc_cck_or_turboscanoff = true;
412 414
413 if (mac->act_scanning == true) { 415 if (mac->act_scanning) {
414 txagc = 0x3f; 416 txagc = 0x3f;
415 if (dont_inc_cck_or_turboscanoff) 417 if (dont_inc_cck_or_turboscanoff)
416 txagc = pwrlevel; 418 txagc = pwrlevel;
@@ -507,7 +509,7 @@ bool rtl92s_phy_rf6052_config(struct ieee80211_hw *hw)
507 } 509 }
508 510
509 if (rtstatus != true) { 511 if (rtstatus != true) {
510 printk(KERN_ERR "Radio[%d] Fail!!", rfpath); 512 pr_err("Radio[%d] Fail!!\n", rfpath);
511 goto fail; 513 goto fail;
512 } 514 }
513 515
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/sw.c b/drivers/net/wireless/rtlwifi/rtl8192se/sw.c
index 1c6cb1d7d660..3876078a63de 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/sw.c
@@ -27,6 +27,8 @@
27 * 27 *
28 *****************************************************************************/ 28 *****************************************************************************/
29 29
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
30#include <linux/vmalloc.h> 32#include <linux/vmalloc.h>
31 33
32#include "../wifi.h" 34#include "../wifi.h"
@@ -183,8 +185,8 @@ static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
183 return 1; 185 return 1;
184 } 186 }
185 187
186 printk(KERN_INFO "rtl8192se: Driver for Realtek RTL8192SE/RTL8191SE\n" 188 pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
187 " Loading firmware %s\n", rtlpriv->cfg->fw_name); 189 "Loading firmware %s\n", rtlpriv->cfg->fw_name);
188 /* request fw */ 190 /* request fw */
189 err = request_firmware(&firmware, rtlpriv->cfg->fw_name, 191 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
190 rtlpriv->io.dev); 192 rtlpriv->io.dev);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/trx.c b/drivers/net/wireless/rtlwifi/rtl8192se/trx.c
index 5cf442373d46..cffe30851f79 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/trx.c
@@ -581,7 +581,6 @@ static void _rtl92se_translate_rx_signal_stuff(struct ieee80211_hw *hw,
581 struct ieee80211_hdr *hdr; 581 struct ieee80211_hdr *hdr;
582 u8 *tmp_buf; 582 u8 *tmp_buf;
583 u8 *praddr; 583 u8 *praddr;
584 u8 *psaddr;
585 __le16 fc; 584 __le16 fc;
586 u16 type, cfc; 585 u16 type, cfc;
587 bool packet_matchbssid, packet_toself, packet_beacon; 586 bool packet_matchbssid, packet_toself, packet_beacon;
@@ -593,7 +592,6 @@ static void _rtl92se_translate_rx_signal_stuff(struct ieee80211_hw *hw,
593 cfc = le16_to_cpu(fc); 592 cfc = le16_to_cpu(fc);
594 type = WLAN_FC_GET_TYPE(fc); 593 type = WLAN_FC_GET_TYPE(fc);
595 praddr = hdr->addr1; 594 praddr = hdr->addr1;
596 psaddr = hdr->addr2;
597 595
598 packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) && 596 packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
599 (!compare_ether_addr(mac->bssid, (cfc & IEEE80211_FCTL_TODS) ? 597 (!compare_ether_addr(mac->bssid, (cfc & IEEE80211_FCTL_TODS) ?
@@ -663,7 +661,7 @@ bool rtl92se_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats,
663 661
664 662
665 rx_status->mactime = GET_RX_STATUS_DESC_TSFL(pdesc); 663 rx_status->mactime = GET_RX_STATUS_DESC_TSFL(pdesc);
666 if (phystatus == true) { 664 if (phystatus) {
667 p_drvinfo = (struct rx_fwinfo *)(skb->data + 665 p_drvinfo = (struct rx_fwinfo *)(skb->data +
668 stats->rx_bufshift); 666 stats->rx_bufshift);
669 _rtl92se_translate_rx_signal_stuff(hw, skb, stats, pdesc, 667 _rtl92se_translate_rx_signal_stuff(hw, skb, stats, pdesc,
@@ -875,6 +873,7 @@ void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
875 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len)); 873 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
876 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping)); 874 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
877 875
876 wmb();
878 SET_TX_DESC_OWN(pdesc, 1); 877 SET_TX_DESC_OWN(pdesc, 1);
879 } else { /* H2C Command Desc format (Host TXCMD) */ 878 } else { /* H2C Command Desc format (Host TXCMD) */
880 /* 92SE must set as 1 for firmware download HW DMA error */ 879 /* 92SE must set as 1 for firmware download HW DMA error */
@@ -893,6 +892,7 @@ void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
893 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len)); 892 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
894 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping)); 893 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
895 894
895 wmb();
896 SET_TX_DESC_OWN(pdesc, 1); 896 SET_TX_DESC_OWN(pdesc, 1);
897 897
898 } 898 }
@@ -900,9 +900,10 @@ void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
900 900
901void rtl92se_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val) 901void rtl92se_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
902{ 902{
903 if (istx == true) { 903 if (istx) {
904 switch (desc_name) { 904 switch (desc_name) {
905 case HW_DESC_OWN: 905 case HW_DESC_OWN:
906 wmb();
906 SET_TX_DESC_OWN(pdesc, 1); 907 SET_TX_DESC_OWN(pdesc, 1);
907 break; 908 break;
908 case HW_DESC_TX_NEXTDESC_ADDR: 909 case HW_DESC_TX_NEXTDESC_ADDR:
@@ -916,6 +917,7 @@ void rtl92se_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
916 } else { 917 } else {
917 switch (desc_name) { 918 switch (desc_name) {
918 case HW_DESC_RXOWN: 919 case HW_DESC_RXOWN:
920 wmb();
919 SET_RX_STATUS_DESC_OWN(pdesc, 1); 921 SET_RX_STATUS_DESC_OWN(pdesc, 1);
920 break; 922 break;
921 case HW_DESC_RXBUFF_ADDR: 923 case HW_DESC_RXBUFF_ADDR:
@@ -939,7 +941,7 @@ u32 rtl92se_get_desc(u8 *desc, bool istx, u8 desc_name)
939{ 941{
940 u32 ret = 0; 942 u32 ret = 0;
941 943
942 if (istx == true) { 944 if (istx) {
943 switch (desc_name) { 945 switch (desc_name) {
944 case HW_DESC_OWN: 946 case HW_DESC_OWN:
945 ret = GET_TX_DESC_OWN(desc); 947 ret = GET_TX_DESC_OWN(desc);
diff --git a/drivers/net/wireless/rtlwifi/usb.c b/drivers/net/wireless/rtlwifi/usb.c
index a9367eba1ea7..8b1cef0ffde6 100644
--- a/drivers/net/wireless/rtlwifi/usb.c
+++ b/drivers/net/wireless/rtlwifi/usb.c
@@ -24,6 +24,9 @@
24 * Hsinchu 300, Taiwan. 24 * Hsinchu 300, Taiwan.
25 * 25 *
26 *****************************************************************************/ 26 *****************************************************************************/
27
28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
27#include <linux/usb.h> 30#include <linux/usb.h>
28#include "core.h" 31#include "core.h"
29#include "wifi.h" 32#include "wifi.h"
@@ -104,9 +107,8 @@ static int _usbctrl_vendorreq_sync_read(struct usb_device *udev, u8 request,
104 pdata, len, 0); /* max. timeout */ 107 pdata, len, 0); /* max. timeout */
105 108
106 if (status < 0) 109 if (status < 0)
107 printk(KERN_ERR "reg 0x%x, usbctrl_vendorreq TimeOut! " 110 pr_err("reg 0x%x, usbctrl_vendorreq TimeOut! status:0x%x value=0x%x\n",
108 "status:0x%x value=0x%x\n", value, status, 111 value, status, *(u32 *)pdata);
109 *(u32 *)pdata);
110 return status; 112 return status;
111} 113}
112 114
@@ -316,7 +318,7 @@ static int _rtl_usb_init_rx(struct ieee80211_hw *hw)
316 rtlusb->usb_rx_segregate_hdl = 318 rtlusb->usb_rx_segregate_hdl =
317 rtlpriv->cfg->usb_interface_cfg->usb_rx_segregate_hdl; 319 rtlpriv->cfg->usb_interface_cfg->usb_rx_segregate_hdl;
318 320
319 printk(KERN_INFO "rtl8192cu: rx_max_size %d, rx_urb_num %d, in_ep %d\n", 321 pr_info("rx_max_size %d, rx_urb_num %d, in_ep %d\n",
320 rtlusb->rx_max_size, rtlusb->rx_urb_num, rtlusb->in_ep); 322 rtlusb->rx_max_size, rtlusb->rx_urb_num, rtlusb->in_ep);
321 init_usb_anchor(&rtlusb->rx_submitted); 323 init_usb_anchor(&rtlusb->rx_submitted);
322 return 0; 324 return 0;
@@ -580,7 +582,7 @@ static void _rtl_rx_completed(struct urb *_urb)
580 } else{ 582 } else{
581 /* TO DO */ 583 /* TO DO */
582 _rtl_rx_pre_process(hw, skb); 584 _rtl_rx_pre_process(hw, skb);
583 printk(KERN_ERR "rtlwifi: rx agg not supported\n"); 585 pr_err("rx agg not supported\n");
584 } 586 }
585 goto resubmit; 587 goto resubmit;
586 } 588 }
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index 693395ee98f9..d3c3ffd38984 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -32,7 +32,6 @@
32 32
33#include <linux/sched.h> 33#include <linux/sched.h>
34#include <linux/firmware.h> 34#include <linux/firmware.h>
35#include <linux/version.h>
36#include <linux/etherdevice.h> 35#include <linux/etherdevice.h>
37#include <linux/vmalloc.h> 36#include <linux/vmalloc.h>
38#include <linux/usb.h> 37#include <linux/usb.h>
@@ -303,9 +302,6 @@ enum hw_variables {
303 HW_VAR_DATA_FILTER, 302 HW_VAR_DATA_FILTER,
304}; 303};
305 304
306#define HWSET_MAX_SIZE 128
307#define EFUSE_MAX_SECTION 16
308
309enum _RT_MEDIA_STATUS { 305enum _RT_MEDIA_STATUS {
310 RT_MEDIA_DISCONNECT = 0, 306 RT_MEDIA_DISCONNECT = 0,
311 RT_MEDIA_CONNECT = 1 307 RT_MEDIA_CONNECT = 1
@@ -938,7 +934,7 @@ struct rtl_mac {
938 int n_channels; 934 int n_channels;
939 int n_bitrates; 935 int n_bitrates;
940 936
941 bool offchan_deley; 937 bool offchan_delay;
942 938
943 /*filters */ 939 /*filters */
944 u32 rx_conf; 940 u32 rx_conf;
@@ -1188,7 +1184,6 @@ struct rtl_efuse {
1188 1184
1189struct rtl_ps_ctl { 1185struct rtl_ps_ctl {
1190 bool pwrdomain_protect; 1186 bool pwrdomain_protect;
1191 bool set_rfpowerstate_inprogress;
1192 bool in_powersavemode; 1187 bool in_powersavemode;
1193 bool rfchange_inprogress; 1188 bool rfchange_inprogress;
1194 bool swrf_processing; 1189 bool swrf_processing;
@@ -1536,6 +1531,7 @@ struct rtl_works {
1536 /* For SW LPS */ 1531 /* For SW LPS */
1537 struct delayed_work ps_work; 1532 struct delayed_work ps_work;
1538 struct delayed_work ps_rfon_wq; 1533 struct delayed_work ps_rfon_wq;
1534 struct tasklet_struct ips_leave_tasklet;
1539}; 1535};
1540 1536
1541struct rtl_debug { 1537struct rtl_debug {
@@ -1983,7 +1979,7 @@ static inline u16 rtl_get_tid(struct sk_buff *skb)
1983 1979
1984static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw, 1980static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
1985 struct ieee80211_vif *vif, 1981 struct ieee80211_vif *vif,
1986 u8 *bssid) 1982 const u8 *bssid)
1987{ 1983{
1988 return ieee80211_find_sta(vif, bssid); 1984 return ieee80211_find_sta(vif, bssid);
1989} 1985}
diff --git a/drivers/net/wireless/wl1251/sdio.c b/drivers/net/wireless/wl1251/sdio.c
index f51a0241a440..f78694295c39 100644
--- a/drivers/net/wireless/wl1251/sdio.c
+++ b/drivers/net/wireless/wl1251/sdio.c
@@ -19,6 +19,7 @@
19 * Copyright (C) 2008 Google Inc 19 * Copyright (C) 2008 Google Inc
20 * Copyright (C) 2009 Bob Copeland (me@bobcopeland.com) 20 * Copyright (C) 2009 Bob Copeland (me@bobcopeland.com)
21 */ 21 */
22#include <linux/interrupt.h>
22#include <linux/module.h> 23#include <linux/module.h>
23#include <linux/mod_devicetable.h> 24#include <linux/mod_devicetable.h>
24#include <linux/mmc/sdio_func.h> 25#include <linux/mmc/sdio_func.h>
diff --git a/drivers/net/wireless/wl1251/spi.c b/drivers/net/wireless/wl1251/spi.c
index af6448c4d3e2..eaa5f9556200 100644
--- a/drivers/net/wireless/wl1251/spi.c
+++ b/drivers/net/wireless/wl1251/spi.c
@@ -19,6 +19,7 @@
19 * 19 *
20 */ 20 */
21 21
22#include <linux/interrupt.h>
22#include <linux/irq.h> 23#include <linux/irq.h>
23#include <linux/module.h> 24#include <linux/module.h>
24#include <linux/slab.h> 25#include <linux/slab.h>
diff --git a/drivers/net/wireless/wl12xx/Kconfig b/drivers/net/wireless/wl12xx/Kconfig
index 35ce7b0f4a60..07bcb1548d8b 100644
--- a/drivers/net/wireless/wl12xx/Kconfig
+++ b/drivers/net/wireless/wl12xx/Kconfig
@@ -11,7 +11,6 @@ config WL12XX
11 depends on WL12XX_MENU && GENERIC_HARDIRQS 11 depends on WL12XX_MENU && GENERIC_HARDIRQS
12 depends on INET 12 depends on INET
13 select FW_LOADER 13 select FW_LOADER
14 select CRC7
15 ---help--- 14 ---help---
16 This module adds support for wireless adapters based on TI wl1271 and 15 This module adds support for wireless adapters based on TI wl1271 and
17 TI wl1273 chipsets. This module does *not* include support for wl1251. 16 TI wl1273 chipsets. This module does *not* include support for wl1251.
@@ -33,6 +32,7 @@ config WL12XX_HT
33config WL12XX_SPI 32config WL12XX_SPI
34 tristate "TI wl12xx SPI support" 33 tristate "TI wl12xx SPI support"
35 depends on WL12XX && SPI_MASTER 34 depends on WL12XX && SPI_MASTER
35 select CRC7
36 ---help--- 36 ---help---
37 This module adds support for the SPI interface of adapters using 37 This module adds support for the SPI interface of adapters using
38 TI wl12xx chipsets. Select this if your platform is using 38 TI wl12xx chipsets. Select this if your platform is using
diff --git a/drivers/net/wireless/wl12xx/acx.c b/drivers/net/wireless/wl12xx/acx.c
index c6ee530e5bf7..7e33f1f4f3d4 100644
--- a/drivers/net/wireless/wl12xx/acx.c
+++ b/drivers/net/wireless/wl12xx/acx.c
@@ -25,7 +25,6 @@
25 25
26#include <linux/module.h> 26#include <linux/module.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/crc7.h>
29#include <linux/spi/spi.h> 28#include <linux/spi/spi.h>
30#include <linux/slab.h> 29#include <linux/slab.h>
31 30
@@ -91,7 +90,7 @@ int wl1271_acx_tx_power(struct wl1271 *wl, int power)
91 struct acx_current_tx_power *acx; 90 struct acx_current_tx_power *acx;
92 int ret; 91 int ret;
93 92
94 wl1271_debug(DEBUG_ACX, "acx dot11_cur_tx_pwr"); 93 wl1271_debug(DEBUG_ACX, "acx dot11_cur_tx_pwr %d", power);
95 94
96 if (power < 0 || power > 25) 95 if (power < 0 || power > 25)
97 return -EINVAL; 96 return -EINVAL;
@@ -1068,6 +1067,7 @@ int wl1271_acx_sta_mem_cfg(struct wl1271 *wl)
1068 mem_conf->tx_free_req = mem->min_req_tx_blocks; 1067 mem_conf->tx_free_req = mem->min_req_tx_blocks;
1069 mem_conf->rx_free_req = mem->min_req_rx_blocks; 1068 mem_conf->rx_free_req = mem->min_req_rx_blocks;
1070 mem_conf->tx_min = mem->tx_min; 1069 mem_conf->tx_min = mem->tx_min;
1070 mem_conf->fwlog_blocks = wl->conf.fwlog.mem_blocks;
1071 1071
1072 ret = wl1271_cmd_configure(wl, ACX_MEM_CFG, mem_conf, 1072 ret = wl1271_cmd_configure(wl, ACX_MEM_CFG, mem_conf,
1073 sizeof(*mem_conf)); 1073 sizeof(*mem_conf));
@@ -1577,22 +1577,69 @@ out:
1577 return ret; 1577 return ret;
1578} 1578}
1579 1579
1580int wl1271_acx_max_tx_retry(struct wl1271 *wl) 1580int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, bool enable)
1581{ 1581{
1582 struct wl1271_acx_max_tx_retry *acx = NULL; 1582 struct wl1271_acx_ps_rx_streaming *rx_streaming;
1583 u32 conf_queues, enable_queues;
1584 int i, ret = 0;
1585
1586 wl1271_debug(DEBUG_ACX, "acx ps rx streaming");
1587
1588 rx_streaming = kzalloc(sizeof(*rx_streaming), GFP_KERNEL);
1589 if (!rx_streaming) {
1590 ret = -ENOMEM;
1591 goto out;
1592 }
1593
1594 conf_queues = wl->conf.rx_streaming.queues;
1595 if (enable)
1596 enable_queues = conf_queues;
1597 else
1598 enable_queues = 0;
1599
1600 for (i = 0; i < 8; i++) {
1601 /*
1602 * Skip non-changed queues, to avoid redundant acxs.
1603 * this check assumes conf.rx_streaming.queues can't
1604 * be changed while rx_streaming is enabled.
1605 */
1606 if (!(conf_queues & BIT(i)))
1607 continue;
1608
1609 rx_streaming->tid = i;
1610 rx_streaming->enable = enable_queues & BIT(i);
1611 rx_streaming->period = wl->conf.rx_streaming.interval;
1612 rx_streaming->timeout = wl->conf.rx_streaming.interval;
1613
1614 ret = wl1271_cmd_configure(wl, ACX_PS_RX_STREAMING,
1615 rx_streaming,
1616 sizeof(*rx_streaming));
1617 if (ret < 0) {
1618 wl1271_warning("acx ps rx streaming failed: %d", ret);
1619 goto out;
1620 }
1621 }
1622out:
1623 kfree(rx_streaming);
1624 return ret;
1625}
1626
1627int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl)
1628{
1629 struct wl1271_acx_ap_max_tx_retry *acx = NULL;
1583 int ret; 1630 int ret;
1584 1631
1585 wl1271_debug(DEBUG_ACX, "acx max tx retry"); 1632 wl1271_debug(DEBUG_ACX, "acx ap max tx retry");
1586 1633
1587 acx = kzalloc(sizeof(*acx), GFP_KERNEL); 1634 acx = kzalloc(sizeof(*acx), GFP_KERNEL);
1588 if (!acx) 1635 if (!acx)
1589 return -ENOMEM; 1636 return -ENOMEM;
1590 1637
1591 acx->max_tx_retry = cpu_to_le16(wl->conf.tx.ap_max_tx_retries); 1638 acx->max_tx_retry = cpu_to_le16(wl->conf.tx.max_tx_retries);
1592 1639
1593 ret = wl1271_cmd_configure(wl, ACX_MAX_TX_FAILURE, acx, sizeof(*acx)); 1640 ret = wl1271_cmd_configure(wl, ACX_MAX_TX_FAILURE, acx, sizeof(*acx));
1594 if (ret < 0) { 1641 if (ret < 0) {
1595 wl1271_warning("acx max tx retry failed: %d", ret); 1642 wl1271_warning("acx ap max tx retry failed: %d", ret);
1596 goto out; 1643 goto out;
1597 } 1644 }
1598 1645
diff --git a/drivers/net/wireless/wl12xx/acx.h b/drivers/net/wireless/wl12xx/acx.h
index 9a895e3cc613..d2eb86eccc04 100644
--- a/drivers/net/wireless/wl12xx/acx.h
+++ b/drivers/net/wireless/wl12xx/acx.h
@@ -828,6 +828,8 @@ struct wl1271_acx_sta_config_memory {
828 u8 tx_free_req; 828 u8 tx_free_req;
829 u8 rx_free_req; 829 u8 rx_free_req;
830 u8 tx_min; 830 u8 tx_min;
831 u8 fwlog_blocks;
832 u8 padding[3];
831} __packed; 833} __packed;
832 834
833struct wl1271_acx_mem_map { 835struct wl1271_acx_mem_map {
@@ -1153,7 +1155,20 @@ struct wl1271_acx_fw_tsf_information {
1153 u8 padding[3]; 1155 u8 padding[3];
1154} __packed; 1156} __packed;
1155 1157
1156struct wl1271_acx_max_tx_retry { 1158struct wl1271_acx_ps_rx_streaming {
1159 struct acx_header header;
1160
1161 u8 tid;
1162 u8 enable;
1163
1164 /* interval between triggers (10-100 msec) */
1165 u8 period;
1166
1167 /* timeout before first trigger (0-200 msec) */
1168 u8 timeout;
1169} __packed;
1170
1171struct wl1271_acx_ap_max_tx_retry {
1157 struct acx_header header; 1172 struct acx_header header;
1158 1173
1159 /* 1174 /*
@@ -1384,7 +1399,8 @@ int wl1271_acx_set_ba_session(struct wl1271 *wl,
1384int wl1271_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index, u16 ssn, 1399int wl1271_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index, u16 ssn,
1385 bool enable); 1400 bool enable);
1386int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime); 1401int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime);
1387int wl1271_acx_max_tx_retry(struct wl1271 *wl); 1402int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, bool enable);
1403int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl);
1388int wl1271_acx_config_ps(struct wl1271 *wl); 1404int wl1271_acx_config_ps(struct wl1271 *wl);
1389int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr); 1405int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr);
1390int wl1271_acx_set_ap_beacon_filter(struct wl1271 *wl, bool enable); 1406int wl1271_acx_set_ap_beacon_filter(struct wl1271 *wl, bool enable);
diff --git a/drivers/net/wireless/wl12xx/boot.c b/drivers/net/wireless/wl12xx/boot.c
index b07f8b7e5f11..5ebc64d89407 100644
--- a/drivers/net/wireless/wl12xx/boot.c
+++ b/drivers/net/wireless/wl12xx/boot.c
@@ -102,6 +102,33 @@ static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
102 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl); 102 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
103} 103}
104 104
105static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271 *wl)
106{
107 unsigned int quirks = 0;
108 unsigned int *fw_ver = wl->chip.fw_ver;
109
110 /* Only for wl127x */
111 if ((fw_ver[FW_VER_CHIP] == FW_VER_CHIP_WL127X) &&
112 /* Check STA version */
113 (((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
114 (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_1_SPARE_STA_MIN)) ||
115 /* Check AP version */
116 ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP) &&
117 (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_1_SPARE_AP_MIN))))
118 quirks |= WL12XX_QUIRK_USE_2_SPARE_BLOCKS;
119
120 /* Only new station firmwares support routing fw logs to the host */
121 if ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
122 (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_FWLOG_STA_MIN))
123 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED;
124
125 /* This feature is not yet supported for AP mode */
126 if (fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP)
127 quirks |= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED;
128
129 return quirks;
130}
131
105static void wl1271_parse_fw_ver(struct wl1271 *wl) 132static void wl1271_parse_fw_ver(struct wl1271 *wl)
106{ 133{
107 int ret; 134 int ret;
@@ -116,6 +143,9 @@ static void wl1271_parse_fw_ver(struct wl1271 *wl)
116 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver)); 143 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
117 return; 144 return;
118 } 145 }
146
147 /* Check if any quirks are needed with older fw versions */
148 wl->quirks |= wl12xx_get_fw_ver_quirks(wl);
119} 149}
120 150
121static void wl1271_boot_fw_version(struct wl1271 *wl) 151static void wl1271_boot_fw_version(struct wl1271 *wl)
@@ -483,9 +513,12 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
483 PERIODIC_SCAN_COMPLETE_EVENT_ID; 513 PERIODIC_SCAN_COMPLETE_EVENT_ID;
484 514
485 if (wl->bss_type == BSS_TYPE_AP_BSS) 515 if (wl->bss_type == BSS_TYPE_AP_BSS)
486 wl->event_mask |= STA_REMOVE_COMPLETE_EVENT_ID; 516 wl->event_mask |= STA_REMOVE_COMPLETE_EVENT_ID |
517 INACTIVE_STA_EVENT_ID |
518 MAX_TX_RETRY_EVENT_ID;
487 else 519 else
488 wl->event_mask |= DUMMY_PACKET_EVENT_ID; 520 wl->event_mask |= DUMMY_PACKET_EVENT_ID |
521 BA_SESSION_RX_CONSTRAINT_EVENT_ID;
489 522
490 ret = wl1271_event_unmask(wl); 523 ret = wl1271_event_unmask(wl);
491 if (ret < 0) { 524 if (ret < 0) {
@@ -748,6 +781,9 @@ int wl1271_load_firmware(struct wl1271 *wl)
748 clk |= (wl->ref_clock << 1) << 4; 781 clk |= (wl->ref_clock << 1) << 4;
749 } 782 }
750 783
784 if (wl->quirks & WL12XX_QUIRK_LPD_MODE)
785 clk |= SCRATCH_ENABLE_LPD;
786
751 wl1271_write32(wl, DRPW_SCRATCH_START, clk); 787 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
752 788
753 wl1271_set_partition(wl, &part_table[PART_WORK]); 789 wl1271_set_partition(wl, &part_table[PART_WORK]);
diff --git a/drivers/net/wireless/wl12xx/cmd.c b/drivers/net/wireless/wl12xx/cmd.c
index 42935ac72663..97dd237a9580 100644
--- a/drivers/net/wireless/wl12xx/cmd.c
+++ b/drivers/net/wireless/wl12xx/cmd.c
@@ -23,7 +23,6 @@
23 23
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/crc7.h>
27#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
28#include <linux/etherdevice.h> 27#include <linux/etherdevice.h>
29#include <linux/ieee80211.h> 28#include <linux/ieee80211.h>
@@ -106,7 +105,7 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
106 105
107fail: 106fail:
108 WARN_ON(1); 107 WARN_ON(1);
109 ieee80211_queue_work(wl->hw, &wl->recovery_work); 108 wl12xx_queue_recovery_work(wl);
110 return ret; 109 return ret;
111} 110}
112 111
@@ -135,6 +134,11 @@ int wl1271_cmd_general_parms(struct wl1271 *wl)
135 /* Override the REF CLK from the NVS with the one from platform data */ 134 /* Override the REF CLK from the NVS with the one from platform data */
136 gen_parms->general_params.ref_clock = wl->ref_clock; 135 gen_parms->general_params.ref_clock = wl->ref_clock;
137 136
137 /* LPD mode enable (bits 6-7) in WL1271 AP mode only */
138 if (wl->quirks & WL12XX_QUIRK_LPD_MODE)
139 gen_parms->general_params.general_settings |=
140 GENERAL_SETTINGS_DRPW_LPD;
141
138 ret = wl1271_cmd_test(wl, gen_parms, sizeof(*gen_parms), answer); 142 ret = wl1271_cmd_test(wl, gen_parms, sizeof(*gen_parms), answer);
139 if (ret < 0) { 143 if (ret < 0) {
140 wl1271_warning("CMD_INI_FILE_GENERAL_PARAM failed"); 144 wl1271_warning("CMD_INI_FILE_GENERAL_PARAM failed");
@@ -352,7 +356,7 @@ static int wl1271_cmd_wait_for_event(struct wl1271 *wl, u32 mask)
352 356
353 ret = wl1271_cmd_wait_for_event_or_timeout(wl, mask); 357 ret = wl1271_cmd_wait_for_event_or_timeout(wl, mask);
354 if (ret != 0) { 358 if (ret != 0) {
355 ieee80211_queue_work(wl->hw, &wl->recovery_work); 359 wl12xx_queue_recovery_work(wl);
356 return ret; 360 return ret;
357 } 361 }
358 362
@@ -396,10 +400,6 @@ int wl1271_cmd_join(struct wl1271 *wl, u8 bss_type)
396 400
397 join->ctrl |= wl->session_counter << WL1271_JOIN_CMD_TX_SESSION_OFFSET; 401 join->ctrl |= wl->session_counter << WL1271_JOIN_CMD_TX_SESSION_OFFSET;
398 402
399 /* reset TX security counters */
400 wl->tx_security_last_seq = 0;
401 wl->tx_security_seq = 0;
402
403 wl1271_debug(DEBUG_CMD, "cmd join: basic_rate_set=0x%x, rate_set=0x%x", 403 wl1271_debug(DEBUG_CMD, "cmd join: basic_rate_set=0x%x, rate_set=0x%x",
404 join->basic_rate_set, join->supported_rate_set); 404 join->basic_rate_set, join->supported_rate_set);
405 405
@@ -1080,7 +1080,7 @@ int wl1271_cmd_start_bss(struct wl1271 *wl)
1080 1080
1081 memcpy(cmd->bssid, bss_conf->bssid, ETH_ALEN); 1081 memcpy(cmd->bssid, bss_conf->bssid, ETH_ALEN);
1082 1082
1083 cmd->aging_period = cpu_to_le16(WL1271_AP_DEF_INACTIV_SEC); 1083 cmd->aging_period = cpu_to_le16(wl->conf.tx.ap_aging_period);
1084 cmd->bss_index = WL1271_AP_BSS_INDEX; 1084 cmd->bss_index = WL1271_AP_BSS_INDEX;
1085 cmd->global_hlid = WL1271_AP_GLOBAL_HLID; 1085 cmd->global_hlid = WL1271_AP_GLOBAL_HLID;
1086 cmd->broadcast_hlid = WL1271_AP_BROADCAST_HLID; 1086 cmd->broadcast_hlid = WL1271_AP_BROADCAST_HLID;
@@ -1167,14 +1167,7 @@ int wl1271_cmd_add_sta(struct wl1271 *wl, struct ieee80211_sta *sta, u8 hlid)
1167 cmd->bss_index = WL1271_AP_BSS_INDEX; 1167 cmd->bss_index = WL1271_AP_BSS_INDEX;
1168 cmd->aid = sta->aid; 1168 cmd->aid = sta->aid;
1169 cmd->hlid = hlid; 1169 cmd->hlid = hlid;
1170 1170 cmd->wmm = sta->wme ? 1 : 0;
1171 /*
1172 * FIXME: Does STA support QOS? We need to propagate this info from
1173 * hostapd. Currently not that important since this is only used for
1174 * sending the correct flavor of null-data packet in response to a
1175 * trigger.
1176 */
1177 cmd->wmm = 0;
1178 1171
1179 cmd->supported_rates = cpu_to_le32(wl1271_tx_enabled_rates_get(wl, 1172 cmd->supported_rates = cpu_to_le32(wl1271_tx_enabled_rates_get(wl,
1180 sta->supp_rates[wl->band])); 1173 sta->supp_rates[wl->band]));
@@ -1230,3 +1223,87 @@ out_free:
1230out: 1223out:
1231 return ret; 1224 return ret;
1232} 1225}
1226
1227int wl12xx_cmd_config_fwlog(struct wl1271 *wl)
1228{
1229 struct wl12xx_cmd_config_fwlog *cmd;
1230 int ret = 0;
1231
1232 wl1271_debug(DEBUG_CMD, "cmd config firmware logger");
1233
1234 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1235 if (!cmd) {
1236 ret = -ENOMEM;
1237 goto out;
1238 }
1239
1240 cmd->logger_mode = wl->conf.fwlog.mode;
1241 cmd->log_severity = wl->conf.fwlog.severity;
1242 cmd->timestamp = wl->conf.fwlog.timestamp;
1243 cmd->output = wl->conf.fwlog.output;
1244 cmd->threshold = wl->conf.fwlog.threshold;
1245
1246 ret = wl1271_cmd_send(wl, CMD_CONFIG_FWLOGGER, cmd, sizeof(*cmd), 0);
1247 if (ret < 0) {
1248 wl1271_error("failed to send config firmware logger command");
1249 goto out_free;
1250 }
1251
1252out_free:
1253 kfree(cmd);
1254
1255out:
1256 return ret;
1257}
1258
1259int wl12xx_cmd_start_fwlog(struct wl1271 *wl)
1260{
1261 struct wl12xx_cmd_start_fwlog *cmd;
1262 int ret = 0;
1263
1264 wl1271_debug(DEBUG_CMD, "cmd start firmware logger");
1265
1266 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1267 if (!cmd) {
1268 ret = -ENOMEM;
1269 goto out;
1270 }
1271
1272 ret = wl1271_cmd_send(wl, CMD_START_FWLOGGER, cmd, sizeof(*cmd), 0);
1273 if (ret < 0) {
1274 wl1271_error("failed to send start firmware logger command");
1275 goto out_free;
1276 }
1277
1278out_free:
1279 kfree(cmd);
1280
1281out:
1282 return ret;
1283}
1284
1285int wl12xx_cmd_stop_fwlog(struct wl1271 *wl)
1286{
1287 struct wl12xx_cmd_stop_fwlog *cmd;
1288 int ret = 0;
1289
1290 wl1271_debug(DEBUG_CMD, "cmd stop firmware logger");
1291
1292 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1293 if (!cmd) {
1294 ret = -ENOMEM;
1295 goto out;
1296 }
1297
1298 ret = wl1271_cmd_send(wl, CMD_STOP_FWLOGGER, cmd, sizeof(*cmd), 0);
1299 if (ret < 0) {
1300 wl1271_error("failed to send stop firmware logger command");
1301 goto out_free;
1302 }
1303
1304out_free:
1305 kfree(cmd);
1306
1307out:
1308 return ret;
1309}
diff --git a/drivers/net/wireless/wl12xx/cmd.h b/drivers/net/wireless/wl12xx/cmd.h
index 5cac95d9480c..1f7037292c15 100644
--- a/drivers/net/wireless/wl12xx/cmd.h
+++ b/drivers/net/wireless/wl12xx/cmd.h
@@ -70,6 +70,9 @@ int wl1271_cmd_start_bss(struct wl1271 *wl);
70int wl1271_cmd_stop_bss(struct wl1271 *wl); 70int wl1271_cmd_stop_bss(struct wl1271 *wl);
71int wl1271_cmd_add_sta(struct wl1271 *wl, struct ieee80211_sta *sta, u8 hlid); 71int wl1271_cmd_add_sta(struct wl1271 *wl, struct ieee80211_sta *sta, u8 hlid);
72int wl1271_cmd_remove_sta(struct wl1271 *wl, u8 hlid); 72int wl1271_cmd_remove_sta(struct wl1271 *wl, u8 hlid);
73int wl12xx_cmd_config_fwlog(struct wl1271 *wl);
74int wl12xx_cmd_start_fwlog(struct wl1271 *wl);
75int wl12xx_cmd_stop_fwlog(struct wl1271 *wl);
73 76
74enum wl1271_commands { 77enum wl1271_commands {
75 CMD_INTERROGATE = 1, /*use this to read information elements*/ 78 CMD_INTERROGATE = 1, /*use this to read information elements*/
@@ -107,6 +110,9 @@ enum wl1271_commands {
107 CMD_START_PERIODIC_SCAN = 50, 110 CMD_START_PERIODIC_SCAN = 50,
108 CMD_STOP_PERIODIC_SCAN = 51, 111 CMD_STOP_PERIODIC_SCAN = 51,
109 CMD_SET_STA_STATE = 52, 112 CMD_SET_STA_STATE = 52,
113 CMD_CONFIG_FWLOGGER = 53,
114 CMD_START_FWLOGGER = 54,
115 CMD_STOP_FWLOGGER = 55,
110 116
111 /* AP mode commands */ 117 /* AP mode commands */
112 CMD_BSS_START = 60, 118 CMD_BSS_START = 60,
@@ -575,4 +581,60 @@ struct wl1271_cmd_remove_sta {
575 u8 padding1; 581 u8 padding1;
576} __packed; 582} __packed;
577 583
584/*
585 * Continuous mode - packets are transferred to the host periodically
586 * via the data path.
587 * On demand - Log messages are stored in a cyclic buffer in the
588 * firmware, and only transferred to the host when explicitly requested
589 */
590enum wl12xx_fwlogger_log_mode {
591 WL12XX_FWLOG_CONTINUOUS,
592 WL12XX_FWLOG_ON_DEMAND
593};
594
595/* Include/exclude timestamps from the log messages */
596enum wl12xx_fwlogger_timestamp {
597 WL12XX_FWLOG_TIMESTAMP_DISABLED,
598 WL12XX_FWLOG_TIMESTAMP_ENABLED
599};
600
601/*
602 * Logs can be routed to the debug pinouts (where available), to the host bus
603 * (SDIO/SPI), or dropped
604 */
605enum wl12xx_fwlogger_output {
606 WL12XX_FWLOG_OUTPUT_NONE,
607 WL12XX_FWLOG_OUTPUT_DBG_PINS,
608 WL12XX_FWLOG_OUTPUT_HOST,
609};
610
611struct wl12xx_cmd_config_fwlog {
612 struct wl1271_cmd_header header;
613
614 /* See enum wl12xx_fwlogger_log_mode */
615 u8 logger_mode;
616
617 /* Minimum log level threshold */
618 u8 log_severity;
619
620 /* Include/exclude timestamps from the log messages */
621 u8 timestamp;
622
623 /* See enum wl1271_fwlogger_output */
624 u8 output;
625
626 /* Regulates the frequency of log messages */
627 u8 threshold;
628
629 u8 padding[3];
630} __packed;
631
632struct wl12xx_cmd_start_fwlog {
633 struct wl1271_cmd_header header;
634} __packed;
635
636struct wl12xx_cmd_stop_fwlog {
637 struct wl1271_cmd_header header;
638} __packed;
639
578#endif /* __WL1271_CMD_H__ */ 640#endif /* __WL1271_CMD_H__ */
diff --git a/drivers/net/wireless/wl12xx/conf.h b/drivers/net/wireless/wl12xx/conf.h
index c83fefb6662f..6080e01d92c6 100644
--- a/drivers/net/wireless/wl12xx/conf.h
+++ b/drivers/net/wireless/wl12xx/conf.h
@@ -713,8 +713,16 @@ struct conf_tx_settings {
713 /* 713 /*
714 * AP-mode - allow this number of TX retries to a station before an 714 * AP-mode - allow this number of TX retries to a station before an
715 * event is triggered from FW. 715 * event is triggered from FW.
716 * In AP-mode the hlids of unreachable stations are given in the
717 * "sta_tx_retry_exceeded" member in the event mailbox.
716 */ 718 */
717 u16 ap_max_tx_retries; 719 u8 max_tx_retries;
720
721 /*
722 * AP-mode - after this number of seconds a connected station is
723 * considered inactive.
724 */
725 u16 ap_aging_period;
718 726
719 /* 727 /*
720 * Configuration for TID parameters. 728 * Configuration for TID parameters.
@@ -1248,6 +1256,59 @@ struct conf_fm_coex {
1248 u8 swallow_clk_diff; 1256 u8 swallow_clk_diff;
1249}; 1257};
1250 1258
1259struct conf_rx_streaming_settings {
1260 /*
1261 * RX Streaming duration (in msec) from last tx/rx
1262 *
1263 * Range: u32
1264 */
1265 u32 duration;
1266
1267 /*
1268 * Bitmap of tids to be polled during RX streaming.
1269 * (Note: it doesn't look like it really matters)
1270 *
1271 * Range: 0x1-0xff
1272 */
1273 u8 queues;
1274
1275 /*
1276 * RX Streaming interval.
1277 * (Note:this value is also used as the rx streaming timeout)
1278 * Range: 0 (disabled), 10 - 100
1279 */
1280 u8 interval;
1281
1282 /*
1283 * enable rx streaming also when there is no coex activity
1284 */
1285 u8 always;
1286};
1287
1288struct conf_fwlog {
1289 /* Continuous or on-demand */
1290 u8 mode;
1291
1292 /*
1293 * Number of memory blocks dedicated for the FW logger
1294 *
1295 * Range: 1-3, or 0 to disable the FW logger
1296 */
1297 u8 mem_blocks;
1298
1299 /* Minimum log level threshold */
1300 u8 severity;
1301
1302 /* Include/exclude timestamps from the log messages */
1303 u8 timestamp;
1304
1305 /* See enum wl1271_fwlogger_output */
1306 u8 output;
1307
1308 /* Regulates the frequency of log messages */
1309 u8 threshold;
1310};
1311
1251struct conf_drv_settings { 1312struct conf_drv_settings {
1252 struct conf_sg_settings sg; 1313 struct conf_sg_settings sg;
1253 struct conf_rx_settings rx; 1314 struct conf_rx_settings rx;
@@ -1263,6 +1324,8 @@ struct conf_drv_settings {
1263 struct conf_memory_settings mem_wl127x; 1324 struct conf_memory_settings mem_wl127x;
1264 struct conf_memory_settings mem_wl128x; 1325 struct conf_memory_settings mem_wl128x;
1265 struct conf_fm_coex fm_coex; 1326 struct conf_fm_coex fm_coex;
1327 struct conf_rx_streaming_settings rx_streaming;
1328 struct conf_fwlog fwlog;
1266 u8 hci_io_ds; 1329 u8 hci_io_ds;
1267}; 1330};
1268 1331
diff --git a/drivers/net/wireless/wl12xx/debugfs.c b/drivers/net/wireless/wl12xx/debugfs.c
index f1f8df9b6cd7..37934b5601cd 100644
--- a/drivers/net/wireless/wl12xx/debugfs.c
+++ b/drivers/net/wireless/wl12xx/debugfs.c
@@ -30,6 +30,7 @@
30#include "acx.h" 30#include "acx.h"
31#include "ps.h" 31#include "ps.h"
32#include "io.h" 32#include "io.h"
33#include "tx.h"
33 34
34/* ms */ 35/* ms */
35#define WL1271_DEBUGFS_STATS_LIFETIME 1000 36#define WL1271_DEBUGFS_STATS_LIFETIME 1000
@@ -71,6 +72,14 @@ static const struct file_operations name## _ops = { \
71 if (!entry || IS_ERR(entry)) \ 72 if (!entry || IS_ERR(entry)) \
72 goto err; \ 73 goto err; \
73 74
75#define DEBUGFS_ADD_PREFIX(prefix, name, parent) \
76 do { \
77 entry = debugfs_create_file(#name, 0400, parent, \
78 wl, &prefix## _## name## _ops); \
79 if (!entry || IS_ERR(entry)) \
80 goto err; \
81 } while (0);
82
74#define DEBUGFS_FWSTATS_FILE(sub, name, fmt) \ 83#define DEBUGFS_FWSTATS_FILE(sub, name, fmt) \
75static ssize_t sub## _ ##name## _read(struct file *file, \ 84static ssize_t sub## _ ##name## _read(struct file *file, \
76 char __user *userbuf, \ 85 char __user *userbuf, \
@@ -225,7 +234,7 @@ static ssize_t tx_queue_len_read(struct file *file, char __user *userbuf,
225 char buf[20]; 234 char buf[20];
226 int res; 235 int res;
227 236
228 queue_len = wl->tx_queue_count; 237 queue_len = wl1271_tx_total_queue_count(wl);
229 238
230 res = scnprintf(buf, sizeof(buf), "%u\n", queue_len); 239 res = scnprintf(buf, sizeof(buf), "%u\n", queue_len);
231 return simple_read_from_buffer(userbuf, count, ppos, buf, res); 240 return simple_read_from_buffer(userbuf, count, ppos, buf, res);
@@ -298,7 +307,7 @@ static ssize_t start_recovery_write(struct file *file,
298 struct wl1271 *wl = file->private_data; 307 struct wl1271 *wl = file->private_data;
299 308
300 mutex_lock(&wl->mutex); 309 mutex_lock(&wl->mutex);
301 ieee80211_queue_work(wl->hw, &wl->recovery_work); 310 wl12xx_queue_recovery_work(wl);
302 mutex_unlock(&wl->mutex); 311 mutex_unlock(&wl->mutex);
303 312
304 return count; 313 return count;
@@ -330,10 +339,16 @@ static ssize_t driver_state_read(struct file *file, char __user *user_buf,
330#define DRIVER_STATE_PRINT_HEX(x) DRIVER_STATE_PRINT(x, "0x%x") 339#define DRIVER_STATE_PRINT_HEX(x) DRIVER_STATE_PRINT(x, "0x%x")
331 340
332 DRIVER_STATE_PRINT_INT(tx_blocks_available); 341 DRIVER_STATE_PRINT_INT(tx_blocks_available);
333 DRIVER_STATE_PRINT_INT(tx_allocated_blocks); 342 DRIVER_STATE_PRINT_INT(tx_allocated_blocks[0]);
343 DRIVER_STATE_PRINT_INT(tx_allocated_blocks[1]);
344 DRIVER_STATE_PRINT_INT(tx_allocated_blocks[2]);
345 DRIVER_STATE_PRINT_INT(tx_allocated_blocks[3]);
334 DRIVER_STATE_PRINT_INT(tx_frames_cnt); 346 DRIVER_STATE_PRINT_INT(tx_frames_cnt);
335 DRIVER_STATE_PRINT_LHEX(tx_frames_map[0]); 347 DRIVER_STATE_PRINT_LHEX(tx_frames_map[0]);
336 DRIVER_STATE_PRINT_INT(tx_queue_count); 348 DRIVER_STATE_PRINT_INT(tx_queue_count[0]);
349 DRIVER_STATE_PRINT_INT(tx_queue_count[1]);
350 DRIVER_STATE_PRINT_INT(tx_queue_count[2]);
351 DRIVER_STATE_PRINT_INT(tx_queue_count[3]);
337 DRIVER_STATE_PRINT_INT(tx_packets_count); 352 DRIVER_STATE_PRINT_INT(tx_packets_count);
338 DRIVER_STATE_PRINT_INT(tx_results_count); 353 DRIVER_STATE_PRINT_INT(tx_results_count);
339 DRIVER_STATE_PRINT_LHEX(flags); 354 DRIVER_STATE_PRINT_LHEX(flags);
@@ -341,7 +356,7 @@ static ssize_t driver_state_read(struct file *file, char __user *user_buf,
341 DRIVER_STATE_PRINT_INT(tx_blocks_freed[1]); 356 DRIVER_STATE_PRINT_INT(tx_blocks_freed[1]);
342 DRIVER_STATE_PRINT_INT(tx_blocks_freed[2]); 357 DRIVER_STATE_PRINT_INT(tx_blocks_freed[2]);
343 DRIVER_STATE_PRINT_INT(tx_blocks_freed[3]); 358 DRIVER_STATE_PRINT_INT(tx_blocks_freed[3]);
344 DRIVER_STATE_PRINT_INT(tx_security_last_seq); 359 DRIVER_STATE_PRINT_INT(tx_security_last_seq_lsb);
345 DRIVER_STATE_PRINT_INT(rx_counter); 360 DRIVER_STATE_PRINT_INT(rx_counter);
346 DRIVER_STATE_PRINT_INT(session_counter); 361 DRIVER_STATE_PRINT_INT(session_counter);
347 DRIVER_STATE_PRINT_INT(state); 362 DRIVER_STATE_PRINT_INT(state);
@@ -527,11 +542,129 @@ static const struct file_operations beacon_interval_ops = {
527 .llseek = default_llseek, 542 .llseek = default_llseek,
528}; 543};
529 544
545static ssize_t rx_streaming_interval_write(struct file *file,
546 const char __user *user_buf,
547 size_t count, loff_t *ppos)
548{
549 struct wl1271 *wl = file->private_data;
550 char buf[10];
551 size_t len;
552 unsigned long value;
553 int ret;
554
555 len = min(count, sizeof(buf) - 1);
556 if (copy_from_user(buf, user_buf, len))
557 return -EFAULT;
558 buf[len] = '\0';
559
560 ret = kstrtoul(buf, 0, &value);
561 if (ret < 0) {
562 wl1271_warning("illegal value in rx_streaming_interval!");
563 return -EINVAL;
564 }
565
566 /* valid values: 0, 10-100 */
567 if (value && (value < 10 || value > 100)) {
568 wl1271_warning("value is not in range!");
569 return -ERANGE;
570 }
571
572 mutex_lock(&wl->mutex);
573
574 wl->conf.rx_streaming.interval = value;
575
576 ret = wl1271_ps_elp_wakeup(wl);
577 if (ret < 0)
578 goto out;
579
580 wl1271_recalc_rx_streaming(wl);
581
582 wl1271_ps_elp_sleep(wl);
583out:
584 mutex_unlock(&wl->mutex);
585 return count;
586}
587
588static ssize_t rx_streaming_interval_read(struct file *file,
589 char __user *userbuf,
590 size_t count, loff_t *ppos)
591{
592 struct wl1271 *wl = file->private_data;
593 return wl1271_format_buffer(userbuf, count, ppos,
594 "%d\n", wl->conf.rx_streaming.interval);
595}
596
597static const struct file_operations rx_streaming_interval_ops = {
598 .read = rx_streaming_interval_read,
599 .write = rx_streaming_interval_write,
600 .open = wl1271_open_file_generic,
601 .llseek = default_llseek,
602};
603
604static ssize_t rx_streaming_always_write(struct file *file,
605 const char __user *user_buf,
606 size_t count, loff_t *ppos)
607{
608 struct wl1271 *wl = file->private_data;
609 char buf[10];
610 size_t len;
611 unsigned long value;
612 int ret;
613
614 len = min(count, sizeof(buf) - 1);
615 if (copy_from_user(buf, user_buf, len))
616 return -EFAULT;
617 buf[len] = '\0';
618
619 ret = kstrtoul(buf, 0, &value);
620 if (ret < 0) {
621 wl1271_warning("illegal value in rx_streaming_write!");
622 return -EINVAL;
623 }
624
625 /* valid values: 0, 10-100 */
626 if (!(value == 0 || value == 1)) {
627 wl1271_warning("value is not in valid!");
628 return -EINVAL;
629 }
630
631 mutex_lock(&wl->mutex);
632
633 wl->conf.rx_streaming.always = value;
634
635 ret = wl1271_ps_elp_wakeup(wl);
636 if (ret < 0)
637 goto out;
638
639 wl1271_recalc_rx_streaming(wl);
640
641 wl1271_ps_elp_sleep(wl);
642out:
643 mutex_unlock(&wl->mutex);
644 return count;
645}
646
647static ssize_t rx_streaming_always_read(struct file *file,
648 char __user *userbuf,
649 size_t count, loff_t *ppos)
650{
651 struct wl1271 *wl = file->private_data;
652 return wl1271_format_buffer(userbuf, count, ppos,
653 "%d\n", wl->conf.rx_streaming.always);
654}
655
656static const struct file_operations rx_streaming_always_ops = {
657 .read = rx_streaming_always_read,
658 .write = rx_streaming_always_write,
659 .open = wl1271_open_file_generic,
660 .llseek = default_llseek,
661};
662
530static int wl1271_debugfs_add_files(struct wl1271 *wl, 663static int wl1271_debugfs_add_files(struct wl1271 *wl,
531 struct dentry *rootdir) 664 struct dentry *rootdir)
532{ 665{
533 int ret = 0; 666 int ret = 0;
534 struct dentry *entry, *stats; 667 struct dentry *entry, *stats, *streaming;
535 668
536 stats = debugfs_create_dir("fw-statistics", rootdir); 669 stats = debugfs_create_dir("fw-statistics", rootdir);
537 if (!stats || IS_ERR(stats)) { 670 if (!stats || IS_ERR(stats)) {
@@ -640,6 +773,14 @@ static int wl1271_debugfs_add_files(struct wl1271 *wl,
640 DEBUGFS_ADD(dtim_interval, rootdir); 773 DEBUGFS_ADD(dtim_interval, rootdir);
641 DEBUGFS_ADD(beacon_interval, rootdir); 774 DEBUGFS_ADD(beacon_interval, rootdir);
642 775
776 streaming = debugfs_create_dir("rx_streaming", rootdir);
777 if (!streaming || IS_ERR(streaming))
778 goto err;
779
780 DEBUGFS_ADD_PREFIX(rx_streaming, interval, streaming);
781 DEBUGFS_ADD_PREFIX(rx_streaming, always, streaming);
782
783
643 return 0; 784 return 0;
644 785
645err: 786err:
diff --git a/drivers/net/wireless/wl12xx/event.c b/drivers/net/wireless/wl12xx/event.c
index c3c554cd6580..304aaa2ee011 100644
--- a/drivers/net/wireless/wl12xx/event.c
+++ b/drivers/net/wireless/wl12xx/event.c
@@ -133,10 +133,13 @@ static int wl1271_event_ps_report(struct wl1271 *wl,
133 if (ret < 0) 133 if (ret < 0)
134 break; 134 break;
135 135
136 /* enable beacon early termination */ 136 /*
137 ret = wl1271_acx_bet_enable(wl, true); 137 * BET has only a minor effect in 5GHz and masks
138 if (ret < 0) 138 * channel switch IEs, so we only enable BET on 2.4GHz
139 break; 139 */
140 if (wl->band == IEEE80211_BAND_2GHZ)
141 /* enable beacon early termination */
142 ret = wl1271_acx_bet_enable(wl, true);
140 143
141 if (wl->ps_compl) { 144 if (wl->ps_compl) {
142 complete(wl->ps_compl); 145 complete(wl->ps_compl);
@@ -168,6 +171,36 @@ static void wl1271_event_rssi_trigger(struct wl1271 *wl,
168 wl->last_rssi_event = event; 171 wl->last_rssi_event = event;
169} 172}
170 173
174static void wl1271_stop_ba_event(struct wl1271 *wl, u8 ba_allowed)
175{
176 /* Convert the value to bool */
177 wl->ba_allowed = !!ba_allowed;
178
179 /*
180 * Return in case:
181 * there are not BA open or the event indication is to allowed BA
182 */
183 if ((!wl->ba_rx_bitmap) || (wl->ba_allowed))
184 return;
185
186 ieee80211_stop_rx_ba_session(wl->vif, wl->ba_rx_bitmap, wl->bssid);
187}
188
189static void wl12xx_event_soft_gemini_sense(struct wl1271 *wl,
190 u8 enable)
191{
192 if (enable) {
193 /* disable dynamic PS when requested by the firmware */
194 ieee80211_disable_dyn_ps(wl->vif);
195 set_bit(WL1271_FLAG_SOFT_GEMINI, &wl->flags);
196 } else {
197 ieee80211_enable_dyn_ps(wl->vif);
198 clear_bit(WL1271_FLAG_SOFT_GEMINI, &wl->flags);
199 wl1271_recalc_rx_streaming(wl);
200 }
201
202}
203
171static void wl1271_event_mbox_dump(struct event_mailbox *mbox) 204static void wl1271_event_mbox_dump(struct event_mailbox *mbox)
172{ 205{
173 wl1271_debug(DEBUG_EVENT, "MBOX DUMP:"); 206 wl1271_debug(DEBUG_EVENT, "MBOX DUMP:");
@@ -181,6 +214,8 @@ static int wl1271_event_process(struct wl1271 *wl, struct event_mailbox *mbox)
181 u32 vector; 214 u32 vector;
182 bool beacon_loss = false; 215 bool beacon_loss = false;
183 bool is_ap = (wl->bss_type == BSS_TYPE_AP_BSS); 216 bool is_ap = (wl->bss_type == BSS_TYPE_AP_BSS);
217 bool disconnect_sta = false;
218 unsigned long sta_bitmap = 0;
184 219
185 wl1271_event_mbox_dump(mbox); 220 wl1271_event_mbox_dump(mbox);
186 221
@@ -211,14 +246,10 @@ static int wl1271_event_process(struct wl1271 *wl, struct event_mailbox *mbox)
211 } 246 }
212 } 247 }
213 248
214 /* disable dynamic PS when requested by the firmware */
215 if (vector & SOFT_GEMINI_SENSE_EVENT_ID && 249 if (vector & SOFT_GEMINI_SENSE_EVENT_ID &&
216 wl->bss_type == BSS_TYPE_STA_BSS) { 250 wl->bss_type == BSS_TYPE_STA_BSS)
217 if (mbox->soft_gemini_sense_info) 251 wl12xx_event_soft_gemini_sense(wl,
218 ieee80211_disable_dyn_ps(wl->vif); 252 mbox->soft_gemini_sense_info);
219 else
220 ieee80211_enable_dyn_ps(wl->vif);
221 }
222 253
223 /* 254 /*
224 * The BSS_LOSE_EVENT_ID is only needed while psm (and hence beacon 255 * The BSS_LOSE_EVENT_ID is only needed while psm (and hence beacon
@@ -252,12 +283,60 @@ static int wl1271_event_process(struct wl1271 *wl, struct event_mailbox *mbox)
252 wl1271_event_rssi_trigger(wl, mbox); 283 wl1271_event_rssi_trigger(wl, mbox);
253 } 284 }
254 285
286 if ((vector & BA_SESSION_RX_CONSTRAINT_EVENT_ID) && !is_ap) {
287 wl1271_debug(DEBUG_EVENT, "BA_SESSION_RX_CONSTRAINT_EVENT_ID. "
288 "ba_allowed = 0x%x", mbox->ba_allowed);
289
290 if (wl->vif)
291 wl1271_stop_ba_event(wl, mbox->ba_allowed);
292 }
293
255 if ((vector & DUMMY_PACKET_EVENT_ID) && !is_ap) { 294 if ((vector & DUMMY_PACKET_EVENT_ID) && !is_ap) {
256 wl1271_debug(DEBUG_EVENT, "DUMMY_PACKET_ID_EVENT_ID"); 295 wl1271_debug(DEBUG_EVENT, "DUMMY_PACKET_ID_EVENT_ID");
257 if (wl->vif) 296 if (wl->vif)
258 wl1271_tx_dummy_packet(wl); 297 wl1271_tx_dummy_packet(wl);
259 } 298 }
260 299
300 /*
301 * "TX retries exceeded" has a different meaning according to mode.
302 * In AP mode the offending station is disconnected.
303 */
304 if ((vector & MAX_TX_RETRY_EVENT_ID) && is_ap) {
305 wl1271_debug(DEBUG_EVENT, "MAX_TX_RETRY_EVENT_ID");
306 sta_bitmap |= le16_to_cpu(mbox->sta_tx_retry_exceeded);
307 disconnect_sta = true;
308 }
309
310 if ((vector & INACTIVE_STA_EVENT_ID) && is_ap) {
311 wl1271_debug(DEBUG_EVENT, "INACTIVE_STA_EVENT_ID");
312 sta_bitmap |= le16_to_cpu(mbox->sta_aging_status);
313 disconnect_sta = true;
314 }
315
316 if (is_ap && disconnect_sta) {
317 u32 num_packets = wl->conf.tx.max_tx_retries;
318 struct ieee80211_sta *sta;
319 const u8 *addr;
320 int h;
321
322 for (h = find_first_bit(&sta_bitmap, AP_MAX_LINKS);
323 h < AP_MAX_LINKS;
324 h = find_next_bit(&sta_bitmap, AP_MAX_LINKS, h+1)) {
325 if (!wl1271_is_active_sta(wl, h))
326 continue;
327
328 addr = wl->links[h].addr;
329
330 rcu_read_lock();
331 sta = ieee80211_find_sta(wl->vif, addr);
332 if (sta) {
333 wl1271_debug(DEBUG_EVENT, "remove sta %d", h);
334 ieee80211_report_low_ack(sta, num_packets);
335 }
336 rcu_read_unlock();
337 }
338 }
339
261 if (wl->vif && beacon_loss) 340 if (wl->vif && beacon_loss)
262 ieee80211_connection_loss(wl->vif); 341 ieee80211_connection_loss(wl->vif);
263 342
diff --git a/drivers/net/wireless/wl12xx/event.h b/drivers/net/wireless/wl12xx/event.h
index b6cf06e565a4..e524ad6fe4e3 100644
--- a/drivers/net/wireless/wl12xx/event.h
+++ b/drivers/net/wireless/wl12xx/event.h
@@ -58,20 +58,23 @@ enum {
58 CHANNEL_SWITCH_COMPLETE_EVENT_ID = BIT(17), 58 CHANNEL_SWITCH_COMPLETE_EVENT_ID = BIT(17),
59 BSS_LOSE_EVENT_ID = BIT(18), 59 BSS_LOSE_EVENT_ID = BIT(18),
60 REGAINED_BSS_EVENT_ID = BIT(19), 60 REGAINED_BSS_EVENT_ID = BIT(19),
61 ROAMING_TRIGGER_MAX_TX_RETRY_EVENT_ID = BIT(20), 61 MAX_TX_RETRY_EVENT_ID = BIT(20),
62 /* STA: dummy paket for dynamic mem blocks */ 62 /* STA: dummy paket for dynamic mem blocks */
63 DUMMY_PACKET_EVENT_ID = BIT(21), 63 DUMMY_PACKET_EVENT_ID = BIT(21),
64 /* AP: STA remove complete */ 64 /* AP: STA remove complete */
65 STA_REMOVE_COMPLETE_EVENT_ID = BIT(21), 65 STA_REMOVE_COMPLETE_EVENT_ID = BIT(21),
66 SOFT_GEMINI_SENSE_EVENT_ID = BIT(22), 66 SOFT_GEMINI_SENSE_EVENT_ID = BIT(22),
67 /* STA: SG prediction */
67 SOFT_GEMINI_PREDICTION_EVENT_ID = BIT(23), 68 SOFT_GEMINI_PREDICTION_EVENT_ID = BIT(23),
69 /* AP: Inactive STA */
70 INACTIVE_STA_EVENT_ID = BIT(23),
68 SOFT_GEMINI_AVALANCHE_EVENT_ID = BIT(24), 71 SOFT_GEMINI_AVALANCHE_EVENT_ID = BIT(24),
69 PLT_RX_CALIBRATION_COMPLETE_EVENT_ID = BIT(25), 72 PLT_RX_CALIBRATION_COMPLETE_EVENT_ID = BIT(25),
70 DBG_EVENT_ID = BIT(26), 73 DBG_EVENT_ID = BIT(26),
71 HEALTH_CHECK_REPLY_EVENT_ID = BIT(27), 74 HEALTH_CHECK_REPLY_EVENT_ID = BIT(27),
72 PERIODIC_SCAN_COMPLETE_EVENT_ID = BIT(28), 75 PERIODIC_SCAN_COMPLETE_EVENT_ID = BIT(28),
73 PERIODIC_SCAN_REPORT_EVENT_ID = BIT(29), 76 PERIODIC_SCAN_REPORT_EVENT_ID = BIT(29),
74 BA_SESSION_TEAR_DOWN_EVENT_ID = BIT(30), 77 BA_SESSION_RX_CONSTRAINT_EVENT_ID = BIT(30),
75 EVENT_MBOX_ALL_EVENT_ID = 0x7fffffff, 78 EVENT_MBOX_ALL_EVENT_ID = 0x7fffffff,
76}; 79};
77 80
@@ -119,10 +122,27 @@ struct event_mailbox {
119 122
120 /* AP FW only */ 123 /* AP FW only */
121 u8 hlid_removed; 124 u8 hlid_removed;
125
126 /* a bitmap of hlids for stations that have been inactive too long */
122 __le16 sta_aging_status; 127 __le16 sta_aging_status;
128
129 /* a bitmap of hlids for stations which didn't respond to TX */
123 __le16 sta_tx_retry_exceeded; 130 __le16 sta_tx_retry_exceeded;
124 131
125 u8 reserved_5[24]; 132 /*
133 * Bitmap, Each bit set represents the Role ID for which this constraint
134 * is set. Range: 0 - FF, FF means ANY role
135 */
136 u8 ba_role_id;
137 /*
138 * Bitmap, Each bit set represents the Link ID for which this constraint
139 * is set. Not applicable if ba_role_id is set to ANY role (FF).
140 * Range: 0 - FFFF, FFFF means ANY link in that role
141 */
142 u8 ba_link_id;
143 u8 ba_allowed;
144
145 u8 reserved_5[21];
126} __packed; 146} __packed;
127 147
128int wl1271_event_unmask(struct wl1271 *wl); 148int wl1271_event_unmask(struct wl1271 *wl);
@@ -130,4 +150,7 @@ void wl1271_event_mbox_config(struct wl1271 *wl);
130int wl1271_event_handle(struct wl1271 *wl, u8 mbox); 150int wl1271_event_handle(struct wl1271 *wl, u8 mbox);
131void wl1271_pspoll_work(struct work_struct *work); 151void wl1271_pspoll_work(struct work_struct *work);
132 152
153/* Functions from main.c */
154bool wl1271_is_active_sta(struct wl1271 *wl, u8 hlid);
155
133#endif 156#endif
diff --git a/drivers/net/wireless/wl12xx/ini.h b/drivers/net/wireless/wl12xx/ini.h
index 1420c842b8f1..4cf9ecc56212 100644
--- a/drivers/net/wireless/wl12xx/ini.h
+++ b/drivers/net/wireless/wl12xx/ini.h
@@ -24,6 +24,9 @@
24#ifndef __INI_H__ 24#ifndef __INI_H__
25#define __INI_H__ 25#define __INI_H__
26 26
27#define GENERAL_SETTINGS_DRPW_LPD 0xc0
28#define SCRATCH_ENABLE_LPD BIT(25)
29
27#define WL1271_INI_MAX_SMART_REFLEX_PARAM 16 30#define WL1271_INI_MAX_SMART_REFLEX_PARAM 16
28 31
29struct wl1271_ini_general_params { 32struct wl1271_ini_general_params {
diff --git a/drivers/net/wireless/wl12xx/init.c b/drivers/net/wireless/wl12xx/init.c
index a8f4f156c055..c3e9a2e4410e 100644
--- a/drivers/net/wireless/wl12xx/init.c
+++ b/drivers/net/wireless/wl12xx/init.c
@@ -321,6 +321,20 @@ static int wl1271_init_beacon_broadcast(struct wl1271 *wl)
321 return 0; 321 return 0;
322} 322}
323 323
324static int wl12xx_init_fwlog(struct wl1271 *wl)
325{
326 int ret;
327
328 if (wl->quirks & WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED)
329 return 0;
330
331 ret = wl12xx_cmd_config_fwlog(wl);
332 if (ret < 0)
333 return ret;
334
335 return 0;
336}
337
324static int wl1271_sta_hw_init(struct wl1271 *wl) 338static int wl1271_sta_hw_init(struct wl1271 *wl)
325{ 339{
326 int ret; 340 int ret;
@@ -382,6 +396,11 @@ static int wl1271_sta_hw_init(struct wl1271 *wl)
382 if (ret < 0) 396 if (ret < 0)
383 return ret; 397 return ret;
384 398
399 /* Configure the FW logger */
400 ret = wl12xx_init_fwlog(wl);
401 if (ret < 0)
402 return ret;
403
385 return 0; 404 return 0;
386} 405}
387 406
@@ -428,7 +447,7 @@ static int wl1271_ap_hw_init(struct wl1271 *wl)
428 if (ret < 0) 447 if (ret < 0)
429 return ret; 448 return ret;
430 449
431 ret = wl1271_acx_max_tx_retry(wl); 450 ret = wl1271_acx_ap_max_tx_retry(wl);
432 if (ret < 0) 451 if (ret < 0)
433 return ret; 452 return ret;
434 453
@@ -436,6 +455,11 @@ static int wl1271_ap_hw_init(struct wl1271 *wl)
436 if (ret < 0) 455 if (ret < 0)
437 return ret; 456 return ret;
438 457
458 /* initialize Tx power */
459 ret = wl1271_acx_tx_power(wl, wl->power_level);
460 if (ret < 0)
461 return ret;
462
439 return 0; 463 return 0;
440} 464}
441 465
@@ -541,6 +565,7 @@ static int wl1271_set_ba_policies(struct wl1271 *wl)
541 565
542 /* Reset the BA RX indicators */ 566 /* Reset the BA RX indicators */
543 wl->ba_rx_bitmap = 0; 567 wl->ba_rx_bitmap = 0;
568 wl->ba_allowed = true;
544 569
545 /* validate that FW support BA */ 570 /* validate that FW support BA */
546 wl1271_check_ba_support(wl); 571 wl1271_check_ba_support(wl);
diff --git a/drivers/net/wireless/wl12xx/io.c b/drivers/net/wireless/wl12xx/io.c
index da5c1ad942a4..c2da66f45046 100644
--- a/drivers/net/wireless/wl12xx/io.c
+++ b/drivers/net/wireless/wl12xx/io.c
@@ -23,7 +23,6 @@
23 23
24#include <linux/module.h> 24#include <linux/module.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/crc7.h>
27#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
28 27
29#include "wl12xx.h" 28#include "wl12xx.h"
@@ -128,12 +127,14 @@ EXPORT_SYMBOL_GPL(wl1271_set_partition);
128 127
129void wl1271_io_reset(struct wl1271 *wl) 128void wl1271_io_reset(struct wl1271 *wl)
130{ 129{
131 wl->if_ops->reset(wl); 130 if (wl->if_ops->reset)
131 wl->if_ops->reset(wl);
132} 132}
133 133
134void wl1271_io_init(struct wl1271 *wl) 134void wl1271_io_init(struct wl1271 *wl)
135{ 135{
136 wl->if_ops->init(wl); 136 if (wl->if_ops->init)
137 wl->if_ops->init(wl);
137} 138}
138 139
139void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val) 140void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
diff --git a/drivers/net/wireless/wl12xx/io.h b/drivers/net/wireless/wl12xx/io.h
index beed621a8ae0..a2fe4f506ada 100644
--- a/drivers/net/wireless/wl12xx/io.h
+++ b/drivers/net/wireless/wl12xx/io.h
@@ -25,6 +25,7 @@
25#ifndef __IO_H__ 25#ifndef __IO_H__
26#define __IO_H__ 26#define __IO_H__
27 27
28#include <linux/irqreturn.h>
28#include "reg.h" 29#include "reg.h"
29 30
30#define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0 31#define HW_ACCESS_MEMORY_MAX_RANGE 0x1FFC0
@@ -128,6 +129,20 @@ static inline void wl1271_write(struct wl1271 *wl, int addr, void *buf,
128 wl1271_raw_write(wl, physical, buf, len, fixed); 129 wl1271_raw_write(wl, physical, buf, len, fixed);
129} 130}
130 131
132static inline void wl1271_read_hwaddr(struct wl1271 *wl, int hwaddr,
133 void *buf, size_t len, bool fixed)
134{
135 int physical;
136 int addr;
137
138 /* Addresses are stored internally as addresses to 32 bytes blocks */
139 addr = hwaddr << 5;
140
141 physical = wl1271_translate_addr(wl, addr);
142
143 wl1271_raw_read(wl, physical, buf, len, fixed);
144}
145
131static inline u32 wl1271_read32(struct wl1271 *wl, int addr) 146static inline u32 wl1271_read32(struct wl1271 *wl, int addr)
132{ 147{
133 return wl1271_raw_read32(wl, wl1271_translate_addr(wl, addr)); 148 return wl1271_raw_read32(wl, wl1271_translate_addr(wl, addr));
diff --git a/drivers/net/wireless/wl12xx/main.c b/drivers/net/wireless/wl12xx/main.c
index e6497dc669df..e58c22d21e39 100644
--- a/drivers/net/wireless/wl12xx/main.c
+++ b/drivers/net/wireless/wl12xx/main.c
@@ -31,6 +31,7 @@
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/slab.h> 32#include <linux/slab.h>
33#include <linux/wl12xx.h> 33#include <linux/wl12xx.h>
34#include <linux/sched.h>
34 35
35#include "wl12xx.h" 36#include "wl12xx.h"
36#include "wl12xx_80211.h" 37#include "wl12xx_80211.h"
@@ -209,7 +210,8 @@ static struct conf_drv_settings default_conf = {
209 .tx_op_limit = 1504, 210 .tx_op_limit = 1504,
210 }, 211 },
211 }, 212 },
212 .ap_max_tx_retries = 100, 213 .max_tx_retries = 100,
214 .ap_aging_period = 300,
213 .tid_conf_count = 4, 215 .tid_conf_count = 4,
214 .tid_conf = { 216 .tid_conf = {
215 [CONF_TX_AC_BE] = { 217 [CONF_TX_AC_BE] = {
@@ -362,9 +364,25 @@ static struct conf_drv_settings default_conf = {
362 .fm_disturbed_band_margin = 0xff, /* default */ 364 .fm_disturbed_band_margin = 0xff, /* default */
363 .swallow_clk_diff = 0xff, /* default */ 365 .swallow_clk_diff = 0xff, /* default */
364 }, 366 },
367 .rx_streaming = {
368 .duration = 150,
369 .queues = 0x1,
370 .interval = 20,
371 .always = 0,
372 },
373 .fwlog = {
374 .mode = WL12XX_FWLOG_ON_DEMAND,
375 .mem_blocks = 2,
376 .severity = 0,
377 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
378 .output = WL12XX_FWLOG_OUTPUT_HOST,
379 .threshold = 0,
380 },
365 .hci_io_ds = HCI_IO_DS_6MA, 381 .hci_io_ds = HCI_IO_DS_6MA,
366}; 382};
367 383
384static char *fwlog_param;
385
368static void __wl1271_op_remove_interface(struct wl1271 *wl, 386static void __wl1271_op_remove_interface(struct wl1271 *wl,
369 bool reset_tx_queues); 387 bool reset_tx_queues);
370static void wl1271_free_ap_keys(struct wl1271 *wl); 388static void wl1271_free_ap_keys(struct wl1271 *wl);
@@ -388,6 +406,22 @@ static struct platform_device wl1271_device = {
388static DEFINE_MUTEX(wl_list_mutex); 406static DEFINE_MUTEX(wl_list_mutex);
389static LIST_HEAD(wl_list); 407static LIST_HEAD(wl_list);
390 408
409static int wl1271_check_operstate(struct wl1271 *wl, unsigned char operstate)
410{
411 int ret;
412 if (operstate != IF_OPER_UP)
413 return 0;
414
415 if (test_and_set_bit(WL1271_FLAG_STA_STATE_SENT, &wl->flags))
416 return 0;
417
418 ret = wl1271_cmd_set_sta_state(wl);
419 if (ret < 0)
420 return ret;
421
422 wl1271_info("Association completed.");
423 return 0;
424}
391static int wl1271_dev_notify(struct notifier_block *me, unsigned long what, 425static int wl1271_dev_notify(struct notifier_block *me, unsigned long what,
392 void *arg) 426 void *arg)
393{ 427{
@@ -437,11 +471,7 @@ static int wl1271_dev_notify(struct notifier_block *me, unsigned long what,
437 if (ret < 0) 471 if (ret < 0)
438 goto out; 472 goto out;
439 473
440 if ((dev->operstate == IF_OPER_UP) && 474 wl1271_check_operstate(wl, dev->operstate);
441 !test_and_set_bit(WL1271_FLAG_STA_STATE_SENT, &wl->flags)) {
442 wl1271_cmd_set_sta_state(wl);
443 wl1271_info("Association completed.");
444 }
445 475
446 wl1271_ps_elp_sleep(wl); 476 wl1271_ps_elp_sleep(wl);
447 477
@@ -473,6 +503,117 @@ static int wl1271_reg_notify(struct wiphy *wiphy,
473 return 0; 503 return 0;
474} 504}
475 505
506static int wl1271_set_rx_streaming(struct wl1271 *wl, bool enable)
507{
508 int ret = 0;
509
510 /* we should hold wl->mutex */
511 ret = wl1271_acx_ps_rx_streaming(wl, enable);
512 if (ret < 0)
513 goto out;
514
515 if (enable)
516 set_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags);
517 else
518 clear_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags);
519out:
520 return ret;
521}
522
523/*
524 * this function is being called when the rx_streaming interval
525 * has beed changed or rx_streaming should be disabled
526 */
527int wl1271_recalc_rx_streaming(struct wl1271 *wl)
528{
529 int ret = 0;
530 int period = wl->conf.rx_streaming.interval;
531
532 /* don't reconfigure if rx_streaming is disabled */
533 if (!test_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags))
534 goto out;
535
536 /* reconfigure/disable according to new streaming_period */
537 if (period &&
538 test_bit(WL1271_FLAG_STA_ASSOCIATED, &wl->flags) &&
539 (wl->conf.rx_streaming.always ||
540 test_bit(WL1271_FLAG_SOFT_GEMINI, &wl->flags)))
541 ret = wl1271_set_rx_streaming(wl, true);
542 else {
543 ret = wl1271_set_rx_streaming(wl, false);
544 /* don't cancel_work_sync since we might deadlock */
545 del_timer_sync(&wl->rx_streaming_timer);
546 }
547out:
548 return ret;
549}
550
551static void wl1271_rx_streaming_enable_work(struct work_struct *work)
552{
553 int ret;
554 struct wl1271 *wl =
555 container_of(work, struct wl1271, rx_streaming_enable_work);
556
557 mutex_lock(&wl->mutex);
558
559 if (test_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags) ||
560 !test_bit(WL1271_FLAG_STA_ASSOCIATED, &wl->flags) ||
561 (!wl->conf.rx_streaming.always &&
562 !test_bit(WL1271_FLAG_SOFT_GEMINI, &wl->flags)))
563 goto out;
564
565 if (!wl->conf.rx_streaming.interval)
566 goto out;
567
568 ret = wl1271_ps_elp_wakeup(wl);
569 if (ret < 0)
570 goto out;
571
572 ret = wl1271_set_rx_streaming(wl, true);
573 if (ret < 0)
574 goto out_sleep;
575
576 /* stop it after some time of inactivity */
577 mod_timer(&wl->rx_streaming_timer,
578 jiffies + msecs_to_jiffies(wl->conf.rx_streaming.duration));
579
580out_sleep:
581 wl1271_ps_elp_sleep(wl);
582out:
583 mutex_unlock(&wl->mutex);
584}
585
586static void wl1271_rx_streaming_disable_work(struct work_struct *work)
587{
588 int ret;
589 struct wl1271 *wl =
590 container_of(work, struct wl1271, rx_streaming_disable_work);
591
592 mutex_lock(&wl->mutex);
593
594 if (!test_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags))
595 goto out;
596
597 ret = wl1271_ps_elp_wakeup(wl);
598 if (ret < 0)
599 goto out;
600
601 ret = wl1271_set_rx_streaming(wl, false);
602 if (ret)
603 goto out_sleep;
604
605out_sleep:
606 wl1271_ps_elp_sleep(wl);
607out:
608 mutex_unlock(&wl->mutex);
609}
610
611static void wl1271_rx_streaming_timer(unsigned long data)
612{
613 struct wl1271 *wl = (struct wl1271 *)data;
614 ieee80211_queue_work(wl->hw, &wl->rx_streaming_disable_work);
615}
616
476static void wl1271_conf_init(struct wl1271 *wl) 617static void wl1271_conf_init(struct wl1271 *wl)
477{ 618{
478 619
@@ -488,8 +629,24 @@ static void wl1271_conf_init(struct wl1271 *wl)
488 629
489 /* apply driver default configuration */ 630 /* apply driver default configuration */
490 memcpy(&wl->conf, &default_conf, sizeof(default_conf)); 631 memcpy(&wl->conf, &default_conf, sizeof(default_conf));
491}
492 632
633 /* Adjust settings according to optional module parameters */
634 if (fwlog_param) {
635 if (!strcmp(fwlog_param, "continuous")) {
636 wl->conf.fwlog.mode = WL12XX_FWLOG_CONTINUOUS;
637 } else if (!strcmp(fwlog_param, "ondemand")) {
638 wl->conf.fwlog.mode = WL12XX_FWLOG_ON_DEMAND;
639 } else if (!strcmp(fwlog_param, "dbgpins")) {
640 wl->conf.fwlog.mode = WL12XX_FWLOG_CONTINUOUS;
641 wl->conf.fwlog.output = WL12XX_FWLOG_OUTPUT_DBG_PINS;
642 } else if (!strcmp(fwlog_param, "disable")) {
643 wl->conf.fwlog.mem_blocks = 0;
644 wl->conf.fwlog.output = WL12XX_FWLOG_OUTPUT_NONE;
645 } else {
646 wl1271_error("Unknown fwlog parameter %s", fwlog_param);
647 }
648 }
649}
493 650
494static int wl1271_plt_init(struct wl1271 *wl) 651static int wl1271_plt_init(struct wl1271 *wl)
495{ 652{
@@ -667,13 +824,24 @@ static void wl1271_irq_update_links_status(struct wl1271 *wl,
667 } 824 }
668} 825}
669 826
827static u32 wl1271_tx_allocated_blocks(struct wl1271 *wl)
828{
829 int i;
830 u32 total_alloc_blocks = 0;
831
832 for (i = 0; i < NUM_TX_QUEUES; i++)
833 total_alloc_blocks += wl->tx_allocated_blocks[i];
834
835 return total_alloc_blocks;
836}
837
670static void wl1271_fw_status(struct wl1271 *wl, 838static void wl1271_fw_status(struct wl1271 *wl,
671 struct wl1271_fw_full_status *full_status) 839 struct wl1271_fw_full_status *full_status)
672{ 840{
673 struct wl1271_fw_common_status *status = &full_status->common; 841 struct wl1271_fw_common_status *status = &full_status->common;
674 struct timespec ts; 842 struct timespec ts;
675 u32 old_tx_blk_count = wl->tx_blocks_available; 843 u32 old_tx_blk_count = wl->tx_blocks_available;
676 u32 freed_blocks = 0; 844 u32 freed_blocks = 0, ac_freed_blocks;
677 int i; 845 int i;
678 846
679 if (wl->bss_type == BSS_TYPE_AP_BSS) { 847 if (wl->bss_type == BSS_TYPE_AP_BSS) {
@@ -693,21 +861,23 @@ static void wl1271_fw_status(struct wl1271 *wl,
693 861
694 /* update number of available TX blocks */ 862 /* update number of available TX blocks */
695 for (i = 0; i < NUM_TX_QUEUES; i++) { 863 for (i = 0; i < NUM_TX_QUEUES; i++) {
696 freed_blocks += le32_to_cpu(status->tx_released_blks[i]) - 864 ac_freed_blocks = le32_to_cpu(status->tx_released_blks[i]) -
697 wl->tx_blocks_freed[i]; 865 wl->tx_blocks_freed[i];
866 freed_blocks += ac_freed_blocks;
867
868 wl->tx_allocated_blocks[i] -= ac_freed_blocks;
698 869
699 wl->tx_blocks_freed[i] = 870 wl->tx_blocks_freed[i] =
700 le32_to_cpu(status->tx_released_blks[i]); 871 le32_to_cpu(status->tx_released_blks[i]);
701 } 872 }
702 873
703 wl->tx_allocated_blocks -= freed_blocks;
704
705 if (wl->bss_type == BSS_TYPE_AP_BSS) { 874 if (wl->bss_type == BSS_TYPE_AP_BSS) {
706 /* Update num of allocated TX blocks per link and ps status */ 875 /* Update num of allocated TX blocks per link and ps status */
707 wl1271_irq_update_links_status(wl, &full_status->ap); 876 wl1271_irq_update_links_status(wl, &full_status->ap);
708 wl->tx_blocks_available += freed_blocks; 877 wl->tx_blocks_available += freed_blocks;
709 } else { 878 } else {
710 int avail = full_status->sta.tx_total - wl->tx_allocated_blocks; 879 int avail = full_status->sta.tx_total -
880 wl1271_tx_allocated_blocks(wl);
711 881
712 /* 882 /*
713 * The FW might change the total number of TX memblocks before 883 * The FW might change the total number of TX memblocks before
@@ -741,7 +911,7 @@ static void wl1271_flush_deferred_work(struct wl1271 *wl)
741 911
742 /* Return sent skbs to the network stack */ 912 /* Return sent skbs to the network stack */
743 while ((skb = skb_dequeue(&wl->deferred_tx_queue))) 913 while ((skb = skb_dequeue(&wl->deferred_tx_queue)))
744 ieee80211_tx_status(wl->hw, skb); 914 ieee80211_tx_status_ni(wl->hw, skb);
745} 915}
746 916
747static void wl1271_netstack_work(struct work_struct *work) 917static void wl1271_netstack_work(struct work_struct *work)
@@ -808,7 +978,7 @@ irqreturn_t wl1271_irq(int irq, void *cookie)
808 if (unlikely(intr & WL1271_ACX_INTR_WATCHDOG)) { 978 if (unlikely(intr & WL1271_ACX_INTR_WATCHDOG)) {
809 wl1271_error("watchdog interrupt received! " 979 wl1271_error("watchdog interrupt received! "
810 "starting recovery."); 980 "starting recovery.");
811 ieee80211_queue_work(wl->hw, &wl->recovery_work); 981 wl12xx_queue_recovery_work(wl);
812 982
813 /* restarting the chip. ignore any other interrupt. */ 983 /* restarting the chip. ignore any other interrupt. */
814 goto out; 984 goto out;
@@ -822,7 +992,7 @@ irqreturn_t wl1271_irq(int irq, void *cookie)
822 /* Check if any tx blocks were freed */ 992 /* Check if any tx blocks were freed */
823 spin_lock_irqsave(&wl->wl_lock, flags); 993 spin_lock_irqsave(&wl->wl_lock, flags);
824 if (!test_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags) && 994 if (!test_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags) &&
825 wl->tx_queue_count) { 995 wl1271_tx_total_queue_count(wl) > 0) {
826 spin_unlock_irqrestore(&wl->wl_lock, flags); 996 spin_unlock_irqrestore(&wl->wl_lock, flags);
827 /* 997 /*
828 * In order to avoid starvation of the TX path, 998 * In order to avoid starvation of the TX path,
@@ -870,7 +1040,7 @@ out:
870 /* In case TX was not handled here, queue TX work */ 1040 /* In case TX was not handled here, queue TX work */
871 clear_bit(WL1271_FLAG_TX_PENDING, &wl->flags); 1041 clear_bit(WL1271_FLAG_TX_PENDING, &wl->flags);
872 if (!test_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags) && 1042 if (!test_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags) &&
873 wl->tx_queue_count) 1043 wl1271_tx_total_queue_count(wl) > 0)
874 ieee80211_queue_work(wl->hw, &wl->tx_work); 1044 ieee80211_queue_work(wl->hw, &wl->tx_work);
875 spin_unlock_irqrestore(&wl->wl_lock, flags); 1045 spin_unlock_irqrestore(&wl->wl_lock, flags);
876 1046
@@ -970,6 +1140,89 @@ out:
970 return ret; 1140 return ret;
971} 1141}
972 1142
1143void wl12xx_queue_recovery_work(struct wl1271 *wl)
1144{
1145 if (!test_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags))
1146 ieee80211_queue_work(wl->hw, &wl->recovery_work);
1147}
1148
1149size_t wl12xx_copy_fwlog(struct wl1271 *wl, u8 *memblock, size_t maxlen)
1150{
1151 size_t len = 0;
1152
1153 /* The FW log is a length-value list, find where the log end */
1154 while (len < maxlen) {
1155 if (memblock[len] == 0)
1156 break;
1157 if (len + memblock[len] + 1 > maxlen)
1158 break;
1159 len += memblock[len] + 1;
1160 }
1161
1162 /* Make sure we have enough room */
1163 len = min(len, (size_t)(PAGE_SIZE - wl->fwlog_size));
1164
1165 /* Fill the FW log file, consumed by the sysfs fwlog entry */
1166 memcpy(wl->fwlog + wl->fwlog_size, memblock, len);
1167 wl->fwlog_size += len;
1168
1169 return len;
1170}
1171
1172static void wl12xx_read_fwlog_panic(struct wl1271 *wl)
1173{
1174 u32 addr;
1175 u32 first_addr;
1176 u8 *block;
1177
1178 if ((wl->quirks & WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED) ||
1179 (wl->conf.fwlog.mode != WL12XX_FWLOG_ON_DEMAND) ||
1180 (wl->conf.fwlog.mem_blocks == 0))
1181 return;
1182
1183 wl1271_info("Reading FW panic log");
1184
1185 block = kmalloc(WL12XX_HW_BLOCK_SIZE, GFP_KERNEL);
1186 if (!block)
1187 return;
1188
1189 /*
1190 * Make sure the chip is awake and the logger isn't active.
1191 * This might fail if the firmware hanged.
1192 */
1193 if (!wl1271_ps_elp_wakeup(wl))
1194 wl12xx_cmd_stop_fwlog(wl);
1195
1196 /* Read the first memory block address */
1197 wl1271_fw_status(wl, wl->fw_status);
1198 first_addr = __le32_to_cpu(wl->fw_status->sta.log_start_addr);
1199 if (!first_addr)
1200 goto out;
1201
1202 /* Traverse the memory blocks linked list */
1203 addr = first_addr;
1204 do {
1205 memset(block, 0, WL12XX_HW_BLOCK_SIZE);
1206 wl1271_read_hwaddr(wl, addr, block, WL12XX_HW_BLOCK_SIZE,
1207 false);
1208
1209 /*
1210 * Memory blocks are linked to one another. The first 4 bytes
1211 * of each memory block hold the hardware address of the next
1212 * one. The last memory block points to the first one.
1213 */
1214 addr = __le32_to_cpup((__le32 *)block);
1215 if (!wl12xx_copy_fwlog(wl, block + sizeof(addr),
1216 WL12XX_HW_BLOCK_SIZE - sizeof(addr)))
1217 break;
1218 } while (addr && (addr != first_addr));
1219
1220 wake_up_interruptible(&wl->fwlog_waitq);
1221
1222out:
1223 kfree(block);
1224}
1225
973static void wl1271_recovery_work(struct work_struct *work) 1226static void wl1271_recovery_work(struct work_struct *work)
974{ 1227{
975 struct wl1271 *wl = 1228 struct wl1271 *wl =
@@ -980,9 +1233,23 @@ static void wl1271_recovery_work(struct work_struct *work)
980 if (wl->state != WL1271_STATE_ON) 1233 if (wl->state != WL1271_STATE_ON)
981 goto out; 1234 goto out;
982 1235
1236 /* Avoid a recursive recovery */
1237 set_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags);
1238
1239 wl12xx_read_fwlog_panic(wl);
1240
983 wl1271_info("Hardware recovery in progress. FW ver: %s pc: 0x%x", 1241 wl1271_info("Hardware recovery in progress. FW ver: %s pc: 0x%x",
984 wl->chip.fw_ver_str, wl1271_read32(wl, SCR_PAD4)); 1242 wl->chip.fw_ver_str, wl1271_read32(wl, SCR_PAD4));
985 1243
1244 /*
1245 * Advance security sequence number to overcome potential progress
1246 * in the firmware during recovery. This doens't hurt if the network is
1247 * not encrypted.
1248 */
1249 if (test_bit(WL1271_FLAG_STA_ASSOCIATED, &wl->flags) ||
1250 test_bit(WL1271_FLAG_AP_STARTED, &wl->flags))
1251 wl->tx_security_seq += WL1271_TX_SQN_POST_RECOVERY_PADDING;
1252
986 if (test_bit(WL1271_FLAG_STA_ASSOCIATED, &wl->flags)) 1253 if (test_bit(WL1271_FLAG_STA_ASSOCIATED, &wl->flags))
987 ieee80211_connection_loss(wl->vif); 1254 ieee80211_connection_loss(wl->vif);
988 1255
@@ -996,6 +1263,9 @@ static void wl1271_recovery_work(struct work_struct *work)
996 1263
997 /* reboot the chipset */ 1264 /* reboot the chipset */
998 __wl1271_op_remove_interface(wl, false); 1265 __wl1271_op_remove_interface(wl, false);
1266
1267 clear_bit(WL1271_FLAG_RECOVERY_IN_PROGRESS, &wl->flags);
1268
999 ieee80211_restart_hw(wl->hw); 1269 ieee80211_restart_hw(wl->hw);
1000 1270
1001 /* 1271 /*
@@ -1074,9 +1344,13 @@ static int wl1271_chip_wakeup(struct wl1271 *wl)
1074 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)", 1344 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (1271 PG20)",
1075 wl->chip.id); 1345 wl->chip.id);
1076 1346
1077 /* end-of-transaction flag should be set in wl127x AP mode */ 1347 /*
1348 * 'end-of-transaction flag' and 'LPD mode flag'
1349 * should be set in wl127x AP mode only
1350 */
1078 if (wl->bss_type == BSS_TYPE_AP_BSS) 1351 if (wl->bss_type == BSS_TYPE_AP_BSS)
1079 wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION; 1352 wl->quirks |= (WL12XX_QUIRK_END_OF_TRANSACTION |
1353 WL12XX_QUIRK_LPD_MODE);
1080 1354
1081 ret = wl1271_setup(wl); 1355 ret = wl1271_setup(wl);
1082 if (ret < 0) 1356 if (ret < 0)
@@ -1089,6 +1363,7 @@ static int wl1271_chip_wakeup(struct wl1271 *wl)
1089 ret = wl1271_setup(wl); 1363 ret = wl1271_setup(wl);
1090 if (ret < 0) 1364 if (ret < 0)
1091 goto out; 1365 goto out;
1366
1092 if (wl1271_set_block_size(wl)) 1367 if (wl1271_set_block_size(wl))
1093 wl->quirks |= WL12XX_QUIRK_BLOCKSIZE_ALIGNMENT; 1368 wl->quirks |= WL12XX_QUIRK_BLOCKSIZE_ALIGNMENT;
1094 break; 1369 break;
@@ -1117,24 +1392,6 @@ out:
1117 return ret; 1392 return ret;
1118} 1393}
1119 1394
1120static unsigned int wl1271_get_fw_ver_quirks(struct wl1271 *wl)
1121{
1122 unsigned int quirks = 0;
1123 unsigned int *fw_ver = wl->chip.fw_ver;
1124
1125 /* Only for wl127x */
1126 if ((fw_ver[FW_VER_CHIP] == FW_VER_CHIP_WL127X) &&
1127 /* Check STA version */
1128 (((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_STA) &&
1129 (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_1_SPARE_STA_MIN)) ||
1130 /* Check AP version */
1131 ((fw_ver[FW_VER_IF_TYPE] == FW_VER_IF_TYPE_AP) &&
1132 (fw_ver[FW_VER_MINOR] < FW_VER_MINOR_1_SPARE_AP_MIN))))
1133 quirks |= WL12XX_QUIRK_USE_2_SPARE_BLOCKS;
1134
1135 return quirks;
1136}
1137
1138int wl1271_plt_start(struct wl1271 *wl) 1395int wl1271_plt_start(struct wl1271 *wl)
1139{ 1396{
1140 int retries = WL1271_BOOT_RETRIES; 1397 int retries = WL1271_BOOT_RETRIES;
@@ -1171,8 +1428,6 @@ int wl1271_plt_start(struct wl1271 *wl)
1171 wl1271_notice("firmware booted in PLT mode (%s)", 1428 wl1271_notice("firmware booted in PLT mode (%s)",
1172 wl->chip.fw_ver_str); 1429 wl->chip.fw_ver_str);
1173 1430
1174 /* Check if any quirks are needed with older fw versions */
1175 wl->quirks |= wl1271_get_fw_ver_quirks(wl);
1176 goto out; 1431 goto out;
1177 1432
1178irq_disable: 1433irq_disable:
@@ -1242,26 +1497,27 @@ static void wl1271_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1242{ 1497{
1243 struct wl1271 *wl = hw->priv; 1498 struct wl1271 *wl = hw->priv;
1244 unsigned long flags; 1499 unsigned long flags;
1245 int q; 1500 int q, mapping;
1246 u8 hlid = 0; 1501 u8 hlid = 0;
1247 1502
1248 q = wl1271_tx_get_queue(skb_get_queue_mapping(skb)); 1503 mapping = skb_get_queue_mapping(skb);
1504 q = wl1271_tx_get_queue(mapping);
1249 1505
1250 if (wl->bss_type == BSS_TYPE_AP_BSS) 1506 if (wl->bss_type == BSS_TYPE_AP_BSS)
1251 hlid = wl1271_tx_get_hlid(skb); 1507 hlid = wl1271_tx_get_hlid(skb);
1252 1508
1253 spin_lock_irqsave(&wl->wl_lock, flags); 1509 spin_lock_irqsave(&wl->wl_lock, flags);
1254 1510
1255 wl->tx_queue_count++; 1511 wl->tx_queue_count[q]++;
1256 1512
1257 /* 1513 /*
1258 * The workqueue is slow to process the tx_queue and we need stop 1514 * The workqueue is slow to process the tx_queue and we need stop
1259 * the queue here, otherwise the queue will get too long. 1515 * the queue here, otherwise the queue will get too long.
1260 */ 1516 */
1261 if (wl->tx_queue_count >= WL1271_TX_QUEUE_HIGH_WATERMARK) { 1517 if (wl->tx_queue_count[q] >= WL1271_TX_QUEUE_HIGH_WATERMARK) {
1262 wl1271_debug(DEBUG_TX, "op_tx: stopping queues"); 1518 wl1271_debug(DEBUG_TX, "op_tx: stopping queues for q %d", q);
1263 ieee80211_stop_queues(wl->hw); 1519 ieee80211_stop_queue(wl->hw, mapping);
1264 set_bit(WL1271_FLAG_TX_QUEUE_STOPPED, &wl->flags); 1520 set_bit(q, &wl->stopped_queues_map);
1265 } 1521 }
1266 1522
1267 /* queue the packet */ 1523 /* queue the packet */
@@ -1287,10 +1543,11 @@ static void wl1271_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1287int wl1271_tx_dummy_packet(struct wl1271 *wl) 1543int wl1271_tx_dummy_packet(struct wl1271 *wl)
1288{ 1544{
1289 unsigned long flags; 1545 unsigned long flags;
1546 int q = wl1271_tx_get_queue(skb_get_queue_mapping(wl->dummy_packet));
1290 1547
1291 spin_lock_irqsave(&wl->wl_lock, flags); 1548 spin_lock_irqsave(&wl->wl_lock, flags);
1292 set_bit(WL1271_FLAG_DUMMY_PACKET_PENDING, &wl->flags); 1549 set_bit(WL1271_FLAG_DUMMY_PACKET_PENDING, &wl->flags);
1293 wl->tx_queue_count++; 1550 wl->tx_queue_count[q]++;
1294 spin_unlock_irqrestore(&wl->wl_lock, flags); 1551 spin_unlock_irqrestore(&wl->wl_lock, flags);
1295 1552
1296 /* The FW is low on RX memory blocks, so send the dummy packet asap */ 1553 /* The FW is low on RX memory blocks, so send the dummy packet asap */
@@ -1352,15 +1609,15 @@ static struct notifier_block wl1271_dev_notifier = {
1352}; 1609};
1353 1610
1354#ifdef CONFIG_PM 1611#ifdef CONFIG_PM
1355static int wl1271_configure_suspend(struct wl1271 *wl) 1612static int wl1271_configure_suspend_sta(struct wl1271 *wl)
1356{ 1613{
1357 int ret; 1614 int ret = 0;
1358
1359 if (wl->bss_type != BSS_TYPE_STA_BSS)
1360 return 0;
1361 1615
1362 mutex_lock(&wl->mutex); 1616 mutex_lock(&wl->mutex);
1363 1617
1618 if (!test_bit(WL1271_FLAG_STA_ASSOCIATED, &wl->flags))
1619 goto out_unlock;
1620
1364 ret = wl1271_ps_elp_wakeup(wl); 1621 ret = wl1271_ps_elp_wakeup(wl);
1365 if (ret < 0) 1622 if (ret < 0)
1366 goto out_unlock; 1623 goto out_unlock;
@@ -1403,11 +1660,44 @@ out:
1403 1660
1404} 1661}
1405 1662
1663static int wl1271_configure_suspend_ap(struct wl1271 *wl)
1664{
1665 int ret = 0;
1666
1667 mutex_lock(&wl->mutex);
1668
1669 if (!test_bit(WL1271_FLAG_AP_STARTED, &wl->flags))
1670 goto out_unlock;
1671
1672 ret = wl1271_ps_elp_wakeup(wl);
1673 if (ret < 0)
1674 goto out_unlock;
1675
1676 ret = wl1271_acx_set_ap_beacon_filter(wl, true);
1677
1678 wl1271_ps_elp_sleep(wl);
1679out_unlock:
1680 mutex_unlock(&wl->mutex);
1681 return ret;
1682
1683}
1684
1685static int wl1271_configure_suspend(struct wl1271 *wl)
1686{
1687 if (wl->bss_type == BSS_TYPE_STA_BSS)
1688 return wl1271_configure_suspend_sta(wl);
1689 if (wl->bss_type == BSS_TYPE_AP_BSS)
1690 return wl1271_configure_suspend_ap(wl);
1691 return 0;
1692}
1693
1406static void wl1271_configure_resume(struct wl1271 *wl) 1694static void wl1271_configure_resume(struct wl1271 *wl)
1407{ 1695{
1408 int ret; 1696 int ret;
1697 bool is_sta = wl->bss_type == BSS_TYPE_STA_BSS;
1698 bool is_ap = wl->bss_type == BSS_TYPE_AP_BSS;
1409 1699
1410 if (wl->bss_type != BSS_TYPE_STA_BSS) 1700 if (!is_sta && !is_ap)
1411 return; 1701 return;
1412 1702
1413 mutex_lock(&wl->mutex); 1703 mutex_lock(&wl->mutex);
@@ -1415,10 +1705,14 @@ static void wl1271_configure_resume(struct wl1271 *wl)
1415 if (ret < 0) 1705 if (ret < 0)
1416 goto out; 1706 goto out;
1417 1707
1418 /* exit psm if it wasn't configured */ 1708 if (is_sta) {
1419 if (!test_bit(WL1271_FLAG_PSM_REQUESTED, &wl->flags)) 1709 /* exit psm if it wasn't configured */
1420 wl1271_ps_set_mode(wl, STATION_ACTIVE_MODE, 1710 if (!test_bit(WL1271_FLAG_PSM_REQUESTED, &wl->flags))
1421 wl->basic_rate, true); 1711 wl1271_ps_set_mode(wl, STATION_ACTIVE_MODE,
1712 wl->basic_rate, true);
1713 } else if (is_ap) {
1714 wl1271_acx_set_ap_beacon_filter(wl, false);
1715 }
1422 1716
1423 wl1271_ps_elp_sleep(wl); 1717 wl1271_ps_elp_sleep(wl);
1424out: 1718out:
@@ -1429,69 +1723,68 @@ static int wl1271_op_suspend(struct ieee80211_hw *hw,
1429 struct cfg80211_wowlan *wow) 1723 struct cfg80211_wowlan *wow)
1430{ 1724{
1431 struct wl1271 *wl = hw->priv; 1725 struct wl1271 *wl = hw->priv;
1726 int ret;
1727
1432 wl1271_debug(DEBUG_MAC80211, "mac80211 suspend wow=%d", !!wow); 1728 wl1271_debug(DEBUG_MAC80211, "mac80211 suspend wow=%d", !!wow);
1433 wl->wow_enabled = !!wow; 1729 WARN_ON(!wow || !wow->any);
1434 if (wl->wow_enabled) {
1435 int ret;
1436 ret = wl1271_configure_suspend(wl);
1437 if (ret < 0) {
1438 wl1271_warning("couldn't prepare device to suspend");
1439 return ret;
1440 }
1441 /* flush any remaining work */
1442 wl1271_debug(DEBUG_MAC80211, "flushing remaining works");
1443 flush_delayed_work(&wl->scan_complete_work);
1444 1730
1445 /* 1731 wl->wow_enabled = true;
1446 * disable and re-enable interrupts in order to flush 1732 ret = wl1271_configure_suspend(wl);
1447 * the threaded_irq 1733 if (ret < 0) {
1448 */ 1734 wl1271_warning("couldn't prepare device to suspend");
1449 wl1271_disable_interrupts(wl); 1735 return ret;
1736 }
1737 /* flush any remaining work */
1738 wl1271_debug(DEBUG_MAC80211, "flushing remaining works");
1450 1739
1451 /* 1740 /*
1452 * set suspended flag to avoid triggering a new threaded_irq 1741 * disable and re-enable interrupts in order to flush
1453 * work. no need for spinlock as interrupts are disabled. 1742 * the threaded_irq
1454 */ 1743 */
1455 set_bit(WL1271_FLAG_SUSPENDED, &wl->flags); 1744 wl1271_disable_interrupts(wl);
1745
1746 /*
1747 * set suspended flag to avoid triggering a new threaded_irq
1748 * work. no need for spinlock as interrupts are disabled.
1749 */
1750 set_bit(WL1271_FLAG_SUSPENDED, &wl->flags);
1751
1752 wl1271_enable_interrupts(wl);
1753 flush_work(&wl->tx_work);
1754 flush_delayed_work(&wl->pspoll_work);
1755 flush_delayed_work(&wl->elp_work);
1456 1756
1457 wl1271_enable_interrupts(wl);
1458 flush_work(&wl->tx_work);
1459 flush_delayed_work(&wl->pspoll_work);
1460 flush_delayed_work(&wl->elp_work);
1461 }
1462 return 0; 1757 return 0;
1463} 1758}
1464 1759
1465static int wl1271_op_resume(struct ieee80211_hw *hw) 1760static int wl1271_op_resume(struct ieee80211_hw *hw)
1466{ 1761{
1467 struct wl1271 *wl = hw->priv; 1762 struct wl1271 *wl = hw->priv;
1763 unsigned long flags;
1764 bool run_irq_work = false;
1765
1468 wl1271_debug(DEBUG_MAC80211, "mac80211 resume wow=%d", 1766 wl1271_debug(DEBUG_MAC80211, "mac80211 resume wow=%d",
1469 wl->wow_enabled); 1767 wl->wow_enabled);
1768 WARN_ON(!wl->wow_enabled);
1470 1769
1471 /* 1770 /*
1472 * re-enable irq_work enqueuing, and call irq_work directly if 1771 * re-enable irq_work enqueuing, and call irq_work directly if
1473 * there is a pending work. 1772 * there is a pending work.
1474 */ 1773 */
1475 if (wl->wow_enabled) { 1774 spin_lock_irqsave(&wl->wl_lock, flags);
1476 struct wl1271 *wl = hw->priv; 1775 clear_bit(WL1271_FLAG_SUSPENDED, &wl->flags);
1477 unsigned long flags; 1776 if (test_and_clear_bit(WL1271_FLAG_PENDING_WORK, &wl->flags))
1478 bool run_irq_work = false; 1777 run_irq_work = true;
1479 1778 spin_unlock_irqrestore(&wl->wl_lock, flags);
1480 spin_lock_irqsave(&wl->wl_lock, flags);
1481 clear_bit(WL1271_FLAG_SUSPENDED, &wl->flags);
1482 if (test_and_clear_bit(WL1271_FLAG_PENDING_WORK, &wl->flags))
1483 run_irq_work = true;
1484 spin_unlock_irqrestore(&wl->wl_lock, flags);
1485
1486 if (run_irq_work) {
1487 wl1271_debug(DEBUG_MAC80211,
1488 "run postponed irq_work directly");
1489 wl1271_irq(0, wl);
1490 wl1271_enable_interrupts(wl);
1491 }
1492 1779
1493 wl1271_configure_resume(wl); 1780 if (run_irq_work) {
1781 wl1271_debug(DEBUG_MAC80211,
1782 "run postponed irq_work directly");
1783 wl1271_irq(0, wl);
1784 wl1271_enable_interrupts(wl);
1494 } 1785 }
1786 wl1271_configure_resume(wl);
1787 wl->wow_enabled = false;
1495 1788
1496 return 0; 1789 return 0;
1497} 1790}
@@ -1629,9 +1922,6 @@ power_off:
1629 strncpy(wiphy->fw_version, wl->chip.fw_ver_str, 1922 strncpy(wiphy->fw_version, wl->chip.fw_ver_str,
1630 sizeof(wiphy->fw_version)); 1923 sizeof(wiphy->fw_version));
1631 1924
1632 /* Check if any quirks are needed with older fw versions */
1633 wl->quirks |= wl1271_get_fw_ver_quirks(wl);
1634
1635 /* 1925 /*
1636 * Now we know if 11a is supported (info from the NVS), so disable 1926 * Now we know if 11a is supported (info from the NVS), so disable
1637 * 11a channels if not supported 1927 * 11a channels if not supported
@@ -1694,6 +1984,9 @@ static void __wl1271_op_remove_interface(struct wl1271 *wl,
1694 cancel_delayed_work_sync(&wl->scan_complete_work); 1984 cancel_delayed_work_sync(&wl->scan_complete_work);
1695 cancel_work_sync(&wl->netstack_work); 1985 cancel_work_sync(&wl->netstack_work);
1696 cancel_work_sync(&wl->tx_work); 1986 cancel_work_sync(&wl->tx_work);
1987 del_timer_sync(&wl->rx_streaming_timer);
1988 cancel_work_sync(&wl->rx_streaming_enable_work);
1989 cancel_work_sync(&wl->rx_streaming_disable_work);
1697 cancel_delayed_work_sync(&wl->pspoll_work); 1990 cancel_delayed_work_sync(&wl->pspoll_work);
1698 cancel_delayed_work_sync(&wl->elp_work); 1991 cancel_delayed_work_sync(&wl->elp_work);
1699 1992
@@ -1714,11 +2007,8 @@ static void __wl1271_op_remove_interface(struct wl1271 *wl,
1714 wl->psm_entry_retry = 0; 2007 wl->psm_entry_retry = 0;
1715 wl->power_level = WL1271_DEFAULT_POWER_LEVEL; 2008 wl->power_level = WL1271_DEFAULT_POWER_LEVEL;
1716 wl->tx_blocks_available = 0; 2009 wl->tx_blocks_available = 0;
1717 wl->tx_allocated_blocks = 0;
1718 wl->tx_results_count = 0; 2010 wl->tx_results_count = 0;
1719 wl->tx_packets_count = 0; 2011 wl->tx_packets_count = 0;
1720 wl->tx_security_last_seq = 0;
1721 wl->tx_security_seq = 0;
1722 wl->time_offset = 0; 2012 wl->time_offset = 0;
1723 wl->session_counter = 0; 2013 wl->session_counter = 0;
1724 wl->rate_set = CONF_TX_RATE_MASK_BASIC; 2014 wl->rate_set = CONF_TX_RATE_MASK_BASIC;
@@ -1737,8 +2027,10 @@ static void __wl1271_op_remove_interface(struct wl1271 *wl,
1737 */ 2027 */
1738 wl->flags = 0; 2028 wl->flags = 0;
1739 2029
1740 for (i = 0; i < NUM_TX_QUEUES; i++) 2030 for (i = 0; i < NUM_TX_QUEUES; i++) {
1741 wl->tx_blocks_freed[i] = 0; 2031 wl->tx_blocks_freed[i] = 0;
2032 wl->tx_allocated_blocks[i] = 0;
2033 }
1742 2034
1743 wl1271_debugfs_reset(wl); 2035 wl1271_debugfs_reset(wl);
1744 2036
@@ -1891,6 +2183,10 @@ static int wl1271_unjoin(struct wl1271 *wl)
1891 clear_bit(WL1271_FLAG_JOINED, &wl->flags); 2183 clear_bit(WL1271_FLAG_JOINED, &wl->flags);
1892 memset(wl->bssid, 0, ETH_ALEN); 2184 memset(wl->bssid, 0, ETH_ALEN);
1893 2185
2186 /* reset TX security counters on a clean disconnect */
2187 wl->tx_security_last_seq_lsb = 0;
2188 wl->tx_security_seq = 0;
2189
1894 /* stop filtering packets based on bssid */ 2190 /* stop filtering packets based on bssid */
1895 wl1271_configure_filters(wl, FIF_OTHER_BSS); 2191 wl1271_configure_filters(wl, FIF_OTHER_BSS);
1896 2192
@@ -1983,6 +2279,9 @@ static int wl1271_op_config(struct ieee80211_hw *hw, u32 changed)
1983 wl->channel = channel; 2279 wl->channel = channel;
1984 } 2280 }
1985 2281
2282 if ((changed & IEEE80211_CONF_CHANGE_POWER))
2283 wl->power_level = conf->power_level;
2284
1986 goto out; 2285 goto out;
1987 } 2286 }
1988 2287
@@ -2490,6 +2789,44 @@ out:
2490 return ret; 2789 return ret;
2491} 2790}
2492 2791
2792static void wl1271_op_cancel_hw_scan(struct ieee80211_hw *hw,
2793 struct ieee80211_vif *vif)
2794{
2795 struct wl1271 *wl = hw->priv;
2796 int ret;
2797
2798 wl1271_debug(DEBUG_MAC80211, "mac80211 cancel hw scan");
2799
2800 mutex_lock(&wl->mutex);
2801
2802 if (wl->state == WL1271_STATE_OFF)
2803 goto out;
2804
2805 if (wl->scan.state == WL1271_SCAN_STATE_IDLE)
2806 goto out;
2807
2808 ret = wl1271_ps_elp_wakeup(wl);
2809 if (ret < 0)
2810 goto out;
2811
2812 if (wl->scan.state != WL1271_SCAN_STATE_DONE) {
2813 ret = wl1271_scan_stop(wl);
2814 if (ret < 0)
2815 goto out_sleep;
2816 }
2817 wl->scan.state = WL1271_SCAN_STATE_IDLE;
2818 memset(wl->scan.scanned_ch, 0, sizeof(wl->scan.scanned_ch));
2819 wl->scan.req = NULL;
2820 ieee80211_scan_completed(wl->hw, true);
2821
2822out_sleep:
2823 wl1271_ps_elp_sleep(wl);
2824out:
2825 mutex_unlock(&wl->mutex);
2826
2827 cancel_delayed_work_sync(&wl->scan_complete_work);
2828}
2829
2493static int wl1271_op_sched_scan_start(struct ieee80211_hw *hw, 2830static int wl1271_op_sched_scan_start(struct ieee80211_hw *hw,
2494 struct ieee80211_vif *vif, 2831 struct ieee80211_vif *vif,
2495 struct cfg80211_sched_scan_request *req, 2832 struct cfg80211_sched_scan_request *req,
@@ -2780,24 +3117,6 @@ static void wl1271_bss_info_changed_ap(struct wl1271 *wl,
2780 } 3117 }
2781 } 3118 }
2782 3119
2783 if (changed & BSS_CHANGED_IBSS) {
2784 wl1271_debug(DEBUG_ADHOC, "ibss_joined: %d",
2785 bss_conf->ibss_joined);
2786
2787 if (bss_conf->ibss_joined) {
2788 u32 rates = bss_conf->basic_rates;
2789 wl->basic_rate_set = wl1271_tx_enabled_rates_get(wl,
2790 rates);
2791 wl->basic_rate = wl1271_tx_min_rate_get(wl);
2792
2793 /* by default, use 11b rates */
2794 wl->rate_set = CONF_TX_IBSS_DEFAULT_RATES;
2795 ret = wl1271_acx_sta_rate_policies(wl);
2796 if (ret < 0)
2797 goto out;
2798 }
2799 }
2800
2801 ret = wl1271_bss_erp_info_changed(wl, bss_conf, changed); 3120 ret = wl1271_bss_erp_info_changed(wl, bss_conf, changed);
2802 if (ret < 0) 3121 if (ret < 0)
2803 goto out; 3122 goto out;
@@ -3023,6 +3342,24 @@ static void wl1271_bss_info_changed_sta(struct wl1271 *wl,
3023 } 3342 }
3024 } 3343 }
3025 3344
3345 if (changed & BSS_CHANGED_IBSS) {
3346 wl1271_debug(DEBUG_ADHOC, "ibss_joined: %d",
3347 bss_conf->ibss_joined);
3348
3349 if (bss_conf->ibss_joined) {
3350 u32 rates = bss_conf->basic_rates;
3351 wl->basic_rate_set = wl1271_tx_enabled_rates_get(wl,
3352 rates);
3353 wl->basic_rate = wl1271_tx_min_rate_get(wl);
3354
3355 /* by default, use 11b rates */
3356 wl->rate_set = CONF_TX_IBSS_DEFAULT_RATES;
3357 ret = wl1271_acx_sta_rate_policies(wl);
3358 if (ret < 0)
3359 goto out;
3360 }
3361 }
3362
3026 ret = wl1271_bss_erp_info_changed(wl, bss_conf, changed); 3363 ret = wl1271_bss_erp_info_changed(wl, bss_conf, changed);
3027 if (ret < 0) 3364 if (ret < 0)
3028 goto out; 3365 goto out;
@@ -3061,6 +3398,7 @@ static void wl1271_bss_info_changed_sta(struct wl1271 *wl,
3061 wl1271_warning("cmd join failed %d", ret); 3398 wl1271_warning("cmd join failed %d", ret);
3062 goto out; 3399 goto out;
3063 } 3400 }
3401 wl1271_check_operstate(wl, ieee80211_get_operstate(vif));
3064 } 3402 }
3065 3403
3066out: 3404out:
@@ -3251,6 +3589,12 @@ static void wl1271_free_sta(struct wl1271 *wl, u8 hlid)
3251 __clear_bit(hlid, (unsigned long *)&wl->ap_fw_ps_map); 3589 __clear_bit(hlid, (unsigned long *)&wl->ap_fw_ps_map);
3252} 3590}
3253 3591
3592bool wl1271_is_active_sta(struct wl1271 *wl, u8 hlid)
3593{
3594 int id = hlid - WL1271_AP_STA_HLID_START;
3595 return test_bit(id, wl->ap_hlid_map);
3596}
3597
3254static int wl1271_op_sta_add(struct ieee80211_hw *hw, 3598static int wl1271_op_sta_add(struct ieee80211_hw *hw,
3255 struct ieee80211_vif *vif, 3599 struct ieee80211_vif *vif,
3256 struct ieee80211_sta *sta) 3600 struct ieee80211_sta *sta)
@@ -3354,9 +3698,12 @@ static int wl1271_op_ampdu_action(struct ieee80211_hw *hw,
3354 if (ret < 0) 3698 if (ret < 0)
3355 goto out; 3699 goto out;
3356 3700
3701 wl1271_debug(DEBUG_MAC80211, "mac80211 ampdu: Rx tid %d action %d",
3702 tid, action);
3703
3357 switch (action) { 3704 switch (action) {
3358 case IEEE80211_AMPDU_RX_START: 3705 case IEEE80211_AMPDU_RX_START:
3359 if (wl->ba_support) { 3706 if ((wl->ba_support) && (wl->ba_allowed)) {
3360 ret = wl1271_acx_set_ba_receiver_session(wl, tid, *ssn, 3707 ret = wl1271_acx_set_ba_receiver_session(wl, tid, *ssn,
3361 true); 3708 true);
3362 if (!ret) 3709 if (!ret)
@@ -3406,7 +3753,7 @@ static bool wl1271_tx_frames_pending(struct ieee80211_hw *hw)
3406 goto out; 3753 goto out;
3407 3754
3408 /* packets are considered pending if in the TX queue or the FW */ 3755 /* packets are considered pending if in the TX queue or the FW */
3409 ret = (wl->tx_queue_count > 0) || (wl->tx_frames_cnt > 0); 3756 ret = (wl1271_tx_total_queue_count(wl) > 0) || (wl->tx_frames_cnt > 0);
3410 3757
3411 /* the above is appropriate for STA mode for PS purposes */ 3758 /* the above is appropriate for STA mode for PS purposes */
3412 WARN_ON(wl->bss_type != BSS_TYPE_STA_BSS); 3759 WARN_ON(wl->bss_type != BSS_TYPE_STA_BSS);
@@ -3569,40 +3916,40 @@ static struct ieee80211_rate wl1271_rates_5ghz[] = {
3569 3916
3570/* 5 GHz band channels for WL1273 */ 3917/* 5 GHz band channels for WL1273 */
3571static struct ieee80211_channel wl1271_channels_5ghz[] = { 3918static struct ieee80211_channel wl1271_channels_5ghz[] = {
3572 { .hw_value = 7, .center_freq = 5035}, 3919 { .hw_value = 7, .center_freq = 5035, .max_power = 25 },
3573 { .hw_value = 8, .center_freq = 5040}, 3920 { .hw_value = 8, .center_freq = 5040, .max_power = 25 },
3574 { .hw_value = 9, .center_freq = 5045}, 3921 { .hw_value = 9, .center_freq = 5045, .max_power = 25 },
3575 { .hw_value = 11, .center_freq = 5055}, 3922 { .hw_value = 11, .center_freq = 5055, .max_power = 25 },
3576 { .hw_value = 12, .center_freq = 5060}, 3923 { .hw_value = 12, .center_freq = 5060, .max_power = 25 },
3577 { .hw_value = 16, .center_freq = 5080}, 3924 { .hw_value = 16, .center_freq = 5080, .max_power = 25 },
3578 { .hw_value = 34, .center_freq = 5170}, 3925 { .hw_value = 34, .center_freq = 5170, .max_power = 25 },
3579 { .hw_value = 36, .center_freq = 5180}, 3926 { .hw_value = 36, .center_freq = 5180, .max_power = 25 },
3580 { .hw_value = 38, .center_freq = 5190}, 3927 { .hw_value = 38, .center_freq = 5190, .max_power = 25 },
3581 { .hw_value = 40, .center_freq = 5200}, 3928 { .hw_value = 40, .center_freq = 5200, .max_power = 25 },
3582 { .hw_value = 42, .center_freq = 5210}, 3929 { .hw_value = 42, .center_freq = 5210, .max_power = 25 },
3583 { .hw_value = 44, .center_freq = 5220}, 3930 { .hw_value = 44, .center_freq = 5220, .max_power = 25 },
3584 { .hw_value = 46, .center_freq = 5230}, 3931 { .hw_value = 46, .center_freq = 5230, .max_power = 25 },
3585 { .hw_value = 48, .center_freq = 5240}, 3932 { .hw_value = 48, .center_freq = 5240, .max_power = 25 },
3586 { .hw_value = 52, .center_freq = 5260}, 3933 { .hw_value = 52, .center_freq = 5260, .max_power = 25 },
3587 { .hw_value = 56, .center_freq = 5280}, 3934 { .hw_value = 56, .center_freq = 5280, .max_power = 25 },
3588 { .hw_value = 60, .center_freq = 5300}, 3935 { .hw_value = 60, .center_freq = 5300, .max_power = 25 },
3589 { .hw_value = 64, .center_freq = 5320}, 3936 { .hw_value = 64, .center_freq = 5320, .max_power = 25 },
3590 { .hw_value = 100, .center_freq = 5500}, 3937 { .hw_value = 100, .center_freq = 5500, .max_power = 25 },
3591 { .hw_value = 104, .center_freq = 5520}, 3938 { .hw_value = 104, .center_freq = 5520, .max_power = 25 },
3592 { .hw_value = 108, .center_freq = 5540}, 3939 { .hw_value = 108, .center_freq = 5540, .max_power = 25 },
3593 { .hw_value = 112, .center_freq = 5560}, 3940 { .hw_value = 112, .center_freq = 5560, .max_power = 25 },
3594 { .hw_value = 116, .center_freq = 5580}, 3941 { .hw_value = 116, .center_freq = 5580, .max_power = 25 },
3595 { .hw_value = 120, .center_freq = 5600}, 3942 { .hw_value = 120, .center_freq = 5600, .max_power = 25 },
3596 { .hw_value = 124, .center_freq = 5620}, 3943 { .hw_value = 124, .center_freq = 5620, .max_power = 25 },
3597 { .hw_value = 128, .center_freq = 5640}, 3944 { .hw_value = 128, .center_freq = 5640, .max_power = 25 },
3598 { .hw_value = 132, .center_freq = 5660}, 3945 { .hw_value = 132, .center_freq = 5660, .max_power = 25 },
3599 { .hw_value = 136, .center_freq = 5680}, 3946 { .hw_value = 136, .center_freq = 5680, .max_power = 25 },
3600 { .hw_value = 140, .center_freq = 5700}, 3947 { .hw_value = 140, .center_freq = 5700, .max_power = 25 },
3601 { .hw_value = 149, .center_freq = 5745}, 3948 { .hw_value = 149, .center_freq = 5745, .max_power = 25 },
3602 { .hw_value = 153, .center_freq = 5765}, 3949 { .hw_value = 153, .center_freq = 5765, .max_power = 25 },
3603 { .hw_value = 157, .center_freq = 5785}, 3950 { .hw_value = 157, .center_freq = 5785, .max_power = 25 },
3604 { .hw_value = 161, .center_freq = 5805}, 3951 { .hw_value = 161, .center_freq = 5805, .max_power = 25 },
3605 { .hw_value = 165, .center_freq = 5825}, 3952 { .hw_value = 165, .center_freq = 5825, .max_power = 25 },
3606}; 3953};
3607 3954
3608/* mapping to indexes for wl1271_rates_5ghz */ 3955/* mapping to indexes for wl1271_rates_5ghz */
@@ -3663,6 +4010,7 @@ static const struct ieee80211_ops wl1271_ops = {
3663 .tx = wl1271_op_tx, 4010 .tx = wl1271_op_tx,
3664 .set_key = wl1271_op_set_key, 4011 .set_key = wl1271_op_set_key,
3665 .hw_scan = wl1271_op_hw_scan, 4012 .hw_scan = wl1271_op_hw_scan,
4013 .cancel_hw_scan = wl1271_op_cancel_hw_scan,
3666 .sched_scan_start = wl1271_op_sched_scan_start, 4014 .sched_scan_start = wl1271_op_sched_scan_start,
3667 .sched_scan_stop = wl1271_op_sched_scan_stop, 4015 .sched_scan_stop = wl1271_op_sched_scan_stop,
3668 .bss_info_changed = wl1271_op_bss_info_changed, 4016 .bss_info_changed = wl1271_op_bss_info_changed,
@@ -3781,6 +4129,69 @@ static ssize_t wl1271_sysfs_show_hw_pg_ver(struct device *dev,
3781static DEVICE_ATTR(hw_pg_ver, S_IRUGO | S_IWUSR, 4129static DEVICE_ATTR(hw_pg_ver, S_IRUGO | S_IWUSR,
3782 wl1271_sysfs_show_hw_pg_ver, NULL); 4130 wl1271_sysfs_show_hw_pg_ver, NULL);
3783 4131
4132static ssize_t wl1271_sysfs_read_fwlog(struct file *filp, struct kobject *kobj,
4133 struct bin_attribute *bin_attr,
4134 char *buffer, loff_t pos, size_t count)
4135{
4136 struct device *dev = container_of(kobj, struct device, kobj);
4137 struct wl1271 *wl = dev_get_drvdata(dev);
4138 ssize_t len;
4139 int ret;
4140
4141 ret = mutex_lock_interruptible(&wl->mutex);
4142 if (ret < 0)
4143 return -ERESTARTSYS;
4144
4145 /* Let only one thread read the log at a time, blocking others */
4146 while (wl->fwlog_size == 0) {
4147 DEFINE_WAIT(wait);
4148
4149 prepare_to_wait_exclusive(&wl->fwlog_waitq,
4150 &wait,
4151 TASK_INTERRUPTIBLE);
4152
4153 if (wl->fwlog_size != 0) {
4154 finish_wait(&wl->fwlog_waitq, &wait);
4155 break;
4156 }
4157
4158 mutex_unlock(&wl->mutex);
4159
4160 schedule();
4161 finish_wait(&wl->fwlog_waitq, &wait);
4162
4163 if (signal_pending(current))
4164 return -ERESTARTSYS;
4165
4166 ret = mutex_lock_interruptible(&wl->mutex);
4167 if (ret < 0)
4168 return -ERESTARTSYS;
4169 }
4170
4171 /* Check if the fwlog is still valid */
4172 if (wl->fwlog_size < 0) {
4173 mutex_unlock(&wl->mutex);
4174 return 0;
4175 }
4176
4177 /* Seeking is not supported - old logs are not kept. Disregard pos. */
4178 len = min(count, (size_t)wl->fwlog_size);
4179 wl->fwlog_size -= len;
4180 memcpy(buffer, wl->fwlog, len);
4181
4182 /* Make room for new messages */
4183 memmove(wl->fwlog, wl->fwlog + len, wl->fwlog_size);
4184
4185 mutex_unlock(&wl->mutex);
4186
4187 return len;
4188}
4189
4190static struct bin_attribute fwlog_attr = {
4191 .attr = {.name = "fwlog", .mode = S_IRUSR},
4192 .read = wl1271_sysfs_read_fwlog,
4193};
4194
3784int wl1271_register_hw(struct wl1271 *wl) 4195int wl1271_register_hw(struct wl1271 *wl)
3785{ 4196{
3786 int ret; 4197 int ret;
@@ -3961,6 +4372,17 @@ struct ieee80211_hw *wl1271_alloc_hw(void)
3961 INIT_WORK(&wl->tx_work, wl1271_tx_work); 4372 INIT_WORK(&wl->tx_work, wl1271_tx_work);
3962 INIT_WORK(&wl->recovery_work, wl1271_recovery_work); 4373 INIT_WORK(&wl->recovery_work, wl1271_recovery_work);
3963 INIT_DELAYED_WORK(&wl->scan_complete_work, wl1271_scan_complete_work); 4374 INIT_DELAYED_WORK(&wl->scan_complete_work, wl1271_scan_complete_work);
4375 INIT_WORK(&wl->rx_streaming_enable_work,
4376 wl1271_rx_streaming_enable_work);
4377 INIT_WORK(&wl->rx_streaming_disable_work,
4378 wl1271_rx_streaming_disable_work);
4379
4380 wl->freezable_wq = create_freezable_workqueue("wl12xx_wq");
4381 if (!wl->freezable_wq) {
4382 ret = -ENOMEM;
4383 goto err_hw;
4384 }
4385
3964 wl->channel = WL1271_DEFAULT_CHANNEL; 4386 wl->channel = WL1271_DEFAULT_CHANNEL;
3965 wl->beacon_int = WL1271_DEFAULT_BEACON_INT; 4387 wl->beacon_int = WL1271_DEFAULT_BEACON_INT;
3966 wl->default_key = 0; 4388 wl->default_key = 0;
@@ -3986,6 +4408,13 @@ struct ieee80211_hw *wl1271_alloc_hw(void)
3986 wl->quirks = 0; 4408 wl->quirks = 0;
3987 wl->platform_quirks = 0; 4409 wl->platform_quirks = 0;
3988 wl->sched_scanning = false; 4410 wl->sched_scanning = false;
4411 wl->tx_security_seq = 0;
4412 wl->tx_security_last_seq_lsb = 0;
4413
4414 setup_timer(&wl->rx_streaming_timer, wl1271_rx_streaming_timer,
4415 (unsigned long) wl);
4416 wl->fwlog_size = 0;
4417 init_waitqueue_head(&wl->fwlog_waitq);
3989 4418
3990 memset(wl->tx_frames_map, 0, sizeof(wl->tx_frames_map)); 4419 memset(wl->tx_frames_map, 0, sizeof(wl->tx_frames_map));
3991 for (i = 0; i < ACX_TX_DESCRIPTORS; i++) 4420 for (i = 0; i < ACX_TX_DESCRIPTORS; i++)
@@ -4003,7 +4432,7 @@ struct ieee80211_hw *wl1271_alloc_hw(void)
4003 wl->aggr_buf = (u8 *)__get_free_pages(GFP_KERNEL, order); 4432 wl->aggr_buf = (u8 *)__get_free_pages(GFP_KERNEL, order);
4004 if (!wl->aggr_buf) { 4433 if (!wl->aggr_buf) {
4005 ret = -ENOMEM; 4434 ret = -ENOMEM;
4006 goto err_hw; 4435 goto err_wq;
4007 } 4436 }
4008 4437
4009 wl->dummy_packet = wl12xx_alloc_dummy_packet(wl); 4438 wl->dummy_packet = wl12xx_alloc_dummy_packet(wl);
@@ -4012,11 +4441,18 @@ struct ieee80211_hw *wl1271_alloc_hw(void)
4012 goto err_aggr; 4441 goto err_aggr;
4013 } 4442 }
4014 4443
4444 /* Allocate one page for the FW log */
4445 wl->fwlog = (u8 *)get_zeroed_page(GFP_KERNEL);
4446 if (!wl->fwlog) {
4447 ret = -ENOMEM;
4448 goto err_dummy_packet;
4449 }
4450
4015 /* Register platform device */ 4451 /* Register platform device */
4016 ret = platform_device_register(wl->plat_dev); 4452 ret = platform_device_register(wl->plat_dev);
4017 if (ret) { 4453 if (ret) {
4018 wl1271_error("couldn't register platform device"); 4454 wl1271_error("couldn't register platform device");
4019 goto err_dummy_packet; 4455 goto err_fwlog;
4020 } 4456 }
4021 dev_set_drvdata(&wl->plat_dev->dev, wl); 4457 dev_set_drvdata(&wl->plat_dev->dev, wl);
4022 4458
@@ -4034,20 +4470,36 @@ struct ieee80211_hw *wl1271_alloc_hw(void)
4034 goto err_bt_coex_state; 4470 goto err_bt_coex_state;
4035 } 4471 }
4036 4472
4473 /* Create sysfs file for the FW log */
4474 ret = device_create_bin_file(&wl->plat_dev->dev, &fwlog_attr);
4475 if (ret < 0) {
4476 wl1271_error("failed to create sysfs file fwlog");
4477 goto err_hw_pg_ver;
4478 }
4479
4037 return hw; 4480 return hw;
4038 4481
4482err_hw_pg_ver:
4483 device_remove_file(&wl->plat_dev->dev, &dev_attr_hw_pg_ver);
4484
4039err_bt_coex_state: 4485err_bt_coex_state:
4040 device_remove_file(&wl->plat_dev->dev, &dev_attr_bt_coex_state); 4486 device_remove_file(&wl->plat_dev->dev, &dev_attr_bt_coex_state);
4041 4487
4042err_platform: 4488err_platform:
4043 platform_device_unregister(wl->plat_dev); 4489 platform_device_unregister(wl->plat_dev);
4044 4490
4491err_fwlog:
4492 free_page((unsigned long)wl->fwlog);
4493
4045err_dummy_packet: 4494err_dummy_packet:
4046 dev_kfree_skb(wl->dummy_packet); 4495 dev_kfree_skb(wl->dummy_packet);
4047 4496
4048err_aggr: 4497err_aggr:
4049 free_pages((unsigned long)wl->aggr_buf, order); 4498 free_pages((unsigned long)wl->aggr_buf, order);
4050 4499
4500err_wq:
4501 destroy_workqueue(wl->freezable_wq);
4502
4051err_hw: 4503err_hw:
4052 wl1271_debugfs_exit(wl); 4504 wl1271_debugfs_exit(wl);
4053 kfree(plat_dev); 4505 kfree(plat_dev);
@@ -4063,7 +4515,15 @@ EXPORT_SYMBOL_GPL(wl1271_alloc_hw);
4063 4515
4064int wl1271_free_hw(struct wl1271 *wl) 4516int wl1271_free_hw(struct wl1271 *wl)
4065{ 4517{
4518 /* Unblock any fwlog readers */
4519 mutex_lock(&wl->mutex);
4520 wl->fwlog_size = -1;
4521 wake_up_interruptible_all(&wl->fwlog_waitq);
4522 mutex_unlock(&wl->mutex);
4523
4524 device_remove_bin_file(&wl->plat_dev->dev, &fwlog_attr);
4066 platform_device_unregister(wl->plat_dev); 4525 platform_device_unregister(wl->plat_dev);
4526 free_page((unsigned long)wl->fwlog);
4067 dev_kfree_skb(wl->dummy_packet); 4527 dev_kfree_skb(wl->dummy_packet);
4068 free_pages((unsigned long)wl->aggr_buf, 4528 free_pages((unsigned long)wl->aggr_buf,
4069 get_order(WL1271_AGGR_BUFFER_SIZE)); 4529 get_order(WL1271_AGGR_BUFFER_SIZE));
@@ -4078,6 +4538,7 @@ int wl1271_free_hw(struct wl1271 *wl)
4078 4538
4079 kfree(wl->fw_status); 4539 kfree(wl->fw_status);
4080 kfree(wl->tx_res_if); 4540 kfree(wl->tx_res_if);
4541 destroy_workqueue(wl->freezable_wq);
4081 4542
4082 ieee80211_free_hw(wl->hw); 4543 ieee80211_free_hw(wl->hw);
4083 4544
@@ -4090,6 +4551,10 @@ EXPORT_SYMBOL_GPL(wl12xx_debug_level);
4090module_param_named(debug_level, wl12xx_debug_level, uint, S_IRUSR | S_IWUSR); 4551module_param_named(debug_level, wl12xx_debug_level, uint, S_IRUSR | S_IWUSR);
4091MODULE_PARM_DESC(debug_level, "wl12xx debugging level"); 4552MODULE_PARM_DESC(debug_level, "wl12xx debugging level");
4092 4553
4554module_param_named(fwlog, fwlog_param, charp, 0);
4555MODULE_PARM_DESC(keymap,
4556 "FW logger options: continuous, ondemand, dbgpins or disable");
4557
4093MODULE_LICENSE("GPL"); 4558MODULE_LICENSE("GPL");
4094MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>"); 4559MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
4095MODULE_AUTHOR("Juuso Oikarinen <juuso.oikarinen@nokia.com>"); 4560MODULE_AUTHOR("Juuso Oikarinen <juuso.oikarinen@nokia.com>");
diff --git a/drivers/net/wireless/wl12xx/ps.c b/drivers/net/wireless/wl12xx/ps.c
index b59b67711a17..3548377ab9c2 100644
--- a/drivers/net/wireless/wl12xx/ps.c
+++ b/drivers/net/wireless/wl12xx/ps.c
@@ -118,7 +118,7 @@ int wl1271_ps_elp_wakeup(struct wl1271 *wl)
118 &compl, msecs_to_jiffies(WL1271_WAKEUP_TIMEOUT)); 118 &compl, msecs_to_jiffies(WL1271_WAKEUP_TIMEOUT));
119 if (ret == 0) { 119 if (ret == 0) {
120 wl1271_error("ELP wakeup timeout!"); 120 wl1271_error("ELP wakeup timeout!");
121 ieee80211_queue_work(wl->hw, &wl->recovery_work); 121 wl12xx_queue_recovery_work(wl);
122 ret = -ETIMEDOUT; 122 ret = -ETIMEDOUT;
123 goto err; 123 goto err;
124 } else if (ret < 0) { 124 } else if (ret < 0) {
@@ -169,9 +169,11 @@ int wl1271_ps_set_mode(struct wl1271 *wl, enum wl1271_cmd_ps_mode mode,
169 wl1271_debug(DEBUG_PSM, "leaving psm"); 169 wl1271_debug(DEBUG_PSM, "leaving psm");
170 170
171 /* disable beacon early termination */ 171 /* disable beacon early termination */
172 ret = wl1271_acx_bet_enable(wl, false); 172 if (wl->band == IEEE80211_BAND_2GHZ) {
173 if (ret < 0) 173 ret = wl1271_acx_bet_enable(wl, false);
174 return ret; 174 if (ret < 0)
175 return ret;
176 }
175 177
176 /* disable beacon filtering */ 178 /* disable beacon filtering */
177 ret = wl1271_acx_beacon_filter_opt(wl, false); 179 ret = wl1271_acx_beacon_filter_opt(wl, false);
@@ -191,24 +193,27 @@ int wl1271_ps_set_mode(struct wl1271 *wl, enum wl1271_cmd_ps_mode mode,
191 193
192static void wl1271_ps_filter_frames(struct wl1271 *wl, u8 hlid) 194static void wl1271_ps_filter_frames(struct wl1271 *wl, u8 hlid)
193{ 195{
194 int i, filtered = 0; 196 int i;
195 struct sk_buff *skb; 197 struct sk_buff *skb;
196 struct ieee80211_tx_info *info; 198 struct ieee80211_tx_info *info;
197 unsigned long flags; 199 unsigned long flags;
200 int filtered[NUM_TX_QUEUES];
198 201
199 /* filter all frames currently the low level queus for this hlid */ 202 /* filter all frames currently the low level queus for this hlid */
200 for (i = 0; i < NUM_TX_QUEUES; i++) { 203 for (i = 0; i < NUM_TX_QUEUES; i++) {
204 filtered[i] = 0;
201 while ((skb = skb_dequeue(&wl->links[hlid].tx_queue[i]))) { 205 while ((skb = skb_dequeue(&wl->links[hlid].tx_queue[i]))) {
202 info = IEEE80211_SKB_CB(skb); 206 info = IEEE80211_SKB_CB(skb);
203 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 207 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
204 info->status.rates[0].idx = -1; 208 info->status.rates[0].idx = -1;
205 ieee80211_tx_status(wl->hw, skb); 209 ieee80211_tx_status_ni(wl->hw, skb);
206 filtered++; 210 filtered[i]++;
207 } 211 }
208 } 212 }
209 213
210 spin_lock_irqsave(&wl->wl_lock, flags); 214 spin_lock_irqsave(&wl->wl_lock, flags);
211 wl->tx_queue_count -= filtered; 215 for (i = 0; i < NUM_TX_QUEUES; i++)
216 wl->tx_queue_count[i] -= filtered[i];
212 spin_unlock_irqrestore(&wl->wl_lock, flags); 217 spin_unlock_irqrestore(&wl->wl_lock, flags);
213 218
214 wl1271_handle_tx_low_watermark(wl); 219 wl1271_handle_tx_low_watermark(wl);
diff --git a/drivers/net/wireless/wl12xx/rx.c b/drivers/net/wireless/wl12xx/rx.c
index 70091035e019..0450fb49dbb1 100644
--- a/drivers/net/wireless/wl12xx/rx.c
+++ b/drivers/net/wireless/wl12xx/rx.c
@@ -22,6 +22,7 @@
22 */ 22 */
23 23
24#include <linux/gfp.h> 24#include <linux/gfp.h>
25#include <linux/sched.h>
25 26
26#include "wl12xx.h" 27#include "wl12xx.h"
27#include "acx.h" 28#include "acx.h"
@@ -95,6 +96,7 @@ static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length)
95 struct ieee80211_hdr *hdr; 96 struct ieee80211_hdr *hdr;
96 u8 *buf; 97 u8 *buf;
97 u8 beacon = 0; 98 u8 beacon = 0;
99 u8 is_data = 0;
98 100
99 /* 101 /*
100 * In PLT mode we seem to get frames and mac80211 warns about them, 102 * In PLT mode we seem to get frames and mac80211 warns about them,
@@ -106,6 +108,13 @@ static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length)
106 /* the data read starts with the descriptor */ 108 /* the data read starts with the descriptor */
107 desc = (struct wl1271_rx_descriptor *) data; 109 desc = (struct wl1271_rx_descriptor *) data;
108 110
111 if (desc->packet_class == WL12XX_RX_CLASS_LOGGER) {
112 size_t len = length - sizeof(*desc);
113 wl12xx_copy_fwlog(wl, data + sizeof(*desc), len);
114 wake_up_interruptible(&wl->fwlog_waitq);
115 return 0;
116 }
117
109 switch (desc->status & WL1271_RX_DESC_STATUS_MASK) { 118 switch (desc->status & WL1271_RX_DESC_STATUS_MASK) {
110 /* discard corrupted packets */ 119 /* discard corrupted packets */
111 case WL1271_RX_DESC_DRIVER_RX_Q_FAIL: 120 case WL1271_RX_DESC_DRIVER_RX_Q_FAIL:
@@ -137,6 +146,8 @@ static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length)
137 hdr = (struct ieee80211_hdr *)skb->data; 146 hdr = (struct ieee80211_hdr *)skb->data;
138 if (ieee80211_is_beacon(hdr->frame_control)) 147 if (ieee80211_is_beacon(hdr->frame_control))
139 beacon = 1; 148 beacon = 1;
149 if (ieee80211_is_data_present(hdr->frame_control))
150 is_data = 1;
140 151
141 wl1271_rx_status(wl, desc, IEEE80211_SKB_RXCB(skb), beacon); 152 wl1271_rx_status(wl, desc, IEEE80211_SKB_RXCB(skb), beacon);
142 153
@@ -147,9 +158,9 @@ static int wl1271_rx_handle_data(struct wl1271 *wl, u8 *data, u32 length)
147 skb_trim(skb, skb->len - desc->pad_len); 158 skb_trim(skb, skb->len - desc->pad_len);
148 159
149 skb_queue_tail(&wl->deferred_rx_queue, skb); 160 skb_queue_tail(&wl->deferred_rx_queue, skb);
150 ieee80211_queue_work(wl->hw, &wl->netstack_work); 161 queue_work(wl->freezable_wq, &wl->netstack_work);
151 162
152 return 0; 163 return is_data;
153} 164}
154 165
155void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_common_status *status) 166void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_common_status *status)
@@ -162,6 +173,8 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_common_status *status)
162 u32 mem_block; 173 u32 mem_block;
163 u32 pkt_length; 174 u32 pkt_length;
164 u32 pkt_offset; 175 u32 pkt_offset;
176 bool is_ap = (wl->bss_type == BSS_TYPE_AP_BSS);
177 bool had_data = false;
165 178
166 while (drv_rx_counter != fw_rx_counter) { 179 while (drv_rx_counter != fw_rx_counter) {
167 buf_size = 0; 180 buf_size = 0;
@@ -214,9 +227,11 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_common_status *status)
214 * conditions, in that case the received frame will just 227 * conditions, in that case the received frame will just
215 * be dropped. 228 * be dropped.
216 */ 229 */
217 wl1271_rx_handle_data(wl, 230 if (wl1271_rx_handle_data(wl,
218 wl->aggr_buf + pkt_offset, 231 wl->aggr_buf + pkt_offset,
219 pkt_length); 232 pkt_length) == 1)
233 had_data = true;
234
220 wl->rx_counter++; 235 wl->rx_counter++;
221 drv_rx_counter++; 236 drv_rx_counter++;
222 drv_rx_counter &= NUM_RX_PKT_DESC_MOD_MASK; 237 drv_rx_counter &= NUM_RX_PKT_DESC_MOD_MASK;
@@ -230,6 +245,20 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_common_status *status)
230 */ 245 */
231 if (wl->quirks & WL12XX_QUIRK_END_OF_TRANSACTION) 246 if (wl->quirks & WL12XX_QUIRK_END_OF_TRANSACTION)
232 wl1271_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter); 247 wl1271_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter);
248
249 if (!is_ap && wl->conf.rx_streaming.interval && had_data &&
250 (wl->conf.rx_streaming.always ||
251 test_bit(WL1271_FLAG_SOFT_GEMINI, &wl->flags))) {
252 u32 timeout = wl->conf.rx_streaming.duration;
253
254 /* restart rx streaming */
255 if (!test_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags))
256 ieee80211_queue_work(wl->hw,
257 &wl->rx_streaming_enable_work);
258
259 mod_timer(&wl->rx_streaming_timer,
260 jiffies + msecs_to_jiffies(timeout));
261 }
233} 262}
234 263
235void wl1271_set_default_filters(struct wl1271 *wl) 264void wl1271_set_default_filters(struct wl1271 *wl)
diff --git a/drivers/net/wireless/wl12xx/rx.h b/drivers/net/wireless/wl12xx/rx.h
index 75fabf836491..c88e3fa1d603 100644
--- a/drivers/net/wireless/wl12xx/rx.h
+++ b/drivers/net/wireless/wl12xx/rx.h
@@ -97,6 +97,18 @@
97#define RX_BUF_SIZE_MASK 0xFFF00 97#define RX_BUF_SIZE_MASK 0xFFF00
98#define RX_BUF_SIZE_SHIFT_DIV 6 98#define RX_BUF_SIZE_SHIFT_DIV 6
99 99
100enum {
101 WL12XX_RX_CLASS_UNKNOWN,
102 WL12XX_RX_CLASS_MANAGEMENT,
103 WL12XX_RX_CLASS_DATA,
104 WL12XX_RX_CLASS_QOS_DATA,
105 WL12XX_RX_CLASS_BCN_PRBRSP,
106 WL12XX_RX_CLASS_EAPOL,
107 WL12XX_RX_CLASS_BA_EVENT,
108 WL12XX_RX_CLASS_AMSDU,
109 WL12XX_RX_CLASS_LOGGER,
110};
111
100struct wl1271_rx_descriptor { 112struct wl1271_rx_descriptor {
101 __le16 length; 113 __le16 length;
102 u8 status; 114 u8 status;
diff --git a/drivers/net/wireless/wl12xx/scan.c b/drivers/net/wireless/wl12xx/scan.c
index 56f76abc754d..edfe01c321ca 100644
--- a/drivers/net/wireless/wl12xx/scan.c
+++ b/drivers/net/wireless/wl12xx/scan.c
@@ -62,7 +62,7 @@ void wl1271_scan_complete_work(struct work_struct *work)
62 62
63 if (wl->scan.failed) { 63 if (wl->scan.failed) {
64 wl1271_info("Scan completed due to error."); 64 wl1271_info("Scan completed due to error.");
65 ieee80211_queue_work(wl->hw, &wl->recovery_work); 65 wl12xx_queue_recovery_work(wl);
66 } 66 }
67 67
68out: 68out:
@@ -321,12 +321,39 @@ int wl1271_scan(struct wl1271 *wl, const u8 *ssid, size_t ssid_len,
321 return 0; 321 return 0;
322} 322}
323 323
324int wl1271_scan_stop(struct wl1271 *wl)
325{
326 struct wl1271_cmd_header *cmd = NULL;
327 int ret = 0;
328
329 if (WARN_ON(wl->scan.state == WL1271_SCAN_STATE_IDLE))
330 return -EINVAL;
331
332 wl1271_debug(DEBUG_CMD, "cmd scan stop");
333
334 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
335 if (!cmd) {
336 ret = -ENOMEM;
337 goto out;
338 }
339
340 ret = wl1271_cmd_send(wl, CMD_STOP_SCAN, cmd,
341 sizeof(*cmd), 0);
342 if (ret < 0) {
343 wl1271_error("cmd stop_scan failed");
344 goto out;
345 }
346out:
347 kfree(cmd);
348 return ret;
349}
350
324static int 351static int
325wl1271_scan_get_sched_scan_channels(struct wl1271 *wl, 352wl1271_scan_get_sched_scan_channels(struct wl1271 *wl,
326 struct cfg80211_sched_scan_request *req, 353 struct cfg80211_sched_scan_request *req,
327 struct conn_scan_ch_params *channels, 354 struct conn_scan_ch_params *channels,
328 u32 band, bool radar, bool passive, 355 u32 band, bool radar, bool passive,
329 int start) 356 int start, int max_channels)
330{ 357{
331 struct conf_sched_scan_settings *c = &wl->conf.sched_scan; 358 struct conf_sched_scan_settings *c = &wl->conf.sched_scan;
332 int i, j; 359 int i, j;
@@ -334,7 +361,7 @@ wl1271_scan_get_sched_scan_channels(struct wl1271 *wl,
334 bool force_passive = !req->n_ssids; 361 bool force_passive = !req->n_ssids;
335 362
336 for (i = 0, j = start; 363 for (i = 0, j = start;
337 i < req->n_channels && j < MAX_CHANNELS_ALL_BANDS; 364 i < req->n_channels && j < max_channels;
338 i++) { 365 i++) {
339 flags = req->channels[i]->flags; 366 flags = req->channels[i]->flags;
340 367
@@ -380,46 +407,42 @@ wl1271_scan_get_sched_scan_channels(struct wl1271 *wl,
380 return j - start; 407 return j - start;
381} 408}
382 409
383static int 410static bool
384wl1271_scan_sched_scan_channels(struct wl1271 *wl, 411wl1271_scan_sched_scan_channels(struct wl1271 *wl,
385 struct cfg80211_sched_scan_request *req, 412 struct cfg80211_sched_scan_request *req,
386 struct wl1271_cmd_sched_scan_config *cfg) 413 struct wl1271_cmd_sched_scan_config *cfg)
387{ 414{
388 int idx = 0;
389
390 cfg->passive[0] = 415 cfg->passive[0] =
391 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels, 416 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels_2,
392 IEEE80211_BAND_2GHZ, 417 IEEE80211_BAND_2GHZ,
393 false, true, idx); 418 false, true, 0,
394 idx += cfg->passive[0]; 419 MAX_CHANNELS_2GHZ);
395
396 cfg->active[0] = 420 cfg->active[0] =
397 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels, 421 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels_2,
398 IEEE80211_BAND_2GHZ, 422 IEEE80211_BAND_2GHZ,
399 false, false, idx); 423 false, false,
400 /* 424 cfg->passive[0],
401 * 5GHz channels always start at position 14, not immediately 425 MAX_CHANNELS_2GHZ);
402 * after the last 2.4GHz channel
403 */
404 idx = 14;
405
406 cfg->passive[1] = 426 cfg->passive[1] =
407 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels, 427 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels_5,
408 IEEE80211_BAND_5GHZ, 428 IEEE80211_BAND_5GHZ,
409 false, true, idx); 429 false, true, 0,
410 idx += cfg->passive[1]; 430 MAX_CHANNELS_5GHZ);
411
412 cfg->dfs = 431 cfg->dfs =
413 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels, 432 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels_5,
414 IEEE80211_BAND_5GHZ, 433 IEEE80211_BAND_5GHZ,
415 true, true, idx); 434 true, true,
416 idx += cfg->dfs; 435 cfg->passive[1],
417 436 MAX_CHANNELS_5GHZ);
418 cfg->active[1] = 437 cfg->active[1] =
419 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels, 438 wl1271_scan_get_sched_scan_channels(wl, req, cfg->channels_5,
420 IEEE80211_BAND_5GHZ, 439 IEEE80211_BAND_5GHZ,
421 false, false, idx); 440 false, false,
422 idx += cfg->active[1]; 441 cfg->passive[1] + cfg->dfs,
442 MAX_CHANNELS_5GHZ);
443 /* 802.11j channels are not supported yet */
444 cfg->passive[2] = 0;
445 cfg->active[2] = 0;
423 446
424 wl1271_debug(DEBUG_SCAN, " 2.4GHz: active %d passive %d", 447 wl1271_debug(DEBUG_SCAN, " 2.4GHz: active %d passive %d",
425 cfg->active[0], cfg->passive[0]); 448 cfg->active[0], cfg->passive[0]);
@@ -427,7 +450,9 @@ wl1271_scan_sched_scan_channels(struct wl1271 *wl,
427 cfg->active[1], cfg->passive[1]); 450 cfg->active[1], cfg->passive[1]);
428 wl1271_debug(DEBUG_SCAN, " DFS: %d", cfg->dfs); 451 wl1271_debug(DEBUG_SCAN, " DFS: %d", cfg->dfs);
429 452
430 return idx; 453 return cfg->passive[0] || cfg->active[0] ||
454 cfg->passive[1] || cfg->active[1] || cfg->dfs ||
455 cfg->passive[2] || cfg->active[2];
431} 456}
432 457
433int wl1271_scan_sched_scan_config(struct wl1271 *wl, 458int wl1271_scan_sched_scan_config(struct wl1271 *wl,
@@ -436,7 +461,7 @@ int wl1271_scan_sched_scan_config(struct wl1271 *wl,
436{ 461{
437 struct wl1271_cmd_sched_scan_config *cfg = NULL; 462 struct wl1271_cmd_sched_scan_config *cfg = NULL;
438 struct conf_sched_scan_settings *c = &wl->conf.sched_scan; 463 struct conf_sched_scan_settings *c = &wl->conf.sched_scan;
439 int i, total_channels, ret; 464 int i, ret;
440 bool force_passive = !req->n_ssids; 465 bool force_passive = !req->n_ssids;
441 466
442 wl1271_debug(DEBUG_CMD, "cmd sched_scan scan config"); 467 wl1271_debug(DEBUG_CMD, "cmd sched_scan scan config");
@@ -471,8 +496,7 @@ int wl1271_scan_sched_scan_config(struct wl1271 *wl,
471 cfg->ssid_len = 0; 496 cfg->ssid_len = 0;
472 } 497 }
473 498
474 total_channels = wl1271_scan_sched_scan_channels(wl, req, cfg); 499 if (!wl1271_scan_sched_scan_channels(wl, req, cfg)) {
475 if (total_channels == 0) {
476 wl1271_error("scan channel list is empty"); 500 wl1271_error("scan channel list is empty");
477 ret = -EINVAL; 501 ret = -EINVAL;
478 goto out; 502 goto out;
diff --git a/drivers/net/wireless/wl12xx/scan.h b/drivers/net/wireless/wl12xx/scan.h
index a0b6c5d67b07..d882e4da71b7 100644
--- a/drivers/net/wireless/wl12xx/scan.h
+++ b/drivers/net/wireless/wl12xx/scan.h
@@ -28,6 +28,7 @@
28 28
29int wl1271_scan(struct wl1271 *wl, const u8 *ssid, size_t ssid_len, 29int wl1271_scan(struct wl1271 *wl, const u8 *ssid, size_t ssid_len,
30 struct cfg80211_scan_request *req); 30 struct cfg80211_scan_request *req);
31int wl1271_scan_stop(struct wl1271 *wl);
31int wl1271_scan_build_probe_req(struct wl1271 *wl, 32int wl1271_scan_build_probe_req(struct wl1271 *wl,
32 const u8 *ssid, size_t ssid_len, 33 const u8 *ssid, size_t ssid_len,
33 const u8 *ie, size_t ie_len, u8 band); 34 const u8 *ie, size_t ie_len, u8 band);
@@ -112,19 +113,14 @@ struct wl1271_cmd_trigger_scan_to {
112 __le32 timeout; 113 __le32 timeout;
113} __packed; 114} __packed;
114 115
115#define MAX_CHANNELS_ALL_BANDS 41 116#define MAX_CHANNELS_2GHZ 14
117#define MAX_CHANNELS_5GHZ 23
118#define MAX_CHANNELS_4GHZ 4
119
116#define SCAN_MAX_CYCLE_INTERVALS 16 120#define SCAN_MAX_CYCLE_INTERVALS 16
117#define SCAN_MAX_BANDS 3 121#define SCAN_MAX_BANDS 3
118 122
119enum { 123enum {
120 SCAN_CHANNEL_TYPE_2GHZ_PASSIVE,
121 SCAN_CHANNEL_TYPE_2GHZ_ACTIVE,
122 SCAN_CHANNEL_TYPE_5GHZ_PASSIVE,
123 SCAN_CHANNEL_TYPE_5GHZ_ACTIVE,
124 SCAN_CHANNEL_TYPE_5GHZ_DFS,
125};
126
127enum {
128 SCAN_SSID_FILTER_ANY = 0, 124 SCAN_SSID_FILTER_ANY = 0,
129 SCAN_SSID_FILTER_SPECIFIC = 1, 125 SCAN_SSID_FILTER_SPECIFIC = 1,
130 SCAN_SSID_FILTER_LIST = 2, 126 SCAN_SSID_FILTER_LIST = 2,
@@ -182,7 +178,9 @@ struct wl1271_cmd_sched_scan_config {
182 178
183 u8 padding[3]; 179 u8 padding[3];
184 180
185 struct conn_scan_ch_params channels[MAX_CHANNELS_ALL_BANDS]; 181 struct conn_scan_ch_params channels_2[MAX_CHANNELS_2GHZ];
182 struct conn_scan_ch_params channels_5[MAX_CHANNELS_5GHZ];
183 struct conn_scan_ch_params channels_4[MAX_CHANNELS_4GHZ];
186} __packed; 184} __packed;
187 185
188 186
diff --git a/drivers/net/wireless/wl12xx/sdio.c b/drivers/net/wireless/wl12xx/sdio.c
index 536e5065454b..5cf18c2c23f0 100644
--- a/drivers/net/wireless/wl12xx/sdio.c
+++ b/drivers/net/wireless/wl12xx/sdio.c
@@ -23,7 +23,6 @@
23 23
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/module.h> 25#include <linux/module.h>
26#include <linux/crc7.h>
27#include <linux/vmalloc.h> 26#include <linux/vmalloc.h>
28#include <linux/mmc/sdio_func.h> 27#include <linux/mmc/sdio_func.h>
29#include <linux/mmc/sdio_ids.h> 28#include <linux/mmc/sdio_ids.h>
@@ -45,7 +44,7 @@
45#define SDIO_DEVICE_ID_TI_WL1271 0x4076 44#define SDIO_DEVICE_ID_TI_WL1271 0x4076
46#endif 45#endif
47 46
48static const struct sdio_device_id wl1271_devices[] = { 47static const struct sdio_device_id wl1271_devices[] __devinitconst = {
49 { SDIO_DEVICE(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271) }, 48 { SDIO_DEVICE(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271) },
50 {} 49 {}
51}; 50};
@@ -107,14 +106,6 @@ static void wl1271_sdio_enable_interrupts(struct wl1271 *wl)
107 enable_irq(wl->irq); 106 enable_irq(wl->irq);
108} 107}
109 108
110static void wl1271_sdio_reset(struct wl1271 *wl)
111{
112}
113
114static void wl1271_sdio_init(struct wl1271 *wl)
115{
116}
117
118static void wl1271_sdio_raw_read(struct wl1271 *wl, int addr, void *buf, 109static void wl1271_sdio_raw_read(struct wl1271 *wl, int addr, void *buf,
119 size_t len, bool fixed) 110 size_t len, bool fixed)
120{ 111{
@@ -170,15 +161,17 @@ static int wl1271_sdio_power_on(struct wl1271 *wl)
170 struct sdio_func *func = wl_to_func(wl); 161 struct sdio_func *func = wl_to_func(wl);
171 int ret; 162 int ret;
172 163
173 /* Make sure the card will not be powered off by runtime PM */ 164 /* If enabled, tell runtime PM not to power off the card */
174 ret = pm_runtime_get_sync(&func->dev); 165 if (pm_runtime_enabled(&func->dev)) {
175 if (ret < 0) 166 ret = pm_runtime_get_sync(&func->dev);
176 goto out; 167 if (ret)
177 168 goto out;
178 /* Runtime PM might be disabled, so power up the card manually */ 169 } else {
179 ret = mmc_power_restore_host(func->card->host); 170 /* Runtime PM is disabled: power up the card manually */
180 if (ret < 0) 171 ret = mmc_power_restore_host(func->card->host);
181 goto out; 172 if (ret < 0)
173 goto out;
174 }
182 175
183 sdio_claim_host(func); 176 sdio_claim_host(func);
184 sdio_enable_func(func); 177 sdio_enable_func(func);
@@ -195,13 +188,16 @@ static int wl1271_sdio_power_off(struct wl1271 *wl)
195 sdio_disable_func(func); 188 sdio_disable_func(func);
196 sdio_release_host(func); 189 sdio_release_host(func);
197 190
198 /* Runtime PM might be disabled, so power off the card manually */ 191 /* Power off the card manually, even if runtime PM is enabled. */
199 ret = mmc_power_save_host(func->card->host); 192 ret = mmc_power_save_host(func->card->host);
200 if (ret < 0) 193 if (ret < 0)
201 return ret; 194 return ret;
202 195
203 /* Let runtime PM know the card is powered off */ 196 /* If enabled, let runtime PM know the card is powered off */
204 return pm_runtime_put_sync(&func->dev); 197 if (pm_runtime_enabled(&func->dev))
198 ret = pm_runtime_put_sync(&func->dev);
199
200 return ret;
205} 201}
206 202
207static int wl1271_sdio_set_power(struct wl1271 *wl, bool enable) 203static int wl1271_sdio_set_power(struct wl1271 *wl, bool enable)
@@ -215,8 +211,6 @@ static int wl1271_sdio_set_power(struct wl1271 *wl, bool enable)
215static struct wl1271_if_operations sdio_ops = { 211static struct wl1271_if_operations sdio_ops = {
216 .read = wl1271_sdio_raw_read, 212 .read = wl1271_sdio_raw_read,
217 .write = wl1271_sdio_raw_write, 213 .write = wl1271_sdio_raw_write,
218 .reset = wl1271_sdio_reset,
219 .init = wl1271_sdio_init,
220 .power = wl1271_sdio_set_power, 214 .power = wl1271_sdio_set_power,
221 .dev = wl1271_sdio_wl_to_dev, 215 .dev = wl1271_sdio_wl_to_dev,
222 .enable_irq = wl1271_sdio_enable_interrupts, 216 .enable_irq = wl1271_sdio_enable_interrupts,
@@ -278,17 +272,19 @@ static int __devinit wl1271_probe(struct sdio_func *func,
278 goto out_free; 272 goto out_free;
279 } 273 }
280 274
281 enable_irq_wake(wl->irq); 275 ret = enable_irq_wake(wl->irq);
282 device_init_wakeup(wl1271_sdio_wl_to_dev(wl), 1); 276 if (!ret) {
277 wl->irq_wake_enabled = true;
278 device_init_wakeup(wl1271_sdio_wl_to_dev(wl), 1);
283 279
284 disable_irq(wl->irq); 280 /* if sdio can keep power while host is suspended, enable wow */
285 281 mmcflags = sdio_get_host_pm_caps(func);
286 /* if sdio can keep power while host is suspended, enable wow */ 282 wl1271_debug(DEBUG_SDIO, "sdio PM caps = 0x%x", mmcflags);
287 mmcflags = sdio_get_host_pm_caps(func);
288 wl1271_debug(DEBUG_SDIO, "sdio PM caps = 0x%x", mmcflags);
289 283
290 if (mmcflags & MMC_PM_KEEP_POWER) 284 if (mmcflags & MMC_PM_KEEP_POWER)
291 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_ANY; 285 hw->wiphy->wowlan.flags = WIPHY_WOWLAN_ANY;
286 }
287 disable_irq(wl->irq);
292 288
293 ret = wl1271_init_ieee80211(wl); 289 ret = wl1271_init_ieee80211(wl);
294 if (ret) 290 if (ret)
@@ -303,8 +299,6 @@ static int __devinit wl1271_probe(struct sdio_func *func,
303 /* Tell PM core that we don't need the card to be powered now */ 299 /* Tell PM core that we don't need the card to be powered now */
304 pm_runtime_put_noidle(&func->dev); 300 pm_runtime_put_noidle(&func->dev);
305 301
306 wl1271_notice("initialized");
307
308 return 0; 302 return 0;
309 303
310 out_irq: 304 out_irq:
@@ -324,8 +318,10 @@ static void __devexit wl1271_remove(struct sdio_func *func)
324 pm_runtime_get_noresume(&func->dev); 318 pm_runtime_get_noresume(&func->dev);
325 319
326 wl1271_unregister_hw(wl); 320 wl1271_unregister_hw(wl);
327 device_init_wakeup(wl1271_sdio_wl_to_dev(wl), 0); 321 if (wl->irq_wake_enabled) {
328 disable_irq_wake(wl->irq); 322 device_init_wakeup(wl1271_sdio_wl_to_dev(wl), 0);
323 disable_irq_wake(wl->irq);
324 }
329 free_irq(wl->irq, wl); 325 free_irq(wl->irq, wl);
330 wl1271_free_hw(wl); 326 wl1271_free_hw(wl);
331} 327}
@@ -402,23 +398,12 @@ static struct sdio_driver wl1271_sdio_driver = {
402 398
403static int __init wl1271_init(void) 399static int __init wl1271_init(void)
404{ 400{
405 int ret; 401 return sdio_register_driver(&wl1271_sdio_driver);
406
407 ret = sdio_register_driver(&wl1271_sdio_driver);
408 if (ret < 0) {
409 wl1271_error("failed to register sdio driver: %d", ret);
410 goto out;
411 }
412
413out:
414 return ret;
415} 402}
416 403
417static void __exit wl1271_exit(void) 404static void __exit wl1271_exit(void)
418{ 405{
419 sdio_unregister_driver(&wl1271_sdio_driver); 406 sdio_unregister_driver(&wl1271_sdio_driver);
420
421 wl1271_notice("unloaded");
422} 407}
423 408
424module_init(wl1271_init); 409module_init(wl1271_init);
diff --git a/drivers/net/wireless/wl12xx/spi.c b/drivers/net/wireless/wl12xx/spi.c
index 51662bb68019..e0b3736d7e19 100644
--- a/drivers/net/wireless/wl12xx/spi.c
+++ b/drivers/net/wireless/wl12xx/spi.c
@@ -21,6 +21,7 @@
21 * 21 *
22 */ 22 */
23 23
24#include <linux/interrupt.h>
24#include <linux/irq.h> 25#include <linux/irq.h>
25#include <linux/module.h> 26#include <linux/module.h>
26#include <linux/crc7.h> 27#include <linux/crc7.h>
@@ -435,8 +436,6 @@ static int __devinit wl1271_probe(struct spi_device *spi)
435 if (ret) 436 if (ret)
436 goto out_irq; 437 goto out_irq;
437 438
438 wl1271_notice("initialized");
439
440 return 0; 439 return 0;
441 440
442 out_irq: 441 out_irq:
@@ -473,23 +472,12 @@ static struct spi_driver wl1271_spi_driver = {
473 472
474static int __init wl1271_init(void) 473static int __init wl1271_init(void)
475{ 474{
476 int ret; 475 return spi_register_driver(&wl1271_spi_driver);
477
478 ret = spi_register_driver(&wl1271_spi_driver);
479 if (ret < 0) {
480 wl1271_error("failed to register spi driver: %d", ret);
481 goto out;
482 }
483
484out:
485 return ret;
486} 476}
487 477
488static void __exit wl1271_exit(void) 478static void __exit wl1271_exit(void)
489{ 479{
490 spi_unregister_driver(&wl1271_spi_driver); 480 spi_unregister_driver(&wl1271_spi_driver);
491
492 wl1271_notice("unloaded");
493} 481}
494 482
495module_init(wl1271_init); 483module_init(wl1271_init);
diff --git a/drivers/net/wireless/wl12xx/testmode.c b/drivers/net/wireless/wl12xx/testmode.c
index da351d7cd1f2..5d5e1ef87206 100644
--- a/drivers/net/wireless/wl12xx/testmode.c
+++ b/drivers/net/wireless/wl12xx/testmode.c
@@ -260,7 +260,7 @@ static int wl1271_tm_cmd_recover(struct wl1271 *wl, struct nlattr *tb[])
260{ 260{
261 wl1271_debug(DEBUG_TESTMODE, "testmode cmd recover"); 261 wl1271_debug(DEBUG_TESTMODE, "testmode cmd recover");
262 262
263 ieee80211_queue_work(wl->hw, &wl->recovery_work); 263 wl12xx_queue_recovery_work(wl);
264 264
265 return 0; 265 return 0;
266} 266}
diff --git a/drivers/net/wireless/wl12xx/tx.c b/drivers/net/wireless/wl12xx/tx.c
index ca3ab1c1acef..48fde96ce0d4 100644
--- a/drivers/net/wireless/wl12xx/tx.c
+++ b/drivers/net/wireless/wl12xx/tx.c
@@ -168,7 +168,7 @@ static int wl1271_tx_allocate(struct wl1271 *wl, struct sk_buff *skb, u32 extra,
168 u32 total_len = skb->len + sizeof(struct wl1271_tx_hw_descr) + extra; 168 u32 total_len = skb->len + sizeof(struct wl1271_tx_hw_descr) + extra;
169 u32 len; 169 u32 len;
170 u32 total_blocks; 170 u32 total_blocks;
171 int id, ret = -EBUSY; 171 int id, ret = -EBUSY, ac;
172 u32 spare_blocks; 172 u32 spare_blocks;
173 173
174 if (unlikely(wl->quirks & WL12XX_QUIRK_USE_2_SPARE_BLOCKS)) 174 if (unlikely(wl->quirks & WL12XX_QUIRK_USE_2_SPARE_BLOCKS))
@@ -206,7 +206,9 @@ static int wl1271_tx_allocate(struct wl1271 *wl, struct sk_buff *skb, u32 extra,
206 desc->id = id; 206 desc->id = id;
207 207
208 wl->tx_blocks_available -= total_blocks; 208 wl->tx_blocks_available -= total_blocks;
209 wl->tx_allocated_blocks += total_blocks; 209
210 ac = wl1271_tx_get_queue(skb_get_queue_mapping(skb));
211 wl->tx_allocated_blocks[ac] += total_blocks;
210 212
211 if (wl->bss_type == BSS_TYPE_AP_BSS) 213 if (wl->bss_type == BSS_TYPE_AP_BSS)
212 wl->links[hlid].allocated_blks += total_blocks; 214 wl->links[hlid].allocated_blks += total_blocks;
@@ -383,6 +385,8 @@ static int wl1271_prepare_tx_frame(struct wl1271 *wl, struct sk_buff *skb,
383 if (ret < 0) 385 if (ret < 0)
384 return ret; 386 return ret;
385 387
388 wl1271_tx_fill_hdr(wl, skb, extra, info, hlid);
389
386 if (wl->bss_type == BSS_TYPE_AP_BSS) { 390 if (wl->bss_type == BSS_TYPE_AP_BSS) {
387 wl1271_tx_ap_update_inconnection_sta(wl, skb); 391 wl1271_tx_ap_update_inconnection_sta(wl, skb);
388 wl1271_tx_regulate_link(wl, hlid); 392 wl1271_tx_regulate_link(wl, hlid);
@@ -390,8 +394,6 @@ static int wl1271_prepare_tx_frame(struct wl1271 *wl, struct sk_buff *skb,
390 wl1271_tx_update_filters(wl, skb); 394 wl1271_tx_update_filters(wl, skb);
391 } 395 }
392 396
393 wl1271_tx_fill_hdr(wl, skb, extra, info, hlid);
394
395 /* 397 /*
396 * The length of each packet is stored in terms of 398 * The length of each packet is stored in terms of
397 * words. Thus, we must pad the skb data to make sure its 399 * words. Thus, we must pad the skb data to make sure its
@@ -442,37 +444,62 @@ u32 wl1271_tx_enabled_rates_get(struct wl1271 *wl, u32 rate_set)
442void wl1271_handle_tx_low_watermark(struct wl1271 *wl) 444void wl1271_handle_tx_low_watermark(struct wl1271 *wl)
443{ 445{
444 unsigned long flags; 446 unsigned long flags;
447 int i;
445 448
446 if (test_bit(WL1271_FLAG_TX_QUEUE_STOPPED, &wl->flags) && 449 for (i = 0; i < NUM_TX_QUEUES; i++) {
447 wl->tx_queue_count <= WL1271_TX_QUEUE_LOW_WATERMARK) { 450 if (test_bit(i, &wl->stopped_queues_map) &&
448 /* firmware buffer has space, restart queues */ 451 wl->tx_queue_count[i] <= WL1271_TX_QUEUE_LOW_WATERMARK) {
449 spin_lock_irqsave(&wl->wl_lock, flags); 452 /* firmware buffer has space, restart queues */
450 ieee80211_wake_queues(wl->hw); 453 spin_lock_irqsave(&wl->wl_lock, flags);
451 clear_bit(WL1271_FLAG_TX_QUEUE_STOPPED, &wl->flags); 454 ieee80211_wake_queue(wl->hw,
452 spin_unlock_irqrestore(&wl->wl_lock, flags); 455 wl1271_tx_get_mac80211_queue(i));
456 clear_bit(i, &wl->stopped_queues_map);
457 spin_unlock_irqrestore(&wl->wl_lock, flags);
458 }
453 } 459 }
454} 460}
455 461
462static struct sk_buff_head *wl1271_select_queue(struct wl1271 *wl,
463 struct sk_buff_head *queues)
464{
465 int i, q = -1;
466 u32 min_blks = 0xffffffff;
467
468 /*
469 * Find a non-empty ac where:
470 * 1. There are packets to transmit
471 * 2. The FW has the least allocated blocks
472 */
473 for (i = 0; i < NUM_TX_QUEUES; i++)
474 if (!skb_queue_empty(&queues[i]) &&
475 (wl->tx_allocated_blocks[i] < min_blks)) {
476 q = i;
477 min_blks = wl->tx_allocated_blocks[q];
478 }
479
480 if (q == -1)
481 return NULL;
482
483 return &queues[q];
484}
485
456static struct sk_buff *wl1271_sta_skb_dequeue(struct wl1271 *wl) 486static struct sk_buff *wl1271_sta_skb_dequeue(struct wl1271 *wl)
457{ 487{
458 struct sk_buff *skb = NULL; 488 struct sk_buff *skb = NULL;
459 unsigned long flags; 489 unsigned long flags;
490 struct sk_buff_head *queue;
460 491
461 skb = skb_dequeue(&wl->tx_queue[CONF_TX_AC_VO]); 492 queue = wl1271_select_queue(wl, wl->tx_queue);
462 if (skb) 493 if (!queue)
463 goto out;
464 skb = skb_dequeue(&wl->tx_queue[CONF_TX_AC_VI]);
465 if (skb)
466 goto out;
467 skb = skb_dequeue(&wl->tx_queue[CONF_TX_AC_BE]);
468 if (skb)
469 goto out; 494 goto out;
470 skb = skb_dequeue(&wl->tx_queue[CONF_TX_AC_BK]); 495
496 skb = skb_dequeue(queue);
471 497
472out: 498out:
473 if (skb) { 499 if (skb) {
500 int q = wl1271_tx_get_queue(skb_get_queue_mapping(skb));
474 spin_lock_irqsave(&wl->wl_lock, flags); 501 spin_lock_irqsave(&wl->wl_lock, flags);
475 wl->tx_queue_count--; 502 wl->tx_queue_count[q]--;
476 spin_unlock_irqrestore(&wl->wl_lock, flags); 503 spin_unlock_irqrestore(&wl->wl_lock, flags);
477 } 504 }
478 505
@@ -484,6 +511,7 @@ static struct sk_buff *wl1271_ap_skb_dequeue(struct wl1271 *wl)
484 struct sk_buff *skb = NULL; 511 struct sk_buff *skb = NULL;
485 unsigned long flags; 512 unsigned long flags;
486 int i, h, start_hlid; 513 int i, h, start_hlid;
514 struct sk_buff_head *queue;
487 515
488 /* start from the link after the last one */ 516 /* start from the link after the last one */
489 start_hlid = (wl->last_tx_hlid + 1) % AP_MAX_LINKS; 517 start_hlid = (wl->last_tx_hlid + 1) % AP_MAX_LINKS;
@@ -492,25 +520,25 @@ static struct sk_buff *wl1271_ap_skb_dequeue(struct wl1271 *wl)
492 for (i = 0; i < AP_MAX_LINKS; i++) { 520 for (i = 0; i < AP_MAX_LINKS; i++) {
493 h = (start_hlid + i) % AP_MAX_LINKS; 521 h = (start_hlid + i) % AP_MAX_LINKS;
494 522
495 skb = skb_dequeue(&wl->links[h].tx_queue[CONF_TX_AC_VO]); 523 /* only consider connected stations */
496 if (skb) 524 if (h >= WL1271_AP_STA_HLID_START &&
497 goto out; 525 !test_bit(h - WL1271_AP_STA_HLID_START, wl->ap_hlid_map))
498 skb = skb_dequeue(&wl->links[h].tx_queue[CONF_TX_AC_VI]); 526 continue;
499 if (skb) 527
500 goto out; 528 queue = wl1271_select_queue(wl, wl->links[h].tx_queue);
501 skb = skb_dequeue(&wl->links[h].tx_queue[CONF_TX_AC_BE]); 529 if (!queue)
502 if (skb) 530 continue;
503 goto out; 531
504 skb = skb_dequeue(&wl->links[h].tx_queue[CONF_TX_AC_BK]); 532 skb = skb_dequeue(queue);
505 if (skb) 533 if (skb)
506 goto out; 534 break;
507 } 535 }
508 536
509out:
510 if (skb) { 537 if (skb) {
538 int q = wl1271_tx_get_queue(skb_get_queue_mapping(skb));
511 wl->last_tx_hlid = h; 539 wl->last_tx_hlid = h;
512 spin_lock_irqsave(&wl->wl_lock, flags); 540 spin_lock_irqsave(&wl->wl_lock, flags);
513 wl->tx_queue_count--; 541 wl->tx_queue_count[q]--;
514 spin_unlock_irqrestore(&wl->wl_lock, flags); 542 spin_unlock_irqrestore(&wl->wl_lock, flags);
515 } else { 543 } else {
516 wl->last_tx_hlid = 0; 544 wl->last_tx_hlid = 0;
@@ -531,9 +559,12 @@ static struct sk_buff *wl1271_skb_dequeue(struct wl1271 *wl)
531 559
532 if (!skb && 560 if (!skb &&
533 test_and_clear_bit(WL1271_FLAG_DUMMY_PACKET_PENDING, &wl->flags)) { 561 test_and_clear_bit(WL1271_FLAG_DUMMY_PACKET_PENDING, &wl->flags)) {
562 int q;
563
534 skb = wl->dummy_packet; 564 skb = wl->dummy_packet;
565 q = wl1271_tx_get_queue(skb_get_queue_mapping(skb));
535 spin_lock_irqsave(&wl->wl_lock, flags); 566 spin_lock_irqsave(&wl->wl_lock, flags);
536 wl->tx_queue_count--; 567 wl->tx_queue_count[q]--;
537 spin_unlock_irqrestore(&wl->wl_lock, flags); 568 spin_unlock_irqrestore(&wl->wl_lock, flags);
538 } 569 }
539 570
@@ -558,21 +589,33 @@ static void wl1271_skb_queue_head(struct wl1271 *wl, struct sk_buff *skb)
558 } 589 }
559 590
560 spin_lock_irqsave(&wl->wl_lock, flags); 591 spin_lock_irqsave(&wl->wl_lock, flags);
561 wl->tx_queue_count++; 592 wl->tx_queue_count[q]++;
562 spin_unlock_irqrestore(&wl->wl_lock, flags); 593 spin_unlock_irqrestore(&wl->wl_lock, flags);
563} 594}
564 595
596static bool wl1271_tx_is_data_present(struct sk_buff *skb)
597{
598 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
599
600 return ieee80211_is_data_present(hdr->frame_control);
601}
602
565void wl1271_tx_work_locked(struct wl1271 *wl) 603void wl1271_tx_work_locked(struct wl1271 *wl)
566{ 604{
567 struct sk_buff *skb; 605 struct sk_buff *skb;
568 u32 buf_offset = 0; 606 u32 buf_offset = 0;
569 bool sent_packets = false; 607 bool sent_packets = false;
608 bool had_data = false;
609 bool is_ap = (wl->bss_type == BSS_TYPE_AP_BSS);
570 int ret; 610 int ret;
571 611
572 if (unlikely(wl->state == WL1271_STATE_OFF)) 612 if (unlikely(wl->state == WL1271_STATE_OFF))
573 return; 613 return;
574 614
575 while ((skb = wl1271_skb_dequeue(wl))) { 615 while ((skb = wl1271_skb_dequeue(wl))) {
616 if (wl1271_tx_is_data_present(skb))
617 had_data = true;
618
576 ret = wl1271_prepare_tx_frame(wl, skb, buf_offset); 619 ret = wl1271_prepare_tx_frame(wl, skb, buf_offset);
577 if (ret == -EAGAIN) { 620 if (ret == -EAGAIN) {
578 /* 621 /*
@@ -619,6 +662,19 @@ out_ack:
619 662
620 wl1271_handle_tx_low_watermark(wl); 663 wl1271_handle_tx_low_watermark(wl);
621 } 664 }
665 if (!is_ap && wl->conf.rx_streaming.interval && had_data &&
666 (wl->conf.rx_streaming.always ||
667 test_bit(WL1271_FLAG_SOFT_GEMINI, &wl->flags))) {
668 u32 timeout = wl->conf.rx_streaming.duration;
669
670 /* enable rx streaming */
671 if (!test_bit(WL1271_FLAG_RX_STREAMING_STARTED, &wl->flags))
672 ieee80211_queue_work(wl->hw,
673 &wl->rx_streaming_enable_work);
674
675 mod_timer(&wl->rx_streaming_timer,
676 jiffies + msecs_to_jiffies(timeout));
677 }
622} 678}
623 679
624void wl1271_tx_work(struct work_struct *work) 680void wl1271_tx_work(struct work_struct *work)
@@ -679,10 +735,24 @@ static void wl1271_tx_complete_packet(struct wl1271 *wl,
679 735
680 wl->stats.retry_count += result->ack_failures; 736 wl->stats.retry_count += result->ack_failures;
681 737
682 /* update security sequence number */ 738 /*
683 wl->tx_security_seq += (result->lsb_security_sequence_number - 739 * update sequence number only when relevant, i.e. only in
684 wl->tx_security_last_seq); 740 * sessions of TKIP, AES and GEM (not in open or WEP sessions)
685 wl->tx_security_last_seq = result->lsb_security_sequence_number; 741 */
742 if (info->control.hw_key &&
743 (info->control.hw_key->cipher == WLAN_CIPHER_SUITE_TKIP ||
744 info->control.hw_key->cipher == WLAN_CIPHER_SUITE_CCMP ||
745 info->control.hw_key->cipher == WL1271_CIPHER_SUITE_GEM)) {
746 u8 fw_lsb = result->tx_security_sequence_number_lsb;
747 u8 cur_lsb = wl->tx_security_last_seq_lsb;
748
749 /*
750 * update security sequence number, taking care of potential
751 * wrap-around
752 */
753 wl->tx_security_seq += (fw_lsb - cur_lsb + 256) % 256;
754 wl->tx_security_last_seq_lsb = fw_lsb;
755 }
686 756
687 /* remove private header from packet */ 757 /* remove private header from packet */
688 skb_pull(skb, sizeof(struct wl1271_tx_hw_descr)); 758 skb_pull(skb, sizeof(struct wl1271_tx_hw_descr));
@@ -702,7 +772,7 @@ static void wl1271_tx_complete_packet(struct wl1271 *wl,
702 772
703 /* return the packet to the stack */ 773 /* return the packet to the stack */
704 skb_queue_tail(&wl->deferred_tx_queue, skb); 774 skb_queue_tail(&wl->deferred_tx_queue, skb);
705 ieee80211_queue_work(wl->hw, &wl->netstack_work); 775 queue_work(wl->freezable_wq, &wl->netstack_work);
706 wl1271_free_tx_id(wl, result->id); 776 wl1271_free_tx_id(wl, result->id);
707} 777}
708 778
@@ -747,23 +817,26 @@ void wl1271_tx_complete(struct wl1271 *wl)
747void wl1271_tx_reset_link_queues(struct wl1271 *wl, u8 hlid) 817void wl1271_tx_reset_link_queues(struct wl1271 *wl, u8 hlid)
748{ 818{
749 struct sk_buff *skb; 819 struct sk_buff *skb;
750 int i, total = 0; 820 int i;
751 unsigned long flags; 821 unsigned long flags;
752 struct ieee80211_tx_info *info; 822 struct ieee80211_tx_info *info;
823 int total[NUM_TX_QUEUES];
753 824
754 for (i = 0; i < NUM_TX_QUEUES; i++) { 825 for (i = 0; i < NUM_TX_QUEUES; i++) {
826 total[i] = 0;
755 while ((skb = skb_dequeue(&wl->links[hlid].tx_queue[i]))) { 827 while ((skb = skb_dequeue(&wl->links[hlid].tx_queue[i]))) {
756 wl1271_debug(DEBUG_TX, "link freeing skb 0x%p", skb); 828 wl1271_debug(DEBUG_TX, "link freeing skb 0x%p", skb);
757 info = IEEE80211_SKB_CB(skb); 829 info = IEEE80211_SKB_CB(skb);
758 info->status.rates[0].idx = -1; 830 info->status.rates[0].idx = -1;
759 info->status.rates[0].count = 0; 831 info->status.rates[0].count = 0;
760 ieee80211_tx_status(wl->hw, skb); 832 ieee80211_tx_status_ni(wl->hw, skb);
761 total++; 833 total[i]++;
762 } 834 }
763 } 835 }
764 836
765 spin_lock_irqsave(&wl->wl_lock, flags); 837 spin_lock_irqsave(&wl->wl_lock, flags);
766 wl->tx_queue_count -= total; 838 for (i = 0; i < NUM_TX_QUEUES; i++)
839 wl->tx_queue_count[i] -= total[i];
767 spin_unlock_irqrestore(&wl->wl_lock, flags); 840 spin_unlock_irqrestore(&wl->wl_lock, flags);
768 841
769 wl1271_handle_tx_low_watermark(wl); 842 wl1271_handle_tx_low_watermark(wl);
@@ -795,13 +868,14 @@ void wl1271_tx_reset(struct wl1271 *wl, bool reset_tx_queues)
795 info = IEEE80211_SKB_CB(skb); 868 info = IEEE80211_SKB_CB(skb);
796 info->status.rates[0].idx = -1; 869 info->status.rates[0].idx = -1;
797 info->status.rates[0].count = 0; 870 info->status.rates[0].count = 0;
798 ieee80211_tx_status(wl->hw, skb); 871 ieee80211_tx_status_ni(wl->hw, skb);
799 } 872 }
800 } 873 }
874 wl->tx_queue_count[i] = 0;
801 } 875 }
802 } 876 }
803 877
804 wl->tx_queue_count = 0; 878 wl->stopped_queues_map = 0;
805 879
806 /* 880 /*
807 * Make sure the driver is at a consistent state, in case this 881 * Make sure the driver is at a consistent state, in case this
@@ -838,7 +912,7 @@ void wl1271_tx_reset(struct wl1271 *wl, bool reset_tx_queues)
838 info->status.rates[0].idx = -1; 912 info->status.rates[0].idx = -1;
839 info->status.rates[0].count = 0; 913 info->status.rates[0].count = 0;
840 914
841 ieee80211_tx_status(wl->hw, skb); 915 ieee80211_tx_status_ni(wl->hw, skb);
842 } 916 }
843 } 917 }
844} 918}
@@ -854,8 +928,10 @@ void wl1271_tx_flush(struct wl1271 *wl)
854 while (!time_after(jiffies, timeout)) { 928 while (!time_after(jiffies, timeout)) {
855 mutex_lock(&wl->mutex); 929 mutex_lock(&wl->mutex);
856 wl1271_debug(DEBUG_TX, "flushing tx buffer: %d %d", 930 wl1271_debug(DEBUG_TX, "flushing tx buffer: %d %d",
857 wl->tx_frames_cnt, wl->tx_queue_count); 931 wl->tx_frames_cnt,
858 if ((wl->tx_frames_cnt == 0) && (wl->tx_queue_count == 0)) { 932 wl1271_tx_total_queue_count(wl));
933 if ((wl->tx_frames_cnt == 0) &&
934 (wl1271_tx_total_queue_count(wl) == 0)) {
859 mutex_unlock(&wl->mutex); 935 mutex_unlock(&wl->mutex);
860 return; 936 return;
861 } 937 }
diff --git a/drivers/net/wireless/wl12xx/tx.h b/drivers/net/wireless/wl12xx/tx.h
index 832f9258d675..5d719b5a3d1d 100644
--- a/drivers/net/wireless/wl12xx/tx.h
+++ b/drivers/net/wireless/wl12xx/tx.h
@@ -150,7 +150,7 @@ struct wl1271_tx_hw_res_descr {
150 (from 1st EDCA AIFS counter until TX Complete). */ 150 (from 1st EDCA AIFS counter until TX Complete). */
151 __le32 medium_delay; 151 __le32 medium_delay;
152 /* LS-byte of last TKIP seq-num (saved per AC for recovery). */ 152 /* LS-byte of last TKIP seq-num (saved per AC for recovery). */
153 u8 lsb_security_sequence_number; 153 u8 tx_security_sequence_number_lsb;
154 /* Retry count - number of transmissions without successful ACK.*/ 154 /* Retry count - number of transmissions without successful ACK.*/
155 u8 ack_failures; 155 u8 ack_failures;
156 /* The rate that succeeded getting ACK 156 /* The rate that succeeded getting ACK
@@ -182,6 +182,32 @@ static inline int wl1271_tx_get_queue(int queue)
182 } 182 }
183} 183}
184 184
185static inline int wl1271_tx_get_mac80211_queue(int queue)
186{
187 switch (queue) {
188 case CONF_TX_AC_VO:
189 return 0;
190 case CONF_TX_AC_VI:
191 return 1;
192 case CONF_TX_AC_BE:
193 return 2;
194 case CONF_TX_AC_BK:
195 return 3;
196 default:
197 return 2;
198 }
199}
200
201static inline int wl1271_tx_total_queue_count(struct wl1271 *wl)
202{
203 int i, count = 0;
204
205 for (i = 0; i < NUM_TX_QUEUES; i++)
206 count += wl->tx_queue_count[i];
207
208 return count;
209}
210
185void wl1271_tx_work(struct work_struct *work); 211void wl1271_tx_work(struct work_struct *work);
186void wl1271_tx_work_locked(struct wl1271 *wl); 212void wl1271_tx_work_locked(struct wl1271 *wl);
187void wl1271_tx_complete(struct wl1271 *wl); 213void wl1271_tx_complete(struct wl1271 *wl);
diff --git a/drivers/net/wireless/wl12xx/wl12xx.h b/drivers/net/wireless/wl12xx/wl12xx.h
index fbe8f46d1232..1a8751eb8140 100644
--- a/drivers/net/wireless/wl12xx/wl12xx.h
+++ b/drivers/net/wireless/wl12xx/wl12xx.h
@@ -144,6 +144,7 @@ extern u32 wl12xx_debug_level;
144 144
145#define WL1271_TX_SECURITY_LO16(s) ((u16)((s) & 0xffff)) 145#define WL1271_TX_SECURITY_LO16(s) ((u16)((s) & 0xffff))
146#define WL1271_TX_SECURITY_HI32(s) ((u32)(((s) >> 16) & 0xffffffff)) 146#define WL1271_TX_SECURITY_HI32(s) ((u32)(((s) >> 16) & 0xffffffff))
147#define WL1271_TX_SQN_POST_RECOVERY_PADDING 0xff
147 148
148#define WL1271_CIPHER_SUITE_GEM 0x00147201 149#define WL1271_CIPHER_SUITE_GEM 0x00147201
149 150
@@ -172,7 +173,6 @@ extern u32 wl12xx_debug_level;
172#define WL1271_PS_STA_MAX_BLOCKS (2 * 9) 173#define WL1271_PS_STA_MAX_BLOCKS (2 * 9)
173 174
174#define WL1271_AP_BSS_INDEX 0 175#define WL1271_AP_BSS_INDEX 0
175#define WL1271_AP_DEF_INACTIV_SEC 300
176#define WL1271_AP_DEF_BEACON_EXP 20 176#define WL1271_AP_DEF_BEACON_EXP 20
177 177
178#define ACX_TX_DESCRIPTORS 32 178#define ACX_TX_DESCRIPTORS 32
@@ -226,6 +226,8 @@ enum {
226#define FW_VER_MINOR_1_SPARE_STA_MIN 58 226#define FW_VER_MINOR_1_SPARE_STA_MIN 58
227#define FW_VER_MINOR_1_SPARE_AP_MIN 47 227#define FW_VER_MINOR_1_SPARE_AP_MIN 47
228 228
229#define FW_VER_MINOR_FWLOG_STA_MIN 70
230
229struct wl1271_chip { 231struct wl1271_chip {
230 u32 id; 232 u32 id;
231 char fw_ver_str[ETHTOOL_BUSINFO_LEN]; 233 char fw_ver_str[ETHTOOL_BUSINFO_LEN];
@@ -284,8 +286,7 @@ struct wl1271_fw_sta_status {
284 u8 tx_total; 286 u8 tx_total;
285 u8 reserved1; 287 u8 reserved1;
286 __le16 reserved2; 288 __le16 reserved2;
287 /* Total structure size is 68 bytes */ 289 __le32 log_start_addr;
288 u32 padding;
289} __packed; 290} __packed;
290 291
291struct wl1271_fw_full_status { 292struct wl1271_fw_full_status {
@@ -359,6 +360,9 @@ enum wl12xx_flags {
359 WL1271_FLAG_DUMMY_PACKET_PENDING, 360 WL1271_FLAG_DUMMY_PACKET_PENDING,
360 WL1271_FLAG_SUSPENDED, 361 WL1271_FLAG_SUSPENDED,
361 WL1271_FLAG_PENDING_WORK, 362 WL1271_FLAG_PENDING_WORK,
363 WL1271_FLAG_SOFT_GEMINI,
364 WL1271_FLAG_RX_STREAMING_STARTED,
365 WL1271_FLAG_RECOVERY_IN_PROGRESS,
362}; 366};
363 367
364struct wl1271_link { 368struct wl1271_link {
@@ -420,7 +424,7 @@ struct wl1271 {
420 /* Accounting for allocated / available TX blocks on HW */ 424 /* Accounting for allocated / available TX blocks on HW */
421 u32 tx_blocks_freed[NUM_TX_QUEUES]; 425 u32 tx_blocks_freed[NUM_TX_QUEUES];
422 u32 tx_blocks_available; 426 u32 tx_blocks_available;
423 u32 tx_allocated_blocks; 427 u32 tx_allocated_blocks[NUM_TX_QUEUES];
424 u32 tx_results_count; 428 u32 tx_results_count;
425 429
426 /* Transmitted TX packets counter for chipset interface */ 430 /* Transmitted TX packets counter for chipset interface */
@@ -434,7 +438,8 @@ struct wl1271 {
434 438
435 /* Frames scheduled for transmission, not handled yet */ 439 /* Frames scheduled for transmission, not handled yet */
436 struct sk_buff_head tx_queue[NUM_TX_QUEUES]; 440 struct sk_buff_head tx_queue[NUM_TX_QUEUES];
437 int tx_queue_count; 441 int tx_queue_count[NUM_TX_QUEUES];
442 long stopped_queues_map;
438 443
439 /* Frames received, not handled yet by mac80211 */ 444 /* Frames received, not handled yet by mac80211 */
440 struct sk_buff_head deferred_rx_queue; 445 struct sk_buff_head deferred_rx_queue;
@@ -443,15 +448,23 @@ struct wl1271 {
443 struct sk_buff_head deferred_tx_queue; 448 struct sk_buff_head deferred_tx_queue;
444 449
445 struct work_struct tx_work; 450 struct work_struct tx_work;
451 struct workqueue_struct *freezable_wq;
446 452
447 /* Pending TX frames */ 453 /* Pending TX frames */
448 unsigned long tx_frames_map[BITS_TO_LONGS(ACX_TX_DESCRIPTORS)]; 454 unsigned long tx_frames_map[BITS_TO_LONGS(ACX_TX_DESCRIPTORS)];
449 struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS]; 455 struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
450 int tx_frames_cnt; 456 int tx_frames_cnt;
451 457
452 /* Security sequence number counters */ 458 /*
453 u8 tx_security_last_seq; 459 * Security sequence number
454 s64 tx_security_seq; 460 * bits 0-15: lower 16 bits part of sequence number
461 * bits 16-47: higher 32 bits part of sequence number
462 * bits 48-63: not in use
463 */
464 u64 tx_security_seq;
465
466 /* 8 bits of the last sequence number in use */
467 u8 tx_security_last_seq_lsb;
455 468
456 /* FW Rx counter */ 469 /* FW Rx counter */
457 u32 rx_counter; 470 u32 rx_counter;
@@ -468,6 +481,15 @@ struct wl1271 {
468 /* Network stack work */ 481 /* Network stack work */
469 struct work_struct netstack_work; 482 struct work_struct netstack_work;
470 483
484 /* FW log buffer */
485 u8 *fwlog;
486
487 /* Number of valid bytes in the FW log buffer */
488 ssize_t fwlog_size;
489
490 /* Sysfs FW log entry readers wait queue */
491 wait_queue_head_t fwlog_waitq;
492
471 /* Hardware recovery work */ 493 /* Hardware recovery work */
472 struct work_struct recovery_work; 494 struct work_struct recovery_work;
473 495
@@ -508,6 +530,11 @@ struct wl1271 {
508 /* Default key (for WEP) */ 530 /* Default key (for WEP) */
509 u32 default_key; 531 u32 default_key;
510 532
533 /* Rx Streaming */
534 struct work_struct rx_streaming_enable_work;
535 struct work_struct rx_streaming_disable_work;
536 struct timer_list rx_streaming_timer;
537
511 unsigned int filters; 538 unsigned int filters;
512 unsigned int rx_config; 539 unsigned int rx_config;
513 unsigned int rx_filter; 540 unsigned int rx_filter;
@@ -564,6 +591,7 @@ struct wl1271 {
564 /* RX BA constraint value */ 591 /* RX BA constraint value */
565 bool ba_support; 592 bool ba_support;
566 u8 ba_rx_bitmap; 593 u8 ba_rx_bitmap;
594 bool ba_allowed;
567 595
568 int tcxo_clock; 596 int tcxo_clock;
569 597
@@ -572,6 +600,7 @@ struct wl1271 {
572 * (currently, only "ANY" trigger is supported) 600 * (currently, only "ANY" trigger is supported)
573 */ 601 */
574 bool wow_enabled; 602 bool wow_enabled;
603 bool irq_wake_enabled;
575 604
576 /* 605 /*
577 * AP-mode - links indexed by HLID. The global and broadcast links 606 * AP-mode - links indexed by HLID. The global and broadcast links
@@ -601,6 +630,9 @@ struct wl1271_station {
601 630
602int wl1271_plt_start(struct wl1271 *wl); 631int wl1271_plt_start(struct wl1271 *wl);
603int wl1271_plt_stop(struct wl1271 *wl); 632int wl1271_plt_stop(struct wl1271 *wl);
633int wl1271_recalc_rx_streaming(struct wl1271 *wl);
634void wl12xx_queue_recovery_work(struct wl1271 *wl);
635size_t wl12xx_copy_fwlog(struct wl1271 *wl, u8 *memblock, size_t maxlen);
604 636
605#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */ 637#define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */
606 638
@@ -608,8 +640,8 @@ int wl1271_plt_stop(struct wl1271 *wl);
608 640
609#define WL1271_DEFAULT_POWER_LEVEL 0 641#define WL1271_DEFAULT_POWER_LEVEL 0
610 642
611#define WL1271_TX_QUEUE_LOW_WATERMARK 10 643#define WL1271_TX_QUEUE_LOW_WATERMARK 32
612#define WL1271_TX_QUEUE_HIGH_WATERMARK 25 644#define WL1271_TX_QUEUE_HIGH_WATERMARK 256
613 645
614#define WL1271_DEFERRED_QUEUE_LIMIT 64 646#define WL1271_DEFERRED_QUEUE_LIMIT 64
615 647
@@ -636,4 +668,15 @@ int wl1271_plt_stop(struct wl1271 *wl);
636/* WL128X requires aggregated packets to be aligned to the SDIO block size */ 668/* WL128X requires aggregated packets to be aligned to the SDIO block size */
637#define WL12XX_QUIRK_BLOCKSIZE_ALIGNMENT BIT(2) 669#define WL12XX_QUIRK_BLOCKSIZE_ALIGNMENT BIT(2)
638 670
671/*
672 * WL127X AP mode requires Low Power DRPw (LPD) enable to reduce power
673 * consumption
674 */
675#define WL12XX_QUIRK_LPD_MODE BIT(3)
676
677/* Older firmwares did not implement the FW logger over bus feature */
678#define WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
679
680#define WL12XX_HW_BLOCK_SIZE 256
681
639#endif 682#endif
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.h b/drivers/net/wireless/zd1211rw/zd_chip.h
index 4be7c3b5b265..117c4123943c 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.h
+++ b/drivers/net/wireless/zd1211rw/zd_chip.h
@@ -21,6 +21,8 @@
21#ifndef _ZD_CHIP_H 21#ifndef _ZD_CHIP_H
22#define _ZD_CHIP_H 22#define _ZD_CHIP_H
23 23
24#include <net/mac80211.h>
25
24#include "zd_rf.h" 26#include "zd_rf.h"
25#include "zd_usb.h" 27#include "zd_usb.h"
26 28
diff --git a/drivers/net/wireless/zd1211rw/zd_def.h b/drivers/net/wireless/zd1211rw/zd_def.h
index 5463ca9ebc01..9a1b013f81be 100644
--- a/drivers/net/wireless/zd1211rw/zd_def.h
+++ b/drivers/net/wireless/zd1211rw/zd_def.h
@@ -37,9 +37,15 @@ typedef u16 __nocast zd_addr_t;
37 if (net_ratelimit()) \ 37 if (net_ratelimit()) \
38 dev_printk_f(KERN_DEBUG, dev, fmt, ## args); \ 38 dev_printk_f(KERN_DEBUG, dev, fmt, ## args); \
39} while (0) 39} while (0)
40# define dev_dbg_f_cond(dev, cond, fmt, args...) ({ \
41 bool __cond = !!(cond); \
42 if (unlikely(__cond)) \
43 dev_printk_f(KERN_DEBUG, dev, fmt, ## args); \
44})
40#else 45#else
41# define dev_dbg_f(dev, fmt, args...) do { (void)(dev); } while (0) 46# define dev_dbg_f(dev, fmt, args...) do { (void)(dev); } while (0)
42# define dev_dbg_f_limit(dev, fmt, args...) do { (void)(dev); } while (0) 47# define dev_dbg_f_limit(dev, fmt, args...) do { (void)(dev); } while (0)
48# define dev_dbg_f_cond(dev, cond, fmt, args...) do { (void)(dev); } while (0)
43#endif /* DEBUG */ 49#endif /* DEBUG */
44 50
45#ifdef DEBUG 51#ifdef DEBUG
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c
index 5037c8b2b415..cabfae1e70b1 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.c
+++ b/drivers/net/wireless/zd1211rw/zd_mac.c
@@ -143,7 +143,7 @@ static void beacon_enable(struct zd_mac *mac);
143static void beacon_disable(struct zd_mac *mac); 143static void beacon_disable(struct zd_mac *mac);
144static void set_rts_cts(struct zd_mac *mac, unsigned int short_preamble); 144static void set_rts_cts(struct zd_mac *mac, unsigned int short_preamble);
145static int zd_mac_config_beacon(struct ieee80211_hw *hw, 145static int zd_mac_config_beacon(struct ieee80211_hw *hw,
146 struct sk_buff *beacon); 146 struct sk_buff *beacon, bool in_intr);
147 147
148static int zd_reg2alpha2(u8 regdomain, char *alpha2) 148static int zd_reg2alpha2(u8 regdomain, char *alpha2)
149{ 149{
@@ -160,6 +160,22 @@ static int zd_reg2alpha2(u8 regdomain, char *alpha2)
160 return 1; 160 return 1;
161} 161}
162 162
163static int zd_check_signal(struct ieee80211_hw *hw, int signal)
164{
165 struct zd_mac *mac = zd_hw_mac(hw);
166
167 dev_dbg_f_cond(zd_mac_dev(mac), signal < 0 || signal > 100,
168 "%s: signal value from device not in range 0..100, "
169 "but %d.\n", __func__, signal);
170
171 if (signal < 0)
172 signal = 0;
173 else if (signal > 100)
174 signal = 100;
175
176 return signal;
177}
178
163int zd_mac_preinit_hw(struct ieee80211_hw *hw) 179int zd_mac_preinit_hw(struct ieee80211_hw *hw)
164{ 180{
165 int r; 181 int r;
@@ -387,10 +403,8 @@ int zd_restore_settings(struct zd_mac *mac)
387 mac->type == NL80211_IFTYPE_AP) { 403 mac->type == NL80211_IFTYPE_AP) {
388 if (mac->vif != NULL) { 404 if (mac->vif != NULL) {
389 beacon = ieee80211_beacon_get(mac->hw, mac->vif); 405 beacon = ieee80211_beacon_get(mac->hw, mac->vif);
390 if (beacon) { 406 if (beacon)
391 zd_mac_config_beacon(mac->hw, beacon); 407 zd_mac_config_beacon(mac->hw, beacon, false);
392 kfree_skb(beacon);
393 }
394 } 408 }
395 409
396 zd_set_beacon_interval(&mac->chip, beacon_interval, 410 zd_set_beacon_interval(&mac->chip, beacon_interval,
@@ -461,7 +475,7 @@ static void zd_mac_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb,
461 if (i<IEEE80211_TX_MAX_RATES) 475 if (i<IEEE80211_TX_MAX_RATES)
462 info->status.rates[i].idx = -1; /* terminate */ 476 info->status.rates[i].idx = -1; /* terminate */
463 477
464 info->status.ack_signal = ackssi; 478 info->status.ack_signal = zd_check_signal(hw, ackssi);
465 ieee80211_tx_status_irqsafe(hw, skb); 479 ieee80211_tx_status_irqsafe(hw, skb);
466} 480}
467 481
@@ -664,7 +678,34 @@ static void cs_set_control(struct zd_mac *mac, struct zd_ctrlset *cs,
664 /* FIXME: Management frame? */ 678 /* FIXME: Management frame? */
665} 679}
666 680
667static int zd_mac_config_beacon(struct ieee80211_hw *hw, struct sk_buff *beacon) 681static bool zd_mac_match_cur_beacon(struct zd_mac *mac, struct sk_buff *beacon)
682{
683 if (!mac->beacon.cur_beacon)
684 return false;
685
686 if (mac->beacon.cur_beacon->len != beacon->len)
687 return false;
688
689 return !memcmp(beacon->data, mac->beacon.cur_beacon->data, beacon->len);
690}
691
692static void zd_mac_free_cur_beacon_locked(struct zd_mac *mac)
693{
694 ZD_ASSERT(mutex_is_locked(&mac->chip.mutex));
695
696 kfree_skb(mac->beacon.cur_beacon);
697 mac->beacon.cur_beacon = NULL;
698}
699
700static void zd_mac_free_cur_beacon(struct zd_mac *mac)
701{
702 mutex_lock(&mac->chip.mutex);
703 zd_mac_free_cur_beacon_locked(mac);
704 mutex_unlock(&mac->chip.mutex);
705}
706
707static int zd_mac_config_beacon(struct ieee80211_hw *hw, struct sk_buff *beacon,
708 bool in_intr)
668{ 709{
669 struct zd_mac *mac = zd_hw_mac(hw); 710 struct zd_mac *mac = zd_hw_mac(hw);
670 int r, ret, num_cmds, req_pos = 0; 711 int r, ret, num_cmds, req_pos = 0;
@@ -674,13 +715,21 @@ static int zd_mac_config_beacon(struct ieee80211_hw *hw, struct sk_buff *beacon)
674 unsigned long end_jiffies, message_jiffies; 715 unsigned long end_jiffies, message_jiffies;
675 struct zd_ioreq32 *ioreqs; 716 struct zd_ioreq32 *ioreqs;
676 717
718 mutex_lock(&mac->chip.mutex);
719
720 /* Check if hw already has this beacon. */
721 if (zd_mac_match_cur_beacon(mac, beacon)) {
722 r = 0;
723 goto out_nofree;
724 }
725
677 /* Alloc memory for full beacon write at once. */ 726 /* Alloc memory for full beacon write at once. */
678 num_cmds = 1 + zd_chip_is_zd1211b(&mac->chip) + full_len; 727 num_cmds = 1 + zd_chip_is_zd1211b(&mac->chip) + full_len;
679 ioreqs = kmalloc(num_cmds * sizeof(struct zd_ioreq32), GFP_KERNEL); 728 ioreqs = kmalloc(num_cmds * sizeof(struct zd_ioreq32), GFP_KERNEL);
680 if (!ioreqs) 729 if (!ioreqs) {
681 return -ENOMEM; 730 r = -ENOMEM;
682 731 goto out_nofree;
683 mutex_lock(&mac->chip.mutex); 732 }
684 733
685 r = zd_iowrite32_locked(&mac->chip, 0, CR_BCN_FIFO_SEMAPHORE); 734 r = zd_iowrite32_locked(&mac->chip, 0, CR_BCN_FIFO_SEMAPHORE);
686 if (r < 0) 735 if (r < 0)
@@ -688,6 +737,10 @@ static int zd_mac_config_beacon(struct ieee80211_hw *hw, struct sk_buff *beacon)
688 r = zd_ioread32_locked(&mac->chip, &tmp, CR_BCN_FIFO_SEMAPHORE); 737 r = zd_ioread32_locked(&mac->chip, &tmp, CR_BCN_FIFO_SEMAPHORE);
689 if (r < 0) 738 if (r < 0)
690 goto release_sema; 739 goto release_sema;
740 if (in_intr && tmp & 0x2) {
741 r = -EBUSY;
742 goto release_sema;
743 }
691 744
692 end_jiffies = jiffies + HZ / 2; /*~500ms*/ 745 end_jiffies = jiffies + HZ / 2; /*~500ms*/
693 message_jiffies = jiffies + HZ / 10; /*~100ms*/ 746 message_jiffies = jiffies + HZ / 10; /*~100ms*/
@@ -742,7 +795,7 @@ release_sema:
742 end_jiffies = jiffies + HZ / 2; /*~500ms*/ 795 end_jiffies = jiffies + HZ / 2; /*~500ms*/
743 ret = zd_iowrite32_locked(&mac->chip, 1, CR_BCN_FIFO_SEMAPHORE); 796 ret = zd_iowrite32_locked(&mac->chip, 1, CR_BCN_FIFO_SEMAPHORE);
744 while (ret < 0) { 797 while (ret < 0) {
745 if (time_is_before_eq_jiffies(end_jiffies)) { 798 if (in_intr || time_is_before_eq_jiffies(end_jiffies)) {
746 ret = -ETIMEDOUT; 799 ret = -ETIMEDOUT;
747 break; 800 break;
748 } 801 }
@@ -757,9 +810,19 @@ release_sema:
757 if (r < 0 || ret < 0) { 810 if (r < 0 || ret < 0) {
758 if (r >= 0) 811 if (r >= 0)
759 r = ret; 812 r = ret;
813
814 /* We don't know if beacon was written successfully or not,
815 * so clear current. */
816 zd_mac_free_cur_beacon_locked(mac);
817
760 goto out; 818 goto out;
761 } 819 }
762 820
821 /* Beacon has now been written successfully, update current. */
822 zd_mac_free_cur_beacon_locked(mac);
823 mac->beacon.cur_beacon = beacon;
824 beacon = NULL;
825
763 /* 802.11b/g 2.4G CCK 1Mb 826 /* 802.11b/g 2.4G CCK 1Mb
764 * 802.11a, not yet implemented, uses different values (see GPL vendor 827 * 802.11a, not yet implemented, uses different values (see GPL vendor
765 * driver) 828 * driver)
@@ -767,11 +830,17 @@ release_sema:
767 r = zd_iowrite32_locked(&mac->chip, 0x00000400 | (full_len << 19), 830 r = zd_iowrite32_locked(&mac->chip, 0x00000400 | (full_len << 19),
768 CR_BCN_PLCP_CFG); 831 CR_BCN_PLCP_CFG);
769out: 832out:
770 mutex_unlock(&mac->chip.mutex);
771 kfree(ioreqs); 833 kfree(ioreqs);
834out_nofree:
835 kfree_skb(beacon);
836 mutex_unlock(&mac->chip.mutex);
837
772 return r; 838 return r;
773 839
774reset_device: 840reset_device:
841 zd_mac_free_cur_beacon_locked(mac);
842 kfree_skb(beacon);
843
775 mutex_unlock(&mac->chip.mutex); 844 mutex_unlock(&mac->chip.mutex);
776 kfree(ioreqs); 845 kfree(ioreqs);
777 846
@@ -982,7 +1051,7 @@ int zd_mac_rx(struct ieee80211_hw *hw, const u8 *buffer, unsigned int length)
982 1051
983 stats.freq = zd_channels[_zd_chip_get_channel(&mac->chip) - 1].center_freq; 1052 stats.freq = zd_channels[_zd_chip_get_channel(&mac->chip) - 1].center_freq;
984 stats.band = IEEE80211_BAND_2GHZ; 1053 stats.band = IEEE80211_BAND_2GHZ;
985 stats.signal = status->signal_strength; 1054 stats.signal = zd_check_signal(hw, status->signal_strength);
986 1055
987 rate = zd_rx_rate(buffer, status); 1056 rate = zd_rx_rate(buffer, status);
988 1057
@@ -1057,6 +1126,8 @@ static void zd_op_remove_interface(struct ieee80211_hw *hw,
1057 mac->vif = NULL; 1126 mac->vif = NULL;
1058 zd_set_beacon_interval(&mac->chip, 0, 0, NL80211_IFTYPE_UNSPECIFIED); 1127 zd_set_beacon_interval(&mac->chip, 0, 0, NL80211_IFTYPE_UNSPECIFIED);
1059 zd_write_mac_addr(&mac->chip, NULL); 1128 zd_write_mac_addr(&mac->chip, NULL);
1129
1130 zd_mac_free_cur_beacon(mac);
1060} 1131}
1061 1132
1062static int zd_op_config(struct ieee80211_hw *hw, u32 changed) 1133static int zd_op_config(struct ieee80211_hw *hw, u32 changed)
@@ -1094,10 +1165,8 @@ static void zd_beacon_done(struct zd_mac *mac)
1094 * Fetch next beacon so that tim_count is updated. 1165 * Fetch next beacon so that tim_count is updated.
1095 */ 1166 */
1096 beacon = ieee80211_beacon_get(mac->hw, mac->vif); 1167 beacon = ieee80211_beacon_get(mac->hw, mac->vif);
1097 if (beacon) { 1168 if (beacon)
1098 zd_mac_config_beacon(mac->hw, beacon); 1169 zd_mac_config_beacon(mac->hw, beacon, true);
1099 kfree_skb(beacon);
1100 }
1101 1170
1102 spin_lock_irq(&mac->lock); 1171 spin_lock_irq(&mac->lock);
1103 mac->beacon.last_update = jiffies; 1172 mac->beacon.last_update = jiffies;
@@ -1222,9 +1291,8 @@ static void zd_op_bss_info_changed(struct ieee80211_hw *hw,
1222 1291
1223 if (beacon) { 1292 if (beacon) {
1224 zd_chip_disable_hwint(&mac->chip); 1293 zd_chip_disable_hwint(&mac->chip);
1225 zd_mac_config_beacon(hw, beacon); 1294 zd_mac_config_beacon(hw, beacon, false);
1226 zd_chip_enable_hwint(&mac->chip); 1295 zd_chip_enable_hwint(&mac->chip);
1227 kfree_skb(beacon);
1228 } 1296 }
1229 } 1297 }
1230 1298
@@ -1361,7 +1429,8 @@ static void beacon_watchdog_handler(struct work_struct *work)
1361 spin_lock_irq(&mac->lock); 1429 spin_lock_irq(&mac->lock);
1362 interval = mac->beacon.interval; 1430 interval = mac->beacon.interval;
1363 period = mac->beacon.period; 1431 period = mac->beacon.period;
1364 timeout = mac->beacon.last_update + msecs_to_jiffies(interval) + HZ; 1432 timeout = mac->beacon.last_update +
1433 msecs_to_jiffies(interval * 1024 / 1000) * 3;
1365 spin_unlock_irq(&mac->lock); 1434 spin_unlock_irq(&mac->lock);
1366 1435
1367 if (interval > 0 && time_is_before_jiffies(timeout)) { 1436 if (interval > 0 && time_is_before_jiffies(timeout)) {
@@ -1374,8 +1443,9 @@ static void beacon_watchdog_handler(struct work_struct *work)
1374 1443
1375 beacon = ieee80211_beacon_get(mac->hw, mac->vif); 1444 beacon = ieee80211_beacon_get(mac->hw, mac->vif);
1376 if (beacon) { 1445 if (beacon) {
1377 zd_mac_config_beacon(mac->hw, beacon); 1446 zd_mac_free_cur_beacon(mac);
1378 kfree_skb(beacon); 1447
1448 zd_mac_config_beacon(mac->hw, beacon, false);
1379 } 1449 }
1380 1450
1381 zd_set_beacon_interval(&mac->chip, interval, period, mac->type); 1451 zd_set_beacon_interval(&mac->chip, interval, period, mac->type);
@@ -1410,6 +1480,8 @@ static void beacon_disable(struct zd_mac *mac)
1410{ 1480{
1411 dev_dbg_f(zd_mac_dev(mac), "\n"); 1481 dev_dbg_f(zd_mac_dev(mac), "\n");
1412 cancel_delayed_work_sync(&mac->beacon.watchdog_work); 1482 cancel_delayed_work_sync(&mac->beacon.watchdog_work);
1483
1484 zd_mac_free_cur_beacon(mac);
1413} 1485}
1414 1486
1415#define LINK_LED_WORK_DELAY HZ 1487#define LINK_LED_WORK_DELAY HZ
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.h b/drivers/net/wireless/zd1211rw/zd_mac.h
index f8c93c3fe755..c01eca859f95 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.h
+++ b/drivers/net/wireless/zd1211rw/zd_mac.h
@@ -165,6 +165,7 @@ struct housekeeping {
165 165
166struct beacon { 166struct beacon {
167 struct delayed_work watchdog_work; 167 struct delayed_work watchdog_work;
168 struct sk_buff *cur_beacon;
168 unsigned long last_update; 169 unsigned long last_update;
169 u16 interval; 170 u16 interval;
170 u8 period; 171 u8 period;
diff --git a/drivers/net/wireless/zd1211rw/zd_usb.c b/drivers/net/wireless/zd1211rw/zd_usb.c
index 631194d49828..cf0d69dd7be5 100644
--- a/drivers/net/wireless/zd1211rw/zd_usb.c
+++ b/drivers/net/wireless/zd1211rw/zd_usb.c
@@ -111,6 +111,9 @@ MODULE_DEVICE_TABLE(usb, usb_ids);
111#define FW_ZD1211_PREFIX "zd1211/zd1211_" 111#define FW_ZD1211_PREFIX "zd1211/zd1211_"
112#define FW_ZD1211B_PREFIX "zd1211/zd1211b_" 112#define FW_ZD1211B_PREFIX "zd1211/zd1211b_"
113 113
114static bool check_read_regs(struct zd_usb *usb, struct usb_req_read_regs *req,
115 unsigned int count);
116
114/* USB device initialization */ 117/* USB device initialization */
115static void int_urb_complete(struct urb *urb); 118static void int_urb_complete(struct urb *urb);
116 119
@@ -365,6 +368,20 @@ exit:
365 368
366#define urb_dev(urb) (&(urb)->dev->dev) 369#define urb_dev(urb) (&(urb)->dev->dev)
367 370
371static inline void handle_regs_int_override(struct urb *urb)
372{
373 struct zd_usb *usb = urb->context;
374 struct zd_usb_interrupt *intr = &usb->intr;
375
376 spin_lock(&intr->lock);
377 if (atomic_read(&intr->read_regs_enabled)) {
378 atomic_set(&intr->read_regs_enabled, 0);
379 intr->read_regs_int_overridden = 1;
380 complete(&intr->read_regs.completion);
381 }
382 spin_unlock(&intr->lock);
383}
384
368static inline void handle_regs_int(struct urb *urb) 385static inline void handle_regs_int(struct urb *urb)
369{ 386{
370 struct zd_usb *usb = urb->context; 387 struct zd_usb *usb = urb->context;
@@ -383,25 +400,45 @@ static inline void handle_regs_int(struct urb *urb)
383 USB_MAX_EP_INT_BUFFER); 400 USB_MAX_EP_INT_BUFFER);
384 spin_unlock(&mac->lock); 401 spin_unlock(&mac->lock);
385 schedule_work(&mac->process_intr); 402 schedule_work(&mac->process_intr);
386 } else if (intr->read_regs_enabled) { 403 } else if (atomic_read(&intr->read_regs_enabled)) {
387 intr->read_regs.length = len = urb->actual_length; 404 len = urb->actual_length;
388 405 intr->read_regs.length = urb->actual_length;
389 if (len > sizeof(intr->read_regs.buffer)) 406 if (len > sizeof(intr->read_regs.buffer))
390 len = sizeof(intr->read_regs.buffer); 407 len = sizeof(intr->read_regs.buffer);
408
391 memcpy(intr->read_regs.buffer, urb->transfer_buffer, len); 409 memcpy(intr->read_regs.buffer, urb->transfer_buffer, len);
392 intr->read_regs_enabled = 0; 410
411 /* Sometimes USB_INT_ID_REGS is not overridden, but comes after
412 * USB_INT_ID_RETRY_FAILED. Read-reg retry then gets this
413 * delayed USB_INT_ID_REGS, but leaves USB_INT_ID_REGS of
414 * retry unhandled. Next read-reg command then might catch
415 * this wrong USB_INT_ID_REGS. Fix by ignoring wrong reads.
416 */
417 if (!check_read_regs(usb, intr->read_regs.req,
418 intr->read_regs.req_count))
419 goto out;
420
421 atomic_set(&intr->read_regs_enabled, 0);
422 intr->read_regs_int_overridden = 0;
393 complete(&intr->read_regs.completion); 423 complete(&intr->read_regs.completion);
424
394 goto out; 425 goto out;
395 } 426 }
396 427
397out: 428out:
398 spin_unlock(&intr->lock); 429 spin_unlock(&intr->lock);
430
431 /* CR_INTERRUPT might override read_reg too. */
432 if (int_num == CR_INTERRUPT && atomic_read(&intr->read_regs_enabled))
433 handle_regs_int_override(urb);
399} 434}
400 435
401static void int_urb_complete(struct urb *urb) 436static void int_urb_complete(struct urb *urb)
402{ 437{
403 int r; 438 int r;
404 struct usb_int_header *hdr; 439 struct usb_int_header *hdr;
440 struct zd_usb *usb;
441 struct zd_usb_interrupt *intr;
405 442
406 switch (urb->status) { 443 switch (urb->status) {
407 case 0: 444 case 0:
@@ -430,6 +467,14 @@ static void int_urb_complete(struct urb *urb)
430 goto resubmit; 467 goto resubmit;
431 } 468 }
432 469
470 /* USB_INT_ID_RETRY_FAILED triggered by tx-urb submit can override
471 * pending USB_INT_ID_REGS causing read command timeout.
472 */
473 usb = urb->context;
474 intr = &usb->intr;
475 if (hdr->id != USB_INT_ID_REGS && atomic_read(&intr->read_regs_enabled))
476 handle_regs_int_override(urb);
477
433 switch (hdr->id) { 478 switch (hdr->id) {
434 case USB_INT_ID_REGS: 479 case USB_INT_ID_REGS:
435 handle_regs_int(urb); 480 handle_regs_int(urb);
@@ -579,8 +624,8 @@ static void handle_rx_packet(struct zd_usb *usb, const u8 *buffer,
579 624
580 if (length < sizeof(struct rx_length_info)) { 625 if (length < sizeof(struct rx_length_info)) {
581 /* It's not a complete packet anyhow. */ 626 /* It's not a complete packet anyhow. */
582 printk("%s: invalid, small RX packet : %d\n", 627 dev_dbg_f(zd_usb_dev(usb), "invalid, small RX packet : %d\n",
583 __func__, length); 628 length);
584 return; 629 return;
585 } 630 }
586 length_info = (struct rx_length_info *) 631 length_info = (struct rx_length_info *)
@@ -1129,6 +1174,7 @@ static inline void init_usb_interrupt(struct zd_usb *usb)
1129 spin_lock_init(&intr->lock); 1174 spin_lock_init(&intr->lock);
1130 intr->interval = int_urb_interval(zd_usb_to_usbdev(usb)); 1175 intr->interval = int_urb_interval(zd_usb_to_usbdev(usb));
1131 init_completion(&intr->read_regs.completion); 1176 init_completion(&intr->read_regs.completion);
1177 atomic_set(&intr->read_regs_enabled, 0);
1132 intr->read_regs.cr_int_addr = cpu_to_le16((u16)CR_INTERRUPT); 1178 intr->read_regs.cr_int_addr = cpu_to_le16((u16)CR_INTERRUPT);
1133} 1179}
1134 1180
@@ -1563,12 +1609,16 @@ static int usb_int_regs_length(unsigned int count)
1563 return sizeof(struct usb_int_regs) + count * sizeof(struct reg_data); 1609 return sizeof(struct usb_int_regs) + count * sizeof(struct reg_data);
1564} 1610}
1565 1611
1566static void prepare_read_regs_int(struct zd_usb *usb) 1612static void prepare_read_regs_int(struct zd_usb *usb,
1613 struct usb_req_read_regs *req,
1614 unsigned int count)
1567{ 1615{
1568 struct zd_usb_interrupt *intr = &usb->intr; 1616 struct zd_usb_interrupt *intr = &usb->intr;
1569 1617
1570 spin_lock_irq(&intr->lock); 1618 spin_lock_irq(&intr->lock);
1571 intr->read_regs_enabled = 1; 1619 atomic_set(&intr->read_regs_enabled, 1);
1620 intr->read_regs.req = req;
1621 intr->read_regs.req_count = count;
1572 INIT_COMPLETION(intr->read_regs.completion); 1622 INIT_COMPLETION(intr->read_regs.completion);
1573 spin_unlock_irq(&intr->lock); 1623 spin_unlock_irq(&intr->lock);
1574} 1624}
@@ -1578,22 +1628,18 @@ static void disable_read_regs_int(struct zd_usb *usb)
1578 struct zd_usb_interrupt *intr = &usb->intr; 1628 struct zd_usb_interrupt *intr = &usb->intr;
1579 1629
1580 spin_lock_irq(&intr->lock); 1630 spin_lock_irq(&intr->lock);
1581 intr->read_regs_enabled = 0; 1631 atomic_set(&intr->read_regs_enabled, 0);
1582 spin_unlock_irq(&intr->lock); 1632 spin_unlock_irq(&intr->lock);
1583} 1633}
1584 1634
1585static int get_results(struct zd_usb *usb, u16 *values, 1635static bool check_read_regs(struct zd_usb *usb, struct usb_req_read_regs *req,
1586 struct usb_req_read_regs *req, unsigned int count) 1636 unsigned int count)
1587{ 1637{
1588 int r;
1589 int i; 1638 int i;
1590 struct zd_usb_interrupt *intr = &usb->intr; 1639 struct zd_usb_interrupt *intr = &usb->intr;
1591 struct read_regs_int *rr = &intr->read_regs; 1640 struct read_regs_int *rr = &intr->read_regs;
1592 struct usb_int_regs *regs = (struct usb_int_regs *)rr->buffer; 1641 struct usb_int_regs *regs = (struct usb_int_regs *)rr->buffer;
1593 1642
1594 spin_lock_irq(&intr->lock);
1595
1596 r = -EIO;
1597 /* The created block size seems to be larger than expected. 1643 /* The created block size seems to be larger than expected.
1598 * However results appear to be correct. 1644 * However results appear to be correct.
1599 */ 1645 */
@@ -1601,13 +1647,14 @@ static int get_results(struct zd_usb *usb, u16 *values,
1601 dev_dbg_f(zd_usb_dev(usb), 1647 dev_dbg_f(zd_usb_dev(usb),
1602 "error: actual length %d less than expected %d\n", 1648 "error: actual length %d less than expected %d\n",
1603 rr->length, usb_int_regs_length(count)); 1649 rr->length, usb_int_regs_length(count));
1604 goto error_unlock; 1650 return false;
1605 } 1651 }
1652
1606 if (rr->length > sizeof(rr->buffer)) { 1653 if (rr->length > sizeof(rr->buffer)) {
1607 dev_dbg_f(zd_usb_dev(usb), 1654 dev_dbg_f(zd_usb_dev(usb),
1608 "error: actual length %d exceeds buffer size %zu\n", 1655 "error: actual length %d exceeds buffer size %zu\n",
1609 rr->length, sizeof(rr->buffer)); 1656 rr->length, sizeof(rr->buffer));
1610 goto error_unlock; 1657 return false;
1611 } 1658 }
1612 1659
1613 for (i = 0; i < count; i++) { 1660 for (i = 0; i < count; i++) {
@@ -1617,8 +1664,39 @@ static int get_results(struct zd_usb *usb, u16 *values,
1617 "rd[%d] addr %#06hx expected %#06hx\n", i, 1664 "rd[%d] addr %#06hx expected %#06hx\n", i,
1618 le16_to_cpu(rd->addr), 1665 le16_to_cpu(rd->addr),
1619 le16_to_cpu(req->addr[i])); 1666 le16_to_cpu(req->addr[i]));
1620 goto error_unlock; 1667 return false;
1621 } 1668 }
1669 }
1670
1671 return true;
1672}
1673
1674static int get_results(struct zd_usb *usb, u16 *values,
1675 struct usb_req_read_regs *req, unsigned int count,
1676 bool *retry)
1677{
1678 int r;
1679 int i;
1680 struct zd_usb_interrupt *intr = &usb->intr;
1681 struct read_regs_int *rr = &intr->read_regs;
1682 struct usb_int_regs *regs = (struct usb_int_regs *)rr->buffer;
1683
1684 spin_lock_irq(&intr->lock);
1685
1686 r = -EIO;
1687
1688 /* Read failed because firmware bug? */
1689 *retry = !!intr->read_regs_int_overridden;
1690 if (*retry)
1691 goto error_unlock;
1692
1693 if (!check_read_regs(usb, req, count)) {
1694 dev_dbg_f(zd_usb_dev(usb), "error: invalid read regs\n");
1695 goto error_unlock;
1696 }
1697
1698 for (i = 0; i < count; i++) {
1699 struct reg_data *rd = &regs->regs[i];
1622 values[i] = le16_to_cpu(rd->value); 1700 values[i] = le16_to_cpu(rd->value);
1623 } 1701 }
1624 1702
@@ -1631,11 +1709,11 @@ error_unlock:
1631int zd_usb_ioread16v(struct zd_usb *usb, u16 *values, 1709int zd_usb_ioread16v(struct zd_usb *usb, u16 *values,
1632 const zd_addr_t *addresses, unsigned int count) 1710 const zd_addr_t *addresses, unsigned int count)
1633{ 1711{
1634 int r; 1712 int r, i, req_len, actual_req_len, try_count = 0;
1635 int i, req_len, actual_req_len;
1636 struct usb_device *udev; 1713 struct usb_device *udev;
1637 struct usb_req_read_regs *req = NULL; 1714 struct usb_req_read_regs *req = NULL;
1638 unsigned long timeout; 1715 unsigned long timeout;
1716 bool retry = false;
1639 1717
1640 if (count < 1) { 1718 if (count < 1) {
1641 dev_dbg_f(zd_usb_dev(usb), "error: count is zero\n"); 1719 dev_dbg_f(zd_usb_dev(usb), "error: count is zero\n");
@@ -1671,8 +1749,10 @@ int zd_usb_ioread16v(struct zd_usb *usb, u16 *values,
1671 for (i = 0; i < count; i++) 1749 for (i = 0; i < count; i++)
1672 req->addr[i] = cpu_to_le16((u16)addresses[i]); 1750 req->addr[i] = cpu_to_le16((u16)addresses[i]);
1673 1751
1752retry_read:
1753 try_count++;
1674 udev = zd_usb_to_usbdev(usb); 1754 udev = zd_usb_to_usbdev(usb);
1675 prepare_read_regs_int(usb); 1755 prepare_read_regs_int(usb, req, count);
1676 r = zd_ep_regs_out_msg(udev, req, req_len, &actual_req_len, 50 /*ms*/); 1756 r = zd_ep_regs_out_msg(udev, req, req_len, &actual_req_len, 50 /*ms*/);
1677 if (r) { 1757 if (r) {
1678 dev_dbg_f(zd_usb_dev(usb), 1758 dev_dbg_f(zd_usb_dev(usb),
@@ -1696,7 +1776,12 @@ int zd_usb_ioread16v(struct zd_usb *usb, u16 *values,
1696 goto error; 1776 goto error;
1697 } 1777 }
1698 1778
1699 r = get_results(usb, values, req, count); 1779 r = get_results(usb, values, req, count, &retry);
1780 if (retry && try_count < 20) {
1781 dev_dbg_f(zd_usb_dev(usb), "read retry, tries so far: %d\n",
1782 try_count);
1783 goto retry_read;
1784 }
1700error: 1785error:
1701 return r; 1786 return r;
1702} 1787}
diff --git a/drivers/net/wireless/zd1211rw/zd_usb.h b/drivers/net/wireless/zd1211rw/zd_usb.h
index bf942843b733..99193b456a79 100644
--- a/drivers/net/wireless/zd1211rw/zd_usb.h
+++ b/drivers/net/wireless/zd1211rw/zd_usb.h
@@ -144,6 +144,8 @@ struct usb_int_retry_fail {
144 144
145struct read_regs_int { 145struct read_regs_int {
146 struct completion completion; 146 struct completion completion;
147 struct usb_req_read_regs *req;
148 unsigned int req_count;
147 /* Stores the USB int structure and contains the USB address of the 149 /* Stores the USB int structure and contains the USB address of the
148 * first requested register before request. 150 * first requested register before request.
149 */ 151 */
@@ -169,7 +171,8 @@ struct zd_usb_interrupt {
169 void *buffer; 171 void *buffer;
170 dma_addr_t buffer_dma; 172 dma_addr_t buffer_dma;
171 int interval; 173 int interval;
172 u8 read_regs_enabled:1; 174 atomic_t read_regs_enabled;
175 u8 read_regs_int_overridden:1;
173}; 176};
174 177
175static inline struct usb_int_regs *get_read_regs(struct zd_usb_interrupt *intr) 178static inline struct usb_int_regs *get_read_regs(struct zd_usb_interrupt *intr)