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-rw-r--r--drivers/net/wireless/ath9k/ani.c34
-rw-r--r--drivers/net/wireless/ath9k/beacon.c77
-rw-r--r--drivers/net/wireless/ath9k/calib.c69
-rw-r--r--drivers/net/wireless/ath9k/core.h157
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c16
-rw-r--r--drivers/net/wireless/ath9k/hw.c189
-rw-r--r--drivers/net/wireless/ath9k/mac.c66
-rw-r--r--drivers/net/wireless/ath9k/main.c237
-rw-r--r--drivers/net/wireless/ath9k/phy.c14
-rw-r--r--drivers/net/wireless/ath9k/rc.c7
-rw-r--r--drivers/net/wireless/ath9k/recv.c14
-rw-r--r--drivers/net/wireless/ath9k/regd.c81
-rw-r--r--drivers/net/wireless/ath9k/xmit.c77
13 files changed, 429 insertions, 609 deletions
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c
index ada12e9aa7f9..c25b72be1139 100644
--- a/drivers/net/wireless/ath9k/ani.c
+++ b/drivers/net/wireless/ath9k/ani.c
@@ -53,8 +53,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
53 53
54 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { 54 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
55 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 55 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
56 "%s: level out of range (%u > %u)\n", 56 "level out of range (%u > %u)\n",
57 __func__, level, 57 level,
58 (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); 58 (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired));
59 return false; 59 return false;
60 } 60 }
@@ -158,8 +158,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
158 158
159 if (level >= ARRAY_SIZE(firstep)) { 159 if (level >= ARRAY_SIZE(firstep)) {
160 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 160 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
161 "%s: level out of range (%u > %u)\n", 161 "level out of range (%u > %u)\n",
162 __func__, level, 162 level,
163 (unsigned) ARRAY_SIZE(firstep)); 163 (unsigned) ARRAY_SIZE(firstep));
164 return false; 164 return false;
165 } 165 }
@@ -180,8 +180,8 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
180 180
181 if (level >= ARRAY_SIZE(cycpwrThr1)) { 181 if (level >= ARRAY_SIZE(cycpwrThr1)) {
182 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 182 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
183 "%s: level out of range (%u > %u)\n", 183 "level out of range (%u > %u)\n",
184 __func__, level, 184 level,
185 (unsigned) 185 (unsigned)
186 ARRAY_SIZE(cycpwrThr1)); 186 ARRAY_SIZE(cycpwrThr1));
187 return false; 187 return false;
@@ -200,11 +200,11 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah,
200 break; 200 break;
201 default: 201 default:
202 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 202 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
203 "%s: invalid cmd %u\n", __func__, cmd); 203 "invalid cmd %u\n", cmd);
204 return false; 204 return false;
205 } 205 }
206 206
207 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "%s: ANI parameters:\n", __func__); 207 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "ANI parameters:\n");
208 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 208 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
209 "noiseImmunityLevel=%d, spurImmunityLevel=%d, " 209 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
210 "ofdmWeakSigDetectOff=%d\n", 210 "ofdmWeakSigDetectOff=%d\n",
@@ -262,8 +262,8 @@ static void ath9k_ani_restart(struct ath_hal *ah)
262 AR_PHY_COUNTMAX - aniState->cckTrigHigh; 262 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
263 } 263 }
264 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 264 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
265 "%s: Writing ofdmbase=%u cckbase=%u\n", 265 "Writing ofdmbase=%u cckbase=%u\n",
266 __func__, aniState->ofdmPhyErrBase, 266 aniState->ofdmPhyErrBase,
267 aniState->cckPhyErrBase); 267 aniState->cckPhyErrBase);
268 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase); 268 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
269 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase); 269 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
@@ -490,8 +490,7 @@ void ath9k_ani_reset(struct ath_hal *ah)
490 if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA 490 if (DO_ANI(ah) && ah->ah_opmode != ATH9K_M_STA
491 && ah->ah_opmode != ATH9K_M_IBSS) { 491 && ah->ah_opmode != ATH9K_M_IBSS) {
492 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 492 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
493 "%s: Reset ANI state opmode %u\n", __func__, 493 "Reset ANI state opmode %u\n", ah->ah_opmode);
494 ah->ah_opmode);
495 ahp->ah_stats.ast_ani_reset++; 494 ahp->ah_stats.ast_ani_reset++;
496 495
497 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); 496 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
@@ -581,9 +580,9 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
581 phyCnt2 < aniState->cckPhyErrBase) { 580 phyCnt2 < aniState->cckPhyErrBase) {
582 if (phyCnt1 < aniState->ofdmPhyErrBase) { 581 if (phyCnt1 < aniState->ofdmPhyErrBase) {
583 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 582 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
584 "%s: phyCnt1 0x%x, resetting " 583 "phyCnt1 0x%x, resetting "
585 "counter value to 0x%x\n", 584 "counter value to 0x%x\n",
586 __func__, phyCnt1, 585 phyCnt1,
587 aniState->ofdmPhyErrBase); 586 aniState->ofdmPhyErrBase);
588 REG_WRITE(ah, AR_PHY_ERR_1, 587 REG_WRITE(ah, AR_PHY_ERR_1,
589 aniState->ofdmPhyErrBase); 588 aniState->ofdmPhyErrBase);
@@ -592,9 +591,9 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah,
592 } 591 }
593 if (phyCnt2 < aniState->cckPhyErrBase) { 592 if (phyCnt2 < aniState->cckPhyErrBase) {
594 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 593 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
595 "%s: phyCnt2 0x%x, resetting " 594 "phyCnt2 0x%x, resetting "
596 "counter value to 0x%x\n", 595 "counter value to 0x%x\n",
597 __func__, phyCnt2, 596 phyCnt2,
598 aniState->cckPhyErrBase); 597 aniState->cckPhyErrBase);
599 REG_WRITE(ah, AR_PHY_ERR_2, 598 REG_WRITE(ah, AR_PHY_ERR_2,
600 aniState->cckPhyErrBase); 599 aniState->cckPhyErrBase);
@@ -692,8 +691,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
692 691
693 if (cycles == 0 || cycles > cc) { 692 if (cycles == 0 || cycles > cc) {
694 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 693 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
695 "%s: cycle counter wrap. ExtBusy = 0\n", 694 "cycle counter wrap. ExtBusy = 0\n");
696 __func__);
697 good = 0; 695 good = 0;
698 } else { 696 } else {
699 u32 cc_d = cc - cycles; 697 u32 cc_d = cc - cycles;
diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c
index e80d9b9b61a0..88fbfe5bb7b5 100644
--- a/drivers/net/wireless/ath9k/beacon.c
+++ b/drivers/net/wireless/ath9k/beacon.c
@@ -41,8 +41,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
41 41
42 if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) { 42 if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) {
43 DPRINTF(sc, ATH_DBG_FATAL, 43 DPRINTF(sc, ATH_DBG_FATAL,
44 "%s: unable to update h/w beacon queue parameters\n", 44 "unable to update h/w beacon queue parameters\n");
45 __func__);
46 return 0; 45 return 0;
47 } else { 46 } else {
48 ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 47 ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
@@ -53,8 +52,8 @@ static int ath_beaconq_config(struct ath_softc *sc)
53static void ath_bstuck_process(struct ath_softc *sc) 52static void ath_bstuck_process(struct ath_softc *sc)
54{ 53{
55 DPRINTF(sc, ATH_DBG_BEACON, 54 DPRINTF(sc, ATH_DBG_BEACON,
56 "%s: stuck beacon; resetting (bmiss count %u)\n", 55 "stuck beacon; resetting (bmiss count %u)\n",
57 __func__, sc->sc_bmisscount); 56 sc->sc_bmisscount);
58 ath_reset(sc, false); 57 ath_reset(sc, false);
59} 58}
60 59
@@ -76,8 +75,7 @@ static void ath_beacon_setup(struct ath_softc *sc,
76 int ctsrate = 0; 75 int ctsrate = 0;
77 int ctsduration = 0; 76 int ctsduration = 0;
78 77
79 DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n", 78 DPRINTF(sc, ATH_DBG_BEACON, "m %p len %u\n", skb, skb->len);
80 __func__, skb, skb->len);
81 79
82 /* setup descriptors */ 80 /* setup descriptors */
83 ds = bf->bf_desc; 81 ds = bf->bf_desc;
@@ -158,8 +156,8 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
158 cabq = sc->sc_cabq; 156 cabq = sc->sc_cabq;
159 157
160 if (avp->av_bcbuf == NULL) { 158 if (avp->av_bcbuf == NULL) {
161 DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", 159 DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n",
162 __func__, avp, avp->av_bcbuf); 160 avp, avp->av_bcbuf);
163 return NULL; 161 return NULL;
164 } 162 }
165 163
@@ -216,7 +214,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id)
216 if (sc->sc_nvaps > 1) { 214 if (sc->sc_nvaps > 1) {
217 ath_tx_draintxq(sc, cabq, false); 215 ath_tx_draintxq(sc, cabq, false);
218 DPRINTF(sc, ATH_DBG_BEACON, 216 DPRINTF(sc, ATH_DBG_BEACON,
219 "%s: flush previous cabq traffic\n", __func__); 217 "flush previous cabq traffic\n");
220 } 218 }
221 } 219 }
222 220
@@ -253,8 +251,8 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
253 avp = (void *)vif->drv_priv; 251 avp = (void *)vif->drv_priv;
254 252
255 if (avp->av_bcbuf == NULL) { 253 if (avp->av_bcbuf == NULL) {
256 DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", 254 DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n",
257 __func__, avp, avp != NULL ? avp->av_bcbuf : NULL); 255 avp, avp != NULL ? avp->av_bcbuf : NULL);
258 return; 256 return;
259 } 257 }
260 bf = avp->av_bcbuf; 258 bf = avp->av_bcbuf;
@@ -266,7 +264,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id)
266 /* NB: caller is known to have already stopped tx dma */ 264 /* NB: caller is known to have already stopped tx dma */
267 ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 265 ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
268 ath9k_hw_txstart(ah, sc->sc_bhalq); 266 ath9k_hw_txstart(ah, sc->sc_bhalq);
269 DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__, 267 DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
270 sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); 268 sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc);
271} 269}
272 270
@@ -351,8 +349,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
351 */ 349 */
352 skb = ieee80211_beacon_get(sc->hw, vif); 350 skb = ieee80211_beacon_get(sc->hw, vif);
353 if (skb == NULL) { 351 if (skb == NULL) {
354 DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n", 352 DPRINTF(sc, ATH_DBG_BEACON, "cannot get skb\n");
355 __func__);
356 return -ENOMEM; 353 return -ENOMEM;
357 } 354 }
358 355
@@ -388,8 +385,7 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id)
388 val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */ 385 val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */
389 386
390 DPRINTF(sc, ATH_DBG_BEACON, 387 DPRINTF(sc, ATH_DBG_BEACON,
391 "%s: %s beacons, bslot %d intval %u tsfadjust %llu\n", 388 "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
392 __func__, "stagger",
393 avp->av_bslot, intval, (unsigned long long)tsfadjust); 389 avp->av_bslot, intval, (unsigned long long)tsfadjust);
394 390
395 hdr = (struct ieee80211_hdr *)skb->data; 391 hdr = (struct ieee80211_hdr *)skb->data;
@@ -468,40 +464,39 @@ void ath9k_beacon_tasklet(unsigned long data)
468 if (sc->sc_bmisscount < BSTUCK_THRESH) { 464 if (sc->sc_bmisscount < BSTUCK_THRESH) {
469 if (sc->sc_flags & SC_OP_NO_RESET) { 465 if (sc->sc_flags & SC_OP_NO_RESET) {
470 DPRINTF(sc, ATH_DBG_BEACON, 466 DPRINTF(sc, ATH_DBG_BEACON,
471 "%s: missed %u consecutive beacons\n", 467 "missed %u consecutive beacons\n",
472 __func__, sc->sc_bmisscount); 468 sc->sc_bmisscount);
473 if (show_cycles) { 469 if (show_cycles) {
474 /* 470 /*
475 * Display cycle counter stats from HW 471 * Display cycle counter stats from HW
476 * to aide in debug of stickiness. 472 * to aide in debug of stickiness.
477 */ 473 */
478 DPRINTF(sc, ATH_DBG_BEACON, 474 DPRINTF(sc, ATH_DBG_BEACON,
479 "%s: busy times: rx_clear=%d, " 475 "busy times: rx_clear=%d, "
480 "rx_frame=%d, tx_frame=%d\n", 476 "rx_frame=%d, tx_frame=%d\n",
481 __func__, rx_clear, rx_frame, 477 rx_clear, rx_frame,
482 tx_frame); 478 tx_frame);
483 } else { 479 } else {
484 DPRINTF(sc, ATH_DBG_BEACON, 480 DPRINTF(sc, ATH_DBG_BEACON,
485 "%s: unable to obtain " 481 "unable to obtain "
486 "busy times\n", __func__); 482 "busy times\n");
487 } 483 }
488 } else { 484 } else {
489 DPRINTF(sc, ATH_DBG_BEACON, 485 DPRINTF(sc, ATH_DBG_BEACON,
490 "%s: missed %u consecutive beacons\n", 486 "missed %u consecutive beacons\n",
491 __func__, sc->sc_bmisscount); 487 sc->sc_bmisscount);
492 } 488 }
493 } else if (sc->sc_bmisscount >= BSTUCK_THRESH) { 489 } else if (sc->sc_bmisscount >= BSTUCK_THRESH) {
494 if (sc->sc_flags & SC_OP_NO_RESET) { 490 if (sc->sc_flags & SC_OP_NO_RESET) {
495 if (sc->sc_bmisscount == BSTUCK_THRESH) { 491 if (sc->sc_bmisscount == BSTUCK_THRESH) {
496 DPRINTF(sc, ATH_DBG_BEACON, 492 DPRINTF(sc, ATH_DBG_BEACON,
497 "%s: beacon is officially " 493 "beacon is officially "
498 "stuck\n", __func__); 494 "stuck\n");
499 ath9k_hw_dmaRegDump(ah); 495 ath9k_hw_dmaRegDump(ah);
500 } 496 }
501 } else { 497 } else {
502 DPRINTF(sc, ATH_DBG_BEACON, 498 DPRINTF(sc, ATH_DBG_BEACON,
503 "%s: beacon is officially stuck\n", 499 "beacon is officially stuck\n");
504 __func__);
505 ath_bstuck_process(sc); 500 ath_bstuck_process(sc);
506 } 501 }
507 } 502 }
@@ -511,12 +506,12 @@ void ath9k_beacon_tasklet(unsigned long data)
511 if (sc->sc_bmisscount != 0) { 506 if (sc->sc_bmisscount != 0) {
512 if (sc->sc_flags & SC_OP_NO_RESET) { 507 if (sc->sc_flags & SC_OP_NO_RESET) {
513 DPRINTF(sc, ATH_DBG_BEACON, 508 DPRINTF(sc, ATH_DBG_BEACON,
514 "%s: resume beacon xmit after %u misses\n", 509 "resume beacon xmit after %u misses\n",
515 __func__, sc->sc_bmisscount); 510 sc->sc_bmisscount);
516 } else { 511 } else {
517 DPRINTF(sc, ATH_DBG_BEACON, 512 DPRINTF(sc, ATH_DBG_BEACON,
518 "%s: resume beacon xmit after %u misses\n", 513 "resume beacon xmit after %u misses\n",
519 __func__, sc->sc_bmisscount); 514 sc->sc_bmisscount);
520 } 515 }
521 sc->sc_bmisscount = 0; 516 sc->sc_bmisscount = 0;
522 } 517 }
@@ -536,8 +531,8 @@ void ath9k_beacon_tasklet(unsigned long data)
536 if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF]; 531 if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF];
537 532
538 DPRINTF(sc, ATH_DBG_BEACON, 533 DPRINTF(sc, ATH_DBG_BEACON,
539 "%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n", 534 "slot %d [tsf %llu tsftu %u intval %u] if_id %d\n",
540 __func__, slot, (unsigned long long)tsf, tsftu, 535 slot, (unsigned long long)tsf, tsftu,
541 intval, if_id); 536 intval, if_id);
542 537
543 bfaddr = 0; 538 bfaddr = 0;
@@ -580,8 +575,7 @@ void ath9k_beacon_tasklet(unsigned long data)
580 */ 575 */
581 if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) { 576 if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) {
582 DPRINTF(sc, ATH_DBG_FATAL, 577 DPRINTF(sc, ATH_DBG_FATAL,
583 "%s: beacon queue %u did not stop?\n", 578 "beacon queue %u did not stop?\n", sc->sc_bhalq);
584 __func__, sc->sc_bhalq);
585 /* NB: the HAL still stops DMA, so proceed */ 579 /* NB: the HAL still stops DMA, so proceed */
586 } 580 }
587 581
@@ -658,8 +652,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
658 else if (intval) /* NB: can be 0 for monitor mode */ 652 else if (intval) /* NB: can be 0 for monitor mode */
659 nexttbtt = roundup(nexttbtt, intval); 653 nexttbtt = roundup(nexttbtt, intval);
660 654
661 DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 655 DPRINTF(sc, ATH_DBG_BEACON, "nexttbtt %u intval %u (%u)\n",
662 __func__, nexttbtt, intval, conf.beacon_interval); 656 nexttbtt, intval, conf.beacon_interval);
663 657
664 /* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */ 658 /* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */
665 if (sc->sc_ah->ah_opmode == ATH9K_M_STA) { 659 if (sc->sc_ah->ah_opmode == ATH9K_M_STA) {
@@ -746,7 +740,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
746 bs.bs_sleepduration = bs.bs_dtimperiod; 740 bs.bs_sleepduration = bs.bs_dtimperiod;
747 741
748 DPRINTF(sc, ATH_DBG_BEACON, 742 DPRINTF(sc, ATH_DBG_BEACON,
749 "%s: tsf %llu " 743 "tsf %llu "
750 "tsf:tu %u " 744 "tsf:tu %u "
751 "intval %u " 745 "intval %u "
752 "nexttbtt %u " 746 "nexttbtt %u "
@@ -758,7 +752,6 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
758 "maxdur %u " 752 "maxdur %u "
759 "next %u " 753 "next %u "
760 "timoffset %u\n", 754 "timoffset %u\n",
761 __func__,
762 (unsigned long long)tsf, tsftu, 755 (unsigned long long)tsf, tsftu,
763 bs.bs_intval, 756 bs.bs_intval,
764 bs.bs_nexttbtt, 757 bs.bs_nexttbtt,
@@ -798,8 +791,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id)
798 } 791 }
799#undef FUDGE 792#undef FUDGE
800 DPRINTF(sc, ATH_DBG_BEACON, 793 DPRINTF(sc, ATH_DBG_BEACON,
801 "%s: IBSS nexttbtt %u intval %u (%u)\n", 794 "IBSS nexttbtt %u intval %u (%u)\n",
802 __func__, nexttbtt, 795 nexttbtt,
803 intval & ~ATH9K_BEACON_RESET_TSF, 796 intval & ~ATH9K_BEACON_RESET_TSF,
804 conf.beacon_interval); 797 conf.beacon_interval);
805 798
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 0e214f746a96..51c8a3ce4e60 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -31,11 +31,11 @@ static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
31static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf) 31static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf)
32{ 32{
33 if (nf > ATH9K_NF_TOO_LOW) { 33 if (nf > ATH9K_NF_TOO_LOW) {
34 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, 34 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
35 "%s: noise floor value detected (%d) is " 35 "noise floor value detected (%d) is "
36 "lower than what we think is a " 36 "lower than what we think is a "
37 "reasonable value (%d)\n", 37 "reasonable value (%d)\n",
38 __func__, nf, ATH9K_NF_TOO_LOW); 38 nf, ATH9K_NF_TOO_LOW);
39 return false; 39 return false;
40 } 40 }
41 return true; 41 return true;
@@ -116,7 +116,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
116 116
117 if (nf & 0x100) 117 if (nf & 0x100)
118 nf = 0 - ((nf ^ 0x1ff) + 1); 118 nf = 0 - ((nf ^ 0x1ff) + 1);
119 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, 119 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
120 "NF calibrated [ctl] [chain 1] is %d\n", nf); 120 "NF calibrated [ctl] [chain 1] is %d\n", nf);
121 nfarray[1] = nf; 121 nfarray[1] = nf;
122 122
@@ -125,7 +125,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
125 AR_PHY_CH2_MINCCA_PWR); 125 AR_PHY_CH2_MINCCA_PWR);
126 if (nf & 0x100) 126 if (nf & 0x100)
127 nf = 0 - ((nf ^ 0x1ff) + 1); 127 nf = 0 - ((nf ^ 0x1ff) + 1);
128 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, 128 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
129 "NF calibrated [ctl] [chain 2] is %d\n", nf); 129 "NF calibrated [ctl] [chain 2] is %d\n", nf);
130 nfarray[2] = nf; 130 nfarray[2] = nf;
131 } 131 }
@@ -139,7 +139,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
139 139
140 if (nf & 0x100) 140 if (nf & 0x100)
141 nf = 0 - ((nf ^ 0x1ff) + 1); 141 nf = 0 - ((nf ^ 0x1ff) + 1);
142 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, 142 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
143 "NF calibrated [ext] [chain 0] is %d\n", nf); 143 "NF calibrated [ext] [chain 0] is %d\n", nf);
144 nfarray[3] = nf; 144 nfarray[3] = nf;
145 145
@@ -161,7 +161,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah,
161 AR_PHY_CH2_EXT_MINCCA_PWR); 161 AR_PHY_CH2_EXT_MINCCA_PWR);
162 if (nf & 0x100) 162 if (nf & 0x100)
163 nf = 0 - ((nf ^ 0x1ff) + 1); 163 nf = 0 - ((nf ^ 0x1ff) + 1);
164 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, 164 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
165 "NF calibrated [ext] [chain 2] is %d\n", nf); 165 "NF calibrated [ext] [chain 2] is %d\n", nf);
166 nfarray[5] = nf; 166 nfarray[5] = nf;
167 } 167 }
@@ -187,8 +187,7 @@ static bool getNoiseFloorThresh(struct ath_hal *ah,
187 break; 187 break;
188 default: 188 default:
189 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 189 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
190 "%s: invalid channel flags 0x%x\n", __func__, 190 "invalid channel flags 0x%x\n", chan->channelFlags);
191 chan->channelFlags);
192 return false; 191 return false;
193 } 192 }
194 193
@@ -206,24 +205,22 @@ static void ath9k_hw_setup_calibration(struct ath_hal *ah,
206 case IQ_MISMATCH_CAL: 205 case IQ_MISMATCH_CAL:
207 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 206 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
208 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 207 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
209 "%s: starting IQ Mismatch Calibration\n", 208 "starting IQ Mismatch Calibration\n");
210 __func__);
211 break; 209 break;
212 case ADC_GAIN_CAL: 210 case ADC_GAIN_CAL:
213 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); 211 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
214 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 212 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
215 "%s: starting ADC Gain Calibration\n", __func__); 213 "starting ADC Gain Calibration\n");
216 break; 214 break;
217 case ADC_DC_CAL: 215 case ADC_DC_CAL:
218 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); 216 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
219 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 217 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
220 "%s: starting ADC DC Calibration\n", __func__); 218 "starting ADC DC Calibration\n");
221 break; 219 break;
222 case ADC_DC_INIT_CAL: 220 case ADC_DC_INIT_CAL:
223 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); 221 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
224 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 222 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
225 "%s: starting Init ADC DC Calibration\n", 223 "starting Init ADC DC Calibration\n");
226 __func__);
227 break; 224 break;
228 } 225 }
229 226
@@ -594,16 +591,16 @@ void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
594 591
595 if (ichan == NULL) { 592 if (ichan == NULL) {
596 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 593 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
597 "%s: invalid channel %u/0x%x; no mapping\n", 594 "invalid channel %u/0x%x; no mapping\n",
598 __func__, chan->channel, chan->channelFlags); 595 chan->channel, chan->channelFlags);
599 return; 596 return;
600 } 597 }
601 598
602 599
603 if (currCal->calState != CAL_DONE) { 600 if (currCal->calState != CAL_DONE) {
604 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 601 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
605 "%s: Calibration state incorrect, %d\n", 602 "Calibration state incorrect, %d\n",
606 __func__, currCal->calState); 603 currCal->calState);
607 return; 604 return;
608 } 605 }
609 606
@@ -612,8 +609,8 @@ void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
612 return; 609 return;
613 610
614 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 611 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
615 "%s: Resetting Cal %d state for channel %u/0x%x\n", 612 "Resetting Cal %d state for channel %u/0x%x\n",
616 __func__, currCal->calData->calType, chan->channel, 613 currCal->calData->calType, chan->channel,
617 chan->channelFlags); 614 chan->channelFlags);
618 615
619 ichan->CalValid &= ~currCal->calData->calType; 616 ichan->CalValid &= ~currCal->calData->calType;
@@ -705,8 +702,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah,
705 chan->channelFlags &= (~CHANNEL_CW_INT); 702 chan->channelFlags &= (~CHANNEL_CW_INT);
706 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 703 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
707 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 704 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
708 "%s: NF did not complete in calibration window\n", 705 "NF did not complete in calibration window\n");
709 __func__);
710 nf = 0; 706 nf = 0;
711 chan->rawNoiseFloor = nf; 707 chan->rawNoiseFloor = nf;
712 return chan->rawNoiseFloor; 708 return chan->rawNoiseFloor;
@@ -716,8 +712,8 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah,
716 if (getNoiseFloorThresh(ah, chan, &nfThresh) 712 if (getNoiseFloorThresh(ah, chan, &nfThresh)
717 && nf > nfThresh) { 713 && nf > nfThresh) {
718 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 714 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
719 "%s: noise floor failed detected; " 715 "noise floor failed detected; "
720 "detected %d, threshold %d\n", __func__, 716 "detected %d, threshold %d\n",
721 nf, nfThresh); 717 nf, nfThresh);
722 chan->channelFlags |= CHANNEL_CW_INT; 718 chan->channelFlags |= CHANNEL_CW_INT;
723 } 719 }
@@ -759,9 +755,9 @@ s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan)
759 755
760 ichan = ath9k_regd_check_channel(ah, chan); 756 ichan = ath9k_regd_check_channel(ah, chan);
761 if (ichan == NULL) { 757 if (ichan == NULL) {
762 DPRINTF(ah->ah_sc, ATH_DBG_NF_CAL, 758 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
763 "%s: invalid channel %u/0x%x; no mapping\n", 759 "invalid channel %u/0x%x; no mapping\n",
764 __func__, chan->channel, chan->channelFlags); 760 chan->channel, chan->channelFlags);
765 return ATH_DEFAULT_NOISE_FLOOR; 761 return ATH_DEFAULT_NOISE_FLOOR;
766 } 762 }
767 if (ichan->rawNoiseFloor == 0) { 763 if (ichan->rawNoiseFloor == 0) {
@@ -788,8 +784,8 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
788 784
789 if (ichan == NULL) { 785 if (ichan == NULL) {
790 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 786 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
791 "%s: invalid channel %u/0x%x; no mapping\n", 787 "invalid channel %u/0x%x; no mapping\n",
792 __func__, chan->channel, chan->channelFlags); 788 chan->channel, chan->channelFlags);
793 return false; 789 return false;
794 } 790 }
795 791
@@ -834,8 +830,8 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
834 830
835 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { 831 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
836 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 832 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
837 "%s: offset calibration failed to complete in 1ms; " 833 "offset calibration failed to complete in 1ms; "
838 "noisy environment?\n", __func__); 834 "noisy environment?\n");
839 return false; 835 return false;
840 } 836 }
841 837
@@ -850,22 +846,19 @@ bool ath9k_hw_init_cal(struct ath_hal *ah,
850 INIT_CAL(&ahp->ah_adcGainCalData); 846 INIT_CAL(&ahp->ah_adcGainCalData);
851 INSERT_CAL(ahp, &ahp->ah_adcGainCalData); 847 INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
852 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 848 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
853 "%s: enabling ADC Gain Calibration.\n", 849 "enabling ADC Gain Calibration.\n");
854 __func__);
855 } 850 }
856 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) { 851 if (ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
857 INIT_CAL(&ahp->ah_adcDcCalData); 852 INIT_CAL(&ahp->ah_adcDcCalData);
858 INSERT_CAL(ahp, &ahp->ah_adcDcCalData); 853 INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
859 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 854 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
860 "%s: enabling ADC DC Calibration.\n", 855 "enabling ADC DC Calibration.\n");
861 __func__);
862 } 856 }
863 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) { 857 if (ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
864 INIT_CAL(&ahp->ah_iqCalData); 858 INIT_CAL(&ahp->ah_iqCalData);
865 INSERT_CAL(ahp, &ahp->ah_iqCalData); 859 INSERT_CAL(ahp, &ahp->ah_iqCalData);
866 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 860 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE,
867 "%s: enabling IQ Calibration.\n", 861 "enabling IQ Calibration.\n");
868 __func__);
869 } 862 }
870 863
871 ahp->ah_cal_list_curr = ahp->ah_cal_list; 864 ahp->ah_cal_list_curr = ahp->ah_cal_list;
diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h
index f0c54377dfe6..ae32b2c4ef16 100644
--- a/drivers/net/wireless/ath9k/core.h
+++ b/drivers/net/wireless/ath9k/core.h
@@ -84,52 +84,33 @@ struct ath_node;
84 84
85static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; 85static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
86 86
87/*************/
88/* Debugging */
89/*************/
90
91enum ATH_DEBUG { 87enum ATH_DEBUG {
92 ATH_DBG_RESET = 0x00000001, 88 ATH_DBG_RESET = 0x00000001,
93 ATH_DBG_PHY_IO = 0x00000002, 89 ATH_DBG_REG_IO = 0x00000002,
94 ATH_DBG_REG_IO = 0x00000004, 90 ATH_DBG_QUEUE = 0x00000004,
95 ATH_DBG_QUEUE = 0x00000008, 91 ATH_DBG_EEPROM = 0x00000008,
96 ATH_DBG_EEPROM = 0x00000010, 92 ATH_DBG_CALIBRATE = 0x00000010,
97 ATH_DBG_NF_CAL = 0x00000020, 93 ATH_DBG_CHANNEL = 0x00000020,
98 ATH_DBG_CALIBRATE = 0x00000040, 94 ATH_DBG_INTERRUPT = 0x00000040,
99 ATH_DBG_CHANNEL = 0x00000080, 95 ATH_DBG_REGULATORY = 0x00000080,
100 ATH_DBG_INTERRUPT = 0x00000100, 96 ATH_DBG_ANI = 0x00000100,
101 ATH_DBG_REGULATORY = 0x00000200, 97 ATH_DBG_POWER_MGMT = 0x00000200,
102 ATH_DBG_ANI = 0x00000400, 98 ATH_DBG_XMIT = 0x00000400,
103 ATH_DBG_POWER_MGMT = 0x00000800, 99 ATH_DBG_BEACON = 0x00001000,
104 ATH_DBG_XMIT = 0x00001000, 100 ATH_DBG_CONFIG = 0x00002000,
105 ATH_DBG_BEACON = 0x00002000, 101 ATH_DBG_KEYCACHE = 0x00004000,
106 ATH_DBG_RATE = 0x00004000, 102 ATH_DBG_FATAL = 0x00008000,
107 ATH_DBG_CONFIG = 0x00008000,
108 ATH_DBG_KEYCACHE = 0x00010000,
109 ATH_DBG_AGGR = 0x00020000,
110 ATH_DBG_FATAL = 0x00040000,
111 ATH_DBG_ANY = 0xffffffff 103 ATH_DBG_ANY = 0xffffffff
112}; 104};
113 105
114#define DBG_DEFAULT (ATH_DBG_FATAL) 106#define DBG_DEFAULT (ATH_DBG_FATAL)
115 107
116#define DPRINTF(sc, _m, _fmt, ...) do { \
117 if (sc->sc_debug & (_m)) \
118 printk(_fmt , ##__VA_ARGS__); \
119 } while (0)
120
121/***************************/
122/* Load-time Configuration */
123/***************************/
124
125/* Per-instance load-time (note: NOT run-time) configurations
126 * for Atheros Device */
127struct ath_config { 108struct ath_config {
128 u32 ath_aggr_prot; 109 u32 ath_aggr_prot;
129 u16 txpowlimit; 110 u16 txpowlimit;
130 u16 txpowlimit_override; 111 u16 txpowlimit_override;
131 u8 cabqReadytime; /* Cabq Readytime % */ 112 u8 cabqReadytime;
132 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */ 113 u8 swBeaconProcess;
133}; 114};
134 115
135/*************************/ 116/*************************/
@@ -160,14 +141,13 @@ enum buffer_type {
160}; 141};
161 142
162struct ath_buf_state { 143struct ath_buf_state {
163 int bfs_nframes; /* # frames in aggregate */ 144 int bfs_nframes; /* # frames in aggregate */
164 u16 bfs_al; /* length of aggregate */ 145 u16 bfs_al; /* length of aggregate */
165 u16 bfs_frmlen; /* length of frame */ 146 u16 bfs_frmlen; /* length of frame */
166 int bfs_seqno; /* sequence number */ 147 int bfs_seqno; /* sequence number */
167 int bfs_tidno; /* tid of this frame */ 148 int bfs_tidno; /* tid of this frame */
168 int bfs_retries; /* current retries */ 149 int bfs_retries; /* current retries */
169 u32 bf_type; /* BUF_* (enum buffer_type) */ 150 u32 bf_type; /* BUF_* (enum buffer_type) */
170 /* key type use to encrypt this frame */
171 u32 bfs_keyix; 151 u32 bfs_keyix;
172 enum ath9k_key_type bfs_keytype; 152 enum ath9k_key_type bfs_keytype;
173}; 153};
@@ -213,13 +193,6 @@ struct ath_buf {
213 dma_addr_t bf_dmacontext; 193 dma_addr_t bf_dmacontext;
214}; 194};
215 195
216/*
217 * reset the rx buffer.
218 * any new fields added to the athbuf and require
219 * reset need to be added to this macro.
220 * currently bf_status is the only one requires that
221 * requires reset.
222 */
223#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0) 196#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
224 197
225/* hw processing complete, desc processed by hal */ 198/* hw processing complete, desc processed by hal */
@@ -263,11 +236,8 @@ void ath_rx_cleanup(struct ath_softc *sc);
263int ath_rx_tasklet(struct ath_softc *sc, int flush); 236int ath_rx_tasklet(struct ath_softc *sc, int flush);
264 237
265#define ATH_TXBUF 512 238#define ATH_TXBUF 512
266/* max number of transmit attempts (tries) */
267#define ATH_TXMAXTRY 13 239#define ATH_TXMAXTRY 13
268/* max number of 11n transmit attempts (tries) */
269#define ATH_11N_TXMAXTRY 10 240#define ATH_11N_TXMAXTRY 10
270/* max number of tries for management and control frames */
271#define ATH_MGT_TXMAXTRY 4 241#define ATH_MGT_TXMAXTRY 4
272#define WME_BA_BMP_SIZE 64 242#define WME_BA_BMP_SIZE 64
273#define WME_MAX_BA WME_BA_BMP_SIZE 243#define WME_MAX_BA WME_BA_BMP_SIZE
@@ -279,22 +249,12 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush);
279 WME_AC_VO) 249 WME_AC_VO)
280 250
281 251
282/* Wireless Multimedia Extension Defines */ 252#define WME_AC_BE 0
283#define WME_AC_BE 0 /* best effort */ 253#define WME_AC_BK 1
284#define WME_AC_BK 1 /* background */ 254#define WME_AC_VI 2
285#define WME_AC_VI 2 /* video */ 255#define WME_AC_VO 3
286#define WME_AC_VO 3 /* voice */ 256#define WME_NUM_AC 4
287#define WME_NUM_AC 4
288 257
289/*
290 * Data transmit queue state. One of these exists for each
291 * hardware transmit queue. Packets sent to us from above
292 * are assigned to queues based on their priority. Not all
293 * devices support a complete set of hardware transmit queues.
294 * For those devices the array sc_ac2q will map multiple
295 * priorities to fewer hardware queues (typically all to one
296 * hardware queue).
297 */
298struct ath_txq { 258struct ath_txq {
299 u32 axq_qnum; /* hardware q number */ 259 u32 axq_qnum; /* hardware q number */
300 u32 *axq_link; /* link ptr in last TX desc */ 260 u32 *axq_link; /* link ptr in last TX desc */
@@ -372,14 +332,15 @@ struct ath_xmit_status {
372#define ATH_TX_BAR 0x04 332#define ATH_TX_BAR 0x04
373}; 333};
374 334
335/* All RSSI values are noise floor adjusted */
375struct ath_tx_stat { 336struct ath_tx_stat {
376 int rssi; /* RSSI (noise floor ajusted) */ 337 int rssi;
377 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 338 int rssictl[ATH_MAX_ANTENNA];
378 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */ 339 int rssiextn[ATH_MAX_ANTENNA];
379 int rateieee; /* data rate xmitted (IEEE rate code) */ 340 int rateieee;
380 int rateKbps; /* data rate xmitted (Kbps) */ 341 int rateKbps;
381 int ratecode; /* phy rate code */ 342 int ratecode;
382 int flags; /* validity flags */ 343 int flags;
383/* if any of ctl,extn chain rssis are valid */ 344/* if any of ctl,extn chain rssis are valid */
384#define ATH_TX_CHAIN_RSSI_VALID 0x01 345#define ATH_TX_CHAIN_RSSI_VALID 0x01
385/* if extn chain rssis are valid */ 346/* if extn chain rssis are valid */
@@ -415,7 +376,7 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
415/**********************/ 376/**********************/
416 377
417#define ADDBA_EXCHANGE_ATTEMPTS 10 378#define ADDBA_EXCHANGE_ATTEMPTS 10
418#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */ 379#define ATH_AGGR_DELIM_SZ 4
419#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ 380#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
420/* number of delimiters for encryption padding */ 381/* number of delimiters for encryption padding */
421#define ATH_AGGR_ENCRYPTDELIM 10 382#define ATH_AGGR_ENCRYPTDELIM 10
@@ -466,10 +427,9 @@ struct aggr_rifs_param {
466 427
467/* Per-node aggregation state */ 428/* Per-node aggregation state */
468struct ath_node_aggr { 429struct ath_node_aggr {
469 struct ath_atx tx; /* node transmit state */ 430 struct ath_atx tx;
470}; 431};
471 432
472/* driver-specific node state */
473struct ath_node { 433struct ath_node {
474 struct ath_softc *an_sc; 434 struct ath_softc *an_sc;
475 struct ath_node_aggr an_aggr; 435 struct ath_node_aggr an_aggr;
@@ -500,12 +460,11 @@ void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid
500#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \ 460#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
501 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02)) 461 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
502 462
503/* driver-specific vap state */
504struct ath_vap { 463struct ath_vap {
505 int av_bslot; /* beacon slot index */ 464 int av_bslot;
506 enum ath9k_opmode av_opmode; /* VAP operational mode */ 465 enum ath9k_opmode av_opmode;
507 struct ath_buf *av_bcbuf; /* beacon buffer */ 466 struct ath_buf *av_bcbuf;
508 struct ath_tx_control av_btxctl; /* txctl information for beacon */ 467 struct ath_tx_control av_btxctl;
509}; 468};
510 469
511/*******************/ 470/*******************/
@@ -518,12 +477,11 @@ struct ath_vap {
518 * number of beacon intervals, the game's up. 477 * number of beacon intervals, the game's up.
519 */ 478 */
520#define BSTUCK_THRESH (9 * ATH_BCBUF) 479#define BSTUCK_THRESH (9 * ATH_BCBUF)
521#define ATH_BCBUF 4 /* number of beacon buffers */ 480#define ATH_BCBUF 4
522#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */ 481#define ATH_DEFAULT_BINTVAL 100 /* TU */
523#define ATH_DEFAULT_BMISS_LIMIT 10 482#define ATH_DEFAULT_BMISS_LIMIT 10
524#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) 483#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
525 484
526/* beacon configuration */
527struct ath_beacon_config { 485struct ath_beacon_config {
528 u16 beacon_interval; 486 u16 beacon_interval;
529 u16 listen_interval; 487 u16 listen_interval;
@@ -674,18 +632,18 @@ struct ath_softc {
674 u8 sc_tx_chainmask; 632 u8 sc_tx_chainmask;
675 u8 sc_rx_chainmask; 633 u8 sc_rx_chainmask;
676 enum ath9k_int sc_imask; 634 enum ath9k_int sc_imask;
677 enum wireless_mode sc_curmode; /* current phy mode */ 635 enum wireless_mode sc_curmode;
678 enum PROT_MODE sc_protmode; 636 enum PROT_MODE sc_protmode;
679 637
680 u8 sc_nbcnvaps; /* # of vaps sending beacons */ 638 u8 sc_nbcnvaps;
681 u16 sc_nvaps; /* # of active virtual ap's */ 639 u16 sc_nvaps;
682 struct ieee80211_vif *sc_vaps[ATH_BCBUF]; 640 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
683 641
684 u8 sc_mcastantenna; 642 u8 sc_mcastantenna;
685 u8 sc_defant; /* current default antenna */ 643 u8 sc_defant;
686 u8 sc_rxotherant; /* rx's on non-default antenna */ 644 u8 sc_rxotherant;
687 645
688 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */ 646 struct ath9k_node_stats sc_halstats;
689 enum ath9k_ht_extprotspacing sc_ht_extprotspacing; 647 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
690 enum ath9k_ht_macmode tx_chan_width; 648 enum ath9k_ht_macmode tx_chan_width;
691 649
@@ -699,22 +657,22 @@ struct ath_softc {
699 } sc_updateslot; /* slot time update fsm */ 657 } sc_updateslot; /* slot time update fsm */
700 658
701 /* Crypto */ 659 /* Crypto */
702 u32 sc_keymax; /* size of key cache */ 660 u32 sc_keymax;
703 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */ 661 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
704 u8 sc_splitmic; /* split TKIP MIC keys */ 662 u8 sc_splitmic; /* split TKIP MIC keys */
705 663
706 /* RX */ 664 /* RX */
707 struct list_head sc_rxbuf; 665 struct list_head sc_rxbuf;
708 struct ath_descdma sc_rxdma; 666 struct ath_descdma sc_rxdma;
709 int sc_rxbufsize; /* rx size based on mtu */ 667 int sc_rxbufsize;
710 u32 *sc_rxlink; /* link ptr in last RX desc */ 668 u32 *sc_rxlink;
711 669
712 /* TX */ 670 /* TX */
713 struct list_head sc_txbuf; 671 struct list_head sc_txbuf;
714 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES]; 672 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
715 struct ath_descdma sc_txdma; 673 struct ath_descdma sc_txdma;
716 u32 sc_txqsetup; 674 u32 sc_txqsetup;
717 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */ 675 int sc_haltype2q[ATH9K_WME_AC_VO+1];
718 u16 seq_no; /* TX sequence number */ 676 u16 seq_no; /* TX sequence number */
719 677
720 /* Beacon */ 678 /* Beacon */
@@ -724,13 +682,13 @@ struct ath_softc {
724 struct list_head sc_bbuf; 682 struct list_head sc_bbuf;
725 u32 sc_bhalq; 683 u32 sc_bhalq;
726 u32 sc_bmisscount; 684 u32 sc_bmisscount;
727 u32 ast_be_xmit; /* beacons transmitted */ 685 u32 ast_be_xmit;
728 u64 bc_tstamp; 686 u64 bc_tstamp;
729 687
730 /* Rate */ 688 /* Rate */
731 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; 689 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
732 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; 690 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
733 u8 sc_protrix; /* protection rate index */ 691 u8 sc_protrix;
734 692
735 /* Channel, Band */ 693 /* Channel, Band */
736 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX]; 694 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
@@ -755,6 +713,7 @@ struct ath_softc {
755 struct ath_ani sc_ani; 713 struct ath_ani sc_ani;
756}; 714};
757 715
716void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
758int ath_reset(struct ath_softc *sc, bool retry_tx); 717int ath_reset(struct ath_softc *sc, bool retry_tx);
759int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); 718int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
760int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); 719int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index 466dbce2c5f7..e180c9043df6 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -116,7 +116,7 @@ static int ath9k_hw_flash_map(struct ath_hal *ah)
116 116
117 if (!ahp->ah_cal_mem) { 117 if (!ahp->ah_cal_mem) {
118 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 118 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
119 "%s: cannot remap eeprom region \n", __func__); 119 "cannot remap eeprom region \n");
120 return -EIO; 120 return -EIO;
121 } 121 }
122 122
@@ -149,7 +149,7 @@ static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
149 149
150 if (!ath9k_hw_use_flash(ah)) { 150 if (!ath9k_hw_use_flash(ah)) {
151 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 151 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
152 "%s: Reading from EEPROM, not flash\n", __func__); 152 "Reading from EEPROM, not flash\n");
153 ar5416_eep_start_loc = 256; 153 ar5416_eep_start_loc = 256;
154 } 154 }
155 155
@@ -162,8 +162,7 @@ static bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
162 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 162 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
163 eep_data)) { 163 eep_data)) {
164 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 164 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
165 "%s: Unable to read eeprom region \n", 165 "Unable to read eeprom region \n");
166 __func__);
167 return false; 166 return false;
168 } 167 }
169 eep_data++; 168 eep_data++;
@@ -185,12 +184,11 @@ static int ath9k_hw_check_eeprom(struct ath_hal *ah)
185 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, 184 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
186 &magic)) { 185 &magic)) {
187 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 186 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
188 "%s: Reading Magic # failed\n", __func__); 187 "Reading Magic # failed\n");
189 return false; 188 return false;
190 } 189 }
191 190
192 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "%s: Read Magic = 0x%04X\n", 191 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Read Magic = 0x%04X\n", magic);
193 __func__, magic);
194 192
195 if (magic != AR5416_EEPROM_MAGIC) { 193 if (magic != AR5416_EEPROM_MAGIC) {
196 magic2 = swab16(magic); 194 magic2 = swab16(magic);
@@ -1205,11 +1203,11 @@ bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
1205 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 1203 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
1206 REG_WRITE(ah, regOffset, reg32); 1204 REG_WRITE(ah, regOffset, reg32);
1207 1205
1208 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, 1206 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1209 "PDADC (%d,%4x): %4.4x %8.8x\n", 1207 "PDADC (%d,%4x): %4.4x %8.8x\n",
1210 i, regChainOffset, regOffset, 1208 i, regChainOffset, regOffset,
1211 reg32); 1209 reg32);
1212 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, 1210 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1213 "PDADC: Chain %d | PDADC %3d Value %3d | " 1211 "PDADC: Chain %d | PDADC %3d Value %3d | "
1214 "PDADC %3d Value %3d | PDADC %3d Value %3d | " 1212 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
1215 "PDADC %3d Value %3d |\n", 1213 "PDADC %3d Value %3d |\n",
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 6eef10477896..b3f2899026d6 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -104,9 +104,10 @@ bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
104 104
105 udelay(AH_TIME_QUANTUM); 105 udelay(AH_TIME_QUANTUM);
106 } 106 }
107 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, 107
108 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 108 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
109 __func__, reg, REG_READ(ah, reg), mask, val); 109 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
110 reg, REG_READ(ah, reg), mask, val);
110 111
111 return false; 112 return false;
112} 113}
@@ -188,8 +189,8 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah,
188 } 189 }
189 break; 190 break;
190 default: 191 default:
191 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, 192 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
192 "%s: unknown phy %u (rate ix %u)\n", __func__, 193 "Unknown phy %u (rate ix %u)\n",
193 rates->info[rateix].phy, rateix); 194 rates->info[rateix].phy, rateix);
194 txTime = 0; 195 txTime = 0;
195 break; 196 break;
@@ -355,9 +356,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
355 rdData = REG_READ(ah, addr); 356 rdData = REG_READ(ah, addr);
356 if (rdData != wrData) { 357 if (rdData != wrData) {
357 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 358 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
358 "%s: address test failed " 359 "address test failed "
359 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 360 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
360 __func__, addr, wrData, rdData); 361 addr, wrData, rdData);
361 return false; 362 return false;
362 } 363 }
363 } 364 }
@@ -367,9 +368,9 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah)
367 rdData = REG_READ(ah, addr); 368 rdData = REG_READ(ah, addr);
368 if (wrData != rdData) { 369 if (wrData != rdData) {
369 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 370 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
370 "%s: address test failed " 371 "address test failed "
371 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 372 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
372 __func__, addr, wrData, rdData); 373 addr, wrData, rdData);
373 return false; 374 return false;
374 } 375 }
375 } 376 }
@@ -449,8 +450,7 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
449 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); 450 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
450 if (ahp == NULL) { 451 if (ahp == NULL) {
451 DPRINTF(sc, ATH_DBG_FATAL, 452 DPRINTF(sc, ATH_DBG_FATAL,
452 "%s: cannot allocate memory for state block\n", 453 "Cannot allocate memory for state block\n");
453 __func__);
454 *status = -ENOMEM; 454 *status = -ENOMEM;
455 return NULL; 455 return NULL;
456 } 456 }
@@ -497,8 +497,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah)
497 rfStatus = ath9k_hw_init_rf(ah, &ecode); 497 rfStatus = ath9k_hw_init_rf(ah, &ecode);
498 if (!rfStatus) { 498 if (!rfStatus) {
499 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 499 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
500 "%s: RF setup failed, status %u\n", __func__, 500 "RF setup failed, status %u\n", ecode);
501 ecode);
502 return ecode; 501 return ecode;
503 } 502 }
504 503
@@ -523,9 +522,9 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah)
523 break; 522 break;
524 default: 523 default:
525 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 524 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
526 "%s: 5G Radio Chip Rev 0x%02X is not " 525 "5G Radio Chip Rev 0x%02X is not "
527 "supported by this driver\n", 526 "supported by this driver\n",
528 __func__, ah->ah_analog5GhzRev); 527 ah->ah_analog5GhzRev);
529 return -EOPNOTSUPP; 528 return -EOPNOTSUPP;
530 } 529 }
531 530
@@ -550,7 +549,7 @@ static int ath9k_hw_init_macaddr(struct ath_hal *ah)
550 } 549 }
551 if (sum == 0 || sum == 0xffff * 3) { 550 if (sum == 0 || sum == 0xffff * 3) {
552 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 551 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
553 "%s: mac address read failed: %pM\n", __func__, 552 "mac address read failed: %pM\n",
554 ahp->ah_macaddr); 553 ahp->ah_macaddr);
555 return -EADDRNOTAVAIL; 554 return -EADDRNOTAVAIL;
556 } 555 }
@@ -612,7 +611,7 @@ static int ath9k_hw_post_attach(struct ath_hal *ah)
612 611
613 if (!ath9k_hw_chip_test(ah)) { 612 if (!ath9k_hw_chip_test(ah)) {
614 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 613 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
615 "%s: hardware self-test failed\n", __func__); 614 "hardware self-test failed\n");
616 return -ENODEV; 615 return -ENODEV;
617 } 616 }
618 617
@@ -658,15 +657,13 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
658 ahp->ah_intrMitigation = true; 657 ahp->ah_intrMitigation = true;
659 658
660 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 659 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
661 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n", 660 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
662 __func__);
663 ecode = -EIO; 661 ecode = -EIO;
664 goto bad; 662 goto bad;
665 } 663 }
666 664
667 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 665 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
668 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n", 666 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
669 __func__);
670 ecode = -EIO; 667 ecode = -EIO;
671 goto bad; 668 goto bad;
672 } 669 }
@@ -682,17 +679,16 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
682 } 679 }
683 680
684 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 681 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
685 "%s: serialize_regmode is %d\n", 682 "serialize_regmode is %d\n",
686 __func__, ah->ah_config.serialize_regmode); 683 ah->ah_config.serialize_regmode);
687 684
688 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) && 685 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
689 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) && 686 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
690 (ah->ah_macVersion != AR_SREV_VERSION_9160) && 687 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
691 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) { 688 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
692 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 689 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
693 "%s: Mac Chip Rev 0x%02x.%x is not supported by " 690 "Mac Chip Rev 0x%02x.%x is not supported by "
694 "this driver\n", __func__, 691 "this driver\n", ah->ah_macVersion, ah->ah_macRev);
695 ah->ah_macVersion, ah->ah_macRev);
696 ecode = -EOPNOTSUPP; 692 ecode = -EOPNOTSUPP;
697 goto bad; 693 goto bad;
698 } 694 }
@@ -737,7 +733,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
737 } 733 }
738 734
739 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 735 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
740 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__, 736 "This Mac Chip Rev 0x%02x.%x is \n",
741 ah->ah_macVersion, ah->ah_macRev); 737 ah->ah_macVersion, ah->ah_macRev);
742 738
743 if (AR_SREV_9280_20_OR_LATER(ah)) { 739 if (AR_SREV_9280_20_OR_LATER(ah)) {
@@ -874,7 +870,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
874#endif 870#endif
875 if (!ath9k_hw_fill_cap_info(ah)) { 871 if (!ath9k_hw_fill_cap_info(ah)) {
876 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 872 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
877 "%s:failed ath9k_hw_fill_cap_info\n", __func__); 873 "failed ath9k_hw_fill_cap_info\n");
878 ecode = -EINVAL; 874 ecode = -EINVAL;
879 goto bad; 875 goto bad;
880 } 876 }
@@ -882,8 +878,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
882 ecode = ath9k_hw_init_macaddr(ah); 878 ecode = ath9k_hw_init_macaddr(ah);
883 if (ecode != 0) { 879 if (ecode != 0) {
884 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 880 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
885 "%s: failed initializing mac address\n", 881 "failed initializing mac address\n");
886 __func__);
887 goto bad; 882 goto bad;
888 } 883 }
889 884
@@ -1080,8 +1075,7 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1080 struct ath_hal_5416 *ahp = AH5416(ah); 1075 struct ath_hal_5416 *ahp = AH5416(ah);
1081 1076
1082 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1077 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n", 1078 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1084 __func__, us);
1085 ahp->ah_acktimeout = (u32) -1; 1079 ahp->ah_acktimeout = (u32) -1;
1086 return false; 1080 return false;
1087 } else { 1081 } else {
@@ -1097,8 +1091,7 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1097 struct ath_hal_5416 *ahp = AH5416(ah); 1091 struct ath_hal_5416 *ahp = AH5416(ah);
1098 1092
1099 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1093 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1100 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n", 1094 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1101 __func__, us);
1102 ahp->ah_ctstimeout = (u32) -1; 1095 ahp->ah_ctstimeout = (u32) -1;
1103 return false; 1096 return false;
1104 } else { 1097 } else {
@@ -1115,7 +1108,7 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1115 1108
1116 if (tu > 0xFFFF) { 1109 if (tu > 0xFFFF) {
1117 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1110 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1118 "%s: bad global tx timeout %u\n", __func__, tu); 1111 "bad global tx timeout %u\n", tu);
1119 ahp->ah_globaltxtimeout = (u32) -1; 1112 ahp->ah_globaltxtimeout = (u32) -1;
1120 return false; 1113 return false;
1121 } else { 1114 } else {
@@ -1129,8 +1122,8 @@ static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1129{ 1122{
1130 struct ath_hal_5416 *ahp = AH5416(ah); 1123 struct ath_hal_5416 *ahp = AH5416(ah);
1131 1124
1132 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n", 1125 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1133 __func__, ahp->ah_miscMode); 1126 ahp->ah_miscMode);
1134 1127
1135 if (ahp->ah_miscMode != 0) 1128 if (ahp->ah_miscMode != 0)
1136 REG_WRITE(ah, AR_PCU_MISC, 1129 REG_WRITE(ah, AR_PCU_MISC,
@@ -1176,7 +1169,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1176 break; 1169 break;
1177 default: 1170 default:
1178 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 1171 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1179 "devid=0x%x not supported.\n", devid); 1172 "devid=0x%x not supported.\n", devid);
1180 ah = NULL; 1173 ah = NULL;
1181 *error = -ENXIO; 1174 *error = -ENXIO;
1182 break; 1175 break;
@@ -1355,13 +1348,13 @@ static int ath9k_hw_process_ini(struct ath_hal *ah,
1355 (u32) ah->ah_powerLimit)); 1348 (u32) ah->ah_powerLimit));
1356 if (status != 0) { 1349 if (status != 0) {
1357 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 1350 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1358 "%s: error init'ing transmit power\n", __func__); 1351 "error init'ing transmit power\n");
1359 return -EIO; 1352 return -EIO;
1360 } 1353 }
1361 1354
1362 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1355 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1363 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, 1356 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1364 "%s: ar5416SetRfRegs failed\n", __func__); 1357 "ar5416SetRfRegs failed\n");
1365 return -EIO; 1358 return -EIO;
1366 } 1359 }
1367 1360
@@ -1533,8 +1526,7 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1533 REG_WRITE(ah, (u16) (AR_RTC_RC), 0); 1526 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1534 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) { 1527 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1535 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 1528 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1536 "%s: RTC stuck in MAC reset\n", 1529 "RTC stuck in MAC reset\n");
1537 __func__);
1538 return false; 1530 return false;
1539 } 1531 }
1540 1532
@@ -1561,8 +1553,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1561 AR_RTC_STATUS, 1553 AR_RTC_STATUS,
1562 AR_RTC_STATUS_M, 1554 AR_RTC_STATUS_M,
1563 AR_RTC_STATUS_ON)) { 1555 AR_RTC_STATUS_ON)) {
1564 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n", 1556 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1565 __func__);
1566 return false; 1557 return false;
1567 } 1558 }
1568 1559
@@ -1641,9 +1632,8 @@ static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1641{ 1632{
1642 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) { 1633 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1643 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 1634 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1644 "%s: invalid channel %u/0x%x; not marked as " 1635 "invalid channel %u/0x%x; not marked as "
1645 "2GHz or 5GHz\n", __func__, chan->channel, 1636 "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
1646 chan->channelFlags);
1647 return NULL; 1637 return NULL;
1648 } 1638 }
1649 1639
@@ -1652,9 +1642,9 @@ static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1652 !IS_CHAN_HT20(chan) && 1642 !IS_CHAN_HT20(chan) &&
1653 !IS_CHAN_HT40(chan)) { 1643 !IS_CHAN_HT40(chan)) {
1654 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 1644 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1655 "%s: invalid channel %u/0x%x; not marked as " 1645 "invalid channel %u/0x%x; not marked as "
1656 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n", 1646 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1657 __func__, chan->channel, chan->channelFlags); 1647 chan->channel, chan->channelFlags);
1658 return NULL; 1648 return NULL;
1659 } 1649 }
1660 1650
@@ -1670,8 +1660,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1670 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1660 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1671 if (ath9k_hw_numtxpending(ah, qnum)) { 1661 if (ath9k_hw_numtxpending(ah, qnum)) {
1672 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 1662 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1673 "%s: Transmit frames pending on queue %d\n", 1663 "Transmit frames pending on queue %d\n", qnum);
1674 __func__, qnum);
1675 return false; 1664 return false;
1676 } 1665 }
1677 } 1666 }
@@ -1679,8 +1668,8 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1679 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1668 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1680 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1669 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1681 AR_PHY_RFBUS_GRANT_EN)) { 1670 AR_PHY_RFBUS_GRANT_EN)) {
1682 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO, 1671 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1683 "%s: Could not kill baseband RX\n", __func__); 1672 "Could not kill baseband RX\n");
1684 return false; 1673 return false;
1685 } 1674 }
1686 1675
@@ -1689,13 +1678,13 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1689 if (AR_SREV_9280_10_OR_LATER(ah)) { 1678 if (AR_SREV_9280_10_OR_LATER(ah)) {
1690 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) { 1679 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1691 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 1680 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1692 "%s: failed to set channel\n", __func__); 1681 "failed to set channel\n");
1693 return false; 1682 return false;
1694 } 1683 }
1695 } else { 1684 } else {
1696 if (!(ath9k_hw_set_channel(ah, chan))) { 1685 if (!(ath9k_hw_set_channel(ah, chan))) {
1697 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 1686 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1698 "%s: failed to set channel\n", __func__); 1687 "failed to set channel\n");
1699 return false; 1688 return false;
1700 } 1689 }
1701 } 1690 }
@@ -1707,7 +1696,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah,
1707 min((u32) MAX_RATE_POWER, 1696 min((u32) MAX_RATE_POWER,
1708 (u32) ah->ah_powerLimit)) != 0) { 1697 (u32) ah->ah_powerLimit)) != 0) {
1709 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1698 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1710 "%s: error init'ing transmit power\n", __func__); 1699 "error init'ing transmit power\n");
1711 return false; 1700 return false;
1712 } 1701 }
1713 1702
@@ -2211,8 +2200,8 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2211 2200
2212 if (ath9k_hw_check_chan(ah, chan) == NULL) { 2201 if (ath9k_hw_check_chan(ah, chan) == NULL) {
2213 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 2202 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2214 "%s: invalid channel %u/0x%x; no mapping\n", 2203 "invalid channel %u/0x%x; no mapping\n",
2215 __func__, chan->channel, chan->channelFlags); 2204 chan->channel, chan->channelFlags);
2216 ecode = -EINVAL; 2205 ecode = -EINVAL;
2217 goto bad; 2206 goto bad;
2218 } 2207 }
@@ -2254,8 +2243,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2254 ath9k_hw_mark_phy_inactive(ah); 2243 ath9k_hw_mark_phy_inactive(ah);
2255 2244
2256 if (!ath9k_hw_chip_reset(ah, chan)) { 2245 if (!ath9k_hw_chip_reset(ah, chan)) {
2257 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n", 2246 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2258 __func__);
2259 ecode = -EINVAL; 2247 ecode = -EINVAL;
2260 goto bad; 2248 goto bad;
2261 } 2249 }
@@ -2289,7 +2277,7 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2289 2277
2290 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { 2278 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2291 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 2279 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2292 "%s: error setting board options\n", __func__); 2280 "error setting board options\n");
2293 ecode = -EIO; 2281 ecode = -EIO;
2294 goto bad; 2282 goto bad;
2295 } 2283 }
@@ -2379,15 +2367,13 @@ bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2379 mask = REG_READ(ah, AR_CFG); 2367 mask = REG_READ(ah, AR_CFG);
2380 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2368 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2381 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2369 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2382 "%s CFG Byte Swap Set 0x%x\n", __func__, 2370 "CFG Byte Swap Set 0x%x\n", mask);
2383 mask);
2384 } else { 2371 } else {
2385 mask = 2372 mask =
2386 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2373 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2387 REG_WRITE(ah, AR_CFG, mask); 2374 REG_WRITE(ah, AR_CFG, mask);
2388 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2375 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2389 "%s Setting CFG 0x%x\n", __func__, 2376 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2390 REG_READ(ah, AR_CFG));
2391 } 2377 }
2392 } else { 2378 } else {
2393#ifdef __BIG_ENDIAN 2379#ifdef __BIG_ENDIAN
@@ -2412,7 +2398,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2412 2398
2413 if (entry >= ah->ah_caps.keycache_size) { 2399 if (entry >= ah->ah_caps.keycache_size) {
2414 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2400 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2415 "%s: entry %u out of range\n", __func__, entry); 2401 "entry %u out of range\n", entry);
2416 return false; 2402 return false;
2417 } 2403 }
2418 2404
@@ -2449,7 +2435,7 @@ bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2449 2435
2450 if (entry >= ah->ah_caps.keycache_size) { 2436 if (entry >= ah->ah_caps.keycache_size) {
2451 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2437 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2452 "%s: entry %u out of range\n", __func__, entry); 2438 "entry %u out of range\n", entry);
2453 return false; 2439 return false;
2454 } 2440 }
2455 2441
@@ -2485,7 +2471,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2485 2471
2486 if (entry >= pCap->keycache_size) { 2472 if (entry >= pCap->keycache_size) {
2487 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2473 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2488 "%s: entry %u out of range\n", __func__, entry); 2474 "entry %u out of range\n", entry);
2489 return false; 2475 return false;
2490 } 2476 }
2491 2477
@@ -2496,8 +2482,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2496 case ATH9K_CIPHER_AES_CCM: 2482 case ATH9K_CIPHER_AES_CCM:
2497 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2483 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2498 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2484 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2499 "%s: AES-CCM not supported by " 2485 "AES-CCM not supported by mac rev 0x%x\n",
2500 "mac rev 0x%x\n", __func__,
2501 ah->ah_macRev); 2486 ah->ah_macRev);
2502 return false; 2487 return false;
2503 } 2488 }
@@ -2508,16 +2493,14 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2508 if (ATH9K_IS_MIC_ENABLED(ah) 2493 if (ATH9K_IS_MIC_ENABLED(ah)
2509 && entry + 64 >= pCap->keycache_size) { 2494 && entry + 64 >= pCap->keycache_size) {
2510 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2495 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2511 "%s: entry %u inappropriate for TKIP\n", 2496 "entry %u inappropriate for TKIP\n", entry);
2512 __func__, entry);
2513 return false; 2497 return false;
2514 } 2498 }
2515 break; 2499 break;
2516 case ATH9K_CIPHER_WEP: 2500 case ATH9K_CIPHER_WEP:
2517 if (k->kv_len < LEN_WEP40) { 2501 if (k->kv_len < LEN_WEP40) {
2518 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2502 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2519 "%s: WEP key length %u too small\n", 2503 "WEP key length %u too small\n", k->kv_len);
2520 __func__, k->kv_len);
2521 return false; 2504 return false;
2522 } 2505 }
2523 if (k->kv_len <= LEN_WEP40) 2506 if (k->kv_len <= LEN_WEP40)
@@ -2532,8 +2515,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2532 break; 2515 break;
2533 default: 2516 default:
2534 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, 2517 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2535 "%s: cipher %u not supported\n", __func__, 2518 "cipher %u not supported\n", k->kv_type);
2536 k->kv_type);
2537 return false; 2519 return false;
2538 } 2520 }
2539 2521
@@ -2682,8 +2664,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2682 } 2664 }
2683 if (i == 0) { 2665 if (i == 0) {
2684 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2666 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2685 "%s: Failed to wakeup in %uus\n", 2667 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2686 __func__, POWER_UP_TIME / 20);
2687 return false; 2668 return false;
2688 } 2669 }
2689 } 2670 }
@@ -2705,7 +2686,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
2705 }; 2686 };
2706 int status = true, setChip = true; 2687 int status = true, setChip = true;
2707 2688
2708 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__, 2689 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2709 modes[ahp->ah_powerMode], modes[mode], 2690 modes[ahp->ah_powerMode], modes[mode],
2710 setChip ? "set chip " : ""); 2691 setChip ? "set chip " : "");
2711 2692
@@ -2722,7 +2703,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah,
2722 break; 2703 break;
2723 default: 2704 default:
2724 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, 2705 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2725 "%s: unknown power mode %u\n", __func__, mode); 2706 "Unknown power mode %u\n", mode);
2726 return false; 2707 return false;
2727 } 2708 }
2728 ahp->ah_powerMode = mode; 2709 ahp->ah_powerMode = mode;
@@ -2899,8 +2880,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2899 2880
2900 if (isr & AR_ISR_RXORN) { 2881 if (isr & AR_ISR_RXORN) {
2901 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2882 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2902 "%s: receive FIFO overrun interrupt\n", 2883 "receive FIFO overrun interrupt\n");
2903 __func__);
2904 } 2884 }
2905 2885
2906 if (!AR_SREV_9100(ah)) { 2886 if (!AR_SREV_9100(ah)) {
@@ -2926,27 +2906,23 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2926 if (fatal_int) { 2906 if (fatal_int) {
2927 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 2907 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2928 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2908 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2929 "%s: received PCI FATAL interrupt\n", 2909 "received PCI FATAL interrupt\n");
2930 __func__);
2931 } 2910 }
2932 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 2911 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2933 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2912 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2934 "%s: received PCI PERR interrupt\n", 2913 "received PCI PERR interrupt\n");
2935 __func__);
2936 } 2914 }
2937 } 2915 }
2938 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 2916 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2939 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2917 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2940 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n", 2918 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2941 __func__);
2942 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 2919 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2943 REG_WRITE(ah, AR_RC, 0); 2920 REG_WRITE(ah, AR_RC, 0);
2944 *masked |= ATH9K_INT_FATAL; 2921 *masked |= ATH9K_INT_FATAL;
2945 } 2922 }
2946 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 2923 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2947 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 2924 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2948 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n", 2925 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2949 __func__);
2950 } 2926 }
2951 2927
2952 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); 2928 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
@@ -2968,12 +2944,10 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2968 u32 mask, mask2; 2944 u32 mask, mask2;
2969 struct ath9k_hw_capabilities *pCap = &ah->ah_caps; 2945 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2970 2946
2971 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__, 2947 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2972 omask, ints);
2973 2948
2974 if (omask & ATH9K_INT_GLOBAL) { 2949 if (omask & ATH9K_INT_GLOBAL) {
2975 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n", 2950 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2976 __func__);
2977 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 2951 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2978 (void) REG_READ(ah, AR_IER); 2952 (void) REG_READ(ah, AR_IER);
2979 if (!AR_SREV_9100(ah)) { 2953 if (!AR_SREV_9100(ah)) {
@@ -3028,8 +3002,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3028 mask2 |= AR_IMR_S2_CST; 3002 mask2 |= AR_IMR_S2_CST;
3029 } 3003 }
3030 3004
3031 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__, 3005 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3032 mask);
3033 REG_WRITE(ah, AR_IMR, mask); 3006 REG_WRITE(ah, AR_IMR, mask);
3034 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 3007 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3035 AR_IMR_S2_DTIM | 3008 AR_IMR_S2_DTIM |
@@ -3049,8 +3022,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
3049 } 3022 }
3050 3023
3051 if (ints & ATH9K_INT_GLOBAL) { 3024 if (ints & ATH9K_INT_GLOBAL) {
3052 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n", 3025 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3053 __func__);
3054 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 3026 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3055 if (!AR_SREV_9100(ah)) { 3027 if (!AR_SREV_9100(ah)) {
3056 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 3028 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
@@ -3156,14 +3128,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3156 else 3128 else
3157 nextTbtt = bs->bs_nexttbtt; 3129 nextTbtt = bs->bs_nexttbtt;
3158 3130
3159 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__, 3131 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3160 bs->bs_nextdtim); 3132 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3161 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__, 3133 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3162 nextTbtt); 3134 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3163 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
3164 beaconintval);
3165 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
3166 dtimperiod);
3167 3135
3168 REG_WRITE(ah, AR_NEXT_DTIM, 3136 REG_WRITE(ah, AR_NEXT_DTIM,
3169 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3137 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
@@ -3216,8 +3184,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3216 else if (ah->ah_currentRD == 0x41) 3184 else if (ah->ah_currentRD == 0x41)
3217 ah->ah_currentRD = 0x43; 3185 ah->ah_currentRD = 0x43;
3218 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 3186 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3219 "%s: regdomain mapped to 0x%x\n", __func__, 3187 "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3220 ah->ah_currentRD);
3221 } 3188 }
3222 3189
3223 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); 3190 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
@@ -3823,8 +3790,7 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah)
3823 count++; 3790 count++;
3824 if (count > 10) { 3791 if (count > 10) {
3825 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 3792 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3826 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", 3793 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3827 __func__);
3828 break; 3794 break;
3829 } 3795 }
3830 udelay(10); 3796 udelay(10);
@@ -3849,8 +3815,7 @@ bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3849 struct ath_hal_5416 *ahp = AH5416(ah); 3815 struct ath_hal_5416 *ahp = AH5416(ah);
3850 3816
3851 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 3817 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3852 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n", 3818 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3853 __func__, us);
3854 ahp->ah_slottime = (u32) -1; 3819 ahp->ah_slottime = (u32) -1;
3855 return false; 3820 return false;
3856 } else { 3821 } else {
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
index 36955e0b1849..8d2b139818ee 100644
--- a/drivers/net/wireless/ath9k/mac.c
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -25,10 +25,10 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
25 struct ath_hal_5416 *ahp = AH5416(ah); 25 struct ath_hal_5416 *ahp = AH5416(ah);
26 26
27 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 27 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
28 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 28 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
29 __func__, ahp->ah_txOkInterruptMask, 29 ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask,
30 ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask, 30 ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask,
31 ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask); 31 ahp->ah_txUrnInterruptMask);
32 32
33 REG_WRITE(ah, AR_IMR_S0, 33 REG_WRITE(ah, AR_IMR_S0,
34 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) 34 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
@@ -126,7 +126,7 @@ bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp)
126 126
127bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) 127bool ath9k_hw_txstart(struct ath_hal *ah, u32 q)
128{ 128{
129 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); 129 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
130 130
131 REG_WRITE(ah, AR_Q_TXE, 1 << q); 131 REG_WRITE(ah, AR_Q_TXE, 1 << q);
132 132
@@ -207,9 +207,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
207 break; 207 break;
208 208
209 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 209 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
210 "%s: TSF have moved while trying to set " 210 "TSF have moved while trying to set "
211 "quiet time TSF: 0x%08x\n", 211 "quiet time TSF: 0x%08x\n", tsfLow);
212 __func__, tsfLow);
213 } 212 }
214 213
215 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); 214 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
@@ -222,9 +221,8 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q)
222 while (ath9k_hw_numtxpending(ah, q)) { 221 while (ath9k_hw_numtxpending(ah, q)) {
223 if ((--wait) == 0) { 222 if ((--wait) == 0) {
224 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 223 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
225 "%s: Failed to stop Tx DMA in 100 " 224 "Failed to stop Tx DMA in 100 "
226 "msec after killing last frame\n", 225 "msec after killing last frame\n");
227 __func__);
228 break; 226 break;
229 } 227 }
230 udelay(100); 228 udelay(100);
@@ -523,19 +521,17 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
523 struct ath9k_tx_queue_info *qi; 521 struct ath9k_tx_queue_info *qi;
524 522
525 if (q >= pCap->total_queues) { 523 if (q >= pCap->total_queues) {
526 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 524 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
527 __func__, q);
528 return false; 525 return false;
529 } 526 }
530 527
531 qi = &ahp->ah_txq[q]; 528 qi = &ahp->ah_txq[q];
532 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 529 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
533 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", 530 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
534 __func__);
535 return false; 531 return false;
536 } 532 }
537 533
538 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %p\n", __func__, qi); 534 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %p\n", qi);
539 535
540 qi->tqi_ver = qinfo->tqi_ver; 536 qi->tqi_ver = qinfo->tqi_ver;
541 qi->tqi_subtype = qinfo->tqi_subtype; 537 qi->tqi_subtype = qinfo->tqi_subtype;
@@ -593,15 +589,13 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
593 struct ath9k_tx_queue_info *qi; 589 struct ath9k_tx_queue_info *qi;
594 590
595 if (q >= pCap->total_queues) { 591 if (q >= pCap->total_queues) {
596 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 592 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
597 __func__, q);
598 return false; 593 return false;
599 } 594 }
600 595
601 qi = &ahp->ah_txq[q]; 596 qi = &ahp->ah_txq[q];
602 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 597 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
603 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue\n", 598 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n");
604 __func__);
605 return false; 599 return false;
606 } 600 }
607 601
@@ -651,22 +645,21 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
651 break; 645 break;
652 if (q == pCap->total_queues) { 646 if (q == pCap->total_queues) {
653 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 647 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
654 "%s: no available tx queue\n", __func__); 648 "no available tx queue\n");
655 return -1; 649 return -1;
656 } 650 }
657 break; 651 break;
658 default: 652 default:
659 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: bad tx queue type %u\n", 653 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "bad tx queue type %u\n", type);
660 __func__, type);
661 return -1; 654 return -1;
662 } 655 }
663 656
664 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: queue %u\n", __func__, q); 657 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q);
665 658
666 qi = &ahp->ah_txq[q]; 659 qi = &ahp->ah_txq[q];
667 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 660 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
668 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 661 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
669 "%s: tx queue %u already active\n", __func__, q); 662 "tx queue %u already active\n", q);
670 return -1; 663 return -1;
671 } 664 }
672 memset(qi, 0, sizeof(struct ath9k_tx_queue_info)); 665 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -697,19 +690,16 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q)
697 struct ath9k_tx_queue_info *qi; 690 struct ath9k_tx_queue_info *qi;
698 691
699 if (q >= pCap->total_queues) { 692 if (q >= pCap->total_queues) {
700 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 693 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
701 __func__, q);
702 return false; 694 return false;
703 } 695 }
704 qi = &ahp->ah_txq[q]; 696 qi = &ahp->ah_txq[q];
705 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 697 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
706 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", 698 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
707 __func__, q);
708 return false; 699 return false;
709 } 700 }
710 701
711 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: release queue %u\n", 702 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q);
712 __func__, q);
713 703
714 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 704 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
715 ahp->ah_txOkInterruptMask &= ~(1 << q); 705 ahp->ah_txOkInterruptMask &= ~(1 << q);
@@ -731,19 +721,17 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q)
731 u32 cwMin, chanCwMin, value; 721 u32 cwMin, chanCwMin, value;
732 722
733 if (q >= pCap->total_queues) { 723 if (q >= pCap->total_queues) {
734 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: invalid queue num %u\n", 724 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q);
735 __func__, q);
736 return false; 725 return false;
737 } 726 }
738 727
739 qi = &ahp->ah_txq[q]; 728 qi = &ahp->ah_txq[q];
740 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 729 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
741 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: inactive queue %u\n", 730 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q);
742 __func__, q);
743 return true; 731 return true;
744 } 732 }
745 733
746 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "%s: reset queue %u\n", __func__, q); 734 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "reset queue %u\n", q);
747 735
748 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 736 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
749 if (chan && IS_CHAN_B(chan)) 737 if (chan && IS_CHAN_B(chan))
@@ -976,8 +964,7 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set)
976 964
977 reg = REG_READ(ah, AR_OBS_BUS_1); 965 reg = REG_READ(ah, AR_OBS_BUS_1);
978 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 966 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
979 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n", 967 "rx failed to go idle in 10 ms RXSM=0x%x\n", reg);
980 __func__, reg);
981 968
982 return false; 969 return false;
983 } 970 }
@@ -1022,9 +1009,8 @@ bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
1022 1009
1023 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) { 1010 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
1024 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 1011 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1025 "%s: dma failed to stop in 10ms\n" 1012 "dma failed to stop in 10ms\n"
1026 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n", 1013 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
1027 __func__,
1028 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); 1014 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
1029 return false; 1015 return false;
1030 } else { 1016 } else {
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index e05eb1f07894..de059c38467d 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -38,6 +38,21 @@ static struct pci_device_id ath_pci_id_table[] __devinitdata = {
38 38
39static void ath_detach(struct ath_softc *sc); 39static void ath_detach(struct ath_softc *sc);
40 40
41void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...)
42{
43 if (!sc)
44 return;
45
46 if (sc->sc_debug & dbg_mask) {
47 va_list args;
48
49 va_start(args, fmt);
50 printk(KERN_DEBUG "ath9k: ");
51 vprintk(fmt, args);
52 va_end(args);
53 }
54}
55
41/* return bus cachesize in 4B word units */ 56/* return bus cachesize in 4B word units */
42 57
43static void bus_read_cachesize(struct ath_softc *sc, int *csz) 58static void bus_read_cachesize(struct ath_softc *sc, int *csz)
@@ -175,8 +190,8 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
175 rate[i].bitrate = rate_table->info[i].ratekbps / 100; 190 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
176 rate[i].hw_value = rate_table->info[i].ratecode; 191 rate[i].hw_value = rate_table->info[i].ratecode;
177 sband->n_bitrates++; 192 sband->n_bitrates++;
178 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Rate: %2dMbps, ratecode: %2d\n", 193 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
179 __func__, rate[i].bitrate / 10, rate[i].hw_value); 194 rate[i].bitrate / 10, rate[i].hw_value);
180 } 195 }
181} 196}
182 197
@@ -198,9 +213,9 @@ static int ath_setup_channels(struct ath_softc *sc)
198 &nregclass, CTRY_DEFAULT, false, 1)) { 213 &nregclass, CTRY_DEFAULT, false, 1)) {
199 u32 rd = ah->ah_currentRD; 214 u32 rd = ah->ah_currentRD;
200 DPRINTF(sc, ATH_DBG_FATAL, 215 DPRINTF(sc, ATH_DBG_FATAL,
201 "%s: unable to collect channel list; " 216 "Unable to collect channel list; "
202 "regdomain likely %u country code %u\n", 217 "regdomain likely %u country code %u\n",
203 __func__, rd, CTRY_DEFAULT); 218 rd, CTRY_DEFAULT);
204 return -EINVAL; 219 return -EINVAL;
205 } 220 }
206 221
@@ -223,9 +238,9 @@ static int ath_setup_channels(struct ath_softc *sc)
223 238
224 band_2ghz->n_channels = ++a; 239 band_2ghz->n_channels = ++a;
225 240
226 DPRINTF(sc, ATH_DBG_CONFIG, "%s: 2MHz channel: %d, " 241 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
227 "channelFlags: 0x%x\n", 242 "channelFlags: 0x%x\n",
228 __func__, c->channel, c->channelFlags); 243 c->channel, c->channelFlags);
229 } else if (IS_CHAN_5GHZ(c)) { 244 } else if (IS_CHAN_5GHZ(c)) {
230 chan_5ghz[b].band = IEEE80211_BAND_5GHZ; 245 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
231 chan_5ghz[b].center_freq = c->channel; 246 chan_5ghz[b].center_freq = c->channel;
@@ -238,9 +253,9 @@ static int ath_setup_channels(struct ath_softc *sc)
238 253
239 band_5ghz->n_channels = ++b; 254 band_5ghz->n_channels = ++b;
240 255
241 DPRINTF(sc, ATH_DBG_CONFIG, "%s: 5MHz channel: %d, " 256 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
242 "channelFlags: 0x%x\n", 257 "channelFlags: 0x%x\n",
243 __func__, c->channel, c->channelFlags); 258 c->channel, c->channelFlags);
244 } 259 }
245 } 260 }
246 261
@@ -274,9 +289,9 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
274 * hardware at the new frequency, and then re-enable 289 * hardware at the new frequency, and then re-enable
275 * the relevant bits of the h/w. 290 * the relevant bits of the h/w.
276 */ 291 */
277 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */ 292 ath9k_hw_set_interrupts(ah, 0);
278 ath_draintxq(sc, false); /* clear pending tx frames */ 293 ath_draintxq(sc, false);
279 stopped = ath_stoprecv(sc); /* turn off frame recv */ 294 stopped = ath_stoprecv(sc);
280 295
281 /* XXX: do not flush receive queue here. We don't want 296 /* XXX: do not flush receive queue here. We don't want
282 * to flush data frames already in queue because of 297 * to flush data frames already in queue because of
@@ -286,8 +301,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
286 fastcc = false; 301 fastcc = false;
287 302
288 DPRINTF(sc, ATH_DBG_CONFIG, 303 DPRINTF(sc, ATH_DBG_CONFIG,
289 "%s: (%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n", 304 "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
290 __func__,
291 sc->sc_ah->ah_curchan->channel, 305 sc->sc_ah->ah_curchan->channel,
292 hchan->channel, hchan->channelFlags, sc->tx_chan_width); 306 hchan->channel, hchan->channelFlags, sc->tx_chan_width);
293 307
@@ -296,8 +310,8 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
296 sc->sc_tx_chainmask, sc->sc_rx_chainmask, 310 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
297 sc->sc_ht_extprotspacing, fastcc, &status)) { 311 sc->sc_ht_extprotspacing, fastcc, &status)) {
298 DPRINTF(sc, ATH_DBG_FATAL, 312 DPRINTF(sc, ATH_DBG_FATAL,
299 "%s: unable to reset channel %u (%uMhz) " 313 "Unable to reset channel %u (%uMhz) "
300 "flags 0x%x hal status %u\n", __func__, 314 "flags 0x%x hal status %u\n",
301 ath9k_hw_mhz2ieee(ah, hchan->channel, 315 ath9k_hw_mhz2ieee(ah, hchan->channel,
302 hchan->channelFlags), 316 hchan->channelFlags),
303 hchan->channel, hchan->channelFlags, status); 317 hchan->channel, hchan->channelFlags, status);
@@ -311,7 +325,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
311 325
312 if (ath_startrecv(sc) != 0) { 326 if (ath_startrecv(sc) != 0) {
313 DPRINTF(sc, ATH_DBG_FATAL, 327 DPRINTF(sc, ATH_DBG_FATAL,
314 "%s: unable to restart recv logic\n", __func__); 328 "Unable to restart recv logic\n");
315 return -EIO; 329 return -EIO;
316 } 330 }
317 331
@@ -352,8 +366,7 @@ static void ath_ani_calibrate(unsigned long data)
352 /* Long calibration runs independently of short calibration. */ 366 /* Long calibration runs independently of short calibration. */
353 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) { 367 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
354 longcal = true; 368 longcal = true;
355 DPRINTF(sc, ATH_DBG_ANI, "%s: longcal @%lu\n", 369 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
356 __func__, jiffies);
357 sc->sc_ani.sc_longcal_timer = timestamp; 370 sc->sc_ani.sc_longcal_timer = timestamp;
358 } 371 }
359 372
@@ -362,8 +375,7 @@ static void ath_ani_calibrate(unsigned long data)
362 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >= 375 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
363 ATH_SHORT_CALINTERVAL) { 376 ATH_SHORT_CALINTERVAL) {
364 shortcal = true; 377 shortcal = true;
365 DPRINTF(sc, ATH_DBG_ANI, "%s: shortcal @%lu\n", 378 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
366 __func__, jiffies);
367 sc->sc_ani.sc_shortcal_timer = timestamp; 379 sc->sc_ani.sc_shortcal_timer = timestamp;
368 sc->sc_ani.sc_resetcal_timer = timestamp; 380 sc->sc_ani.sc_resetcal_timer = timestamp;
369 } 381 }
@@ -404,15 +416,13 @@ static void ath_ani_calibrate(unsigned long data)
404 ah->ah_curchan); 416 ah->ah_curchan);
405 417
406 DPRINTF(sc, ATH_DBG_ANI, 418 DPRINTF(sc, ATH_DBG_ANI,
407 "%s: calibrate chan %u/%x nf: %d\n", 419 "calibrate chan %u/%x nf: %d\n",
408 __func__,
409 ah->ah_curchan->channel, 420 ah->ah_curchan->channel,
410 ah->ah_curchan->channelFlags, 421 ah->ah_curchan->channelFlags,
411 sc->sc_ani.sc_noise_floor); 422 sc->sc_ani.sc_noise_floor);
412 } else { 423 } else {
413 DPRINTF(sc, ATH_DBG_ANY, 424 DPRINTF(sc, ATH_DBG_ANY,
414 "%s: calibrate chan %u/%x failed\n", 425 "calibrate chan %u/%x failed\n",
415 __func__,
416 ah->ah_curchan->channel, 426 ah->ah_curchan->channel,
417 ah->ah_curchan->channelFlags); 427 ah->ah_curchan->channelFlags);
418 } 428 }
@@ -449,8 +459,8 @@ static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
449 sc->sc_rx_chainmask = 1; 459 sc->sc_rx_chainmask = 1;
450 } 460 }
451 461
452 DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n", 462 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
453 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask); 463 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
454} 464}
455 465
456static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) 466static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
@@ -712,7 +722,7 @@ static int ath_setkey_tkip(struct ath_softc *sc,
712 if (!ath_keyset(sc, key->keyidx, hk, NULL)) { 722 if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
713 /* Txmic entry failed. No need to proceed further */ 723 /* Txmic entry failed. No need to proceed further */
714 DPRINTF(sc, ATH_DBG_KEYCACHE, 724 DPRINTF(sc, ATH_DBG_KEYCACHE,
715 "%s Setting TX MIC Key Failed\n", __func__); 725 "Setting TX MIC Key Failed\n");
716 return 0; 726 return 0;
717 } 727 }
718 728
@@ -836,8 +846,7 @@ static void ath9k_ht_conf(struct ath_softc *sc,
836 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width); 846 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width);
837 847
838 DPRINTF(sc, ATH_DBG_CONFIG, 848 DPRINTF(sc, ATH_DBG_CONFIG,
839 "%s: BSS Changed HT, chanwidth: %d\n", 849 "BSS Changed HT, chanwidth: %d\n", sc->tx_chan_width);
840 __func__, sc->tx_chan_width);
841 } 850 }
842} 851}
843 852
@@ -863,9 +872,7 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
863 int pos; 872 int pos;
864 873
865 if (bss_conf->assoc) { 874 if (bss_conf->assoc) {
866 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n", 875 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d\n", bss_conf->aid);
867 __func__,
868 bss_conf->aid);
869 876
870 /* New association, store aid */ 877 /* New association, store aid */
871 if (avp->av_opmode == ATH9K_M_STA) { 878 if (avp->av_opmode == ATH9K_M_STA) {
@@ -888,18 +895,13 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
888 ath_update_chainmask(sc, hw->conf.ht.enabled); 895 ath_update_chainmask(sc, hw->conf.ht.enabled);
889 896
890 DPRINTF(sc, ATH_DBG_CONFIG, 897 DPRINTF(sc, ATH_DBG_CONFIG,
891 "%s: bssid %pM aid 0x%x\n", 898 "bssid %pM aid 0x%x\n",
892 __func__,
893 sc->sc_curbssid, sc->sc_curaid); 899 sc->sc_curbssid, sc->sc_curaid);
894 900
895 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
896 __func__,
897 curchan->center_freq);
898
899 pos = ath_get_channel(sc, curchan); 901 pos = ath_get_channel(sc, curchan);
900 if (pos == -1) { 902 if (pos == -1) {
901 DPRINTF(sc, ATH_DBG_FATAL, 903 DPRINTF(sc, ATH_DBG_FATAL,
902 "%s: Invalid channel\n", __func__); 904 "Invalid channel: %d\n", curchan->center_freq);
903 return; 905 return;
904 } 906 }
905 907
@@ -920,14 +922,15 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
920 922
921 /* set h/w channel */ 923 /* set h/w channel */
922 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) 924 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
923 DPRINTF(sc, ATH_DBG_FATAL, 925 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel: %d\n",
924 "%s: Unable to set channel\n", __func__); 926 curchan->center_freq);
927
925 /* Start ANI */ 928 /* Start ANI */
926 mod_timer(&sc->sc_ani.timer, 929 mod_timer(&sc->sc_ani.timer,
927 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); 930 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
928 931
929 } else { 932 } else {
930 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info DISSOC\n", __func__); 933 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
931 sc->sc_curaid = 0; 934 sc->sc_curaid = 0;
932 } 935 }
933} 936}
@@ -1066,8 +1069,8 @@ static void ath_radio_enable(struct ath_softc *sc)
1066 sc->sc_ht_extprotspacing, 1069 sc->sc_ht_extprotspacing,
1067 false, &status)) { 1070 false, &status)) {
1068 DPRINTF(sc, ATH_DBG_FATAL, 1071 DPRINTF(sc, ATH_DBG_FATAL,
1069 "%s: unable to reset channel %u (%uMhz) " 1072 "Unable to reset channel %u (%uMhz) "
1070 "flags 0x%x hal status %u\n", __func__, 1073 "flags 0x%x hal status %u\n",
1071 ath9k_hw_mhz2ieee(ah, 1074 ath9k_hw_mhz2ieee(ah,
1072 ah->ah_curchan->channel, 1075 ah->ah_curchan->channel,
1073 ah->ah_curchan->channelFlags), 1076 ah->ah_curchan->channelFlags),
@@ -1079,7 +1082,7 @@ static void ath_radio_enable(struct ath_softc *sc)
1079 ath_update_txpow(sc); 1082 ath_update_txpow(sc);
1080 if (ath_startrecv(sc) != 0) { 1083 if (ath_startrecv(sc) != 0) {
1081 DPRINTF(sc, ATH_DBG_FATAL, 1084 DPRINTF(sc, ATH_DBG_FATAL,
1082 "%s: unable to restart recv logic\n", __func__); 1085 "Unable to restart recv logic\n");
1083 return; 1086 return;
1084 } 1087 }
1085 1088
@@ -1124,8 +1127,8 @@ static void ath_radio_disable(struct ath_softc *sc)
1124 sc->sc_ht_extprotspacing, 1127 sc->sc_ht_extprotspacing,
1125 false, &status)) { 1128 false, &status)) {
1126 DPRINTF(sc, ATH_DBG_FATAL, 1129 DPRINTF(sc, ATH_DBG_FATAL,
1127 "%s: unable to reset channel %u (%uMhz) " 1130 "Unable to reset channel %u (%uMhz) "
1128 "flags 0x%x hal status %u\n", __func__, 1131 "flags 0x%x hal status %u\n",
1129 ath9k_hw_mhz2ieee(ah, 1132 ath9k_hw_mhz2ieee(ah,
1130 ah->ah_curchan->channel, 1133 ah->ah_curchan->channel,
1131 ah->ah_curchan->channelFlags), 1134 ah->ah_curchan->channelFlags),
@@ -1205,7 +1208,7 @@ static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1205 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED; 1208 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1206 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) { 1209 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1207 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the" 1210 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1208 "radio as it is disabled by h/w \n"); 1211 "radio as it is disabled by h/w\n");
1209 return -EPERM; 1212 return -EPERM;
1210 } 1213 }
1211 ath_radio_enable(sc); 1214 ath_radio_enable(sc);
@@ -1285,7 +1288,7 @@ static void ath_detach(struct ath_softc *sc)
1285 struct ieee80211_hw *hw = sc->hw; 1288 struct ieee80211_hw *hw = sc->hw;
1286 int i = 0; 1289 int i = 0;
1287 1290
1288 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__); 1291 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1289 1292
1290#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 1293#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1291 ath_deinit_rfkill(sc); 1294 ath_deinit_rfkill(sc);
@@ -1340,8 +1343,7 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1340 ah = ath9k_hw_attach(devid, sc, sc->mem, &status); 1343 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1341 if (ah == NULL) { 1344 if (ah == NULL) {
1342 DPRINTF(sc, ATH_DBG_FATAL, 1345 DPRINTF(sc, ATH_DBG_FATAL,
1343 "%s: unable to attach hardware; HAL status %u\n", 1346 "Unable to attach hardware; HAL status %u\n", status);
1344 __func__, status);
1345 error = -ENXIO; 1347 error = -ENXIO;
1346 goto bad; 1348 goto bad;
1347 } 1349 }
@@ -1351,8 +1353,8 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1351 sc->sc_keymax = ah->ah_caps.keycache_size; 1353 sc->sc_keymax = ah->ah_caps.keycache_size;
1352 if (sc->sc_keymax > ATH_KEYMAX) { 1354 if (sc->sc_keymax > ATH_KEYMAX) {
1353 DPRINTF(sc, ATH_DBG_KEYCACHE, 1355 DPRINTF(sc, ATH_DBG_KEYCACHE,
1354 "%s: Warning, using only %u entries in %u key cache\n", 1356 "Warning, using only %u entries in %u key cache\n",
1355 __func__, ATH_KEYMAX, sc->sc_keymax); 1357 ATH_KEYMAX, sc->sc_keymax);
1356 sc->sc_keymax = ATH_KEYMAX; 1358 sc->sc_keymax = ATH_KEYMAX;
1357 } 1359 }
1358 1360
@@ -1399,14 +1401,14 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1399 sc->sc_bhalq = ath_beaconq_setup(ah); 1401 sc->sc_bhalq = ath_beaconq_setup(ah);
1400 if (sc->sc_bhalq == -1) { 1402 if (sc->sc_bhalq == -1) {
1401 DPRINTF(sc, ATH_DBG_FATAL, 1403 DPRINTF(sc, ATH_DBG_FATAL,
1402 "%s: unable to setup a beacon xmit queue\n", __func__); 1404 "Unable to setup a beacon xmit queue\n");
1403 error = -EIO; 1405 error = -EIO;
1404 goto bad2; 1406 goto bad2;
1405 } 1407 }
1406 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 1408 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1407 if (sc->sc_cabq == NULL) { 1409 if (sc->sc_cabq == NULL) {
1408 DPRINTF(sc, ATH_DBG_FATAL, 1410 DPRINTF(sc, ATH_DBG_FATAL,
1409 "%s: unable to setup CAB xmit queue\n", __func__); 1411 "Unable to setup CAB xmit queue\n");
1410 error = -EIO; 1412 error = -EIO;
1411 goto bad2; 1413 goto bad2;
1412 } 1414 }
@@ -1421,30 +1423,26 @@ static int ath_init(u16 devid, struct ath_softc *sc)
1421 /* NB: ensure BK queue is the lowest priority h/w queue */ 1423 /* NB: ensure BK queue is the lowest priority h/w queue */
1422 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { 1424 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1423 DPRINTF(sc, ATH_DBG_FATAL, 1425 DPRINTF(sc, ATH_DBG_FATAL,
1424 "%s: unable to setup xmit queue for BK traffic\n", 1426 "Unable to setup xmit queue for BK traffic\n");
1425 __func__);
1426 error = -EIO; 1427 error = -EIO;
1427 goto bad2; 1428 goto bad2;
1428 } 1429 }
1429 1430
1430 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { 1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1431 DPRINTF(sc, ATH_DBG_FATAL, 1432 DPRINTF(sc, ATH_DBG_FATAL,
1432 "%s: unable to setup xmit queue for BE traffic\n", 1433 "Unable to setup xmit queue for BE traffic\n");
1433 __func__);
1434 error = -EIO; 1434 error = -EIO;
1435 goto bad2; 1435 goto bad2;
1436 } 1436 }
1437 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { 1437 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1438 DPRINTF(sc, ATH_DBG_FATAL, 1438 DPRINTF(sc, ATH_DBG_FATAL,
1439 "%s: unable to setup xmit queue for VI traffic\n", 1439 "Unable to setup xmit queue for VI traffic\n");
1440 __func__);
1441 error = -EIO; 1440 error = -EIO;
1442 goto bad2; 1441 goto bad2;
1443 } 1442 }
1444 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { 1443 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1445 DPRINTF(sc, ATH_DBG_FATAL, 1444 DPRINTF(sc, ATH_DBG_FATAL,
1446 "%s: unable to setup xmit queue for VO traffic\n", 1445 "Unable to setup xmit queue for VO traffic\n");
1447 __func__);
1448 error = -EIO; 1446 error = -EIO;
1449 goto bad2; 1447 goto bad2;
1450 } 1448 }
@@ -1556,7 +1554,7 @@ static int ath_attach(u16 devid, struct ath_softc *sc)
1556 struct ieee80211_hw *hw = sc->hw; 1554 struct ieee80211_hw *hw = sc->hw;
1557 int error = 0; 1555 int error = 0;
1558 1556
1559 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__); 1557 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1560 1558
1561 error = ath_init(devid, sc); 1559 error = ath_init(devid, sc);
1562 if (error != 0) 1560 if (error != 0)
@@ -1587,8 +1585,7 @@ static int ath_attach(u16 devid, struct ath_softc *sc)
1587 error = ath_rate_control_register(); 1585 error = ath_rate_control_register();
1588 if (error != 0) { 1586 if (error != 0) {
1589 DPRINTF(sc, ATH_DBG_FATAL, 1587 DPRINTF(sc, ATH_DBG_FATAL,
1590 "%s: Unable to register rate control " 1588 "Unable to register rate control algorithm: %d\n", error);
1591 "algorithm:%d\n", __func__, error);
1592 ath_rate_control_unregister(); 1589 ath_rate_control_unregister();
1593 goto bad; 1590 goto bad;
1594 } 1591 }
@@ -1656,15 +1653,13 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1656 sc->sc_tx_chainmask, sc->sc_rx_chainmask, 1653 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1657 sc->sc_ht_extprotspacing, false, &status)) { 1654 sc->sc_ht_extprotspacing, false, &status)) {
1658 DPRINTF(sc, ATH_DBG_FATAL, 1655 DPRINTF(sc, ATH_DBG_FATAL,
1659 "%s: unable to reset hardware; hal status %u\n", 1656 "Unable to reset hardware; hal status %u\n", status);
1660 __func__, status);
1661 error = -EIO; 1657 error = -EIO;
1662 } 1658 }
1663 spin_unlock_bh(&sc->sc_resetlock); 1659 spin_unlock_bh(&sc->sc_resetlock);
1664 1660
1665 if (ath_startrecv(sc) != 0) 1661 if (ath_startrecv(sc) != 0)
1666 DPRINTF(sc, ATH_DBG_FATAL, 1662 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1667 "%s: unable to start recv logic\n", __func__);
1668 1663
1669 /* 1664 /*
1670 * We may be doing a reset in response to a request 1665 * We may be doing a reset in response to a request
@@ -1712,13 +1707,12 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1712 struct ath_buf *bf; 1707 struct ath_buf *bf;
1713 int i, bsize, error; 1708 int i, bsize, error;
1714 1709
1715 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n", 1710 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1716 __func__, name, nbuf, ndesc); 1711 name, nbuf, ndesc);
1717 1712
1718 /* ath_desc must be a multiple of DWORDs */ 1713 /* ath_desc must be a multiple of DWORDs */
1719 if ((sizeof(struct ath_desc) % 4) != 0) { 1714 if ((sizeof(struct ath_desc) % 4) != 0) {
1720 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n", 1715 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1721 __func__);
1722 ASSERT((sizeof(struct ath_desc) % 4) == 0); 1716 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1723 error = -ENOMEM; 1717 error = -ENOMEM;
1724 goto fail; 1718 goto fail;
@@ -1754,8 +1748,8 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1754 goto fail; 1748 goto fail;
1755 } 1749 }
1756 ds = dd->dd_desc; 1750 ds = dd->dd_desc;
1757 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n", 1751 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1758 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len, 1752 dd->dd_name, ds, (u32) dd->dd_desc_len,
1759 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 1753 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1760 1754
1761 /* allocate buffers */ 1755 /* allocate buffers */
@@ -1877,14 +1871,14 @@ static int ath9k_start(struct ieee80211_hw *hw)
1877 struct ath9k_channel *init_channel; 1871 struct ath9k_channel *init_channel;
1878 int error = 0, pos, status; 1872 int error = 0, pos, status;
1879 1873
1880 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with " 1874 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1881 "initial channel: %d MHz\n", __func__, curchan->center_freq); 1875 "initial channel: %d MHz\n", curchan->center_freq);
1882 1876
1883 /* setup initial channel */ 1877 /* setup initial channel */
1884 1878
1885 pos = ath_get_channel(sc, curchan); 1879 pos = ath_get_channel(sc, curchan);
1886 if (pos == -1) { 1880 if (pos == -1) {
1887 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__); 1881 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1888 error = -EINVAL; 1882 error = -EINVAL;
1889 goto error; 1883 goto error;
1890 } 1884 }
@@ -1910,8 +1904,8 @@ static int ath9k_start(struct ieee80211_hw *hw)
1910 sc->sc_tx_chainmask, sc->sc_rx_chainmask, 1904 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1911 sc->sc_ht_extprotspacing, false, &status)) { 1905 sc->sc_ht_extprotspacing, false, &status)) {
1912 DPRINTF(sc, ATH_DBG_FATAL, 1906 DPRINTF(sc, ATH_DBG_FATAL,
1913 "%s: unable to reset hardware; hal status %u " 1907 "Unable to reset hardware; hal status %u "
1914 "(freq %u flags 0x%x)\n", __func__, status, 1908 "(freq %u flags 0x%x)\n", status,
1915 init_channel->channel, init_channel->channelFlags); 1909 init_channel->channel, init_channel->channelFlags);
1916 error = -EIO; 1910 error = -EIO;
1917 spin_unlock_bh(&sc->sc_resetlock); 1911 spin_unlock_bh(&sc->sc_resetlock);
@@ -1934,7 +1928,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1934 */ 1928 */
1935 if (ath_startrecv(sc) != 0) { 1929 if (ath_startrecv(sc) != 0) {
1936 DPRINTF(sc, ATH_DBG_FATAL, 1930 DPRINTF(sc, ATH_DBG_FATAL,
1937 "%s: unable to start recv logic\n", __func__); 1931 "Unable to start recv logic\n");
1938 error = -EIO; 1932 error = -EIO;
1939 goto error; 1933 goto error;
1940 } 1934 }
@@ -2026,12 +2020,10 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2026 if (!txctl.txq) 2020 if (!txctl.txq)
2027 goto exit; 2021 goto exit;
2028 2022
2029 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n", 2023 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2030 __func__,
2031 skb);
2032 2024
2033 if (ath_tx_start(sc, skb, &txctl) != 0) { 2025 if (ath_tx_start(sc, skb, &txctl) != 0) {
2034 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__); 2026 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2035 goto exit; 2027 goto exit;
2036 } 2028 }
2037 2029
@@ -2046,11 +2038,11 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2046 struct ath_softc *sc = hw->priv; 2038 struct ath_softc *sc = hw->priv;
2047 2039
2048 if (sc->sc_flags & SC_OP_INVALID) { 2040 if (sc->sc_flags & SC_OP_INVALID) {
2049 DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__); 2041 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2050 return; 2042 return;
2051 } 2043 }
2052 2044
2053 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Cleaning up\n", __func__); 2045 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2054 2046
2055 ieee80211_stop_queues(sc->hw); 2047 ieee80211_stop_queues(sc->hw);
2056 2048
@@ -2075,7 +2067,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2075 2067
2076 sc->sc_flags |= SC_OP_INVALID; 2068 sc->sc_flags |= SC_OP_INVALID;
2077 2069
2078 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__); 2070 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2079} 2071}
2080 2072
2081static int ath9k_add_interface(struct ieee80211_hw *hw, 2073static int ath9k_add_interface(struct ieee80211_hw *hw,
@@ -2102,14 +2094,11 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2102 break; 2094 break;
2103 default: 2095 default:
2104 DPRINTF(sc, ATH_DBG_FATAL, 2096 DPRINTF(sc, ATH_DBG_FATAL,
2105 "%s: Interface type %d not yet supported\n", 2097 "Interface type %d not yet supported\n", conf->type);
2106 __func__, conf->type);
2107 return -EOPNOTSUPP; 2098 return -EOPNOTSUPP;
2108 } 2099 }
2109 2100
2110 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n", 2101 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2111 __func__,
2112 ic_opmode);
2113 2102
2114 /* Set the VAP opmode */ 2103 /* Set the VAP opmode */
2115 avp->av_opmode = ic_opmode; 2104 avp->av_opmode = ic_opmode;
@@ -2140,7 +2129,7 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2140 struct ath_softc *sc = hw->priv; 2129 struct ath_softc *sc = hw->priv;
2141 struct ath_vap *avp = (void *)conf->vif->drv_priv; 2130 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2142 2131
2143 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__); 2132 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2144 2133
2145#ifdef CONFIG_SLOW_ANT_DIV 2134#ifdef CONFIG_SLOW_ANT_DIV
2146 ath_slow_ant_div_stop(&sc->sc_antdiv); 2135 ath_slow_ant_div_stop(&sc->sc_antdiv);
@@ -2170,12 +2159,13 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2170 struct ieee80211_channel *curchan = hw->conf.channel; 2159 struct ieee80211_channel *curchan = hw->conf.channel;
2171 int pos; 2160 int pos;
2172 2161
2173 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n", 2162 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2174 __func__, curchan->center_freq); 2163 curchan->center_freq);
2175 2164
2176 pos = ath_get_channel(sc, curchan); 2165 pos = ath_get_channel(sc, curchan);
2177 if (pos == -1) { 2166 if (pos == -1) {
2178 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__); 2167 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2168 curchan->center_freq);
2179 return -EINVAL; 2169 return -EINVAL;
2180 } 2170 }
2181 2171
@@ -2196,8 +2186,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2196 } 2186 }
2197 2187
2198 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) { 2188 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2199 DPRINTF(sc, ATH_DBG_FATAL, 2189 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2200 "%s: Unable to set channel\n", __func__);
2201 return -EINVAL; 2190 return -EINVAL;
2202 } 2191 }
2203 } 2192 }
@@ -2247,9 +2236,8 @@ static int ath9k_config_interface(struct ieee80211_hw *hw,
2247 sc->sc_config.ath_aggr_prot = 0; 2236 sc->sc_config.ath_aggr_prot = 0;
2248 2237
2249 DPRINTF(sc, ATH_DBG_CONFIG, 2238 DPRINTF(sc, ATH_DBG_CONFIG,
2250 "%s: RX filter 0x%x bssid %pM aid 0x%x\n", 2239 "RX filter 0x%x bssid %pM aid 0x%x\n",
2251 __func__, rfilt, 2240 rfilt, sc->sc_curbssid, sc->sc_curaid);
2252 sc->sc_curbssid, sc->sc_curaid);
2253 2241
2254 /* need to reconfigure the beacon */ 2242 /* need to reconfigure the beacon */
2255 sc->sc_flags &= ~SC_OP_BEACONS ; 2243 sc->sc_flags &= ~SC_OP_BEACONS ;
@@ -2326,8 +2314,7 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2326 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0); 2314 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2327 } 2315 }
2328 2316
2329 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n", 2317 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx_filter);
2330 __func__, sc->rx_filter);
2331} 2318}
2332 2319
2333static void ath9k_sta_notify(struct ieee80211_hw *hw, 2320static void ath9k_sta_notify(struct ieee80211_hw *hw,
@@ -2367,20 +2354,14 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw,
2367 qnum = ath_get_hal_qnum(queue, sc); 2354 qnum = ath_get_hal_qnum(queue, sc);
2368 2355
2369 DPRINTF(sc, ATH_DBG_CONFIG, 2356 DPRINTF(sc, ATH_DBG_CONFIG,
2370 "%s: Configure tx [queue/halq] [%d/%d], " 2357 "Configure tx [queue/halq] [%d/%d], "
2371 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 2358 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2372 __func__, 2359 queue, qnum, params->aifs, params->cw_min,
2373 queue, 2360 params->cw_max, params->txop);
2374 qnum,
2375 params->aifs,
2376 params->cw_min,
2377 params->cw_max,
2378 params->txop);
2379 2361
2380 ret = ath_txq_update(sc, qnum, &qi); 2362 ret = ath_txq_update(sc, qnum, &qi);
2381 if (ret) 2363 if (ret)
2382 DPRINTF(sc, ATH_DBG_FATAL, 2364 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2383 "%s: TXQ Update failed\n", __func__);
2384 2365
2385 return ret; 2366 return ret;
2386} 2367}
@@ -2394,7 +2375,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2394 struct ath_softc *sc = hw->priv; 2375 struct ath_softc *sc = hw->priv;
2395 int ret = 0; 2376 int ret = 0;
2396 2377
2397 DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__); 2378 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2398 2379
2399 switch (cmd) { 2380 switch (cmd) {
2400 case SET_KEY: 2381 case SET_KEY:
@@ -2427,8 +2408,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2427 struct ath_softc *sc = hw->priv; 2408 struct ath_softc *sc = hw->priv;
2428 2409
2429 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2410 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2430 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n", 2411 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2431 __func__,
2432 bss_conf->use_short_preamble); 2412 bss_conf->use_short_preamble);
2433 if (bss_conf->use_short_preamble) 2413 if (bss_conf->use_short_preamble)
2434 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 2414 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
@@ -2437,8 +2417,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2437 } 2417 }
2438 2418
2439 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2419 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2440 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n", 2420 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2441 __func__,
2442 bss_conf->use_cts_prot); 2421 bss_conf->use_cts_prot);
2443 if (bss_conf->use_cts_prot && 2422 if (bss_conf->use_cts_prot &&
2444 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 2423 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
@@ -2451,8 +2430,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2451 ath9k_ht_conf(sc, bss_conf); 2430 ath9k_ht_conf(sc, bss_conf);
2452 2431
2453 if (changed & BSS_CHANGED_ASSOC) { 2432 if (changed & BSS_CHANGED_ASSOC) {
2454 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n", 2433 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2455 __func__,
2456 bss_conf->assoc); 2434 bss_conf->assoc);
2457 ath9k_bss_assoc_info(sc, vif, bss_conf); 2435 ath9k_bss_assoc_info(sc, vif, bss_conf);
2458 } 2436 }
@@ -2496,8 +2474,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2496 ret = ath_tx_aggr_start(sc, sta, tid, ssn); 2474 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2497 if (ret < 0) 2475 if (ret < 0)
2498 DPRINTF(sc, ATH_DBG_FATAL, 2476 DPRINTF(sc, ATH_DBG_FATAL,
2499 "%s: Unable to start TX aggregation\n", 2477 "Unable to start TX aggregation\n");
2500 __func__);
2501 else 2478 else
2502 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid); 2479 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2503 break; 2480 break;
@@ -2505,8 +2482,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2505 ret = ath_tx_aggr_stop(sc, sta, tid); 2482 ret = ath_tx_aggr_stop(sc, sta, tid);
2506 if (ret < 0) 2483 if (ret < 0)
2507 DPRINTF(sc, ATH_DBG_FATAL, 2484 DPRINTF(sc, ATH_DBG_FATAL,
2508 "%s: Unable to stop TX aggregation\n", 2485 "Unable to stop TX aggregation\n");
2509 __func__);
2510 2486
2511 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid); 2487 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2512 break; 2488 break;
@@ -2514,8 +2490,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2514 ath_tx_aggr_resume(sc, sta, tid); 2490 ath_tx_aggr_resume(sc, sta, tid);
2515 break; 2491 break;
2516 default: 2492 default:
2517 DPRINTF(sc, ATH_DBG_FATAL, 2493 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2518 "%s: Unknown AMPDU action\n", __func__);
2519 } 2494 }
2520 2495
2521 return ret; 2496 return ret;
@@ -2571,7 +2546,6 @@ static struct {
2571/* 2546/*
2572 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 2547 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2573 */ 2548 */
2574
2575static const char * 2549static const char *
2576ath_mac_bb_name(u32 mac_bb_version) 2550ath_mac_bb_name(u32 mac_bb_version)
2577{ 2551{
@@ -2589,7 +2563,6 @@ ath_mac_bb_name(u32 mac_bb_version)
2589/* 2563/*
2590 * Return the RF name. "????" is returned if the RF is unknown. 2564 * Return the RF name. "????" is returned if the RF is unknown.
2591 */ 2565 */
2592
2593static const char * 2566static const char *
2594ath_rf_name(u16 rf_version) 2567ath_rf_name(u16 rf_version)
2595{ 2568{
@@ -2628,7 +2601,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2628 2601
2629 if (ret) { 2602 if (ret) {
2630 printk(KERN_ERR "ath9k: 32-bit DMA consistent " 2603 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2631 "DMA enable faled\n"); 2604 "DMA enable failed\n");
2632 goto bad; 2605 goto bad;
2633 } 2606 }
2634 2607
@@ -2838,6 +2811,6 @@ module_init(init_ath_pci);
2838static void __exit exit_ath_pci(void) 2811static void __exit exit_ath_pci(void)
2839{ 2812{
2840 pci_unregister_driver(&ath_pci_driver); 2813 pci_unregister_driver(&ath_pci_driver);
2841 printk(KERN_INFO "%s: driver unloaded\n", dev_info); 2814 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2842} 2815}
2843module_exit(exit_ath_pci); 2816module_exit(exit_ath_pci);
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c
index 4f1c8bf8342b..766982a8196e 100644
--- a/drivers/net/wireless/ath9k/phy.c
+++ b/drivers/net/wireless/ath9k/phy.c
@@ -52,8 +52,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
52 bModeSynth = 1; 52 bModeSynth = 1;
53 } else { 53 } else {
54 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 54 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
55 "%s: invalid channel %u MHz\n", __func__, 55 "Invalid channel %u MHz\n", freq);
56 freq);
57 return false; 56 return false;
58 } 57 }
59 58
@@ -86,7 +85,7 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan)
86 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 85 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
87 } else { 86 } else {
88 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL, 87 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
89 "%s: invalid channel %u MHz\n", __func__, freq); 88 "Invalid channel %u MHz\n", freq);
90 return false; 89 return false;
91 } 90 }
92 91
@@ -348,8 +347,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
348 || ahp->ah_analogBank6TPCData == NULL 347 || ahp->ah_analogBank6TPCData == NULL
349 || ahp->ah_analogBank7Data == NULL) { 348 || ahp->ah_analogBank7Data == NULL) {
350 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 349 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
351 "%s: cannot allocate RF banks\n", 350 "Cannot allocate RF banks\n");
352 __func__);
353 *status = -ENOMEM; 351 *status = -ENOMEM;
354 return false; 352 return false;
355 } 353 }
@@ -360,8 +358,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
360 ahp->ah_iniAddac.ia_columns), GFP_KERNEL); 358 ahp->ah_iniAddac.ia_columns), GFP_KERNEL);
361 if (ahp->ah_addac5416_21 == NULL) { 359 if (ahp->ah_addac5416_21 == NULL) {
362 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 360 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
363 "%s: cannot allocate ah_addac5416_21\n", 361 "Cannot allocate ah_addac5416_21\n");
364 __func__);
365 *status = -ENOMEM; 362 *status = -ENOMEM;
366 return false; 363 return false;
367 } 364 }
@@ -371,8 +368,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status)
371 ahp->ah_iniBank6.ia_rows), GFP_KERNEL); 368 ahp->ah_iniBank6.ia_rows), GFP_KERNEL);
372 if (ahp->ah_bank6Temp == NULL) { 369 if (ahp->ah_bank6Temp == NULL) {
373 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 370 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
374 "%s: cannot allocate ah_bank6Temp\n", 371 "Cannot allocate ah_bank6Temp\n");
375 __func__);
376 *status = -ENOMEM; 372 *status = -ENOMEM;
377 return false; 373 return false;
378 } 374 }
diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c
index 7c08583a7943..7d5affda3b8b 100644
--- a/drivers/net/wireless/ath9k/rc.c
+++ b/drivers/net/wireless/ath9k/rc.c
@@ -1326,13 +1326,13 @@ static struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1326 mode = ATH9K_MODE_11NA_HT40PLUS; 1326 mode = ATH9K_MODE_11NA_HT40PLUS;
1327 break; 1327 break;
1328 default: 1328 default:
1329 DPRINTF(sc, ATH_DBG_RATE, "Invalid band\n"); 1329 DPRINTF(sc, ATH_DBG_CONFIG, "Invalid band\n");
1330 return NULL; 1330 return NULL;
1331 } 1331 }
1332 1332
1333 BUG_ON(mode >= ATH9K_MODE_MAX); 1333 BUG_ON(mode >= ATH9K_MODE_MAX);
1334 1334
1335 DPRINTF(sc, ATH_DBG_RATE, "Choosing rate table for mode: %d\n", mode); 1335 DPRINTF(sc, ATH_DBG_CONFIG, "Choosing rate table for mode: %d\n", mode);
1336 return sc->hw_rate_table[mode]; 1336 return sc->hw_rate_table[mode];
1337} 1337}
1338 1338
@@ -1572,8 +1572,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
1572 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp); 1572 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
1573 if (!rate_priv) { 1573 if (!rate_priv) {
1574 DPRINTF(sc, ATH_DBG_FATAL, 1574 DPRINTF(sc, ATH_DBG_FATAL,
1575 "%s: Unable to allocate private rc structure\n", 1575 "Unable to allocate private rc structure\n");
1576 __func__);
1577 return NULL; 1576 return NULL;
1578 } 1577 }
1579 1578
diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c
index e49e32356e92..0b9a3d9c5824 100644
--- a/drivers/net/wireless/ath9k/recv.c
+++ b/drivers/net/wireless/ath9k/recv.c
@@ -105,8 +105,7 @@ static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len)
105 skb_reserve(skb, sc->sc_cachelsz - off); 105 skb_reserve(skb, sc->sc_cachelsz - off);
106 } else { 106 } else {
107 DPRINTF(sc, ATH_DBG_FATAL, 107 DPRINTF(sc, ATH_DBG_FATAL,
108 "%s: skbuff alloc of size %u failed\n", 108 "skbuff alloc of size %u failed\n", len);
109 __func__, len);
110 return NULL; 109 return NULL;
111 } 110 }
112 111
@@ -263,11 +262,7 @@ static void ath_opmode_init(struct ath_softc *sc)
263 262
264 /* calculate and install multicast filter */ 263 /* calculate and install multicast filter */
265 mfilt[0] = mfilt[1] = ~0; 264 mfilt[0] = mfilt[1] = ~0;
266
267 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); 265 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
268 DPRINTF(sc, ATH_DBG_CONFIG ,
269 "%s: RX filter 0x%x, MC filter %08x:%08x\n",
270 __func__, rfilt, mfilt[0], mfilt[1]);
271} 266}
272 267
273int ath_rx_init(struct ath_softc *sc, int nbufs) 268int ath_rx_init(struct ath_softc *sc, int nbufs)
@@ -285,8 +280,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
285 min(sc->sc_cachelsz, 280 min(sc->sc_cachelsz,
286 (u16)64)); 281 (u16)64));
287 282
288 DPRINTF(sc, ATH_DBG_CONFIG, "%s: cachelsz %u rxbufsize %u\n", 283 DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
289 __func__, sc->sc_cachelsz, sc->sc_rxbufsize); 284 sc->sc_cachelsz, sc->sc_rxbufsize);
290 285
291 /* Initialize rx descriptors */ 286 /* Initialize rx descriptors */
292 287
@@ -294,8 +289,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
294 "rx", nbufs, 1); 289 "rx", nbufs, 1);
295 if (error != 0) { 290 if (error != 0) {
296 DPRINTF(sc, ATH_DBG_FATAL, 291 DPRINTF(sc, ATH_DBG_FATAL,
297 "%s: failed to allocate rx descriptors: %d\n", 292 "failed to allocate rx descriptors: %d\n", error);
298 __func__, error);
299 break; 293 break;
300 } 294 }
301 295
diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c
index 62e28887ccd3..e3dd91f7b7b7 100644
--- a/drivers/net/wireless/ath9k/regd.c
+++ b/drivers/net/wireless/ath9k/regd.c
@@ -78,8 +78,7 @@ static bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah)
78 return true; 78 return true;
79 } 79 }
80 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 80 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
81 "%s: invalid regulatory domain/country code 0x%x\n", 81 "invalid regulatory domain/country code 0x%x\n", rd);
82 __func__, rd);
83 return false; 82 return false;
84} 83}
85 84
@@ -107,13 +106,12 @@ static bool ath9k_regd_is_ccode_valid(struct ath_hal *ah,
107 return true; 106 return true;
108 107
109 rd = ath9k_regd_get_eepromRD(ah); 108 rd = ath9k_regd_get_eepromRD(ah);
110 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: EEPROM regdomain 0x%x\n", 109 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "EEPROM regdomain 0x%x\n", rd);
111 __func__, rd);
112 110
113 if (rd & COUNTRY_ERD_FLAG) { 111 if (rd & COUNTRY_ERD_FLAG) {
114 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 112 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
115 "%s: EEPROM setting is country code %u\n", 113 "EEPROM setting is country code %u\n",
116 __func__, rd & ~COUNTRY_ERD_FLAG); 114 rd & ~COUNTRY_ERD_FLAG);
117 return cc == (rd & ~COUNTRY_ERD_FLAG); 115 return cc == (rd & ~COUNTRY_ERD_FLAG);
118 } 116 }
119 117
@@ -290,8 +288,7 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
290 } 288 }
291 if (!found) { 289 if (!found) {
292 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 290 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
293 "%s: Failed to find reg domain pair %u\n", 291 "Failed to find reg domain pair %u\n", regDmn);
294 __func__, regDmn);
295 return false; 292 return false;
296 } 293 }
297 if (!(channelFlag & CHANNEL_2GHZ)) { 294 if (!(channelFlag & CHANNEL_2GHZ)) {
@@ -307,8 +304,7 @@ ath9k_regd_get_wmode_regdomain(struct ath_hal *ah, int regDmn,
307 found = ath9k_regd_is_valid_reg_domain(regDmn, rd); 304 found = ath9k_regd_is_valid_reg_domain(regDmn, rd);
308 if (!found) { 305 if (!found) {
309 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 306 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
310 "%s: Failed to find unitary reg domain %u\n", 307 "Failed to find unitary reg domain %u\n", regDmn);
311 __func__, regDmn);
312 return false; 308 return false;
313 } else { 309 } else {
314 rd->pscan &= regPair->pscanMask; 310 rd->pscan &= regPair->pscanMask;
@@ -430,30 +426,27 @@ ath9k_regd_add_channel(struct ath_hal *ah,
430 426
431 if (!(c_lo <= c && c <= c_hi)) { 427 if (!(c_lo <= c && c <= c_hi)) {
432 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 428 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
433 "%s: c %u out of range [%u..%u]\n", 429 "c %u out of range [%u..%u]\n",
434 __func__, c, c_lo, c_hi); 430 c, c_lo, c_hi);
435 return false; 431 return false;
436 } 432 }
437 if ((fband->channelBW == CHANNEL_HALF_BW) && 433 if ((fband->channelBW == CHANNEL_HALF_BW) &&
438 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) { 434 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_HALFRATE)) {
439 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 435 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
440 "%s: Skipping %u half rate channel\n", 436 "Skipping %u half rate channel\n", c);
441 __func__, c);
442 return false; 437 return false;
443 } 438 }
444 439
445 if ((fband->channelBW == CHANNEL_QUARTER_BW) && 440 if ((fband->channelBW == CHANNEL_QUARTER_BW) &&
446 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_QUARTERRATE)) { 441 !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_CHAN_QUARTERRATE)) {
447 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 442 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
448 "%s: Skipping %u quarter rate channel\n", 443 "Skipping %u quarter rate channel\n", c);
449 __func__, c);
450 return false; 444 return false;
451 } 445 }
452 446
453 if (((c + fband->channelSep) / 2) > (maxChan + HALF_MAXCHANBW)) { 447 if (((c + fband->channelSep) / 2) > (maxChan + HALF_MAXCHANBW)) {
454 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 448 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
455 "%s: c %u > maxChan %u\n", 449 "c %u > maxChan %u\n", c, maxChan);
456 __func__, c, maxChan);
457 return false; 450 return false;
458 } 451 }
459 452
@@ -606,8 +599,7 @@ static bool ath9k_regd_japan_check(struct ath_hal *ah,
606 } 599 }
607 600
608 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 601 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
609 "%s: Skipping %d freq band\n", 602 "Skipping %d freq band\n", j_bandcheck[i].freqbandbit);
610 __func__, j_bandcheck[i].freqbandbit);
611 603
612 return skipband; 604 return skipband;
613} 605}
@@ -632,20 +624,19 @@ ath9k_regd_init_channels(struct ath_hal *ah,
632 unsigned long *modes_avail; 624 unsigned long *modes_avail;
633 DECLARE_BITMAP(modes_allowed, ATH9K_MODE_MAX); 625 DECLARE_BITMAP(modes_allowed, ATH9K_MODE_MAX);
634 626
635 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: cc %u %s %s\n", 627 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "cc %u %s %s\n", cc,
636 __func__, cc,
637 enableOutdoor ? "Enable outdoor" : "", 628 enableOutdoor ? "Enable outdoor" : "",
638 enableExtendedChannels ? "Enable ecm" : ""); 629 enableExtendedChannels ? "Enable ecm" : "");
639 630
640 if (!ath9k_regd_is_ccode_valid(ah, cc)) { 631 if (!ath9k_regd_is_ccode_valid(ah, cc)) {
641 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 632 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
642 "%s: invalid country code %d\n", __func__, cc); 633 "Invalid country code %d\n", cc);
643 return false; 634 return false;
644 } 635 }
645 636
646 if (!ath9k_regd_is_eeprom_valid(ah)) { 637 if (!ath9k_regd_is_eeprom_valid(ah)) {
647 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 638 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
648 "%s: invalid EEPROM contents\n", __func__); 639 "Invalid EEPROM contents\n");
649 return false; 640 return false;
650 } 641 }
651 642
@@ -693,9 +684,9 @@ ath9k_regd_init_channels(struct ath_hal *ah,
693 ~CHANNEL_2GHZ, 684 ~CHANNEL_2GHZ,
694 &rd5GHz)) { 685 &rd5GHz)) {
695 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 686 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
696 "%s: couldn't find unitary " 687 "Couldn't find unitary "
697 "5GHz reg domain for country %u\n", 688 "5GHz reg domain for country %u\n",
698 __func__, ah->ah_countryCode); 689 ah->ah_countryCode);
699 return false; 690 return false;
700 } 691 }
701 if (!ath9k_regd_get_wmode_regdomain(ah, 692 if (!ath9k_regd_get_wmode_regdomain(ah,
@@ -703,9 +694,9 @@ ath9k_regd_init_channels(struct ath_hal *ah,
703 CHANNEL_2GHZ, 694 CHANNEL_2GHZ,
704 &rd2GHz)) { 695 &rd2GHz)) {
705 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 696 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
706 "%s: couldn't find unitary 2GHz " 697 "Couldn't find unitary 2GHz "
707 "reg domain for country %u\n", 698 "reg domain for country %u\n",
708 __func__, ah->ah_countryCode); 699 ah->ah_countryCode);
709 return false; 700 return false;
710 } 701 }
711 702
@@ -717,9 +708,9 @@ ath9k_regd_init_channels(struct ath_hal *ah,
717 ~CHANNEL_2GHZ, 708 ~CHANNEL_2GHZ,
718 &rd5GHz)) { 709 &rd5GHz)) {
719 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 710 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
720 "%s: couldn't find unitary 5GHz " 711 "Couldn't find unitary 5GHz "
721 "reg domain for country %u\n", 712 "reg domain for country %u\n",
722 __func__, ah->ah_countryCode); 713 ah->ah_countryCode);
723 return false; 714 return false;
724 } 715 }
725 } 716 }
@@ -749,15 +740,14 @@ ath9k_regd_init_channels(struct ath_hal *ah,
749 740
750 if (!test_bit(cm->mode, modes_avail)) { 741 if (!test_bit(cm->mode, modes_avail)) {
751 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 742 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
752 "%s: !avail mode %d flags 0x%x\n", 743 "!avail mode %d flags 0x%x\n",
753 __func__, cm->mode, cm->flags); 744 cm->mode, cm->flags);
754 continue; 745 continue;
755 } 746 }
756 if (!ath9k_get_channel_edges(ah, cm->flags, &c_lo, &c_hi)) { 747 if (!ath9k_get_channel_edges(ah, cm->flags, &c_lo, &c_hi)) {
757 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 748 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
758 "%s: channels 0x%x not supported " 749 "channels 0x%x not supported "
759 "by hardware\n", 750 "by hardware\n", cm->flags);
760 __func__, cm->flags);
761 continue; 751 continue;
762 } 752 }
763 753
@@ -788,8 +778,7 @@ ath9k_regd_init_channels(struct ath_hal *ah,
788 break; 778 break;
789 default: 779 default:
790 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 780 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
791 "%s: Unknown HAL mode 0x%x\n", __func__, 781 "Unknown HAL mode 0x%x\n", cm->mode);
792 cm->mode);
793 continue; 782 continue;
794 } 783 }
795 784
@@ -841,9 +830,8 @@ ath9k_regd_init_channels(struct ath_hal *ah,
841 if (next >= maxchans) { 830 if (next >= maxchans) {
842 DPRINTF(ah->ah_sc, 831 DPRINTF(ah->ah_sc,
843 ATH_DBG_REGULATORY, 832 ATH_DBG_REGULATORY,
844 "%s: too many channels " 833 "too many channels "
845 "for channel table\n", 834 "for channel table\n");
846 __func__);
847 goto done; 835 goto done;
848 } 836 }
849 if (ath9k_regd_add_channel(ah, 837 if (ath9k_regd_add_channel(ah,
@@ -869,9 +857,8 @@ done:
869 857
870 if (next > ARRAY_SIZE(ah->ah_channels)) { 858 if (next > ARRAY_SIZE(ah->ah_channels)) {
871 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 859 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
872 "%s: too many channels %u; truncating to %u\n", 860 "too many channels %u; truncating to %u\n",
873 __func__, next, 861 next, (int) ARRAY_SIZE(ah->ah_channels));
874 (int) ARRAY_SIZE(ah->ah_channels));
875 next = ARRAY_SIZE(ah->ah_channels); 862 next = ARRAY_SIZE(ah->ah_channels);
876 } 863 }
877#ifdef ATH_NF_PER_CHAN 864#ifdef ATH_NF_PER_CHAN
@@ -919,7 +906,7 @@ ath9k_regd_check_channel(struct ath_hal *ah,
919 int n, lim; 906 int n, lim;
920 907
921 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 908 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
922 "%s: channel %u/0x%x (0x%x) requested\n", __func__, 909 "channel %u/0x%x (0x%x) requested\n",
923 c->channel, c->channelFlags, flags); 910 c->channel, c->channelFlags, flags);
924 911
925 cc = ah->ah_curchan; 912 cc = ah->ah_curchan;
@@ -950,15 +937,15 @@ ath9k_regd_check_channel(struct ath_hal *ah,
950 d = flags - (cc->channelFlags & CHAN_FLAGS); 937 d = flags - (cc->channelFlags & CHAN_FLAGS);
951 } 938 }
952 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 939 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
953 "%s: channel %u/0x%x d %d\n", __func__, 940 "channel %u/0x%x d %d\n",
954 cc->channel, cc->channelFlags, d); 941 cc->channel, cc->channelFlags, d);
955 if (d > 0) { 942 if (d > 0) {
956 base = cc + 1; 943 base = cc + 1;
957 lim--; 944 lim--;
958 } 945 }
959 } 946 }
960 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "%s: no match for %u/0x%x\n", 947 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, "no match for %u/0x%x\n",
961 __func__, c->channel, c->channelFlags); 948 c->channel, c->channelFlags);
962 return NULL; 949 return NULL;
963} 950}
964 951
diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c
index 413fbdd38ab6..fc52f61ef3ed 100644
--- a/drivers/net/wireless/ath9k/xmit.c
+++ b/drivers/net/wireless/ath9k/xmit.c
@@ -83,18 +83,16 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
83 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); 83 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
84 84
85 DPRINTF(sc, ATH_DBG_QUEUE, 85 DPRINTF(sc, ATH_DBG_QUEUE,
86 "%s: txq depth = %d\n", __func__, txq->axq_depth); 86 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
87 87
88 if (txq->axq_link == NULL) { 88 if (txq->axq_link == NULL) {
89 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 89 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
90 DPRINTF(sc, ATH_DBG_XMIT, 90 DPRINTF(sc, ATH_DBG_XMIT,
91 "%s: TXDP[%u] = %llx (%p)\n", 91 "TXDP[%u] = %llx (%p)\n",
92 __func__, txq->axq_qnum, 92 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
93 ito64(bf->bf_daddr), bf->bf_desc);
94 } else { 93 } else {
95 *txq->axq_link = bf->bf_daddr; 94 *txq->axq_link = bf->bf_daddr;
96 DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n", 95 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
97 __func__,
98 txq->axq_qnum, txq->axq_link, 96 txq->axq_qnum, txq->axq_link,
99 ito64(bf->bf_daddr), bf->bf_desc); 97 ito64(bf->bf_daddr), bf->bf_desc);
100 } 98 }
@@ -109,8 +107,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
109 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 107 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
110 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 108 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
111 109
112 DPRINTF(sc, ATH_DBG_XMIT, 110 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
113 "%s: TX complete: skb: %p\n", __func__, skb);
114 111
115 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || 112 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
116 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { 113 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
@@ -983,8 +980,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
983 int txok, nbad = 0; 980 int txok, nbad = 0;
984 int status; 981 int status;
985 982
986 DPRINTF(sc, ATH_DBG_QUEUE, 983 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
987 "%s: tx queue %d (%x), link %p\n", __func__,
988 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 984 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
989 txq->axq_link); 985 txq->axq_link);
990 986
@@ -1116,9 +1112,9 @@ static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1116 struct ath_hal *ah = sc->sc_ah; 1112 struct ath_hal *ah = sc->sc_ah;
1117 1113
1118 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum); 1114 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1119 DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n", 1115 DPRINTF(sc, ATH_DBG_XMIT, "tx queue [%u] %x, link %p\n",
1120 __func__, txq->axq_qnum, 1116 txq->axq_qnum, ath9k_hw_gettxbuf(ah, txq->axq_qnum),
1121 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link); 1117 txq->axq_link);
1122} 1118}
1123 1119
1124/* Drain only the data queues */ 1120/* Drain only the data queues */
@@ -1142,8 +1138,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1142 1138
1143 if (npend) { 1139 if (npend) {
1144 /* TxDMA not stopped, reset the hal */ 1140 /* TxDMA not stopped, reset the hal */
1145 DPRINTF(sc, ATH_DBG_XMIT, 1141 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1146 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1147 1142
1148 spin_lock_bh(&sc->sc_resetlock); 1143 spin_lock_bh(&sc->sc_resetlock);
1149 if (!ath9k_hw_reset(ah, 1144 if (!ath9k_hw_reset(ah,
@@ -1153,8 +1148,7 @@ static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1153 sc->sc_ht_extprotspacing, true, &status)) { 1148 sc->sc_ht_extprotspacing, true, &status)) {
1154 1149
1155 DPRINTF(sc, ATH_DBG_FATAL, 1150 DPRINTF(sc, ATH_DBG_FATAL,
1156 "%s: unable to reset hardware; hal status %u\n", 1151 "Unable to reset hardware; hal status %u\n",
1157 __func__,
1158 status); 1152 status);
1159 } 1153 }
1160 spin_unlock_bh(&sc->sc_resetlock); 1154 spin_unlock_bh(&sc->sc_resetlock);
@@ -1194,7 +1188,6 @@ static void ath_tx_addto_baw(struct ath_softc *sc,
1194 * Function to send an A-MPDU 1188 * Function to send an A-MPDU
1195 * NB: must be called with txq lock held 1189 * NB: must be called with txq lock held
1196 */ 1190 */
1197
1198static int ath_tx_send_ampdu(struct ath_softc *sc, 1191static int ath_tx_send_ampdu(struct ath_softc *sc,
1199 struct ath_atx_tid *tid, 1192 struct ath_atx_tid *tid,
1200 struct list_head *bf_head, 1193 struct list_head *bf_head,
@@ -1242,7 +1235,6 @@ static int ath_tx_send_ampdu(struct ath_softc *sc,
1242 * looks up the rate 1235 * looks up the rate
1243 * returns aggr limit based on lowest of the rates 1236 * returns aggr limit based on lowest of the rates
1244 */ 1237 */
1245
1246static u32 ath_lookup_rate(struct ath_softc *sc, 1238static u32 ath_lookup_rate(struct ath_softc *sc,
1247 struct ath_buf *bf, 1239 struct ath_buf *bf,
1248 struct ath_atx_tid *tid) 1240 struct ath_atx_tid *tid)
@@ -1310,7 +1302,6 @@ static u32 ath_lookup_rate(struct ath_softc *sc,
1310 * meet the minimum required mpdudensity. 1302 * meet the minimum required mpdudensity.
1311 * caller should make sure that the rate is HT rate . 1303 * caller should make sure that the rate is HT rate .
1312 */ 1304 */
1313
1314static int ath_compute_num_delims(struct ath_softc *sc, 1305static int ath_compute_num_delims(struct ath_softc *sc,
1315 struct ath_atx_tid *tid, 1306 struct ath_atx_tid *tid,
1316 struct ath_buf *bf, 1307 struct ath_buf *bf,
@@ -1382,7 +1373,6 @@ static int ath_compute_num_delims(struct ath_softc *sc,
1382 * For aggregation from software buffer queue. 1373 * For aggregation from software buffer queue.
1383 * NB: must be called with txq lock held 1374 * NB: must be called with txq lock held
1384 */ 1375 */
1385
1386static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, 1376static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1387 struct ath_atx_tid *tid, 1377 struct ath_atx_tid *tid,
1388 struct list_head *bf_q, 1378 struct list_head *bf_q,
@@ -1505,7 +1495,6 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1505 * process pending frames possibly doing a-mpdu aggregation 1495 * process pending frames possibly doing a-mpdu aggregation
1506 * NB: must be called with txq lock held 1496 * NB: must be called with txq lock held
1507 */ 1497 */
1508
1509static void ath_tx_sched_aggr(struct ath_softc *sc, 1498static void ath_tx_sched_aggr(struct ath_softc *sc,
1510 struct ath_txq *txq, struct ath_atx_tid *tid) 1499 struct ath_txq *txq, struct ath_atx_tid *tid)
1511{ 1500{
@@ -1635,7 +1624,6 @@ static void ath_tid_drain(struct ath_softc *sc,
1635 * Drain all pending buffers 1624 * Drain all pending buffers
1636 * NB: must be called with txq lock held 1625 * NB: must be called with txq lock held
1637 */ 1626 */
1638
1639static void ath_txq_drain_pending_buffers(struct ath_softc *sc, 1627static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1640 struct ath_txq *txq) 1628 struct ath_txq *txq)
1641{ 1629{
@@ -1795,8 +1783,7 @@ int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
1795 1783
1796 bf = ath_tx_get_buffer(sc); 1784 bf = ath_tx_get_buffer(sc);
1797 if (!bf) { 1785 if (!bf) {
1798 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX buffers are full\n", 1786 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1799 __func__);
1800 return -1; 1787 return -1;
1801 } 1788 }
1802 1789
@@ -1820,8 +1807,8 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
1820 "tx", nbufs, 1); 1807 "tx", nbufs, 1);
1821 if (error != 0) { 1808 if (error != 0) {
1822 DPRINTF(sc, ATH_DBG_FATAL, 1809 DPRINTF(sc, ATH_DBG_FATAL,
1823 "%s: failed to allocate tx descriptors: %d\n", 1810 "Failed to allocate tx descriptors: %d\n",
1824 __func__, error); 1811 error);
1825 break; 1812 break;
1826 } 1813 }
1827 1814
@@ -1830,9 +1817,8 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
1830 "beacon", ATH_BCBUF, 1); 1817 "beacon", ATH_BCBUF, 1);
1831 if (error != 0) { 1818 if (error != 0) {
1832 DPRINTF(sc, ATH_DBG_FATAL, 1819 DPRINTF(sc, ATH_DBG_FATAL,
1833 "%s: failed to allocate " 1820 "Failed to allocate beacon descriptors: %d\n",
1834 "beacon descripotrs: %d\n", 1821 error);
1835 __func__, error);
1836 break; 1822 break;
1837 } 1823 }
1838 1824
@@ -1904,8 +1890,8 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1904 } 1890 }
1905 if (qnum >= ARRAY_SIZE(sc->sc_txq)) { 1891 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
1906 DPRINTF(sc, ATH_DBG_FATAL, 1892 DPRINTF(sc, ATH_DBG_FATAL,
1907 "%s: hal qnum %u out of range, max %u!\n", 1893 "qnum %u out of range, max %u!\n",
1908 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq)); 1894 qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
1909 ath9k_hw_releasetxqueue(ah, qnum); 1895 ath9k_hw_releasetxqueue(ah, qnum);
1910 return NULL; 1896 return NULL;
1911 } 1897 }
@@ -1950,8 +1936,8 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
1950 1936
1951 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { 1937 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
1952 DPRINTF(sc, ATH_DBG_FATAL, 1938 DPRINTF(sc, ATH_DBG_FATAL,
1953 "%s: HAL AC %u out of range, max %zu!\n", 1939 "HAL AC %u out of range, max %zu!\n",
1954 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q)); 1940 haltype, ARRAY_SIZE(sc->sc_haltype2q));
1955 return 0; 1941 return 0;
1956 } 1942 }
1957 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); 1943 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
@@ -1970,8 +1956,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
1970 case ATH9K_TX_QUEUE_DATA: 1956 case ATH9K_TX_QUEUE_DATA:
1971 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { 1957 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
1972 DPRINTF(sc, ATH_DBG_FATAL, 1958 DPRINTF(sc, ATH_DBG_FATAL,
1973 "%s: HAL AC %u out of range, max %zu!\n", 1959 "HAL AC %u out of range, max %zu!\n",
1974 __func__,
1975 haltype, ARRAY_SIZE(sc->sc_haltype2q)); 1960 haltype, ARRAY_SIZE(sc->sc_haltype2q));
1976 return -1; 1961 return -1;
1977 } 1962 }
@@ -2004,8 +1989,8 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
2004 /* Try to avoid running out of descriptors */ 1989 /* Try to avoid running out of descriptors */
2005 if (txq->axq_depth >= (ATH_TXBUF - 20)) { 1990 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
2006 DPRINTF(sc, ATH_DBG_FATAL, 1991 DPRINTF(sc, ATH_DBG_FATAL,
2007 "%s: TX queue: %d is full, depth: %d\n", 1992 "TX queue: %d is full, depth: %d\n",
2008 __func__, qnum, txq->axq_depth); 1993 qnum, txq->axq_depth);
2009 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); 1994 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
2010 txq->stopped = 1; 1995 txq->stopped = 1;
2011 spin_unlock_bh(&txq->axq_lock); 1996 spin_unlock_bh(&txq->axq_lock);
@@ -2047,8 +2032,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
2047 2032
2048 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 2033 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
2049 DPRINTF(sc, ATH_DBG_FATAL, 2034 DPRINTF(sc, ATH_DBG_FATAL,
2050 "%s: unable to update hardware queue %u!\n", 2035 "Unable to update hardware queue %u!\n", qnum);
2051 __func__, qnum);
2052 error = -EIO; 2036 error = -EIO;
2053 } else { 2037 } else {
2054 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */ 2038 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
@@ -2167,7 +2151,7 @@ void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2167 * we go to INIT state */ 2151 * we go to INIT state */
2168 if (!(sc->sc_flags & SC_OP_INVALID)) { 2152 if (!(sc->sc_flags & SC_OP_INVALID)) {
2169 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); 2153 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2170 DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__, 2154 DPRINTF(sc, ATH_DBG_XMIT, "beacon queue %x\n",
2171 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq)); 2155 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2172 } 2156 }
2173 2157
@@ -2267,8 +2251,6 @@ void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid)
2267 struct list_head bf_head; 2251 struct list_head bf_head;
2268 INIT_LIST_HEAD(&bf_head); 2252 INIT_LIST_HEAD(&bf_head);
2269 2253
2270 DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
2271
2272 if (txtid->state & AGGR_CLEANUP) /* cleanup is in progress */ 2254 if (txtid->state & AGGR_CLEANUP) /* cleanup is in progress */
2273 return; 2255 return;
2274 2256
@@ -2501,8 +2483,7 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2501 if (hdrlen & 3) { 2483 if (hdrlen & 3) {
2502 padsize = hdrlen % 4; 2484 padsize = hdrlen % 4;
2503 if (skb_headroom(skb) < padsize) { 2485 if (skb_headroom(skb) < padsize) {
2504 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding " 2486 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
2505 "failed\n", __func__);
2506 dev_kfree_skb_any(skb); 2487 dev_kfree_skb_any(skb);
2507 return; 2488 return;
2508 } 2489 }
@@ -2512,12 +2493,10 @@ void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2512 2493
2513 txctl.txq = sc->sc_cabq; 2494 txctl.txq = sc->sc_cabq;
2514 2495
2515 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n", 2496 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
2516 __func__,
2517 skb);
2518 2497
2519 if (ath_tx_start(sc, skb, &txctl) != 0) { 2498 if (ath_tx_start(sc, skb, &txctl) != 0) {
2520 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__); 2499 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
2521 goto exit; 2500 goto exit;
2522 } 2501 }
2523 2502
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 17:46:43 -0500