diff options
Diffstat (limited to 'drivers/net/wireless/zd1211rw/zd_chip.c')
-rw-r--r-- | drivers/net/wireless/zd1211rw/zd_chip.c | 126 |
1 files changed, 66 insertions, 60 deletions
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.c b/drivers/net/wireless/zd1211rw/zd_chip.c index 78ea72fb8f0c..12dfc0b6efe6 100644 --- a/drivers/net/wireless/zd1211rw/zd_chip.c +++ b/drivers/net/wireless/zd1211rw/zd_chip.c | |||
@@ -84,6 +84,18 @@ static void print_id(struct zd_chip *chip) | |||
84 | dev_info(zd_chip_dev(chip), "%s\n", buffer); | 84 | dev_info(zd_chip_dev(chip), "%s\n", buffer); |
85 | } | 85 | } |
86 | 86 | ||
87 | static zd_addr_t inc_addr(zd_addr_t addr) | ||
88 | { | ||
89 | u16 a = (u16)addr; | ||
90 | /* Control registers use byte addressing, but everything else uses word | ||
91 | * addressing. */ | ||
92 | if ((a & 0xf000) == CR_START) | ||
93 | a += 2; | ||
94 | else | ||
95 | a += 1; | ||
96 | return (zd_addr_t)a; | ||
97 | } | ||
98 | |||
87 | /* Read a variable number of 32-bit values. Parameter count is not allowed to | 99 | /* Read a variable number of 32-bit values. Parameter count is not allowed to |
88 | * exceed USB_MAX_IOREAD32_COUNT. | 100 | * exceed USB_MAX_IOREAD32_COUNT. |
89 | */ | 101 | */ |
@@ -114,7 +126,7 @@ int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr | |||
114 | for (i = 0; i < count; i++) { | 126 | for (i = 0; i < count; i++) { |
115 | int j = 2*i; | 127 | int j = 2*i; |
116 | /* We read the high word always first. */ | 128 | /* We read the high word always first. */ |
117 | a16[j] = zd_inc_word(addr[i]); | 129 | a16[j] = inc_addr(addr[i]); |
118 | a16[j+1] = addr[i]; | 130 | a16[j+1] = addr[i]; |
119 | } | 131 | } |
120 | 132 | ||
@@ -163,7 +175,7 @@ int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs, | |||
163 | j = 2*i; | 175 | j = 2*i; |
164 | /* We write the high word always first. */ | 176 | /* We write the high word always first. */ |
165 | ioreqs16[j].value = ioreqs[i].value >> 16; | 177 | ioreqs16[j].value = ioreqs[i].value >> 16; |
166 | ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr); | 178 | ioreqs16[j].addr = inc_addr(ioreqs[i].addr); |
167 | ioreqs16[j+1].value = ioreqs[i].value; | 179 | ioreqs16[j+1].value = ioreqs[i].value; |
168 | ioreqs16[j+1].addr = ioreqs[i].addr; | 180 | ioreqs16[j+1].addr = ioreqs[i].addr; |
169 | } | 181 | } |
@@ -466,7 +478,8 @@ static int read_values(struct zd_chip *chip, u8 *values, size_t count, | |||
466 | 478 | ||
467 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | 479 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
468 | for (i = 0;;) { | 480 | for (i = 0;;) { |
469 | r = zd_ioread32_locked(chip, &v, e2p_addr+i/2); | 481 | r = zd_ioread32_locked(chip, &v, |
482 | (zd_addr_t)((u16)e2p_addr+i/2)); | ||
470 | if (r) | 483 | if (r) |
471 | return r; | 484 | return r; |
472 | v -= guard; | 485 | v -= guard; |
@@ -798,47 +811,18 @@ static int hw_reset_phy(struct zd_chip *chip) | |||
798 | static int zd1211_hw_init_hmac(struct zd_chip *chip) | 811 | static int zd1211_hw_init_hmac(struct zd_chip *chip) |
799 | { | 812 | { |
800 | static const struct zd_ioreq32 ioreqs[] = { | 813 | static const struct zd_ioreq32 ioreqs[] = { |
801 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | ||
802 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | ||
803 | { CR_ZD1211_RETRY_MAX, 0x2 }, | 814 | { CR_ZD1211_RETRY_MAX, 0x2 }, |
804 | { CR_SNIFFER_ON, 0 }, | ||
805 | { CR_RX_FILTER, STA_RX_FILTER }, | ||
806 | { CR_GROUP_HASH_P1, 0x00 }, | ||
807 | { CR_GROUP_HASH_P2, 0x80000000 }, | ||
808 | { CR_REG1, 0xa4 }, | ||
809 | { CR_ADDA_PWR_DWN, 0x7f }, | ||
810 | { CR_BCN_PLCP_CFG, 0x00f00401 }, | ||
811 | { CR_PHY_DELAY, 0x00 }, | ||
812 | { CR_ACK_TIMEOUT_EXT, 0x80 }, | ||
813 | { CR_ADDA_PWR_DWN, 0x00 }, | ||
814 | { CR_ACK_TIME_80211, 0x100 }, | ||
815 | { CR_RX_PE_DELAY, 0x70 }, | ||
816 | { CR_PS_CTRL, 0x10000000 }, | ||
817 | { CR_RTS_CTS_RATE, 0x02030203 }, | ||
818 | { CR_RX_THRESHOLD, 0x000c0640 }, | 815 | { CR_RX_THRESHOLD, 0x000c0640 }, |
819 | { CR_AFTER_PNP, 0x1 }, | ||
820 | { CR_WEP_PROTECT, 0x114 }, | ||
821 | }; | 816 | }; |
822 | 817 | ||
823 | int r; | ||
824 | |||
825 | dev_dbg_f(zd_chip_dev(chip), "\n"); | 818 | dev_dbg_f(zd_chip_dev(chip), "\n"); |
826 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | 819 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
827 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | 820 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
828 | #ifdef DEBUG | ||
829 | if (r) { | ||
830 | dev_err(zd_chip_dev(chip), | ||
831 | "error in zd_iowrite32a_locked. Error number %d\n", r); | ||
832 | } | ||
833 | #endif /* DEBUG */ | ||
834 | return r; | ||
835 | } | 821 | } |
836 | 822 | ||
837 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) | 823 | static int zd1211b_hw_init_hmac(struct zd_chip *chip) |
838 | { | 824 | { |
839 | static const struct zd_ioreq32 ioreqs[] = { | 825 | static const struct zd_ioreq32 ioreqs[] = { |
840 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | ||
841 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | ||
842 | { CR_ZD1211B_RETRY_MAX, 0x02020202 }, | 826 | { CR_ZD1211B_RETRY_MAX, 0x02020202 }, |
843 | { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f }, | 827 | { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f }, |
844 | { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f }, | 828 | { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f }, |
@@ -847,6 +831,20 @@ static int zd1211b_hw_init_hmac(struct zd_chip *chip) | |||
847 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, | 831 | { CR_ZD1211B_AIFS_CTL1, 0x00280028 }, |
848 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, | 832 | { CR_ZD1211B_AIFS_CTL2, 0x008C003C }, |
849 | { CR_ZD1211B_TXOP, 0x01800824 }, | 833 | { CR_ZD1211B_TXOP, 0x01800824 }, |
834 | { CR_RX_THRESHOLD, 0x000c0eff, }, | ||
835 | }; | ||
836 | |||
837 | dev_dbg_f(zd_chip_dev(chip), "\n"); | ||
838 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | ||
839 | return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | ||
840 | } | ||
841 | |||
842 | static int hw_init_hmac(struct zd_chip *chip) | ||
843 | { | ||
844 | int r; | ||
845 | static const struct zd_ioreq32 ioreqs[] = { | ||
846 | { CR_ACK_TIMEOUT_EXT, 0x20 }, | ||
847 | { CR_ADDA_MBIAS_WARMTIME, 0x30000808 }, | ||
850 | { CR_SNIFFER_ON, 0 }, | 848 | { CR_SNIFFER_ON, 0 }, |
851 | { CR_RX_FILTER, STA_RX_FILTER }, | 849 | { CR_RX_FILTER, STA_RX_FILTER }, |
852 | { CR_GROUP_HASH_P1, 0x00 }, | 850 | { CR_GROUP_HASH_P1, 0x00 }, |
@@ -861,25 +859,16 @@ static int zd1211b_hw_init_hmac(struct zd_chip *chip) | |||
861 | { CR_RX_PE_DELAY, 0x70 }, | 859 | { CR_RX_PE_DELAY, 0x70 }, |
862 | { CR_PS_CTRL, 0x10000000 }, | 860 | { CR_PS_CTRL, 0x10000000 }, |
863 | { CR_RTS_CTS_RATE, 0x02030203 }, | 861 | { CR_RTS_CTS_RATE, 0x02030203 }, |
864 | { CR_RX_THRESHOLD, 0x000c0eff, }, | ||
865 | { CR_AFTER_PNP, 0x1 }, | 862 | { CR_AFTER_PNP, 0x1 }, |
866 | { CR_WEP_PROTECT, 0x114 }, | 863 | { CR_WEP_PROTECT, 0x114 }, |
864 | { CR_IFS_VALUE, IFS_VALUE_DEFAULT }, | ||
867 | }; | 865 | }; |
868 | 866 | ||
869 | int r; | ||
870 | |||
871 | dev_dbg_f(zd_chip_dev(chip), "\n"); | ||
872 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | 867 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); |
873 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); | 868 | r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs)); |
874 | if (r) { | 869 | if (r) |
875 | dev_dbg_f(zd_chip_dev(chip), | 870 | return r; |
876 | "error in zd_iowrite32a_locked. Error number %d\n", r); | ||
877 | } | ||
878 | return r; | ||
879 | } | ||
880 | 871 | ||
881 | static int hw_init_hmac(struct zd_chip *chip) | ||
882 | { | ||
883 | return chip->is_zd1211b ? | 872 | return chip->is_zd1211b ? |
884 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); | 873 | zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip); |
885 | } | 874 | } |
@@ -974,16 +963,14 @@ static int hw_init(struct zd_chip *chip) | |||
974 | if (r) | 963 | if (r) |
975 | return r; | 964 | return r; |
976 | 965 | ||
977 | /* Although the vendor driver defaults to a different value during | ||
978 | * init, it overwrites the IFS value with the following every time | ||
979 | * the channel changes. We should aim to be more intelligent... */ | ||
980 | r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE); | ||
981 | if (r) | ||
982 | return r; | ||
983 | |||
984 | return set_beacon_interval(chip, 100); | 966 | return set_beacon_interval(chip, 100); |
985 | } | 967 | } |
986 | 968 | ||
969 | static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset) | ||
970 | { | ||
971 | return (zd_addr_t)((u16)chip->fw_regs_base + offset); | ||
972 | } | ||
973 | |||
987 | #ifdef DEBUG | 974 | #ifdef DEBUG |
988 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, | 975 | static int dump_cr(struct zd_chip *chip, const zd_addr_t addr, |
989 | const char *addr_string) | 976 | const char *addr_string) |
@@ -1018,9 +1005,11 @@ static int test_init(struct zd_chip *chip) | |||
1018 | 1005 | ||
1019 | static void dump_fw_registers(struct zd_chip *chip) | 1006 | static void dump_fw_registers(struct zd_chip *chip) |
1020 | { | 1007 | { |
1021 | static const zd_addr_t addr[4] = { | 1008 | const zd_addr_t addr[4] = { |
1022 | FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE, | 1009 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER), |
1023 | FW_LINK_STATUS | 1010 | fw_reg_addr(chip, FW_REG_USB_SPEED), |
1011 | fw_reg_addr(chip, FW_REG_FIX_TX_RATE), | ||
1012 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), | ||
1024 | }; | 1013 | }; |
1025 | 1014 | ||
1026 | int r; | 1015 | int r; |
@@ -1046,7 +1035,8 @@ static int print_fw_version(struct zd_chip *chip) | |||
1046 | int r; | 1035 | int r; |
1047 | u16 version; | 1036 | u16 version; |
1048 | 1037 | ||
1049 | r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER); | 1038 | r = zd_ioread16_locked(chip, &version, |
1039 | fw_reg_addr(chip, FW_REG_FIRMWARE_VER)); | ||
1050 | if (r) | 1040 | if (r) |
1051 | return r; | 1041 | return r; |
1052 | 1042 | ||
@@ -1126,6 +1116,22 @@ int zd_chip_disable_hwint(struct zd_chip *chip) | |||
1126 | return r; | 1116 | return r; |
1127 | } | 1117 | } |
1128 | 1118 | ||
1119 | static int read_fw_regs_offset(struct zd_chip *chip) | ||
1120 | { | ||
1121 | int r; | ||
1122 | |||
1123 | ZD_ASSERT(mutex_is_locked(&chip->mutex)); | ||
1124 | r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base, | ||
1125 | FWRAW_REGS_ADDR); | ||
1126 | if (r) | ||
1127 | return r; | ||
1128 | dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n", | ||
1129 | (u16)chip->fw_regs_base); | ||
1130 | |||
1131 | return 0; | ||
1132 | } | ||
1133 | |||
1134 | |||
1129 | int zd_chip_init_hw(struct zd_chip *chip, u8 device_type) | 1135 | int zd_chip_init_hw(struct zd_chip *chip, u8 device_type) |
1130 | { | 1136 | { |
1131 | int r; | 1137 | int r; |
@@ -1145,7 +1151,7 @@ int zd_chip_init_hw(struct zd_chip *chip, u8 device_type) | |||
1145 | if (r) | 1151 | if (r) |
1146 | goto out; | 1152 | goto out; |
1147 | 1153 | ||
1148 | r = zd_usb_init_hw(&chip->usb); | 1154 | r = read_fw_regs_offset(chip); |
1149 | if (r) | 1155 | if (r) |
1150 | goto out; | 1156 | goto out; |
1151 | 1157 | ||
@@ -1325,15 +1331,15 @@ u8 zd_chip_get_channel(struct zd_chip *chip) | |||
1325 | 1331 | ||
1326 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) | 1332 | int zd_chip_control_leds(struct zd_chip *chip, enum led_status status) |
1327 | { | 1333 | { |
1328 | static const zd_addr_t a[] = { | 1334 | const zd_addr_t a[] = { |
1329 | FW_LINK_STATUS, | 1335 | fw_reg_addr(chip, FW_REG_LED_LINK_STATUS), |
1330 | CR_LED, | 1336 | CR_LED, |
1331 | }; | 1337 | }; |
1332 | 1338 | ||
1333 | int r; | 1339 | int r; |
1334 | u16 v[ARRAY_SIZE(a)]; | 1340 | u16 v[ARRAY_SIZE(a)]; |
1335 | struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { | 1341 | struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = { |
1336 | [0] = { FW_LINK_STATUS }, | 1342 | [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) }, |
1337 | [1] = { CR_LED }, | 1343 | [1] = { CR_LED }, |
1338 | }; | 1344 | }; |
1339 | u16 other_led; | 1345 | u16 other_led; |