diff options
Diffstat (limited to 'drivers/net/wireless/wl12xx/boot.h')
-rw-r--r-- | drivers/net/wireless/wl12xx/boot.h | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/drivers/net/wireless/wl12xx/boot.h b/drivers/net/wireless/wl12xx/boot.h index 17229b86fc71..e8f8255bbabe 100644 --- a/drivers/net/wireless/wl12xx/boot.h +++ b/drivers/net/wireless/wl12xx/boot.h | |||
@@ -74,4 +74,56 @@ struct wl1271_static_data { | |||
74 | #define FREF_CLK_POLARITY_BITS 0xfffff8ff | 74 | #define FREF_CLK_POLARITY_BITS 0xfffff8ff |
75 | #define CLK_REQ_OUTN_SEL 0x700 | 75 | #define CLK_REQ_OUTN_SEL 0x700 |
76 | 76 | ||
77 | /* PLL configuration algorithm for wl128x */ | ||
78 | #define SYS_CLK_CFG_REG 0x2200 | ||
79 | /* Bit[0] - 0-TCXO, 1-FREF */ | ||
80 | #define MCS_PLL_CLK_SEL_FREF BIT(0) | ||
81 | /* Bit[3:2] - 01-TCXO, 10-FREF */ | ||
82 | #define WL_CLK_REQ_TYPE_FREF BIT(3) | ||
83 | #define WL_CLK_REQ_TYPE_PG2 (BIT(3) | BIT(2)) | ||
84 | /* Bit[4] - 0-TCXO, 1-FREF */ | ||
85 | #define PRCM_CM_EN_MUX_WLAN_FREF BIT(4) | ||
86 | |||
87 | #define TCXO_ILOAD_INT_REG 0x2264 | ||
88 | #define TCXO_CLK_DETECT_REG 0x2266 | ||
89 | |||
90 | #define TCXO_DET_FAILED BIT(4) | ||
91 | |||
92 | #define FREF_ILOAD_INT_REG 0x2084 | ||
93 | #define FREF_CLK_DETECT_REG 0x2086 | ||
94 | #define FREF_CLK_DETECT_FAIL BIT(4) | ||
95 | |||
96 | /* Use this reg for masking during driver access */ | ||
97 | #define WL_SPARE_REG 0x2320 | ||
98 | #define WL_SPARE_VAL BIT(2) | ||
99 | /* Bit[6:5:3] - mask wl write SYS_CLK_CFG[8:5:2:4] */ | ||
100 | #define WL_SPARE_MASK_8526 (BIT(6) | BIT(5) | BIT(3)) | ||
101 | |||
102 | #define PLL_LOCK_COUNTERS_REG 0xD8C | ||
103 | #define PLL_LOCK_COUNTERS_COEX 0x0F | ||
104 | #define PLL_LOCK_COUNTERS_MCS 0xF0 | ||
105 | #define MCS_PLL_OVERRIDE_REG 0xD90 | ||
106 | #define MCS_PLL_CONFIG_REG 0xD92 | ||
107 | #define MCS_SEL_IN_FREQ_MASK 0x0070 | ||
108 | #define MCS_SEL_IN_FREQ_SHIFT 4 | ||
109 | #define MCS_PLL_CONFIG_REG_VAL 0x73 | ||
110 | #define MCS_PLL_ENABLE_HP (BIT(0) | BIT(1)) | ||
111 | |||
112 | #define MCS_PLL_M_REG 0xD94 | ||
113 | #define MCS_PLL_N_REG 0xD96 | ||
114 | #define MCS_PLL_M_REG_VAL 0xC8 | ||
115 | #define MCS_PLL_N_REG_VAL 0x07 | ||
116 | |||
117 | #define SDIO_IO_DS 0xd14 | ||
118 | |||
119 | /* SDIO/wSPI DS configuration values */ | ||
120 | enum { | ||
121 | HCI_IO_DS_8MA = 0, | ||
122 | HCI_IO_DS_4MA = 1, /* default */ | ||
123 | HCI_IO_DS_6MA = 2, | ||
124 | HCI_IO_DS_2MA = 3, | ||
125 | }; | ||
126 | |||
127 | /* end PLL configuration algorithm for wl128x */ | ||
128 | |||
77 | #endif | 129 | #endif |