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diff --git a/drivers/net/wireless/wl1251/acx.h b/drivers/net/wireless/wl1251/acx.h
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1/*
2 * This file is part of wl1251
3 *
4 * Copyright (c) 1998-2007 Texas Instruments Incorporated
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 */
22
23#ifndef __WL1251_ACX_H__
24#define __WL1251_ACX_H__
25
26#include "wl1251.h"
27#include "cmd.h"
28
29/* Target's information element */
30struct acx_header {
31 struct wl1251_cmd_header cmd;
32
33 /* acx (or information element) header */
34 u16 id;
35
36 /* payload length (not including headers */
37 u16 len;
38} __packed;
39
40struct acx_error_counter {
41 struct acx_header header;
42
43 /* The number of PLCP errors since the last time this */
44 /* information element was interrogated. This field is */
45 /* automatically cleared when it is interrogated.*/
46 u32 PLCP_error;
47
48 /* The number of FCS errors since the last time this */
49 /* information element was interrogated. This field is */
50 /* automatically cleared when it is interrogated.*/
51 u32 FCS_error;
52
53 /* The number of MPDUs without PLCP header errors received*/
54 /* since the last time this information element was interrogated. */
55 /* This field is automatically cleared when it is interrogated.*/
56 u32 valid_frame;
57
58 /* the number of missed sequence numbers in the squentially */
59 /* values of frames seq numbers */
60 u32 seq_num_miss;
61} __packed;
62
63struct acx_revision {
64 struct acx_header header;
65
66 /*
67 * The WiLink firmware version, an ASCII string x.x.x.x,
68 * that uniquely identifies the current firmware.
69 * The left most digit is incremented each time a
70 * significant change is made to the firmware, such as
71 * code redesign or new platform support.
72 * The second digit is incremented when major enhancements
73 * are added or major fixes are made.
74 * The third digit is incremented for each GA release.
75 * The fourth digit is incremented for each build.
76 * The first two digits identify a firmware release version,
77 * in other words, a unique set of features.
78 * The first three digits identify a GA release.
79 */
80 char fw_version[20];
81
82 /*
83 * This 4 byte field specifies the WiLink hardware version.
84 * bits 0 - 15: Reserved.
85 * bits 16 - 23: Version ID - The WiLink version ID
86 * (1 = first spin, 2 = second spin, and so on).
87 * bits 24 - 31: Chip ID - The WiLink chip ID.
88 */
89 u32 hw_version;
90} __packed;
91
92enum wl1251_psm_mode {
93 /* Active mode */
94 WL1251_PSM_CAM = 0,
95
96 /* Power save mode */
97 WL1251_PSM_PS = 1,
98
99 /* Extreme low power */
100 WL1251_PSM_ELP = 2,
101};
102
103struct acx_sleep_auth {
104 struct acx_header header;
105
106 /* The sleep level authorization of the device. */
107 /* 0 - Always active*/
108 /* 1 - Power down mode: light / fast sleep*/
109 /* 2 - ELP mode: Deep / Max sleep*/
110 u8 sleep_auth;
111 u8 padding[3];
112} __packed;
113
114enum {
115 HOSTIF_PCI_MASTER_HOST_INDIRECT,
116 HOSTIF_PCI_MASTER_HOST_DIRECT,
117 HOSTIF_SLAVE,
118 HOSTIF_PKT_RING,
119 HOSTIF_DONTCARE = 0xFF
120};
121
122#define DEFAULT_UCAST_PRIORITY 0
123#define DEFAULT_RX_Q_PRIORITY 0
124#define DEFAULT_NUM_STATIONS 1
125#define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
126#define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
127#define TRACE_BUFFER_MAX_SIZE 256
128
129#define DP_RX_PACKET_RING_CHUNK_SIZE 1600
130#define DP_TX_PACKET_RING_CHUNK_SIZE 1600
131#define DP_RX_PACKET_RING_CHUNK_NUM 2
132#define DP_TX_PACKET_RING_CHUNK_NUM 2
133#define DP_TX_COMPLETE_TIME_OUT 20
134#define FW_TX_CMPLT_BLOCK_SIZE 16
135
136struct acx_data_path_params {
137 struct acx_header header;
138
139 u16 rx_packet_ring_chunk_size;
140 u16 tx_packet_ring_chunk_size;
141
142 u8 rx_packet_ring_chunk_num;
143 u8 tx_packet_ring_chunk_num;
144
145 /*
146 * Maximum number of packets that can be gathered
147 * in the TX complete ring before an interrupt
148 * is generated.
149 */
150 u8 tx_complete_threshold;
151
152 /* Number of pending TX complete entries in cyclic ring.*/
153 u8 tx_complete_ring_depth;
154
155 /*
156 * Max num microseconds since a packet enters the TX
157 * complete ring until an interrupt is generated.
158 */
159 u32 tx_complete_timeout;
160} __packed;
161
162
163struct acx_data_path_params_resp {
164 struct acx_header header;
165
166 u16 rx_packet_ring_chunk_size;
167 u16 tx_packet_ring_chunk_size;
168
169 u8 rx_packet_ring_chunk_num;
170 u8 tx_packet_ring_chunk_num;
171
172 u8 pad[2];
173
174 u32 rx_packet_ring_addr;
175 u32 tx_packet_ring_addr;
176
177 u32 rx_control_addr;
178 u32 tx_control_addr;
179
180 u32 tx_complete_addr;
181} __packed;
182
183#define TX_MSDU_LIFETIME_MIN 0
184#define TX_MSDU_LIFETIME_MAX 3000
185#define TX_MSDU_LIFETIME_DEF 512
186#define RX_MSDU_LIFETIME_MIN 0
187#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
188#define RX_MSDU_LIFETIME_DEF 512000
189
190struct acx_rx_msdu_lifetime {
191 struct acx_header header;
192
193 /*
194 * The maximum amount of time, in TU, before the
195 * firmware discards the MSDU.
196 */
197 u32 lifetime;
198} __packed;
199
200/*
201 * RX Config Options Table
202 * Bit Definition
203 * === ==========
204 * 31:14 Reserved
205 * 13 Copy RX Status - when set, write three receive status words
206 * to top of rx'd MPDUs.
207 * When cleared, do not write three status words (added rev 1.5)
208 * 12 Reserved
209 * 11 RX Complete upon FCS error - when set, give rx complete
210 * interrupt for FCS errors, after the rx filtering, e.g. unicast
211 * frames not to us with FCS error will not generate an interrupt.
212 * 10 SSID Filter Enable - When set, the WiLink discards all beacon,
213 * probe request, and probe response frames with an SSID that does
214 * not match the SSID specified by the host in the START/JOIN
215 * command.
216 * When clear, the WiLink receives frames with any SSID.
217 * 9 Broadcast Filter Enable - When set, the WiLink discards all
218 * broadcast frames. When clear, the WiLink receives all received
219 * broadcast frames.
220 * 8:6 Reserved
221 * 5 BSSID Filter Enable - When set, the WiLink discards any frames
222 * with a BSSID that does not match the BSSID specified by the
223 * host.
224 * When clear, the WiLink receives frames from any BSSID.
225 * 4 MAC Addr Filter - When set, the WiLink discards any frames
226 * with a destination address that does not match the MAC address
227 * of the adaptor.
228 * When clear, the WiLink receives frames destined to any MAC
229 * address.
230 * 3 Promiscuous - When set, the WiLink receives all valid frames
231 * (i.e., all frames that pass the FCS check).
232 * When clear, only frames that pass the other filters specified
233 * are received.
234 * 2 FCS - When set, the WiLink includes the FCS with the received
235 * frame.
236 * When cleared, the FCS is discarded.
237 * 1 PLCP header - When set, write all data from baseband to frame
238 * buffer including PHY header.
239 * 0 Reserved - Always equal to 0.
240 *
241 * RX Filter Options Table
242 * Bit Definition
243 * === ==========
244 * 31:12 Reserved - Always equal to 0.
245 * 11 Association - When set, the WiLink receives all association
246 * related frames (association request/response, reassocation
247 * request/response, and disassociation). When clear, these frames
248 * are discarded.
249 * 10 Auth/De auth - When set, the WiLink receives all authentication
250 * and de-authentication frames. When clear, these frames are
251 * discarded.
252 * 9 Beacon - When set, the WiLink receives all beacon frames.
253 * When clear, these frames are discarded.
254 * 8 Contention Free - When set, the WiLink receives all contention
255 * free frames.
256 * When clear, these frames are discarded.
257 * 7 Control - When set, the WiLink receives all control frames.
258 * When clear, these frames are discarded.
259 * 6 Data - When set, the WiLink receives all data frames.
260 * When clear, these frames are discarded.
261 * 5 FCS Error - When set, the WiLink receives frames that have FCS
262 * errors.
263 * When clear, these frames are discarded.
264 * 4 Management - When set, the WiLink receives all management
265 * frames.
266 * When clear, these frames are discarded.
267 * 3 Probe Request - When set, the WiLink receives all probe request
268 * frames.
269 * When clear, these frames are discarded.
270 * 2 Probe Response - When set, the WiLink receives all probe
271 * response frames.
272 * When clear, these frames are discarded.
273 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
274 * frames.
275 * When clear, these frames are discarded.
276 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames
277 * that have reserved frame types and sub types as defined by the
278 * 802.11 specification.
279 * When clear, these frames are discarded.
280 */
281struct acx_rx_config {
282 struct acx_header header;
283
284 u32 config_options;
285 u32 filter_options;
286} __packed;
287
288enum {
289 QOS_AC_BE = 0,
290 QOS_AC_BK,
291 QOS_AC_VI,
292 QOS_AC_VO,
293 QOS_HIGHEST_AC_INDEX = QOS_AC_VO,
294};
295
296#define MAX_NUM_OF_AC (QOS_HIGHEST_AC_INDEX+1)
297#define FIRST_AC_INDEX QOS_AC_BE
298#define MAX_NUM_OF_802_1d_TAGS 8
299#define AC_PARAMS_MAX_TSID 15
300#define MAX_APSD_CONF 0xffff
301
302#define QOS_TX_HIGH_MIN (0)
303#define QOS_TX_HIGH_MAX (100)
304
305#define QOS_TX_HIGH_BK_DEF (25)
306#define QOS_TX_HIGH_BE_DEF (35)
307#define QOS_TX_HIGH_VI_DEF (35)
308#define QOS_TX_HIGH_VO_DEF (35)
309
310#define QOS_TX_LOW_BK_DEF (15)
311#define QOS_TX_LOW_BE_DEF (25)
312#define QOS_TX_LOW_VI_DEF (25)
313#define QOS_TX_LOW_VO_DEF (25)
314
315struct acx_tx_queue_qos_config {
316 struct acx_header header;
317
318 u8 qid;
319 u8 pad[3];
320
321 /* Max number of blocks allowd in the queue */
322 u16 high_threshold;
323
324 /* Lowest memory blocks guaranteed for this queue */
325 u16 low_threshold;
326} __packed;
327
328struct acx_packet_detection {
329 struct acx_header header;
330
331 u32 threshold;
332} __packed;
333
334
335enum acx_slot_type {
336 SLOT_TIME_LONG = 0,
337 SLOT_TIME_SHORT = 1,
338 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
339 MAX_SLOT_TIMES = 0xFF
340};
341
342#define STATION_WONE_INDEX 0
343
344struct acx_slot {
345 struct acx_header header;
346
347 u8 wone_index; /* Reserved */
348 u8 slot_time;
349 u8 reserved[6];
350} __packed;
351
352
353#define ADDRESS_GROUP_MAX (8)
354#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ADDRESS_GROUP_MAX)
355
356struct acx_dot11_grp_addr_tbl {
357 struct acx_header header;
358
359 u8 enabled;
360 u8 num_groups;
361 u8 pad[2];
362 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
363} __packed;
364
365
366#define RX_TIMEOUT_PS_POLL_MIN 0
367#define RX_TIMEOUT_PS_POLL_MAX (200000)
368#define RX_TIMEOUT_PS_POLL_DEF (15)
369#define RX_TIMEOUT_UPSD_MIN 0
370#define RX_TIMEOUT_UPSD_MAX (200000)
371#define RX_TIMEOUT_UPSD_DEF (15)
372
373struct acx_rx_timeout {
374 struct acx_header header;
375
376 /*
377 * The longest time the STA will wait to receive
378 * traffic from the AP after a PS-poll has been
379 * transmitted.
380 */
381 u16 ps_poll_timeout;
382
383 /*
384 * The longest time the STA will wait to receive
385 * traffic from the AP after a frame has been sent
386 * from an UPSD enabled queue.
387 */
388 u16 upsd_timeout;
389} __packed;
390
391#define RTS_THRESHOLD_MIN 0
392#define RTS_THRESHOLD_MAX 4096
393#define RTS_THRESHOLD_DEF 2347
394
395struct acx_rts_threshold {
396 struct acx_header header;
397
398 u16 threshold;
399 u8 pad[2];
400} __packed;
401
402struct acx_beacon_filter_option {
403 struct acx_header header;
404
405 u8 enable;
406
407 /*
408 * The number of beacons without the unicast TIM
409 * bit set that the firmware buffers before
410 * signaling the host about ready frames.
411 * When set to 0 and the filter is enabled, beacons
412 * without the unicast TIM bit set are dropped.
413 */
414 u8 max_num_beacons;
415 u8 pad[2];
416} __packed;
417
418/*
419 * ACXBeaconFilterEntry (not 221)
420 * Byte Offset Size (Bytes) Definition
421 * =========== ============ ==========
422 * 0 1 IE identifier
423 * 1 1 Treatment bit mask
424 *
425 * ACXBeaconFilterEntry (221)
426 * Byte Offset Size (Bytes) Definition
427 * =========== ============ ==========
428 * 0 1 IE identifier
429 * 1 1 Treatment bit mask
430 * 2 3 OUI
431 * 5 1 Type
432 * 6 2 Version
433 *
434 *
435 * Treatment bit mask - The information element handling:
436 * bit 0 - The information element is compared and transferred
437 * in case of change.
438 * bit 1 - The information element is transferred to the host
439 * with each appearance or disappearance.
440 * Note that both bits can be set at the same time.
441 */
442#define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
443#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
444#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
445#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
446#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
447 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
448 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
449 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
450
451#define BEACON_RULE_PASS_ON_CHANGE BIT(0)
452#define BEACON_RULE_PASS_ON_APPEARANCE BIT(1)
453
454#define BEACON_FILTER_IE_ID_CHANNEL_SWITCH_ANN (37)
455
456struct acx_beacon_filter_ie_table {
457 struct acx_header header;
458
459 u8 num_ie;
460 u8 pad[3];
461 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
462} __packed;
463
464#define SYNCH_FAIL_DEFAULT_THRESHOLD 10 /* number of beacons */
465#define NO_BEACON_DEFAULT_TIMEOUT (500) /* in microseconds */
466
467struct acx_conn_monit_params {
468 struct acx_header header;
469
470 u32 synch_fail_thold; /* number of beacons missed */
471 u32 bss_lose_timeout; /* number of TU's from synch fail */
472} __packed;
473
474enum {
475 SG_ENABLE = 0,
476 SG_DISABLE,
477 SG_SENSE_NO_ACTIVITY,
478 SG_SENSE_ACTIVE
479};
480
481struct acx_bt_wlan_coex {
482 struct acx_header header;
483
484 /*
485 * 0 -> PTA enabled
486 * 1 -> PTA disabled
487 * 2 -> sense no active mode, i.e.
488 * an interrupt is sent upon
489 * BT activity.
490 * 3 -> PTA is switched on in response
491 * to the interrupt sending.
492 */
493 u8 enable;
494 u8 pad[3];
495} __packed;
496
497#define PTA_ANTENNA_TYPE_DEF (0)
498#define PTA_BT_HP_MAXTIME_DEF (2000)
499#define PTA_WLAN_HP_MAX_TIME_DEF (5000)
500#define PTA_SENSE_DISABLE_TIMER_DEF (1350)
501#define PTA_PROTECTIVE_RX_TIME_DEF (1500)
502#define PTA_PROTECTIVE_TX_TIME_DEF (1500)
503#define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000)
504#define PTA_SIGNALING_TYPE_DEF (1)
505#define PTA_AFH_LEVERAGE_ON_DEF (0)
506#define PTA_NUMBER_QUIET_CYCLE_DEF (0)
507#define PTA_MAX_NUM_CTS_DEF (3)
508#define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2)
509#define PTA_NUMBER_OF_BT_PACKETS_DEF (2)
510#define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500)
511#define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000)
512#define PTA_CYCLE_TIME_FAST_DEF (8700)
513#define PTA_RX_FOR_AVALANCHE_DEF (5)
514#define PTA_ELP_HP_DEF (0)
515#define PTA_ANTI_STARVE_PERIOD_DEF (500)
516#define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4)
517#define PTA_ALLOW_PA_SD_DEF (1)
518#define PTA_TIME_BEFORE_BEACON_DEF (6300)
519#define PTA_HPDM_MAX_TIME_DEF (1600)
520#define PTA_TIME_OUT_NEXT_WLAN_DEF (2550)
521#define PTA_AUTO_MODE_NO_CTS_DEF (0)
522#define PTA_BT_HP_RESPECTED_DEF (3)
523#define PTA_WLAN_RX_MIN_RATE_DEF (24)
524#define PTA_ACK_MODE_DEF (1)
525
526struct acx_bt_wlan_coex_param {
527 struct acx_header header;
528
529 /*
530 * The minimum rate of a received WLAN packet in the STA,
531 * during protective mode, of which a new BT-HP request
532 * during this Rx will always be respected and gain the antenna.
533 */
534 u32 min_rate;
535
536 /* Max time the BT HP will be respected. */
537 u16 bt_hp_max_time;
538
539 /* Max time the WLAN HP will be respected. */
540 u16 wlan_hp_max_time;
541
542 /*
543 * The time between the last BT activity
544 * and the moment when the sense mode returns
545 * to SENSE_INACTIVE.
546 */
547 u16 sense_disable_timer;
548
549 /* Time before the next BT HP instance */
550 u16 rx_time_bt_hp;
551 u16 tx_time_bt_hp;
552
553 /* range: 10-20000 default: 1500 */
554 u16 rx_time_bt_hp_fast;
555 u16 tx_time_bt_hp_fast;
556
557 /* range: 2000-65535 default: 8700 */
558 u16 wlan_cycle_fast;
559
560 /* range: 0 - 15000 (Msec) default: 1000 */
561 u16 bt_anti_starvation_period;
562
563 /* range 400-10000(Usec) default: 3000 */
564 u16 next_bt_lp_packet;
565
566 /* Deafult: worst case for BT DH5 traffic */
567 u16 wake_up_beacon;
568
569 /* range: 0-50000(Usec) default: 1050 */
570 u16 hp_dm_max_guard_time;
571
572 /*
573 * This is to prevent both BT & WLAN antenna
574 * starvation.
575 * Range: 100-50000(Usec) default:2550
576 */
577 u16 next_wlan_packet;
578
579 /* 0 -> shared antenna */
580 u8 antenna_type;
581
582 /*
583 * 0 -> TI legacy
584 * 1 -> Palau
585 */
586 u8 signal_type;
587
588 /*
589 * BT AFH status
590 * 0 -> no AFH
591 * 1 -> from dedicated GPIO
592 * 2 -> AFH on (from host)
593 */
594 u8 afh_leverage_on;
595
596 /*
597 * The number of cycles during which no
598 * TX will be sent after 1 cycle of RX
599 * transaction in protective mode
600 */
601 u8 quiet_cycle_num;
602
603 /*
604 * The maximum number of CTSs that will
605 * be sent for receiving RX packet in
606 * protective mode
607 */
608 u8 max_cts;
609
610 /*
611 * The number of WLAN packets
612 * transferred in common mode before
613 * switching to BT.
614 */
615 u8 wlan_packets_num;
616
617 /*
618 * The number of BT packets
619 * transferred in common mode before
620 * switching to WLAN.
621 */
622 u8 bt_packets_num;
623
624 /* range: 1-255 default: 5 */
625 u8 missed_rx_avalanche;
626
627 /* range: 0-1 default: 1 */
628 u8 wlan_elp_hp;
629
630 /* range: 0 - 15 default: 4 */
631 u8 bt_anti_starvation_cycles;
632
633 u8 ack_mode_dual_ant;
634
635 /*
636 * Allow PA_SD assertion/de-assertion
637 * during enabled BT activity.
638 */
639 u8 pa_sd_enable;
640
641 /*
642 * Enable/Disable PTA in auto mode:
643 * Support Both Active & P.S modes
644 */
645 u8 pta_auto_mode_enable;
646
647 /* range: 0 - 20 default: 1 */
648 u8 bt_hp_respected_num;
649} __packed;
650
651#define CCA_THRSH_ENABLE_ENERGY_D 0x140A
652#define CCA_THRSH_DISABLE_ENERGY_D 0xFFEF
653
654struct acx_energy_detection {
655 struct acx_header header;
656
657 /* The RX Clear Channel Assessment threshold in the PHY */
658 u16 rx_cca_threshold;
659 u8 tx_energy_detection;
660 u8 pad;
661} __packed;
662
663#define BCN_RX_TIMEOUT_DEF_VALUE 10000
664#define BROADCAST_RX_TIMEOUT_DEF_VALUE 20000
665#define RX_BROADCAST_IN_PS_DEF_VALUE 1
666#define CONSECUTIVE_PS_POLL_FAILURE_DEF 4
667
668struct acx_beacon_broadcast {
669 struct acx_header header;
670
671 u16 beacon_rx_timeout;
672 u16 broadcast_timeout;
673
674 /* Enables receiving of broadcast packets in PS mode */
675 u8 rx_broadcast_in_ps;
676
677 /* Consecutive PS Poll failures before updating the host */
678 u8 ps_poll_threshold;
679 u8 pad[2];
680} __packed;
681
682struct acx_event_mask {
683 struct acx_header header;
684
685 u32 event_mask;
686 u32 high_event_mask; /* Unused */
687} __packed;
688
689#define CFG_RX_FCS BIT(2)
690#define CFG_RX_ALL_GOOD BIT(3)
691#define CFG_UNI_FILTER_EN BIT(4)
692#define CFG_BSSID_FILTER_EN BIT(5)
693#define CFG_MC_FILTER_EN BIT(6)
694#define CFG_MC_ADDR0_EN BIT(7)
695#define CFG_MC_ADDR1_EN BIT(8)
696#define CFG_BC_REJECT_EN BIT(9)
697#define CFG_SSID_FILTER_EN BIT(10)
698#define CFG_RX_INT_FCS_ERROR BIT(11)
699#define CFG_RX_INT_ENCRYPTED BIT(12)
700#define CFG_RX_WR_RX_STATUS BIT(13)
701#define CFG_RX_FILTER_NULTI BIT(14)
702#define CFG_RX_RESERVE BIT(15)
703#define CFG_RX_TIMESTAMP_TSF BIT(16)
704
705#define CFG_RX_RSV_EN BIT(0)
706#define CFG_RX_RCTS_ACK BIT(1)
707#define CFG_RX_PRSP_EN BIT(2)
708#define CFG_RX_PREQ_EN BIT(3)
709#define CFG_RX_MGMT_EN BIT(4)
710#define CFG_RX_FCS_ERROR BIT(5)
711#define CFG_RX_DATA_EN BIT(6)
712#define CFG_RX_CTL_EN BIT(7)
713#define CFG_RX_CF_EN BIT(8)
714#define CFG_RX_BCN_EN BIT(9)
715#define CFG_RX_AUTH_EN BIT(10)
716#define CFG_RX_ASSOC_EN BIT(11)
717
718#define SCAN_PASSIVE BIT(0)
719#define SCAN_5GHZ_BAND BIT(1)
720#define SCAN_TRIGGERED BIT(2)
721#define SCAN_PRIORITY_HIGH BIT(3)
722
723struct acx_fw_gen_frame_rates {
724 struct acx_header header;
725
726 u8 tx_ctrl_frame_rate; /* RATE_* */
727 u8 tx_ctrl_frame_mod; /* CCK_* or PBCC_* */
728 u8 tx_mgt_frame_rate;
729 u8 tx_mgt_frame_mod;
730} __packed;
731
732/* STA MAC */
733struct acx_dot11_station_id {
734 struct acx_header header;
735
736 u8 mac[ETH_ALEN];
737 u8 pad[2];
738} __packed;
739
740struct acx_feature_config {
741 struct acx_header header;
742
743 u32 options;
744 u32 data_flow_options;
745} __packed;
746
747struct acx_current_tx_power {
748 struct acx_header header;
749
750 u8 current_tx_power;
751 u8 padding[3];
752} __packed;
753
754struct acx_dot11_default_key {
755 struct acx_header header;
756
757 u8 id;
758 u8 pad[3];
759} __packed;
760
761struct acx_tsf_info {
762 struct acx_header header;
763
764 u32 current_tsf_msb;
765 u32 current_tsf_lsb;
766 u32 last_TBTT_msb;
767 u32 last_TBTT_lsb;
768 u8 last_dtim_count;
769 u8 pad[3];
770} __packed;
771
772enum acx_wake_up_event {
773 WAKE_UP_EVENT_BEACON_BITMAP = 0x01, /* Wake on every Beacon*/
774 WAKE_UP_EVENT_DTIM_BITMAP = 0x02, /* Wake on every DTIM*/
775 WAKE_UP_EVENT_N_DTIM_BITMAP = 0x04, /* Wake on every Nth DTIM */
776 WAKE_UP_EVENT_N_BEACONS_BITMAP = 0x08, /* Wake on every Nth Beacon */
777 WAKE_UP_EVENT_BITS_MASK = 0x0F
778};
779
780struct acx_wake_up_condition {
781 struct acx_header header;
782
783 u8 wake_up_event; /* Only one bit can be set */
784 u8 listen_interval;
785 u8 pad[2];
786} __packed;
787
788struct acx_aid {
789 struct acx_header header;
790
791 /*
792 * To be set when associated with an AP.
793 */
794 u16 aid;
795 u8 pad[2];
796} __packed;
797
798enum acx_preamble_type {
799 ACX_PREAMBLE_LONG = 0,
800 ACX_PREAMBLE_SHORT = 1
801};
802
803struct acx_preamble {
804 struct acx_header header;
805
806 /*
807 * When set, the WiLink transmits the frames with a short preamble and
808 * when cleared, the WiLink transmits the frames with a long preamble.
809 */
810 u8 preamble;
811 u8 padding[3];
812} __packed;
813
814enum acx_ctsprotect_type {
815 CTSPROTECT_DISABLE = 0,
816 CTSPROTECT_ENABLE = 1
817};
818
819struct acx_ctsprotect {
820 struct acx_header header;
821 u8 ctsprotect;
822 u8 padding[3];
823} __packed;
824
825struct acx_tx_statistics {
826 u32 internal_desc_overflow;
827} __packed;
828
829struct acx_rx_statistics {
830 u32 out_of_mem;
831 u32 hdr_overflow;
832 u32 hw_stuck;
833 u32 dropped;
834 u32 fcs_err;
835 u32 xfr_hint_trig;
836 u32 path_reset;
837 u32 reset_counter;
838} __packed;
839
840struct acx_dma_statistics {
841 u32 rx_requested;
842 u32 rx_errors;
843 u32 tx_requested;
844 u32 tx_errors;
845} __packed;
846
847struct acx_isr_statistics {
848 /* host command complete */
849 u32 cmd_cmplt;
850
851 /* fiqisr() */
852 u32 fiqs;
853
854 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
855 u32 rx_headers;
856
857 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
858 u32 rx_completes;
859
860 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
861 u32 rx_mem_overflow;
862
863 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
864 u32 rx_rdys;
865
866 /* irqisr() */
867 u32 irqs;
868
869 /* (INT_STS_ND & INT_TRIG_TX_PROC) */
870 u32 tx_procs;
871
872 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
873 u32 decrypt_done;
874
875 /* (INT_STS_ND & INT_TRIG_DMA0) */
876 u32 dma0_done;
877
878 /* (INT_STS_ND & INT_TRIG_DMA1) */
879 u32 dma1_done;
880
881 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
882 u32 tx_exch_complete;
883
884 /* (INT_STS_ND & INT_TRIG_COMMAND) */
885 u32 commands;
886
887 /* (INT_STS_ND & INT_TRIG_RX_PROC) */
888 u32 rx_procs;
889
890 /* (INT_STS_ND & INT_TRIG_PM_802) */
891 u32 hw_pm_mode_changes;
892
893 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
894 u32 host_acknowledges;
895
896 /* (INT_STS_ND & INT_TRIG_PM_PCI) */
897 u32 pci_pm;
898
899 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
900 u32 wakeups;
901
902 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
903 u32 low_rssi;
904} __packed;
905
906struct acx_wep_statistics {
907 /* WEP address keys configured */
908 u32 addr_key_count;
909
910 /* default keys configured */
911 u32 default_key_count;
912
913 u32 reserved;
914
915 /* number of times that WEP key not found on lookup */
916 u32 key_not_found;
917
918 /* number of times that WEP key decryption failed */
919 u32 decrypt_fail;
920
921 /* WEP packets decrypted */
922 u32 packets;
923
924 /* WEP decrypt interrupts */
925 u32 interrupt;
926} __packed;
927
928#define ACX_MISSED_BEACONS_SPREAD 10
929
930struct acx_pwr_statistics {
931 /* the amount of enters into power save mode (both PD & ELP) */
932 u32 ps_enter;
933
934 /* the amount of enters into ELP mode */
935 u32 elp_enter;
936
937 /* the amount of missing beacon interrupts to the host */
938 u32 missing_bcns;
939
940 /* the amount of wake on host-access times */
941 u32 wake_on_host;
942
943 /* the amount of wake on timer-expire */
944 u32 wake_on_timer_exp;
945
946 /* the number of packets that were transmitted with PS bit set */
947 u32 tx_with_ps;
948
949 /* the number of packets that were transmitted with PS bit clear */
950 u32 tx_without_ps;
951
952 /* the number of received beacons */
953 u32 rcvd_beacons;
954
955 /* the number of entering into PowerOn (power save off) */
956 u32 power_save_off;
957
958 /* the number of entries into power save mode */
959 u16 enable_ps;
960
961 /*
962 * the number of exits from power save, not including failed PS
963 * transitions
964 */
965 u16 disable_ps;
966
967 /*
968 * the number of times the TSF counter was adjusted because
969 * of drift
970 */
971 u32 fix_tsf_ps;
972
973 /* Gives statistics about the spread continuous missed beacons.
974 * The 16 LSB are dedicated for the PS mode.
975 * The 16 MSB are dedicated for the PS mode.
976 * cont_miss_bcns_spread[0] - single missed beacon.
977 * cont_miss_bcns_spread[1] - two continuous missed beacons.
978 * cont_miss_bcns_spread[2] - three continuous missed beacons.
979 * ...
980 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
981 */
982 u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
983
984 /* the number of beacons in awake mode */
985 u32 rcvd_awake_beacons;
986} __packed;
987
988struct acx_mic_statistics {
989 u32 rx_pkts;
990 u32 calc_failure;
991} __packed;
992
993struct acx_aes_statistics {
994 u32 encrypt_fail;
995 u32 decrypt_fail;
996 u32 encrypt_packets;
997 u32 decrypt_packets;
998 u32 encrypt_interrupt;
999 u32 decrypt_interrupt;
1000} __packed;
1001
1002struct acx_event_statistics {
1003 u32 heart_beat;
1004 u32 calibration;
1005 u32 rx_mismatch;
1006 u32 rx_mem_empty;
1007 u32 rx_pool;
1008 u32 oom_late;
1009 u32 phy_transmit_error;
1010 u32 tx_stuck;
1011} __packed;
1012
1013struct acx_ps_statistics {
1014 u32 pspoll_timeouts;
1015 u32 upsd_timeouts;
1016 u32 upsd_max_sptime;
1017 u32 upsd_max_apturn;
1018 u32 pspoll_max_apturn;
1019 u32 pspoll_utilization;
1020 u32 upsd_utilization;
1021} __packed;
1022
1023struct acx_rxpipe_statistics {
1024 u32 rx_prep_beacon_drop;
1025 u32 descr_host_int_trig_rx_data;
1026 u32 beacon_buffer_thres_host_int_trig_rx_data;
1027 u32 missed_beacon_host_int_trig_rx_data;
1028 u32 tx_xfr_host_int_trig_rx_data;
1029} __packed;
1030
1031struct acx_statistics {
1032 struct acx_header header;
1033
1034 struct acx_tx_statistics tx;
1035 struct acx_rx_statistics rx;
1036 struct acx_dma_statistics dma;
1037 struct acx_isr_statistics isr;
1038 struct acx_wep_statistics wep;
1039 struct acx_pwr_statistics pwr;
1040 struct acx_aes_statistics aes;
1041 struct acx_mic_statistics mic;
1042 struct acx_event_statistics event;
1043 struct acx_ps_statistics ps;
1044 struct acx_rxpipe_statistics rxpipe;
1045} __packed;
1046
1047#define ACX_MAX_RATE_CLASSES 8
1048#define ACX_RATE_MASK_UNSPECIFIED 0
1049#define ACX_RATE_RETRY_LIMIT 10
1050
1051struct acx_rate_class {
1052 u32 enabled_rates;
1053 u8 short_retry_limit;
1054 u8 long_retry_limit;
1055 u8 aflags;
1056 u8 reserved;
1057} __packed;
1058
1059struct acx_rate_policy {
1060 struct acx_header header;
1061
1062 u32 rate_class_cnt;
1063 struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES];
1064} __packed;
1065
1066struct wl1251_acx_memory {
1067 __le16 num_stations; /* number of STAs to be supported. */
1068 u16 reserved_1;
1069
1070 /*
1071 * Nmber of memory buffers for the RX mem pool.
1072 * The actual number may be less if there are
1073 * not enough blocks left for the minimum num
1074 * of TX ones.
1075 */
1076 u8 rx_mem_block_num;
1077 u8 reserved_2;
1078 u8 num_tx_queues; /* From 1 to 16 */
1079 u8 host_if_options; /* HOST_IF* */
1080 u8 tx_min_mem_block_num;
1081 u8 num_ssid_profiles;
1082 __le16 debug_buffer_size;
1083} __packed;
1084
1085
1086#define ACX_RX_DESC_MIN 1
1087#define ACX_RX_DESC_MAX 127
1088#define ACX_RX_DESC_DEF 32
1089struct wl1251_acx_rx_queue_config {
1090 u8 num_descs;
1091 u8 pad;
1092 u8 type;
1093 u8 priority;
1094 __le32 dma_address;
1095} __packed;
1096
1097#define ACX_TX_DESC_MIN 1
1098#define ACX_TX_DESC_MAX 127
1099#define ACX_TX_DESC_DEF 16
1100struct wl1251_acx_tx_queue_config {
1101 u8 num_descs;
1102 u8 pad[2];
1103 u8 attributes;
1104} __packed;
1105
1106#define MAX_TX_QUEUE_CONFIGS 5
1107#define MAX_TX_QUEUES 4
1108struct wl1251_acx_config_memory {
1109 struct acx_header header;
1110
1111 struct wl1251_acx_memory mem_config;
1112 struct wl1251_acx_rx_queue_config rx_queue_config;
1113 struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS];
1114} __packed;
1115
1116struct wl1251_acx_mem_map {
1117 struct acx_header header;
1118
1119 void *code_start;
1120 void *code_end;
1121
1122 void *wep_defkey_start;
1123 void *wep_defkey_end;
1124
1125 void *sta_table_start;
1126 void *sta_table_end;
1127
1128 void *packet_template_start;
1129 void *packet_template_end;
1130
1131 void *queue_memory_start;
1132 void *queue_memory_end;
1133
1134 void *packet_memory_pool_start;
1135 void *packet_memory_pool_end;
1136
1137 void *debug_buffer1_start;
1138 void *debug_buffer1_end;
1139
1140 void *debug_buffer2_start;
1141 void *debug_buffer2_end;
1142
1143 /* Number of blocks FW allocated for TX packets */
1144 u32 num_tx_mem_blocks;
1145
1146 /* Number of blocks FW allocated for RX packets */
1147 u32 num_rx_mem_blocks;
1148} __packed;
1149
1150
1151struct wl1251_acx_wr_tbtt_and_dtim {
1152
1153 struct acx_header header;
1154
1155 /* Time in TUs between two consecutive beacons */
1156 u16 tbtt;
1157
1158 /*
1159 * DTIM period
1160 * For BSS: Number of TBTTs in a DTIM period (range: 1-10)
1161 * For IBSS: value shall be set to 1
1162 */
1163 u8 dtim;
1164 u8 padding;
1165} __packed;
1166
1167struct wl1251_acx_ac_cfg {
1168 struct acx_header header;
1169
1170 /*
1171 * Access Category - The TX queue's access category
1172 * (refer to AccessCategory_enum)
1173 */
1174 u8 ac;
1175
1176 /*
1177 * The contention window minimum size (in slots) for
1178 * the access class.
1179 */
1180 u8 cw_min;
1181
1182 /*
1183 * The contention window maximum size (in slots) for
1184 * the access class.
1185 */
1186 u16 cw_max;
1187
1188 /* The AIF value (in slots) for the access class. */
1189 u8 aifsn;
1190
1191 u8 reserved;
1192
1193 /* The TX Op Limit (in microseconds) for the access class. */
1194 u16 txop_limit;
1195} __packed;
1196
1197
1198enum wl1251_acx_channel_type {
1199 CHANNEL_TYPE_DCF = 0,
1200 CHANNEL_TYPE_EDCF = 1,
1201 CHANNEL_TYPE_HCCA = 2,
1202};
1203
1204enum wl1251_acx_ps_scheme {
1205 /* regular ps: simple sending of packets */
1206 WL1251_ACX_PS_SCHEME_LEGACY = 0,
1207
1208 /* sending a packet triggers a unscheduled apsd downstream */
1209 WL1251_ACX_PS_SCHEME_UPSD_TRIGGER = 1,
1210
1211 /* a pspoll packet will be sent before every data packet */
1212 WL1251_ACX_PS_SCHEME_LEGACY_PSPOLL = 2,
1213
1214 /* scheduled apsd mode */
1215 WL1251_ACX_PS_SCHEME_SAPSD = 3,
1216};
1217
1218enum wl1251_acx_ack_policy {
1219 WL1251_ACX_ACK_POLICY_LEGACY = 0,
1220 WL1251_ACX_ACK_POLICY_NO_ACK = 1,
1221 WL1251_ACX_ACK_POLICY_BLOCK = 2,
1222};
1223
1224struct wl1251_acx_tid_cfg {
1225 struct acx_header header;
1226
1227 /* tx queue id number (0-7) */
1228 u8 queue;
1229
1230 /* channel access type for the queue, enum wl1251_acx_channel_type */
1231 u8 type;
1232
1233 /* EDCA: ac index (0-3), HCCA: traffic stream id (8-15) */
1234 u8 tsid;
1235
1236 /* ps scheme of the specified queue, enum wl1251_acx_ps_scheme */
1237 u8 ps_scheme;
1238
1239 /* the tx queue ack policy, enum wl1251_acx_ack_policy */
1240 u8 ack_policy;
1241
1242 u8 padding[3];
1243
1244 /* not supported */
1245 u32 apsdconf[2];
1246} __packed;
1247
1248/*************************************************************************
1249
1250 Host Interrupt Register (WiLink -> Host)
1251
1252**************************************************************************/
1253
1254/* RX packet is ready in Xfer buffer #0 */
1255#define WL1251_ACX_INTR_RX0_DATA BIT(0)
1256
1257/* TX result(s) are in the TX complete buffer */
1258#define WL1251_ACX_INTR_TX_RESULT BIT(1)
1259
1260/* OBSOLETE */
1261#define WL1251_ACX_INTR_TX_XFR BIT(2)
1262
1263/* RX packet is ready in Xfer buffer #1 */
1264#define WL1251_ACX_INTR_RX1_DATA BIT(3)
1265
1266/* Event was entered to Event MBOX #A */
1267#define WL1251_ACX_INTR_EVENT_A BIT(4)
1268
1269/* Event was entered to Event MBOX #B */
1270#define WL1251_ACX_INTR_EVENT_B BIT(5)
1271
1272/* OBSOLETE */
1273#define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6)
1274
1275/* Trace meassge on MBOX #A */
1276#define WL1251_ACX_INTR_TRACE_A BIT(7)
1277
1278/* Trace meassge on MBOX #B */
1279#define WL1251_ACX_INTR_TRACE_B BIT(8)
1280
1281/* Command processing completion */
1282#define WL1251_ACX_INTR_CMD_COMPLETE BIT(9)
1283
1284/* Init sequence is done */
1285#define WL1251_ACX_INTR_INIT_COMPLETE BIT(14)
1286
1287#define WL1251_ACX_INTR_ALL 0xFFFFFFFF
1288
1289enum {
1290 ACX_WAKE_UP_CONDITIONS = 0x0002,
1291 ACX_MEM_CFG = 0x0003,
1292 ACX_SLOT = 0x0004,
1293 ACX_QUEUE_HEAD = 0x0005, /* for MASTER mode only */
1294 ACX_AC_CFG = 0x0007,
1295 ACX_MEM_MAP = 0x0008,
1296 ACX_AID = 0x000A,
1297 ACX_RADIO_PARAM = 0x000B, /* Not used */
1298 ACX_CFG = 0x000C, /* Not used */
1299 ACX_FW_REV = 0x000D,
1300 ACX_MEDIUM_USAGE = 0x000F,
1301 ACX_RX_CFG = 0x0010,
1302 ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */
1303 ACX_BSS_IN_PS = 0x0012, /* for AP only */
1304 ACX_STATISTICS = 0x0013, /* Debug API */
1305 ACX_FEATURE_CFG = 0x0015,
1306 ACX_MISC_CFG = 0x0017, /* Not used */
1307 ACX_TID_CFG = 0x001A,
1308 ACX_BEACON_FILTER_OPT = 0x001F,
1309 ACX_LOW_RSSI = 0x0020,
1310 ACX_NOISE_HIST = 0x0021,
1311 ACX_HDK_VERSION = 0x0022, /* ??? */
1312 ACX_PD_THRESHOLD = 0x0023,
1313 ACX_DATA_PATH_PARAMS = 0x0024, /* WO */
1314 ACX_DATA_PATH_RESP_PARAMS = 0x0024, /* RO */
1315 ACX_CCA_THRESHOLD = 0x0025,
1316 ACX_EVENT_MBOX_MASK = 0x0026,
1317#ifdef FW_RUNNING_AS_AP
1318 ACX_DTIM_PERIOD = 0x0027, /* for AP only */
1319#else
1320 ACX_WR_TBTT_AND_DTIM = 0x0027, /* STA only */
1321#endif
1322 ACX_ACI_OPTION_CFG = 0x0029, /* OBSOLETE (for 1251)*/
1323 ACX_GPIO_CFG = 0x002A, /* Not used */
1324 ACX_GPIO_SET = 0x002B, /* Not used */
1325 ACX_PM_CFG = 0x002C, /* To Be Documented */
1326 ACX_CONN_MONIT_PARAMS = 0x002D,
1327 ACX_AVERAGE_RSSI = 0x002E, /* Not used */
1328 ACX_CONS_TX_FAILURE = 0x002F,
1329 ACX_BCN_DTIM_OPTIONS = 0x0031,
1330 ACX_SG_ENABLE = 0x0032,
1331 ACX_SG_CFG = 0x0033,
1332 ACX_ANTENNA_DIVERSITY_CFG = 0x0035, /* To Be Documented */
1333 ACX_LOW_SNR = 0x0037, /* To Be Documented */
1334 ACX_BEACON_FILTER_TABLE = 0x0038,
1335 ACX_ARP_IP_FILTER = 0x0039,
1336 ACX_ROAMING_STATISTICS_TBL = 0x003B,
1337 ACX_RATE_POLICY = 0x003D,
1338 ACX_CTS_PROTECTION = 0x003E,
1339 ACX_SLEEP_AUTH = 0x003F,
1340 ACX_PREAMBLE_TYPE = 0x0040,
1341 ACX_ERROR_CNT = 0x0041,
1342 ACX_FW_GEN_FRAME_RATES = 0x0042,
1343 ACX_IBSS_FILTER = 0x0044,
1344 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045,
1345 ACX_TSF_INFO = 0x0046,
1346 ACX_CONFIG_PS_WMM = 0x0049,
1347 ACX_ENABLE_RX_DATA_FILTER = 0x004A,
1348 ACX_SET_RX_DATA_FILTER = 0x004B,
1349 ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1350 ACX_POWER_LEVEL_TABLE = 0x004D,
1351 ACX_BET_ENABLE = 0x0050,
1352 DOT11_STATION_ID = 0x1001,
1353 DOT11_RX_MSDU_LIFE_TIME = 0x1004,
1354 DOT11_CUR_TX_PWR = 0x100D,
1355 DOT11_DEFAULT_KEY = 0x1010,
1356 DOT11_RX_DOT11_MODE = 0x1012,
1357 DOT11_RTS_THRESHOLD = 0x1013,
1358 DOT11_GROUP_ADDRESS_TBL = 0x1014,
1359
1360 MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
1361
1362 MAX_IE = 0xFFFF
1363};
1364
1365
1366int wl1251_acx_frame_rates(struct wl1251 *wl, u8 ctrl_rate, u8 ctrl_mod,
1367 u8 mgt_rate, u8 mgt_mod);
1368int wl1251_acx_station_id(struct wl1251 *wl);
1369int wl1251_acx_default_key(struct wl1251 *wl, u8 key_id);
1370int wl1251_acx_wake_up_conditions(struct wl1251 *wl, u8 wake_up_event,
1371 u8 listen_interval);
1372int wl1251_acx_sleep_auth(struct wl1251 *wl, u8 sleep_auth);
1373int wl1251_acx_fw_version(struct wl1251 *wl, char *buf, size_t len);
1374int wl1251_acx_tx_power(struct wl1251 *wl, int power);
1375int wl1251_acx_feature_cfg(struct wl1251 *wl);
1376int wl1251_acx_mem_map(struct wl1251 *wl,
1377 struct acx_header *mem_map, size_t len);
1378int wl1251_acx_data_path_params(struct wl1251 *wl,
1379 struct acx_data_path_params_resp *data_path);
1380int wl1251_acx_rx_msdu_life_time(struct wl1251 *wl, u32 life_time);
1381int wl1251_acx_rx_config(struct wl1251 *wl, u32 config, u32 filter);
1382int wl1251_acx_pd_threshold(struct wl1251 *wl);
1383int wl1251_acx_slot(struct wl1251 *wl, enum acx_slot_type slot_time);
1384int wl1251_acx_group_address_tbl(struct wl1251 *wl);
1385int wl1251_acx_service_period_timeout(struct wl1251 *wl);
1386int wl1251_acx_rts_threshold(struct wl1251 *wl, u16 rts_threshold);
1387int wl1251_acx_beacon_filter_opt(struct wl1251 *wl, bool enable_filter);
1388int wl1251_acx_beacon_filter_table(struct wl1251 *wl);
1389int wl1251_acx_conn_monit_params(struct wl1251 *wl);
1390int wl1251_acx_sg_enable(struct wl1251 *wl);
1391int wl1251_acx_sg_cfg(struct wl1251 *wl);
1392int wl1251_acx_cca_threshold(struct wl1251 *wl);
1393int wl1251_acx_bcn_dtim_options(struct wl1251 *wl);
1394int wl1251_acx_aid(struct wl1251 *wl, u16 aid);
1395int wl1251_acx_event_mbox_mask(struct wl1251 *wl, u32 event_mask);
1396int wl1251_acx_set_preamble(struct wl1251 *wl, enum acx_preamble_type preamble);
1397int wl1251_acx_cts_protect(struct wl1251 *wl,
1398 enum acx_ctsprotect_type ctsprotect);
1399int wl1251_acx_statistics(struct wl1251 *wl, struct acx_statistics *stats);
1400int wl1251_acx_tsf_info(struct wl1251 *wl, u64 *mactime);
1401int wl1251_acx_rate_policies(struct wl1251 *wl);
1402int wl1251_acx_mem_cfg(struct wl1251 *wl);
1403int wl1251_acx_wr_tbtt_and_dtim(struct wl1251 *wl, u16 tbtt, u8 dtim);
1404int wl1251_acx_ac_cfg(struct wl1251 *wl, u8 ac, u8 cw_min, u16 cw_max,
1405 u8 aifs, u16 txop);
1406int wl1251_acx_tid_cfg(struct wl1251 *wl, u8 queue,
1407 enum wl1251_acx_channel_type type,
1408 u8 tsid, enum wl1251_acx_ps_scheme ps_scheme,
1409 enum wl1251_acx_ack_policy ack_policy);
1410
1411#endif /* __WL1251_ACX_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 18:44:11 -0500