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path: root/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
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Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192de/phy.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192de/phy.c429
1 files changed, 185 insertions, 244 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
index 13196cc4b1d3..3d1f0dd4e52d 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192de/phy.c
@@ -30,6 +30,7 @@
30#include "../wifi.h" 30#include "../wifi.h"
31#include "../pci.h" 31#include "../pci.h"
32#include "../ps.h" 32#include "../ps.h"
33#include "../core.h"
33#include "reg.h" 34#include "reg.h"
34#include "def.h" 35#include "def.h"
35#include "phy.h" 36#include "phy.h"
@@ -242,7 +243,7 @@ void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
242 else if (rtlhal->during_mac0init_radiob) 243 else if (rtlhal->during_mac0init_radiob)
243 /* mac0 use phy1 write radio_b. */ 244 /* mac0 use phy1 write radio_b. */
244 dbi_direct = BIT(3) | BIT(2); 245 dbi_direct = BIT(3) | BIT(2);
245 if (bitmask != BMASKDWORD) { 246 if (bitmask != MASKDWORD) {
246 if (rtlhal->during_mac1init_radioa || 247 if (rtlhal->during_mac1init_radioa ||
247 rtlhal->during_mac0init_radiob) 248 rtlhal->during_mac0init_radiob)
248 originalvalue = rtl92de_read_dword_dbi(hw, 249 originalvalue = rtl92de_read_dword_dbi(hw,
@@ -275,20 +276,20 @@ static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
275 u32 retvalue; 276 u32 retvalue;
276 277
277 newoffset = offset; 278 newoffset = offset;
278 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD); 279 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
279 if (rfpath == RF90_PATH_A) 280 if (rfpath == RF90_PATH_A)
280 tmplong2 = tmplong; 281 tmplong2 = tmplong;
281 else 282 else
282 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD); 283 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
283 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | 284 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
284 (newoffset << 23) | BLSSIREADEDGE; 285 (newoffset << 23) | BLSSIREADEDGE;
285 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD, 286 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
286 tmplong & (~BLSSIREADEDGE)); 287 tmplong & (~BLSSIREADEDGE));
287 udelay(10); 288 udelay(10);
288 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2); 289 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
289 udelay(50); 290 udelay(50);
290 udelay(50); 291 udelay(50);
291 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD, 292 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
292 tmplong | BLSSIREADEDGE); 293 tmplong | BLSSIREADEDGE);
293 udelay(10); 294 udelay(10);
294 if (rfpath == RF90_PATH_A) 295 if (rfpath == RF90_PATH_A)
@@ -321,7 +322,7 @@ static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
321 newoffset = offset; 322 newoffset = offset;
322 /* T65 RF */ 323 /* T65 RF */
323 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; 324 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
324 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr); 325 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
325 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", 326 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
326 rfpath, pphyreg->rf3wire_offset, data_and_addr); 327 rfpath, pphyreg->rf3wire_offset, data_and_addr);
327} 328}
@@ -362,7 +363,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
362 return; 363 return;
363 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 364 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
364 if (rtlphy->rf_mode != RF_OP_BY_FW) { 365 if (rtlphy->rf_mode != RF_OP_BY_FW) {
365 if (bitmask != BRFREGOFFSETMASK) { 366 if (bitmask != RFREG_OFFSET_MASK) {
366 original_value = _rtl92d_phy_rf_serial_read(hw, 367 original_value = _rtl92d_phy_rf_serial_read(hw,
367 rfpath, regaddr); 368 rfpath, regaddr);
368 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); 369 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
@@ -567,19 +568,8 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
567 " ===> phy:Rtl819XPHY_REG_Array_PG\n"); 568 " ===> phy:Rtl819XPHY_REG_Array_PG\n");
568 if (configtype == BASEBAND_CONFIG_PHY_REG) { 569 if (configtype == BASEBAND_CONFIG_PHY_REG) {
569 for (i = 0; i < phy_reg_arraylen; i = i + 2) { 570 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
570 if (phy_regarray_table[i] == 0xfe) 571 rtl_addr_delay(phy_regarray_table[i]);
571 mdelay(50); 572 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
572 else if (phy_regarray_table[i] == 0xfd)
573 mdelay(5);
574 else if (phy_regarray_table[i] == 0xfc)
575 mdelay(1);
576 else if (phy_regarray_table[i] == 0xfb)
577 udelay(50);
578 else if (phy_regarray_table[i] == 0xfa)
579 udelay(5);
580 else if (phy_regarray_table[i] == 0xf9)
581 udelay(1);
582 rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
583 phy_regarray_table[i + 1]); 573 phy_regarray_table[i + 1]);
584 udelay(1); 574 udelay(1);
585 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 575 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
@@ -591,7 +581,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
591 if (rtlhal->interfaceindex == 0) { 581 if (rtlhal->interfaceindex == 0) {
592 for (i = 0; i < agctab_arraylen; i = i + 2) { 582 for (i = 0; i < agctab_arraylen; i = i + 2) {
593 rtl_set_bbreg(hw, agctab_array_table[i], 583 rtl_set_bbreg(hw, agctab_array_table[i],
594 BMASKDWORD, 584 MASKDWORD,
595 agctab_array_table[i + 1]); 585 agctab_array_table[i + 1]);
596 /* Add 1us delay between BB/RF register 586 /* Add 1us delay between BB/RF register
597 * setting. */ 587 * setting. */
@@ -607,7 +597,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
607 if (rtlhal->current_bandtype == BAND_ON_2_4G) { 597 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
608 for (i = 0; i < agctab_arraylen; i = i + 2) { 598 for (i = 0; i < agctab_arraylen; i = i + 2) {
609 rtl_set_bbreg(hw, agctab_array_table[i], 599 rtl_set_bbreg(hw, agctab_array_table[i],
610 BMASKDWORD, 600 MASKDWORD,
611 agctab_array_table[i + 1]); 601 agctab_array_table[i + 1]);
612 /* Add 1us delay between BB/RF register 602 /* Add 1us delay between BB/RF register
613 * setting. */ 603 * setting. */
@@ -623,7 +613,7 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
623 for (i = 0; i < agctab_5garraylen; i = i + 2) { 613 for (i = 0; i < agctab_5garraylen; i = i + 2) {
624 rtl_set_bbreg(hw, 614 rtl_set_bbreg(hw,
625 agctab_5garray_table[i], 615 agctab_5garray_table[i],
626 BMASKDWORD, 616 MASKDWORD,
627 agctab_5garray_table[i + 1]); 617 agctab_5garray_table[i + 1]);
628 /* Add 1us delay between BB/RF registeri 618 /* Add 1us delay between BB/RF registeri
629 * setting. */ 619 * setting. */
@@ -705,18 +695,7 @@ static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
705 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg; 695 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
706 if (configtype == BASEBAND_CONFIG_PHY_REG) { 696 if (configtype == BASEBAND_CONFIG_PHY_REG) {
707 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { 697 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
708 if (phy_regarray_table_pg[i] == 0xfe) 698 rtl_addr_delay(phy_regarray_table_pg[i]);
709 mdelay(50);
710 else if (phy_regarray_table_pg[i] == 0xfd)
711 mdelay(5);
712 else if (phy_regarray_table_pg[i] == 0xfc)
713 mdelay(1);
714 else if (phy_regarray_table_pg[i] == 0xfb)
715 udelay(50);
716 else if (phy_regarray_table_pg[i] == 0xfa)
717 udelay(5);
718 else if (phy_regarray_table_pg[i] == 0xf9)
719 udelay(1);
720 _rtl92d_store_pwrindex_diffrate_offset(hw, 699 _rtl92d_store_pwrindex_diffrate_offset(hw,
721 phy_regarray_table_pg[i], 700 phy_regarray_table_pg[i],
722 phy_regarray_table_pg[i + 1], 701 phy_regarray_table_pg[i + 1],
@@ -843,54 +822,16 @@ bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
843 switch (rfpath) { 822 switch (rfpath) {
844 case RF90_PATH_A: 823 case RF90_PATH_A:
845 for (i = 0; i < radioa_arraylen; i = i + 2) { 824 for (i = 0; i < radioa_arraylen; i = i + 2) {
846 if (radioa_array_table[i] == 0xfe) { 825 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
847 mdelay(50); 826 RFREG_OFFSET_MASK,
848 } else if (radioa_array_table[i] == 0xfd) { 827 radioa_array_table[i + 1]);
849 /* delay_ms(5); */
850 mdelay(5);
851 } else if (radioa_array_table[i] == 0xfc) {
852 /* delay_ms(1); */
853 mdelay(1);
854 } else if (radioa_array_table[i] == 0xfb) {
855 udelay(50);
856 } else if (radioa_array_table[i] == 0xfa) {
857 udelay(5);
858 } else if (radioa_array_table[i] == 0xf9) {
859 udelay(1);
860 } else {
861 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
862 BRFREGOFFSETMASK,
863 radioa_array_table[i + 1]);
864 /* Add 1us delay between BB/RF register set. */
865 udelay(1);
866 }
867 } 828 }
868 break; 829 break;
869 case RF90_PATH_B: 830 case RF90_PATH_B:
870 for (i = 0; i < radiob_arraylen; i = i + 2) { 831 for (i = 0; i < radiob_arraylen; i = i + 2) {
871 if (radiob_array_table[i] == 0xfe) { 832 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
872 /* Delay specific ms. Only RF configuration 833 RFREG_OFFSET_MASK,
873 * requires delay. */ 834 radiob_array_table[i + 1]);
874 mdelay(50);
875 } else if (radiob_array_table[i] == 0xfd) {
876 /* delay_ms(5); */
877 mdelay(5);
878 } else if (radiob_array_table[i] == 0xfc) {
879 /* delay_ms(1); */
880 mdelay(1);
881 } else if (radiob_array_table[i] == 0xfb) {
882 udelay(50);
883 } else if (radiob_array_table[i] == 0xfa) {
884 udelay(5);
885 } else if (radiob_array_table[i] == 0xf9) {
886 udelay(1);
887 } else {
888 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
889 BRFREGOFFSETMASK,
890 radiob_array_table[i + 1]);
891 /* Add 1us delay between BB/RF register set. */
892 udelay(1);
893 }
894 } 835 }
895 break; 836 break;
896 case RF90_PATH_C: 837 case RF90_PATH_C:
@@ -911,13 +852,13 @@ void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
911 struct rtl_phy *rtlphy = &(rtlpriv->phy); 852 struct rtl_phy *rtlphy = &(rtlpriv->phy);
912 853
913 rtlphy->default_initialgain[0] = 854 rtlphy->default_initialgain[0] =
914 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0); 855 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
915 rtlphy->default_initialgain[1] = 856 rtlphy->default_initialgain[1] =
916 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0); 857 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
917 rtlphy->default_initialgain[2] = 858 rtlphy->default_initialgain[2] =
918 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0); 859 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
919 rtlphy->default_initialgain[3] = 860 rtlphy->default_initialgain[3] =
920 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0); 861 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
921 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 862 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
922 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", 863 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
923 rtlphy->default_initialgain[0], 864 rtlphy->default_initialgain[0],
@@ -925,9 +866,9 @@ void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
925 rtlphy->default_initialgain[2], 866 rtlphy->default_initialgain[2],
926 rtlphy->default_initialgain[3]); 867 rtlphy->default_initialgain[3]);
927 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, 868 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
928 BMASKBYTE0); 869 MASKBYTE0);
929 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, 870 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
930 BMASKDWORD); 871 MASKDWORD);
931 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, 872 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
932 "Default framesync (0x%x) = 0x%x\n", 873 "Default framesync (0x%x) = 0x%x\n",
933 ROFDM0_RXDETECTOR3, rtlphy->framesync); 874 ROFDM0_RXDETECTOR3, rtlphy->framesync);
@@ -1106,7 +1047,7 @@ static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1106{ 1047{
1107 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); 1048 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1108 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); 1049 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1109 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00); 1050 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00);
1110 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); 1051 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1111} 1052}
1112 1053
@@ -1168,7 +1109,7 @@ static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1168{ 1109{
1169 struct rtl_priv *rtlpriv = rtl_priv(hw); 1110 struct rtl_priv *rtlpriv = rtl_priv(hw);
1170 u32 imr_num = MAX_RF_IMR_INDEX; 1111 u32 imr_num = MAX_RF_IMR_INDEX;
1171 u32 rfmask = BRFREGOFFSETMASK; 1112 u32 rfmask = RFREG_OFFSET_MASK;
1172 u8 group, i; 1113 u8 group, i;
1173 unsigned long flag = 0; 1114 unsigned long flag = 0;
1174 1115
@@ -1211,7 +1152,7 @@ static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1211 for (i = 0; i < imr_num; i++) { 1152 for (i = 0; i < imr_num; i++) {
1212 rtl_set_rfreg(hw, (enum radio_path)rfpath, 1153 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1213 rf_reg_for_5g_swchnl_normal[i], 1154 rf_reg_for_5g_swchnl_normal[i],
1214 BRFREGOFFSETMASK, 1155 RFREG_OFFSET_MASK,
1215 rf_imr_param_normal[0][0][i]); 1156 rf_imr_param_normal[0][0][i]);
1216 } 1157 }
1217 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 1158 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
@@ -1329,7 +1270,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1329 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { 1270 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1330 rtl_set_rfreg(hw, (enum radio_path)path, 1271 rtl_set_rfreg(hw, (enum radio_path)path,
1331 rf_reg_for_c_cut_5g[i], 1272 rf_reg_for_c_cut_5g[i],
1332 BRFREGOFFSETMASK, 0xE439D); 1273 RFREG_OFFSET_MASK, 0xE439D);
1333 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { 1274 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1334 u4tmp2 = (rf_reg_pram_c_5g[index][i] & 1275 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1335 0x7FF) | (u4tmp << 11); 1276 0x7FF) | (u4tmp << 11);
@@ -1337,11 +1278,11 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1337 u4tmp2 &= ~(BIT(7) | BIT(6)); 1278 u4tmp2 &= ~(BIT(7) | BIT(6));
1338 rtl_set_rfreg(hw, (enum radio_path)path, 1279 rtl_set_rfreg(hw, (enum radio_path)path,
1339 rf_reg_for_c_cut_5g[i], 1280 rf_reg_for_c_cut_5g[i],
1340 BRFREGOFFSETMASK, u4tmp2); 1281 RFREG_OFFSET_MASK, u4tmp2);
1341 } else { 1282 } else {
1342 rtl_set_rfreg(hw, (enum radio_path)path, 1283 rtl_set_rfreg(hw, (enum radio_path)path,
1343 rf_reg_for_c_cut_5g[i], 1284 rf_reg_for_c_cut_5g[i],
1344 BRFREGOFFSETMASK, 1285 RFREG_OFFSET_MASK,
1345 rf_reg_pram_c_5g[index][i]); 1286 rf_reg_pram_c_5g[index][i]);
1346 } 1287 }
1347 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1288 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
@@ -1351,7 +1292,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1351 path, index, 1292 path, index,
1352 rtl_get_rfreg(hw, (enum radio_path)path, 1293 rtl_get_rfreg(hw, (enum radio_path)path,
1353 rf_reg_for_c_cut_5g[i], 1294 rf_reg_for_c_cut_5g[i],
1354 BRFREGOFFSETMASK)); 1295 RFREG_OFFSET_MASK));
1355 } 1296 }
1356 if (need_pwr_down) 1297 if (need_pwr_down)
1357 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1298 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
@@ -1381,7 +1322,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1381 i++) { 1322 i++) {
1382 rtl_set_rfreg(hw, rfpath, 1323 rtl_set_rfreg(hw, rfpath,
1383 rf_for_c_cut_5g_internal_pa[i], 1324 rf_for_c_cut_5g_internal_pa[i],
1384 BRFREGOFFSETMASK, 1325 RFREG_OFFSET_MASK,
1385 rf_pram_c_5g_int_pa[index][i]); 1326 rf_pram_c_5g_int_pa[index][i]);
1386 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, 1327 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1387 "offset 0x%x value 0x%x path %d index %d\n", 1328 "offset 0x%x value 0x%x path %d index %d\n",
@@ -1422,13 +1363,13 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1422 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) 1363 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1423 rtl_set_rfreg(hw, (enum radio_path)path, 1364 rtl_set_rfreg(hw, (enum radio_path)path,
1424 rf_reg_for_c_cut_2g[i], 1365 rf_reg_for_c_cut_2g[i],
1425 BRFREGOFFSETMASK, 1366 RFREG_OFFSET_MASK,
1426 (rf_reg_param_for_c_cut_2g[index][i] | 1367 (rf_reg_param_for_c_cut_2g[index][i] |
1427 BIT(17))); 1368 BIT(17)));
1428 else 1369 else
1429 rtl_set_rfreg(hw, (enum radio_path)path, 1370 rtl_set_rfreg(hw, (enum radio_path)path,
1430 rf_reg_for_c_cut_2g[i], 1371 rf_reg_for_c_cut_2g[i],
1431 BRFREGOFFSETMASK, 1372 RFREG_OFFSET_MASK,
1432 rf_reg_param_for_c_cut_2g 1373 rf_reg_param_for_c_cut_2g
1433 [index][i]); 1374 [index][i]);
1434 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 1375 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
@@ -1438,14 +1379,14 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1438 rf_reg_mask_for_c_cut_2g[i], path, index, 1379 rf_reg_mask_for_c_cut_2g[i], path, index,
1439 rtl_get_rfreg(hw, (enum radio_path)path, 1380 rtl_get_rfreg(hw, (enum radio_path)path,
1440 rf_reg_for_c_cut_2g[i], 1381 rf_reg_for_c_cut_2g[i],
1441 BRFREGOFFSETMASK)); 1382 RFREG_OFFSET_MASK));
1442 } 1383 }
1443 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1384 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1444 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", 1385 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1445 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1386 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1446 1387
1447 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, 1388 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1448 BRFREGOFFSETMASK, 1389 RFREG_OFFSET_MASK,
1449 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); 1390 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1450 if (need_pwr_down) 1391 if (need_pwr_down)
1451 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); 1392 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
@@ -1493,41 +1434,41 @@ static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1493 /* path-A IQK setting */ 1434 /* path-A IQK setting */
1494 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1435 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1495 if (rtlhal->interfaceindex == 0) { 1436 if (rtlhal->interfaceindex == 0) {
1496 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f); 1437 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1497 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f); 1438 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1498 } else { 1439 } else {
1499 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22); 1440 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22);
1500 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22); 1441 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22);
1501 } 1442 }
1502 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102); 1443 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1503 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206); 1444 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206);
1504 /* path-B IQK setting */ 1445 /* path-B IQK setting */
1505 if (configpathb) { 1446 if (configpathb) {
1506 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22); 1447 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1507 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22); 1448 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1508 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102); 1449 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1509 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206); 1450 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206);
1510 } 1451 }
1511 /* LO calibration setting */ 1452 /* LO calibration setting */
1512 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1453 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1513 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1454 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1514 /* One shot, path A LOK & IQK */ 1455 /* One shot, path A LOK & IQK */
1515 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1456 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1516 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000); 1457 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1517 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1458 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1518 /* delay x ms */ 1459 /* delay x ms */
1519 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1460 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1520 "Delay %d ms for One shot, path A LOK & IQK\n", 1461 "Delay %d ms for One shot, path A LOK & IQK\n",
1521 IQK_DELAY_TIME); 1462 IQK_DELAY_TIME);
1522 mdelay(IQK_DELAY_TIME); 1463 mdelay(IQK_DELAY_TIME);
1523 /* Check failed */ 1464 /* Check failed */
1524 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1465 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1525 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1466 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1526 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD); 1467 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1527 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1468 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1528 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD); 1469 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1529 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1470 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1530 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD); 1471 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1531 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1472 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1532 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && 1473 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1533 (((rege9c & 0x03FF0000) >> 16) != 0x42)) 1474 (((rege9c & 0x03FF0000) >> 16) != 0x42))
@@ -1563,42 +1504,42 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1563 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n"); 1504 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1564 /* path-A IQK setting */ 1505 /* path-A IQK setting */
1565 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1506 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1566 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f); 1507 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1567 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f); 1508 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1568 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307); 1509 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1569 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960); 1510 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);
1570 /* path-B IQK setting */ 1511 /* path-B IQK setting */
1571 if (configpathb) { 1512 if (configpathb) {
1572 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f); 1513 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1573 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f); 1514 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1574 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000); 1515 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000);
1575 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000); 1516 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000);
1576 } 1517 }
1577 /* LO calibration setting */ 1518 /* LO calibration setting */
1578 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1519 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1579 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1520 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1580 /* path-A PA on */ 1521 /* path-A PA on */
1581 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60); 1522 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60);
1582 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30); 1523 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30);
1583 for (i = 0; i < retrycount; i++) { 1524 for (i = 0; i < retrycount; i++) {
1584 /* One shot, path A LOK & IQK */ 1525 /* One shot, path A LOK & IQK */
1585 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1526 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1586 "One shot, path A LOK & IQK!\n"); 1527 "One shot, path A LOK & IQK!\n");
1587 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000); 1528 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1588 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1529 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1589 /* delay x ms */ 1530 /* delay x ms */
1590 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1531 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1591 "Delay %d ms for One shot, path A LOK & IQK.\n", 1532 "Delay %d ms for One shot, path A LOK & IQK.\n",
1592 IQK_DELAY_TIME); 1533 IQK_DELAY_TIME);
1593 mdelay(IQK_DELAY_TIME * 10); 1534 mdelay(IQK_DELAY_TIME * 10);
1594 /* Check failed */ 1535 /* Check failed */
1595 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1536 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1596 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1537 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1597 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD); 1538 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1598 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); 1539 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1599 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD); 1540 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1600 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); 1541 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1601 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD); 1542 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1602 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); 1543 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1603 if (!(regeac & TxOKBit) && 1544 if (!(regeac & TxOKBit) &&
1604 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { 1545 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
@@ -1620,9 +1561,9 @@ static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1620 } 1561 }
1621 } 1562 }
1622 /* path A PA off */ 1563 /* path A PA off */
1623 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 1564 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1624 rtlphy->iqk_bb_backup[0]); 1565 rtlphy->iqk_bb_backup[0]);
1625 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 1566 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD,
1626 rtlphy->iqk_bb_backup[1]); 1567 rtlphy->iqk_bb_backup[1]);
1627 return result; 1568 return result;
1628} 1569}
@@ -1637,22 +1578,22 @@ static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1637 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1578 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1638 /* One shot, path B LOK & IQK */ 1579 /* One shot, path B LOK & IQK */
1639 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); 1580 RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n");
1640 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002); 1581 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1641 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000); 1582 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1642 /* delay x ms */ 1583 /* delay x ms */
1643 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1584 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1644 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); 1585 "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME);
1645 mdelay(IQK_DELAY_TIME); 1586 mdelay(IQK_DELAY_TIME);
1646 /* Check failed */ 1587 /* Check failed */
1647 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1588 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1648 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1589 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1649 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD); 1590 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1650 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1591 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1651 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD); 1592 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1652 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1593 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1653 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD); 1594 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1654 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1595 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1655 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD); 1596 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1656 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1597 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1657 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && 1598 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1658 (((regebc & 0x03FF0000) >> 16) != 0x42)) 1599 (((regebc & 0x03FF0000) >> 16) != 0x42))
@@ -1680,31 +1621,31 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1680 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n"); 1621 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQK!\n");
1681 /* path-A IQK setting */ 1622 /* path-A IQK setting */
1682 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); 1623 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1683 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f); 1624 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1684 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f); 1625 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1685 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000); 1626 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000);
1686 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000); 1627 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000);
1687 1628
1688 /* path-B IQK setting */ 1629 /* path-B IQK setting */
1689 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f); 1630 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f);
1690 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f); 1631 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f);
1691 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307); 1632 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307);
1692 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960); 1633 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960);
1693 1634
1694 /* LO calibration setting */ 1635 /* LO calibration setting */
1695 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); 1636 RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n");
1696 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911); 1637 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1697 1638
1698 /* path-B PA on */ 1639 /* path-B PA on */
1699 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700); 1640 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700);
1700 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30); 1641 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30);
1701 1642
1702 for (i = 0; i < retrycount; i++) { 1643 for (i = 0; i < retrycount; i++) {
1703 /* One shot, path B LOK & IQK */ 1644 /* One shot, path B LOK & IQK */
1704 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1645 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1705 "One shot, path A LOK & IQK!\n"); 1646 "One shot, path A LOK & IQK!\n");
1706 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000); 1647 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000);
1707 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000); 1648 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1708 1649
1709 /* delay x ms */ 1650 /* delay x ms */
1710 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1651 RTPRINT(rtlpriv, FINIT, INIT_IQK,
@@ -1712,15 +1653,15 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1712 mdelay(IQK_DELAY_TIME * 10); 1653 mdelay(IQK_DELAY_TIME * 10);
1713 1654
1714 /* Check failed */ 1655 /* Check failed */
1715 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD); 1656 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1716 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); 1657 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1717 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD); 1658 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1718 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); 1659 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4);
1719 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD); 1660 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1720 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); 1661 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc);
1721 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD); 1662 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1722 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); 1663 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4);
1723 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD); 1664 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1724 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); 1665 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc);
1725 if (!(regeac & BIT(31)) && 1666 if (!(regeac & BIT(31)) &&
1726 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) 1667 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
@@ -1738,9 +1679,9 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1738 } 1679 }
1739 1680
1740 /* path B PA off */ 1681 /* path B PA off */
1741 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 1682 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD,
1742 rtlphy->iqk_bb_backup[0]); 1683 rtlphy->iqk_bb_backup[0]);
1743 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 1684 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD,
1744 rtlphy->iqk_bb_backup[2]); 1685 rtlphy->iqk_bb_backup[2]);
1745 return result; 1686 return result;
1746} 1687}
@@ -1754,7 +1695,7 @@ static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1754 1695
1755 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); 1696 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n");
1756 for (i = 0; i < regnum; i++) 1697 for (i = 0; i < regnum; i++)
1757 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD); 1698 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD);
1758} 1699}
1759 1700
1760static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, 1701static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
@@ -1779,7 +1720,7 @@ static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1779 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1720 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1780 "Reload ADDA power saving parameters !\n"); 1721 "Reload ADDA power saving parameters !\n");
1781 for (i = 0; i < regnum; i++) 1722 for (i = 0; i < regnum; i++)
1782 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]); 1723 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]);
1783} 1724}
1784 1725
1785static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, 1726static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
@@ -1807,7 +1748,7 @@ static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1807 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? 1748 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1808 0x04db25a4 : 0x0b1b25a4; 1749 0x04db25a4 : 0x0b1b25a4;
1809 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 1750 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1810 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon); 1751 rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon);
1811} 1752}
1812 1753
1813static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, 1754static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
@@ -1830,9 +1771,9 @@ static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1830 struct rtl_priv *rtlpriv = rtl_priv(hw); 1771 struct rtl_priv *rtlpriv = rtl_priv(hw);
1831 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); 1772 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n");
1832 1773
1833 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0); 1774 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1834 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000); 1775 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000);
1835 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000); 1776 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1836} 1777}
1837 1778
1838static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) 1779static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
@@ -1843,8 +1784,8 @@ static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1843 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1784 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1844 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); 1785 "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI");
1845 mode = pi_mode ? 0x01000100 : 0x01000000; 1786 mode = pi_mode ? 0x01000100 : 0x01000000;
1846 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode); 1787 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1847 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode); 1788 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1848} 1789}
1849 1790
1850static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], 1791static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
@@ -1875,7 +1816,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1875 1816
1876 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); 1817 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n");
1877 if (t == 0) { 1818 if (t == 0) {
1878 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD); 1819 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
1879 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1820 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
1880 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1821 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
1881 is2t ? "2T2R" : "1T1R"); 1822 is2t ? "2T2R" : "1T1R");
@@ -1898,40 +1839,40 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1898 _rtl92d_phy_pimode_switch(hw, true); 1839 _rtl92d_phy_pimode_switch(hw, true);
1899 1840
1900 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 1841 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
1901 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600); 1842 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
1902 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4); 1843 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
1903 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000); 1844 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000);
1904 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 1845 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
1905 if (is2t) { 1846 if (is2t) {
1906 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 1847 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD,
1907 0x00010000); 1848 0x00010000);
1908 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD, 1849 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD,
1909 0x00010000); 1850 0x00010000);
1910 } 1851 }
1911 /* MAC settings */ 1852 /* MAC settings */
1912 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, 1853 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
1913 rtlphy->iqk_mac_backup); 1854 rtlphy->iqk_mac_backup);
1914 /* Page B init */ 1855 /* Page B init */
1915 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000); 1856 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1916 if (is2t) 1857 if (is2t)
1917 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000); 1858 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1918 /* IQ calibration setting */ 1859 /* IQ calibration setting */
1919 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 1860 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
1920 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000); 1861 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1921 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00); 1862 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1922 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800); 1863 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1923 for (i = 0; i < retrycount; i++) { 1864 for (i = 0; i < retrycount; i++) {
1924 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t); 1865 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
1925 if (patha_ok == 0x03) { 1866 if (patha_ok == 0x03) {
1926 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1867 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1927 "Path A IQK Success!!\n"); 1868 "Path A IQK Success!!\n");
1928 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 1869 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1929 0x3FF0000) >> 16; 1870 0x3FF0000) >> 16;
1930 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 1871 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1931 0x3FF0000) >> 16; 1872 0x3FF0000) >> 16;
1932 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) & 1873 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1933 0x3FF0000) >> 16; 1874 0x3FF0000) >> 16;
1934 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) & 1875 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1935 0x3FF0000) >> 16; 1876 0x3FF0000) >> 16;
1936 break; 1877 break;
1937 } else if (i == (retrycount - 1) && patha_ok == 0x01) { 1878 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
@@ -1939,9 +1880,9 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1939 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1880 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1940 "Path A IQK Only Tx Success!!\n"); 1881 "Path A IQK Only Tx Success!!\n");
1941 1882
1942 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 1883 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1943 0x3FF0000) >> 16; 1884 0x3FF0000) >> 16;
1944 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 1885 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1945 0x3FF0000) >> 16; 1886 0x3FF0000) >> 16;
1946 } 1887 }
1947 } 1888 }
@@ -1957,22 +1898,22 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1957 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1898 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1958 "Path B IQK Success!!\n"); 1899 "Path B IQK Success!!\n");
1959 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1900 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1960 BMASKDWORD) & 0x3FF0000) >> 16; 1901 MASKDWORD) & 0x3FF0000) >> 16;
1961 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1902 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1962 BMASKDWORD) & 0x3FF0000) >> 16; 1903 MASKDWORD) & 0x3FF0000) >> 16;
1963 result[t][6] = (rtl_get_bbreg(hw, 0xec4, 1904 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
1964 BMASKDWORD) & 0x3FF0000) >> 16; 1905 MASKDWORD) & 0x3FF0000) >> 16;
1965 result[t][7] = (rtl_get_bbreg(hw, 0xecc, 1906 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
1966 BMASKDWORD) & 0x3FF0000) >> 16; 1907 MASKDWORD) & 0x3FF0000) >> 16;
1967 break; 1908 break;
1968 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { 1909 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1969 /* Tx IQK OK */ 1910 /* Tx IQK OK */
1970 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1911 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1971 "Path B Only Tx IQK Success!!\n"); 1912 "Path B Only Tx IQK Success!!\n");
1972 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, 1913 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
1973 BMASKDWORD) & 0x3FF0000) >> 16; 1914 MASKDWORD) & 0x3FF0000) >> 16;
1974 result[t][5] = (rtl_get_bbreg(hw, 0xebc, 1915 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
1975 BMASKDWORD) & 0x3FF0000) >> 16; 1916 MASKDWORD) & 0x3FF0000) >> 16;
1976 } 1917 }
1977 } 1918 }
1978 if (0x00 == pathb_ok) 1919 if (0x00 == pathb_ok)
@@ -1984,7 +1925,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
1984 RTPRINT(rtlpriv, FINIT, INIT_IQK, 1925 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1985 "IQK:Back to BB mode, load original value!\n"); 1926 "IQK:Back to BB mode, load original value!\n");
1986 1927
1987 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0); 1928 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1988 if (t != 0) { 1929 if (t != 0) {
1989 /* Switch back BB to SI mode after finish IQ Calibration. */ 1930 /* Switch back BB to SI mode after finish IQ Calibration. */
1990 if (!rtlphy->rfpi_enable) 1931 if (!rtlphy->rfpi_enable)
@@ -2004,8 +1945,8 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2004 rtlphy->iqk_bb_backup, 1945 rtlphy->iqk_bb_backup,
2005 IQK_BB_REG_NUM - 1); 1946 IQK_BB_REG_NUM - 1);
2006 /* load 0xe30 IQC default value */ 1947 /* load 0xe30 IQC default value */
2007 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00); 1948 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
2008 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00); 1949 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
2009 } 1950 }
2010 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); 1951 RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n");
2011} 1952}
@@ -2042,7 +1983,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2042 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); 1983 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n");
2043 mdelay(IQK_DELAY_TIME * 20); 1984 mdelay(IQK_DELAY_TIME * 20);
2044 if (t == 0) { 1985 if (t == 0) {
2045 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD); 1986 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD);
2046 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); 1987 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue);
2047 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", 1988 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n",
2048 is2t ? "2T2R" : "1T1R"); 1989 is2t ? "2T2R" : "1T1R");
@@ -2072,38 +2013,38 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2072 if (!rtlphy->rfpi_enable) 2013 if (!rtlphy->rfpi_enable)
2073 _rtl92d_phy_pimode_switch(hw, true); 2014 _rtl92d_phy_pimode_switch(hw, true);
2074 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); 2015 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2075 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600); 2016 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600);
2076 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4); 2017 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4);
2077 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000); 2018 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000);
2078 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); 2019 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2079 2020
2080 /* Page B init */ 2021 /* Page B init */
2081 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000); 2022 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
2082 if (is2t) 2023 if (is2t)
2083 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000); 2024 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
2084 /* IQ calibration setting */ 2025 /* IQ calibration setting */
2085 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); 2026 RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n");
2086 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000); 2027 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
2087 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00); 2028 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00);
2088 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800); 2029 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
2089 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t); 2030 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2090 if (patha_ok == 0x03) { 2031 if (patha_ok == 0x03) {
2091 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); 2032 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n");
2092 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 2033 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2093 0x3FF0000) >> 16; 2034 0x3FF0000) >> 16;
2094 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 2035 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2095 0x3FF0000) >> 16; 2036 0x3FF0000) >> 16;
2096 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) & 2037 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
2097 0x3FF0000) >> 16; 2038 0x3FF0000) >> 16;
2098 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) & 2039 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
2099 0x3FF0000) >> 16; 2040 0x3FF0000) >> 16;
2100 } else if (patha_ok == 0x01) { /* Tx IQK OK */ 2041 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2101 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2042 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2102 "Path A IQK Only Tx Success!!\n"); 2043 "Path A IQK Only Tx Success!!\n");
2103 2044
2104 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) & 2045 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
2105 0x3FF0000) >> 16; 2046 0x3FF0000) >> 16;
2106 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) & 2047 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
2107 0x3FF0000) >> 16; 2048 0x3FF0000) >> 16;
2108 } else { 2049 } else {
2109 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); 2050 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n");
@@ -2116,20 +2057,20 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2116 if (pathb_ok == 0x03) { 2057 if (pathb_ok == 0x03) {
2117 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2058 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2118 "Path B IQK Success!!\n"); 2059 "Path B IQK Success!!\n");
2119 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) & 2060 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2120 0x3FF0000) >> 16; 2061 0x3FF0000) >> 16;
2121 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) & 2062 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2122 0x3FF0000) >> 16; 2063 0x3FF0000) >> 16;
2123 result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) & 2064 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
2124 0x3FF0000) >> 16; 2065 0x3FF0000) >> 16;
2125 result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) & 2066 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
2126 0x3FF0000) >> 16; 2067 0x3FF0000) >> 16;
2127 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ 2068 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2128 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2069 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2129 "Path B Only Tx IQK Success!!\n"); 2070 "Path B Only Tx IQK Success!!\n");
2130 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) & 2071 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) &
2131 0x3FF0000) >> 16; 2072 0x3FF0000) >> 16;
2132 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) & 2073 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
2133 0x3FF0000) >> 16; 2074 0x3FF0000) >> 16;
2134 } else { 2075 } else {
2135 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2076 RTPRINT(rtlpriv, FINIT, INIT_IQK,
@@ -2140,7 +2081,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2140 /* Back to BB mode, load original value */ 2081 /* Back to BB mode, load original value */
2141 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2082 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2142 "IQK:Back to BB mode, load original value!\n"); 2083 "IQK:Back to BB mode, load original value!\n");
2143 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0); 2084 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
2144 if (t != 0) { 2085 if (t != 0) {
2145 if (is2t) 2086 if (is2t)
2146 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg, 2087 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
@@ -2240,7 +2181,7 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2240 return; 2181 return;
2241 } else if (iqk_ok) { 2182 } else if (iqk_ok) {
2242 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2183 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2243 BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ 2184 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2244 val_x = result[final_candidate][0]; 2185 val_x = result[final_candidate][0];
2245 if ((val_x & 0x00000200) != 0) 2186 if ((val_x & 0x00000200) != 0)
2246 val_x = val_x | 0xFFFFFC00; 2187 val_x = val_x | 0xFFFFFC00;
@@ -2271,7 +2212,7 @@ static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2271 ((val_y * oldval_0 >> 7) & 0x1)); 2212 ((val_y * oldval_0 >> 7) & 0x1));
2272 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", 2213 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2273 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 2214 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2274 BMASKDWORD)); 2215 MASKDWORD));
2275 if (txonly) { 2216 if (txonly) {
2276 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); 2217 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
2277 return; 2218 return;
@@ -2299,7 +2240,7 @@ static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2299 return; 2240 return;
2300 } else if (iqk_ok) { 2241 } else if (iqk_ok) {
2301 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 2242 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2302 BMASKDWORD) >> 22) & 0x3FF; 2243 MASKDWORD) >> 22) & 0x3FF;
2303 val_x = result[final_candidate][4]; 2244 val_x = result[final_candidate][4];
2304 if ((val_x & 0x00000200) != 0) 2245 if ((val_x & 0x00000200) != 0)
2305 val_x = val_x | 0xFFFFFC00; 2246 val_x = val_x | 0xFFFFFC00;
@@ -2657,7 +2598,7 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2657 rf_mode[index] = rtl_read_byte(rtlpriv, offset); 2598 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2658 /* 2. Set RF mode = standby mode */ 2599 /* 2. Set RF mode = standby mode */
2659 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, 2600 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2660 BRFREGOFFSETMASK, 0x010000); 2601 RFREG_OFFSET_MASK, 0x010000);
2661 if (rtlpci->init_ready) { 2602 if (rtlpci->init_ready) {
2662 /* switch CV-curve control by LC-calibration */ 2603 /* switch CV-curve control by LC-calibration */
2663 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, 2604 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
@@ -2667,16 +2608,16 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2667 0x08000, 0x01); 2608 0x08000, 0x01);
2668 } 2609 }
2669 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, 2610 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2670 BRFREGOFFSETMASK); 2611 RFREG_OFFSET_MASK);
2671 while ((!(u4tmp & BIT(11))) && timecount <= timeout) { 2612 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2672 mdelay(50); 2613 mdelay(50);
2673 timecount += 50; 2614 timecount += 50;
2674 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, 2615 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2675 RF_SYN_G6, BRFREGOFFSETMASK); 2616 RF_SYN_G6, RFREG_OFFSET_MASK);
2676 } 2617 }
2677 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2618 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2678 "PHY_LCK finish delay for %d ms=2\n", timecount); 2619 "PHY_LCK finish delay for %d ms=2\n", timecount);
2679 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK); 2620 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK);
2680 if (index == 0 && rtlhal->interfaceindex == 0) { 2621 if (index == 0 && rtlhal->interfaceindex == 0) {
2681 RTPRINT(rtlpriv, FINIT, INIT_IQK, 2622 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2682 "path-A / 5G LCK\n"); 2623 "path-A / 5G LCK\n");
@@ -2696,9 +2637,9 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2696 0x7f, i); 2637 0x7f, i);
2697 2638
2698 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, 2639 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2699 BRFREGOFFSETMASK, 0x0); 2640 RFREG_OFFSET_MASK, 0x0);
2700 readval = rtl_get_rfreg(hw, (enum radio_path)index, 2641 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2701 0x4F, BRFREGOFFSETMASK); 2642 0x4F, RFREG_OFFSET_MASK);
2702 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; 2643 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2703 /* reg 0x4f [4:0] */ 2644 /* reg 0x4f [4:0] */
2704 /* reg 0x50 [19:10] */ 2645 /* reg 0x50 [19:10] */
@@ -2912,7 +2853,7 @@ static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2912 } 2853 }
2913 rtl_set_rfreg(hw, (enum radio_path)rfpath, 2854 rtl_set_rfreg(hw, (enum radio_path)rfpath,
2914 currentcmd->para1, 2855 currentcmd->para1,
2915 BRFREGOFFSETMASK, 2856 RFREG_OFFSET_MASK,
2916 rtlphy->rfreg_chnlval[rfpath]); 2857 rtlphy->rfreg_chnlval[rfpath]);
2917 _rtl92d_phy_reload_imr_setting(hw, channel, 2858 _rtl92d_phy_reload_imr_setting(hw, channel,
2918 rfpath); 2859 rfpath);
@@ -2960,7 +2901,7 @@ u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
2960 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && 2901 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
2961 rtlhal->bandset == BAND_ON_BOTH) { 2902 rtlhal->bandset == BAND_ON_BOTH) {
2962 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, 2903 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
2963 BMASKDWORD); 2904 MASKDWORD);
2964 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) 2905 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
2965 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G); 2906 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
2966 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) 2907 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
@@ -3112,7 +3053,7 @@ static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3112 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ 3053 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
3113 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); 3054 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3114 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ 3055 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
3115 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00); 3056 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3116 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ 3057 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
3117 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3058 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3118 /* d. APSD_CTRL 0x600[7:0] = 0x00 3059 /* d. APSD_CTRL 0x600[7:0] = 0x00
@@ -3120,12 +3061,12 @@ static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3120 * RF path 0 offset 0x00 = 0x00 3061 * RF path 0 offset 0x00 = 0x00
3121 * APSD_CTRL 0x600[7:0] = 0x40 3062 * APSD_CTRL 0x600[7:0] = 0x40
3122 * */ 3063 * */
3123 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK); 3064 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3124 while (u4btmp != 0 && delay > 0) { 3065 while (u4btmp != 0 && delay > 0) {
3125 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); 3066 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3126 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00); 3067 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
3127 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 3068 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3128 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK); 3069 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
3129 delay--; 3070 delay--;
3130 } 3071 }
3131 if (delay == 0) { 3072 if (delay == 0) {
@@ -3468,9 +3409,9 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3468 /* 5G LAN ON */ 3409 /* 5G LAN ON */
3469 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); 3410 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3470 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ 3411 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3471 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD, 3412 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3472 0x40000100); 3413 0x40000100);
3473 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD, 3414 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3474 0x40000100); 3415 0x40000100);
3475 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3416 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3476 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3417 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
@@ -3524,16 +3465,16 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3524 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); 3465 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3525 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ 3466 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3526 if (rtlefuse->internal_pa_5g[0]) 3467 if (rtlefuse->internal_pa_5g[0])
3527 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD, 3468 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3528 0x2d4000b5); 3469 0x2d4000b5);
3529 else 3470 else
3530 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD, 3471 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3531 0x20000080); 3472 0x20000080);
3532 if (rtlefuse->internal_pa_5g[1]) 3473 if (rtlefuse->internal_pa_5g[1])
3533 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD, 3474 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3534 0x2d4000b5); 3475 0x2d4000b5);
3535 else 3476 else
3536 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD, 3477 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3537 0x20000080); 3478 0x20000080);
3538 if (rtlhal->macphymode == DUALMAC_DUALPHY) { 3479 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3539 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, 3480 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
@@ -3560,8 +3501,8 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3560 } 3501 }
3561 } 3502 }
3562 /* update IQK related settings */ 3503 /* update IQK related settings */
3563 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100); 3504 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3564 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100); 3505 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3565 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00); 3506 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3566 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | 3507 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3567 BIT(26) | BIT(24), 0x00); 3508 BIT(26) | BIT(24), 0x00);
@@ -3590,7 +3531,7 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3590 /* DMDP */ 3531 /* DMDP */
3591 if (rtlphy->rf_type == RF_1T1R) { 3532 if (rtlphy->rf_type == RF_1T1R) {
3592 /* Use antenna 0,0xc04,0xd04 */ 3533 /* Use antenna 0,0xc04,0xd04 */
3593 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11); 3534 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11);
3594 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); 3535 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3595 3536
3596 /* enable ad/da clock1 for dual-phy reg0x888 */ 3537 /* enable ad/da clock1 for dual-phy reg0x888 */
@@ -3612,7 +3553,7 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3612 } else { 3553 } else {
3613 /* Single PHY */ 3554 /* Single PHY */
3614 /* Use antenna 0 & 1,0xc04,0xd04 */ 3555 /* Use antenna 0 & 1,0xc04,0xd04 */
3615 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33); 3556 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33);
3616 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); 3557 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3617 /* disable ad/da clock1,0x888 */ 3558 /* disable ad/da clock1,0x888 */
3618 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); 3559 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
@@ -3620,9 +3561,9 @@ void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3620 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 3561 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3621 rfpath++) { 3562 rfpath++) {
3622 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, 3563 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3623 RF_CHNLBW, BRFREGOFFSETMASK); 3564 RF_CHNLBW, RFREG_OFFSET_MASK);
3624 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, 3565 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3625 BRFREGOFFSETMASK); 3566 RFREG_OFFSET_MASK);
3626 } 3567 }
3627 for (i = 0; i < 2; i++) 3568 for (i = 0; i < 2; i++)
3628 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", 3569 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n",
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 11:51:07 -0500