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-rw-r--r--drivers/net/wireless/rt2x00/Kconfig12
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c183
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c179
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c17
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h139
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c917
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.h4
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c239
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c4
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h67
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dev.c74
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00ht.c29
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00lib.h24
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00link.c7
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00mac.c75
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c7
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.c178
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h31
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00reg.h2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c8
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c251
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c75
22 files changed, 1796 insertions, 726 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 6f383cd684b0..f630552427b7 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -97,6 +97,18 @@ config RT2800PCI_RT35XX
97 Support for these devices is non-functional at the moment and is 97 Support for these devices is non-functional at the moment and is
98 intended for testers and developers. 98 intended for testers and developers.
99 99
100config RT2800PCI_RT53XX
101 bool "rt2800-pci - Include support for rt53xx devices (EXPERIMENTAL)"
102 depends on EXPERIMENTAL
103 default n
104 ---help---
105 This adds support for rt53xx wireless chipset family to the
106 rt2800pci driver.
107 Supported chips: RT5390
108
109 Support for these devices is non-functional at the moment and is
110 intended for testers and developers.
111
100endif 112endif
101 113
102config RT2500USB 114config RT2500USB
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 54ca49ad3472..329f3283697b 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -46,7 +46,7 @@
46 * These indirect registers work with busy bits, 46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access 47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay 48 * the register while taking a REGISTER_BUSY_DELAY us delay
49 * between each attampt. When the busy bit is still set at that time, 49 * between each attempt. When the busy bit is still set at that time,
50 * the access attempt is considered to have failed, 50 * the access attempt is considered to have failed,
51 * and we will print an error. 51 * and we will print an error.
52 */ 52 */
@@ -305,9 +305,7 @@ static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
305 * Enable synchronisation. 305 * Enable synchronisation.
306 */ 306 */
307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
308 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
309 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync); 308 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
310 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
311 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 309 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
312 } 310 }
313 311
@@ -647,6 +645,11 @@ static void rt2400pci_start_queue(struct data_queue *queue)
647 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); 645 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
648 break; 646 break;
649 case QID_BEACON: 647 case QID_BEACON:
648 /*
649 * Allow the tbtt tasklet to be scheduled.
650 */
651 tasklet_enable(&rt2x00dev->tbtt_tasklet);
652
650 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 653 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
651 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); 654 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
652 rt2x00_set_field32(&reg, CSR14_TBCN, 1); 655 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
@@ -708,6 +711,11 @@ static void rt2400pci_stop_queue(struct data_queue *queue)
708 rt2x00_set_field32(&reg, CSR14_TBCN, 0); 711 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
709 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 712 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
710 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 713 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
714
715 /*
716 * Wait for possibly running tbtt tasklets.
717 */
718 tasklet_disable(&rt2x00dev->tbtt_tasklet);
711 break; 719 break;
712 default: 720 default:
713 break; 721 break;
@@ -771,7 +779,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
771 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg); 779 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
772 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); 780 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
773 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); 781 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
774 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); 782 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
775 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 783 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
776 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 784 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
777 785
@@ -787,13 +795,13 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
787 entry_priv->desc_dma); 795 entry_priv->desc_dma);
788 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 796 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
789 797
790 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; 798 entry_priv = rt2x00dev->atim->entries[0].priv_data;
791 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 799 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
792 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 800 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
793 entry_priv->desc_dma); 801 entry_priv->desc_dma);
794 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 802 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
795 803
796 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; 804 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
797 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 805 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
798 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 806 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
799 entry_priv->desc_dma); 807 entry_priv->desc_dma);
@@ -963,9 +971,9 @@ static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
963static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 971static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
964 enum dev_state state) 972 enum dev_state state)
965{ 973{
966 int mask = (state == STATE_RADIO_IRQ_OFF) || 974 int mask = (state == STATE_RADIO_IRQ_OFF);
967 (state == STATE_RADIO_IRQ_OFF_ISR);
968 u32 reg; 975 u32 reg;
976 unsigned long flags;
969 977
970 /* 978 /*
971 * When interrupts are being enabled, the interrupt registers 979 * When interrupts are being enabled, the interrupt registers
@@ -974,12 +982,20 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
974 if (state == STATE_RADIO_IRQ_ON) { 982 if (state == STATE_RADIO_IRQ_ON) {
975 rt2x00pci_register_read(rt2x00dev, CSR7, &reg); 983 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
976 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 984 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
985
986 /*
987 * Enable tasklets.
988 */
989 tasklet_enable(&rt2x00dev->txstatus_tasklet);
990 tasklet_enable(&rt2x00dev->rxdone_tasklet);
977 } 991 }
978 992
979 /* 993 /*
980 * Only toggle the interrupts bits we are going to use. 994 * Only toggle the interrupts bits we are going to use.
981 * Non-checked interrupt bits are disabled by default. 995 * Non-checked interrupt bits are disabled by default.
982 */ 996 */
997 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
998
983 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 999 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
984 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask); 1000 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
985 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask); 1001 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
@@ -987,6 +1003,17 @@ static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
987 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask); 1003 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
988 rt2x00_set_field32(&reg, CSR8_RXDONE, mask); 1004 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
989 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 1005 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1006
1007 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1008
1009 if (state == STATE_RADIO_IRQ_OFF) {
1010 /*
1011 * Ensure that all tasklets are finished before
1012 * disabling the interrupts.
1013 */
1014 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1015 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1016 }
990} 1017}
991 1018
992static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1019static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1059,9 +1086,7 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1059 rt2400pci_disable_radio(rt2x00dev); 1086 rt2400pci_disable_radio(rt2x00dev);
1060 break; 1087 break;
1061 case STATE_RADIO_IRQ_ON: 1088 case STATE_RADIO_IRQ_ON:
1062 case STATE_RADIO_IRQ_ON_ISR:
1063 case STATE_RADIO_IRQ_OFF: 1089 case STATE_RADIO_IRQ_OFF:
1064 case STATE_RADIO_IRQ_OFF_ISR:
1065 rt2400pci_toggle_irq(rt2x00dev, state); 1090 rt2400pci_toggle_irq(rt2x00dev, state);
1066 break; 1091 break;
1067 case STATE_DEEP_SLEEP: 1092 case STATE_DEEP_SLEEP:
@@ -1106,19 +1131,21 @@ static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1106 rt2x00_desc_write(txd, 2, word); 1131 rt2x00_desc_write(txd, 2, word);
1107 1132
1108 rt2x00_desc_read(txd, 3, &word); 1133 rt2x00_desc_read(txd, 3, &word);
1109 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); 1134 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1110 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); 1135 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1111 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); 1136 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1112 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); 1137 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1113 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); 1138 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1114 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); 1139 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1115 rt2x00_desc_write(txd, 3, word); 1140 rt2x00_desc_write(txd, 3, word);
1116 1141
1117 rt2x00_desc_read(txd, 4, &word); 1142 rt2x00_desc_read(txd, 4, &word);
1118 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low); 1143 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1144 txdesc->u.plcp.length_low);
1119 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); 1145 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1120 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); 1146 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1121 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high); 1147 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1148 txdesc->u.plcp.length_high);
1122 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); 1149 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1123 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); 1150 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1124 rt2x00_desc_write(txd, 4, word); 1151 rt2x00_desc_write(txd, 4, word);
@@ -1139,7 +1166,7 @@ static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1139 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1166 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1140 rt2x00_set_field32(&word, TXD_W0_RTS, 1167 rt2x00_set_field32(&word, TXD_W0_RTS,
1141 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); 1168 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1142 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1169 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1143 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1170 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1144 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1171 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1145 rt2x00_desc_write(txd, 0, word); 1172 rt2x00_desc_write(txd, 0, word);
@@ -1183,8 +1210,6 @@ static void rt2400pci_write_beacon(struct queue_entry *entry,
1183 /* 1210 /*
1184 * Enable beaconing again. 1211 * Enable beaconing again.
1185 */ 1212 */
1186 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1187 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1188 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); 1213 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1189 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1214 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1190} 1215}
@@ -1253,7 +1278,7 @@ static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1253static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, 1278static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1254 const enum data_queue_qid queue_idx) 1279 const enum data_queue_qid queue_idx)
1255{ 1280{
1256 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1281 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1257 struct queue_entry_priv_pci *entry_priv; 1282 struct queue_entry_priv_pci *entry_priv;
1258 struct queue_entry *entry; 1283 struct queue_entry *entry;
1259 struct txdone_entry_desc txdesc; 1284 struct txdone_entry_desc txdesc;
@@ -1289,57 +1314,68 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1289 } 1314 }
1290} 1315}
1291 1316
1292static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance) 1317static void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1318 struct rt2x00_field32 irq_field)
1293{ 1319{
1294 struct rt2x00_dev *rt2x00dev = dev_instance; 1320 u32 reg;
1295 u32 reg = rt2x00dev->irqvalue[0];
1296 1321
1297 /* 1322 /*
1298 * Handle interrupts, walk through all bits 1323 * Enable a single interrupt. The interrupt mask register
1299 * and run the tasks, the bits are checked in order of 1324 * access needs locking.
1300 * priority.
1301 */ 1325 */
1326 spin_lock_irq(&rt2x00dev->irqmask_lock);
1302 1327
1303 /* 1328 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1304 * 1 - Beacon timer expired interrupt. 1329 rt2x00_set_field32(&reg, irq_field, 0);
1305 */ 1330 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1306 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1307 rt2x00lib_beacondone(rt2x00dev);
1308 1331
1309 /* 1332 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1310 * 2 - Rx ring done interrupt. 1333}
1311 */
1312 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1313 rt2x00pci_rxdone(rt2x00dev);
1314 1334
1315 /* 1335static void rt2400pci_txstatus_tasklet(unsigned long data)
1316 * 3 - Atim ring transmit done interrupt. 1336{
1317 */ 1337 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1318 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1338 u32 reg;
1319 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1320 1339
1321 /* 1340 /*
1322 * 4 - Priority ring transmit done interrupt. 1341 * Handle all tx queues.
1323 */ 1342 */
1324 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) 1343 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1325 rt2400pci_txdone(rt2x00dev, QID_AC_VO); 1344 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1345 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1326 1346
1327 /* 1347 /*
1328 * 5 - Tx ring transmit done interrupt. 1348 * Enable all TXDONE interrupts again.
1329 */ 1349 */
1330 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) 1350 spin_lock_irq(&rt2x00dev->irqmask_lock);
1331 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1332 1351
1333 /* Enable interrupts again. */ 1352 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1334 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 1353 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1335 STATE_RADIO_IRQ_ON_ISR); 1354 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1336 return IRQ_HANDLED; 1355 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1356 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1357
1358 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1359}
1360
1361static void rt2400pci_tbtt_tasklet(unsigned long data)
1362{
1363 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1364 rt2x00lib_beacondone(rt2x00dev);
1365 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1366}
1367
1368static void rt2400pci_rxdone_tasklet(unsigned long data)
1369{
1370 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1371 rt2x00pci_rxdone(rt2x00dev);
1372 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1337} 1373}
1338 1374
1339static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) 1375static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1340{ 1376{
1341 struct rt2x00_dev *rt2x00dev = dev_instance; 1377 struct rt2x00_dev *rt2x00dev = dev_instance;
1342 u32 reg; 1378 u32 reg, mask;
1343 1379
1344 /* 1380 /*
1345 * Get the interrupt sources & saved to local variable. 1381 * Get the interrupt sources & saved to local variable.
@@ -1354,14 +1390,44 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1354 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1390 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1355 return IRQ_HANDLED; 1391 return IRQ_HANDLED;
1356 1392
1357 /* Store irqvalues for use in the interrupt thread. */ 1393 mask = reg;
1358 rt2x00dev->irqvalue[0] = reg;
1359 1394
1360 /* Disable interrupts, will be enabled again in the interrupt thread. */ 1395 /*
1361 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 1396 * Schedule tasklets for interrupt handling.
1362 STATE_RADIO_IRQ_OFF_ISR); 1397 */
1398 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1399 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1363 1400
1364 return IRQ_WAKE_THREAD; 1401 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1402 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1403
1404 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1405 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1406 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1407 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1408 /*
1409 * Mask out all txdone interrupts.
1410 */
1411 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1412 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1413 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1414 }
1415
1416 /*
1417 * Disable all interrupts for which a tasklet was scheduled right now,
1418 * the tasklet will reenable the appropriate interrupts.
1419 */
1420 spin_lock(&rt2x00dev->irqmask_lock);
1421
1422 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1423 reg |= mask;
1424 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1425
1426 spin_unlock(&rt2x00dev->irqmask_lock);
1427
1428
1429
1430 return IRQ_HANDLED;
1365} 1431}
1366 1432
1367/* 1433/*
@@ -1574,6 +1640,7 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1574 */ 1640 */
1575 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1641 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1576 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 1642 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1643 __set_bit(DRIVER_REQUIRE_SW_SEQNO, &rt2x00dev->flags);
1577 1644
1578 /* 1645 /*
1579 * Set the rssi offset. 1646 * Set the rssi offset.
@@ -1655,7 +1722,9 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1655 1722
1656static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = { 1723static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1657 .irq_handler = rt2400pci_interrupt, 1724 .irq_handler = rt2400pci_interrupt,
1658 .irq_handler_thread = rt2400pci_interrupt_thread, 1725 .txstatus_tasklet = rt2400pci_txstatus_tasklet,
1726 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1727 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
1659 .probe_hw = rt2400pci_probe_hw, 1728 .probe_hw = rt2400pci_probe_hw,
1660 .initialize = rt2x00pci_initialize, 1729 .initialize = rt2x00pci_initialize,
1661 .uninitialize = rt2x00pci_uninitialize, 1730 .uninitialize = rt2x00pci_uninitialize,
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index a9ff26a27724..58277878889e 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -293,7 +293,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
293 struct rt2x00intf_conf *conf, 293 struct rt2x00intf_conf *conf,
294 const unsigned int flags) 294 const unsigned int flags)
295{ 295{
296 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); 296 struct data_queue *queue = rt2x00dev->bcn;
297 unsigned int bcn_preload; 297 unsigned int bcn_preload;
298 u32 reg; 298 u32 reg;
299 299
@@ -311,9 +311,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
311 * Enable synchronisation. 311 * Enable synchronisation.
312 */ 312 */
313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 313 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
314 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
315 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync); 314 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
316 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
317 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 315 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
318 } 316 }
319 317
@@ -737,6 +735,11 @@ static void rt2500pci_start_queue(struct data_queue *queue)
737 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); 735 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
738 break; 736 break;
739 case QID_BEACON: 737 case QID_BEACON:
738 /*
739 * Allow the tbtt tasklet to be scheduled.
740 */
741 tasklet_enable(&rt2x00dev->tbtt_tasklet);
742
740 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 743 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
741 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); 744 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
742 rt2x00_set_field32(&reg, CSR14_TBCN, 1); 745 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
@@ -798,6 +801,11 @@ static void rt2500pci_stop_queue(struct data_queue *queue)
798 rt2x00_set_field32(&reg, CSR14_TBCN, 0); 801 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
799 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 802 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
800 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 803 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
804
805 /*
806 * Wait for possibly running tbtt tasklets.
807 */
808 tasklet_disable(&rt2x00dev->tbtt_tasklet);
801 break; 809 break;
802 default: 810 default:
803 break; 811 break;
@@ -857,7 +865,7 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
857 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg); 865 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
858 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); 866 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
859 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); 867 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
860 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); 868 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
861 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 869 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
862 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 870 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
863 871
@@ -873,13 +881,13 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
873 entry_priv->desc_dma); 881 entry_priv->desc_dma);
874 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 882 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
875 883
876 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; 884 entry_priv = rt2x00dev->atim->entries[0].priv_data;
877 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 885 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
878 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 886 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
879 entry_priv->desc_dma); 887 entry_priv->desc_dma);
880 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 888 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
881 889
882 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; 890 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
883 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 891 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
884 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 892 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
885 entry_priv->desc_dma); 893 entry_priv->desc_dma);
@@ -1118,9 +1126,9 @@ static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1118static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1126static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1119 enum dev_state state) 1127 enum dev_state state)
1120{ 1128{
1121 int mask = (state == STATE_RADIO_IRQ_OFF) || 1129 int mask = (state == STATE_RADIO_IRQ_OFF);
1122 (state == STATE_RADIO_IRQ_OFF_ISR);
1123 u32 reg; 1130 u32 reg;
1131 unsigned long flags;
1124 1132
1125 /* 1133 /*
1126 * When interrupts are being enabled, the interrupt registers 1134 * When interrupts are being enabled, the interrupt registers
@@ -1129,12 +1137,20 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1129 if (state == STATE_RADIO_IRQ_ON) { 1137 if (state == STATE_RADIO_IRQ_ON) {
1130 rt2x00pci_register_read(rt2x00dev, CSR7, &reg); 1138 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1131 rt2x00pci_register_write(rt2x00dev, CSR7, reg); 1139 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1140
1141 /*
1142 * Enable tasklets.
1143 */
1144 tasklet_enable(&rt2x00dev->txstatus_tasklet);
1145 tasklet_enable(&rt2x00dev->rxdone_tasklet);
1132 } 1146 }
1133 1147
1134 /* 1148 /*
1135 * Only toggle the interrupts bits we are going to use. 1149 * Only toggle the interrupts bits we are going to use.
1136 * Non-checked interrupt bits are disabled by default. 1150 * Non-checked interrupt bits are disabled by default.
1137 */ 1151 */
1152 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1153
1138 rt2x00pci_register_read(rt2x00dev, CSR8, &reg); 1154 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1139 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask); 1155 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1140 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask); 1156 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
@@ -1142,6 +1158,16 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1142 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask); 1158 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1143 rt2x00_set_field32(&reg, CSR8_RXDONE, mask); 1159 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1144 rt2x00pci_register_write(rt2x00dev, CSR8, reg); 1160 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1161
1162 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1163
1164 if (state == STATE_RADIO_IRQ_OFF) {
1165 /*
1166 * Ensure that all tasklets are finished.
1167 */
1168 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1169 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1170 }
1145} 1171}
1146 1172
1147static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1173static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1214,9 +1240,7 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1214 rt2500pci_disable_radio(rt2x00dev); 1240 rt2500pci_disable_radio(rt2x00dev);
1215 break; 1241 break;
1216 case STATE_RADIO_IRQ_ON: 1242 case STATE_RADIO_IRQ_ON:
1217 case STATE_RADIO_IRQ_ON_ISR:
1218 case STATE_RADIO_IRQ_OFF: 1243 case STATE_RADIO_IRQ_OFF:
1219 case STATE_RADIO_IRQ_OFF_ISR:
1220 rt2500pci_toggle_irq(rt2x00dev, state); 1244 rt2500pci_toggle_irq(rt2x00dev, state);
1221 break; 1245 break;
1222 case STATE_DEEP_SLEEP: 1246 case STATE_DEEP_SLEEP:
@@ -1263,10 +1287,12 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1263 rt2x00_desc_write(txd, 2, word); 1287 rt2x00_desc_write(txd, 2, word);
1264 1288
1265 rt2x00_desc_read(txd, 3, &word); 1289 rt2x00_desc_read(txd, 3, &word);
1266 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); 1290 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1267 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); 1291 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1268 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low); 1292 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW,
1269 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high); 1293 txdesc->u.plcp.length_low);
1294 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH,
1295 txdesc->u.plcp.length_high);
1270 rt2x00_desc_write(txd, 3, word); 1296 rt2x00_desc_write(txd, 3, word);
1271 1297
1272 rt2x00_desc_read(txd, 10, &word); 1298 rt2x00_desc_read(txd, 10, &word);
@@ -1291,7 +1317,7 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry,
1291 rt2x00_set_field32(&word, TXD_W0_OFDM, 1317 rt2x00_set_field32(&word, TXD_W0_OFDM,
1292 (txdesc->rate_mode == RATE_MODE_OFDM)); 1318 (txdesc->rate_mode == RATE_MODE_OFDM));
1293 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); 1319 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1294 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1320 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1295 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1321 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1296 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1322 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1297 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1323 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
@@ -1337,8 +1363,6 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
1337 /* 1363 /*
1338 * Enable beaconing again. 1364 * Enable beaconing again.
1339 */ 1365 */
1340 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1341 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1342 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1); 1366 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1343 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1367 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1344} 1368}
@@ -1386,7 +1410,7 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1386static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, 1410static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1387 const enum data_queue_qid queue_idx) 1411 const enum data_queue_qid queue_idx)
1388{ 1412{
1389 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1413 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1390 struct queue_entry_priv_pci *entry_priv; 1414 struct queue_entry_priv_pci *entry_priv;
1391 struct queue_entry *entry; 1415 struct queue_entry *entry;
1392 struct txdone_entry_desc txdesc; 1416 struct txdone_entry_desc txdesc;
@@ -1422,58 +1446,68 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1422 } 1446 }
1423} 1447}
1424 1448
1425static irqreturn_t rt2500pci_interrupt_thread(int irq, void *dev_instance) 1449static void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1450 struct rt2x00_field32 irq_field)
1426{ 1451{
1427 struct rt2x00_dev *rt2x00dev = dev_instance; 1452 u32 reg;
1428 u32 reg = rt2x00dev->irqvalue[0];
1429 1453
1430 /* 1454 /*
1431 * Handle interrupts, walk through all bits 1455 * Enable a single interrupt. The interrupt mask register
1432 * and run the tasks, the bits are checked in order of 1456 * access needs locking.
1433 * priority.
1434 */ 1457 */
1458 spin_lock_irq(&rt2x00dev->irqmask_lock);
1435 1459
1436 /* 1460 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1437 * 1 - Beacon timer expired interrupt. 1461 rt2x00_set_field32(&reg, irq_field, 0);
1438 */ 1462 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1439 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1440 rt2x00lib_beacondone(rt2x00dev);
1441 1463
1442 /* 1464 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1443 * 2 - Rx ring done interrupt. 1465}
1444 */
1445 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1446 rt2x00pci_rxdone(rt2x00dev);
1447 1466
1448 /* 1467static void rt2500pci_txstatus_tasklet(unsigned long data)
1449 * 3 - Atim ring transmit done interrupt. 1468{
1450 */ 1469 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1451 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1470 u32 reg;
1452 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1453 1471
1454 /* 1472 /*
1455 * 4 - Priority ring transmit done interrupt. 1473 * Handle all tx queues.
1456 */ 1474 */
1457 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) 1475 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1458 rt2500pci_txdone(rt2x00dev, QID_AC_VO); 1476 rt2500pci_txdone(rt2x00dev, QID_AC_VO);
1477 rt2500pci_txdone(rt2x00dev, QID_AC_VI);
1459 1478
1460 /* 1479 /*
1461 * 5 - Tx ring transmit done interrupt. 1480 * Enable all TXDONE interrupts again.
1462 */ 1481 */
1463 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) 1482 spin_lock_irq(&rt2x00dev->irqmask_lock);
1464 rt2500pci_txdone(rt2x00dev, QID_AC_VI); 1483
1484 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1485 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1486 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1487 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1488 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1465 1489
1466 /* Enable interrupts again. */ 1490 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1467 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 1491}
1468 STATE_RADIO_IRQ_ON_ISR);
1469 1492
1470 return IRQ_HANDLED; 1493static void rt2500pci_tbtt_tasklet(unsigned long data)
1494{
1495 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1496 rt2x00lib_beacondone(rt2x00dev);
1497 rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1498}
1499
1500static void rt2500pci_rxdone_tasklet(unsigned long data)
1501{
1502 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1503 rt2x00pci_rxdone(rt2x00dev);
1504 rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1471} 1505}
1472 1506
1473static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) 1507static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1474{ 1508{
1475 struct rt2x00_dev *rt2x00dev = dev_instance; 1509 struct rt2x00_dev *rt2x00dev = dev_instance;
1476 u32 reg; 1510 u32 reg, mask;
1477 1511
1478 /* 1512 /*
1479 * Get the interrupt sources & saved to local variable. 1513 * Get the interrupt sources & saved to local variable.
@@ -1488,14 +1522,42 @@ static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1488 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 1522 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1489 return IRQ_HANDLED; 1523 return IRQ_HANDLED;
1490 1524
1491 /* Store irqvalues for use in the interrupt thread. */ 1525 mask = reg;
1492 rt2x00dev->irqvalue[0] = reg;
1493 1526
1494 /* Disable interrupts, will be enabled again in the interrupt thread. */ 1527 /*
1495 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 1528 * Schedule tasklets for interrupt handling.
1496 STATE_RADIO_IRQ_OFF_ISR); 1529 */
1530 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1531 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1497 1532
1498 return IRQ_WAKE_THREAD; 1533 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1534 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1535
1536 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1537 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1538 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1539 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1540 /*
1541 * Mask out all txdone interrupts.
1542 */
1543 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1544 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1545 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1546 }
1547
1548 /*
1549 * Disable all interrupts for which a tasklet was scheduled right now,
1550 * the tasklet will reenable the appropriate interrupts.
1551 */
1552 spin_lock(&rt2x00dev->irqmask_lock);
1553
1554 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1555 reg |= mask;
1556 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1557
1558 spin_unlock(&rt2x00dev->irqmask_lock);
1559
1560 return IRQ_HANDLED;
1499} 1561}
1500 1562
1501/* 1563/*
@@ -1896,6 +1958,7 @@ static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1896 */ 1958 */
1897 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1959 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1898 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); 1960 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1961 __set_bit(DRIVER_REQUIRE_SW_SEQNO, &rt2x00dev->flags);
1899 1962
1900 /* 1963 /*
1901 * Set the rssi offset. 1964 * Set the rssi offset.
@@ -1952,7 +2015,9 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1952 2015
1953static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { 2016static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1954 .irq_handler = rt2500pci_interrupt, 2017 .irq_handler = rt2500pci_interrupt,
1955 .irq_handler_thread = rt2500pci_interrupt_thread, 2018 .txstatus_tasklet = rt2500pci_txstatus_tasklet,
2019 .tbtt_tasklet = rt2500pci_tbtt_tasklet,
2020 .rxdone_tasklet = rt2500pci_rxdone_tasklet,
1956 .probe_hw = rt2500pci_probe_hw, 2021 .probe_hw = rt2500pci_probe_hw,
1957 .initialize = rt2x00pci_initialize, 2022 .initialize = rt2x00pci_initialize,
1958 .uninitialize = rt2x00pci_uninitialize, 2023 .uninitialize = rt2x00pci_uninitialize,
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index 6b3b1de46792..979fe6596a2d 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -478,9 +478,7 @@ static void rt2500usb_config_intf(struct rt2x00_dev *rt2x00dev,
478 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg); 478 rt2500usb_register_write(rt2x00dev, TXRX_CSR18, reg);
479 479
480 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg); 480 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
481 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
482 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync); 481 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_SYNC, conf->sync);
483 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
484 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); 482 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
485 } 483 }
486 484
@@ -1056,9 +1054,7 @@ static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1056 rt2500usb_disable_radio(rt2x00dev); 1054 rt2500usb_disable_radio(rt2x00dev);
1057 break; 1055 break;
1058 case STATE_RADIO_IRQ_ON: 1056 case STATE_RADIO_IRQ_ON:
1059 case STATE_RADIO_IRQ_ON_ISR:
1060 case STATE_RADIO_IRQ_OFF: 1057 case STATE_RADIO_IRQ_OFF:
1061 case STATE_RADIO_IRQ_OFF_ISR:
1062 /* No support, but no error either */ 1058 /* No support, but no error either */
1063 break; 1059 break;
1064 case STATE_DEEP_SLEEP: 1060 case STATE_DEEP_SLEEP:
@@ -1104,7 +1100,7 @@ static void rt2500usb_write_tx_desc(struct queue_entry *entry,
1104 (txdesc->rate_mode == RATE_MODE_OFDM)); 1100 (txdesc->rate_mode == RATE_MODE_OFDM));
1105 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ, 1101 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
1106 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)); 1102 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1107 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1103 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1108 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); 1104 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1109 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher); 1105 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher);
1110 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx); 1106 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
@@ -1118,10 +1114,12 @@ static void rt2500usb_write_tx_desc(struct queue_entry *entry,
1118 rt2x00_desc_write(txd, 1, word); 1114 rt2x00_desc_write(txd, 1, word);
1119 1115
1120 rt2x00_desc_read(txd, 2, &word); 1116 rt2x00_desc_read(txd, 2, &word);
1121 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); 1117 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1122 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); 1118 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1123 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); 1119 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1124 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); 1120 txdesc->u.plcp.length_low);
1121 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1122 txdesc->u.plcp.length_high);
1125 rt2x00_desc_write(txd, 2, word); 1123 rt2x00_desc_write(txd, 2, word);
1126 1124
1127 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1125 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
@@ -1799,6 +1797,7 @@ static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1799 __set_bit(DRIVER_REQUIRE_COPY_IV, &rt2x00dev->flags); 1797 __set_bit(DRIVER_REQUIRE_COPY_IV, &rt2x00dev->flags);
1800 } 1798 }
1801 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags); 1799 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags);
1800 __set_bit(DRIVER_REQUIRE_SW_SEQNO, &rt2x00dev->flags);
1802 1801
1803 /* 1802 /*
1804 * Set the rssi offset. 1803 * Set the rssi offset.
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 4c55e8525cad..70b9abbdeb9e 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -51,6 +51,7 @@
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390) 51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392) 52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662) 53 * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5390 2.4G 1T1R
54 */ 55 */
55#define RF2820 0x0001 56#define RF2820 0x0001
56#define RF2850 0x0002 57#define RF2850 0x0002
@@ -65,6 +66,7 @@
65#define RF3320 0x000b 66#define RF3320 0x000b
66#define RF3322 0x000c 67#define RF3322 0x000c
67#define RF3853 0x000d 68#define RF3853 0x000d
69#define RF5390 0x5390
68 70
69/* 71/*
70 * Chipset revisions. 72 * Chipset revisions.
@@ -77,6 +79,7 @@
77#define REV_RT3071E 0x0211 79#define REV_RT3071E 0x0211
78#define REV_RT3090E 0x0211 80#define REV_RT3090E 0x0211
79#define REV_RT3390E 0x0211 81#define REV_RT3390E 0x0211
82#define REV_RT5390F 0x0502
80 83
81/* 84/*
82 * Signal information. 85 * Signal information.
@@ -121,6 +124,13 @@
121#define E2PROM_CSR_RELOAD FIELD32(0x00000080) 124#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
122 125
123/* 126/*
127 * AUX_CTRL: Aux/PCI-E related configuration
128 */
129#define AUX_CTRL 0x10c
130#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
131#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
132
133/*
124 * OPT_14: Unknown register used by rt3xxx devices. 134 * OPT_14: Unknown register used by rt3xxx devices.
125 */ 135 */
126#define OPT_14_CSR 0x0114 136#define OPT_14_CSR 0x0114
@@ -270,6 +280,7 @@
270 280
271/* 281/*
272 * GPIO_CTRL_CFG: 282 * GPIO_CTRL_CFG:
283 * GPIOD: GPIO direction, 0: Output, 1: Input
273 */ 284 */
274#define GPIO_CTRL_CFG 0x0228 285#define GPIO_CTRL_CFG 0x0228
275#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001) 286#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
@@ -280,7 +291,14 @@
280#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020) 291#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
281#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040) 292#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
282#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080) 293#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
283#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100) 294#define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100)
295#define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200)
296#define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400)
297#define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800)
298#define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000)
299#define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000)
300#define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000)
301#define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000)
284 302
285/* 303/*
286 * MCU_CMD_CFG 304 * MCU_CMD_CFG
@@ -372,8 +390,12 @@
372 390
373/* 391/*
374 * US_CYC_CNT 392 * US_CYC_CNT
393 * BT_MODE_EN: Bluetooth mode enable
394 * CLOCK CYCLE: Clock cycle count in 1us.
395 * PCI:0x21, PCIE:0x7d, USB:0x1e
375 */ 396 */
376#define US_CYC_CNT 0x02a4 397#define US_CYC_CNT 0x02a4
398#define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
377#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff) 399#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
378 400
379/* 401/*
@@ -442,7 +464,7 @@
442 */ 464 */
443#define RF_CSR_CFG 0x0500 465#define RF_CSR_CFG 0x0500
444#define RF_CSR_CFG_DATA FIELD32(0x000000ff) 466#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
445#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00) 467#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
446#define RF_CSR_CFG_WRITE FIELD32(0x00010000) 468#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
447#define RF_CSR_CFG_BUSY FIELD32(0x00020000) 469#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
448 470
@@ -1132,8 +1154,8 @@
1132 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) 1154 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1133 * PROTECT_CTRL: Protection control frame type for CCK TX 1155 * PROTECT_CTRL: Protection control frame type for CCK TX
1134 * 0:none, 1:RTS/CTS, 2:CTS-to-self 1156 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1135 * PROTECT_NAV: TXOP protection type for CCK TX 1157 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1136 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect 1158 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1137 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow 1159 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1138 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow 1160 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1139 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow 1161 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
@@ -1145,7 +1167,8 @@
1145#define CCK_PROT_CFG 0x1364 1167#define CCK_PROT_CFG 0x1364
1146#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1168#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1147#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1169#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1148#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1170#define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1171#define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1149#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1172#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1150#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1173#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1151#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1174#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1160,7 +1183,8 @@
1160#define OFDM_PROT_CFG 0x1368 1183#define OFDM_PROT_CFG 0x1368
1161#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1184#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1162#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1185#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1163#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1186#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1187#define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1164#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1188#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1165#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1189#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1166#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1190#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1175,7 +1199,8 @@
1175#define MM20_PROT_CFG 0x136c 1199#define MM20_PROT_CFG 0x136c
1176#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1200#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1177#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1201#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1178#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1202#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1203#define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1179#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1204#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1180#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1205#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1181#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1206#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1190,7 +1215,8 @@
1190#define MM40_PROT_CFG 0x1370 1215#define MM40_PROT_CFG 0x1370
1191#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1216#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1192#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1217#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1193#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1218#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1219#define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1194#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1220#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1195#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1221#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1196#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1222#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1205,7 +1231,8 @@
1205#define GF20_PROT_CFG 0x1374 1231#define GF20_PROT_CFG 0x1374
1206#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1232#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1207#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1233#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1208#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1234#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1235#define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1209#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1236#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1210#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1237#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1211#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1238#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1220,7 +1247,8 @@
1220#define GF40_PROT_CFG 0x1378 1247#define GF40_PROT_CFG 0x1378
1221#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff) 1248#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1222#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000) 1249#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1223#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000) 1250#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1251#define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1224#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000) 1252#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1225#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000) 1253#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1226#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000) 1254#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
@@ -1697,11 +1725,14 @@ struct mac_iveiv_entry {
1697 */ 1725 */
1698 1726
1699/* 1727/*
1700 * BBP 1: TX Antenna & Power 1728 * BBP 1: TX Antenna & Power Control
1701 * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm, 1729 * POWER_CTRL:
1702 * 3 - increase tx power by 6dBm 1730 * 0 - normal,
1731 * 1 - drop tx power by 6dBm,
1732 * 2 - drop tx power by 12dBm,
1733 * 3 - increase tx power by 6dBm
1703 */ 1734 */
1704#define BBP1_TX_POWER FIELD8(0x07) 1735#define BBP1_TX_POWER_CTRL FIELD8(0x07)
1705#define BBP1_TX_ANTENNA FIELD8(0x18) 1736#define BBP1_TX_ANTENNA FIELD8(0x18)
1706 1737
1707/* 1738/*
@@ -1715,6 +1746,13 @@ struct mac_iveiv_entry {
1715 */ 1746 */
1716#define BBP4_TX_BF FIELD8(0x01) 1747#define BBP4_TX_BF FIELD8(0x01)
1717#define BBP4_BANDWIDTH FIELD8(0x18) 1748#define BBP4_BANDWIDTH FIELD8(0x18)
1749#define BBP4_MAC_IF_CTRL FIELD8(0x40)
1750
1751/*
1752 * BBP 109
1753 */
1754#define BBP109_TX0_POWER FIELD8(0x0f)
1755#define BBP109_TX1_POWER FIELD8(0xf0)
1718 1756
1719/* 1757/*
1720 * BBP 138: Unknown 1758 * BBP 138: Unknown
@@ -1725,6 +1763,11 @@ struct mac_iveiv_entry {
1725#define BBP138_TX_DAC2 FIELD8(0x40) 1763#define BBP138_TX_DAC2 FIELD8(0x40)
1726 1764
1727/* 1765/*
1766 * BBP 152: Rx Ant
1767 */
1768#define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1769
1770/*
1728 * RFCSR registers 1771 * RFCSR registers
1729 * The wordsize of the RFCSR is 8 bits. 1772 * The wordsize of the RFCSR is 8 bits.
1730 */ 1773 */
@@ -1733,12 +1776,18 @@ struct mac_iveiv_entry {
1733 * RFCSR 1: 1776 * RFCSR 1:
1734 */ 1777 */
1735#define RFCSR1_RF_BLOCK_EN FIELD8(0x01) 1778#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1779#define RFCSR1_PLL_PD FIELD8(0x02)
1736#define RFCSR1_RX0_PD FIELD8(0x04) 1780#define RFCSR1_RX0_PD FIELD8(0x04)
1737#define RFCSR1_TX0_PD FIELD8(0x08) 1781#define RFCSR1_TX0_PD FIELD8(0x08)
1738#define RFCSR1_RX1_PD FIELD8(0x10) 1782#define RFCSR1_RX1_PD FIELD8(0x10)
1739#define RFCSR1_TX1_PD FIELD8(0x20) 1783#define RFCSR1_TX1_PD FIELD8(0x20)
1740 1784
1741/* 1785/*
1786 * RFCSR 2:
1787 */
1788#define RFCSR2_RESCAL_EN FIELD8(0x80)
1789
1790/*
1742 * RFCSR 6: 1791 * RFCSR 6:
1743 */ 1792 */
1744#define RFCSR6_R1 FIELD8(0x03) 1793#define RFCSR6_R1 FIELD8(0x03)
@@ -1750,6 +1799,11 @@ struct mac_iveiv_entry {
1750#define RFCSR7_RF_TUNING FIELD8(0x01) 1799#define RFCSR7_RF_TUNING FIELD8(0x01)
1751 1800
1752/* 1801/*
1802 * RFCSR 11:
1803 */
1804#define RFCSR11_R FIELD8(0x03)
1805
1806/*
1753 * RFCSR 12: 1807 * RFCSR 12:
1754 */ 1808 */
1755#define RFCSR12_TX_POWER FIELD8(0x1f) 1809#define RFCSR12_TX_POWER FIELD8(0x1f)
@@ -1770,6 +1824,7 @@ struct mac_iveiv_entry {
1770#define RFCSR17_TXMIXER_GAIN FIELD8(0x07) 1824#define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1771#define RFCSR17_TX_LO1_EN FIELD8(0x08) 1825#define RFCSR17_TX_LO1_EN FIELD8(0x08)
1772#define RFCSR17_R FIELD8(0x20) 1826#define RFCSR17_R FIELD8(0x20)
1827#define RFCSR17_CODE FIELD8(0x7f)
1773 1828
1774/* 1829/*
1775 * RFCSR 20: 1830 * RFCSR 20:
@@ -1802,9 +1857,33 @@ struct mac_iveiv_entry {
1802/* 1857/*
1803 * RFCSR 30: 1858 * RFCSR 30:
1804 */ 1859 */
1860#define RFCSR30_TX_H20M FIELD8(0x02)
1861#define RFCSR30_RX_H20M FIELD8(0x04)
1862#define RFCSR30_RX_VCM FIELD8(0x18)
1805#define RFCSR30_RF_CALIBRATION FIELD8(0x80) 1863#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1806 1864
1807/* 1865/*
1866 * RFCSR 31:
1867 */
1868#define RFCSR31_RX_AGC_FC FIELD8(0x1f)
1869#define RFCSR31_RX_H20M FIELD8(0x20)
1870
1871/*
1872 * RFCSR 38:
1873 */
1874#define RFCSR38_RX_LO1_EN FIELD8(0x20)
1875
1876/*
1877 * RFCSR 39:
1878 */
1879#define RFCSR39_RX_LO2_EN FIELD8(0x80)
1880
1881/*
1882 * RFCSR 49:
1883 */
1884#define RFCSR49_TX FIELD8(0x3f)
1885
1886/*
1808 * RF registers 1887 * RF registers
1809 */ 1888 */
1810 1889
@@ -1837,6 +1916,11 @@ struct mac_iveiv_entry {
1837 */ 1916 */
1838 1917
1839/* 1918/*
1919 * Chip ID
1920 */
1921#define EEPROM_CHIP_ID 0x0000
1922
1923/*
1840 * EEPROM Version 1924 * EEPROM Version
1841 */ 1925 */
1842#define EEPROM_VERSION 0x0001 1926#define EEPROM_VERSION 0x0001
@@ -1989,23 +2073,26 @@ struct mac_iveiv_entry {
1989#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00) 2073#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1990 2074
1991/* 2075/*
1992 * EEPROM Maximum TX power values 2076 * EEPROM EIRP Maximum TX power values(unit: dbm)
1993 */ 2077 */
1994#define EEPROM_MAX_TX_POWER 0x0027 2078#define EEPROM_EIRP_MAX_TX_POWER 0x0027
1995#define EEPROM_MAX_TX_POWER_24GHZ FIELD16(0x00ff) 2079#define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
1996#define EEPROM_MAX_TX_POWER_5GHZ FIELD16(0xff00) 2080#define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
1997 2081
1998/* 2082/*
1999 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. 2083 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2000 * This is delta in 40MHZ. 2084 * This is delta in 40MHZ.
2001 * VALUE: Tx Power dalta value (MAX=4) 2085 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2002 * TYPE: 1: Plus the delta value, 0: minus the delta value 2086 * TYPE: 1: Plus the delta value, 0: minus the delta value
2003 * TXPOWER: Enable: 2087 * ENABLE: enable tx power compensation for 40BW
2004 */ 2088 */
2005#define EEPROM_TXPOWER_DELTA 0x0028 2089#define EEPROM_TXPOWER_DELTA 0x0028
2006#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f) 2090#define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2007#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040) 2091#define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2008#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080) 2092#define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2093#define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2094#define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2095#define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2009 2096
2010/* 2097/*
2011 * EEPROM TXPOWER 802.11BG 2098 * EEPROM TXPOWER 802.11BG
@@ -2058,6 +2145,7 @@ struct mac_iveiv_entry {
2058#define MCU_LED_LED_POLARITY 0x54 2145#define MCU_LED_LED_POLARITY 0x54
2059#define MCU_RADAR 0x60 2146#define MCU_RADAR 0x60
2060#define MCU_BOOT_SIGNAL 0x72 2147#define MCU_BOOT_SIGNAL 0x72
2148#define MCU_ANT_SELECT 0X73
2061#define MCU_BBP_SIGNAL 0x80 2149#define MCU_BBP_SIGNAL 0x80
2062#define MCU_POWER_SAVE 0x83 2150#define MCU_POWER_SAVE 0x83
2063 2151
@@ -2202,4 +2290,9 @@ struct mac_iveiv_entry {
2202#define TXPOWER_A_TO_DEV(__txpower) \ 2290#define TXPOWER_A_TO_DEV(__txpower) \
2203 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER) 2291 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2204 2292
2293/*
2294 * Board's maximun TX power limitation
2295 */
2296#define EIRP_MAX_TX_POWER_LIMIT 0x50
2297
2205#endif /* RT2800_H */ 2298#endif /* RT2800_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 54917a281398..2ee6cebb9b25 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -400,8 +400,15 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
400 if (rt2800_wait_csr_ready(rt2x00dev)) 400 if (rt2800_wait_csr_ready(rt2x00dev))
401 return -EBUSY; 401 return -EBUSY;
402 402
403 if (rt2x00_is_pci(rt2x00dev)) 403 if (rt2x00_is_pci(rt2x00dev)) {
404 if (rt2x00_rt(rt2x00dev, RT5390)) {
405 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
406 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
407 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
408 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
409 }
404 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 410 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
411 }
405 412
406 /* 413 /*
407 * Disable DMA, will be reenabled later when enabling 414 * Disable DMA, will be reenabled later when enabling
@@ -465,14 +472,15 @@ void rt2800_write_tx_data(struct queue_entry *entry,
465 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 472 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
466 rt2x00_set_field32(&word, TXWI_W0_AMPDU, 473 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
467 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags)); 474 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
468 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density); 475 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
469 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop); 476 txdesc->u.ht.mpdu_density);
470 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs); 477 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
478 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
471 rt2x00_set_field32(&word, TXWI_W0_BW, 479 rt2x00_set_field32(&word, TXWI_W0_BW,
472 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags)); 480 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, 481 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
474 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags)); 482 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc); 483 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
476 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); 484 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
477 rt2x00_desc_write(txwi, 0, word); 485 rt2x00_desc_write(txwi, 0, word);
478 486
@@ -481,7 +489,7 @@ void rt2800_write_tx_data(struct queue_entry *entry,
481 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); 489 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W1_NSEQ, 490 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
483 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); 491 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size); 492 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
485 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 493 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
486 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 494 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
487 txdesc->key_idx : 0xff); 495 txdesc->key_idx : 0xff);
@@ -674,7 +682,7 @@ void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
674 * confuse the rate control algortihm by providing clearly wrong 682 * confuse the rate control algortihm by providing clearly wrong
675 * data. 683 * data.
676 */ 684 */
677 if (aggr == 1 && ampdu == 0 && real_mcs != mcs) { 685 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
678 skbdesc->tx_rate_idx = real_mcs; 686 skbdesc->tx_rate_idx = real_mcs;
679 mcs = real_mcs; 687 mcs = real_mcs;
680 } 688 }
@@ -744,7 +752,7 @@ void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
744 if (pid >= QID_RX) 752 if (pid >= QID_RX)
745 continue; 753 continue;
746 754
747 queue = rt2x00queue_get_queue(rt2x00dev, pid); 755 queue = rt2x00queue_get_tx_queue(rt2x00dev, pid);
748 if (unlikely(!queue)) 756 if (unlikely(!queue))
749 continue; 757 continue;
750 758
@@ -773,13 +781,14 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 781 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
774 unsigned int beacon_base; 782 unsigned int beacon_base;
775 unsigned int padding_len; 783 unsigned int padding_len;
776 u32 reg; 784 u32 orig_reg, reg;
777 785
778 /* 786 /*
779 * Disable beaconing while we are reloading the beacon data, 787 * Disable beaconing while we are reloading the beacon data,
780 * otherwise we might be sending out invalid data. 788 * otherwise we might be sending out invalid data.
781 */ 789 */
782 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 790 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
791 orig_reg = reg;
783 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 792 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
784 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 793 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
785 794
@@ -810,7 +819,14 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
810 * Write entire beacon with TXWI and padding to register. 819 * Write entire beacon with TXWI and padding to register.
811 */ 820 */
812 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 821 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
813 skb_pad(entry->skb, padding_len); 822 if (padding_len && skb_pad(entry->skb, padding_len)) {
823 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
824 /* skb freed by skb_pad() on failure */
825 entry->skb = NULL;
826 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
827 return;
828 }
829
814 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 830 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
815 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 831 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
816 entry->skb->len + padding_len); 832 entry->skb->len + padding_len);
@@ -818,8 +834,6 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
818 /* 834 /*
819 * Enable beaconing again. 835 * Enable beaconing again.
820 */ 836 */
821 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
822 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
823 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 837 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
824 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 838 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
825 839
@@ -831,8 +845,8 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
831} 845}
832EXPORT_SYMBOL_GPL(rt2800_write_beacon); 846EXPORT_SYMBOL_GPL(rt2800_write_beacon);
833 847
834static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev, 848static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
835 unsigned int beacon_base) 849 unsigned int beacon_base)
836{ 850{
837 int i; 851 int i;
838 852
@@ -845,6 +859,33 @@ static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
845 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 859 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
846} 860}
847 861
862void rt2800_clear_beacon(struct queue_entry *entry)
863{
864 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
865 u32 reg;
866
867 /*
868 * Disable beaconing while we are reloading the beacon data,
869 * otherwise we might be sending out invalid data.
870 */
871 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
872 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
873 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
874
875 /*
876 * Clear beacon.
877 */
878 rt2800_clear_beacon_register(rt2x00dev,
879 HW_BEACON_OFFSET(entry->entry_idx));
880
881 /*
882 * Enabled beaconing again.
883 */
884 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
885 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
886}
887EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
888
848#ifdef CONFIG_RT2X00_LIB_DEBUGFS 889#ifdef CONFIG_RT2X00_LIB_DEBUGFS
849const struct rt2x00debug rt2800_rt2x00debug = { 890const struct rt2x00debug rt2800_rt2x00debug = {
850 .owner = THIS_MODULE, 891 .owner = THIS_MODULE,
@@ -1005,7 +1046,7 @@ static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1005 1046
1006 memset(&wcid_entry, 0, sizeof(wcid_entry)); 1047 memset(&wcid_entry, 0, sizeof(wcid_entry));
1007 if (crypto->cmd == SET_KEY) 1048 if (crypto->cmd == SET_KEY)
1008 memcpy(&wcid_entry, crypto->address, ETH_ALEN); 1049 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
1009 rt2800_register_multiwrite(rt2x00dev, offset, 1050 rt2800_register_multiwrite(rt2x00dev, offset,
1010 &wcid_entry, sizeof(wcid_entry)); 1051 &wcid_entry, sizeof(wcid_entry));
1011} 1052}
@@ -1060,27 +1101,44 @@ int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1060} 1101}
1061EXPORT_SYMBOL_GPL(rt2800_config_shared_key); 1102EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1062 1103
1104static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1105{
1106 int idx;
1107 u32 offset, reg;
1108
1109 /*
1110 * Search for the first free pairwise key entry and return the
1111 * corresponding index.
1112 *
1113 * Make sure the WCID starts _after_ the last possible shared key
1114 * entry (>32).
1115 *
1116 * Since parts of the pairwise key table might be shared with
1117 * the beacon frame buffers 6 & 7 we should only write into the
1118 * first 222 entries.
1119 */
1120 for (idx = 33; idx <= 222; idx++) {
1121 offset = MAC_WCID_ATTR_ENTRY(idx);
1122 rt2800_register_read(rt2x00dev, offset, &reg);
1123 if (!reg)
1124 return idx;
1125 }
1126 return -1;
1127}
1128
1063int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev, 1129int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1064 struct rt2x00lib_crypto *crypto, 1130 struct rt2x00lib_crypto *crypto,
1065 struct ieee80211_key_conf *key) 1131 struct ieee80211_key_conf *key)
1066{ 1132{
1067 struct hw_key_entry key_entry; 1133 struct hw_key_entry key_entry;
1068 u32 offset; 1134 u32 offset;
1135 int idx;
1069 1136
1070 if (crypto->cmd == SET_KEY) { 1137 if (crypto->cmd == SET_KEY) {
1071 /* 1138 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1072 * 1 pairwise key is possible per AID, this means that the AID 1139 if (idx < 0)
1073 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1074 * last possible shared key entry.
1075 *
1076 * Since parts of the pairwise key table might be shared with
1077 * the beacon frame buffers 6 & 7 we should only write into the
1078 * first 222 entries.
1079 */
1080 if (crypto->aid > (222 - 32))
1081 return -ENOSPC; 1140 return -ENOSPC;
1082 1141 key->hw_key_idx = idx;
1083 key->hw_key_idx = 32 + crypto->aid;
1084 1142
1085 memcpy(key_entry.key, crypto->key, 1143 memcpy(key_entry.key, crypto->key,
1086 sizeof(key_entry.key)); 1144 sizeof(key_entry.key));
@@ -1155,29 +1213,11 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1155 1213
1156 if (flags & CONFIG_UPDATE_TYPE) { 1214 if (flags & CONFIG_UPDATE_TYPE) {
1157 /* 1215 /*
1158 * Clear current synchronisation setup.
1159 */
1160 rt2800_clear_beacon(rt2x00dev,
1161 HW_BEACON_OFFSET(intf->beacon->entry_idx));
1162 /*
1163 * Enable synchronisation. 1216 * Enable synchronisation.
1164 */ 1217 */
1165 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 1218 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1166 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1167 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync); 1219 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1168 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE,
1169 (conf->sync == TSF_SYNC_ADHOC ||
1170 conf->sync == TSF_SYNC_AP_NONE));
1171 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1220 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1172
1173 /*
1174 * Enable pre tbtt interrupt for beaconing modes
1175 */
1176 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
1177 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER,
1178 (conf->sync == TSF_SYNC_AP_NONE));
1179 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1180
1181 } 1221 }
1182 1222
1183 if (flags & CONFIG_UPDATE_MAC) { 1223 if (flags & CONFIG_UPDATE_MAC) {
@@ -1361,10 +1401,32 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1361} 1401}
1362EXPORT_SYMBOL_GPL(rt2800_config_erp); 1402EXPORT_SYMBOL_GPL(rt2800_config_erp);
1363 1403
1404static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1405 enum antenna ant)
1406{
1407 u32 reg;
1408 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1409 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1410
1411 if (rt2x00_is_pci(rt2x00dev)) {
1412 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1413 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1414 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1415 } else if (rt2x00_is_usb(rt2x00dev))
1416 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1417 eesk_pin, 0);
1418
1419 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1420 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1421 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1422 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1423}
1424
1364void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) 1425void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1365{ 1426{
1366 u8 r1; 1427 u8 r1;
1367 u8 r3; 1428 u8 r3;
1429 u16 eeprom;
1368 1430
1369 rt2800_bbp_read(rt2x00dev, 1, &r1); 1431 rt2800_bbp_read(rt2x00dev, 1, &r1);
1370 rt2800_bbp_read(rt2x00dev, 3, &r3); 1432 rt2800_bbp_read(rt2x00dev, 3, &r3);
@@ -1372,7 +1434,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1372 /* 1434 /*
1373 * Configure the TX antenna. 1435 * Configure the TX antenna.
1374 */ 1436 */
1375 switch ((int)ant->tx) { 1437 switch (ant->tx_chain_num) {
1376 case 1: 1438 case 1:
1377 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); 1439 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1378 break; 1440 break;
@@ -1387,8 +1449,18 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1387 /* 1449 /*
1388 * Configure the RX antenna. 1450 * Configure the RX antenna.
1389 */ 1451 */
1390 switch ((int)ant->rx) { 1452 switch (ant->rx_chain_num) {
1391 case 1: 1453 case 1:
1454 if (rt2x00_rt(rt2x00dev, RT3070) ||
1455 rt2x00_rt(rt2x00dev, RT3090) ||
1456 rt2x00_rt(rt2x00dev, RT3390)) {
1457 rt2x00_eeprom_read(rt2x00dev,
1458 EEPROM_NIC_CONF1, &eeprom);
1459 if (rt2x00_get_field16(eeprom,
1460 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1461 rt2800_set_ant_diversity(rt2x00dev,
1462 rt2x00dev->default_ant.rx);
1463 }
1392 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); 1464 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1393 break; 1465 break;
1394 case 2: 1466 case 2:
@@ -1434,13 +1506,13 @@ static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1434{ 1506{
1435 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 1507 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1436 1508
1437 if (rt2x00dev->default_ant.tx == 1) 1509 if (rt2x00dev->default_ant.tx_chain_num == 1)
1438 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); 1510 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1439 1511
1440 if (rt2x00dev->default_ant.rx == 1) { 1512 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1441 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); 1513 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1442 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1514 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1443 } else if (rt2x00dev->default_ant.rx == 2) 1515 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1444 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); 1516 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1445 1517
1446 if (rf->channel > 14) { 1518 if (rf->channel > 14) {
@@ -1526,6 +1598,105 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1526 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); 1598 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1527} 1599}
1528 1600
1601
1602#define RT5390_POWER_BOUND 0x27
1603#define RT5390_FREQ_OFFSET_BOUND 0x5f
1604
1605static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1606 struct ieee80211_conf *conf,
1607 struct rf_channel *rf,
1608 struct channel_info *info)
1609{
1610 u8 rfcsr;
1611 u16 eeprom;
1612
1613 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1614 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1615 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1616 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1617 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1618
1619 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1620 if (info->default_power1 > RT5390_POWER_BOUND)
1621 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1622 else
1623 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1624 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1625
1626 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1627 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1628 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1629 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1630 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1631 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1632
1633 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1634 if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1635 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1636 RT5390_FREQ_OFFSET_BOUND);
1637 else
1638 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1639 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1640
1641 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1642 if (rf->channel <= 14) {
1643 int idx = rf->channel-1;
1644
1645 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1646 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1647 /* r55/r59 value array of channel 1~14 */
1648 static const char r55_bt_rev[] = {0x83, 0x83,
1649 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1650 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1651 static const char r59_bt_rev[] = {0x0e, 0x0e,
1652 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1653 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1654
1655 rt2800_rfcsr_write(rt2x00dev, 55,
1656 r55_bt_rev[idx]);
1657 rt2800_rfcsr_write(rt2x00dev, 59,
1658 r59_bt_rev[idx]);
1659 } else {
1660 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1661 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1662 0x88, 0x88, 0x86, 0x85, 0x84};
1663
1664 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1665 }
1666 } else {
1667 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1668 static const char r55_nonbt_rev[] = {0x23, 0x23,
1669 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1670 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1671 static const char r59_nonbt_rev[] = {0x07, 0x07,
1672 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1673 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1674
1675 rt2800_rfcsr_write(rt2x00dev, 55,
1676 r55_nonbt_rev[idx]);
1677 rt2800_rfcsr_write(rt2x00dev, 59,
1678 r59_nonbt_rev[idx]);
1679 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1680 static const char r59_non_bt[] = {0x8f, 0x8f,
1681 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1682 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1683
1684 rt2800_rfcsr_write(rt2x00dev, 59,
1685 r59_non_bt[idx]);
1686 }
1687 }
1688 }
1689
1690 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1691 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1692 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1693 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1694
1695 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1696 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1697 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1698}
1699
1529static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 1700static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1530 struct ieee80211_conf *conf, 1701 struct ieee80211_conf *conf,
1531 struct rf_channel *rf, 1702 struct rf_channel *rf,
@@ -1550,6 +1721,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1550 rt2x00_rf(rt2x00dev, RF3052) || 1721 rt2x00_rf(rt2x00dev, RF3052) ||
1551 rt2x00_rf(rt2x00dev, RF3320)) 1722 rt2x00_rf(rt2x00dev, RF3320))
1552 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); 1723 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1724 else if (rt2x00_rf(rt2x00dev, RF5390))
1725 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1553 else 1726 else
1554 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 1727 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1555 1728
@@ -1562,12 +1735,15 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1562 rt2800_bbp_write(rt2x00dev, 86, 0); 1735 rt2800_bbp_write(rt2x00dev, 86, 0);
1563 1736
1564 if (rf->channel <= 14) { 1737 if (rf->channel <= 14) {
1565 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) { 1738 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1566 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1739 if (test_bit(CONFIG_EXTERNAL_LNA_BG,
1567 rt2800_bbp_write(rt2x00dev, 75, 0x46); 1740 &rt2x00dev->flags)) {
1568 } else { 1741 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1569 rt2800_bbp_write(rt2x00dev, 82, 0x84); 1742 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1570 rt2800_bbp_write(rt2x00dev, 75, 0x50); 1743 } else {
1744 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1745 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1746 }
1571 } 1747 }
1572 } else { 1748 } else {
1573 rt2800_bbp_write(rt2x00dev, 82, 0xf2); 1749 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
@@ -1587,13 +1763,13 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1587 tx_pin = 0; 1763 tx_pin = 0;
1588 1764
1589 /* Turn on unused PA or LNA when not using 1T or 1R */ 1765 /* Turn on unused PA or LNA when not using 1T or 1R */
1590 if (rt2x00dev->default_ant.tx != 1) { 1766 if (rt2x00dev->default_ant.tx_chain_num == 2) {
1591 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); 1767 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1592 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); 1768 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1593 } 1769 }
1594 1770
1595 /* Turn on unused PA or LNA when not using 1T or 1R */ 1771 /* Turn on unused PA or LNA when not using 1T or 1R */
1596 if (rt2x00dev->default_ant.rx != 1) { 1772 if (rt2x00dev->default_ant.rx_chain_num == 2) {
1597 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); 1773 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1598 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); 1774 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1599 } 1775 }
@@ -1637,30 +1813,116 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1637 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg); 1813 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1638} 1814}
1639 1815
1816static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1817 enum ieee80211_band band)
1818{
1819 u16 eeprom;
1820 u8 comp_en;
1821 u8 comp_type;
1822 int comp_value;
1823
1824 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1825
1826 if (eeprom == 0xffff)
1827 return 0;
1828
1829 if (band == IEEE80211_BAND_2GHZ) {
1830 comp_en = rt2x00_get_field16(eeprom,
1831 EEPROM_TXPOWER_DELTA_ENABLE_2G);
1832 if (comp_en) {
1833 comp_type = rt2x00_get_field16(eeprom,
1834 EEPROM_TXPOWER_DELTA_TYPE_2G);
1835 comp_value = rt2x00_get_field16(eeprom,
1836 EEPROM_TXPOWER_DELTA_VALUE_2G);
1837 if (!comp_type)
1838 comp_value = -comp_value;
1839 }
1840 } else {
1841 comp_en = rt2x00_get_field16(eeprom,
1842 EEPROM_TXPOWER_DELTA_ENABLE_5G);
1843 if (comp_en) {
1844 comp_type = rt2x00_get_field16(eeprom,
1845 EEPROM_TXPOWER_DELTA_TYPE_5G);
1846 comp_value = rt2x00_get_field16(eeprom,
1847 EEPROM_TXPOWER_DELTA_VALUE_5G);
1848 if (!comp_type)
1849 comp_value = -comp_value;
1850 }
1851 }
1852
1853 return comp_value;
1854}
1855
1856static u8 rt2800_compesate_txpower(struct rt2x00_dev *rt2x00dev,
1857 int is_rate_b,
1858 enum ieee80211_band band,
1859 int power_level,
1860 u8 txpower)
1861{
1862 u32 reg;
1863 u16 eeprom;
1864 u8 criterion;
1865 u8 eirp_txpower;
1866 u8 eirp_txpower_criterion;
1867 u8 reg_limit;
1868 int bw_comp = 0;
1869
1870 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
1871 return txpower;
1872
1873 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1874 bw_comp = rt2800_get_txpower_bw_comp(rt2x00dev, band);
1875
1876 if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
1877 /*
1878 * Check if eirp txpower exceed txpower_limit.
1879 * We use OFDM 6M as criterion and its eirp txpower
1880 * is stored at EEPROM_EIRP_MAX_TX_POWER.
1881 * .11b data rate need add additional 4dbm
1882 * when calculating eirp txpower.
1883 */
1884 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1885 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
1886
1887 rt2x00_eeprom_read(rt2x00dev,
1888 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
1889
1890 if (band == IEEE80211_BAND_2GHZ)
1891 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1892 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
1893 else
1894 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
1895 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
1896
1897 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
1898 (is_rate_b ? 4 : 0) + bw_comp;
1899
1900 reg_limit = (eirp_txpower > power_level) ?
1901 (eirp_txpower - power_level) : 0;
1902 } else
1903 reg_limit = 0;
1904
1905 return txpower + bw_comp - reg_limit;
1906}
1907
1640static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev, 1908static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1641 const int max_txpower) 1909 struct ieee80211_conf *conf)
1642{ 1910{
1643 u8 txpower; 1911 u8 txpower;
1644 u8 max_value = (u8)max_txpower;
1645 u16 eeprom; 1912 u16 eeprom;
1646 int i; 1913 int i, is_rate_b;
1647 u32 reg; 1914 u32 reg;
1648 u8 r1; 1915 u8 r1;
1649 u32 offset; 1916 u32 offset;
1917 enum ieee80211_band band = conf->channel->band;
1918 int power_level = conf->power_level;
1650 1919
1651 /* 1920 /*
1652 * set to normal tx power mode: +/- 0dBm 1921 * set to normal bbp tx power control mode: +/- 0dBm
1653 */ 1922 */
1654 rt2800_bbp_read(rt2x00dev, 1, &r1); 1923 rt2800_bbp_read(rt2x00dev, 1, &r1);
1655 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0); 1924 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
1656 rt2800_bbp_write(rt2x00dev, 1, r1); 1925 rt2800_bbp_write(rt2x00dev, 1, r1);
1657
1658 /*
1659 * The eeprom contains the tx power values for each rate. These
1660 * values map to 100% tx power. Each 16bit word contains four tx
1661 * power values and the order is the same as used in the TX_PWR_CFG
1662 * registers.
1663 */
1664 offset = TX_PWR_CFG_0; 1926 offset = TX_PWR_CFG_0;
1665 1927
1666 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) { 1928 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
@@ -1674,73 +1936,99 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1674 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i, 1936 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1675 &eeprom); 1937 &eeprom);
1676 1938
1677 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS, 1939 is_rate_b = i ? 0 : 1;
1940 /*
1941 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1678 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12, 1942 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1679 * TX_PWR_CFG_4: unknown */ 1943 * TX_PWR_CFG_4: unknown
1944 */
1680 txpower = rt2x00_get_field16(eeprom, 1945 txpower = rt2x00_get_field16(eeprom,
1681 EEPROM_TXPOWER_BYRATE_RATE0); 1946 EEPROM_TXPOWER_BYRATE_RATE0);
1682 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, 1947 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1683 min(txpower, max_value)); 1948 power_level, txpower);
1949 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
1684 1950
1685 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS, 1951 /*
1952 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1686 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13, 1953 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1687 * TX_PWR_CFG_4: unknown */ 1954 * TX_PWR_CFG_4: unknown
1955 */
1688 txpower = rt2x00_get_field16(eeprom, 1956 txpower = rt2x00_get_field16(eeprom,
1689 EEPROM_TXPOWER_BYRATE_RATE1); 1957 EEPROM_TXPOWER_BYRATE_RATE1);
1690 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, 1958 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1691 min(txpower, max_value)); 1959 power_level, txpower);
1960 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
1692 1961
1693 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS, 1962 /*
1963 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
1694 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14, 1964 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1695 * TX_PWR_CFG_4: unknown */ 1965 * TX_PWR_CFG_4: unknown
1966 */
1696 txpower = rt2x00_get_field16(eeprom, 1967 txpower = rt2x00_get_field16(eeprom,
1697 EEPROM_TXPOWER_BYRATE_RATE2); 1968 EEPROM_TXPOWER_BYRATE_RATE2);
1698 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, 1969 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1699 min(txpower, max_value)); 1970 power_level, txpower);
1971 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
1700 1972
1701 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS, 1973 /*
1974 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1702 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15, 1975 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1703 * TX_PWR_CFG_4: unknown */ 1976 * TX_PWR_CFG_4: unknown
1977 */
1704 txpower = rt2x00_get_field16(eeprom, 1978 txpower = rt2x00_get_field16(eeprom,
1705 EEPROM_TXPOWER_BYRATE_RATE3); 1979 EEPROM_TXPOWER_BYRATE_RATE3);
1706 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, 1980 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1707 min(txpower, max_value)); 1981 power_level, txpower);
1982 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
1708 1983
1709 /* read the next four txpower values */ 1984 /* read the next four txpower values */
1710 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1, 1985 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1711 &eeprom); 1986 &eeprom);
1712 1987
1713 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0, 1988 is_rate_b = 0;
1989 /*
1990 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1714 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown, 1991 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1715 * TX_PWR_CFG_4: unknown */ 1992 * TX_PWR_CFG_4: unknown
1993 */
1716 txpower = rt2x00_get_field16(eeprom, 1994 txpower = rt2x00_get_field16(eeprom,
1717 EEPROM_TXPOWER_BYRATE_RATE0); 1995 EEPROM_TXPOWER_BYRATE_RATE0);
1718 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, 1996 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1719 min(txpower, max_value)); 1997 power_level, txpower);
1998 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
1720 1999
1721 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1, 2000 /*
2001 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1722 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown, 2002 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1723 * TX_PWR_CFG_4: unknown */ 2003 * TX_PWR_CFG_4: unknown
2004 */
1724 txpower = rt2x00_get_field16(eeprom, 2005 txpower = rt2x00_get_field16(eeprom,
1725 EEPROM_TXPOWER_BYRATE_RATE1); 2006 EEPROM_TXPOWER_BYRATE_RATE1);
1726 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, 2007 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1727 min(txpower, max_value)); 2008 power_level, txpower);
2009 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
1728 2010
1729 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2, 2011 /*
2012 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1730 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown, 2013 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1731 * TX_PWR_CFG_4: unknown */ 2014 * TX_PWR_CFG_4: unknown
2015 */
1732 txpower = rt2x00_get_field16(eeprom, 2016 txpower = rt2x00_get_field16(eeprom,
1733 EEPROM_TXPOWER_BYRATE_RATE2); 2017 EEPROM_TXPOWER_BYRATE_RATE2);
1734 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, 2018 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1735 min(txpower, max_value)); 2019 power_level, txpower);
2020 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
1736 2021
1737 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3, 2022 /*
2023 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1738 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown, 2024 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1739 * TX_PWR_CFG_4: unknown */ 2025 * TX_PWR_CFG_4: unknown
2026 */
1740 txpower = rt2x00_get_field16(eeprom, 2027 txpower = rt2x00_get_field16(eeprom,
1741 EEPROM_TXPOWER_BYRATE_RATE3); 2028 EEPROM_TXPOWER_BYRATE_RATE3);
1742 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, 2029 txpower = rt2800_compesate_txpower(rt2x00dev, is_rate_b, band,
1743 min(txpower, max_value)); 2030 power_level, txpower);
2031 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
1744 2032
1745 rt2800_register_write(rt2x00dev, offset, reg); 2033 rt2800_register_write(rt2x00dev, offset, reg);
1746 2034
@@ -1799,11 +2087,13 @@ void rt2800_config(struct rt2x00_dev *rt2x00dev,
1799 /* Always recalculate LNA gain before changing configuration */ 2087 /* Always recalculate LNA gain before changing configuration */
1800 rt2800_config_lna_gain(rt2x00dev, libconf); 2088 rt2800_config_lna_gain(rt2x00dev, libconf);
1801 2089
1802 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) 2090 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
1803 rt2800_config_channel(rt2x00dev, libconf->conf, 2091 rt2800_config_channel(rt2x00dev, libconf->conf,
1804 &libconf->rf, &libconf->channel); 2092 &libconf->rf, &libconf->channel);
2093 rt2800_config_txpower(rt2x00dev, libconf->conf);
2094 }
1805 if (flags & IEEE80211_CONF_CHANGE_POWER) 2095 if (flags & IEEE80211_CONF_CHANGE_POWER)
1806 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level); 2096 rt2800_config_txpower(rt2x00dev, libconf->conf);
1807 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 2097 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1808 rt2800_config_retry_limit(rt2x00dev, libconf); 2098 rt2800_config_retry_limit(rt2x00dev, libconf);
1809 if (flags & IEEE80211_CONF_CHANGE_PS) 2099 if (flags & IEEE80211_CONF_CHANGE_PS)
@@ -1832,7 +2122,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1832 if (rt2x00_rt(rt2x00dev, RT3070) || 2122 if (rt2x00_rt(rt2x00dev, RT3070) ||
1833 rt2x00_rt(rt2x00dev, RT3071) || 2123 rt2x00_rt(rt2x00dev, RT3071) ||
1834 rt2x00_rt(rt2x00dev, RT3090) || 2124 rt2x00_rt(rt2x00dev, RT3090) ||
1835 rt2x00_rt(rt2x00dev, RT3390)) 2125 rt2x00_rt(rt2x00dev, RT3390) ||
2126 rt2x00_rt(rt2x00dev, RT5390))
1836 return 0x1c + (2 * rt2x00dev->lna_gain); 2127 return 0x1c + (2 * rt2x00dev->lna_gain);
1837 else 2128 else
1838 return 0x2e + rt2x00dev->lna_gain; 2129 return 0x2e + rt2x00dev->lna_gain;
@@ -1964,6 +2255,10 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1964 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 2255 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1965 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 2256 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1966 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f); 2257 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
2258 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2259 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2260 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2261 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1967 } else { 2262 } else {
1968 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 2263 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1969 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 2264 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -2032,7 +2327,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2032 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 2327 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2033 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3); 2328 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2034 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0); 2329 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2035 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1); 2330 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2036 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2331 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2037 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2332 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2038 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2333 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2045,7 +2340,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2045 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 2340 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2046 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3); 2341 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2047 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0); 2342 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2048 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1); 2343 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2049 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2344 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2050 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2345 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2051 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2346 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2058,7 +2353,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2058 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 2353 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2059 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 2354 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2060 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0); 2355 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2061 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1); 2356 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2062 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2357 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2063 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2358 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2064 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2359 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2071,7 +2366,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2071 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 2366 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2072 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 2367 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2073 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0); 2368 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2074 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1); 2369 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2075 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2370 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2076 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2371 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2077 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2372 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2084,7 +2379,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2084 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 2379 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2085 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 2380 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2086 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0); 2381 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2087 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1); 2382 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2088 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2383 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2089 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2384 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2090 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2385 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2097,7 +2392,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2097 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 2392 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2098 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 2393 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2099 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0); 2394 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2100 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1); 2395 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2101 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 2396 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2102 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 2397 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2103 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 2398 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
@@ -2180,26 +2475,30 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2180 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i), 2475 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2181 wcid, sizeof(wcid)); 2476 wcid, sizeof(wcid));
2182 2477
2183 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1); 2478 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
2184 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0); 2479 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2185 } 2480 }
2186 2481
2187 /* 2482 /*
2188 * Clear all beacons 2483 * Clear all beacons
2189 */ 2484 */
2190 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0); 2485 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2191 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1); 2486 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2192 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2); 2487 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2193 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3); 2488 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2194 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4); 2489 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2195 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5); 2490 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2196 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6); 2491 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2197 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7); 2492 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2198 2493
2199 if (rt2x00_is_usb(rt2x00dev)) { 2494 if (rt2x00_is_usb(rt2x00dev)) {
2200 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg); 2495 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2201 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30); 2496 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2202 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); 2497 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2498 } else if (rt2x00_is_pcie(rt2x00dev)) {
2499 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2500 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2501 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2203 } 2502 }
2204 2503
2205 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg); 2504 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
@@ -2335,15 +2634,31 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2335 rt2800_wait_bbp_ready(rt2x00dev))) 2634 rt2800_wait_bbp_ready(rt2x00dev)))
2336 return -EACCES; 2635 return -EACCES;
2337 2636
2338 if (rt2800_is_305x_soc(rt2x00dev)) 2637 if (rt2x00_rt(rt2x00dev, RT5390)) {
2638 rt2800_bbp_read(rt2x00dev, 4, &value);
2639 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2640 rt2800_bbp_write(rt2x00dev, 4, value);
2641 }
2642
2643 if (rt2800_is_305x_soc(rt2x00dev) ||
2644 rt2x00_rt(rt2x00dev, RT5390))
2339 rt2800_bbp_write(rt2x00dev, 31, 0x08); 2645 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2340 2646
2341 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 2647 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2342 rt2800_bbp_write(rt2x00dev, 66, 0x38); 2648 rt2800_bbp_write(rt2x00dev, 66, 0x38);
2343 2649
2650 if (rt2x00_rt(rt2x00dev, RT5390))
2651 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2652
2344 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) { 2653 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2345 rt2800_bbp_write(rt2x00dev, 69, 0x16); 2654 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2346 rt2800_bbp_write(rt2x00dev, 73, 0x12); 2655 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2656 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2657 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2658 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2659 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2660 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2661 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2347 } else { 2662 } else {
2348 rt2800_bbp_write(rt2x00dev, 69, 0x12); 2663 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2349 rt2800_bbp_write(rt2x00dev, 73, 0x10); 2664 rt2800_bbp_write(rt2x00dev, 73, 0x10);
@@ -2354,7 +2669,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2354 if (rt2x00_rt(rt2x00dev, RT3070) || 2669 if (rt2x00_rt(rt2x00dev, RT3070) ||
2355 rt2x00_rt(rt2x00dev, RT3071) || 2670 rt2x00_rt(rt2x00dev, RT3071) ||
2356 rt2x00_rt(rt2x00dev, RT3090) || 2671 rt2x00_rt(rt2x00dev, RT3090) ||
2357 rt2x00_rt(rt2x00dev, RT3390)) { 2672 rt2x00_rt(rt2x00dev, RT3390) ||
2673 rt2x00_rt(rt2x00dev, RT5390)) {
2358 rt2800_bbp_write(rt2x00dev, 79, 0x13); 2674 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2359 rt2800_bbp_write(rt2x00dev, 80, 0x05); 2675 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2360 rt2800_bbp_write(rt2x00dev, 81, 0x33); 2676 rt2800_bbp_write(rt2x00dev, 81, 0x33);
@@ -2366,35 +2682,62 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2366 } 2682 }
2367 2683
2368 rt2800_bbp_write(rt2x00dev, 82, 0x62); 2684 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2369 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 2685 if (rt2x00_rt(rt2x00dev, RT5390))
2686 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2687 else
2688 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2370 2689
2371 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D)) 2690 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2372 rt2800_bbp_write(rt2x00dev, 84, 0x19); 2691 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2692 else if (rt2x00_rt(rt2x00dev, RT5390))
2693 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2373 else 2694 else
2374 rt2800_bbp_write(rt2x00dev, 84, 0x99); 2695 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2375 2696
2376 rt2800_bbp_write(rt2x00dev, 86, 0x00); 2697 if (rt2x00_rt(rt2x00dev, RT5390))
2698 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2699 else
2700 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2701
2377 rt2800_bbp_write(rt2x00dev, 91, 0x04); 2702 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2378 rt2800_bbp_write(rt2x00dev, 92, 0x00); 2703
2704 if (rt2x00_rt(rt2x00dev, RT5390))
2705 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2706 else
2707 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2379 2708
2380 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) || 2709 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2381 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || 2710 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2382 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 2711 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2383 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 2712 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2713 rt2x00_rt(rt2x00dev, RT5390) ||
2384 rt2800_is_305x_soc(rt2x00dev)) 2714 rt2800_is_305x_soc(rt2x00dev))
2385 rt2800_bbp_write(rt2x00dev, 103, 0xc0); 2715 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2386 else 2716 else
2387 rt2800_bbp_write(rt2x00dev, 103, 0x00); 2717 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2388 2718
2719 if (rt2x00_rt(rt2x00dev, RT5390))
2720 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2721
2389 if (rt2800_is_305x_soc(rt2x00dev)) 2722 if (rt2800_is_305x_soc(rt2x00dev))
2390 rt2800_bbp_write(rt2x00dev, 105, 0x01); 2723 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2724 else if (rt2x00_rt(rt2x00dev, RT5390))
2725 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2391 else 2726 else
2392 rt2800_bbp_write(rt2x00dev, 105, 0x05); 2727 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2393 rt2800_bbp_write(rt2x00dev, 106, 0x35); 2728
2729 if (rt2x00_rt(rt2x00dev, RT5390))
2730 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2731 else
2732 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2733
2734 if (rt2x00_rt(rt2x00dev, RT5390))
2735 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2394 2736
2395 if (rt2x00_rt(rt2x00dev, RT3071) || 2737 if (rt2x00_rt(rt2x00dev, RT3071) ||
2396 rt2x00_rt(rt2x00dev, RT3090) || 2738 rt2x00_rt(rt2x00dev, RT3090) ||
2397 rt2x00_rt(rt2x00dev, RT3390)) { 2739 rt2x00_rt(rt2x00dev, RT3390) ||
2740 rt2x00_rt(rt2x00dev, RT5390)) {
2398 rt2800_bbp_read(rt2x00dev, 138, &value); 2741 rt2800_bbp_read(rt2x00dev, 138, &value);
2399 2742
2400 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 2743 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
@@ -2406,6 +2749,42 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2406 rt2800_bbp_write(rt2x00dev, 138, value); 2749 rt2800_bbp_write(rt2x00dev, 138, value);
2407 } 2750 }
2408 2751
2752 if (rt2x00_rt(rt2x00dev, RT5390)) {
2753 int ant, div_mode;
2754
2755 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2756 div_mode = rt2x00_get_field16(eeprom,
2757 EEPROM_NIC_CONF1_ANT_DIVERSITY);
2758 ant = (div_mode == 3) ? 1 : 0;
2759
2760 /* check if this is a Bluetooth combo card */
2761 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2762 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2763 u32 reg;
2764
2765 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2766 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2767 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2768 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2769 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2770 if (ant == 0)
2771 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2772 else if (ant == 1)
2773 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2774 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2775 }
2776
2777 rt2800_bbp_read(rt2x00dev, 152, &value);
2778 if (ant == 0)
2779 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2780 else
2781 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2782 rt2800_bbp_write(rt2x00dev, 152, value);
2783
2784 /* Init frequency calibration */
2785 rt2800_bbp_write(rt2x00dev, 142, 1);
2786 rt2800_bbp_write(rt2x00dev, 143, 57);
2787 }
2409 2788
2410 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 2789 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2411 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 2790 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
@@ -2436,6 +2815,10 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2436 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40); 2815 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2437 rt2800_bbp_write(rt2x00dev, 4, bbp); 2816 rt2800_bbp_write(rt2x00dev, 4, bbp);
2438 2817
2818 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2819 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2820 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2821
2439 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 2822 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2440 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1); 2823 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2441 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 2824 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
@@ -2491,18 +2874,28 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2491 !rt2x00_rt(rt2x00dev, RT3071) && 2874 !rt2x00_rt(rt2x00dev, RT3071) &&
2492 !rt2x00_rt(rt2x00dev, RT3090) && 2875 !rt2x00_rt(rt2x00dev, RT3090) &&
2493 !rt2x00_rt(rt2x00dev, RT3390) && 2876 !rt2x00_rt(rt2x00dev, RT3390) &&
2877 !rt2x00_rt(rt2x00dev, RT5390) &&
2494 !rt2800_is_305x_soc(rt2x00dev)) 2878 !rt2800_is_305x_soc(rt2x00dev))
2495 return 0; 2879 return 0;
2496 2880
2497 /* 2881 /*
2498 * Init RF calibration. 2882 * Init RF calibration.
2499 */ 2883 */
2500 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); 2884 if (rt2x00_rt(rt2x00dev, RT5390)) {
2501 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); 2885 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
2502 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2886 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
2503 msleep(1); 2887 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2504 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 2888 msleep(1);
2505 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 2889 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
2890 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
2891 } else {
2892 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2893 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2894 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2895 msleep(1);
2896 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2897 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2898 }
2506 2899
2507 if (rt2x00_rt(rt2x00dev, RT3070) || 2900 if (rt2x00_rt(rt2x00dev, RT3070) ||
2508 rt2x00_rt(rt2x00dev, RT3071) || 2901 rt2x00_rt(rt2x00dev, RT3071) ||
@@ -2510,7 +2903,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2510 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 2903 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2511 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 2904 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2512 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 2905 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2513 rt2800_rfcsr_write(rt2x00dev, 7, 0x70); 2906 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
2514 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 2907 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2515 rt2800_rfcsr_write(rt2x00dev, 10, 0x41); 2908 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2516 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 2909 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
@@ -2593,6 +2986,87 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2593 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 2986 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2594 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 2987 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2595 return 0; 2988 return 0;
2989 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2990 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
2991 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
2992 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
2993 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
2994 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
2995 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
2996 else
2997 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
2998 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
2999 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3000 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3001 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3002 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3003 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3004 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3005 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3006 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3007 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3008
3009 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3010 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3011 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3012 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3013 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3014 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3015 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3016 else
3017 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3018 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3019 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3020 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3021 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3022
3023 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3024 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3025 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3026 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3027 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3028 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3029 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3030 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3031 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3032 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3033
3034 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3035 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3036 else
3037 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3038 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3039 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3040 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3041 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3042 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3043 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3044 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3045 else
3046 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3047 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3048 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3049 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3050
3051 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3052 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3053 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3054 else
3055 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3056 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3057 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3058 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3059 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3060 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3061 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3062
3063 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3064 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3065 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3066 else
3067 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3068 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3069 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
2596 } 3070 }
2597 3071
2598 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { 3072 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
@@ -2602,12 +3076,12 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2602 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3076 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2603 } else if (rt2x00_rt(rt2x00dev, RT3071) || 3077 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2604 rt2x00_rt(rt2x00dev, RT3090)) { 3078 rt2x00_rt(rt2x00dev, RT3090)) {
3079 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3080
2605 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 3081 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2606 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); 3082 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2607 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 3083 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2608 3084
2609 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2610
2611 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg); 3085 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2612 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1); 3086 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
2613 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3087 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
@@ -2619,6 +3093,10 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2619 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0); 3093 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2620 } 3094 }
2621 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); 3095 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3096
3097 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3098 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3099 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2622 } else if (rt2x00_rt(rt2x00dev, RT3390)) { 3100 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2623 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg); 3101 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
2624 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0); 3102 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
@@ -2642,21 +3120,23 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2642 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15); 3120 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2643 } 3121 }
2644 3122
2645 /* 3123 if (!rt2x00_rt(rt2x00dev, RT5390)) {
2646 * Set back to initial state 3124 /*
2647 */ 3125 * Set back to initial state
2648 rt2800_bbp_write(rt2x00dev, 24, 0); 3126 */
3127 rt2800_bbp_write(rt2x00dev, 24, 0);
2649 3128
2650 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); 3129 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2651 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0); 3130 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2652 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); 3131 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2653 3132
2654 /* 3133 /*
2655 * set BBP back to BW20 3134 * Set BBP back to BW20
2656 */ 3135 */
2657 rt2800_bbp_read(rt2x00dev, 4, &bbp); 3136 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2658 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 3137 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2659 rt2800_bbp_write(rt2x00dev, 4, bbp); 3138 rt2800_bbp_write(rt2x00dev, 4, bbp);
3139 }
2660 3140
2661 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 3141 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2662 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3142 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
@@ -2668,24 +3148,29 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2668 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1); 3148 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2669 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); 3149 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2670 3150
2671 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 3151 if (!rt2x00_rt(rt2x00dev, RT5390)) {
2672 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); 3152 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2673 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || 3153 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2674 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || 3154 if (rt2x00_rt(rt2x00dev, RT3070) ||
2675 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { 3155 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2676 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) 3156 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2677 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); 3157 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2678 } 3158 if (!test_bit(CONFIG_EXTERNAL_LNA_BG,
2679 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom); 3159 &rt2x00dev->flags))
2680 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1) 3160 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2681 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN, 3161 }
2682 rt2x00_get_field16(eeprom, 3162 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2683 EEPROM_TXMIXER_GAIN_BG_VAL)); 3163 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2684 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); 3164 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3165 rt2x00_get_field16(eeprom,
3166 EEPROM_TXMIXER_GAIN_BG_VAL));
3167 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3168 }
2685 3169
2686 if (rt2x00_rt(rt2x00dev, RT3090)) { 3170 if (rt2x00_rt(rt2x00dev, RT3090)) {
2687 rt2800_bbp_read(rt2x00dev, 138, &bbp); 3171 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2688 3172
3173 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
2689 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 3174 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2690 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1) 3175 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2691 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0); 3176 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
@@ -2719,10 +3204,9 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2719 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); 3204 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2720 } 3205 }
2721 3206
2722 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) { 3207 if (rt2x00_rt(rt2x00dev, RT3070)) {
2723 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr); 3208 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2724 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) || 3209 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
2725 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2726 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3); 3210 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2727 else 3211 else
2728 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0); 3212 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
@@ -2732,6 +3216,20 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2732 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); 3216 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2733 } 3217 }
2734 3218
3219 if (rt2x00_rt(rt2x00dev, RT5390)) {
3220 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3221 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3222 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3223
3224 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3225 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3226 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3227
3228 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3229 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3230 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3231 }
3232
2735 return 0; 3233 return 0;
2736} 3234}
2737 3235
@@ -2810,10 +3308,7 @@ void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2810 3308
2811 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 3309 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2812 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 3310 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2813 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2814 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 3311 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2815 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2816 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2817 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 3312 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2818 3313
2819 /* Wait for DMA, ignore error */ 3314 /* Wait for DMA, ignore error */
@@ -2823,9 +3318,6 @@ void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2823 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0); 3318 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
2824 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); 3319 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2825 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 3320 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2826
2827 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2828 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2829} 3321}
2830EXPORT_SYMBOL_GPL(rt2800_disable_radio); 3322EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2831 3323
@@ -2986,13 +3478,6 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2986 default_lna_gain); 3478 default_lna_gain);
2987 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word); 3479 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2988 3480
2989 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2990 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2991 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2992 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2993 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2994 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2995
2996 return 0; 3481 return 0;
2997} 3482}
2998EXPORT_SYMBOL_GPL(rt2800_validate_eeprom); 3483EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
@@ -3009,10 +3494,15 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3009 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); 3494 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3010 3495
3011 /* 3496 /*
3012 * Identify RF chipset. 3497 * Identify RF chipset by EEPROM value
3498 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3499 * RT53xx: defined in "EEPROM_CHIP_ID" field
3013 */ 3500 */
3014 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3015 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 3501 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3502 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3503 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3504 else
3505 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3016 3506
3017 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 3507 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3018 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); 3508 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
@@ -3024,7 +3514,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3024 !rt2x00_rt(rt2x00dev, RT3071) && 3514 !rt2x00_rt(rt2x00dev, RT3071) &&
3025 !rt2x00_rt(rt2x00dev, RT3090) && 3515 !rt2x00_rt(rt2x00dev, RT3090) &&
3026 !rt2x00_rt(rt2x00dev, RT3390) && 3516 !rt2x00_rt(rt2x00dev, RT3390) &&
3027 !rt2x00_rt(rt2x00dev, RT3572)) { 3517 !rt2x00_rt(rt2x00dev, RT3572) &&
3518 !rt2x00_rt(rt2x00dev, RT5390)) {
3028 ERROR(rt2x00dev, "Invalid RT chipset detected.\n"); 3519 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3029 return -ENODEV; 3520 return -ENODEV;
3030 } 3521 }
@@ -3038,7 +3529,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3038 !rt2x00_rf(rt2x00dev, RF3021) && 3529 !rt2x00_rf(rt2x00dev, RF3021) &&
3039 !rt2x00_rf(rt2x00dev, RF3022) && 3530 !rt2x00_rf(rt2x00dev, RF3022) &&
3040 !rt2x00_rf(rt2x00dev, RF3052) && 3531 !rt2x00_rf(rt2x00dev, RF3052) &&
3041 !rt2x00_rf(rt2x00dev, RF3320)) { 3532 !rt2x00_rf(rt2x00dev, RF3320) &&
3533 !rt2x00_rf(rt2x00dev, RF5390)) {
3042 ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); 3534 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3043 return -ENODEV; 3535 return -ENODEV;
3044 } 3536 }
@@ -3046,11 +3538,35 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3046 /* 3538 /*
3047 * Identify default antenna configuration. 3539 * Identify default antenna configuration.
3048 */ 3540 */
3049 rt2x00dev->default_ant.tx = 3541 rt2x00dev->default_ant.tx_chain_num =
3050 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH); 3542 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3051 rt2x00dev->default_ant.rx = 3543 rt2x00dev->default_ant.rx_chain_num =
3052 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH); 3544 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3053 3545
3546 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3547
3548 if (rt2x00_rt(rt2x00dev, RT3070) ||
3549 rt2x00_rt(rt2x00dev, RT3090) ||
3550 rt2x00_rt(rt2x00dev, RT3390)) {
3551 value = rt2x00_get_field16(eeprom,
3552 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3553 switch (value) {
3554 case 0:
3555 case 1:
3556 case 2:
3557 rt2x00dev->default_ant.tx = ANTENNA_A;
3558 rt2x00dev->default_ant.rx = ANTENNA_A;
3559 break;
3560 case 3:
3561 rt2x00dev->default_ant.tx = ANTENNA_A;
3562 rt2x00dev->default_ant.rx = ANTENNA_B;
3563 break;
3564 }
3565 } else {
3566 rt2x00dev->default_ant.tx = ANTENNA_A;
3567 rt2x00dev->default_ant.rx = ANTENNA_A;
3568 }
3569
3054 /* 3570 /*
3055 * Read frequency offset and RF programming sequence. 3571 * Read frequency offset and RF programming sequence.
3056 */ 3572 */
@@ -3084,6 +3600,15 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3084 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); 3600 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3085#endif /* CONFIG_RT2X00_LIB_LEDS */ 3601#endif /* CONFIG_RT2X00_LIB_LEDS */
3086 3602
3603 /*
3604 * Check if support EIRP tx power limit feature.
3605 */
3606 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3607
3608 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3609 EIRP_MAX_TX_POWER_LIMIT)
3610 __set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
3611
3087 return 0; 3612 return 0;
3088} 3613}
3089EXPORT_SYMBOL_GPL(rt2800_init_eeprom); 3614EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
@@ -3236,7 +3761,6 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3236 char *default_power1; 3761 char *default_power1;
3237 char *default_power2; 3762 char *default_power2;
3238 unsigned int i; 3763 unsigned int i;
3239 unsigned short max_power;
3240 u16 eeprom; 3764 u16 eeprom;
3241 3765
3242 /* 3766 /*
@@ -3303,7 +3827,8 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3303 rt2x00_rf(rt2x00dev, RF2020) || 3827 rt2x00_rf(rt2x00dev, RF2020) ||
3304 rt2x00_rf(rt2x00dev, RF3021) || 3828 rt2x00_rf(rt2x00dev, RF3021) ||
3305 rt2x00_rf(rt2x00dev, RF3022) || 3829 rt2x00_rf(rt2x00dev, RF3022) ||
3306 rt2x00_rf(rt2x00dev, RF3320)) { 3830 rt2x00_rf(rt2x00dev, RF3320) ||
3831 rt2x00_rf(rt2x00dev, RF5390)) {
3307 spec->num_channels = 14; 3832 spec->num_channels = 14;
3308 spec->channels = rf_vals_3x; 3833 spec->channels = rf_vals_3x;
3309 } else if (rt2x00_rf(rt2x00dev, RF3052)) { 3834 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
@@ -3361,26 +3886,21 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3361 3886
3362 spec->channels_info = info; 3887 spec->channels_info = info;
3363 3888
3364 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3365 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3366 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1); 3889 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3367 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2); 3890 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3368 3891
3369 for (i = 0; i < 14; i++) { 3892 for (i = 0; i < 14; i++) {
3370 info[i].max_power = max_power; 3893 info[i].default_power1 = default_power1[i];
3371 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]); 3894 info[i].default_power2 = default_power2[i];
3372 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
3373 } 3895 }
3374 3896
3375 if (spec->num_channels > 14) { 3897 if (spec->num_channels > 14) {
3376 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3377 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1); 3898 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3378 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2); 3899 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3379 3900
3380 for (i = 14; i < spec->num_channels; i++) { 3901 for (i = 14; i < spec->num_channels; i++) {
3381 info[i].max_power = max_power; 3902 info[i].default_power1 = default_power1[i];
3382 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]); 3903 info[i].default_power2 = default_power2[i];
3383 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
3384 } 3904 }
3385 } 3905 }
3386 3906
@@ -3472,7 +3992,7 @@ int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3472 if (queue_idx >= 4) 3992 if (queue_idx >= 4)
3473 return 0; 3993 return 0;
3474 3994
3475 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 3995 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
3476 3996
3477 /* Update WMM TXOP register */ 3997 /* Update WMM TXOP register */
3478 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2))); 3998 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
@@ -3530,7 +4050,8 @@ EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3530 4050
3531int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 4051int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3532 enum ieee80211_ampdu_mlme_action action, 4052 enum ieee80211_ampdu_mlme_action action,
3533 struct ieee80211_sta *sta, u16 tid, u16 *ssn) 4053 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4054 u8 buf_size)
3534{ 4055{
3535 int ret = 0; 4056 int ret = 0;
3536 4057
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
index e3c995a9dec4..0c92d86a36f4 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.h
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -156,6 +156,7 @@ void rt2800_txdone(struct rt2x00_dev *rt2x00dev);
156void rt2800_txdone_entry(struct queue_entry *entry, u32 status); 156void rt2800_txdone_entry(struct queue_entry *entry, u32 status);
157 157
158void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc); 158void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc);
159void rt2800_clear_beacon(struct queue_entry *entry);
159 160
160extern const struct rt2x00debug rt2800_rt2x00debug; 161extern const struct rt2x00debug rt2800_rt2x00debug;
161 162
@@ -198,7 +199,8 @@ int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
198u64 rt2800_get_tsf(struct ieee80211_hw *hw); 199u64 rt2800_get_tsf(struct ieee80211_hw *hw);
199int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 200int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
200 enum ieee80211_ampdu_mlme_action action, 201 enum ieee80211_ampdu_mlme_action action,
201 struct ieee80211_sta *sta, u16 tid, u16 *ssn); 202 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
203 u8 buf_size);
202int rt2800_get_survey(struct ieee80211_hw *hw, int idx, 204int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
203 struct survey_info *survey); 205 struct survey_info *survey);
204 206
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 3b3f1e45ab3e..808073aa9dcc 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -200,11 +200,22 @@ static void rt2800pci_start_queue(struct data_queue *queue)
200 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 200 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
201 break; 201 break;
202 case QID_BEACON: 202 case QID_BEACON:
203 /*
204 * Allow beacon tasklets to be scheduled for periodic
205 * beacon updates.
206 */
207 tasklet_enable(&rt2x00dev->tbtt_tasklet);
208 tasklet_enable(&rt2x00dev->pretbtt_tasklet);
209
203 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 210 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
204 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 211 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
205 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 212 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
206 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 213 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
207 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 214 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
215
216 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
217 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
218 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
208 break; 219 break;
209 default: 220 default:
210 break; 221 break;
@@ -250,6 +261,16 @@ static void rt2800pci_stop_queue(struct data_queue *queue)
250 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0); 261 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
251 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 262 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
252 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 263 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
264
265 rt2800_register_read(rt2x00dev, INT_TIMER_EN, &reg);
266 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
267 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
268
269 /*
270 * Wait for tbtt tasklets to finish.
271 */
272 tasklet_disable(&rt2x00dev->tbtt_tasklet);
273 tasklet_disable(&rt2x00dev->pretbtt_tasklet);
253 break; 274 break;
254 default: 275 default:
255 break; 276 break;
@@ -397,9 +418,9 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
397static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 418static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
398 enum dev_state state) 419 enum dev_state state)
399{ 420{
400 int mask = (state == STATE_RADIO_IRQ_ON) || 421 int mask = (state == STATE_RADIO_IRQ_ON);
401 (state == STATE_RADIO_IRQ_ON_ISR);
402 u32 reg; 422 u32 reg;
423 unsigned long flags;
403 424
404 /* 425 /*
405 * When interrupts are being enabled, the interrupt registers 426 * When interrupts are being enabled, the interrupt registers
@@ -408,8 +429,17 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
408 if (state == STATE_RADIO_IRQ_ON) { 429 if (state == STATE_RADIO_IRQ_ON) {
409 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 430 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
410 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 431 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
432
433 /*
434 * Enable tasklets. The beacon related tasklets are
435 * enabled when the beacon queue is started.
436 */
437 tasklet_enable(&rt2x00dev->txstatus_tasklet);
438 tasklet_enable(&rt2x00dev->rxdone_tasklet);
439 tasklet_enable(&rt2x00dev->autowake_tasklet);
411 } 440 }
412 441
442 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
413 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg); 443 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
414 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0); 444 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
415 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0); 445 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
@@ -430,6 +460,17 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
430 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0); 460 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
431 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0); 461 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
432 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg); 462 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
463 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
464
465 if (state == STATE_RADIO_IRQ_OFF) {
466 /*
467 * Ensure that all tasklets are finished before
468 * disabling the interrupts.
469 */
470 tasklet_disable(&rt2x00dev->txstatus_tasklet);
471 tasklet_disable(&rt2x00dev->rxdone_tasklet);
472 tasklet_disable(&rt2x00dev->autowake_tasklet);
473 }
433} 474}
434 475
435static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev) 476static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
@@ -452,6 +493,13 @@ static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
452 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 493 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
453 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
454 495
496 if (rt2x00_rt(rt2x00dev, RT5390)) {
497 rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
498 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
499 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
500 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
501 }
502
455 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 503 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
456 504
457 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 505 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
@@ -475,39 +523,23 @@ static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
475 523
476static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev) 524static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
477{ 525{
478 u32 reg; 526 if (rt2x00_is_soc(rt2x00dev)) {
479 527 rt2800_disable_radio(rt2x00dev);
480 rt2800_disable_radio(rt2x00dev); 528 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
481 529 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
482 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280); 530 }
483
484 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
485 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
486 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
487 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
488 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
489 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
490 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
491 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
492 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
493
494 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
495 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
496} 531}
497 532
498static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev, 533static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
499 enum dev_state state) 534 enum dev_state state)
500{ 535{
501 /*
502 * Always put the device to sleep (even when we intend to wakeup!)
503 * if the device is booting and wasn't asleep it will return
504 * failure when attempting to wakeup.
505 */
506 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0xff, 2);
507
508 if (state == STATE_AWAKE) { 536 if (state == STATE_AWAKE) {
509 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0); 537 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
510 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP); 538 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
539 } else if (state == STATE_SLEEP) {
540 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, 0xffffffff);
541 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, 0xffffffff);
542 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
511 } 543 }
512 544
513 return 0; 545 return 0;
@@ -538,9 +570,7 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
538 rt2800pci_set_state(rt2x00dev, STATE_SLEEP); 570 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
539 break; 571 break;
540 case STATE_RADIO_IRQ_ON: 572 case STATE_RADIO_IRQ_ON:
541 case STATE_RADIO_IRQ_ON_ISR:
542 case STATE_RADIO_IRQ_OFF: 573 case STATE_RADIO_IRQ_OFF:
543 case STATE_RADIO_IRQ_OFF_ISR:
544 rt2800pci_toggle_irq(rt2x00dev, state); 574 rt2800pci_toggle_irq(rt2x00dev, state);
545 break; 575 break;
546 case STATE_DEEP_SLEEP: 576 case STATE_DEEP_SLEEP:
@@ -696,7 +726,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
696 726
697 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) { 727 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
698 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE); 728 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
699 if (qid >= QID_RX) { 729 if (unlikely(qid >= QID_RX)) {
700 /* 730 /*
701 * Unknown queue, this shouldn't happen. Just drop 731 * Unknown queue, this shouldn't happen. Just drop
702 * this tx status. 732 * this tx status.
@@ -706,7 +736,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
706 break; 736 break;
707 } 737 }
708 738
709 queue = rt2x00queue_get_queue(rt2x00dev, qid); 739 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
710 if (unlikely(queue == NULL)) { 740 if (unlikely(queue == NULL)) {
711 /* 741 /*
712 * The queue is NULL, this shouldn't happen. Stop 742 * The queue is NULL, this shouldn't happen. Stop
@@ -717,7 +747,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
717 break; 747 break;
718 } 748 }
719 749
720 if (rt2x00queue_empty(queue)) { 750 if (unlikely(rt2x00queue_empty(queue))) {
721 /* 751 /*
722 * The queue is empty. Stop processing here 752 * The queue is empty. Stop processing here
723 * and drop the tx status. 753 * and drop the tx status.
@@ -732,45 +762,59 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
732 } 762 }
733} 763}
734 764
735static void rt2800pci_txstatus_tasklet(unsigned long data) 765static void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
766 struct rt2x00_field32 irq_field)
736{ 767{
737 rt2800pci_txdone((struct rt2x00_dev *)data); 768 u32 reg;
738}
739
740static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
741{
742 struct rt2x00_dev *rt2x00dev = dev_instance;
743 u32 reg = rt2x00dev->irqvalue[0];
744 769
745 /* 770 /*
746 * 1 - Pre TBTT interrupt. 771 * Enable a single interrupt. The interrupt mask register
772 * access needs locking.
747 */ 773 */
748 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT)) 774 spin_lock_irq(&rt2x00dev->irqmask_lock);
749 rt2x00lib_pretbtt(rt2x00dev); 775 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
776 rt2x00_set_field32(&reg, irq_field, 1);
777 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
778 spin_unlock_irq(&rt2x00dev->irqmask_lock);
779}
750 780
751 /* 781static void rt2800pci_txstatus_tasklet(unsigned long data)
752 * 2 - Beacondone interrupt. 782{
753 */ 783 rt2800pci_txdone((struct rt2x00_dev *)data);
754 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
755 rt2x00lib_beacondone(rt2x00dev);
756 784
757 /* 785 /*
758 * 3 - Rx ring done interrupt. 786 * No need to enable the tx status interrupt here as we always
787 * leave it enabled to minimize the possibility of a tx status
788 * register overflow. See comment in interrupt handler.
759 */ 789 */
760 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE)) 790}
761 rt2x00pci_rxdone(rt2x00dev);
762 791
763 /* 792static void rt2800pci_pretbtt_tasklet(unsigned long data)
764 * 4 - Auto wakeup interrupt. 793{
765 */ 794 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
766 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) 795 rt2x00lib_pretbtt(rt2x00dev);
767 rt2800pci_wakeup(rt2x00dev); 796 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
797}
768 798
769 /* Enable interrupts again. */ 799static void rt2800pci_tbtt_tasklet(unsigned long data)
770 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 800{
771 STATE_RADIO_IRQ_ON_ISR); 801 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
802 rt2x00lib_beacondone(rt2x00dev);
803 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
804}
772 805
773 return IRQ_HANDLED; 806static void rt2800pci_rxdone_tasklet(unsigned long data)
807{
808 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
809 rt2x00pci_rxdone(rt2x00dev);
810 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
811}
812
813static void rt2800pci_autowake_tasklet(unsigned long data)
814{
815 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
816 rt2800pci_wakeup(rt2x00dev);
817 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
774} 818}
775 819
776static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev) 820static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
@@ -791,7 +835,7 @@ static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
791 * 835 *
792 * Furthermore we don't disable the TX_FIFO_STATUS 836 * Furthermore we don't disable the TX_FIFO_STATUS
793 * interrupt here but leave it enabled so that the TX_STA_FIFO 837 * interrupt here but leave it enabled so that the TX_STA_FIFO
794 * can also be read while the interrupt thread gets executed. 838 * can also be read while the tx status tasklet gets executed.
795 * 839 *
796 * Since we have only one producer and one consumer we don't 840 * Since we have only one producer and one consumer we don't
797 * need to lock the kfifo. 841 * need to lock the kfifo.
@@ -816,8 +860,7 @@ static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
816static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance) 860static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
817{ 861{
818 struct rt2x00_dev *rt2x00dev = dev_instance; 862 struct rt2x00_dev *rt2x00dev = dev_instance;
819 u32 reg; 863 u32 reg, mask;
820 irqreturn_t ret = IRQ_HANDLED;
821 864
822 /* Read status and ACK all interrupts */ 865 /* Read status and ACK all interrupts */
823 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 866 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
@@ -829,38 +872,44 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
829 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 872 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
830 return IRQ_HANDLED; 873 return IRQ_HANDLED;
831 874
832 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) 875 /*
833 rt2800pci_txstatus_interrupt(rt2x00dev); 876 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
877 * for interrupts and interrupt masks we can just use the value of
878 * INT_SOURCE_CSR to create the interrupt mask.
879 */
880 mask = ~reg;
834 881
835 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT) || 882 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
836 rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT) || 883 rt2800pci_txstatus_interrupt(rt2x00dev);
837 rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE) ||
838 rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP)) {
839 /* 884 /*
840 * All other interrupts are handled in the interrupt thread. 885 * Never disable the TX_FIFO_STATUS interrupt.
841 * Store irqvalue for use in the interrupt thread.
842 */ 886 */
843 rt2x00dev->irqvalue[0] = reg; 887 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
888 }
844 889
845 /* 890 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
846 * Disable interrupts, will be enabled again in the 891 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
847 * interrupt thread.
848 */
849 rt2x00dev->ops->lib->set_device_state(rt2x00dev,
850 STATE_RADIO_IRQ_OFF_ISR);
851 892
852 /* 893 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
853 * Leave the TX_FIFO_STATUS interrupt enabled to not lose any 894 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
854 * tx status reports.
855 */
856 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
857 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
858 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
859 895
860 ret = IRQ_WAKE_THREAD; 896 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
861 } 897 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
862 898
863 return ret; 899 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
900 tasklet_schedule(&rt2x00dev->autowake_tasklet);
901
902 /*
903 * Disable all interrupts for which a tasklet was scheduled right now,
904 * the tasklet will reenable the appropriate interrupts.
905 */
906 spin_lock(&rt2x00dev->irqmask_lock);
907 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
908 reg &= mask;
909 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
910 spin_unlock(&rt2x00dev->irqmask_lock);
911
912 return IRQ_HANDLED;
864} 913}
865 914
866/* 915/*
@@ -928,6 +977,7 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
928 if (!modparam_nohwcrypt) 977 if (!modparam_nohwcrypt)
929 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 978 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
930 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 979 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
980 __set_bit(DRIVER_REQUIRE_HT_TX_DESC, &rt2x00dev->flags);
931 981
932 /* 982 /*
933 * Set the rssi offset. 983 * Set the rssi offset.
@@ -975,8 +1025,11 @@ static const struct rt2800_ops rt2800pci_rt2800_ops = {
975 1025
976static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { 1026static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
977 .irq_handler = rt2800pci_interrupt, 1027 .irq_handler = rt2800pci_interrupt,
978 .irq_handler_thread = rt2800pci_interrupt_thread, 1028 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
979 .txstatus_tasklet = rt2800pci_txstatus_tasklet, 1029 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1030 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1031 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1032 .autowake_tasklet = rt2800pci_autowake_tasklet,
980 .probe_hw = rt2800pci_probe_hw, 1033 .probe_hw = rt2800pci_probe_hw,
981 .get_firmware_name = rt2800pci_get_firmware_name, 1034 .get_firmware_name = rt2800pci_get_firmware_name,
982 .check_firmware = rt2800_check_firmware, 1035 .check_firmware = rt2800_check_firmware,
@@ -996,6 +1049,7 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
996 .write_tx_desc = rt2800pci_write_tx_desc, 1049 .write_tx_desc = rt2800pci_write_tx_desc,
997 .write_tx_data = rt2800_write_tx_data, 1050 .write_tx_data = rt2800_write_tx_data,
998 .write_beacon = rt2800_write_beacon, 1051 .write_beacon = rt2800_write_beacon,
1052 .clear_beacon = rt2800_clear_beacon,
999 .fill_rxdone = rt2800pci_fill_rxdone, 1053 .fill_rxdone = rt2800pci_fill_rxdone,
1000 .config_shared_key = rt2800_config_shared_key, 1054 .config_shared_key = rt2800_config_shared_key,
1001 .config_pairwise_key = rt2800_config_pairwise_key, 1055 .config_pairwise_key = rt2800_config_pairwise_key,
@@ -1079,6 +1133,9 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1079 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1133 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1080 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1134 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1081#endif 1135#endif
1136#ifdef CONFIG_RT2800PCI_RT53XX
1137 { PCI_DEVICE(0x1814, 0x5390), PCI_DEVICE_DATA(&rt2800pci_ops) },
1138#endif
1082 { 0, } 1139 { 0, }
1083}; 1140};
1084#endif /* CONFIG_PCI */ 1141#endif /* CONFIG_PCI */
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 197a36c05fda..f1a92144996f 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -253,9 +253,7 @@ static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
253 rt2800usb_set_state(rt2x00dev, STATE_SLEEP); 253 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
254 break; 254 break;
255 case STATE_RADIO_IRQ_ON: 255 case STATE_RADIO_IRQ_ON:
256 case STATE_RADIO_IRQ_ON_ISR:
257 case STATE_RADIO_IRQ_OFF: 256 case STATE_RADIO_IRQ_OFF:
258 case STATE_RADIO_IRQ_OFF_ISR:
259 /* No support, but no error either */ 257 /* No support, but no error either */
260 break; 258 break;
261 case STATE_DEEP_SLEEP: 259 case STATE_DEEP_SLEEP:
@@ -567,6 +565,7 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
567 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags); 565 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
568 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags); 566 __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
569 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags); 567 __set_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags);
568 __set_bit(DRIVER_REQUIRE_HT_TX_DESC, &rt2x00dev->flags);
570 569
571 /* 570 /*
572 * Set the rssi offset. 571 * Set the rssi offset.
@@ -639,6 +638,7 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
639 .write_tx_desc = rt2800usb_write_tx_desc, 638 .write_tx_desc = rt2800usb_write_tx_desc,
640 .write_tx_data = rt2800usb_write_tx_data, 639 .write_tx_data = rt2800usb_write_tx_data,
641 .write_beacon = rt2800_write_beacon, 640 .write_beacon = rt2800_write_beacon,
641 .clear_beacon = rt2800_clear_beacon,
642 .get_tx_data_len = rt2800usb_get_tx_data_len, 642 .get_tx_data_len = rt2800usb_get_tx_data_len,
643 .fill_rxdone = rt2800usb_fill_rxdone, 643 .fill_rxdone = rt2800usb_fill_rxdone,
644 .config_shared_key = rt2800_config_shared_key, 644 .config_shared_key = rt2800_config_shared_key,
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 84aaf393da43..a3940d7300a4 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -189,6 +189,7 @@ struct rt2x00_chip {
189#define RT3572 0x3572 189#define RT3572 0x3572
190#define RT3593 0x3593 /* PCIe */ 190#define RT3593 0x3593 /* PCIe */
191#define RT3883 0x3883 /* WSOC */ 191#define RT3883 0x3883 /* WSOC */
192#define RT5390 0x5390 /* 2.4GHz */
192 193
193 u16 rf; 194 u16 rf;
194 u16 rev; 195 u16 rev;
@@ -225,6 +226,8 @@ struct channel_info {
225struct antenna_setup { 226struct antenna_setup {
226 enum antenna rx; 227 enum antenna rx;
227 enum antenna tx; 228 enum antenna tx;
229 u8 rx_chain_num;
230 u8 tx_chain_num;
228}; 231};
229 232
230/* 233/*
@@ -368,6 +371,7 @@ struct rt2x00_intf {
368 * dedicated beacon entry. 371 * dedicated beacon entry.
369 */ 372 */
370 struct queue_entry *beacon; 373 struct queue_entry *beacon;
374 bool enable_beacon;
371 375
372 /* 376 /*
373 * Actions that needed rescheduling. 377 * Actions that needed rescheduling.
@@ -463,7 +467,6 @@ struct rt2x00lib_crypto {
463 const u8 *address; 467 const u8 *address;
464 468
465 u32 bssidx; 469 u32 bssidx;
466 u32 aid;
467 470
468 u8 key[16]; 471 u8 key[16];
469 u8 tx_mic[8]; 472 u8 tx_mic[8];
@@ -511,14 +514,13 @@ struct rt2x00lib_ops {
511 irq_handler_t irq_handler; 514 irq_handler_t irq_handler;
512 515
513 /* 516 /*
514 * Threaded Interrupt handlers.
515 */
516 irq_handler_t irq_handler_thread;
517
518 /*
519 * TX status tasklet handler. 517 * TX status tasklet handler.
520 */ 518 */
521 void (*txstatus_tasklet) (unsigned long data); 519 void (*txstatus_tasklet) (unsigned long data);
520 void (*pretbtt_tasklet) (unsigned long data);
521 void (*tbtt_tasklet) (unsigned long data);
522 void (*rxdone_tasklet) (unsigned long data);
523 void (*autowake_tasklet) (unsigned long data);
522 524
523 /* 525 /*
524 * Device init handlers. 526 * Device init handlers.
@@ -573,6 +575,7 @@ struct rt2x00lib_ops {
573 struct txentry_desc *txdesc); 575 struct txentry_desc *txdesc);
574 void (*write_beacon) (struct queue_entry *entry, 576 void (*write_beacon) (struct queue_entry *entry,
575 struct txentry_desc *txdesc); 577 struct txentry_desc *txdesc);
578 void (*clear_beacon) (struct queue_entry *entry);
576 int (*get_tx_data_len) (struct queue_entry *entry); 579 int (*get_tx_data_len) (struct queue_entry *entry);
577 580
578 /* 581 /*
@@ -658,12 +661,15 @@ enum rt2x00_flags {
658 DRIVER_REQUIRE_L2PAD, 661 DRIVER_REQUIRE_L2PAD,
659 DRIVER_REQUIRE_TXSTATUS_FIFO, 662 DRIVER_REQUIRE_TXSTATUS_FIFO,
660 DRIVER_REQUIRE_TASKLET_CONTEXT, 663 DRIVER_REQUIRE_TASKLET_CONTEXT,
664 DRIVER_REQUIRE_SW_SEQNO,
665 DRIVER_REQUIRE_HT_TX_DESC,
661 666
662 /* 667 /*
663 * Driver features 668 * Driver features
664 */ 669 */
665 CONFIG_SUPPORT_HW_BUTTON, 670 CONFIG_SUPPORT_HW_BUTTON,
666 CONFIG_SUPPORT_HW_CRYPTO, 671 CONFIG_SUPPORT_HW_CRYPTO,
672 CONFIG_SUPPORT_POWER_LIMIT,
667 DRIVER_SUPPORT_CONTROL_FILTERS, 673 DRIVER_SUPPORT_CONTROL_FILTERS,
668 DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, 674 DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL,
669 DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, 675 DRIVER_SUPPORT_PRE_TBTT_INTERRUPT,
@@ -788,10 +794,12 @@ struct rt2x00_dev {
788 * - Open ap interface count. 794 * - Open ap interface count.
789 * - Open sta interface count. 795 * - Open sta interface count.
790 * - Association count. 796 * - Association count.
797 * - Beaconing enabled count.
791 */ 798 */
792 unsigned int intf_ap_count; 799 unsigned int intf_ap_count;
793 unsigned int intf_sta_count; 800 unsigned int intf_sta_count;
794 unsigned int intf_associated; 801 unsigned int intf_associated;
802 unsigned int intf_beaconing;
795 803
796 /* 804 /*
797 * Link quality 805 * Link quality
@@ -857,6 +865,13 @@ struct rt2x00_dev {
857 */ 865 */
858 struct ieee80211_low_level_stats low_level_stats; 866 struct ieee80211_low_level_stats low_level_stats;
859 867
868 /**
869 * Work queue for all work which should not be placed
870 * on the mac80211 workqueue (because of dependencies
871 * between various work structures).
872 */
873 struct workqueue_struct *workqueue;
874
860 /* 875 /*
861 * Scheduled work. 876 * Scheduled work.
862 * NOTE: intf_work will use ieee80211_iterate_active_interfaces() 877 * NOTE: intf_work will use ieee80211_iterate_active_interfaces()
@@ -872,14 +887,13 @@ struct rt2x00_dev {
872 struct work_struct txdone_work; 887 struct work_struct txdone_work;
873 888
874 /* 889 /*
875 * Data queue arrays for RX, TX and Beacon. 890 * Data queue arrays for RX, TX, Beacon and ATIM.
876 * The Beacon array also contains the Atim queue
877 * if that is supported by the device.
878 */ 891 */
879 unsigned int data_queues; 892 unsigned int data_queues;
880 struct data_queue *rx; 893 struct data_queue *rx;
881 struct data_queue *tx; 894 struct data_queue *tx;
882 struct data_queue *bcn; 895 struct data_queue *bcn;
896 struct data_queue *atim;
883 897
884 /* 898 /*
885 * Firmware image. 899 * Firmware image.
@@ -887,12 +901,6 @@ struct rt2x00_dev {
887 const struct firmware *fw; 901 const struct firmware *fw;
888 902
889 /* 903 /*
890 * Interrupt values, stored between interrupt service routine
891 * and interrupt thread routine.
892 */
893 u32 irqvalue[2];
894
895 /*
896 * FIFO for storing tx status reports between isr and tasklet. 904 * FIFO for storing tx status reports between isr and tasklet.
897 */ 905 */
898 DECLARE_KFIFO_PTR(txstatus_fifo, u32); 906 DECLARE_KFIFO_PTR(txstatus_fifo, u32);
@@ -901,6 +909,15 @@ struct rt2x00_dev {
901 * Tasklet for processing tx status reports (rt2800pci). 909 * Tasklet for processing tx status reports (rt2800pci).
902 */ 910 */
903 struct tasklet_struct txstatus_tasklet; 911 struct tasklet_struct txstatus_tasklet;
912 struct tasklet_struct pretbtt_tasklet;
913 struct tasklet_struct tbtt_tasklet;
914 struct tasklet_struct rxdone_tasklet;
915 struct tasklet_struct autowake_tasklet;
916
917 /*
918 * Protect the interrupt mask register.
919 */
920 spinlock_t irqmask_lock;
904}; 921};
905 922
906/* 923/*
@@ -1046,12 +1063,24 @@ void rt2x00queue_map_txskb(struct queue_entry *entry);
1046void rt2x00queue_unmap_skb(struct queue_entry *entry); 1063void rt2x00queue_unmap_skb(struct queue_entry *entry);
1047 1064
1048/** 1065/**
1049 * rt2x00queue_get_queue - Convert queue index to queue pointer 1066 * rt2x00queue_get_tx_queue - Convert tx queue index to queue pointer
1050 * @rt2x00dev: Pointer to &struct rt2x00_dev. 1067 * @rt2x00dev: Pointer to &struct rt2x00_dev.
1051 * @queue: rt2x00 queue index (see &enum data_queue_qid). 1068 * @queue: rt2x00 queue index (see &enum data_queue_qid).
1069 *
1070 * Returns NULL for non tx queues.
1052 */ 1071 */
1053struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev, 1072static inline struct data_queue *
1054 const enum data_queue_qid queue); 1073rt2x00queue_get_tx_queue(struct rt2x00_dev *rt2x00dev,
1074 const enum data_queue_qid queue)
1075{
1076 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
1077 return &rt2x00dev->tx[queue];
1078
1079 if (queue == QID_ATIM)
1080 return rt2x00dev->atim;
1081
1082 return NULL;
1083}
1055 1084
1056/** 1085/**
1057 * rt2x00queue_get_entry - Get queue entry where the given index points to. 1086 * rt2x00queue_get_entry - Get queue entry where the given index points to.
@@ -1168,7 +1197,7 @@ void rt2x00lib_rxdone(struct queue_entry *entry);
1168/* 1197/*
1169 * mac80211 handlers. 1198 * mac80211 handlers.
1170 */ 1199 */
1171int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb); 1200void rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
1172int rt2x00mac_start(struct ieee80211_hw *hw); 1201int rt2x00mac_start(struct ieee80211_hw *hw);
1173void rt2x00mac_stop(struct ieee80211_hw *hw); 1202void rt2x00mac_stop(struct ieee80211_hw *hw);
1174int rt2x00mac_add_interface(struct ieee80211_hw *hw, 1203int rt2x00mac_add_interface(struct ieee80211_hw *hw,
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
index 9597a03242cc..9de9dbe94399 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dev.c
+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
@@ -121,7 +121,7 @@ static void rt2x00lib_intf_scheduled_iter(void *data, u8 *mac,
121 return; 121 return;
122 122
123 if (test_and_clear_bit(DELAYED_UPDATE_BEACON, &intf->delayed_flags)) 123 if (test_and_clear_bit(DELAYED_UPDATE_BEACON, &intf->delayed_flags))
124 rt2x00queue_update_beacon(rt2x00dev, vif, true); 124 rt2x00queue_update_beacon(rt2x00dev, vif);
125} 125}
126 126
127static void rt2x00lib_intf_scheduled(struct work_struct *work) 127static void rt2x00lib_intf_scheduled(struct work_struct *work)
@@ -174,7 +174,13 @@ static void rt2x00lib_beaconupdate_iter(void *data, u8 *mac,
174 vif->type != NL80211_IFTYPE_WDS) 174 vif->type != NL80211_IFTYPE_WDS)
175 return; 175 return;
176 176
177 rt2x00queue_update_beacon(rt2x00dev, vif, true); 177 /*
178 * Update the beacon without locking. This is safe on PCI devices
179 * as they only update the beacon periodically here. This should
180 * never be called for USB devices.
181 */
182 WARN_ON(rt2x00_is_usb(rt2x00dev));
183 rt2x00queue_update_beacon_locked(rt2x00dev, vif);
178} 184}
179 185
180void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev) 186void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev)
@@ -183,9 +189,9 @@ void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev)
183 return; 189 return;
184 190
185 /* send buffered bc/mc frames out for every bssid */ 191 /* send buffered bc/mc frames out for every bssid */
186 ieee80211_iterate_active_interfaces(rt2x00dev->hw, 192 ieee80211_iterate_active_interfaces_atomic(rt2x00dev->hw,
187 rt2x00lib_bc_buffer_iter, 193 rt2x00lib_bc_buffer_iter,
188 rt2x00dev); 194 rt2x00dev);
189 /* 195 /*
190 * Devices with pre tbtt interrupt don't need to update the beacon 196 * Devices with pre tbtt interrupt don't need to update the beacon
191 * here as they will fetch the next beacon directly prior to 197 * here as they will fetch the next beacon directly prior to
@@ -195,9 +201,9 @@ void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev)
195 return; 201 return;
196 202
197 /* fetch next beacon */ 203 /* fetch next beacon */
198 ieee80211_iterate_active_interfaces(rt2x00dev->hw, 204 ieee80211_iterate_active_interfaces_atomic(rt2x00dev->hw,
199 rt2x00lib_beaconupdate_iter, 205 rt2x00lib_beaconupdate_iter,
200 rt2x00dev); 206 rt2x00dev);
201} 207}
202EXPORT_SYMBOL_GPL(rt2x00lib_beacondone); 208EXPORT_SYMBOL_GPL(rt2x00lib_beacondone);
203 209
@@ -207,9 +213,9 @@ void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev)
207 return; 213 return;
208 214
209 /* fetch next beacon */ 215 /* fetch next beacon */
210 ieee80211_iterate_active_interfaces(rt2x00dev->hw, 216 ieee80211_iterate_active_interfaces_atomic(rt2x00dev->hw,
211 rt2x00lib_beaconupdate_iter, 217 rt2x00lib_beaconupdate_iter,
212 rt2x00dev); 218 rt2x00dev);
213} 219}
214EXPORT_SYMBOL_GPL(rt2x00lib_pretbtt); 220EXPORT_SYMBOL_GPL(rt2x00lib_pretbtt);
215 221
@@ -649,7 +655,10 @@ static void rt2x00lib_channel(struct ieee80211_channel *entry,
649 const int channel, const int tx_power, 655 const int channel, const int tx_power,
650 const int value) 656 const int value)
651{ 657{
652 entry->center_freq = ieee80211_channel_to_frequency(channel); 658 /* XXX: this assumption about the band is wrong for 802.11j */
659 entry->band = channel <= 14 ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
660 entry->center_freq = ieee80211_channel_to_frequency(channel,
661 entry->band);
653 entry->hw_value = value; 662 entry->hw_value = value;
654 entry->max_power = tx_power; 663 entry->max_power = tx_power;
655 entry->max_antenna_gain = 0xff; 664 entry->max_antenna_gain = 0xff;
@@ -812,15 +821,29 @@ static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev)
812 GFP_KERNEL); 821 GFP_KERNEL);
813 if (status) 822 if (status)
814 return status; 823 return status;
824 }
815 825
816 /* tasklet for processing the tx status reports. */ 826 /*
817 if (rt2x00dev->ops->lib->txstatus_tasklet) 827 * Initialize tasklets if used by the driver. Tasklets are
818 tasklet_init(&rt2x00dev->txstatus_tasklet, 828 * disabled until the interrupts are turned on. The driver
819 rt2x00dev->ops->lib->txstatus_tasklet, 829 * has to handle that.
820 (unsigned long)rt2x00dev); 830 */
821 831#define RT2X00_TASKLET_INIT(taskletname) \
832 if (rt2x00dev->ops->lib->taskletname) { \
833 tasklet_init(&rt2x00dev->taskletname, \
834 rt2x00dev->ops->lib->taskletname, \
835 (unsigned long)rt2x00dev); \
836 tasklet_disable(&rt2x00dev->taskletname); \
822 } 837 }
823 838
839 RT2X00_TASKLET_INIT(txstatus_tasklet);
840 RT2X00_TASKLET_INIT(pretbtt_tasklet);
841 RT2X00_TASKLET_INIT(tbtt_tasklet);
842 RT2X00_TASKLET_INIT(rxdone_tasklet);
843 RT2X00_TASKLET_INIT(autowake_tasklet);
844
845#undef RT2X00_TASKLET_INIT
846
824 /* 847 /*
825 * Register HW. 848 * Register HW.
826 */ 849 */
@@ -949,6 +972,7 @@ int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev)
949{ 972{
950 int retval = -ENOMEM; 973 int retval = -ENOMEM;
951 974
975 spin_lock_init(&rt2x00dev->irqmask_lock);
952 mutex_init(&rt2x00dev->csr_mutex); 976 mutex_init(&rt2x00dev->csr_mutex);
953 977
954 set_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags); 978 set_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags);
@@ -973,8 +997,15 @@ int rt2x00lib_probe_dev(struct rt2x00_dev *rt2x00dev)
973 BIT(NL80211_IFTYPE_WDS); 997 BIT(NL80211_IFTYPE_WDS);
974 998
975 /* 999 /*
976 * Initialize configuration work. 1000 * Initialize work.
977 */ 1001 */
1002 rt2x00dev->workqueue =
1003 alloc_ordered_workqueue(wiphy_name(rt2x00dev->hw->wiphy), 0);
1004 if (!rt2x00dev->workqueue) {
1005 retval = -ENOMEM;
1006 goto exit;
1007 }
1008
978 INIT_WORK(&rt2x00dev->intf_work, rt2x00lib_intf_scheduled); 1009 INIT_WORK(&rt2x00dev->intf_work, rt2x00lib_intf_scheduled);
979 1010
980 /* 1011 /*
@@ -1033,6 +1064,7 @@ void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev)
1033 cancel_work_sync(&rt2x00dev->intf_work); 1064 cancel_work_sync(&rt2x00dev->intf_work);
1034 cancel_work_sync(&rt2x00dev->rxdone_work); 1065 cancel_work_sync(&rt2x00dev->rxdone_work);
1035 cancel_work_sync(&rt2x00dev->txdone_work); 1066 cancel_work_sync(&rt2x00dev->txdone_work);
1067 destroy_workqueue(rt2x00dev->workqueue);
1036 1068
1037 /* 1069 /*
1038 * Free the tx status fifo. 1070 * Free the tx status fifo.
@@ -1043,6 +1075,10 @@ void rt2x00lib_remove_dev(struct rt2x00_dev *rt2x00dev)
1043 * Kill the tx status tasklet. 1075 * Kill the tx status tasklet.
1044 */ 1076 */
1045 tasklet_kill(&rt2x00dev->txstatus_tasklet); 1077 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1078 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
1079 tasklet_kill(&rt2x00dev->tbtt_tasklet);
1080 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1081 tasklet_kill(&rt2x00dev->autowake_tasklet);
1046 1082
1047 /* 1083 /*
1048 * Uninitialize device. 1084 * Uninitialize device.
diff --git a/drivers/net/wireless/rt2x00/rt2x00ht.c b/drivers/net/wireless/rt2x00/rt2x00ht.c
index b7ad46ecaa1d..ae1219dffaae 100644
--- a/drivers/net/wireless/rt2x00/rt2x00ht.c
+++ b/drivers/net/wireless/rt2x00/rt2x00ht.c
@@ -38,12 +38,12 @@ void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
38 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data; 38 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
39 39
40 if (tx_info->control.sta) 40 if (tx_info->control.sta)
41 txdesc->mpdu_density = 41 txdesc->u.ht.mpdu_density =
42 tx_info->control.sta->ht_cap.ampdu_density; 42 tx_info->control.sta->ht_cap.ampdu_density;
43 43
44 txdesc->ba_size = 7; /* FIXME: What value is needed? */ 44 txdesc->u.ht.ba_size = 7; /* FIXME: What value is needed? */
45 45
46 txdesc->stbc = 46 txdesc->u.ht.stbc =
47 (tx_info->flags & IEEE80211_TX_CTL_STBC) >> IEEE80211_TX_CTL_STBC_SHIFT; 47 (tx_info->flags & IEEE80211_TX_CTL_STBC) >> IEEE80211_TX_CTL_STBC_SHIFT;
48 48
49 /* 49 /*
@@ -51,25 +51,24 @@ void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
51 * mcs rate to be used 51 * mcs rate to be used
52 */ 52 */
53 if (txrate->flags & IEEE80211_TX_RC_MCS) { 53 if (txrate->flags & IEEE80211_TX_RC_MCS) {
54 txdesc->mcs = txrate->idx; 54 txdesc->u.ht.mcs = txrate->idx;
55 55
56 /* 56 /*
57 * MIMO PS should be set to 1 for STA's using dynamic SM PS 57 * MIMO PS should be set to 1 for STA's using dynamic SM PS
58 * when using more then one tx stream (>MCS7). 58 * when using more then one tx stream (>MCS7).
59 */ 59 */
60 if (tx_info->control.sta && txdesc->mcs > 7 && 60 if (tx_info->control.sta && txdesc->u.ht.mcs > 7 &&
61 ((tx_info->control.sta->ht_cap.cap & 61 ((tx_info->control.sta->ht_cap.cap &
62 IEEE80211_HT_CAP_SM_PS) >> 62 IEEE80211_HT_CAP_SM_PS) >>
63 IEEE80211_HT_CAP_SM_PS_SHIFT) == 63 IEEE80211_HT_CAP_SM_PS_SHIFT) ==
64 WLAN_HT_CAP_SM_PS_DYNAMIC) 64 WLAN_HT_CAP_SM_PS_DYNAMIC)
65 __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags); 65 __set_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags);
66 } else { 66 } else {
67 txdesc->mcs = rt2x00_get_rate_mcs(hwrate->mcs); 67 txdesc->u.ht.mcs = rt2x00_get_rate_mcs(hwrate->mcs);
68 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 68 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
69 txdesc->mcs |= 0x08; 69 txdesc->u.ht.mcs |= 0x08;
70 } 70 }
71 71
72
73 /* 72 /*
74 * This frame is eligible for an AMPDU, however, don't aggregate 73 * This frame is eligible for an AMPDU, however, don't aggregate
75 * frames that are intended to probe a specific tx rate. 74 * frames that are intended to probe a specific tx rate.
@@ -79,14 +78,6 @@ void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
79 __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags); 78 __set_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags);
80 79
81 /* 80 /*
82 * Determine HT Mix/Greenfield rate mode
83 */
84 if (txrate->flags & IEEE80211_TX_RC_MCS)
85 txdesc->rate_mode = RATE_MODE_HT_MIX;
86 if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
87 txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
88
89 /*
90 * Set 40Mhz mode if necessary (for legacy rates this will 81 * Set 40Mhz mode if necessary (for legacy rates this will
91 * duplicate the frame to both channels). 82 * duplicate the frame to both channels).
92 */ 83 */
@@ -106,11 +97,11 @@ void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
106 * for frames not transmitted with TXOP_HTTXOP 97 * for frames not transmitted with TXOP_HTTXOP
107 */ 98 */
108 if (ieee80211_is_mgmt(hdr->frame_control)) 99 if (ieee80211_is_mgmt(hdr->frame_control))
109 txdesc->txop = TXOP_BACKOFF; 100 txdesc->u.ht.txop = TXOP_BACKOFF;
110 else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)) 101 else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
111 txdesc->txop = TXOP_SIFS; 102 txdesc->u.ht.txop = TXOP_SIFS;
112 else 103 else
113 txdesc->txop = TXOP_HTTXOP; 104 txdesc->u.ht.txop = TXOP_HTTXOP;
114} 105}
115 106
116u16 rt2x00ht_center_channel(struct rt2x00_dev *rt2x00dev, 107u16 rt2x00ht_center_channel(struct rt2x00_dev *rt2x00dev,
diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h
index a105c500627b..2d94cbaf5f4a 100644
--- a/drivers/net/wireless/rt2x00/rt2x00lib.h
+++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
@@ -157,14 +157,30 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
157 bool local); 157 bool local);
158 158
159/** 159/**
160 * rt2x00queue_update_beacon - Send new beacon from mac80211 to hardware 160 * rt2x00queue_update_beacon - Send new beacon from mac80211
161 * to hardware. Handles locking by itself (mutex).
161 * @rt2x00dev: Pointer to &struct rt2x00_dev. 162 * @rt2x00dev: Pointer to &struct rt2x00_dev.
162 * @vif: Interface for which the beacon should be updated. 163 * @vif: Interface for which the beacon should be updated.
163 * @enable_beacon: Enable beaconing
164 */ 164 */
165int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev, 165int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
166 struct ieee80211_vif *vif, 166 struct ieee80211_vif *vif);
167 const bool enable_beacon); 167
168/**
169 * rt2x00queue_update_beacon_locked - Send new beacon from mac80211
170 * to hardware. Caller needs to ensure locking.
171 * @rt2x00dev: Pointer to &struct rt2x00_dev.
172 * @vif: Interface for which the beacon should be updated.
173 */
174int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev,
175 struct ieee80211_vif *vif);
176
177/**
178 * rt2x00queue_clear_beacon - Clear beacon in hardware
179 * @rt2x00dev: Pointer to &struct rt2x00_dev.
180 * @vif: Interface for which the beacon should be updated.
181 */
182int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
183 struct ieee80211_vif *vif);
168 184
169/** 185/**
170 * rt2x00queue_index_inc - Index incrementation function 186 * rt2x00queue_index_inc - Index incrementation function
diff --git a/drivers/net/wireless/rt2x00/rt2x00link.c b/drivers/net/wireless/rt2x00/rt2x00link.c
index bfda60eaf4ef..c975b0a12e95 100644
--- a/drivers/net/wireless/rt2x00/rt2x00link.c
+++ b/drivers/net/wireless/rt2x00/rt2x00link.c
@@ -417,7 +417,8 @@ void rt2x00link_start_watchdog(struct rt2x00_dev *rt2x00dev)
417 !test_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags)) 417 !test_bit(DRIVER_SUPPORT_WATCHDOG, &rt2x00dev->flags))
418 return; 418 return;
419 419
420 schedule_delayed_work(&link->watchdog_work, WATCHDOG_INTERVAL); 420 ieee80211_queue_delayed_work(rt2x00dev->hw,
421 &link->watchdog_work, WATCHDOG_INTERVAL);
421} 422}
422 423
423void rt2x00link_stop_watchdog(struct rt2x00_dev *rt2x00dev) 424void rt2x00link_stop_watchdog(struct rt2x00_dev *rt2x00dev)
@@ -441,7 +442,9 @@ static void rt2x00link_watchdog(struct work_struct *work)
441 rt2x00dev->ops->lib->watchdog(rt2x00dev); 442 rt2x00dev->ops->lib->watchdog(rt2x00dev);
442 443
443 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags)) 444 if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
444 schedule_delayed_work(&link->watchdog_work, WATCHDOG_INTERVAL); 445 ieee80211_queue_delayed_work(rt2x00dev->hw,
446 &link->watchdog_work,
447 WATCHDOG_INTERVAL);
445} 448}
446 449
447void rt2x00link_register(struct rt2x00_dev *rt2x00dev) 450void rt2x00link_register(struct rt2x00_dev *rt2x00dev)
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c
index f3da051df39e..661c6baad2b9 100644
--- a/drivers/net/wireless/rt2x00/rt2x00mac.c
+++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
@@ -99,7 +99,7 @@ static int rt2x00mac_tx_rts_cts(struct rt2x00_dev *rt2x00dev,
99 return retval; 99 return retval;
100} 100}
101 101
102int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 102void rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
103{ 103{
104 struct rt2x00_dev *rt2x00dev = hw->priv; 104 struct rt2x00_dev *rt2x00dev = hw->priv;
105 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 105 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -116,13 +116,13 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
116 goto exit_fail; 116 goto exit_fail;
117 117
118 /* 118 /*
119 * Determine which queue to put packet on. 119 * Use the ATIM queue if appropriate and present.
120 */ 120 */
121 if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM && 121 if (tx_info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM &&
122 test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) 122 test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags))
123 queue = rt2x00queue_get_queue(rt2x00dev, QID_ATIM); 123 qid = QID_ATIM;
124 else 124
125 queue = rt2x00queue_get_queue(rt2x00dev, qid); 125 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
126 if (unlikely(!queue)) { 126 if (unlikely(!queue)) {
127 ERROR(rt2x00dev, 127 ERROR(rt2x00dev,
128 "Attempt to send packet over invalid queue %d.\n" 128 "Attempt to send packet over invalid queue %d.\n"
@@ -139,9 +139,9 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
139 * either RTS or CTS-to-self frame and handles everything 139 * either RTS or CTS-to-self frame and handles everything
140 * inside the hardware. 140 * inside the hardware.
141 */ 141 */
142 if ((tx_info->control.rates[0].flags & (IEEE80211_TX_RC_USE_RTS_CTS | 142 if (!rt2x00dev->ops->hw->set_rts_threshold &&
143 IEEE80211_TX_RC_USE_CTS_PROTECT)) && 143 (tx_info->control.rates[0].flags & (IEEE80211_TX_RC_USE_RTS_CTS |
144 !rt2x00dev->ops->hw->set_rts_threshold) { 144 IEEE80211_TX_RC_USE_CTS_PROTECT))) {
145 if (rt2x00queue_available(queue) <= 1) 145 if (rt2x00queue_available(queue) <= 1)
146 goto exit_fail; 146 goto exit_fail;
147 147
@@ -149,18 +149,17 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
149 goto exit_fail; 149 goto exit_fail;
150 } 150 }
151 151
152 if (rt2x00queue_write_tx_frame(queue, skb, false)) 152 if (unlikely(rt2x00queue_write_tx_frame(queue, skb, false)))
153 goto exit_fail; 153 goto exit_fail;
154 154
155 if (rt2x00queue_threshold(queue)) 155 if (rt2x00queue_threshold(queue))
156 rt2x00queue_pause_queue(queue); 156 rt2x00queue_pause_queue(queue);
157 157
158 return NETDEV_TX_OK; 158 return;
159 159
160 exit_fail: 160 exit_fail:
161 ieee80211_stop_queue(rt2x00dev->hw, qid); 161 ieee80211_stop_queue(rt2x00dev->hw, qid);
162 dev_kfree_skb_any(skb); 162 dev_kfree_skb_any(skb);
163 return NETDEV_TX_OK;
164} 163}
165EXPORT_SYMBOL_GPL(rt2x00mac_tx); 164EXPORT_SYMBOL_GPL(rt2x00mac_tx);
166 165
@@ -191,7 +190,7 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
191{ 190{
192 struct rt2x00_dev *rt2x00dev = hw->priv; 191 struct rt2x00_dev *rt2x00dev = hw->priv;
193 struct rt2x00_intf *intf = vif_to_intf(vif); 192 struct rt2x00_intf *intf = vif_to_intf(vif);
194 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); 193 struct data_queue *queue = rt2x00dev->bcn;
195 struct queue_entry *entry = NULL; 194 struct queue_entry *entry = NULL;
196 unsigned int i; 195 unsigned int i;
197 196
@@ -519,11 +518,9 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
519 518
520 crypto.cmd = cmd; 519 crypto.cmd = cmd;
521 520
522 if (sta) { 521 if (sta)
523 /* some drivers need the AID */
524 crypto.aid = sta->aid;
525 crypto.address = sta->addr; 522 crypto.address = sta->addr;
526 } else 523 else
527 crypto.address = bcast_addr; 524 crypto.address = bcast_addr;
528 525
529 if (crypto.cipher == CIPHER_TKIP) 526 if (crypto.cipher == CIPHER_TKIP)
@@ -617,11 +614,47 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
617 bss_conf->bssid); 614 bss_conf->bssid);
618 615
619 /* 616 /*
620 * Update the beacon. 617 * Update the beacon. This is only required on USB devices. PCI
618 * devices fetch beacons periodically.
621 */ 619 */
622 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED)) 620 if (changes & BSS_CHANGED_BEACON && rt2x00_is_usb(rt2x00dev))
623 rt2x00queue_update_beacon(rt2x00dev, vif, 621 rt2x00queue_update_beacon(rt2x00dev, vif);
624 bss_conf->enable_beacon); 622
623 /*
624 * Start/stop beaconing.
625 */
626 if (changes & BSS_CHANGED_BEACON_ENABLED) {
627 if (!bss_conf->enable_beacon && intf->enable_beacon) {
628 rt2x00queue_clear_beacon(rt2x00dev, vif);
629 rt2x00dev->intf_beaconing--;
630 intf->enable_beacon = false;
631
632 if (rt2x00dev->intf_beaconing == 0) {
633 /*
634 * Last beaconing interface disabled
635 * -> stop beacon queue.
636 */
637 mutex_lock(&intf->beacon_skb_mutex);
638 rt2x00queue_stop_queue(rt2x00dev->bcn);
639 mutex_unlock(&intf->beacon_skb_mutex);
640 }
641
642
643 } else if (bss_conf->enable_beacon && !intf->enable_beacon) {
644 rt2x00dev->intf_beaconing++;
645 intf->enable_beacon = true;
646
647 if (rt2x00dev->intf_beaconing == 1) {
648 /*
649 * First beaconing interface enabled
650 * -> start beacon queue.
651 */
652 mutex_lock(&intf->beacon_skb_mutex);
653 rt2x00queue_start_queue(rt2x00dev->bcn);
654 mutex_unlock(&intf->beacon_skb_mutex);
655 }
656 }
657 }
625 658
626 /* 659 /*
627 * When the association status has changed we must reset the link 660 * When the association status has changed we must reset the link
@@ -657,7 +690,7 @@ int rt2x00mac_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
657 struct rt2x00_dev *rt2x00dev = hw->priv; 690 struct rt2x00_dev *rt2x00dev = hw->priv;
658 struct data_queue *queue; 691 struct data_queue *queue;
659 692
660 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 693 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
661 if (unlikely(!queue)) 694 if (unlikely(!queue))
662 return -EINVAL; 695 return -EINVAL;
663 696
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index ace0b668c04e..4dd82b0b0520 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -160,10 +160,9 @@ int rt2x00pci_initialize(struct rt2x00_dev *rt2x00dev)
160 /* 160 /*
161 * Register interrupt handler. 161 * Register interrupt handler.
162 */ 162 */
163 status = request_threaded_irq(rt2x00dev->irq, 163 status = request_irq(rt2x00dev->irq,
164 rt2x00dev->ops->lib->irq_handler, 164 rt2x00dev->ops->lib->irq_handler,
165 rt2x00dev->ops->lib->irq_handler_thread, 165 IRQF_SHARED, rt2x00dev->name, rt2x00dev);
166 IRQF_SHARED, rt2x00dev->name, rt2x00dev);
167 if (status) { 166 if (status) {
168 ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n", 167 ERROR(rt2x00dev, "IRQ %d allocation failed (error %d).\n",
169 rt2x00dev->irq, status); 168 rt2x00dev->irq, status);
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index ca82b3a91697..4b3c70eeef1f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -221,14 +221,17 @@ static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
221 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif); 221 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
222 unsigned long irqflags; 222 unsigned long irqflags;
223 223
224 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) || 224 if (!(tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
225 unlikely(!tx_info->control.vif)) 225 return;
226
227 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
228
229 if (!test_bit(DRIVER_REQUIRE_SW_SEQNO, &entry->queue->rt2x00dev->flags))
226 return; 230 return;
227 231
228 /* 232 /*
229 * Hardware should insert sequence counter. 233 * The hardware is not able to insert a sequence number. Assign a
230 * FIXME: We insert a software sequence counter first for 234 * software generated one here.
231 * hardware that doesn't support hardware sequence counting.
232 * 235 *
233 * This is wrong because beacons are not getting sequence 236 * This is wrong because beacons are not getting sequence
234 * numbers assigned properly. 237 * numbers assigned properly.
@@ -246,7 +249,6 @@ static void rt2x00queue_create_tx_descriptor_seq(struct queue_entry *entry,
246 249
247 spin_unlock_irqrestore(&intf->seqlock, irqflags); 250 spin_unlock_irqrestore(&intf->seqlock, irqflags);
248 251
249 __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
250} 252}
251 253
252static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry, 254static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
@@ -260,6 +262,16 @@ static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
260 unsigned int duration; 262 unsigned int duration;
261 unsigned int residual; 263 unsigned int residual;
262 264
265 /*
266 * Determine with what IFS priority this frame should be send.
267 * Set ifs to IFS_SIFS when the this is not the first fragment,
268 * or this fragment came after RTS/CTS.
269 */
270 if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
271 txdesc->u.plcp.ifs = IFS_BACKOFF;
272 else
273 txdesc->u.plcp.ifs = IFS_SIFS;
274
263 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */ 275 /* Data length + CRC + Crypto overhead (IV/EIV/ICV/MIC) */
264 data_length = entry->skb->len + 4; 276 data_length = entry->skb->len + 4;
265 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb); 277 data_length += rt2x00crypto_tx_overhead(rt2x00dev, entry->skb);
@@ -268,12 +280,12 @@ static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
268 * PLCP setup 280 * PLCP setup
269 * Length calculation depends on OFDM/CCK rate. 281 * Length calculation depends on OFDM/CCK rate.
270 */ 282 */
271 txdesc->signal = hwrate->plcp; 283 txdesc->u.plcp.signal = hwrate->plcp;
272 txdesc->service = 0x04; 284 txdesc->u.plcp.service = 0x04;
273 285
274 if (hwrate->flags & DEV_RATE_OFDM) { 286 if (hwrate->flags & DEV_RATE_OFDM) {
275 txdesc->length_high = (data_length >> 6) & 0x3f; 287 txdesc->u.plcp.length_high = (data_length >> 6) & 0x3f;
276 txdesc->length_low = data_length & 0x3f; 288 txdesc->u.plcp.length_low = data_length & 0x3f;
277 } else { 289 } else {
278 /* 290 /*
279 * Convert length to microseconds. 291 * Convert length to microseconds.
@@ -288,18 +300,18 @@ static void rt2x00queue_create_tx_descriptor_plcp(struct queue_entry *entry,
288 * Check if we need to set the Length Extension 300 * Check if we need to set the Length Extension
289 */ 301 */
290 if (hwrate->bitrate == 110 && residual <= 30) 302 if (hwrate->bitrate == 110 && residual <= 30)
291 txdesc->service |= 0x80; 303 txdesc->u.plcp.service |= 0x80;
292 } 304 }
293 305
294 txdesc->length_high = (duration >> 8) & 0xff; 306 txdesc->u.plcp.length_high = (duration >> 8) & 0xff;
295 txdesc->length_low = duration & 0xff; 307 txdesc->u.plcp.length_low = duration & 0xff;
296 308
297 /* 309 /*
298 * When preamble is enabled we should set the 310 * When preamble is enabled we should set the
299 * preamble bit for the signal. 311 * preamble bit for the signal.
300 */ 312 */
301 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 313 if (txrate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
302 txdesc->signal |= 0x08; 314 txdesc->u.plcp.signal |= 0x08;
303 } 315 }
304} 316}
305 317
@@ -309,9 +321,9 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
309 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 321 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
310 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 322 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
311 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data; 323 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
312 struct ieee80211_rate *rate = 324 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
313 ieee80211_get_tx_rate(rt2x00dev->hw, tx_info); 325 struct ieee80211_rate *rate;
314 const struct rt2x00_rate *hwrate; 326 const struct rt2x00_rate *hwrate = NULL;
315 327
316 memset(txdesc, 0, sizeof(*txdesc)); 328 memset(txdesc, 0, sizeof(*txdesc));
317 329
@@ -365,42 +377,42 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
365 377
366 /* 378 /*
367 * Beacons and probe responses require the tsf timestamp 379 * Beacons and probe responses require the tsf timestamp
368 * to be inserted into the frame, except for a frame that has been injected 380 * to be inserted into the frame.
369 * through a monitor interface. This latter is needed for testing a
370 * monitor interface.
371 */ 381 */
372 if ((ieee80211_is_beacon(hdr->frame_control) || 382 if (ieee80211_is_beacon(hdr->frame_control) ||
373 ieee80211_is_probe_resp(hdr->frame_control)) && 383 ieee80211_is_probe_resp(hdr->frame_control))
374 (!(tx_info->flags & IEEE80211_TX_CTL_INJECTED)))
375 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags); 384 __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
376 385
377 /*
378 * Determine with what IFS priority this frame should be send.
379 * Set ifs to IFS_SIFS when the this is not the first fragment,
380 * or this fragment came after RTS/CTS.
381 */
382 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) && 386 if ((tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) &&
383 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) { 387 !test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags))
384 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags); 388 __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
385 txdesc->ifs = IFS_BACKOFF;
386 } else
387 txdesc->ifs = IFS_SIFS;
388 389
389 /* 390 /*
390 * Determine rate modulation. 391 * Determine rate modulation.
391 */ 392 */
392 hwrate = rt2x00_get_rate(rate->hw_value); 393 if (txrate->flags & IEEE80211_TX_RC_GREEN_FIELD)
393 txdesc->rate_mode = RATE_MODE_CCK; 394 txdesc->rate_mode = RATE_MODE_HT_GREENFIELD;
394 if (hwrate->flags & DEV_RATE_OFDM) 395 else if (txrate->flags & IEEE80211_TX_RC_MCS)
395 txdesc->rate_mode = RATE_MODE_OFDM; 396 txdesc->rate_mode = RATE_MODE_HT_MIX;
397 else {
398 rate = ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
399 hwrate = rt2x00_get_rate(rate->hw_value);
400 if (hwrate->flags & DEV_RATE_OFDM)
401 txdesc->rate_mode = RATE_MODE_OFDM;
402 else
403 txdesc->rate_mode = RATE_MODE_CCK;
404 }
396 405
397 /* 406 /*
398 * Apply TX descriptor handling by components 407 * Apply TX descriptor handling by components
399 */ 408 */
400 rt2x00crypto_create_tx_descriptor(entry, txdesc); 409 rt2x00crypto_create_tx_descriptor(entry, txdesc);
401 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
402 rt2x00queue_create_tx_descriptor_seq(entry, txdesc); 410 rt2x00queue_create_tx_descriptor_seq(entry, txdesc);
403 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate); 411
412 if (test_bit(DRIVER_REQUIRE_HT_TX_DESC, &rt2x00dev->flags))
413 rt2x00ht_create_tx_descriptor(entry, txdesc, hwrate);
414 else
415 rt2x00queue_create_tx_descriptor_plcp(entry, txdesc, hwrate);
404} 416}
405 417
406static int rt2x00queue_write_tx_data(struct queue_entry *entry, 418static int rt2x00queue_write_tx_data(struct queue_entry *entry,
@@ -566,13 +578,10 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
566 return 0; 578 return 0;
567} 579}
568 580
569int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev, 581int rt2x00queue_clear_beacon(struct rt2x00_dev *rt2x00dev,
570 struct ieee80211_vif *vif, 582 struct ieee80211_vif *vif)
571 const bool enable_beacon)
572{ 583{
573 struct rt2x00_intf *intf = vif_to_intf(vif); 584 struct rt2x00_intf *intf = vif_to_intf(vif);
574 struct skb_frame_desc *skbdesc;
575 struct txentry_desc txdesc;
576 585
577 if (unlikely(!intf->beacon)) 586 if (unlikely(!intf->beacon))
578 return -ENOBUFS; 587 return -ENOBUFS;
@@ -584,17 +593,36 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
584 */ 593 */
585 rt2x00queue_free_skb(intf->beacon); 594 rt2x00queue_free_skb(intf->beacon);
586 595
587 if (!enable_beacon) { 596 /*
588 rt2x00queue_stop_queue(intf->beacon->queue); 597 * Clear beacon (single bssid devices don't need to clear the beacon
589 mutex_unlock(&intf->beacon_skb_mutex); 598 * since the beacon queue will get stopped anyway).
590 return 0; 599 */
591 } 600 if (rt2x00dev->ops->lib->clear_beacon)
601 rt2x00dev->ops->lib->clear_beacon(intf->beacon);
602
603 mutex_unlock(&intf->beacon_skb_mutex);
604
605 return 0;
606}
607
608int rt2x00queue_update_beacon_locked(struct rt2x00_dev *rt2x00dev,
609 struct ieee80211_vif *vif)
610{
611 struct rt2x00_intf *intf = vif_to_intf(vif);
612 struct skb_frame_desc *skbdesc;
613 struct txentry_desc txdesc;
614
615 if (unlikely(!intf->beacon))
616 return -ENOBUFS;
617
618 /*
619 * Clean up the beacon skb.
620 */
621 rt2x00queue_free_skb(intf->beacon);
592 622
593 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif); 623 intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
594 if (!intf->beacon->skb) { 624 if (!intf->beacon->skb)
595 mutex_unlock(&intf->beacon_skb_mutex);
596 return -ENOMEM; 625 return -ENOMEM;
597 }
598 626
599 /* 627 /*
600 * Copy all TX descriptor information into txdesc, 628 * Copy all TX descriptor information into txdesc,
@@ -611,13 +639,25 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
611 skbdesc->entry = intf->beacon; 639 skbdesc->entry = intf->beacon;
612 640
613 /* 641 /*
614 * Send beacon to hardware and enable beacon genaration.. 642 * Send beacon to hardware.
615 */ 643 */
616 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc); 644 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
617 645
646 return 0;
647
648}
649
650int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
651 struct ieee80211_vif *vif)
652{
653 struct rt2x00_intf *intf = vif_to_intf(vif);
654 int ret;
655
656 mutex_lock(&intf->beacon_skb_mutex);
657 ret = rt2x00queue_update_beacon_locked(rt2x00dev, vif);
618 mutex_unlock(&intf->beacon_skb_mutex); 658 mutex_unlock(&intf->beacon_skb_mutex);
619 659
620 return 0; 660 return ret;
621} 661}
622 662
623void rt2x00queue_for_each_entry(struct data_queue *queue, 663void rt2x00queue_for_each_entry(struct data_queue *queue,
@@ -665,29 +705,6 @@ void rt2x00queue_for_each_entry(struct data_queue *queue,
665} 705}
666EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry); 706EXPORT_SYMBOL_GPL(rt2x00queue_for_each_entry);
667 707
668struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
669 const enum data_queue_qid queue)
670{
671 int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
672
673 if (queue == QID_RX)
674 return rt2x00dev->rx;
675
676 if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
677 return &rt2x00dev->tx[queue];
678
679 if (!rt2x00dev->bcn)
680 return NULL;
681
682 if (queue == QID_BEACON)
683 return &rt2x00dev->bcn[0];
684 else if (queue == QID_ATIM && atim)
685 return &rt2x00dev->bcn[1];
686
687 return NULL;
688}
689EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
690
691struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue, 708struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
692 enum queue_index index) 709 enum queue_index index)
693{ 710{
@@ -885,7 +902,7 @@ void rt2x00queue_flush_queue(struct data_queue *queue, bool drop)
885 * The queue flush has failed... 902 * The queue flush has failed...
886 */ 903 */
887 if (unlikely(!rt2x00queue_empty(queue))) 904 if (unlikely(!rt2x00queue_empty(queue)))
888 WARNING(queue->rt2x00dev, "Queue %d failed to flush", queue->qid); 905 WARNING(queue->rt2x00dev, "Queue %d failed to flush\n", queue->qid);
889 906
890 /* 907 /*
891 * Restore the queue to the previous status 908 * Restore the queue to the previous status
@@ -1063,7 +1080,7 @@ int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
1063 goto exit; 1080 goto exit;
1064 1081
1065 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) { 1082 if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
1066 status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1], 1083 status = rt2x00queue_alloc_entries(rt2x00dev->atim,
1067 rt2x00dev->ops->atim); 1084 rt2x00dev->ops->atim);
1068 if (status) 1085 if (status)
1069 goto exit; 1086 goto exit;
@@ -1137,6 +1154,7 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
1137 rt2x00dev->rx = queue; 1154 rt2x00dev->rx = queue;
1138 rt2x00dev->tx = &queue[1]; 1155 rt2x00dev->tx = &queue[1];
1139 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues]; 1156 rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
1157 rt2x00dev->atim = req_atim ? &queue[2 + rt2x00dev->ops->tx_queues] : NULL;
1140 1158
1141 /* 1159 /*
1142 * Initialize queue parameters. 1160 * Initialize queue parameters.
@@ -1153,9 +1171,9 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
1153 tx_queue_for_each(rt2x00dev, queue) 1171 tx_queue_for_each(rt2x00dev, queue)
1154 rt2x00queue_init(rt2x00dev, queue, qid++); 1172 rt2x00queue_init(rt2x00dev, queue, qid++);
1155 1173
1156 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON); 1174 rt2x00queue_init(rt2x00dev, rt2x00dev->bcn, QID_BEACON);
1157 if (req_atim) 1175 if (req_atim)
1158 rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM); 1176 rt2x00queue_init(rt2x00dev, rt2x00dev->atim, QID_ATIM);
1159 1177
1160 return 0; 1178 return 0;
1161} 1179}
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index fab8e2687f29..0c8b0c699679 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -305,20 +305,27 @@ struct txentry_desc {
305 u16 length; 305 u16 length;
306 u16 header_length; 306 u16 header_length;
307 307
308 u16 length_high; 308 union {
309 u16 length_low; 309 struct {
310 u16 signal; 310 u16 length_high;
311 u16 service; 311 u16 length_low;
312 312 u16 signal;
313 u16 mcs; 313 u16 service;
314 u16 stbc; 314 enum ifs ifs;
315 u16 ba_size; 315 } plcp;
316 u16 rate_mode; 316
317 u16 mpdu_density; 317 struct {
318 u16 mcs;
319 u8 stbc;
320 u8 ba_size;
321 u8 mpdu_density;
322 enum txop txop;
323 } ht;
324 } u;
325
326 enum rate_modulation rate_mode;
318 327
319 short retry_limit; 328 short retry_limit;
320 short ifs;
321 short txop;
322 329
323 enum cipher cipher; 330 enum cipher cipher;
324 u16 key_idx; 331 u16 key_idx;
diff --git a/drivers/net/wireless/rt2x00/rt2x00reg.h b/drivers/net/wireless/rt2x00/rt2x00reg.h
index e8259ae48ced..6f867eec49cc 100644
--- a/drivers/net/wireless/rt2x00/rt2x00reg.h
+++ b/drivers/net/wireless/rt2x00/rt2x00reg.h
@@ -85,8 +85,6 @@ enum dev_state {
85 STATE_RADIO_OFF, 85 STATE_RADIO_OFF,
86 STATE_RADIO_IRQ_ON, 86 STATE_RADIO_IRQ_ON,
87 STATE_RADIO_IRQ_OFF, 87 STATE_RADIO_IRQ_OFF,
88 STATE_RADIO_IRQ_ON_ISR,
89 STATE_RADIO_IRQ_OFF_ISR,
90}; 88};
91 89
92/* 90/*
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index 1a9937d5aff6..fbe735f5b352 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -227,7 +227,7 @@ static void rt2x00usb_interrupt_txdone(struct urb *urb)
227 * Schedule the delayed work for reading the TX status 227 * Schedule the delayed work for reading the TX status
228 * from the device. 228 * from the device.
229 */ 229 */
230 ieee80211_queue_work(rt2x00dev->hw, &rt2x00dev->txdone_work); 230 queue_work(rt2x00dev->workqueue, &rt2x00dev->txdone_work);
231} 231}
232 232
233static void rt2x00usb_kick_tx_entry(struct queue_entry *entry) 233static void rt2x00usb_kick_tx_entry(struct queue_entry *entry)
@@ -320,7 +320,7 @@ static void rt2x00usb_interrupt_rxdone(struct urb *urb)
320 * Schedule the delayed work for reading the RX status 320 * Schedule the delayed work for reading the RX status
321 * from the device. 321 * from the device.
322 */ 322 */
323 ieee80211_queue_work(rt2x00dev->hw, &rt2x00dev->rxdone_work); 323 queue_work(rt2x00dev->workqueue, &rt2x00dev->rxdone_work);
324} 324}
325 325
326static void rt2x00usb_kick_rx_entry(struct queue_entry *entry) 326static void rt2x00usb_kick_rx_entry(struct queue_entry *entry)
@@ -429,7 +429,7 @@ void rt2x00usb_flush_queue(struct data_queue *queue)
429 * Schedule the completion handler manually, when this 429 * Schedule the completion handler manually, when this
430 * worker function runs, it should cleanup the queue. 430 * worker function runs, it should cleanup the queue.
431 */ 431 */
432 ieee80211_queue_work(queue->rt2x00dev->hw, completion); 432 queue_work(queue->rt2x00dev->workqueue, completion);
433 433
434 /* 434 /*
435 * Wait for a little while to give the driver 435 * Wait for a little while to give the driver
@@ -453,7 +453,7 @@ static void rt2x00usb_watchdog_tx_status(struct data_queue *queue)
453 WARNING(queue->rt2x00dev, "TX queue %d status timed out," 453 WARNING(queue->rt2x00dev, "TX queue %d status timed out,"
454 " invoke forced tx handler\n", queue->qid); 454 " invoke forced tx handler\n", queue->qid);
455 455
456 ieee80211_queue_work(queue->rt2x00dev->hw, &queue->rt2x00dev->txdone_work); 456 queue_work(queue->rt2x00dev->workqueue, &queue->rt2x00dev->txdone_work);
457} 457}
458 458
459void rt2x00usb_watchdog(struct rt2x00_dev *rt2x00dev) 459void rt2x00usb_watchdog(struct rt2x00_dev *rt2x00dev)
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 8de44dd401e0..77e8113b91e1 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -551,26 +551,14 @@ static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
551 struct rt2x00intf_conf *conf, 551 struct rt2x00intf_conf *conf,
552 const unsigned int flags) 552 const unsigned int flags)
553{ 553{
554 unsigned int beacon_base;
555 u32 reg; 554 u32 reg;
556 555
557 if (flags & CONFIG_UPDATE_TYPE) { 556 if (flags & CONFIG_UPDATE_TYPE) {
558 /* 557 /*
559 * Clear current synchronisation setup.
560 * For the Beacon base registers, we only need to clear
561 * the first byte since that byte contains the VALID and OWNER
562 * bits which (when set to 0) will invalidate the entire beacon.
563 */
564 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
565 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
566
567 /*
568 * Enable synchronisation. 558 * Enable synchronisation.
569 */ 559 */
570 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 560 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
571 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
572 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 561 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
573 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
574 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 562 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
575 } 563 }
576 564
@@ -1154,6 +1142,11 @@ static void rt61pci_start_queue(struct data_queue *queue)
1154 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg); 1142 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1155 break; 1143 break;
1156 case QID_BEACON: 1144 case QID_BEACON:
1145 /*
1146 * Allow the tbtt tasklet to be scheduled.
1147 */
1148 tasklet_enable(&rt2x00dev->tbtt_tasklet);
1149
1157 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1150 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1158 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); 1151 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1159 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); 1152 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
@@ -1233,6 +1226,11 @@ static void rt61pci_stop_queue(struct data_queue *queue)
1233 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1226 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1234 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1227 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1235 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1228 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1229
1230 /*
1231 * Wait for possibly running tbtt tasklets.
1232 */
1233 tasklet_disable(&rt2x00dev->tbtt_tasklet);
1236 break; 1234 break;
1237 default: 1235 default:
1238 break; 1236 break;
@@ -1719,9 +1717,9 @@ static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1719static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 1717static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1720 enum dev_state state) 1718 enum dev_state state)
1721{ 1719{
1722 int mask = (state == STATE_RADIO_IRQ_OFF) || 1720 int mask = (state == STATE_RADIO_IRQ_OFF);
1723 (state == STATE_RADIO_IRQ_OFF_ISR);
1724 u32 reg; 1721 u32 reg;
1722 unsigned long flags;
1725 1723
1726 /* 1724 /*
1727 * When interrupts are being enabled, the interrupt registers 1725 * When interrupts are being enabled, the interrupt registers
@@ -1733,12 +1731,21 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1733 1731
1734 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg); 1732 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1735 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); 1733 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1734
1735 /*
1736 * Enable tasklets.
1737 */
1738 tasklet_enable(&rt2x00dev->txstatus_tasklet);
1739 tasklet_enable(&rt2x00dev->rxdone_tasklet);
1740 tasklet_enable(&rt2x00dev->autowake_tasklet);
1736 } 1741 }
1737 1742
1738 /* 1743 /*
1739 * Only toggle the interrupts bits we are going to use. 1744 * Only toggle the interrupts bits we are going to use.
1740 * Non-checked interrupt bits are disabled by default. 1745 * Non-checked interrupt bits are disabled by default.
1741 */ 1746 */
1747 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
1748
1742 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 1749 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1743 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask); 1750 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1744 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask); 1751 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
@@ -1758,6 +1765,17 @@ static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1758 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask); 1765 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1759 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask); 1766 rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_TWAKEUP, mask);
1760 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); 1767 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1768
1769 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
1770
1771 if (state == STATE_RADIO_IRQ_OFF) {
1772 /*
1773 * Ensure that all tasklets are finished.
1774 */
1775 tasklet_disable(&rt2x00dev->txstatus_tasklet);
1776 tasklet_disable(&rt2x00dev->rxdone_tasklet);
1777 tasklet_disable(&rt2x00dev->autowake_tasklet);
1778 }
1761} 1779}
1762 1780
1763static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) 1781static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1833,9 +1851,7 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1833 rt61pci_disable_radio(rt2x00dev); 1851 rt61pci_disable_radio(rt2x00dev);
1834 break; 1852 break;
1835 case STATE_RADIO_IRQ_ON: 1853 case STATE_RADIO_IRQ_ON:
1836 case STATE_RADIO_IRQ_ON_ISR:
1837 case STATE_RADIO_IRQ_OFF: 1854 case STATE_RADIO_IRQ_OFF:
1838 case STATE_RADIO_IRQ_OFF_ISR:
1839 rt61pci_toggle_irq(rt2x00dev, state); 1855 rt61pci_toggle_irq(rt2x00dev, state);
1840 break; 1856 break;
1841 case STATE_DEEP_SLEEP: 1857 case STATE_DEEP_SLEEP:
@@ -1882,10 +1898,12 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
1882 rt2x00_desc_write(txd, 1, word); 1898 rt2x00_desc_write(txd, 1, word);
1883 1899
1884 rt2x00_desc_read(txd, 2, &word); 1900 rt2x00_desc_read(txd, 2, &word);
1885 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); 1901 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1886 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); 1902 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1887 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); 1903 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1888 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); 1904 txdesc->u.plcp.length_low);
1905 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1906 txdesc->u.plcp.length_high);
1889 rt2x00_desc_write(txd, 2, word); 1907 rt2x00_desc_write(txd, 2, word);
1890 1908
1891 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1909 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
@@ -1930,7 +1948,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
1930 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1948 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1931 rt2x00_set_field32(&word, TXD_W0_OFDM, 1949 rt2x00_set_field32(&word, TXD_W0_OFDM,
1932 (txdesc->rate_mode == RATE_MODE_OFDM)); 1950 (txdesc->rate_mode == RATE_MODE_OFDM));
1933 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1951 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1934 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1952 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1935 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1953 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1936 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 1954 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
@@ -1962,13 +1980,14 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1962 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1980 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1963 unsigned int beacon_base; 1981 unsigned int beacon_base;
1964 unsigned int padding_len; 1982 unsigned int padding_len;
1965 u32 reg; 1983 u32 orig_reg, reg;
1966 1984
1967 /* 1985 /*
1968 * Disable beaconing while we are reloading the beacon data, 1986 * Disable beaconing while we are reloading the beacon data,
1969 * otherwise we might be sending out invalid data. 1987 * otherwise we might be sending out invalid data.
1970 */ 1988 */
1971 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg); 1989 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1990 orig_reg = reg;
1972 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1991 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1973 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 1992 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1974 1993
@@ -1986,7 +2005,14 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
1986 * Write entire beacon with descriptor and padding to register. 2005 * Write entire beacon with descriptor and padding to register.
1987 */ 2006 */
1988 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 2007 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1989 skb_pad(entry->skb, padding_len); 2008 if (padding_len && skb_pad(entry->skb, padding_len)) {
2009 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
2010 /* skb freed by skb_pad() on failure */
2011 entry->skb = NULL;
2012 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
2013 return;
2014 }
2015
1990 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 2016 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1991 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base, 2017 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1992 entry_priv->desc, TXINFO_SIZE); 2018 entry_priv->desc, TXINFO_SIZE);
@@ -2002,8 +2028,6 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
2002 */ 2028 */
2003 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 2029 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
2004 2030
2005 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
2006 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
2007 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 2031 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2008 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg); 2032 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2009 2033
@@ -2014,6 +2038,32 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
2014 entry->skb = NULL; 2038 entry->skb = NULL;
2015} 2039}
2016 2040
2041static void rt61pci_clear_beacon(struct queue_entry *entry)
2042{
2043 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2044 u32 reg;
2045
2046 /*
2047 * Disable beaconing while we are reloading the beacon data,
2048 * otherwise we might be sending out invalid data.
2049 */
2050 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2051 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2052 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2053
2054 /*
2055 * Clear beacon.
2056 */
2057 rt2x00pci_register_write(rt2x00dev,
2058 HW_BEACON_OFFSET(entry->entry_idx), 0);
2059
2060 /*
2061 * Enable beaconing again.
2062 */
2063 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
2064 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2065}
2066
2017/* 2067/*
2018 * RX control handlers 2068 * RX control handlers
2019 */ 2069 */
@@ -2078,9 +2128,8 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
2078 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 2128 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2079 2129
2080 /* 2130 /*
2081 * FIXME: Legacy driver indicates that the frame does 2131 * The hardware has already checked the Michael Mic and has
2082 * contain the Michael Mic. Unfortunately, in rt2x00 2132 * stripped it from the frame. Signal this to mac80211.
2083 * the MIC seems to be missing completely...
2084 */ 2133 */
2085 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; 2134 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2086 2135
@@ -2143,7 +2192,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2143 * queue identication number. 2192 * queue identication number.
2144 */ 2193 */
2145 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); 2194 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2146 queue = rt2x00queue_get_queue(rt2x00dev, type); 2195 queue = rt2x00queue_get_tx_queue(rt2x00dev, type);
2147 if (unlikely(!queue)) 2196 if (unlikely(!queue))
2148 continue; 2197 continue;
2149 2198
@@ -2211,61 +2260,77 @@ static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2211 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); 2260 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2212} 2261}
2213 2262
2214static irqreturn_t rt61pci_interrupt_thread(int irq, void *dev_instance) 2263static void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
2264 struct rt2x00_field32 irq_field)
2215{ 2265{
2216 struct rt2x00_dev *rt2x00dev = dev_instance; 2266 u32 reg;
2217 u32 reg = rt2x00dev->irqvalue[0];
2218 u32 reg_mcu = rt2x00dev->irqvalue[1];
2219 2267
2220 /* 2268 /*
2221 * Handle interrupts, walk through all bits 2269 * Enable a single interrupt. The interrupt mask register
2222 * and run the tasks, the bits are checked in order of 2270 * access needs locking.
2223 * priority.
2224 */ 2271 */
2272 spin_lock_irq(&rt2x00dev->irqmask_lock);
2225 2273
2226 /* 2274 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2227 * 1 - Rx ring done interrupt. 2275 rt2x00_set_field32(&reg, irq_field, 0);
2228 */ 2276 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2229 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2230 rt2x00pci_rxdone(rt2x00dev);
2231 2277
2232 /* 2278 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2233 * 2 - Tx ring done interrupt. 2279}
2234 */
2235 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2236 rt61pci_txdone(rt2x00dev);
2237 2280
2238 /* 2281static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev,
2239 * 3 - Handle MCU command done. 2282 struct rt2x00_field32 irq_field)
2240 */ 2283{
2241 if (reg_mcu) 2284 u32 reg;
2242 rt2x00pci_register_write(rt2x00dev,
2243 M2H_CMD_DONE_CSR, 0xffffffff);
2244 2285
2245 /* 2286 /*
2246 * 4 - MCU Autowakeup interrupt. 2287 * Enable a single MCU interrupt. The interrupt mask register
2288 * access needs locking.
2247 */ 2289 */
2248 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP)) 2290 spin_lock_irq(&rt2x00dev->irqmask_lock);
2249 rt61pci_wakeup(rt2x00dev);
2250 2291
2251 /* 2292 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2252 * 5 - Beacon done interrupt. 2293 rt2x00_set_field32(&reg, irq_field, 0);
2253 */ 2294 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2254 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2255 rt2x00lib_beacondone(rt2x00dev);
2256 2295
2257 /* Enable interrupts again. */ 2296 spin_unlock_irq(&rt2x00dev->irqmask_lock);
2258 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 2297}
2259 STATE_RADIO_IRQ_ON_ISR); 2298
2260 return IRQ_HANDLED; 2299static void rt61pci_txstatus_tasklet(unsigned long data)
2300{
2301 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2302 rt61pci_txdone(rt2x00dev);
2303 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE);
2304}
2305
2306static void rt61pci_tbtt_tasklet(unsigned long data)
2307{
2308 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2309 rt2x00lib_beacondone(rt2x00dev);
2310 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE);
2311}
2312
2313static void rt61pci_rxdone_tasklet(unsigned long data)
2314{
2315 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2316 rt2x00pci_rxdone(rt2x00dev);
2317 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE);
2261} 2318}
2262 2319
2320static void rt61pci_autowake_tasklet(unsigned long data)
2321{
2322 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
2323 rt61pci_wakeup(rt2x00dev);
2324 rt2x00pci_register_write(rt2x00dev,
2325 M2H_CMD_DONE_CSR, 0xffffffff);
2326 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP);
2327}
2263 2328
2264static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) 2329static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2265{ 2330{
2266 struct rt2x00_dev *rt2x00dev = dev_instance; 2331 struct rt2x00_dev *rt2x00dev = dev_instance;
2267 u32 reg_mcu; 2332 u32 reg_mcu, mask_mcu;
2268 u32 reg; 2333 u32 reg, mask;
2269 2334
2270 /* 2335 /*
2271 * Get the interrupt sources & saved to local variable. 2336 * Get the interrupt sources & saved to local variable.
@@ -2283,14 +2348,46 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2283 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) 2348 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2284 return IRQ_HANDLED; 2349 return IRQ_HANDLED;
2285 2350
2286 /* Store irqvalues for use in the interrupt thread. */ 2351 /*
2287 rt2x00dev->irqvalue[0] = reg; 2352 * Schedule tasklets for interrupt handling.
2288 rt2x00dev->irqvalue[1] = reg_mcu; 2353 */
2354 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2355 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
2356
2357 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2358 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
2359
2360 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE))
2361 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
2362
2363 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2364 tasklet_schedule(&rt2x00dev->autowake_tasklet);
2365
2366 /*
2367 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
2368 * for interrupts and interrupt masks we can just use the value of
2369 * INT_SOURCE_CSR to create the interrupt mask.
2370 */
2371 mask = reg;
2372 mask_mcu = reg_mcu;
2289 2373
2290 /* Disable interrupts, will be enabled again in the interrupt thread. */ 2374 /*
2291 rt2x00dev->ops->lib->set_device_state(rt2x00dev, 2375 * Disable all interrupts for which a tasklet was scheduled right now,
2292 STATE_RADIO_IRQ_OFF_ISR); 2376 * the tasklet will reenable the appropriate interrupts.
2293 return IRQ_WAKE_THREAD; 2377 */
2378 spin_lock(&rt2x00dev->irqmask_lock);
2379
2380 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
2381 reg |= mask;
2382 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
2383
2384 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
2385 reg |= mask_mcu;
2386 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
2387
2388 spin_unlock(&rt2x00dev->irqmask_lock);
2389
2390 return IRQ_HANDLED;
2294} 2391}
2295 2392
2296/* 2393/*
@@ -2819,7 +2916,7 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2819 if (queue_idx >= 4) 2916 if (queue_idx >= 4)
2820 return 0; 2917 return 0;
2821 2918
2822 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 2919 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2823 2920
2824 /* Update WMM TXOP register */ 2921 /* Update WMM TXOP register */
2825 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); 2922 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
@@ -2884,7 +2981,10 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
2884 2981
2885static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { 2982static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2886 .irq_handler = rt61pci_interrupt, 2983 .irq_handler = rt61pci_interrupt,
2887 .irq_handler_thread = rt61pci_interrupt_thread, 2984 .txstatus_tasklet = rt61pci_txstatus_tasklet,
2985 .tbtt_tasklet = rt61pci_tbtt_tasklet,
2986 .rxdone_tasklet = rt61pci_rxdone_tasklet,
2987 .autowake_tasklet = rt61pci_autowake_tasklet,
2888 .probe_hw = rt61pci_probe_hw, 2988 .probe_hw = rt61pci_probe_hw,
2889 .get_firmware_name = rt61pci_get_firmware_name, 2989 .get_firmware_name = rt61pci_get_firmware_name,
2890 .check_firmware = rt61pci_check_firmware, 2990 .check_firmware = rt61pci_check_firmware,
@@ -2903,6 +3003,7 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2903 .stop_queue = rt61pci_stop_queue, 3003 .stop_queue = rt61pci_stop_queue,
2904 .write_tx_desc = rt61pci_write_tx_desc, 3004 .write_tx_desc = rt61pci_write_tx_desc,
2905 .write_beacon = rt61pci_write_beacon, 3005 .write_beacon = rt61pci_write_beacon,
3006 .clear_beacon = rt61pci_clear_beacon,
2906 .fill_rxdone = rt61pci_fill_rxdone, 3007 .fill_rxdone = rt61pci_fill_rxdone,
2907 .config_shared_key = rt61pci_config_shared_key, 3008 .config_shared_key = rt61pci_config_shared_key,
2908 .config_pairwise_key = rt61pci_config_pairwise_key, 3009 .config_pairwise_key = rt61pci_config_pairwise_key,
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index 029be3c6c030..02f1148c577e 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -502,26 +502,14 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
502 struct rt2x00intf_conf *conf, 502 struct rt2x00intf_conf *conf,
503 const unsigned int flags) 503 const unsigned int flags)
504{ 504{
505 unsigned int beacon_base;
506 u32 reg; 505 u32 reg;
507 506
508 if (flags & CONFIG_UPDATE_TYPE) { 507 if (flags & CONFIG_UPDATE_TYPE) {
509 /* 508 /*
510 * Clear current synchronisation setup.
511 * For the Beacon base registers we only need to clear
512 * the first byte since that byte contains the VALID and OWNER
513 * bits which (when set to 0) will invalidate the entire beacon.
514 */
515 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
516 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
517
518 /*
519 * Enable synchronisation. 509 * Enable synchronisation.
520 */ 510 */
521 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 511 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
522 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
523 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 512 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
524 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
525 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 513 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
526 } 514 }
527 515
@@ -1440,9 +1428,7 @@ static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1440 rt73usb_disable_radio(rt2x00dev); 1428 rt73usb_disable_radio(rt2x00dev);
1441 break; 1429 break;
1442 case STATE_RADIO_IRQ_ON: 1430 case STATE_RADIO_IRQ_ON:
1443 case STATE_RADIO_IRQ_ON_ISR:
1444 case STATE_RADIO_IRQ_OFF: 1431 case STATE_RADIO_IRQ_OFF:
1445 case STATE_RADIO_IRQ_OFF_ISR:
1446 /* No support, but no error either */ 1432 /* No support, but no error either */
1447 break; 1433 break;
1448 case STATE_DEEP_SLEEP: 1434 case STATE_DEEP_SLEEP:
@@ -1488,7 +1474,7 @@ static void rt73usb_write_tx_desc(struct queue_entry *entry,
1488 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); 1474 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1489 rt2x00_set_field32(&word, TXD_W0_OFDM, 1475 rt2x00_set_field32(&word, TXD_W0_OFDM,
1490 (txdesc->rate_mode == RATE_MODE_OFDM)); 1476 (txdesc->rate_mode == RATE_MODE_OFDM));
1491 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1477 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1492 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1478 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1493 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1479 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1494 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 1480 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
@@ -1513,10 +1499,12 @@ static void rt73usb_write_tx_desc(struct queue_entry *entry,
1513 rt2x00_desc_write(txd, 1, word); 1499 rt2x00_desc_write(txd, 1, word);
1514 1500
1515 rt2x00_desc_read(txd, 2, &word); 1501 rt2x00_desc_read(txd, 2, &word);
1516 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal); 1502 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal);
1517 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service); 1503 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service);
1518 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low); 1504 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW,
1519 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high); 1505 txdesc->u.plcp.length_low);
1506 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH,
1507 txdesc->u.plcp.length_high);
1520 rt2x00_desc_write(txd, 2, word); 1508 rt2x00_desc_write(txd, 2, word);
1521 1509
1522 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1510 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
@@ -1547,13 +1535,14 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1547 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1535 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1548 unsigned int beacon_base; 1536 unsigned int beacon_base;
1549 unsigned int padding_len; 1537 unsigned int padding_len;
1550 u32 reg; 1538 u32 orig_reg, reg;
1551 1539
1552 /* 1540 /*
1553 * Disable beaconing while we are reloading the beacon data, 1541 * Disable beaconing while we are reloading the beacon data,
1554 * otherwise we might be sending out invalid data. 1542 * otherwise we might be sending out invalid data.
1555 */ 1543 */
1556 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1544 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1545 orig_reg = reg;
1557 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1546 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1558 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1547 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1559 1548
@@ -1577,7 +1566,14 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1577 * Write entire beacon with descriptor and padding to register. 1566 * Write entire beacon with descriptor and padding to register.
1578 */ 1567 */
1579 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 1568 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1580 skb_pad(entry->skb, padding_len); 1569 if (padding_len && skb_pad(entry->skb, padding_len)) {
1570 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
1571 /* skb freed by skb_pad() on failure */
1572 entry->skb = NULL;
1573 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, orig_reg);
1574 return;
1575 }
1576
1581 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 1577 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1582 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data, 1578 rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1583 entry->skb->len + padding_len); 1579 entry->skb->len + padding_len);
@@ -1590,8 +1586,6 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1590 */ 1586 */
1591 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 1587 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1592 1588
1593 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1594 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1595 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 1589 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1596 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1590 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1597 1591
@@ -1602,6 +1596,33 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
1602 entry->skb = NULL; 1596 entry->skb = NULL;
1603} 1597}
1604 1598
1599static void rt73usb_clear_beacon(struct queue_entry *entry)
1600{
1601 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1602 unsigned int beacon_base;
1603 u32 reg;
1604
1605 /*
1606 * Disable beaconing while we are reloading the beacon data,
1607 * otherwise we might be sending out invalid data.
1608 */
1609 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1610 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1611 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1612
1613 /*
1614 * Clear beacon.
1615 */
1616 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1617 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
1618
1619 /*
1620 * Enable beaconing again.
1621 */
1622 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1623 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1624}
1625
1605static int rt73usb_get_tx_data_len(struct queue_entry *entry) 1626static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1606{ 1627{
1607 int length; 1628 int length;
@@ -1698,9 +1719,8 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry,
1698 rxdesc->flags |= RX_FLAG_IV_STRIPPED; 1719 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1699 1720
1700 /* 1721 /*
1701 * FIXME: Legacy driver indicates that the frame does 1722 * The hardware has already checked the Michael Mic and has
1702 * contain the Michael Mic. Unfortunately, in rt2x00 1723 * stripped it from the frame. Signal this to mac80211.
1703 * the MIC seems to be missing completely...
1704 */ 1724 */
1705 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; 1725 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
1706 1726
@@ -2229,7 +2249,7 @@ static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2229 if (queue_idx >= 4) 2249 if (queue_idx >= 4)
2230 return 0; 2250 return 0;
2231 2251
2232 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 2252 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
2233 2253
2234 /* Update WMM TXOP register */ 2254 /* Update WMM TXOP register */
2235 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2))); 2255 offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
@@ -2313,6 +2333,7 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2313 .flush_queue = rt2x00usb_flush_queue, 2333 .flush_queue = rt2x00usb_flush_queue,
2314 .write_tx_desc = rt73usb_write_tx_desc, 2334 .write_tx_desc = rt73usb_write_tx_desc,
2315 .write_beacon = rt73usb_write_beacon, 2335 .write_beacon = rt73usb_write_beacon,
2336 .clear_beacon = rt73usb_clear_beacon,
2316 .get_tx_data_len = rt73usb_get_tx_data_len, 2337 .get_tx_data_len = rt73usb_get_tx_data_len,
2317 .fill_rxdone = rt73usb_fill_rxdone, 2338 .fill_rxdone = rt73usb_fill_rxdone,
2318 .config_shared_key = rt73usb_config_shared_key, 2339 .config_shared_key = rt73usb_config_shared_key,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 01:12:23 -0500