aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/rt2x00
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c4
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c4
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c9
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h108
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c467
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c31
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c76
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h29
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c14
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c6
10 files changed, 547 insertions, 201 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 5f5204b82891..cdbf59108ef9 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -526,6 +526,10 @@ static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
526 526
527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1); 527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
528 rt2x00pci_register_write(rt2x00dev, CSR20, reg); 528 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
529 } else {
530 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
531 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
532 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
529 } 533 }
530 534
531 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 535 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index 2a73f593aab0..89e986f449da 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -574,6 +574,10 @@ static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
574 574
575 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1); 575 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
576 rt2x00pci_register_write(rt2x00dev, CSR20, reg); 576 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
577 } else {
578 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
579 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
580 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
577 } 581 }
578 582
579 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 583 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index 8ebb705fe106..7185cb05f257 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -649,6 +649,10 @@ static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev,
649 649
650 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1); 650 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1);
651 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); 651 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
652 } else {
653 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
654 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
655 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
652 } 656 }
653 657
654 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 658 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
@@ -1644,11 +1648,6 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1644 unsigned int i; 1648 unsigned int i;
1645 1649
1646 /* 1650 /*
1647 * Disable powersaving as default.
1648 */
1649 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1650
1651 /*
1652 * Initialize all hw fields. 1651 * Initialize all hw fields.
1653 */ 1652 */
1654 rt2x00dev->hw->flags = 1653 rt2x00dev->hw->flags =
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 74c0433dba37..ec893721cc80 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -56,15 +56,20 @@
56#define RF3021 0x0007 56#define RF3021 0x0007
57#define RF3022 0x0008 57#define RF3022 0x0008
58#define RF3052 0x0009 58#define RF3052 0x0009
59#define RF3320 0x000b
59 60
60/* 61/*
61 * Chipset version. 62 * Chipset revisions.
62 */ 63 */
63#define RT2860C_VERSION 0x0100 64#define REV_RT2860C 0x0100
64#define RT2860D_VERSION 0x0101 65#define REV_RT2860D 0x0101
65#define RT2880E_VERSION 0x0200 66#define REV_RT2870D 0x0101
66#define RT2883_VERSION 0x0300 67#define REV_RT2872E 0x0200
67#define RT3070_VERSION 0x0200 68#define REV_RT3070E 0x0200
69#define REV_RT3070F 0x0201
70#define REV_RT3071E 0x0211
71#define REV_RT3090E 0x0211
72#define REV_RT3390E 0x0211
68 73
69/* 74/*
70 * Signal information. 75 * Signal information.
@@ -90,10 +95,16 @@
90#define NUM_TX_QUEUES 4 95#define NUM_TX_QUEUES 4
91 96
92/* 97/*
93 * USB registers. 98 * Registers.
94 */ 99 */
95 100
96/* 101/*
102 * OPT_14: Unknown register used by rt3xxx devices.
103 */
104#define OPT_14_CSR 0x0114
105#define OPT_14_CSR_BIT0 FIELD32(0x00000001)
106
107/*
97 * INT_SOURCE_CSR: Interrupt source register. 108 * INT_SOURCE_CSR: Interrupt source register.
98 * Write one to clear corresponding bit. 109 * Write one to clear corresponding bit.
99 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c 110 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
@@ -398,6 +409,31 @@
398#define EFUSE_DATA3 0x059c 409#define EFUSE_DATA3 0x059c
399 410
400/* 411/*
412 * LDO_CFG0
413 */
414#define LDO_CFG0 0x05d4
415#define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
416#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
417#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
418#define LDO_CFG0_BGSEL FIELD32(0x03000000)
419#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
420#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
421#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
422
423/*
424 * GPIO_SWITCH
425 */
426#define GPIO_SWITCH 0x05dc
427#define GPIO_SWITCH_0 FIELD32(0x00000001)
428#define GPIO_SWITCH_1 FIELD32(0x00000002)
429#define GPIO_SWITCH_2 FIELD32(0x00000004)
430#define GPIO_SWITCH_3 FIELD32(0x00000008)
431#define GPIO_SWITCH_4 FIELD32(0x00000010)
432#define GPIO_SWITCH_5 FIELD32(0x00000020)
433#define GPIO_SWITCH_6 FIELD32(0x00000040)
434#define GPIO_SWITCH_7 FIELD32(0x00000080)
435
436/*
401 * MAC Control/Status Registers(CSR). 437 * MAC Control/Status Registers(CSR).
402 * Some values are set in TU, whereas 1 TU == 1024 us. 438 * Some values are set in TU, whereas 1 TU == 1024 us.
403 */ 439 */
@@ -1492,14 +1528,32 @@ struct mac_iveiv_entry {
1492#define BBP4_BANDWIDTH FIELD8(0x18) 1528#define BBP4_BANDWIDTH FIELD8(0x18)
1493 1529
1494/* 1530/*
1531 * BBP 138: Unknown
1532 */
1533#define BBP138_RX_ADC1 FIELD8(0x02)
1534#define BBP138_RX_ADC2 FIELD8(0x04)
1535#define BBP138_TX_DAC1 FIELD8(0x20)
1536#define BBP138_TX_DAC2 FIELD8(0x40)
1537
1538/*
1495 * RFCSR registers 1539 * RFCSR registers
1496 * The wordsize of the RFCSR is 8 bits. 1540 * The wordsize of the RFCSR is 8 bits.
1497 */ 1541 */
1498 1542
1499/* 1543/*
1544 * RFCSR 1:
1545 */
1546#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1547#define RFCSR1_RX0_PD FIELD8(0x04)
1548#define RFCSR1_TX0_PD FIELD8(0x08)
1549#define RFCSR1_RX1_PD FIELD8(0x10)
1550#define RFCSR1_TX1_PD FIELD8(0x20)
1551
1552/*
1500 * RFCSR 6: 1553 * RFCSR 6:
1501 */ 1554 */
1502#define RFCSR6_R FIELD8(0x03) 1555#define RFCSR6_R1 FIELD8(0x03)
1556#define RFCSR6_R2 FIELD8(0x40)
1503 1557
1504/* 1558/*
1505 * RFCSR 7: 1559 * RFCSR 7:
@@ -1512,6 +1566,28 @@ struct mac_iveiv_entry {
1512#define RFCSR12_TX_POWER FIELD8(0x1f) 1566#define RFCSR12_TX_POWER FIELD8(0x1f)
1513 1567
1514/* 1568/*
1569 * RFCSR 15:
1570 */
1571#define RFCSR15_TX_LO2_EN FIELD8(0x08)
1572
1573/*
1574 * RFCSR 17:
1575 */
1576#define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1577#define RFCSR17_TX_LO1_EN FIELD8(0x08)
1578#define RFCSR17_R FIELD8(0x20)
1579
1580/*
1581 * RFCSR 20:
1582 */
1583#define RFCSR20_RX_LO1_EN FIELD8(0x08)
1584
1585/*
1586 * RFCSR 21:
1587 */
1588#define RFCSR21_RX_LO2_EN FIELD8(0x08)
1589
1590/*
1515 * RFCSR 22: 1591 * RFCSR 22:
1516 */ 1592 */
1517#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) 1593#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
@@ -1522,6 +1598,14 @@ struct mac_iveiv_entry {
1522#define RFCSR23_FREQ_OFFSET FIELD8(0x7f) 1598#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1523 1599
1524/* 1600/*
1601 * RFCSR 27:
1602 */
1603#define RFCSR27_R1 FIELD8(0x03)
1604#define RFCSR27_R2 FIELD8(0x04)
1605#define RFCSR27_R3 FIELD8(0x30)
1606#define RFCSR27_R4 FIELD8(0x40)
1607
1608/*
1525 * RFCSR 30: 1609 * RFCSR 30:
1526 */ 1610 */
1527#define RFCSR30_RF_CALIBRATION FIELD8(0x80) 1611#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
@@ -1603,6 +1687,8 @@ struct mac_iveiv_entry {
1603#define EEPROM_NIC_WPS_PBC FIELD16(0x0080) 1687#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1604#define EEPROM_NIC_BW40M_BG FIELD16(0x0100) 1688#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1605#define EEPROM_NIC_BW40M_A FIELD16(0x0200) 1689#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1690#define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800)
1691#define EEPROM_NIC_DAC_TEST FIELD16(0x8000)
1606 1692
1607/* 1693/*
1608 * EEPROM frequency 1694 * EEPROM frequency
@@ -1659,6 +1745,12 @@ struct mac_iveiv_entry {
1659#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) 1745#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1660 1746
1661/* 1747/*
1748 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
1749 */
1750#define EEPROM_TXMIXER_GAIN_BG 0x0024
1751#define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
1752
1753/*
1662 * EEPROM RSSI A offset 1754 * EEPROM RSSI A offset
1663 */ 1755 */
1664#define EEPROM_RSSI_A 0x0025 1756#define EEPROM_RSSI_A 0x0025
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index c015ce9fdd09..2648f315a934 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -360,11 +360,6 @@ static int rt2800_blink_set(struct led_classdev *led_cdev,
360 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg); 360 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
361 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on); 361 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
362 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off); 362 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
363 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
364 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
365 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
366 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
367 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
368 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 363 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
369 364
370 return 0; 365 return 0;
@@ -610,10 +605,6 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
610{ 605{
611 u32 reg; 606 u32 reg;
612 607
613 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
614 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
615 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
616
617 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 608 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
618 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 609 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
619 !!erp->short_preamble); 610 !!erp->short_preamble);
@@ -632,15 +623,12 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
632 623
633 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); 624 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
634 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); 625 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
635 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
636 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 626 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
637 627
638 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); 628 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
639 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs); 629 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
640 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs); 630 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
641 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
642 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs); 631 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
643 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
644 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 632 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
645 633
646 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 634 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
@@ -718,10 +706,10 @@ static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
718 rt2x00dev->lna_gain = lna_gain; 706 rt2x00dev->lna_gain = lna_gain;
719} 707}
720 708
721static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev, 709static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
722 struct ieee80211_conf *conf, 710 struct ieee80211_conf *conf,
723 struct rf_channel *rf, 711 struct rf_channel *rf,
724 struct channel_info *info) 712 struct channel_info *info)
725{ 713{
726 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 714 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
727 715
@@ -787,10 +775,10 @@ static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
787 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 775 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
788} 776}
789 777
790static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev, 778static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
791 struct ieee80211_conf *conf, 779 struct ieee80211_conf *conf,
792 struct rf_channel *rf, 780 struct rf_channel *rf,
793 struct channel_info *info) 781 struct channel_info *info)
794{ 782{
795 u8 rfcsr; 783 u8 rfcsr;
796 784
@@ -798,7 +786,7 @@ static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
798 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 786 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
799 787
800 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 788 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
801 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2); 789 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
802 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 790 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
803 791
804 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 792 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
@@ -827,15 +815,13 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
827 unsigned int tx_pin; 815 unsigned int tx_pin;
828 u8 bbp; 816 u8 bbp;
829 817
830 if ((rt2x00_rt(rt2x00dev, RT3070) || 818 if (rt2x00_rf(rt2x00dev, RF2020) ||
831 rt2x00_rt(rt2x00dev, RT3090)) && 819 rt2x00_rf(rt2x00dev, RF3020) ||
832 (rt2x00_rf(rt2x00dev, RF2020) || 820 rt2x00_rf(rt2x00dev, RF3021) ||
833 rt2x00_rf(rt2x00dev, RF3020) || 821 rt2x00_rf(rt2x00dev, RF3022))
834 rt2x00_rf(rt2x00dev, RF3021) || 822 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
835 rt2x00_rf(rt2x00dev, RF3022)))
836 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
837 else 823 else
838 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info); 824 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
839 825
840 /* 826 /*
841 * Change BBP settings 827 * Change BBP settings
@@ -899,8 +885,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
899 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf)); 885 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
900 rt2800_bbp_write(rt2x00dev, 3, bbp); 886 rt2800_bbp_write(rt2x00dev, 3, bbp);
901 887
902 if (rt2x00_rt(rt2x00dev, RT2860) && 888 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
903 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
904 if (conf_is_ht40(conf)) { 889 if (conf_is_ht40(conf)) {
905 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 890 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
906 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 891 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
@@ -988,10 +973,6 @@ static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
988 libconf->conf->short_frame_max_tx_count); 973 libconf->conf->short_frame_max_tx_count);
989 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 974 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
990 libconf->conf->long_frame_max_tx_count); 975 libconf->conf->long_frame_max_tx_count);
991 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
992 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
993 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
994 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
995 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 976 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
996} 977}
997 978
@@ -1015,13 +996,13 @@ static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1015 996
1016 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 997 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1017 } else { 998 } else {
1018 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1019
1020 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); 999 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1021 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 1000 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1022 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 1001 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1023 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0); 1002 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1024 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 1003 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1004
1005 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1025 } 1006 }
1026} 1007}
1027 1008
@@ -1062,9 +1043,10 @@ EXPORT_SYMBOL_GPL(rt2800_link_stats);
1062static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 1043static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1063{ 1044{
1064 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 1045 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1065 if (rt2x00_is_usb(rt2x00dev) && 1046 if (rt2x00_rt(rt2x00dev, RT3070) ||
1066 rt2x00_rt(rt2x00dev, RT3070) && 1047 rt2x00_rt(rt2x00dev, RT3071) ||
1067 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) 1048 rt2x00_rt(rt2x00dev, RT3090) ||
1049 rt2x00_rt(rt2x00dev, RT3390))
1068 return 0x1c + (2 * rt2x00dev->lna_gain); 1050 return 0x1c + (2 * rt2x00dev->lna_gain);
1069 else 1051 else
1070 return 0x2e + rt2x00dev->lna_gain; 1052 return 0x2e + rt2x00dev->lna_gain;
@@ -1095,8 +1077,7 @@ EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1095void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 1077void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1096 const u32 count) 1078 const u32 count)
1097{ 1079{
1098 if (rt2x00_rt(rt2x00dev, RT2860) && 1080 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1099 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION))
1100 return; 1081 return;
1101 1082
1102 /* 1083 /*
@@ -1114,8 +1095,17 @@ EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1114int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 1095int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1115{ 1096{
1116 u32 reg; 1097 u32 reg;
1098 u16 eeprom;
1117 unsigned int i; 1099 unsigned int i;
1118 1100
1101 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1102 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1103 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1104 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1105 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1106 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1107 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1108
1119 if (rt2x00_is_usb(rt2x00dev)) { 1109 if (rt2x00_is_usb(rt2x00dev)) {
1120 /* 1110 /*
1121 * Wait until BBP and RF are ready. 1111 * Wait until BBP and RF are ready.
@@ -1135,8 +1125,25 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1135 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 1125 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1136 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 1126 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1137 reg & ~0x00002000); 1127 reg & ~0x00002000);
1138 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) 1128 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1129 /*
1130 * Reset DMA indexes
1131 */
1132 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1133 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1134 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1135 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1136 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1137 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1138 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1139 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1140 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1141
1142 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1143 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1144
1139 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1145 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1146 }
1140 1147
1141 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 1148 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1142 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 1149 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
@@ -1181,12 +1188,42 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1181 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 1188 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1182 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1189 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1183 1190
1184 if (rt2x00_is_usb(rt2x00dev) && 1191 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1185 rt2x00_rt(rt2x00dev, RT3070) && 1192
1186 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) { 1193 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1194 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1195 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1196 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1197
1198 if (rt2x00_rt(rt2x00dev, RT3071) ||
1199 rt2x00_rt(rt2x00dev, RT3090) ||
1200 rt2x00_rt(rt2x00dev, RT3390)) {
1187 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 1201 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1188 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 1202 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1189 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 1203 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1204 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1205 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1206 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1207 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1208 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1209 0x0000002c);
1210 else
1211 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1212 0x0000000f);
1213 } else {
1214 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1215 }
1216 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1217 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1218 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1219
1220 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1221 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1222 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1223 } else {
1224 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1225 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1226 }
1190 } else { 1227 } else {
1191 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 1228 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1192 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 1229 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -1205,19 +1242,15 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1205 1242
1206 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg); 1243 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1207 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 1244 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1245 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1208 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 1246 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1209 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 1247 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1210 1248
1211 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg); 1249 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1212 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 1250 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1213 if ((rt2x00_rt(rt2x00dev, RT2872) && 1251 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1214 (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION)) ||
1215 rt2x00_rt(rt2x00dev, RT2880) ||
1216 rt2x00_rt(rt2x00dev, RT2883) || 1252 rt2x00_rt(rt2x00dev, RT2883) ||
1217 rt2x00_rt(rt2x00dev, RT2890) || 1253 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1218 rt2x00_rt(rt2x00dev, RT3052) ||
1219 (rt2x00_rt(rt2x00dev, RT3070) &&
1220 (rt2x00_rev(rt2x00dev) < RT3070_VERSION)))
1221 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2); 1254 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1222 else 1255 else
1223 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1); 1256 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
@@ -1225,38 +1258,61 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1225 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0); 1258 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1226 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1259 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1227 1260
1261 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1262 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1263 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1264 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1265 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1266 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1267 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1268 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1269 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1270
1228 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 1271 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1229 1272
1273 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1274 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1275 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1276 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1277 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1278 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1279 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1280 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1281
1230 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 1282 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1231 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1); 1283 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1284 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1232 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0); 1285 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1233 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0); 1286 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1287 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1234 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 1288 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1235 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 1289 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1236 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1290 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1237 1291
1238 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 1292 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1239 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8); 1293 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1240 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0); 1294 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1241 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1); 1295 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1242 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1296 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1243 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1297 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1244 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1298 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1245 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1299 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1246 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1300 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1247 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1301 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1302 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1248 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 1303 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1249 1304
1250 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 1305 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1251 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8); 1306 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1252 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0); 1307 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1253 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1); 1308 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1254 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1309 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1255 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1310 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1256 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1311 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1257 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1312 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1258 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1313 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1259 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1314 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1315 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1260 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1316 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1261 1317
1262 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 1318 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
@@ -1269,11 +1325,13 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1269 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1325 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1270 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1326 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1271 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1327 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1328 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1272 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1329 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1273 1330
1274 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 1331 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1275 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 1332 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1276 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0); 1333 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1334 !rt2x00_is_usb(rt2x00dev));
1277 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1); 1335 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1278 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1336 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1279 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1337 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
@@ -1281,6 +1339,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1281 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1339 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1282 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1340 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1283 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1341 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1342 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1284 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1343 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1285 1344
1286 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 1345 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
@@ -1293,6 +1352,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1293 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1352 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1294 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1353 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1295 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1354 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1355 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1296 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1356 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1297 1357
1298 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 1358 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
@@ -1305,6 +1365,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1305 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1365 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1306 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1366 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1307 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1367 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1368 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1308 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1369 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1309 1370
1310 if (rt2x00_is_usb(rt2x00dev)) { 1371 if (rt2x00_is_usb(rt2x00dev)) {
@@ -1334,6 +1395,15 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1334 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 1395 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1335 1396
1336 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 1397 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1398
1399 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1400 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 32);
1401 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 32);
1402 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1403 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1404 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1405 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1406
1337 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1407 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1338 1408
1339 /* 1409 /*
@@ -1483,38 +1553,67 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1483 1553
1484 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 1554 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1485 rt2800_bbp_write(rt2x00dev, 66, 0x38); 1555 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1486 rt2800_bbp_write(rt2x00dev, 69, 0x12); 1556
1557 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1558 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1559 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1560 } else {
1561 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1562 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1563 }
1564
1487 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1565 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1488 rt2800_bbp_write(rt2x00dev, 73, 0x10); 1566
1489 rt2800_bbp_write(rt2x00dev, 81, 0x37); 1567 if (rt2x00_rt(rt2x00dev, RT3070) ||
1568 rt2x00_rt(rt2x00dev, RT3071) ||
1569 rt2x00_rt(rt2x00dev, RT3090) ||
1570 rt2x00_rt(rt2x00dev, RT3390)) {
1571 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1572 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1573 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1574 } else {
1575 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1576 }
1577
1490 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1578 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1491 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 1579 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1492 rt2800_bbp_write(rt2x00dev, 84, 0x99); 1580
1581 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1582 rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1583 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1584 else
1585 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1586
1493 rt2800_bbp_write(rt2x00dev, 86, 0x00); 1587 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1494 rt2800_bbp_write(rt2x00dev, 91, 0x04); 1588 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1495 rt2800_bbp_write(rt2x00dev, 92, 0x00); 1589 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1496 rt2800_bbp_write(rt2x00dev, 103, 0x00); 1590
1591 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1592 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1593 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1594 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
1595 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1596 else
1597 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1598
1497 rt2800_bbp_write(rt2x00dev, 105, 0x05); 1599 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1600 rt2800_bbp_write(rt2x00dev, 106, 0x35);
1498 1601
1499 if (rt2x00_rt(rt2x00dev, RT2860) && 1602 if (rt2x00_rt(rt2x00dev, RT3071) ||
1500 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) { 1603 rt2x00_rt(rt2x00dev, RT3090) ||
1501 rt2800_bbp_write(rt2x00dev, 69, 0x16); 1604 rt2x00_rt(rt2x00dev, RT3390)) {
1502 rt2800_bbp_write(rt2x00dev, 73, 0x12); 1605 rt2800_bbp_read(rt2x00dev, 138, &value);
1503 }
1504 1606
1505 if (rt2x00_rt(rt2x00dev, RT2860) && 1607 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1506 (rt2x00_rev(rt2x00dev) > RT2860D_VERSION)) 1608 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1507 rt2800_bbp_write(rt2x00dev, 84, 0x19); 1609 value |= 0x20;
1610 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1611 value &= ~0x02;
1508 1612
1509 if (rt2x00_is_usb(rt2x00dev) && 1613 rt2800_bbp_write(rt2x00dev, 138, value);
1510 rt2x00_rt(rt2x00dev, RT3070) &&
1511 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1512 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1513 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1514 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1515 } 1614 }
1516 1615
1517 if (rt2x00_rt(rt2x00dev, RT3052)) { 1616 if (rt2x00_rt(rt2x00dev, RT2872)) {
1518 rt2800_bbp_write(rt2x00dev, 31, 0x08); 1617 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1519 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 1618 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1520 rt2800_bbp_write(rt2x00dev, 80, 0x08); 1619 rt2800_bbp_write(rt2x00dev, 80, 0x08);
@@ -1598,19 +1697,15 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1598{ 1697{
1599 u8 rfcsr; 1698 u8 rfcsr;
1600 u8 bbp; 1699 u8 bbp;
1700 u32 reg;
1701 u16 eeprom;
1601 1702
1602 if (rt2x00_is_usb(rt2x00dev) && 1703 if (!rt2x00_rt(rt2x00dev, RT3070) &&
1603 rt2x00_rt(rt2x00dev, RT3070) && 1704 !rt2x00_rt(rt2x00dev, RT3071) &&
1604 (rt2x00_rev(rt2x00dev) != RT3070_VERSION)) 1705 !rt2x00_rt(rt2x00dev, RT3090) &&
1706 !rt2x00_rt(rt2x00dev, RT3390))
1605 return 0; 1707 return 0;
1606 1708
1607 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1608 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1609 !rt2x00_rf(rt2x00dev, RF3021) &&
1610 !rt2x00_rf(rt2x00dev, RF3022))
1611 return 0;
1612 }
1613
1614 /* 1709 /*
1615 * Init RF calibration. 1710 * Init RF calibration.
1616 */ 1711 */
@@ -1621,13 +1716,15 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1621 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 1716 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1622 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1717 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1623 1718
1624 if (rt2x00_is_usb(rt2x00dev)) { 1719 if (rt2x00_rt(rt2x00dev, RT3070) ||
1720 rt2x00_rt(rt2x00dev, RT3071) ||
1721 rt2x00_rt(rt2x00dev, RT3090)) {
1625 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1722 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1626 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1723 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1627 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1724 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1628 rt2800_rfcsr_write(rt2x00dev, 7, 0x70); 1725 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1629 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1726 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1630 rt2800_rfcsr_write(rt2x00dev, 10, 0x71); 1727 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1631 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1728 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1632 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 1729 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1633 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1730 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
@@ -1640,48 +1737,88 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1640 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1737 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1641 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 1738 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1642 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1739 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1643 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1644 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 1740 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1645 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) { 1741 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1646 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 1742 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1647 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 1743 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1648 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 1744 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1649 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 1745 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1650 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1746 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1651 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1747 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1652 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1748 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1653 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 1749 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1654 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 1750 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1655 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1751 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1656 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 1752 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1657 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1753 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1658 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 1754 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1659 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 1755 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1660 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1756 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1661 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 1757 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1662 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 1758 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1663 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 1759 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1664 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 1760 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1665 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 1761 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1666 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 1762 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1667 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1763 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1668 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 1764 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1669 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 1765 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1670 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 1766 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1671 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1767 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1672 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 1768 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1673 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 1769 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1674 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 1770 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1675 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 1771 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1772 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1773 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
1774 }
1775
1776 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1777 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1778 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1779 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1780 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1781 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1782 rt2x00_rt(rt2x00dev, RT3090)) {
1783 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1784 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1785 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1786
1787 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1788
1789 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1790 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1791 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1792 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1793 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1794 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1795 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1796 else
1797 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1798 }
1799 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1800 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1801 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1802 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1803 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1676 } 1804 }
1677 1805
1678 /* 1806 /*
1679 * Set RX Filter calibration for 20MHz and 40MHz 1807 * Set RX Filter calibration for 20MHz and 40MHz
1680 */ 1808 */
1681 rt2x00dev->calibration[0] = 1809 if (rt2x00_rt(rt2x00dev, RT3070)) {
1682 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); 1810 rt2x00dev->calibration[0] =
1683 rt2x00dev->calibration[1] = 1811 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1684 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 1812 rt2x00dev->calibration[1] =
1813 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1814 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1815 rt2x00_rt(rt2x00dev, RT3090) ||
1816 rt2x00_rt(rt2x00dev, RT3390)) {
1817 rt2x00dev->calibration[0] =
1818 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1819 rt2x00dev->calibration[1] =
1820 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
1821 }
1685 1822
1686 /* 1823 /*
1687 * Set back to initial state 1824 * Set back to initial state
@@ -1699,6 +1836,81 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1699 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 1836 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1700 rt2800_bbp_write(rt2x00dev, 4, bbp); 1837 rt2800_bbp_write(rt2x00dev, 4, bbp);
1701 1838
1839 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1840 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1841 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1842 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
1843 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1844
1845 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1846 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1847 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1848
1849 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1850 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1851 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1852 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1853 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1854 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1855 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1856 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1857 }
1858 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1859 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1860 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1861 rt2x00_get_field16(eeprom,
1862 EEPROM_TXMIXER_GAIN_BG_VAL));
1863 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1864
1865 if (rt2x00_rt(rt2x00dev, RT3090)) {
1866 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1867
1868 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1869 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1870 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1871 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1872 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1873
1874 rt2800_bbp_write(rt2x00dev, 138, bbp);
1875 }
1876
1877 if (rt2x00_rt(rt2x00dev, RT3071) ||
1878 rt2x00_rt(rt2x00dev, RT3090) ||
1879 rt2x00_rt(rt2x00dev, RT3390)) {
1880 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1881 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1882 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1883 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1884 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1885 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1886 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1887
1888 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1889 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1890 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1891
1892 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1893 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1894 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1895
1896 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1897 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1898 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1899 }
1900
1901 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
1902 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
1903 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1904 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
1905 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1906 else
1907 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1908 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1909 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1910 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1911 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1912 }
1913
1702 return 0; 1914 return 0;
1703} 1915}
1704EXPORT_SYMBOL_GPL(rt2800_init_rfcsr); 1916EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
@@ -1775,9 +1987,7 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1775 } else if (rt2x00_rt(rt2x00dev, RT2860) || 1987 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1776 rt2x00_rt(rt2x00dev, RT2870) || 1988 rt2x00_rt(rt2x00dev, RT2870) ||
1777 rt2x00_rt(rt2x00dev, RT2872) || 1989 rt2x00_rt(rt2x00dev, RT2872) ||
1778 rt2x00_rt(rt2x00dev, RT2880) || 1990 rt2x00_rt(rt2x00dev, RT2872)) {
1779 (rt2x00_rt(rt2x00dev, RT2883) &&
1780 (rt2x00_rev(rt2x00dev) < RT2883_VERSION))) {
1781 /* 1991 /*
1782 * There is a max of 2 RX streams for RT28x0 series 1992 * There is a max of 2 RX streams for RT28x0 series
1783 */ 1993 */
@@ -1882,10 +2092,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1882 if (!rt2x00_rt(rt2x00dev, RT2860) && 2092 if (!rt2x00_rt(rt2x00dev, RT2860) &&
1883 !rt2x00_rt(rt2x00dev, RT2870) && 2093 !rt2x00_rt(rt2x00dev, RT2870) &&
1884 !rt2x00_rt(rt2x00dev, RT2872) && 2094 !rt2x00_rt(rt2x00dev, RT2872) &&
1885 !rt2x00_rt(rt2x00dev, RT2880) &&
1886 !rt2x00_rt(rt2x00dev, RT2883) && 2095 !rt2x00_rt(rt2x00dev, RT2883) &&
1887 !rt2x00_rt(rt2x00dev, RT2890) &&
1888 !rt2x00_rt(rt2x00dev, RT3052) &&
1889 !rt2x00_rt(rt2x00dev, RT3070) && 2096 !rt2x00_rt(rt2x00dev, RT3070) &&
1890 !rt2x00_rt(rt2x00dev, RT3071) && 2097 !rt2x00_rt(rt2x00dev, RT3071) &&
1891 !rt2x00_rt(rt2x00dev, RT3090) && 2098 !rt2x00_rt(rt2x00dev, RT3090) &&
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index b1f5643f83fc..2131f8f0c502 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -60,6 +60,12 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
60 unsigned int i; 60 unsigned int i;
61 u32 reg; 61 u32 reg;
62 62
63 /*
64 * SOC devices don't support MCU requests.
65 */
66 if (rt2x00_is_soc(rt2x00dev))
67 return;
68
63 for (i = 0; i < 200; i++) { 69 for (i = 0; i < 200; i++) {
64 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 70 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
65 71
@@ -341,19 +347,6 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
341 struct queue_entry_priv_pci *entry_priv; 347 struct queue_entry_priv_pci *entry_priv;
342 u32 reg; 348 u32 reg;
343 349
344 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
345 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
346 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
347 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
348 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
349 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
350 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
351 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
352 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
353
354 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
355 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
356
357 /* 350 /*
358 * Initialize registers. 351 * Initialize registers.
359 */ 352 */
@@ -1009,6 +1002,14 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
1009 } 1002 }
1010} 1003}
1011 1004
1005static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
1006{
1007 struct ieee80211_conf conf = { .flags = 0 };
1008 struct rt2x00lib_conf libconf = { .conf = &conf };
1009
1010 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
1011}
1012
1012static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance) 1013static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1013{ 1014{
1014 struct rt2x00_dev *rt2x00dev = dev_instance; 1015 struct rt2x00_dev *rt2x00dev = dev_instance;
@@ -1033,6 +1034,9 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1033 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) 1034 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1034 rt2800pci_txdone(rt2x00dev); 1035 rt2800pci_txdone(rt2x00dev);
1035 1036
1037 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
1038 rt2800pci_wakeup(rt2x00dev);
1039
1036 return IRQ_HANDLED; 1040 return IRQ_HANDLED;
1037} 1041}
1038 1042
@@ -1212,6 +1216,7 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1212 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1216 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1213 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1217 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1214 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1218 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1219 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1215#endif 1220#endif
1216 { 0, } 1221 { 0, }
1217}; 1222};
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index d27d7d5d850c..6b809ab42c61 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -876,6 +876,8 @@ static struct usb_device_id rt2800usb_device_table[] = {
876 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) }, 876 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
877 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) }, 877 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
878 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) }, 878 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
879 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
880 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
879 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) }, 881 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
880 /* SMC */ 882 /* SMC */
881 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) }, 883 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -905,8 +907,13 @@ static struct usb_device_id rt2800usb_device_table[] = {
905 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) }, 907 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
906 /* AirTies */ 908 /* AirTies */
907 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) }, 909 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
910 /* ASUS */
911 { USB_DEVICE(0x0b05, 0x1784), USB_DEVICE_DATA(&rt2800usb_ops) },
908 /* AzureWave */ 912 /* AzureWave */
909 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) }, 913 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
914 { USB_DEVICE(0x13d3, 0x3305), USB_DEVICE_DATA(&rt2800usb_ops) },
915 { USB_DEVICE(0x13d3, 0x3307), USB_DEVICE_DATA(&rt2800usb_ops) },
916 { USB_DEVICE(0x13d3, 0x3321), USB_DEVICE_DATA(&rt2800usb_ops) },
910 /* Conceptronic */ 917 /* Conceptronic */
911 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) }, 918 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
912 /* Corega */ 919 /* Corega */
@@ -916,20 +923,46 @@ static struct usb_device_id rt2800usb_device_table[] = {
916 { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) }, 923 { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
917 { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) }, 924 { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
918 { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) }, 925 { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
926 { USB_DEVICE(0x07d1, 0x3c16), USB_DEVICE_DATA(&rt2800usb_ops) },
927 /* Draytek */
928 { USB_DEVICE(0x07fa, 0x7712), USB_DEVICE_DATA(&rt2800usb_ops) },
919 /* Edimax */ 929 /* Edimax */
920 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) }, 930 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
921 /* Encore */ 931 /* Encore */
922 { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) }, 932 { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
933 { USB_DEVICE(0x203d, 0x14a9), USB_DEVICE_DATA(&rt2800usb_ops) },
923 /* EnGenius */ 934 /* EnGenius */
924 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) }, 935 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
925 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) }, 936 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
926 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) }, 937 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
938 { USB_DEVICE(0x1740, 0x9707), USB_DEVICE_DATA(&rt2800usb_ops) },
939 { USB_DEVICE(0x1740, 0x9708), USB_DEVICE_DATA(&rt2800usb_ops) },
940 { USB_DEVICE(0x1740, 0x9709), USB_DEVICE_DATA(&rt2800usb_ops) },
927 /* Gigabyte */ 941 /* Gigabyte */
928 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) }, 942 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
929 /* I-O DATA */ 943 /* I-O DATA */
930 { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) }, 944 { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
945 { USB_DEVICE(0x04bb, 0x0947), USB_DEVICE_DATA(&rt2800usb_ops) },
946 { USB_DEVICE(0x04bb, 0x0948), USB_DEVICE_DATA(&rt2800usb_ops) },
947 /* Logitec */
948 { USB_DEVICE(0x0789, 0x0166), USB_DEVICE_DATA(&rt2800usb_ops) },
931 /* MSI */ 949 /* MSI */
932 { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) }, 950 { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
951 { USB_DEVICE(0x0db0, 0x3821), USB_DEVICE_DATA(&rt2800usb_ops) },
952 { USB_DEVICE(0x0db0, 0x3822), USB_DEVICE_DATA(&rt2800usb_ops) },
953 { USB_DEVICE(0x0db0, 0x3870), USB_DEVICE_DATA(&rt2800usb_ops) },
954 { USB_DEVICE(0x0db0, 0x3871), USB_DEVICE_DATA(&rt2800usb_ops) },
955 { USB_DEVICE(0x0db0, 0x821a), USB_DEVICE_DATA(&rt2800usb_ops) },
956 { USB_DEVICE(0x0db0, 0x822a), USB_DEVICE_DATA(&rt2800usb_ops) },
957 { USB_DEVICE(0x0db0, 0x822b), USB_DEVICE_DATA(&rt2800usb_ops) },
958 { USB_DEVICE(0x0db0, 0x822c), USB_DEVICE_DATA(&rt2800usb_ops) },
959 { USB_DEVICE(0x0db0, 0x870a), USB_DEVICE_DATA(&rt2800usb_ops) },
960 { USB_DEVICE(0x0db0, 0x871a), USB_DEVICE_DATA(&rt2800usb_ops) },
961 { USB_DEVICE(0x0db0, 0x871b), USB_DEVICE_DATA(&rt2800usb_ops) },
962 { USB_DEVICE(0x0db0, 0x871c), USB_DEVICE_DATA(&rt2800usb_ops) },
963 { USB_DEVICE(0x0db0, 0x899a), USB_DEVICE_DATA(&rt2800usb_ops) },
964 /* Para */
965 { USB_DEVICE(0x20b8, 0x8888), USB_DEVICE_DATA(&rt2800usb_ops) },
933 /* Pegatron */ 966 /* Pegatron */
934 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) }, 967 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
935 { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) }, 968 { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -944,9 +977,15 @@ static struct usb_device_id rt2800usb_device_table[] = {
944 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) }, 977 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
945 /* Sitecom */ 978 /* Sitecom */
946 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) }, 979 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
980 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
947 { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) }, 981 { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
982 { USB_DEVICE(0x0df6, 0x0047), USB_DEVICE_DATA(&rt2800usb_ops) },
983 { USB_DEVICE(0x0df6, 0x0048), USB_DEVICE_DATA(&rt2800usb_ops) },
948 /* SMC */ 984 /* SMC */
949 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) }, 985 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
986 { USB_DEVICE(0x083a, 0xa701), USB_DEVICE_DATA(&rt2800usb_ops) },
987 { USB_DEVICE(0x083a, 0xa702), USB_DEVICE_DATA(&rt2800usb_ops) },
988 { USB_DEVICE(0x083a, 0xa703), USB_DEVICE_DATA(&rt2800usb_ops) },
950 /* Zinwell */ 989 /* Zinwell */
951 { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) }, 990 { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
952 { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) }, 991 { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -966,6 +1005,7 @@ static struct usb_device_id rt2800usb_device_table[] = {
966 { USB_DEVICE(0x148f, 0x8070), USB_DEVICE_DATA(&rt2800usb_ops) }, 1005 { USB_DEVICE(0x148f, 0x8070), USB_DEVICE_DATA(&rt2800usb_ops) },
967 /* Sitecom */ 1006 /* Sitecom */
968 { USB_DEVICE(0x0df6, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) }, 1007 { USB_DEVICE(0x0df6, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) },
1008 { USB_DEVICE(0x0df6, 0x0050), USB_DEVICE_DATA(&rt2800usb_ops) },
969 /* Zinwell */ 1009 /* Zinwell */
970 { USB_DEVICE(0x5a57, 0x0284), USB_DEVICE_DATA(&rt2800usb_ops) }, 1010 { USB_DEVICE(0x5a57, 0x0284), USB_DEVICE_DATA(&rt2800usb_ops) },
971#endif 1011#endif
@@ -985,18 +1025,14 @@ static struct usb_device_id rt2800usb_device_table[] = {
985 /* Amigo */ 1025 /* Amigo */
986 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) }, 1026 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
987 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) }, 1027 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
988 /* Askey */
989 { USB_DEVICE(0x0930, 0x0a07), USB_DEVICE_DATA(&rt2800usb_ops) },
990 /* ASUS */ 1028 /* ASUS */
991 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) }, 1029 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
992 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) }, 1030 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
993 { USB_DEVICE(0x0b05, 0x1784), USB_DEVICE_DATA(&rt2800usb_ops) },
994 { USB_DEVICE(0x0b05, 0x1790), USB_DEVICE_DATA(&rt2800usb_ops) }, 1031 { USB_DEVICE(0x0b05, 0x1790), USB_DEVICE_DATA(&rt2800usb_ops) },
995 { USB_DEVICE(0x1761, 0x0b05), USB_DEVICE_DATA(&rt2800usb_ops) }, 1032 { USB_DEVICE(0x1761, 0x0b05), USB_DEVICE_DATA(&rt2800usb_ops) },
996 /* AzureWave */ 1033 /* AzureWave */
997 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) }, 1034 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
998 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) }, 1035 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
999 { USB_DEVICE(0x13d3, 0x3305), USB_DEVICE_DATA(&rt2800usb_ops) },
1000 /* Belkin */ 1036 /* Belkin */
1001 { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) }, 1037 { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
1002 /* Buffalo */ 1038 /* Buffalo */
@@ -1015,14 +1051,8 @@ static struct usb_device_id rt2800usb_device_table[] = {
1015 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) }, 1051 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
1016 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) }, 1052 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
1017 { USB_DEVICE(0x07d1, 0x3c15), USB_DEVICE_DATA(&rt2800usb_ops) }, 1053 { USB_DEVICE(0x07d1, 0x3c15), USB_DEVICE_DATA(&rt2800usb_ops) },
1018 { USB_DEVICE(0x07d1, 0x3c16), USB_DEVICE_DATA(&rt2800usb_ops) },
1019 /* Encore */ 1054 /* Encore */
1020 { USB_DEVICE(0x203d, 0x14a1), USB_DEVICE_DATA(&rt2800usb_ops) }, 1055 { USB_DEVICE(0x203d, 0x14a1), USB_DEVICE_DATA(&rt2800usb_ops) },
1021 { USB_DEVICE(0x203d, 0x14a9), USB_DEVICE_DATA(&rt2800usb_ops) },
1022 /* EnGenius */
1023 { USB_DEVICE(0x1740, 0x9707), USB_DEVICE_DATA(&rt2800usb_ops) },
1024 { USB_DEVICE(0x1740, 0x9708), USB_DEVICE_DATA(&rt2800usb_ops) },
1025 { USB_DEVICE(0x1740, 0x9709), USB_DEVICE_DATA(&rt2800usb_ops) },
1026 /* Gemtek */ 1056 /* Gemtek */
1027 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) }, 1057 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
1028 /* Gigabyte */ 1058 /* Gigabyte */
@@ -1030,9 +1060,6 @@ static struct usb_device_id rt2800usb_device_table[] = {
1030 /* Hawking */ 1060 /* Hawking */
1031 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) }, 1061 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
1032 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) }, 1062 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
1033 /* I-O DATA */
1034 { USB_DEVICE(0x04bb, 0x0947), USB_DEVICE_DATA(&rt2800usb_ops) },
1035 { USB_DEVICE(0x04bb, 0x0948), USB_DEVICE_DATA(&rt2800usb_ops) },
1036 /* LevelOne */ 1063 /* LevelOne */
1037 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) }, 1064 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
1038 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) }, 1065 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -1042,20 +1069,8 @@ static struct usb_device_id rt2800usb_device_table[] = {
1042 { USB_DEVICE(0x1737, 0x0079), USB_DEVICE_DATA(&rt2800usb_ops) }, 1069 { USB_DEVICE(0x1737, 0x0079), USB_DEVICE_DATA(&rt2800usb_ops) },
1043 /* Motorola */ 1070 /* Motorola */
1044 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) }, 1071 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
1045 /* MSI */
1046 { USB_DEVICE(0x0db0, 0x3821), USB_DEVICE_DATA(&rt2800usb_ops) },
1047 { USB_DEVICE(0x0db0, 0x3822), USB_DEVICE_DATA(&rt2800usb_ops) },
1048 { USB_DEVICE(0x0db0, 0x3870), USB_DEVICE_DATA(&rt2800usb_ops) },
1049 { USB_DEVICE(0x0db0, 0x3871), USB_DEVICE_DATA(&rt2800usb_ops) },
1050 { USB_DEVICE(0x0db0, 0x821a), USB_DEVICE_DATA(&rt2800usb_ops) },
1051 { USB_DEVICE(0x0db0, 0x822a), USB_DEVICE_DATA(&rt2800usb_ops) },
1052 { USB_DEVICE(0x0db0, 0x870a), USB_DEVICE_DATA(&rt2800usb_ops) },
1053 { USB_DEVICE(0x0db0, 0x871a), USB_DEVICE_DATA(&rt2800usb_ops) },
1054 { USB_DEVICE(0x0db0, 0x899a), USB_DEVICE_DATA(&rt2800usb_ops) },
1055 /* Ovislink */ 1072 /* Ovislink */
1056 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) }, 1073 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
1057 /* Para */
1058 { USB_DEVICE(0x20b8, 0x8888), USB_DEVICE_DATA(&rt2800usb_ops) },
1059 /* Pegatron */ 1074 /* Pegatron */
1060 { USB_DEVICE(0x05a6, 0x0101), USB_DEVICE_DATA(&rt2800usb_ops) }, 1075 { USB_DEVICE(0x05a6, 0x0101), USB_DEVICE_DATA(&rt2800usb_ops) },
1061 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) }, 1076 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -1064,19 +1079,8 @@ static struct usb_device_id rt2800usb_device_table[] = {
1064 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) }, 1079 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
1065 /* Qcom */ 1080 /* Qcom */
1066 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) }, 1081 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
1067 /* Sitecom */
1068 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
1069 { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
1070 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
1071 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
1072 { USB_DEVICE(0x0df6, 0x0047), USB_DEVICE_DATA(&rt2800usb_ops) },
1073 { USB_DEVICE(0x0df6, 0x0048), USB_DEVICE_DATA(&rt2800usb_ops) },
1074 { USB_DEVICE(0x0df6, 0x004a), USB_DEVICE_DATA(&rt2800usb_ops) },
1075 { USB_DEVICE(0x0df6, 0x004d), USB_DEVICE_DATA(&rt2800usb_ops) },
1076 /* SMC */ 1082 /* SMC */
1077 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) }, 1083 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
1078 { USB_DEVICE(0x083a, 0xa701), USB_DEVICE_DATA(&rt2800usb_ops) },
1079 { USB_DEVICE(0x083a, 0xa702), USB_DEVICE_DATA(&rt2800usb_ops) },
1080 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) }, 1084 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
1081 { USB_DEVICE(0x083a, 0xd522), USB_DEVICE_DATA(&rt2800usb_ops) }, 1085 { USB_DEVICE(0x083a, 0xd522), USB_DEVICE_DATA(&rt2800usb_ops) },
1082 /* Sweex */ 1086 /* Sweex */
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index d9daa9c406fa..4de505b98331 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -177,16 +177,15 @@ struct rt2x00_chip {
177#define RT2573 0x2573 177#define RT2573 0x2573
178#define RT2860 0x2860 /* 2.4GHz PCI/CB */ 178#define RT2860 0x2860 /* 2.4GHz PCI/CB */
179#define RT2870 0x2870 179#define RT2870 0x2870
180#define RT2872 0x2872 180#define RT2872 0x2872 /* WSOC */
181#define RT2880 0x2880 /* WSOC */
182#define RT2883 0x2883 /* WSOC */ 181#define RT2883 0x2883 /* WSOC */
183#define RT2890 0x2890 /* 2.4GHz PCIe */
184#define RT3052 0x3052 /* WSOC */
185#define RT3070 0x3070 182#define RT3070 0x3070
186#define RT3071 0x3071 183#define RT3071 0x3071
187#define RT3090 0x3090 /* 2.4GHz PCIe */ 184#define RT3090 0x3090 /* 2.4GHz PCIe */
188#define RT3390 0x3390 185#define RT3390 0x3390
189#define RT3572 0x3572 186#define RT3572 0x3572
187#define RT3593 0x3593 /* PCIe */
188#define RT3883 0x3883 /* WSOC */
190 189
191 u16 rf; 190 u16 rf;
192 u16 rev; 191 u16 rev;
@@ -930,12 +929,12 @@ static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev,
930 rt2x00dev->chip.rt, rt2x00dev->chip.rf, rt2x00dev->chip.rev); 929 rt2x00dev->chip.rt, rt2x00dev->chip.rf, rt2x00dev->chip.rev);
931} 930}
932 931
933static inline char rt2x00_rt(struct rt2x00_dev *rt2x00dev, const u16 rt) 932static inline bool rt2x00_rt(struct rt2x00_dev *rt2x00dev, const u16 rt)
934{ 933{
935 return (rt2x00dev->chip.rt == rt); 934 return (rt2x00dev->chip.rt == rt);
936} 935}
937 936
938static inline char rt2x00_rf(struct rt2x00_dev *rt2x00dev, const u16 rf) 937static inline bool rt2x00_rf(struct rt2x00_dev *rt2x00dev, const u16 rf)
939{ 938{
940 return (rt2x00dev->chip.rf == rf); 939 return (rt2x00dev->chip.rf == rf);
941} 940}
@@ -945,6 +944,24 @@ static inline u16 rt2x00_rev(struct rt2x00_dev *rt2x00dev)
945 return rt2x00dev->chip.rev; 944 return rt2x00dev->chip.rev;
946} 945}
947 946
947static inline bool rt2x00_rt_rev(struct rt2x00_dev *rt2x00dev,
948 const u16 rt, const u16 rev)
949{
950 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) == rev);
951}
952
953static inline bool rt2x00_rt_rev_lt(struct rt2x00_dev *rt2x00dev,
954 const u16 rt, const u16 rev)
955{
956 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) < rev);
957}
958
959static inline bool rt2x00_rt_rev_gte(struct rt2x00_dev *rt2x00dev,
960 const u16 rt, const u16 rev)
961{
962 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) >= rev);
963}
964
948static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev, 965static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev,
949 enum rt2x00_chip_intf intf) 966 enum rt2x00_chip_intf intf)
950{ 967{
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 432e75f960b7..b9885981f3a8 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -2118,6 +2118,14 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2118 } 2118 }
2119} 2119}
2120 2120
2121static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2122{
2123 struct ieee80211_conf conf = { .flags = 0 };
2124 struct rt2x00lib_conf libconf = { .conf = &conf };
2125
2126 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2127}
2128
2121static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) 2129static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2122{ 2130{
2123 struct rt2x00_dev *rt2x00dev = dev_instance; 2131 struct rt2x00_dev *rt2x00dev = dev_instance;
@@ -2165,6 +2173,12 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2165 rt2x00pci_register_write(rt2x00dev, 2173 rt2x00pci_register_write(rt2x00dev,
2166 M2H_CMD_DONE_CSR, 0xffffffff); 2174 M2H_CMD_DONE_CSR, 0xffffffff);
2167 2175
2176 /*
2177 * 4 - MCU Autowakeup interrupt.
2178 */
2179 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2180 rt61pci_wakeup(rt2x00dev);
2181
2168 return IRQ_HANDLED; 2182 return IRQ_HANDLED;
2169} 2183}
2170 2184
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index bb58d797fb72..576ea9dd2824 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -861,15 +861,15 @@ static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
861 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, 861 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
862 USB_MODE_SLEEP, REGISTER_TIMEOUT); 862 USB_MODE_SLEEP, REGISTER_TIMEOUT);
863 } else { 863 } else {
864 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
865 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
866
867 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg); 864 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
868 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0); 865 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
869 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); 866 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
870 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0); 867 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
871 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0); 868 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
872 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); 869 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
870
871 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
872 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
873 } 873 }
874} 874}
875 875
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 00:51:39 -0500