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Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c125
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c125
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c151
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h8
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00leds.c6
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00mac.c3
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c25
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.h18
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.c14
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h22
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c113
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.h136
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c161
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c433
14 files changed, 686 insertions, 654 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 78fca1bcc544..6a977679124d 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -49,20 +49,10 @@
49 * the access attempt is considered to have failed, 49 * the access attempt is considered to have failed,
50 * and we will print an error. 50 * and we will print an error.
51 */ 51 */
52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev) 52#define WAIT_FOR_BBP(__dev, __reg) \
53{ 53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 u32 reg; 54#define WAIT_FOR_RF(__dev, __reg) \
55 unsigned int i; 55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66 56
67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev, 57static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value) 58 const unsigned int word, const u8 value)
@@ -72,31 +62,20 @@ static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
72 mutex_lock(&rt2x00dev->csr_mutex); 62 mutex_lock(&rt2x00dev->csr_mutex);
73 63
74 /* 64 /*
75 * Wait until the BBP becomes ready. 65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
76 */ 67 */
77 reg = rt2400pci_bbp_check(rt2x00dev); 68 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) 69 reg = 0;
79 goto exit_fail; 70 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
80 71 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
81 /* 72 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
82 * Write the data into the BBP. 73 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
83 */ 74
84 reg = 0; 75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); 76 }
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91
92 mutex_unlock(&rt2x00dev->csr_mutex);
93
94 return;
95 77
96exit_fail:
97 mutex_unlock(&rt2x00dev->csr_mutex); 78 mutex_unlock(&rt2x00dev->csr_mutex);
98
99 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
100} 79}
101 80
102static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev, 81static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
@@ -107,75 +86,55 @@ static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
107 mutex_lock(&rt2x00dev->csr_mutex); 86 mutex_lock(&rt2x00dev->csr_mutex);
108 87
109 /* 88 /*
110 * Wait until the BBP becomes ready. 89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
111 */ 95 */
112 reg = rt2400pci_bbp_check(rt2x00dev); 96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
113 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) 97 reg = 0;
114 goto exit_fail; 98 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
115 101
116 /* 102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
117 * Write the request into the BBP.
118 */
119 reg = 0;
120 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
121 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
122 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
123 103
124 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); 104 WAIT_FOR_BBP(rt2x00dev, &reg);
125 105 }
126 /*
127 * Wait until the BBP becomes ready.
128 */
129 reg = rt2400pci_bbp_check(rt2x00dev);
130 if (rt2x00_get_field32(reg, BBPCSR_BUSY))
131 goto exit_fail;
132 106
133 *value = rt2x00_get_field32(reg, BBPCSR_VALUE); 107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
134 108
135 mutex_unlock(&rt2x00dev->csr_mutex); 109 mutex_unlock(&rt2x00dev->csr_mutex);
136
137 return;
138
139exit_fail:
140 mutex_unlock(&rt2x00dev->csr_mutex);
141
142 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
143 *value = 0xff;
144} 110}
145 111
146static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev, 112static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
147 const unsigned int word, const u32 value) 113 const unsigned int word, const u32 value)
148{ 114{
149 u32 reg; 115 u32 reg;
150 unsigned int i;
151 116
152 if (!word) 117 if (!word)
153 return; 118 return;
154 119
155 mutex_lock(&rt2x00dev->csr_mutex); 120 mutex_lock(&rt2x00dev->csr_mutex);
156 121
157 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 122 /*
158 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg); 123 * Wait until the RF becomes available, afterwards we
159 if (!rt2x00_get_field32(reg, RFCSR_BUSY)) 124 * can safely write the new data into the register.
160 goto rf_write; 125 */
161 udelay(REGISTER_BUSY_DELAY); 126 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
127 reg = 0;
128 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
129 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
130 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
131 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
132
133 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
134 rt2x00_rf_write(rt2x00dev, word, value);
162 } 135 }
163 136
164 mutex_unlock(&rt2x00dev->csr_mutex); 137 mutex_unlock(&rt2x00dev->csr_mutex);
165 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
166 return;
167
168rf_write:
169 reg = 0;
170 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
171 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
172 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
173 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
174
175 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
176 rt2x00_rf_write(rt2x00dev, word, value);
177
178 mutex_unlock(&rt2x00dev->csr_mutex);
179} 138}
180 139
181static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 140static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index 972b5a5c3864..d3bc218ec85c 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -49,20 +49,10 @@
49 * the access attempt is considered to have failed, 49 * the access attempt is considered to have failed,
50 * and we will print an error. 50 * and we will print an error.
51 */ 51 */
52static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev) 52#define WAIT_FOR_BBP(__dev, __reg) \
53{ 53 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
54 u32 reg; 54#define WAIT_FOR_RF(__dev, __reg) \
55 unsigned int i; 55 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66 56
67static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev, 57static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68 const unsigned int word, const u8 value) 58 const unsigned int word, const u8 value)
@@ -72,31 +62,20 @@ static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
72 mutex_lock(&rt2x00dev->csr_mutex); 62 mutex_lock(&rt2x00dev->csr_mutex);
73 63
74 /* 64 /*
75 * Wait until the BBP becomes ready. 65 * Wait until the BBP becomes available, afterwards we
66 * can safely write the new data into the register.
76 */ 67 */
77 reg = rt2500pci_bbp_check(rt2x00dev); 68 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
78 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) 69 reg = 0;
79 goto exit_fail; 70 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
80 71 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
81 /* 72 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
82 * Write the data into the BBP. 73 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
83 */ 74
84 reg = 0; 75 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value); 76 }
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91
92 mutex_unlock(&rt2x00dev->csr_mutex);
93
94 return;
95 77
96exit_fail:
97 mutex_unlock(&rt2x00dev->csr_mutex); 78 mutex_unlock(&rt2x00dev->csr_mutex);
98
99 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
100} 79}
101 80
102static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev, 81static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
@@ -107,75 +86,55 @@ static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
107 mutex_lock(&rt2x00dev->csr_mutex); 86 mutex_lock(&rt2x00dev->csr_mutex);
108 87
109 /* 88 /*
110 * Wait until the BBP becomes ready. 89 * Wait until the BBP becomes available, afterwards we
90 * can safely write the read request into the register.
91 * After the data has been written, we wait until hardware
92 * returns the correct value, if at any time the register
93 * doesn't become available in time, reg will be 0xffffffff
94 * which means we return 0xff to the caller.
111 */ 95 */
112 reg = rt2500pci_bbp_check(rt2x00dev); 96 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
113 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) 97 reg = 0;
114 goto exit_fail; 98 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
99 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
100 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
115 101
116 /* 102 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
117 * Write the request into the BBP.
118 */
119 reg = 0;
120 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
121 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
122 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
123 103
124 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg); 104 WAIT_FOR_BBP(rt2x00dev, &reg);
125 105 }
126 /*
127 * Wait until the BBP becomes ready.
128 */
129 reg = rt2500pci_bbp_check(rt2x00dev);
130 if (rt2x00_get_field32(reg, BBPCSR_BUSY))
131 goto exit_fail;
132 106
133 *value = rt2x00_get_field32(reg, BBPCSR_VALUE); 107 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
134 108
135 mutex_unlock(&rt2x00dev->csr_mutex); 109 mutex_unlock(&rt2x00dev->csr_mutex);
136
137 return;
138
139exit_fail:
140 mutex_unlock(&rt2x00dev->csr_mutex);
141
142 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
143 *value = 0xff;
144} 110}
145 111
146static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev, 112static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
147 const unsigned int word, const u32 value) 113 const unsigned int word, const u32 value)
148{ 114{
149 u32 reg; 115 u32 reg;
150 unsigned int i;
151 116
152 if (!word) 117 if (!word)
153 return; 118 return;
154 119
155 mutex_lock(&rt2x00dev->csr_mutex); 120 mutex_lock(&rt2x00dev->csr_mutex);
156 121
157 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 122 /*
158 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg); 123 * Wait until the RF becomes available, afterwards we
159 if (!rt2x00_get_field32(reg, RFCSR_BUSY)) 124 * can safely write the new data into the register.
160 goto rf_write; 125 */
161 udelay(REGISTER_BUSY_DELAY); 126 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
127 reg = 0;
128 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
129 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
130 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
131 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
132
133 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
134 rt2x00_rf_write(rt2x00dev, word, value);
162 } 135 }
163 136
164 mutex_unlock(&rt2x00dev->csr_mutex); 137 mutex_unlock(&rt2x00dev->csr_mutex);
165 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
166 return;
167
168rf_write:
169 reg = 0;
170 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
171 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
172 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
173 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
174
175 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
176 rt2x00_rf_write(rt2x00dev, word, value);
177
178 mutex_unlock(&rt2x00dev->csr_mutex);
179} 138}
180 139
181static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom) 140static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index e6bae4ae4c47..0447e93306ad 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -57,7 +57,7 @@ static inline void rt2500usb_register_read(struct rt2x00_dev *rt2x00dev,
57 __le16 reg; 57 __le16 reg;
58 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ, 58 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
59 USB_VENDOR_REQUEST_IN, offset, 59 USB_VENDOR_REQUEST_IN, offset,
60 &reg, sizeof(u16), REGISTER_TIMEOUT); 60 &reg, sizeof(reg), REGISTER_TIMEOUT);
61 *value = le16_to_cpu(reg); 61 *value = le16_to_cpu(reg);
62} 62}
63 63
@@ -68,7 +68,7 @@ static inline void rt2500usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
68 __le16 reg; 68 __le16 reg;
69 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ, 69 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
70 USB_VENDOR_REQUEST_IN, offset, 70 USB_VENDOR_REQUEST_IN, offset,
71 &reg, sizeof(u16), REGISTER_TIMEOUT); 71 &reg, sizeof(reg), REGISTER_TIMEOUT);
72 *value = le16_to_cpu(reg); 72 *value = le16_to_cpu(reg);
73} 73}
74 74
@@ -89,7 +89,7 @@ static inline void rt2500usb_register_write(struct rt2x00_dev *rt2x00dev,
89 __le16 reg = cpu_to_le16(value); 89 __le16 reg = cpu_to_le16(value);
90 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE, 90 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
91 USB_VENDOR_REQUEST_OUT, offset, 91 USB_VENDOR_REQUEST_OUT, offset,
92 &reg, sizeof(u16), REGISTER_TIMEOUT); 92 &reg, sizeof(reg), REGISTER_TIMEOUT);
93} 93}
94 94
95static inline void rt2500usb_register_write_lock(struct rt2x00_dev *rt2x00dev, 95static inline void rt2500usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
@@ -99,7 +99,7 @@ static inline void rt2500usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
99 __le16 reg = cpu_to_le16(value); 99 __le16 reg = cpu_to_le16(value);
100 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE, 100 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
101 USB_VENDOR_REQUEST_OUT, offset, 101 USB_VENDOR_REQUEST_OUT, offset,
102 &reg, sizeof(u16), REGISTER_TIMEOUT); 102 &reg, sizeof(reg), REGISTER_TIMEOUT);
103} 103}
104 104
105static inline void rt2500usb_register_multiwrite(struct rt2x00_dev *rt2x00dev, 105static inline void rt2500usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
@@ -112,21 +112,32 @@ static inline void rt2500usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
112 REGISTER_TIMEOUT16(length)); 112 REGISTER_TIMEOUT16(length));
113} 113}
114 114
115static u16 rt2500usb_bbp_check(struct rt2x00_dev *rt2x00dev) 115static int rt2500usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
116 const unsigned int offset,
117 struct rt2x00_field16 field,
118 u16 *reg)
116{ 119{
117 u16 reg;
118 unsigned int i; 120 unsigned int i;
119 121
120 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 122 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
121 rt2500usb_register_read_lock(rt2x00dev, PHY_CSR8, &reg); 123 rt2500usb_register_read_lock(rt2x00dev, offset, reg);
122 if (!rt2x00_get_field16(reg, PHY_CSR8_BUSY)) 124 if (!rt2x00_get_field16(*reg, field))
123 break; 125 return 1;
124 udelay(REGISTER_BUSY_DELAY); 126 udelay(REGISTER_BUSY_DELAY);
125 } 127 }
126 128
127 return reg; 129 ERROR(rt2x00dev, "Indirect register access failed: "
130 "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
131 *reg = ~0;
132
133 return 0;
128} 134}
129 135
136#define WAIT_FOR_BBP(__dev, __reg) \
137 rt2500usb_regbusy_read((__dev), PHY_CSR8, PHY_CSR8_BUSY, (__reg))
138#define WAIT_FOR_RF(__dev, __reg) \
139 rt2500usb_regbusy_read((__dev), PHY_CSR10, PHY_CSR10_RF_BUSY, (__reg))
140
130static void rt2500usb_bbp_write(struct rt2x00_dev *rt2x00dev, 141static void rt2500usb_bbp_write(struct rt2x00_dev *rt2x00dev,
131 const unsigned int word, const u8 value) 142 const unsigned int word, const u8 value)
132{ 143{
@@ -135,30 +146,19 @@ static void rt2500usb_bbp_write(struct rt2x00_dev *rt2x00dev,
135 mutex_lock(&rt2x00dev->csr_mutex); 146 mutex_lock(&rt2x00dev->csr_mutex);
136 147
137 /* 148 /*
138 * Wait until the BBP becomes ready. 149 * Wait until the BBP becomes available, afterwards we
139 */ 150 * can safely write the new data into the register.
140 reg = rt2500usb_bbp_check(rt2x00dev);
141 if (rt2x00_get_field16(reg, PHY_CSR8_BUSY))
142 goto exit_fail;
143
144 /*
145 * Write the data into the BBP.
146 */ 151 */
147 reg = 0; 152 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
148 rt2x00_set_field16(&reg, PHY_CSR7_DATA, value); 153 reg = 0;
149 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word); 154 rt2x00_set_field16(&reg, PHY_CSR7_DATA, value);
150 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0); 155 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
151 156 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 0);
152 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
153
154 mutex_unlock(&rt2x00dev->csr_mutex);
155 157
156 return; 158 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
159 }
157 160
158exit_fail:
159 mutex_unlock(&rt2x00dev->csr_mutex); 161 mutex_unlock(&rt2x00dev->csr_mutex);
160
161 ERROR(rt2x00dev, "PHY_CSR8 register busy. Write failed.\n");
162} 162}
163 163
164static void rt2500usb_bbp_read(struct rt2x00_dev *rt2x00dev, 164static void rt2500usb_bbp_read(struct rt2x00_dev *rt2x00dev,
@@ -169,77 +169,57 @@ static void rt2500usb_bbp_read(struct rt2x00_dev *rt2x00dev,
169 mutex_lock(&rt2x00dev->csr_mutex); 169 mutex_lock(&rt2x00dev->csr_mutex);
170 170
171 /* 171 /*
172 * Wait until the BBP becomes ready. 172 * Wait until the BBP becomes available, afterwards we
173 */ 173 * can safely write the read request into the register.
174 reg = rt2500usb_bbp_check(rt2x00dev); 174 * After the data has been written, we wait until hardware
175 if (rt2x00_get_field16(reg, PHY_CSR8_BUSY)) 175 * returns the correct value, if at any time the register
176 goto exit_fail; 176 * doesn't become available in time, reg will be 0xffffffff
177 177 * which means we return 0xff to the caller.
178 /*
179 * Write the request into the BBP.
180 */ 178 */
181 reg = 0; 179 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
182 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word); 180 reg = 0;
183 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1); 181 rt2x00_set_field16(&reg, PHY_CSR7_REG_ID, word);
182 rt2x00_set_field16(&reg, PHY_CSR7_READ_CONTROL, 1);
184 183
185 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg); 184 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR7, reg);
186 185
187 /* 186 if (WAIT_FOR_BBP(rt2x00dev, &reg))
188 * Wait until the BBP becomes ready. 187 rt2500usb_register_read_lock(rt2x00dev, PHY_CSR7, &reg);
189 */ 188 }
190 reg = rt2500usb_bbp_check(rt2x00dev);
191 if (rt2x00_get_field16(reg, PHY_CSR8_BUSY))
192 goto exit_fail;
193 189
194 rt2500usb_register_read_lock(rt2x00dev, PHY_CSR7, &reg);
195 *value = rt2x00_get_field16(reg, PHY_CSR7_DATA); 190 *value = rt2x00_get_field16(reg, PHY_CSR7_DATA);
196 191
197 mutex_unlock(&rt2x00dev->csr_mutex); 192 mutex_unlock(&rt2x00dev->csr_mutex);
198
199 return;
200
201exit_fail:
202 mutex_unlock(&rt2x00dev->csr_mutex);
203
204 ERROR(rt2x00dev, "PHY_CSR8 register busy. Read failed.\n");
205 *value = 0xff;
206} 193}
207 194
208static void rt2500usb_rf_write(struct rt2x00_dev *rt2x00dev, 195static void rt2500usb_rf_write(struct rt2x00_dev *rt2x00dev,
209 const unsigned int word, const u32 value) 196 const unsigned int word, const u32 value)
210{ 197{
211 u16 reg; 198 u16 reg;
212 unsigned int i;
213 199
214 if (!word) 200 if (!word)
215 return; 201 return;
216 202
217 mutex_lock(&rt2x00dev->csr_mutex); 203 mutex_lock(&rt2x00dev->csr_mutex);
218 204
219 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 205 /*
220 rt2500usb_register_read_lock(rt2x00dev, PHY_CSR10, &reg); 206 * Wait until the RF becomes available, afterwards we
221 if (!rt2x00_get_field16(reg, PHY_CSR10_RF_BUSY)) 207 * can safely write the new data into the register.
222 goto rf_write; 208 */
223 udelay(REGISTER_BUSY_DELAY); 209 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
224 } 210 reg = 0;
225 211 rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value);
226 mutex_unlock(&rt2x00dev->csr_mutex); 212 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR9, reg);
227 ERROR(rt2x00dev, "PHY_CSR10 register busy. Write failed.\n");
228 return;
229
230rf_write:
231 reg = 0;
232 rt2x00_set_field16(&reg, PHY_CSR9_RF_VALUE, value);
233 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR9, reg);
234 213
235 reg = 0; 214 reg = 0;
236 rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16); 215 rt2x00_set_field16(&reg, PHY_CSR10_RF_VALUE, value >> 16);
237 rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20); 216 rt2x00_set_field16(&reg, PHY_CSR10_RF_NUMBER_OF_BITS, 20);
238 rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0); 217 rt2x00_set_field16(&reg, PHY_CSR10_RF_IF_SELECT, 0);
239 rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1); 218 rt2x00_set_field16(&reg, PHY_CSR10_RF_BUSY, 1);
240 219
241 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR10, reg); 220 rt2500usb_register_write_lock(rt2x00dev, PHY_CSR10, reg);
242 rt2x00_rf_write(rt2x00dev, word, value); 221 rt2x00_rf_write(rt2x00dev, word, value);
222 }
243 223
244 mutex_unlock(&rt2x00dev->csr_mutex); 224 mutex_unlock(&rt2x00dev->csr_mutex);
245} 225}
@@ -1128,7 +1108,7 @@ static void rt2500usb_write_beacon(struct queue_entry *entry)
1128 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev); 1108 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
1129 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data; 1109 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
1130 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1110 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1131 int pipe = usb_sndbulkpipe(usb_dev, 1); 1111 int pipe = usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint);
1132 int length; 1112 int length;
1133 u16 reg; 1113 u16 reg;
1134 1114
@@ -1154,7 +1134,7 @@ static void rt2500usb_write_beacon(struct queue_entry *entry)
1154 * length of the data to usb_fill_bulk_urb. Pass the skb 1134 * length of the data to usb_fill_bulk_urb. Pass the skb
1155 * to the driver to determine what the length should be. 1135 * to the driver to determine what the length should be.
1156 */ 1136 */
1157 length = rt2x00dev->ops->lib->get_tx_data_len(rt2x00dev, entry->skb); 1137 length = rt2x00dev->ops->lib->get_tx_data_len(entry);
1158 1138
1159 usb_fill_bulk_urb(bcn_priv->urb, usb_dev, pipe, 1139 usb_fill_bulk_urb(bcn_priv->urb, usb_dev, pipe,
1160 entry->skb->data, length, rt2500usb_beacondone, 1140 entry->skb->data, length, rt2500usb_beacondone,
@@ -1176,8 +1156,7 @@ static void rt2500usb_write_beacon(struct queue_entry *entry)
1176 usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC); 1156 usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC);
1177} 1157}
1178 1158
1179static int rt2500usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev, 1159static int rt2500usb_get_tx_data_len(struct queue_entry *entry)
1180 struct sk_buff *skb)
1181{ 1160{
1182 int length; 1161 int length;
1183 1162
@@ -1185,8 +1164,8 @@ static int rt2500usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1185 * The length _must_ be a multiple of 2, 1164 * The length _must_ be a multiple of 2,
1186 * but it must _not_ be a multiple of the USB packet size. 1165 * but it must _not_ be a multiple of the USB packet size.
1187 */ 1166 */
1188 length = roundup(skb->len, 2); 1167 length = roundup(entry->skb->len, 2);
1189 length += (2 * !(length % rt2x00dev->usb_maxpacket)); 1168 length += (2 * !(length % entry->queue->usb_maxpacket));
1190 1169
1191 return length; 1170 return length;
1192} 1171}
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index fee61bee1e7e..780ba7365810 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -555,8 +555,7 @@ struct rt2x00lib_ops {
555 struct txentry_desc *txdesc); 555 struct txentry_desc *txdesc);
556 int (*write_tx_data) (struct queue_entry *entry); 556 int (*write_tx_data) (struct queue_entry *entry);
557 void (*write_beacon) (struct queue_entry *entry); 557 void (*write_beacon) (struct queue_entry *entry);
558 int (*get_tx_data_len) (struct rt2x00_dev *rt2x00dev, 558 int (*get_tx_data_len) (struct queue_entry *entry);
559 struct sk_buff *skb);
560 void (*kick_tx_queue) (struct rt2x00_dev *rt2x00dev, 559 void (*kick_tx_queue) (struct rt2x00_dev *rt2x00dev,
561 const enum data_queue_qid queue); 560 const enum data_queue_qid queue);
562 561
@@ -799,11 +798,6 @@ struct rt2x00_dev {
799 short lna_gain; 798 short lna_gain;
800 799
801 /* 800 /*
802 * USB Max frame size (for rt2500usb & rt73usb).
803 */
804 u16 usb_maxpacket;
805
806 /*
807 * Current TX power value. 801 * Current TX power value.
808 */ 802 */
809 u16 tx_power; 803 u16 tx_power;
diff --git a/drivers/net/wireless/rt2x00/rt2x00leds.c b/drivers/net/wireless/rt2x00/rt2x00leds.c
index 66c61b1eca5d..68f4e0fc35b9 100644
--- a/drivers/net/wireless/rt2x00/rt2x00leds.c
+++ b/drivers/net/wireless/rt2x00/rt2x00leds.c
@@ -111,12 +111,6 @@ static int rt2x00leds_register_led(struct rt2x00_dev *rt2x00dev,
111 led->led_dev.name = name; 111 led->led_dev.name = name;
112 led->led_dev.brightness = LED_OFF; 112 led->led_dev.brightness = LED_OFF;
113 113
114 /*
115 * Ensure the LED is off, it might have been enabled
116 * by the hardware when the device was powered on.
117 */
118 led->led_dev.brightness_set(&led->led_dev, LED_OFF);
119
120 retval = led_classdev_register(device, &led->led_dev); 114 retval = led_classdev_register(device, &led->led_dev);
121 if (retval) { 115 if (retval) {
122 ERROR(rt2x00dev, "Failed to register led handler.\n"); 116 ERROR(rt2x00dev, "Failed to register led handler.\n");
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c
index 48636b0dd895..4c0395729066 100644
--- a/drivers/net/wireless/rt2x00/rt2x00mac.c
+++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
@@ -132,8 +132,7 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
132 ERROR(rt2x00dev, 132 ERROR(rt2x00dev,
133 "Attempt to send packet over invalid queue %d.\n" 133 "Attempt to send packet over invalid queue %d.\n"
134 "Please file bug report to %s.\n", qid, DRV_PROJECT); 134 "Please file bug report to %s.\n", qid, DRV_PROJECT);
135 dev_kfree_skb_any(skb); 135 goto exit_fail;
136 return NETDEV_TX_OK;
137 } 136 }
138 137
139 /* 138 /*
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index e33bd0f150c5..d52b22b82d1f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -32,6 +32,31 @@
32#include "rt2x00pci.h" 32#include "rt2x00pci.h"
33 33
34/* 34/*
35 * Register access.
36 */
37int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
38 const unsigned int offset,
39 const struct rt2x00_field32 field,
40 u32 *reg)
41{
42 unsigned int i;
43
44 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
45 rt2x00pci_register_read(rt2x00dev, offset, reg);
46 if (!rt2x00_get_field32(*reg, field))
47 return 1;
48 udelay(REGISTER_BUSY_DELAY);
49 }
50
51 ERROR(rt2x00dev, "Indirect register access failed: "
52 "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
53 *reg = ~0;
54
55 return 0;
56}
57EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);
58
59/*
35 * TX data handlers. 60 * TX data handlers.
36 */ 61 */
37int rt2x00pci_write_tx_data(struct queue_entry *entry) 62int rt2x00pci_write_tx_data(struct queue_entry *entry)
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index 96a2082a3532..9c0a4d77bc1b 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -77,6 +77,24 @@ rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,
77} 77}
78 78
79/** 79/**
80 * rt2x00pci_regbusy_read - Read from register with busy check
81 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
82 * @offset: Register offset
83 * @field: Field to check if register is busy
84 * @reg: Pointer to where register contents should be stored
85 *
86 * This function will read the given register, and checks if the
87 * register is busy. If it is, it will sleep for a couple of
88 * microseconds before reading the register again. If the register
89 * is not read after a certain timeout, this function will return
90 * FALSE.
91 */
92int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
93 const unsigned int offset,
94 const struct rt2x00_field32 field,
95 u32 *reg);
96
97/**
80 * rt2x00pci_write_tx_data - Initialize data for TX operation 98 * rt2x00pci_write_tx_data - Initialize data for TX operation
81 * @entry: The entry where the frame is located 99 * @entry: The entry where the frame is located
82 * 100 *
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index d7752dbd2023..b8de9d2750e4 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -386,7 +386,7 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
386 u8 rate_idx, rate_flags; 386 u8 rate_idx, rate_flags;
387 387
388 if (unlikely(rt2x00queue_full(queue))) 388 if (unlikely(rt2x00queue_full(queue)))
389 return -EINVAL; 389 return -ENOBUFS;
390 390
391 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) { 391 if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
392 ERROR(queue->rt2x00dev, 392 ERROR(queue->rt2x00dev,
@@ -415,7 +415,7 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
415 tx_info = IEEE80211_SKB_CB(skb); 415 tx_info = IEEE80211_SKB_CB(skb);
416 rate_idx = tx_info->control.rates[0].idx; 416 rate_idx = tx_info->control.rates[0].idx;
417 rate_flags = tx_info->control.rates[0].flags; 417 rate_flags = tx_info->control.rates[0].flags;
418 skbdesc = get_skb_frame_desc(entry->skb); 418 skbdesc = get_skb_frame_desc(skb);
419 memset(skbdesc, 0, sizeof(*skbdesc)); 419 memset(skbdesc, 0, sizeof(*skbdesc));
420 skbdesc->entry = entry; 420 skbdesc->entry = entry;
421 skbdesc->tx_rate_idx = rate_idx; 421 skbdesc->tx_rate_idx = rate_idx;
@@ -427,20 +427,18 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
427 * the frame so we can provide it to the driver seperately. 427 * the frame so we can provide it to the driver seperately.
428 */ 428 */
429 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) && 429 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
430 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags)) { 430 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags))
431 rt2x00crypto_tx_remove_iv(skb, iv_len); 431 rt2x00crypto_tx_remove_iv(skb, iv_len);
432 }
433 432
434 /* 433 /*
435 * It could be possible that the queue was corrupted and this 434 * It could be possible that the queue was corrupted and this
436 * call failed. Just drop the frame, we cannot rollback and pass 435 * call failed. Since we always return NETDEV_TX_OK to mac80211,
437 * the frame to mac80211 because the skb->cb has now been tainted. 436 * this frame will simply be dropped.
438 */ 437 */
439 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) { 438 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
440 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); 439 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
441 dev_kfree_skb_any(entry->skb);
442 entry->skb = NULL; 440 entry->skb = NULL;
443 return 0; 441 return -EIO;
444 } 442 }
445 443
446 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags)) 444 if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index 4d3c7246f9ae..2e99ab53ec65 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -380,6 +380,8 @@ enum queue_index {
380 * @cw_max: The cw max value for outgoing frames (field ignored in RX queue). 380 * @cw_max: The cw max value for outgoing frames (field ignored in RX queue).
381 * @data_size: Maximum data size for the frames in this queue. 381 * @data_size: Maximum data size for the frames in this queue.
382 * @desc_size: Hardware descriptor size for the data in this queue. 382 * @desc_size: Hardware descriptor size for the data in this queue.
383 * @usb_endpoint: Device endpoint used for communication (USB only)
384 * @usb_maxpacket: Max packet size for given endpoint (USB only)
383 */ 385 */
384struct data_queue { 386struct data_queue {
385 struct rt2x00_dev *rt2x00dev; 387 struct rt2x00_dev *rt2x00dev;
@@ -401,6 +403,9 @@ struct data_queue {
401 403
402 unsigned short data_size; 404 unsigned short data_size;
403 unsigned short desc_size; 405 unsigned short desc_size;
406
407 unsigned short usb_endpoint;
408 unsigned short usb_maxpacket;
404}; 409};
405 410
406/** 411/**
@@ -444,6 +449,19 @@ struct data_queue_desc {
444 &(__dev)->tx[(__dev)->ops->tx_queues] 449 &(__dev)->tx[(__dev)->ops->tx_queues]
445 450
446/** 451/**
452 * queue_next - Return pointer to next queue in list (HELPER MACRO).
453 * @__queue: Current queue for which we need the next queue
454 *
455 * Using the current queue address we take the address directly
456 * after the queue to take the next queue. Note that this macro
457 * should be used carefully since it does not protect against
458 * moving past the end of the list. (See macros &queue_end and
459 * &tx_queue_end for determining the end of the queue).
460 */
461#define queue_next(__queue) \
462 &(__queue)[1]
463
464/**
447 * queue_loop - Loop through the queues within a specific range (HELPER MACRO). 465 * queue_loop - Loop through the queues within a specific range (HELPER MACRO).
448 * @__entry: Pointer where the current queue entry will be stored in. 466 * @__entry: Pointer where the current queue entry will be stored in.
449 * @__start: Start queue pointer. 467 * @__start: Start queue pointer.
@@ -453,8 +471,8 @@ struct data_queue_desc {
453 */ 471 */
454#define queue_loop(__entry, __start, __end) \ 472#define queue_loop(__entry, __start, __end) \
455 for ((__entry) = (__start); \ 473 for ((__entry) = (__start); \
456 prefetch(&(__entry)[1]), (__entry) != (__end); \ 474 prefetch(queue_next(__entry)), (__entry) != (__end);\
457 (__entry) = &(__entry)[1]) 475 (__entry) = queue_next(__entry))
458 476
459/** 477/**
460 * queue_for_each - Loop through all queues 478 * queue_for_each - Loop through all queues
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index c507b0d9409f..83df312ac56f 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -154,6 +154,28 @@ int rt2x00usb_vendor_request_large_buff(struct rt2x00_dev *rt2x00dev,
154} 154}
155EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request_large_buff); 155EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request_large_buff);
156 156
157int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
158 const unsigned int offset,
159 struct rt2x00_field32 field,
160 u32 *reg)
161{
162 unsigned int i;
163
164 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
165 rt2x00usb_register_read_lock(rt2x00dev, offset, reg);
166 if (!rt2x00_get_field32(*reg, field))
167 return 1;
168 udelay(REGISTER_BUSY_DELAY);
169 }
170
171 ERROR(rt2x00dev, "Indirect register access failed: "
172 "offset=0x%.08x, value=0x%.08x\n", offset, *reg);
173 *reg = ~0;
174
175 return 0;
176}
177EXPORT_SYMBOL_GPL(rt2x00usb_regbusy_read);
178
157/* 179/*
158 * TX data handlers. 180 * TX data handlers.
159 */ 181 */
@@ -212,10 +234,10 @@ int rt2x00usb_write_tx_data(struct queue_entry *entry)
212 * length of the data to usb_fill_bulk_urb. Pass the skb 234 * length of the data to usb_fill_bulk_urb. Pass the skb
213 * to the driver to determine what the length should be. 235 * to the driver to determine what the length should be.
214 */ 236 */
215 length = rt2x00dev->ops->lib->get_tx_data_len(rt2x00dev, entry->skb); 237 length = rt2x00dev->ops->lib->get_tx_data_len(entry);
216 238
217 usb_fill_bulk_urb(entry_priv->urb, usb_dev, 239 usb_fill_bulk_urb(entry_priv->urb, usb_dev,
218 usb_sndbulkpipe(usb_dev, 1), 240 usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint),
219 entry->skb->data, length, 241 entry->skb->data, length,
220 rt2x00usb_interrupt_txdone, entry); 242 rt2x00usb_interrupt_txdone, entry);
221 243
@@ -356,10 +378,11 @@ void rt2x00usb_clear_entry(struct queue_entry *entry)
356 struct usb_device *usb_dev = 378 struct usb_device *usb_dev =
357 to_usb_device_intf(entry->queue->rt2x00dev->dev); 379 to_usb_device_intf(entry->queue->rt2x00dev->dev);
358 struct queue_entry_priv_usb *entry_priv = entry->priv_data; 380 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
381 int pipe;
359 382
360 if (entry->queue->qid == QID_RX) { 383 if (entry->queue->qid == QID_RX) {
361 usb_fill_bulk_urb(entry_priv->urb, usb_dev, 384 pipe = usb_rcvbulkpipe(usb_dev, entry->queue->usb_endpoint);
362 usb_rcvbulkpipe(usb_dev, 1), 385 usb_fill_bulk_urb(entry_priv->urb, usb_dev, pipe,
363 entry->skb->data, entry->skb->len, 386 entry->skb->data, entry->skb->len,
364 rt2x00usb_interrupt_rxdone, entry); 387 rt2x00usb_interrupt_rxdone, entry);
365 388
@@ -371,6 +394,76 @@ void rt2x00usb_clear_entry(struct queue_entry *entry)
371} 394}
372EXPORT_SYMBOL_GPL(rt2x00usb_clear_entry); 395EXPORT_SYMBOL_GPL(rt2x00usb_clear_entry);
373 396
397static void rt2x00usb_assign_endpoint(struct data_queue *queue,
398 struct usb_endpoint_descriptor *ep_desc)
399{
400 struct usb_device *usb_dev = to_usb_device_intf(queue->rt2x00dev->dev);
401 int pipe;
402
403 queue->usb_endpoint = usb_endpoint_num(ep_desc);
404
405 if (queue->qid == QID_RX) {
406 pipe = usb_rcvbulkpipe(usb_dev, queue->usb_endpoint);
407 queue->usb_maxpacket = usb_maxpacket(usb_dev, pipe, 0);
408 } else {
409 pipe = usb_sndbulkpipe(usb_dev, queue->usb_endpoint);
410 queue->usb_maxpacket = usb_maxpacket(usb_dev, pipe, 1);
411 }
412
413 if (!queue->usb_maxpacket)
414 queue->usb_maxpacket = 1;
415}
416
417static int rt2x00usb_find_endpoints(struct rt2x00_dev *rt2x00dev)
418{
419 struct usb_interface *intf = to_usb_interface(rt2x00dev->dev);
420 struct usb_host_interface *intf_desc = intf->cur_altsetting;
421 struct usb_endpoint_descriptor *ep_desc;
422 struct data_queue *queue = rt2x00dev->tx;
423 struct usb_endpoint_descriptor *tx_ep_desc = NULL;
424 unsigned int i;
425
426 /*
427 * Walk through all available endpoints to search for "bulk in"
428 * and "bulk out" endpoints. When we find such endpoints collect
429 * the information we need from the descriptor and assign it
430 * to the queue.
431 */
432 for (i = 0; i < intf_desc->desc.bNumEndpoints; i++) {
433 ep_desc = &intf_desc->endpoint[i].desc;
434
435 if (usb_endpoint_is_bulk_in(ep_desc)) {
436 rt2x00usb_assign_endpoint(rt2x00dev->rx, ep_desc);
437 } else if (usb_endpoint_is_bulk_out(ep_desc)) {
438 rt2x00usb_assign_endpoint(queue, ep_desc);
439
440 if (queue != queue_end(rt2x00dev))
441 queue = queue_next(queue);
442 tx_ep_desc = ep_desc;
443 }
444 }
445
446 /*
447 * At least 1 endpoint for RX and 1 endpoint for TX must be available.
448 */
449 if (!rt2x00dev->rx->usb_endpoint || !rt2x00dev->tx->usb_endpoint) {
450 ERROR(rt2x00dev, "Bulk-in/Bulk-out endpoints not found\n");
451 return -EPIPE;
452 }
453
454 /*
455 * It might be possible not all queues have a dedicated endpoint.
456 * Loop through all TX queues and copy the endpoint information
457 * which we have gathered from already assigned endpoints.
458 */
459 txall_queue_for_each(rt2x00dev, queue) {
460 if (!queue->usb_endpoint)
461 rt2x00usb_assign_endpoint(queue, tx_ep_desc);
462 }
463
464 return 0;
465}
466
374static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev, 467static int rt2x00usb_alloc_urb(struct rt2x00_dev *rt2x00dev,
375 struct data_queue *queue) 468 struct data_queue *queue)
376{ 469{
@@ -442,6 +535,13 @@ int rt2x00usb_initialize(struct rt2x00_dev *rt2x00dev)
442 int status; 535 int status;
443 536
444 /* 537 /*
538 * Find endpoints for each queue
539 */
540 status = rt2x00usb_find_endpoints(rt2x00dev);
541 if (status)
542 goto exit;
543
544 /*
445 * Allocate DMA 545 * Allocate DMA
446 */ 546 */
447 queue_for_each(rt2x00dev, queue) { 547 queue_for_each(rt2x00dev, queue) {
@@ -532,11 +632,6 @@ int rt2x00usb_probe(struct usb_interface *usb_intf,
532 rt2x00dev->ops = ops; 632 rt2x00dev->ops = ops;
533 rt2x00dev->hw = hw; 633 rt2x00dev->hw = hw;
534 634
535 rt2x00dev->usb_maxpacket =
536 usb_maxpacket(usb_dev, usb_sndbulkpipe(usb_dev, 1), 1);
537 if (!rt2x00dev->usb_maxpacket)
538 rt2x00dev->usb_maxpacket = 1;
539
540 retval = rt2x00usb_alloc_reg(rt2x00dev); 635 retval = rt2x00usb_alloc_reg(rt2x00dev);
541 if (retval) 636 if (retval)
542 goto exit_free_device; 637 goto exit_free_device;
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h
index 4104f0e8fa48..2bd4ac855f52 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.h
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.h
@@ -231,6 +231,142 @@ static inline int rt2x00usb_eeprom_read(struct rt2x00_dev *rt2x00dev,
231 REGISTER_TIMEOUT16(length)); 231 REGISTER_TIMEOUT16(length));
232} 232}
233 233
234/**
235 * rt2x00usb_regbusy_read - Read 32bit register word
236 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
237 * @offset: Register offset
238 * @value: Pointer to where register contents should be stored
239 *
240 * This function is a simple wrapper for 32bit register access
241 * through rt2x00usb_vendor_request_buff().
242 */
243static inline void rt2x00usb_register_read(struct rt2x00_dev *rt2x00dev,
244 const unsigned int offset,
245 u32 *value)
246{
247 __le32 reg;
248 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
249 USB_VENDOR_REQUEST_IN, offset,
250 &reg, sizeof(reg), REGISTER_TIMEOUT);
251 *value = le32_to_cpu(reg);
252}
253
254/**
255 * rt2x00usb_register_read_lock - Read 32bit register word
256 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
257 * @offset: Register offset
258 * @value: Pointer to where register contents should be stored
259 *
260 * This function is a simple wrapper for 32bit register access
261 * through rt2x00usb_vendor_req_buff_lock().
262 */
263static inline void rt2x00usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
264 const unsigned int offset,
265 u32 *value)
266{
267 __le32 reg;
268 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
269 USB_VENDOR_REQUEST_IN, offset,
270 &reg, sizeof(reg), REGISTER_TIMEOUT);
271 *value = le32_to_cpu(reg);
272}
273
274/**
275 * rt2x00usb_register_multiread - Read 32bit register words
276 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
277 * @offset: Register offset
278 * @value: Pointer to where register contents should be stored
279 * @length: Length of the data
280 *
281 * This function is a simple wrapper for 32bit register access
282 * through rt2x00usb_vendor_request_buff().
283 */
284static inline void rt2x00usb_register_multiread(struct rt2x00_dev *rt2x00dev,
285 const unsigned int offset,
286 void *value, const u32 length)
287{
288 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
289 USB_VENDOR_REQUEST_IN, offset,
290 value, length,
291 REGISTER_TIMEOUT32(length));
292}
293
294/**
295 * rt2x00usb_register_write - Write 32bit register word
296 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
297 * @offset: Register offset
298 * @value: Data which should be written
299 *
300 * This function is a simple wrapper for 32bit register access
301 * through rt2x00usb_vendor_request_buff().
302 */
303static inline void rt2x00usb_register_write(struct rt2x00_dev *rt2x00dev,
304 const unsigned int offset,
305 u32 value)
306{
307 __le32 reg = cpu_to_le32(value);
308 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
309 USB_VENDOR_REQUEST_OUT, offset,
310 &reg, sizeof(reg), REGISTER_TIMEOUT);
311}
312
313/**
314 * rt2x00usb_register_write_lock - Write 32bit register word
315 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
316 * @offset: Register offset
317 * @value: Data which should be written
318 *
319 * This function is a simple wrapper for 32bit register access
320 * through rt2x00usb_vendor_req_buff_lock().
321 */
322static inline void rt2x00usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
323 const unsigned int offset,
324 u32 value)
325{
326 __le32 reg = cpu_to_le32(value);
327 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
328 USB_VENDOR_REQUEST_OUT, offset,
329 &reg, sizeof(reg), REGISTER_TIMEOUT);
330}
331
332/**
333 * rt2x00usb_register_multiwrite - Write 32bit register words
334 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
335 * @offset: Register offset
336 * @value: Data which should be written
337 * @length: Length of the data
338 *
339 * This function is a simple wrapper for 32bit register access
340 * through rt2x00usb_vendor_request_buff().
341 */
342static inline void rt2x00usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
343 const unsigned int offset,
344 void *value, const u32 length)
345{
346 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
347 USB_VENDOR_REQUEST_OUT, offset,
348 value, length,
349 REGISTER_TIMEOUT32(length));
350}
351
352/**
353 * rt2x00usb_regbusy_read - Read from register with busy check
354 * @rt2x00dev: Device pointer, see &struct rt2x00_dev.
355 * @offset: Register offset
356 * @field: Field to check if register is busy
357 * @reg: Pointer to where register contents should be stored
358 *
359 * This function will read the given register, and checks if the
360 * register is busy. If it is, it will sleep for a couple of
361 * microseconds before reading the register again. If the register
362 * is not read after a certain timeout, this function will return
363 * FALSE.
364 */
365int rt2x00usb_regbusy_read(struct rt2x00_dev *rt2x00dev,
366 const unsigned int offset,
367 struct rt2x00_field32 field,
368 u32 *reg);
369
234/* 370/*
235 * Radio handlers 371 * Radio handlers
236 */ 372 */
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 89ac34fbadf2..d54443c25fe3 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -55,20 +55,13 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
55 * the access attempt is considered to have failed, 55 * the access attempt is considered to have failed,
56 * and we will print an error. 56 * and we will print an error.
57 */ 57 */
58static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev) 58#define WAIT_FOR_BBP(__dev, __reg) \
59{ 59 rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
60 u32 reg; 60#define WAIT_FOR_RF(__dev, __reg) \
61 unsigned int i; 61 rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
62 62#define WAIT_FOR_MCU(__dev, __reg) \
63 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 63 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
64 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg); 64 H2M_MAILBOX_CSR_OWNER, (__reg))
65 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
66 break;
67 udelay(REGISTER_BUSY_DELAY);
68 }
69
70 return reg;
71}
72 65
73static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, 66static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
74 const unsigned int word, const u8 value) 67 const unsigned int word, const u8 value)
@@ -78,30 +71,20 @@ static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
78 mutex_lock(&rt2x00dev->csr_mutex); 71 mutex_lock(&rt2x00dev->csr_mutex);
79 72
80 /* 73 /*
81 * Wait until the BBP becomes ready. 74 * Wait until the BBP becomes available, afterwards we
82 */ 75 * can safely write the new data into the register.
83 reg = rt61pci_bbp_check(rt2x00dev);
84 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
85 goto exit_fail;
86
87 /*
88 * Write the data into the BBP.
89 */ 76 */
90 reg = 0; 77 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
91 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value); 78 reg = 0;
92 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); 79 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
93 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); 80 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
94 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0); 81 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
95 82 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
96 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
97 mutex_unlock(&rt2x00dev->csr_mutex);
98 83
99 return; 84 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
85 }
100 86
101exit_fail:
102 mutex_unlock(&rt2x00dev->csr_mutex); 87 mutex_unlock(&rt2x00dev->csr_mutex);
103
104 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
105} 88}
106 89
107static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, 90static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
@@ -112,72 +95,53 @@ static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
112 mutex_lock(&rt2x00dev->csr_mutex); 95 mutex_lock(&rt2x00dev->csr_mutex);
113 96
114 /* 97 /*
115 * Wait until the BBP becomes ready. 98 * Wait until the BBP becomes available, afterwards we
99 * can safely write the read request into the register.
100 * After the data has been written, we wait until hardware
101 * returns the correct value, if at any time the register
102 * doesn't become available in time, reg will be 0xffffffff
103 * which means we return 0xff to the caller.
116 */ 104 */
117 reg = rt61pci_bbp_check(rt2x00dev); 105 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
118 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) 106 reg = 0;
119 goto exit_fail; 107 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
108 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
109 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
120 110
121 /* 111 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
122 * Write the request into the BBP.
123 */
124 reg = 0;
125 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
126 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
127 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
128 112
129 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg); 113 WAIT_FOR_BBP(rt2x00dev, &reg);
130 114 }
131 /*
132 * Wait until the BBP becomes ready.
133 */
134 reg = rt61pci_bbp_check(rt2x00dev);
135 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
136 goto exit_fail;
137 115
138 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); 116 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
139 mutex_unlock(&rt2x00dev->csr_mutex);
140
141 return;
142 117
143exit_fail:
144 mutex_unlock(&rt2x00dev->csr_mutex); 118 mutex_unlock(&rt2x00dev->csr_mutex);
145
146 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
147 *value = 0xff;
148} 119}
149 120
150static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, 121static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
151 const unsigned int word, const u32 value) 122 const unsigned int word, const u32 value)
152{ 123{
153 u32 reg; 124 u32 reg;
154 unsigned int i;
155 125
156 if (!word) 126 if (!word)
157 return; 127 return;
158 128
159 mutex_lock(&rt2x00dev->csr_mutex); 129 mutex_lock(&rt2x00dev->csr_mutex);
160 130
161 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 131 /*
162 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg); 132 * Wait until the RF becomes available, afterwards we
163 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY)) 133 * can safely write the new data into the register.
164 goto rf_write; 134 */
165 udelay(REGISTER_BUSY_DELAY); 135 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
166 } 136 reg = 0;
167 137 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
168 mutex_unlock(&rt2x00dev->csr_mutex); 138 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
169 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n"); 139 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
170 return; 140 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
171
172rf_write:
173 reg = 0;
174 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
175 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
176 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
177 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
178 141
179 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg); 142 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
180 rt2x00_rf_write(rt2x00dev, word, value); 143 rt2x00_rf_write(rt2x00dev, word, value);
144 }
181 145
182 mutex_unlock(&rt2x00dev->csr_mutex); 146 mutex_unlock(&rt2x00dev->csr_mutex);
183} 147}
@@ -196,32 +160,25 @@ static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
196 160
197 mutex_lock(&rt2x00dev->csr_mutex); 161 mutex_lock(&rt2x00dev->csr_mutex);
198 162
199 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg); 163 /*
200 164 * Wait until the MCU becomes available, afterwards we
201 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) 165 * can safely write the new data into the register.
202 goto exit_fail; 166 */
203 167 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
204 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1); 168 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
205 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token); 169 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
206 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0); 170 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
207 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1); 171 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
208 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); 172 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
209
210 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
211 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
212 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
213 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
214
215 mutex_unlock(&rt2x00dev->csr_mutex);
216 173
217 return; 174 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
175 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
176 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
177 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
178 }
218 179
219exit_fail:
220 mutex_unlock(&rt2x00dev->csr_mutex); 180 mutex_unlock(&rt2x00dev->csr_mutex);
221 181
222 ERROR(rt2x00dev,
223 "mcu request error. Request 0x%02x failed for token 0x%02x.\n",
224 command, token);
225} 182}
226#endif /* CONFIG_RT2X00_LIB_LEDS */ 183#endif /* CONFIG_RT2X00_LIB_LEDS */
227 184
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index d1a63e0017da..37a782dc8080 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -46,7 +46,7 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46/* 46/*
47 * Register access. 47 * Register access.
48 * All access to the CSR registers will go through the methods 48 * All access to the CSR registers will go through the methods
49 * rt73usb_register_read and rt73usb_register_write. 49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access, 50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this. 51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits, 52 * These indirect registers work with busy bits,
@@ -57,78 +57,10 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57 * and we will print an error. 57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex 58 * The _lock versions must be used if you already hold the csr_mutex
59 */ 59 */
60static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev, 60#define WAIT_FOR_BBP(__dev, __reg) \
61 const unsigned int offset, u32 *value) 61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62{ 62#define WAIT_FOR_RF(__dev, __reg) \
63 __le32 reg; 63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
64 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
65 USB_VENDOR_REQUEST_IN, offset,
66 &reg, sizeof(u32), REGISTER_TIMEOUT);
67 *value = le32_to_cpu(reg);
68}
69
70static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
71 const unsigned int offset, u32 *value)
72{
73 __le32 reg;
74 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
75 USB_VENDOR_REQUEST_IN, offset,
76 &reg, sizeof(u32), REGISTER_TIMEOUT);
77 *value = le32_to_cpu(reg);
78}
79
80static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
81 const unsigned int offset,
82 void *value, const u32 length)
83{
84 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
85 USB_VENDOR_REQUEST_IN, offset,
86 value, length,
87 REGISTER_TIMEOUT32(length));
88}
89
90static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
91 const unsigned int offset, u32 value)
92{
93 __le32 reg = cpu_to_le32(value);
94 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
95 USB_VENDOR_REQUEST_OUT, offset,
96 &reg, sizeof(u32), REGISTER_TIMEOUT);
97}
98
99static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
100 const unsigned int offset, u32 value)
101{
102 __le32 reg = cpu_to_le32(value);
103 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
104 USB_VENDOR_REQUEST_OUT, offset,
105 &reg, sizeof(u32), REGISTER_TIMEOUT);
106}
107
108static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
109 const unsigned int offset,
110 void *value, const u32 length)
111{
112 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
113 USB_VENDOR_REQUEST_OUT, offset,
114 value, length,
115 REGISTER_TIMEOUT32(length));
116}
117
118static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
119{
120 u32 reg;
121 unsigned int i;
122
123 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
124 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
125 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
126 break;
127 udelay(REGISTER_BUSY_DELAY);
128 }
129
130 return reg;
131}
132 64
133static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev, 65static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u8 value) 66 const unsigned int word, const u8 value)
@@ -138,30 +70,20 @@ static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
138 mutex_lock(&rt2x00dev->csr_mutex); 70 mutex_lock(&rt2x00dev->csr_mutex);
139 71
140 /* 72 /*
141 * Wait until the BBP becomes ready. 73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
142 */ 75 */
143 reg = rt73usb_bbp_check(rt2x00dev); 76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
144 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) 77 reg = 0;
145 goto exit_fail; 78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
146 79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
147 /* 80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
148 * Write the data into the BBP. 81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
149 */ 82
150 reg = 0; 83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
151 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value); 84 }
152 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
153 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
154 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
155
156 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
157 mutex_unlock(&rt2x00dev->csr_mutex);
158
159 return;
160 85
161exit_fail:
162 mutex_unlock(&rt2x00dev->csr_mutex); 86 mutex_unlock(&rt2x00dev->csr_mutex);
163
164 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
165} 87}
166 88
167static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev, 89static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
@@ -172,79 +94,59 @@ static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
172 mutex_lock(&rt2x00dev->csr_mutex); 94 mutex_lock(&rt2x00dev->csr_mutex);
173 95
174 /* 96 /*
175 * Wait until the BBP becomes ready. 97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
176 */ 103 */
177 reg = rt73usb_bbp_check(rt2x00dev); 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
178 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) 105 reg = 0;
179 goto exit_fail; 106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
180 109
181 /* 110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
182 * Write the request into the BBP.
183 */
184 reg = 0;
185 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
186 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
187 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
188 111
189 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); 112 WAIT_FOR_BBP(rt2x00dev, &reg);
190 113 }
191 /*
192 * Wait until the BBP becomes ready.
193 */
194 reg = rt73usb_bbp_check(rt2x00dev);
195 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
196 goto exit_fail;
197 114
198 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); 115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
199 mutex_unlock(&rt2x00dev->csr_mutex);
200 116
201 return;
202
203exit_fail:
204 mutex_unlock(&rt2x00dev->csr_mutex); 117 mutex_unlock(&rt2x00dev->csr_mutex);
205
206 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
207 *value = 0xff;
208} 118}
209 119
210static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev, 120static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
211 const unsigned int word, const u32 value) 121 const unsigned int word, const u32 value)
212{ 122{
213 u32 reg; 123 u32 reg;
214 unsigned int i;
215 124
216 if (!word) 125 if (!word)
217 return; 126 return;
218 127
219 mutex_lock(&rt2x00dev->csr_mutex); 128 mutex_lock(&rt2x00dev->csr_mutex);
220 129
221 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
222 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
223 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
224 goto rf_write;
225 udelay(REGISTER_BUSY_DELAY);
226 }
227
228 mutex_unlock(&rt2x00dev->csr_mutex);
229 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
230 return;
231
232rf_write:
233 reg = 0;
234 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
235
236 /* 130 /*
237 * RF5225 and RF2527 contain 21 bits per RF register value, 131 * Wait until the RF becomes available, afterwards we
238 * all others contain 20 bits. 132 * can safely write the new data into the register.
239 */ 133 */
240 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 134 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
241 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) || 135 reg = 0;
242 rt2x00_rf(&rt2x00dev->chip, RF2527))); 136 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
243 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0); 137 /*
244 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1); 138 * RF5225 and RF2527 contain 21 bits per RF register value,
245 139 * all others contain 20 bits.
246 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); 140 */
247 rt2x00_rf_write(rt2x00dev, word, value); 141 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
142 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
143 rt2x00_rf(&rt2x00dev->chip, RF2527)));
144 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
145 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
146
147 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
148 rt2x00_rf_write(rt2x00dev, word, value);
149 }
248 150
249 mutex_unlock(&rt2x00dev->csr_mutex); 151 mutex_unlock(&rt2x00dev->csr_mutex);
250} 152}
@@ -253,8 +155,8 @@ rf_write:
253static const struct rt2x00debug rt73usb_rt2x00debug = { 155static const struct rt2x00debug rt73usb_rt2x00debug = {
254 .owner = THIS_MODULE, 156 .owner = THIS_MODULE,
255 .csr = { 157 .csr = {
256 .read = rt73usb_register_read, 158 .read = rt2x00usb_register_read,
257 .write = rt73usb_register_write, 159 .write = rt2x00usb_register_write,
258 .flags = RT2X00DEBUGFS_OFFSET, 160 .flags = RT2X00DEBUGFS_OFFSET,
259 .word_base = CSR_REG_BASE, 161 .word_base = CSR_REG_BASE,
260 .word_size = sizeof(u32), 162 .word_size = sizeof(u32),
@@ -333,10 +235,10 @@ static int rt73usb_blink_set(struct led_classdev *led_cdev,
333 container_of(led_cdev, struct rt2x00_led, led_dev); 235 container_of(led_cdev, struct rt2x00_led, led_dev);
334 u32 reg; 236 u32 reg;
335 237
336 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg); 238 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
337 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on); 239 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
338 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off); 240 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
339 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg); 241 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
340 242
341 return 0; 243 return 0;
342} 244}
@@ -379,7 +281,7 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
379 */ 281 */
380 mask = (0xf << crypto->bssidx); 282 mask = (0xf << crypto->bssidx);
381 283
382 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg); 284 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
383 reg &= mask; 285 reg &= mask;
384 286
385 if (reg && reg == mask) 287 if (reg && reg == mask)
@@ -416,16 +318,16 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
416 field.bit_offset = (3 * key->hw_key_idx); 318 field.bit_offset = (3 * key->hw_key_idx);
417 field.bit_mask = 0x7 << field.bit_offset; 319 field.bit_mask = 0x7 << field.bit_offset;
418 320
419 rt73usb_register_read(rt2x00dev, SEC_CSR1, &reg); 321 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
420 rt2x00_set_field32(&reg, field, crypto->cipher); 322 rt2x00_set_field32(&reg, field, crypto->cipher);
421 rt73usb_register_write(rt2x00dev, SEC_CSR1, reg); 323 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
422 } else { 324 } else {
423 field.bit_offset = (3 * (key->hw_key_idx - 8)); 325 field.bit_offset = (3 * (key->hw_key_idx - 8));
424 field.bit_mask = 0x7 << field.bit_offset; 326 field.bit_mask = 0x7 << field.bit_offset;
425 327
426 rt73usb_register_read(rt2x00dev, SEC_CSR5, &reg); 328 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
427 rt2x00_set_field32(&reg, field, crypto->cipher); 329 rt2x00_set_field32(&reg, field, crypto->cipher);
428 rt73usb_register_write(rt2x00dev, SEC_CSR5, reg); 330 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
429 } 331 }
430 332
431 /* 333 /*
@@ -448,12 +350,12 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
448 */ 350 */
449 mask = 1 << key->hw_key_idx; 351 mask = 1 << key->hw_key_idx;
450 352
451 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg); 353 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
452 if (crypto->cmd == SET_KEY) 354 if (crypto->cmd == SET_KEY)
453 reg |= mask; 355 reg |= mask;
454 else if (crypto->cmd == DISABLE_KEY) 356 else if (crypto->cmd == DISABLE_KEY)
455 reg &= ~mask; 357 reg &= ~mask;
456 rt73usb_register_write(rt2x00dev, SEC_CSR0, reg); 358 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
457 359
458 return 0; 360 return 0;
459} 361}
@@ -478,10 +380,10 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
478 * When both registers are full, we drop the key, 380 * When both registers are full, we drop the key,
479 * otherwise we use the first invalid entry. 381 * otherwise we use the first invalid entry.
480 */ 382 */
481 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg); 383 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
482 if (reg && reg == ~0) { 384 if (reg && reg == ~0) {
483 key->hw_key_idx = 32; 385 key->hw_key_idx = 32;
484 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg); 386 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
485 if (reg && reg == ~0) 387 if (reg && reg == ~0)
486 return -ENOSPC; 388 return -ENOSPC;
487 } 389 }
@@ -509,14 +411,14 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
509 /* 411 /*
510 * Send the address and cipher type to the hardware register. 412 * Send the address and cipher type to the hardware register.
511 * This data fits within the CSR cache size, so we can use 413 * This data fits within the CSR cache size, so we can use
512 * rt73usb_register_multiwrite() directly. 414 * rt2x00usb_register_multiwrite() directly.
513 */ 415 */
514 memset(&addr_entry, 0, sizeof(addr_entry)); 416 memset(&addr_entry, 0, sizeof(addr_entry));
515 memcpy(&addr_entry, crypto->address, ETH_ALEN); 417 memcpy(&addr_entry, crypto->address, ETH_ALEN);
516 addr_entry.cipher = crypto->cipher; 418 addr_entry.cipher = crypto->cipher;
517 419
518 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); 420 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
519 rt73usb_register_multiwrite(rt2x00dev, reg, 421 rt2x00usb_register_multiwrite(rt2x00dev, reg,
520 &addr_entry, sizeof(addr_entry)); 422 &addr_entry, sizeof(addr_entry));
521 423
522 /* 424 /*
@@ -524,9 +426,9 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
524 * without this received frames will not be decrypted 426 * without this received frames will not be decrypted
525 * by the hardware. 427 * by the hardware.
526 */ 428 */
527 rt73usb_register_read(rt2x00dev, SEC_CSR4, &reg); 429 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
528 reg |= (1 << crypto->bssidx); 430 reg |= (1 << crypto->bssidx);
529 rt73usb_register_write(rt2x00dev, SEC_CSR4, reg); 431 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
530 432
531 /* 433 /*
532 * The driver does not support the IV/EIV generation 434 * The driver does not support the IV/EIV generation
@@ -549,21 +451,21 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
549 if (key->hw_key_idx < 32) { 451 if (key->hw_key_idx < 32) {
550 mask = 1 << key->hw_key_idx; 452 mask = 1 << key->hw_key_idx;
551 453
552 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg); 454 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
553 if (crypto->cmd == SET_KEY) 455 if (crypto->cmd == SET_KEY)
554 reg |= mask; 456 reg |= mask;
555 else if (crypto->cmd == DISABLE_KEY) 457 else if (crypto->cmd == DISABLE_KEY)
556 reg &= ~mask; 458 reg &= ~mask;
557 rt73usb_register_write(rt2x00dev, SEC_CSR2, reg); 459 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
558 } else { 460 } else {
559 mask = 1 << (key->hw_key_idx - 32); 461 mask = 1 << (key->hw_key_idx - 32);
560 462
561 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg); 463 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
562 if (crypto->cmd == SET_KEY) 464 if (crypto->cmd == SET_KEY)
563 reg |= mask; 465 reg |= mask;
564 else if (crypto->cmd == DISABLE_KEY) 466 else if (crypto->cmd == DISABLE_KEY)
565 reg &= ~mask; 467 reg &= ~mask;
566 rt73usb_register_write(rt2x00dev, SEC_CSR3, reg); 468 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
567 } 469 }
568 470
569 return 0; 471 return 0;
@@ -580,7 +482,7 @@ static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
580 * and broadcast frames will always be accepted since 482 * and broadcast frames will always be accepted since
581 * there is no filter for it at this time. 483 * there is no filter for it at this time.
582 */ 484 */
583 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 485 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
584 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, 486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
585 !(filter_flags & FIF_FCSFAIL)); 487 !(filter_flags & FIF_FCSFAIL));
586 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
@@ -598,7 +500,7 @@ static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
598 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0); 500 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
599 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 501 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
600 !(filter_flags & FIF_CONTROL)); 502 !(filter_flags & FIF_CONTROL));
601 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 503 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
602} 504}
603 505
604static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev, 506static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
@@ -617,16 +519,16 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
617 * bits which (when set to 0) will invalidate the entire beacon. 519 * bits which (when set to 0) will invalidate the entire beacon.
618 */ 520 */
619 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); 521 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
620 rt73usb_register_write(rt2x00dev, beacon_base, 0); 522 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
621 523
622 /* 524 /*
623 * Enable synchronisation. 525 * Enable synchronisation.
624 */ 526 */
625 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 527 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
626 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); 528 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
627 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 529 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
628 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); 530 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
629 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 531 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
630 } 532 }
631 533
632 if (flags & CONFIG_UPDATE_MAC) { 534 if (flags & CONFIG_UPDATE_MAC) {
@@ -634,7 +536,7 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
634 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); 536 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
635 conf->mac[1] = cpu_to_le32(reg); 537 conf->mac[1] = cpu_to_le32(reg);
636 538
637 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, 539 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
638 conf->mac, sizeof(conf->mac)); 540 conf->mac, sizeof(conf->mac));
639 } 541 }
640 542
@@ -643,7 +545,7 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
643 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3); 545 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
644 conf->bssid[1] = cpu_to_le32(reg); 546 conf->bssid[1] = cpu_to_le32(reg);
645 547
646 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, 548 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
647 conf->bssid, sizeof(conf->bssid)); 549 conf->bssid, sizeof(conf->bssid));
648 } 550 }
649} 551}
@@ -653,26 +555,26 @@ static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
653{ 555{
654 u32 reg; 556 u32 reg;
655 557
656 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 558 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
657 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout); 559 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
658 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 560 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
659 561
660 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 562 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
661 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 563 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
662 !!erp->short_preamble); 564 !!erp->short_preamble);
663 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); 565 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
664 566
665 rt73usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates); 567 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
666 568
667 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg); 569 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
668 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time); 570 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
669 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); 571 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
670 572
671 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg); 573 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
672 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs); 574 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
673 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 575 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
674 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs); 576 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
675 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg); 577 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
676} 578}
677 579
678static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 580static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
@@ -818,14 +720,14 @@ static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
818 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 720 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
819 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); 721 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
820 722
821 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg); 723 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
822 724
823 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 725 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
824 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)); 726 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
825 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 727 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
826 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)); 728 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
827 729
828 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg); 730 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
829 731
830 if (rt2x00_rf(&rt2x00dev->chip, RF5226) || 732 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
831 rt2x00_rf(&rt2x00dev->chip, RF5225)) 733 rt2x00_rf(&rt2x00dev->chip, RF5225))
@@ -915,12 +817,12 @@ static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
915{ 817{
916 u32 reg; 818 u32 reg;
917 819
918 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 820 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
919 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, 821 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
920 libconf->conf->long_frame_max_tx_count); 822 libconf->conf->long_frame_max_tx_count);
921 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, 823 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
922 libconf->conf->short_frame_max_tx_count); 824 libconf->conf->short_frame_max_tx_count);
923 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); 825 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
924} 826}
925 827
926static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev, 828static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
@@ -928,18 +830,18 @@ static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
928{ 830{
929 u32 reg; 831 u32 reg;
930 832
931 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 833 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
932 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 834 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
933 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 835 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
934 836
935 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 837 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
936 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 838 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
937 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); 839 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
938 840
939 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 841 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
940 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 842 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
941 libconf->conf->beacon_int * 16); 843 libconf->conf->beacon_int * 16);
942 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 844 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
943} 845}
944 846
945static void rt73usb_config(struct rt2x00_dev *rt2x00dev, 847static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
@@ -972,13 +874,13 @@ static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
972 /* 874 /*
973 * Update FCS error count from register. 875 * Update FCS error count from register.
974 */ 876 */
975 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg); 877 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
976 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); 878 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
977 879
978 /* 880 /*
979 * Update False CCA count from register. 881 * Update False CCA count from register.
980 */ 882 */
981 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg); 883 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
982 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); 884 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
983} 885}
984 886
@@ -1138,7 +1040,7 @@ static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1138 * Wait for stable hardware. 1040 * Wait for stable hardware.
1139 */ 1041 */
1140 for (i = 0; i < 100; i++) { 1042 for (i = 0; i < 100; i++) {
1141 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1043 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1142 if (reg) 1044 if (reg)
1143 break; 1045 break;
1144 msleep(1); 1046 msleep(1);
@@ -1180,13 +1082,13 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1180{ 1082{
1181 u32 reg; 1083 u32 reg;
1182 1084
1183 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 1085 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1184 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1); 1086 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1185 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); 1087 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1186 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0); 1088 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1187 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1089 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1188 1090
1189 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg); 1091 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1190 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ 1092 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1191 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1); 1093 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1192 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ 1094 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
@@ -1195,12 +1097,12 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1195 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1); 1097 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1196 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ 1098 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1197 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1); 1099 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1198 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg); 1100 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1199 1101
1200 /* 1102 /*
1201 * CCK TXD BBP registers 1103 * CCK TXD BBP registers
1202 */ 1104 */
1203 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg); 1105 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1204 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13); 1106 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1205 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1); 1107 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1206 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12); 1108 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
@@ -1209,77 +1111,77 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1209 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1); 1111 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1210 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10); 1112 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1211 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1); 1113 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1212 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg); 1114 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1213 1115
1214 /* 1116 /*
1215 * OFDM TXD BBP registers 1117 * OFDM TXD BBP registers
1216 */ 1118 */
1217 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg); 1119 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1218 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7); 1120 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1219 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1); 1121 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1220 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6); 1122 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1221 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1); 1123 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1222 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5); 1124 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1223 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1); 1125 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1224 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg); 1126 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1225 1127
1226 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg); 1128 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1227 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59); 1129 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1228 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53); 1130 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1229 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49); 1131 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1230 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46); 1132 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1231 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg); 1133 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1232 1134
1233 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg); 1135 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1234 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44); 1136 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1235 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42); 1137 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1236 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42); 1138 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1237 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42); 1139 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1238 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg); 1140 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1239 1141
1240 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1142 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1241 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0); 1143 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1242 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); 1144 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1243 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0); 1145 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1244 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1146 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1245 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1147 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1246 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); 1148 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1247 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1149 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1248 1150
1249 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); 1151 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1250 1152
1251 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg); 1153 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1252 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); 1154 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1253 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg); 1155 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1254 1156
1255 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); 1157 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1256 1158
1257 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 1159 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1258 return -EBUSY; 1160 return -EBUSY;
1259 1161
1260 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); 1162 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1261 1163
1262 /* 1164 /*
1263 * Invalidate all Shared Keys (SEC_CSR0), 1165 * Invalidate all Shared Keys (SEC_CSR0),
1264 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) 1166 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1265 */ 1167 */
1266 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); 1168 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1267 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); 1169 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1268 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); 1170 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1269 1171
1270 reg = 0x000023b0; 1172 reg = 0x000023b0;
1271 if (rt2x00_rf(&rt2x00dev->chip, RF5225) || 1173 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1272 rt2x00_rf(&rt2x00dev->chip, RF2527)) 1174 rt2x00_rf(&rt2x00dev->chip, RF2527))
1273 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1); 1175 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1274 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg); 1176 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1275 1177
1276 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); 1178 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1277 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); 1179 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1278 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); 1180 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1279 1181
1280 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg); 1182 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1281 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0); 1183 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1282 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); 1184 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1283 1185
1284 /* 1186 /*
1285 * Clear all beacons 1187 * Clear all beacons
@@ -1287,36 +1189,36 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1287 * the first byte since that byte contains the VALID and OWNER 1189 * the first byte since that byte contains the VALID and OWNER
1288 * bits which (when set to 0) will invalidate the entire beacon. 1190 * bits which (when set to 0) will invalidate the entire beacon.
1289 */ 1191 */
1290 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1192 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1291 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1193 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1292 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1194 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1293 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1195 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1294 1196
1295 /* 1197 /*
1296 * We must clear the error counters. 1198 * We must clear the error counters.
1297 * These registers are cleared on read, 1199 * These registers are cleared on read,
1298 * so we may pass a useless variable to store the value. 1200 * so we may pass a useless variable to store the value.
1299 */ 1201 */
1300 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg); 1202 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1301 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg); 1203 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1302 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg); 1204 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1303 1205
1304 /* 1206 /*
1305 * Reset MAC and BBP registers. 1207 * Reset MAC and BBP registers.
1306 */ 1208 */
1307 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1209 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1308 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); 1210 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1309 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); 1211 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1310 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1212 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1311 1213
1312 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1214 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1313 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); 1215 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1314 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); 1216 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1315 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1217 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1316 1218
1317 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1219 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1318 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); 1220 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1319 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1221 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1320 1222
1321 return 0; 1223 return 0;
1322} 1224}
@@ -1394,11 +1296,11 @@ static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1394{ 1296{
1395 u32 reg; 1297 u32 reg;
1396 1298
1397 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 1299 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1398 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1300 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1399 (state == STATE_RADIO_RX_OFF) || 1301 (state == STATE_RADIO_RX_OFF) ||
1400 (state == STATE_RADIO_RX_OFF_LINK)); 1302 (state == STATE_RADIO_RX_OFF_LINK));
1401 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1303 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1402} 1304}
1403 1305
1404static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) 1306static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1415,12 +1317,12 @@ static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1415 1317
1416static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) 1318static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1417{ 1319{
1418 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); 1320 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1419 1321
1420 /* 1322 /*
1421 * Disable synchronisation. 1323 * Disable synchronisation.
1422 */ 1324 */
1423 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0); 1325 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1424 1326
1425 rt2x00usb_disable_radio(rt2x00dev); 1327 rt2x00usb_disable_radio(rt2x00dev);
1426} 1328}
@@ -1433,10 +1335,10 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1433 1335
1434 put_to_sleep = (state != STATE_AWAKE); 1336 put_to_sleep = (state != STATE_AWAKE);
1435 1337
1436 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); 1338 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1437 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); 1339 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1438 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); 1340 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1439 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg); 1341 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1440 1342
1441 /* 1343 /*
1442 * Device is not guaranteed to be in the requested state yet. 1344 * Device is not guaranteed to be in the requested state yet.
@@ -1444,7 +1346,7 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1444 * device has entered the correct state. 1346 * device has entered the correct state.
1445 */ 1347 */
1446 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1348 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1447 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); 1349 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1448 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); 1350 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1449 if (state == !put_to_sleep) 1351 if (state == !put_to_sleep)
1450 return 0; 1352 return 0;
@@ -1584,11 +1486,11 @@ static void rt73usb_write_beacon(struct queue_entry *entry)
1584 * Disable beaconing while we are reloading the beacon data, 1486 * Disable beaconing while we are reloading the beacon data,
1585 * otherwise we might be sending out invalid data. 1487 * otherwise we might be sending out invalid data.
1586 */ 1488 */
1587 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1489 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1588 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); 1490 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1589 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1491 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1590 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1492 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1591 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1493 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1592 1494
1593 /* 1495 /*
1594 * Write entire beacon with descriptor to register. 1496 * Write entire beacon with descriptor to register.
@@ -1606,8 +1508,7 @@ static void rt73usb_write_beacon(struct queue_entry *entry)
1606 entry->skb = NULL; 1508 entry->skb = NULL;
1607} 1509}
1608 1510
1609static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev, 1511static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1610 struct sk_buff *skb)
1611{ 1512{
1612 int length; 1513 int length;
1613 1514
@@ -1615,8 +1516,8 @@ static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1615 * The length _must_ be a multiple of 4, 1516 * The length _must_ be a multiple of 4,
1616 * but it must _not_ be a multiple of the USB packet size. 1517 * but it must _not_ be a multiple of the USB packet size.
1617 */ 1518 */
1618 length = roundup(skb->len, 4); 1519 length = roundup(entry->skb->len, 4);
1619 length += (4 * !(length % rt2x00dev->usb_maxpacket)); 1520 length += (4 * !(length % entry->queue->usb_maxpacket));
1620 1521
1621 return length; 1522 return length;
1622} 1523}
@@ -1635,14 +1536,14 @@ static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1635 * For Wi-Fi faily generated beacons between participating stations. 1536 * For Wi-Fi faily generated beacons between participating stations.
1636 * Set TBTT phase adaptive adjustment step to 8us (default 16us) 1537 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1637 */ 1538 */
1638 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 1539 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1639 1540
1640 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1541 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1641 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) { 1542 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1642 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); 1543 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1643 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); 1544 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1644 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 1545 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1645 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1546 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1646 } 1547 }
1647} 1548}
1648 1549
@@ -1881,7 +1782,7 @@ static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1881 * Identify RF chipset. 1782 * Identify RF chipset.
1882 */ 1783 */
1883 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1784 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1884 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1785 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1885 rt2x00_set_chip(rt2x00dev, RT2571, value, reg); 1786 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1886 1787
1887 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) { 1788 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
@@ -2235,33 +2136,33 @@ static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2235 field.bit_offset = queue_idx * 16; 2136 field.bit_offset = queue_idx * 16;
2236 field.bit_mask = 0xffff << field.bit_offset; 2137 field.bit_mask = 0xffff << field.bit_offset;
2237 2138
2238 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg); 2139 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2239 rt2x00_set_field32(&reg, field, queue->txop); 2140 rt2x00_set_field32(&reg, field, queue->txop);
2240 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg); 2141 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2241 } else if (queue_idx < 4) { 2142 } else if (queue_idx < 4) {
2242 field.bit_offset = (queue_idx - 2) * 16; 2143 field.bit_offset = (queue_idx - 2) * 16;
2243 field.bit_mask = 0xffff << field.bit_offset; 2144 field.bit_mask = 0xffff << field.bit_offset;
2244 2145
2245 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg); 2146 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2246 rt2x00_set_field32(&reg, field, queue->txop); 2147 rt2x00_set_field32(&reg, field, queue->txop);
2247 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg); 2148 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2248 } 2149 }
2249 2150
2250 /* Update WMM registers */ 2151 /* Update WMM registers */
2251 field.bit_offset = queue_idx * 4; 2152 field.bit_offset = queue_idx * 4;
2252 field.bit_mask = 0xf << field.bit_offset; 2153 field.bit_mask = 0xf << field.bit_offset;
2253 2154
2254 rt73usb_register_read(rt2x00dev, AIFSN_CSR, &reg); 2155 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2255 rt2x00_set_field32(&reg, field, queue->aifs); 2156 rt2x00_set_field32(&reg, field, queue->aifs);
2256 rt73usb_register_write(rt2x00dev, AIFSN_CSR, reg); 2157 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2257 2158
2258 rt73usb_register_read(rt2x00dev, CWMIN_CSR, &reg); 2159 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2259 rt2x00_set_field32(&reg, field, queue->cw_min); 2160 rt2x00_set_field32(&reg, field, queue->cw_min);
2260 rt73usb_register_write(rt2x00dev, CWMIN_CSR, reg); 2161 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2261 2162
2262 rt73usb_register_read(rt2x00dev, CWMAX_CSR, &reg); 2163 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2263 rt2x00_set_field32(&reg, field, queue->cw_max); 2164 rt2x00_set_field32(&reg, field, queue->cw_max);
2264 rt73usb_register_write(rt2x00dev, CWMAX_CSR, reg); 2165 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2265 2166
2266 return 0; 2167 return 0;
2267} 2168}
@@ -2279,9 +2180,9 @@ static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2279 u64 tsf; 2180 u64 tsf;
2280 u32 reg; 2181 u32 reg;
2281 2182
2282 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg); 2183 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2283 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; 2184 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2284 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg); 2185 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2285 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); 2186 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2286 2187
2287 return tsf; 2188 return tsf;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 15:45:55 -0500