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path: root/drivers/net/wireless/rt2x00/rt73usb.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt73usb.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c689
1 files changed, 288 insertions, 401 deletions
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index 934f8e03c5aa..d638a8a59370 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -46,7 +46,7 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
46/* 46/*
47 * Register access. 47 * Register access.
48 * All access to the CSR registers will go through the methods 48 * All access to the CSR registers will go through the methods
49 * rt73usb_register_read and rt73usb_register_write. 49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access, 50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this. 51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits, 52 * These indirect registers work with busy bits,
@@ -55,113 +55,35 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
55 * between each attampt. When the busy bit is still set at that time, 55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed, 56 * the access attempt is considered to have failed,
57 * and we will print an error. 57 * and we will print an error.
58 * The _lock versions must be used if you already hold the usb_cache_mutex 58 * The _lock versions must be used if you already hold the csr_mutex
59 */ 59 */
60static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev, 60#define WAIT_FOR_BBP(__dev, __reg) \
61 const unsigned int offset, u32 *value) 61 rt2x00usb_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
62{ 62#define WAIT_FOR_RF(__dev, __reg) \
63 __le32 reg; 63 rt2x00usb_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
64 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
65 USB_VENDOR_REQUEST_IN, offset,
66 &reg, sizeof(u32), REGISTER_TIMEOUT);
67 *value = le32_to_cpu(reg);
68}
69
70static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
71 const unsigned int offset, u32 *value)
72{
73 __le32 reg;
74 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
75 USB_VENDOR_REQUEST_IN, offset,
76 &reg, sizeof(u32), REGISTER_TIMEOUT);
77 *value = le32_to_cpu(reg);
78}
79
80static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
81 const unsigned int offset,
82 void *value, const u32 length)
83{
84 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
85 USB_VENDOR_REQUEST_IN, offset,
86 value, length,
87 REGISTER_TIMEOUT32(length));
88}
89
90static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
91 const unsigned int offset, u32 value)
92{
93 __le32 reg = cpu_to_le32(value);
94 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
95 USB_VENDOR_REQUEST_OUT, offset,
96 &reg, sizeof(u32), REGISTER_TIMEOUT);
97}
98
99static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
100 const unsigned int offset, u32 value)
101{
102 __le32 reg = cpu_to_le32(value);
103 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
104 USB_VENDOR_REQUEST_OUT, offset,
105 &reg, sizeof(u32), REGISTER_TIMEOUT);
106}
107
108static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
109 const unsigned int offset,
110 void *value, const u32 length)
111{
112 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
113 USB_VENDOR_REQUEST_OUT, offset,
114 value, length,
115 REGISTER_TIMEOUT32(length));
116}
117
118static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
119{
120 u32 reg;
121 unsigned int i;
122
123 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
124 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, &reg);
125 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
126 break;
127 udelay(REGISTER_BUSY_DELAY);
128 }
129
130 return reg;
131}
132 64
133static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev, 65static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u8 value) 66 const unsigned int word, const u8 value)
135{ 67{
136 u32 reg; 68 u32 reg;
137 69
138 mutex_lock(&rt2x00dev->usb_cache_mutex); 70 mutex_lock(&rt2x00dev->csr_mutex);
139 71
140 /* 72 /*
141 * Wait until the BBP becomes ready. 73 * Wait until the BBP becomes available, afterwards we
74 * can safely write the new data into the register.
142 */ 75 */
143 reg = rt73usb_bbp_check(rt2x00dev); 76 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
144 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) 77 reg = 0;
145 goto exit_fail; 78 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
146 79 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
147 /* 80 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
148 * Write the data into the BBP. 81 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
149 */ 82
150 reg = 0; 83 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
151 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value); 84 }
152 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
153 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
154 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
155
156 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
157 mutex_unlock(&rt2x00dev->usb_cache_mutex);
158
159 return;
160
161exit_fail:
162 mutex_unlock(&rt2x00dev->usb_cache_mutex);
163 85
164 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n"); 86 mutex_unlock(&rt2x00dev->csr_mutex);
165} 87}
166 88
167static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev, 89static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
@@ -169,123 +91,95 @@ static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
169{ 91{
170 u32 reg; 92 u32 reg;
171 93
172 mutex_lock(&rt2x00dev->usb_cache_mutex); 94 mutex_lock(&rt2x00dev->csr_mutex);
173
174 /*
175 * Wait until the BBP becomes ready.
176 */
177 reg = rt73usb_bbp_check(rt2x00dev);
178 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
179 goto exit_fail;
180 95
181 /* 96 /*
182 * Write the request into the BBP. 97 * Wait until the BBP becomes available, afterwards we
98 * can safely write the read request into the register.
99 * After the data has been written, we wait until hardware
100 * returns the correct value, if at any time the register
101 * doesn't become available in time, reg will be 0xffffffff
102 * which means we return 0xff to the caller.
183 */ 103 */
184 reg = 0; 104 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
185 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word); 105 reg = 0;
186 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1); 106 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
187 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1); 107 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
108 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
188 109
189 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg); 110 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
190 111
191 /* 112 WAIT_FOR_BBP(rt2x00dev, &reg);
192 * Wait until the BBP becomes ready. 113 }
193 */
194 reg = rt73usb_bbp_check(rt2x00dev);
195 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY))
196 goto exit_fail;
197 114
198 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); 115 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
199 mutex_unlock(&rt2x00dev->usb_cache_mutex);
200
201 return;
202
203exit_fail:
204 mutex_unlock(&rt2x00dev->usb_cache_mutex);
205 116
206 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n"); 117 mutex_unlock(&rt2x00dev->csr_mutex);
207 *value = 0xff;
208} 118}
209 119
210static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev, 120static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
211 const unsigned int word, const u32 value) 121 const unsigned int word, const u32 value)
212{ 122{
213 u32 reg; 123 u32 reg;
214 unsigned int i;
215 124
216 if (!word) 125 if (!word)
217 return; 126 return;
218 127
219 mutex_lock(&rt2x00dev->usb_cache_mutex); 128 mutex_lock(&rt2x00dev->csr_mutex);
220
221 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
222 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, &reg);
223 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
224 goto rf_write;
225 udelay(REGISTER_BUSY_DELAY);
226 }
227
228 mutex_unlock(&rt2x00dev->usb_cache_mutex);
229 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
230 return;
231
232rf_write:
233 reg = 0;
234 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
235 129
236 /* 130 /*
237 * RF5225 and RF2527 contain 21 bits per RF register value, 131 * Wait until the RF becomes available, afterwards we
238 * all others contain 20 bits. 132 * can safely write the new data into the register.
239 */ 133 */
240 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 134 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
241 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) || 135 reg = 0;
242 rt2x00_rf(&rt2x00dev->chip, RF2527))); 136 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
243 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0); 137 /*
244 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1); 138 * RF5225 and RF2527 contain 21 bits per RF register value,
245 139 * all others contain 20 bits.
246 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg); 140 */
247 rt2x00_rf_write(rt2x00dev, word, value); 141 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS,
248 mutex_unlock(&rt2x00dev->usb_cache_mutex); 142 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
249} 143 rt2x00_rf(&rt2x00dev->chip, RF2527)));
250 144 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
251#ifdef CONFIG_RT2X00_LIB_DEBUGFS 145 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
252#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) ) 146
253 147 rt2x00usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
254static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev, 148 rt2x00_rf_write(rt2x00dev, word, value);
255 const unsigned int word, u32 *data) 149 }
256{
257 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
258}
259 150
260static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev, 151 mutex_unlock(&rt2x00dev->csr_mutex);
261 const unsigned int word, u32 data)
262{
263 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
264} 152}
265 153
154#ifdef CONFIG_RT2X00_LIB_DEBUGFS
266static const struct rt2x00debug rt73usb_rt2x00debug = { 155static const struct rt2x00debug rt73usb_rt2x00debug = {
267 .owner = THIS_MODULE, 156 .owner = THIS_MODULE,
268 .csr = { 157 .csr = {
269 .read = rt73usb_read_csr, 158 .read = rt2x00usb_register_read,
270 .write = rt73usb_write_csr, 159 .write = rt2x00usb_register_write,
160 .flags = RT2X00DEBUGFS_OFFSET,
161 .word_base = CSR_REG_BASE,
271 .word_size = sizeof(u32), 162 .word_size = sizeof(u32),
272 .word_count = CSR_REG_SIZE / sizeof(u32), 163 .word_count = CSR_REG_SIZE / sizeof(u32),
273 }, 164 },
274 .eeprom = { 165 .eeprom = {
275 .read = rt2x00_eeprom_read, 166 .read = rt2x00_eeprom_read,
276 .write = rt2x00_eeprom_write, 167 .write = rt2x00_eeprom_write,
168 .word_base = EEPROM_BASE,
277 .word_size = sizeof(u16), 169 .word_size = sizeof(u16),
278 .word_count = EEPROM_SIZE / sizeof(u16), 170 .word_count = EEPROM_SIZE / sizeof(u16),
279 }, 171 },
280 .bbp = { 172 .bbp = {
281 .read = rt73usb_bbp_read, 173 .read = rt73usb_bbp_read,
282 .write = rt73usb_bbp_write, 174 .write = rt73usb_bbp_write,
175 .word_base = BBP_BASE,
283 .word_size = sizeof(u8), 176 .word_size = sizeof(u8),
284 .word_count = BBP_SIZE / sizeof(u8), 177 .word_count = BBP_SIZE / sizeof(u8),
285 }, 178 },
286 .rf = { 179 .rf = {
287 .read = rt2x00_rf_read, 180 .read = rt2x00_rf_read,
288 .write = rt73usb_rf_write, 181 .write = rt73usb_rf_write,
182 .word_base = RF_BASE,
289 .word_size = sizeof(u32), 183 .word_size = sizeof(u32),
290 .word_count = RF_SIZE / sizeof(u32), 184 .word_count = RF_SIZE / sizeof(u32),
291 }, 185 },
@@ -341,10 +235,10 @@ static int rt73usb_blink_set(struct led_classdev *led_cdev,
341 container_of(led_cdev, struct rt2x00_led, led_dev); 235 container_of(led_cdev, struct rt2x00_led, led_dev);
342 u32 reg; 236 u32 reg;
343 237
344 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, &reg); 238 rt2x00usb_register_read(led->rt2x00dev, MAC_CSR14, &reg);
345 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on); 239 rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
346 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off); 240 rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
347 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg); 241 rt2x00usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
348 242
349 return 0; 243 return 0;
350} 244}
@@ -387,7 +281,7 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
387 */ 281 */
388 mask = (0xf << crypto->bssidx); 282 mask = (0xf << crypto->bssidx);
389 283
390 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg); 284 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
391 reg &= mask; 285 reg &= mask;
392 286
393 if (reg && reg == mask) 287 if (reg && reg == mask)
@@ -424,16 +318,16 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
424 field.bit_offset = (3 * key->hw_key_idx); 318 field.bit_offset = (3 * key->hw_key_idx);
425 field.bit_mask = 0x7 << field.bit_offset; 319 field.bit_mask = 0x7 << field.bit_offset;
426 320
427 rt73usb_register_read(rt2x00dev, SEC_CSR1, &reg); 321 rt2x00usb_register_read(rt2x00dev, SEC_CSR1, &reg);
428 rt2x00_set_field32(&reg, field, crypto->cipher); 322 rt2x00_set_field32(&reg, field, crypto->cipher);
429 rt73usb_register_write(rt2x00dev, SEC_CSR1, reg); 323 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, reg);
430 } else { 324 } else {
431 field.bit_offset = (3 * (key->hw_key_idx - 8)); 325 field.bit_offset = (3 * (key->hw_key_idx - 8));
432 field.bit_mask = 0x7 << field.bit_offset; 326 field.bit_mask = 0x7 << field.bit_offset;
433 327
434 rt73usb_register_read(rt2x00dev, SEC_CSR5, &reg); 328 rt2x00usb_register_read(rt2x00dev, SEC_CSR5, &reg);
435 rt2x00_set_field32(&reg, field, crypto->cipher); 329 rt2x00_set_field32(&reg, field, crypto->cipher);
436 rt73usb_register_write(rt2x00dev, SEC_CSR5, reg); 330 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, reg);
437 } 331 }
438 332
439 /* 333 /*
@@ -456,12 +350,12 @@ static int rt73usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
456 */ 350 */
457 mask = 1 << key->hw_key_idx; 351 mask = 1 << key->hw_key_idx;
458 352
459 rt73usb_register_read(rt2x00dev, SEC_CSR0, &reg); 353 rt2x00usb_register_read(rt2x00dev, SEC_CSR0, &reg);
460 if (crypto->cmd == SET_KEY) 354 if (crypto->cmd == SET_KEY)
461 reg |= mask; 355 reg |= mask;
462 else if (crypto->cmd == DISABLE_KEY) 356 else if (crypto->cmd == DISABLE_KEY)
463 reg &= ~mask; 357 reg &= ~mask;
464 rt73usb_register_write(rt2x00dev, SEC_CSR0, reg); 358 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, reg);
465 359
466 return 0; 360 return 0;
467} 361}
@@ -486,10 +380,10 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
486 * When both registers are full, we drop the key, 380 * When both registers are full, we drop the key,
487 * otherwise we use the first invalid entry. 381 * otherwise we use the first invalid entry.
488 */ 382 */
489 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg); 383 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
490 if (reg && reg == ~0) { 384 if (reg && reg == ~0) {
491 key->hw_key_idx = 32; 385 key->hw_key_idx = 32;
492 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg); 386 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
493 if (reg && reg == ~0) 387 if (reg && reg == ~0)
494 return -ENOSPC; 388 return -ENOSPC;
495 } 389 }
@@ -517,14 +411,14 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
517 /* 411 /*
518 * Send the address and cipher type to the hardware register. 412 * Send the address and cipher type to the hardware register.
519 * This data fits within the CSR cache size, so we can use 413 * This data fits within the CSR cache size, so we can use
520 * rt73usb_register_multiwrite() directly. 414 * rt2x00usb_register_multiwrite() directly.
521 */ 415 */
522 memset(&addr_entry, 0, sizeof(addr_entry)); 416 memset(&addr_entry, 0, sizeof(addr_entry));
523 memcpy(&addr_entry, crypto->address, ETH_ALEN); 417 memcpy(&addr_entry, crypto->address, ETH_ALEN);
524 addr_entry.cipher = crypto->cipher; 418 addr_entry.cipher = crypto->cipher;
525 419
526 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); 420 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
527 rt73usb_register_multiwrite(rt2x00dev, reg, 421 rt2x00usb_register_multiwrite(rt2x00dev, reg,
528 &addr_entry, sizeof(addr_entry)); 422 &addr_entry, sizeof(addr_entry));
529 423
530 /* 424 /*
@@ -532,9 +426,9 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
532 * without this received frames will not be decrypted 426 * without this received frames will not be decrypted
533 * by the hardware. 427 * by the hardware.
534 */ 428 */
535 rt73usb_register_read(rt2x00dev, SEC_CSR4, &reg); 429 rt2x00usb_register_read(rt2x00dev, SEC_CSR4, &reg);
536 reg |= (1 << crypto->bssidx); 430 reg |= (1 << crypto->bssidx);
537 rt73usb_register_write(rt2x00dev, SEC_CSR4, reg); 431 rt2x00usb_register_write(rt2x00dev, SEC_CSR4, reg);
538 432
539 /* 433 /*
540 * The driver does not support the IV/EIV generation 434 * The driver does not support the IV/EIV generation
@@ -557,21 +451,21 @@ static int rt73usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
557 if (key->hw_key_idx < 32) { 451 if (key->hw_key_idx < 32) {
558 mask = 1 << key->hw_key_idx; 452 mask = 1 << key->hw_key_idx;
559 453
560 rt73usb_register_read(rt2x00dev, SEC_CSR2, &reg); 454 rt2x00usb_register_read(rt2x00dev, SEC_CSR2, &reg);
561 if (crypto->cmd == SET_KEY) 455 if (crypto->cmd == SET_KEY)
562 reg |= mask; 456 reg |= mask;
563 else if (crypto->cmd == DISABLE_KEY) 457 else if (crypto->cmd == DISABLE_KEY)
564 reg &= ~mask; 458 reg &= ~mask;
565 rt73usb_register_write(rt2x00dev, SEC_CSR2, reg); 459 rt2x00usb_register_write(rt2x00dev, SEC_CSR2, reg);
566 } else { 460 } else {
567 mask = 1 << (key->hw_key_idx - 32); 461 mask = 1 << (key->hw_key_idx - 32);
568 462
569 rt73usb_register_read(rt2x00dev, SEC_CSR3, &reg); 463 rt2x00usb_register_read(rt2x00dev, SEC_CSR3, &reg);
570 if (crypto->cmd == SET_KEY) 464 if (crypto->cmd == SET_KEY)
571 reg |= mask; 465 reg |= mask;
572 else if (crypto->cmd == DISABLE_KEY) 466 else if (crypto->cmd == DISABLE_KEY)
573 reg &= ~mask; 467 reg &= ~mask;
574 rt73usb_register_write(rt2x00dev, SEC_CSR3, reg); 468 rt2x00usb_register_write(rt2x00dev, SEC_CSR3, reg);
575 } 469 }
576 470
577 return 0; 471 return 0;
@@ -588,7 +482,7 @@ static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
588 * and broadcast frames will always be accepted since 482 * and broadcast frames will always be accepted since
589 * there is no filter for it at this time. 483 * there is no filter for it at this time.
590 */ 484 */
591 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 485 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
592 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC, 486 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
593 !(filter_flags & FIF_FCSFAIL)); 487 !(filter_flags & FIF_FCSFAIL));
594 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL, 488 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
@@ -606,7 +500,7 @@ static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
606 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0); 500 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
607 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS, 501 rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
608 !(filter_flags & FIF_CONTROL)); 502 !(filter_flags & FIF_CONTROL));
609 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 503 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
610} 504}
611 505
612static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev, 506static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
@@ -625,16 +519,16 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
625 * bits which (when set to 0) will invalidate the entire beacon. 519 * bits which (when set to 0) will invalidate the entire beacon.
626 */ 520 */
627 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx); 521 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
628 rt73usb_register_write(rt2x00dev, beacon_base, 0); 522 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
629 523
630 /* 524 /*
631 * Enable synchronisation. 525 * Enable synchronisation.
632 */ 526 */
633 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 527 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
634 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); 528 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
635 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync); 529 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
636 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); 530 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
637 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 531 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
638 } 532 }
639 533
640 if (flags & CONFIG_UPDATE_MAC) { 534 if (flags & CONFIG_UPDATE_MAC) {
@@ -642,7 +536,7 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
642 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); 536 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
643 conf->mac[1] = cpu_to_le32(reg); 537 conf->mac[1] = cpu_to_le32(reg);
644 538
645 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, 539 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR2,
646 conf->mac, sizeof(conf->mac)); 540 conf->mac, sizeof(conf->mac));
647 } 541 }
648 542
@@ -651,7 +545,7 @@ static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
651 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3); 545 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
652 conf->bssid[1] = cpu_to_le32(reg); 546 conf->bssid[1] = cpu_to_le32(reg);
653 547
654 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, 548 rt2x00usb_register_multiwrite(rt2x00dev, MAC_CSR4,
655 conf->bssid, sizeof(conf->bssid)); 549 conf->bssid, sizeof(conf->bssid));
656 } 550 }
657} 551}
@@ -661,95 +555,26 @@ static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
661{ 555{
662 u32 reg; 556 u32 reg;
663 557
664 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 558 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
665 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout); 559 rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
666 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 560 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
667 561
668 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 562 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
669 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE, 563 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
670 !!erp->short_preamble); 564 !!erp->short_preamble);
671 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); 565 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
672}
673
674static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
675 struct rt2x00lib_conf *libconf)
676{
677 u16 eeprom;
678 short lna_gain = 0;
679
680 if (libconf->band == IEEE80211_BAND_2GHZ) {
681 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
682 lna_gain += 14;
683
684 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
685 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
686 } else {
687 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
688 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
689 }
690
691 rt2x00dev->lna_gain = lna_gain;
692}
693
694static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
695 const int basic_rate_mask)
696{
697 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
698}
699
700static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
701 struct rf_channel *rf, const int txpower)
702{
703 u8 r3;
704 u8 r94;
705 u8 smart;
706
707 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
708 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
709
710 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
711 rt2x00_rf(&rt2x00dev->chip, RF2527));
712
713 rt73usb_bbp_read(rt2x00dev, 3, &r3);
714 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
715 rt73usb_bbp_write(rt2x00dev, 3, r3);
716
717 r94 = 6;
718 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
719 r94 += txpower - MAX_TXPOWER;
720 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
721 r94 += txpower;
722 rt73usb_bbp_write(rt2x00dev, 94, r94);
723
724 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
725 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
726 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
727 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
728 566
729 rt73usb_rf_write(rt2x00dev, 1, rf->rf1); 567 rt2x00usb_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
730 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
731 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
732 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
733 568
734 rt73usb_rf_write(rt2x00dev, 1, rf->rf1); 569 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
735 rt73usb_rf_write(rt2x00dev, 2, rf->rf2); 570 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
736 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); 571 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
737 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
738 572
739 udelay(10); 573 rt2x00usb_register_read(rt2x00dev, MAC_CSR8, &reg);
740} 574 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
741 575 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
742static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, 576 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
743 const int txpower) 577 rt2x00usb_register_write(rt2x00dev, MAC_CSR8, reg);
744{
745 struct rf_channel rf;
746
747 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
748 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
749 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
750 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
751
752 rt73usb_config_channel(rt2x00dev, &rf, txpower);
753} 578}
754 579
755static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev, 580static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
@@ -869,8 +694,8 @@ static const struct antenna_sel antenna_sel_bg[] = {
869 { 98, { 0x48, 0x48 } }, 694 { 98, { 0x48, 0x48 } },
870}; 695};
871 696
872static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev, 697static void rt73usb_config_ant(struct rt2x00_dev *rt2x00dev,
873 struct antenna_setup *ant) 698 struct antenna_setup *ant)
874{ 699{
875 const struct antenna_sel *sel; 700 const struct antenna_sel *sel;
876 unsigned int lna; 701 unsigned int lna;
@@ -895,14 +720,14 @@ static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
895 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++) 720 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
896 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); 721 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
897 722
898 rt73usb_register_read(rt2x00dev, PHY_CSR0, &reg); 723 rt2x00usb_register_read(rt2x00dev, PHY_CSR0, &reg);
899 724
900 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG, 725 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
901 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)); 726 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
902 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A, 727 rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
903 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)); 728 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
904 729
905 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg); 730 rt2x00usb_register_write(rt2x00dev, PHY_CSR0, reg);
906 731
907 if (rt2x00_rf(&rt2x00dev->chip, RF5226) || 732 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
908 rt2x00_rf(&rt2x00dev->chip, RF5225)) 733 rt2x00_rf(&rt2x00dev->chip, RF5225))
@@ -912,33 +737,111 @@ static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
912 rt73usb_config_antenna_2x(rt2x00dev, ant); 737 rt73usb_config_antenna_2x(rt2x00dev, ant);
913} 738}
914 739
915static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev, 740static void rt73usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
916 struct rt2x00lib_conf *libconf) 741 struct rt2x00lib_conf *libconf)
917{ 742{
743 u16 eeprom;
744 short lna_gain = 0;
745
746 if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
747 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
748 lna_gain += 14;
749
750 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
751 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
752 } else {
753 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
754 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
755 }
756
757 rt2x00dev->lna_gain = lna_gain;
758}
759
760static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
761 struct rf_channel *rf, const int txpower)
762{
763 u8 r3;
764 u8 r94;
765 u8 smart;
766
767 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
768 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
769
770 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
771 rt2x00_rf(&rt2x00dev->chip, RF2527));
772
773 rt73usb_bbp_read(rt2x00dev, 3, &r3);
774 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
775 rt73usb_bbp_write(rt2x00dev, 3, r3);
776
777 r94 = 6;
778 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
779 r94 += txpower - MAX_TXPOWER;
780 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
781 r94 += txpower;
782 rt73usb_bbp_write(rt2x00dev, 94, r94);
783
784 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
785 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
786 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
787 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
788
789 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
790 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
791 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
792 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
793
794 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
795 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
796 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
797 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
798
799 udelay(10);
800}
801
802static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
803 const int txpower)
804{
805 struct rf_channel rf;
806
807 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
808 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
809 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
810 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
811
812 rt73usb_config_channel(rt2x00dev, &rf, txpower);
813}
814
815static void rt73usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
816 struct rt2x00lib_conf *libconf)
817{
918 u32 reg; 818 u32 reg;
919 819
920 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg); 820 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
921 rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time); 821 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
922 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); 822 libconf->conf->long_frame_max_tx_count);
823 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
824 libconf->conf->short_frame_max_tx_count);
825 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
826}
923 827
924 rt73usb_register_read(rt2x00dev, MAC_CSR8, &reg); 828static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
925 rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs); 829 struct rt2x00lib_conf *libconf)
926 rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); 830{
927 rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs); 831 u32 reg;
928 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
929 832
930 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 833 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
931 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); 834 rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
932 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 835 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
933 836
934 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg); 837 rt2x00usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
935 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1); 838 rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
936 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg); 839 rt2x00usb_register_write(rt2x00dev, TXRX_CSR4, reg);
937 840
938 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 841 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
939 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 842 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
940 libconf->conf->beacon_int * 16); 843 libconf->conf->beacon_int * 16);
941 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 844 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
942} 845}
943 846
944static void rt73usb_config(struct rt2x00_dev *rt2x00dev, 847static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
@@ -948,16 +851,15 @@ static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
948 /* Always recalculate LNA gain before changing configuration */ 851 /* Always recalculate LNA gain before changing configuration */
949 rt73usb_config_lna_gain(rt2x00dev, libconf); 852 rt73usb_config_lna_gain(rt2x00dev, libconf);
950 853
951 if (flags & CONFIG_UPDATE_PHYMODE) 854 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
952 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
953 if (flags & CONFIG_UPDATE_CHANNEL)
954 rt73usb_config_channel(rt2x00dev, &libconf->rf, 855 rt73usb_config_channel(rt2x00dev, &libconf->rf,
955 libconf->conf->power_level); 856 libconf->conf->power_level);
956 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL)) 857 if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
858 !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
957 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level); 859 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
958 if (flags & CONFIG_UPDATE_ANTENNA) 860 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
959 rt73usb_config_antenna(rt2x00dev, &libconf->ant); 861 rt73usb_config_retry_limit(rt2x00dev, libconf);
960 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT)) 862 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
961 rt73usb_config_duration(rt2x00dev, libconf); 863 rt73usb_config_duration(rt2x00dev, libconf);
962} 864}
963 865
@@ -972,13 +874,13 @@ static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
972 /* 874 /*
973 * Update FCS error count from register. 875 * Update FCS error count from register.
974 */ 876 */
975 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg); 877 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
976 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); 878 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
977 879
978 /* 880 /*
979 * Update False CCA count from register. 881 * Update False CCA count from register.
980 */ 882 */
981 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg); 883 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
982 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); 884 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
983} 885}
984 886
@@ -1138,7 +1040,7 @@ static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1138 * Wait for stable hardware. 1040 * Wait for stable hardware.
1139 */ 1041 */
1140 for (i = 0; i < 100; i++) { 1042 for (i = 0; i < 100; i++) {
1141 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1043 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1142 if (reg) 1044 if (reg)
1143 break; 1045 break;
1144 msleep(1); 1046 msleep(1);
@@ -1180,13 +1082,13 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1180{ 1082{
1181 u32 reg; 1083 u32 reg;
1182 1084
1183 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 1085 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1184 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1); 1086 rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1185 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0); 1087 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1186 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0); 1088 rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1187 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1089 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1188 1090
1189 rt73usb_register_read(rt2x00dev, TXRX_CSR1, &reg); 1091 rt2x00usb_register_read(rt2x00dev, TXRX_CSR1, &reg);
1190 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ 1092 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1191 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1); 1093 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1192 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ 1094 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
@@ -1195,12 +1097,12 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1195 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1); 1097 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1196 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ 1098 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1197 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1); 1099 rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1198 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg); 1100 rt2x00usb_register_write(rt2x00dev, TXRX_CSR1, reg);
1199 1101
1200 /* 1102 /*
1201 * CCK TXD BBP registers 1103 * CCK TXD BBP registers
1202 */ 1104 */
1203 rt73usb_register_read(rt2x00dev, TXRX_CSR2, &reg); 1105 rt2x00usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
1204 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13); 1106 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1205 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1); 1107 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1206 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12); 1108 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
@@ -1209,77 +1111,77 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1209 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1); 1111 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1210 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10); 1112 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1211 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1); 1113 rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1212 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg); 1114 rt2x00usb_register_write(rt2x00dev, TXRX_CSR2, reg);
1213 1115
1214 /* 1116 /*
1215 * OFDM TXD BBP registers 1117 * OFDM TXD BBP registers
1216 */ 1118 */
1217 rt73usb_register_read(rt2x00dev, TXRX_CSR3, &reg); 1119 rt2x00usb_register_read(rt2x00dev, TXRX_CSR3, &reg);
1218 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7); 1120 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1219 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1); 1121 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1220 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6); 1122 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1221 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1); 1123 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1222 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5); 1124 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1223 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1); 1125 rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1224 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg); 1126 rt2x00usb_register_write(rt2x00dev, TXRX_CSR3, reg);
1225 1127
1226 rt73usb_register_read(rt2x00dev, TXRX_CSR7, &reg); 1128 rt2x00usb_register_read(rt2x00dev, TXRX_CSR7, &reg);
1227 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59); 1129 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1228 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53); 1130 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1229 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49); 1131 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1230 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46); 1132 rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1231 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg); 1133 rt2x00usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1232 1134
1233 rt73usb_register_read(rt2x00dev, TXRX_CSR8, &reg); 1135 rt2x00usb_register_read(rt2x00dev, TXRX_CSR8, &reg);
1234 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44); 1136 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1235 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42); 1137 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1236 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42); 1138 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1237 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42); 1139 rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1238 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg); 1140 rt2x00usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1239 1141
1240 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1142 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1241 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0); 1143 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1242 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); 1144 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1243 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0); 1145 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1244 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1146 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1245 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1147 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1246 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); 1148 rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1247 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1149 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1248 1150
1249 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); 1151 rt2x00usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1250 1152
1251 rt73usb_register_read(rt2x00dev, MAC_CSR6, &reg); 1153 rt2x00usb_register_read(rt2x00dev, MAC_CSR6, &reg);
1252 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff); 1154 rt2x00_set_field32(&reg, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1253 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg); 1155 rt2x00usb_register_write(rt2x00dev, MAC_CSR6, reg);
1254 1156
1255 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718); 1157 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1256 1158
1257 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) 1159 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1258 return -EBUSY; 1160 return -EBUSY;
1259 1161
1260 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00); 1162 rt2x00usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1261 1163
1262 /* 1164 /*
1263 * Invalidate all Shared Keys (SEC_CSR0), 1165 * Invalidate all Shared Keys (SEC_CSR0),
1264 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5) 1166 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1265 */ 1167 */
1266 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000); 1168 rt2x00usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1267 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000); 1169 rt2x00usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1268 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000); 1170 rt2x00usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1269 1171
1270 reg = 0x000023b0; 1172 reg = 0x000023b0;
1271 if (rt2x00_rf(&rt2x00dev->chip, RF5225) || 1173 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1272 rt2x00_rf(&rt2x00dev->chip, RF2527)) 1174 rt2x00_rf(&rt2x00dev->chip, RF2527))
1273 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1); 1175 rt2x00_set_field32(&reg, PHY_CSR1_RF_RPI, 1);
1274 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg); 1176 rt2x00usb_register_write(rt2x00dev, PHY_CSR1, reg);
1275 1177
1276 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06); 1178 rt2x00usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1277 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606); 1179 rt2x00usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1278 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408); 1180 rt2x00usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1279 1181
1280 rt73usb_register_read(rt2x00dev, MAC_CSR9, &reg); 1182 rt2x00usb_register_read(rt2x00dev, MAC_CSR9, &reg);
1281 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0); 1183 rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1282 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg); 1184 rt2x00usb_register_write(rt2x00dev, MAC_CSR9, reg);
1283 1185
1284 /* 1186 /*
1285 * Clear all beacons 1187 * Clear all beacons
@@ -1287,36 +1189,36 @@ static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
1287 * the first byte since that byte contains the VALID and OWNER 1189 * the first byte since that byte contains the VALID and OWNER
1288 * bits which (when set to 0) will invalidate the entire beacon. 1190 * bits which (when set to 0) will invalidate the entire beacon.
1289 */ 1191 */
1290 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0); 1192 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1291 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0); 1193 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1292 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0); 1194 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1293 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0); 1195 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1294 1196
1295 /* 1197 /*
1296 * We must clear the error counters. 1198 * We must clear the error counters.
1297 * These registers are cleared on read, 1199 * These registers are cleared on read,
1298 * so we may pass a useless variable to store the value. 1200 * so we may pass a useless variable to store the value.
1299 */ 1201 */
1300 rt73usb_register_read(rt2x00dev, STA_CSR0, &reg); 1202 rt2x00usb_register_read(rt2x00dev, STA_CSR0, &reg);
1301 rt73usb_register_read(rt2x00dev, STA_CSR1, &reg); 1203 rt2x00usb_register_read(rt2x00dev, STA_CSR1, &reg);
1302 rt73usb_register_read(rt2x00dev, STA_CSR2, &reg); 1204 rt2x00usb_register_read(rt2x00dev, STA_CSR2, &reg);
1303 1205
1304 /* 1206 /*
1305 * Reset MAC and BBP registers. 1207 * Reset MAC and BBP registers.
1306 */ 1208 */
1307 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1209 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1308 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1); 1210 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1309 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1); 1211 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1310 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1212 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1311 1213
1312 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1214 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1313 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0); 1215 rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1314 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0); 1216 rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1315 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1217 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1316 1218
1317 rt73usb_register_read(rt2x00dev, MAC_CSR1, &reg); 1219 rt2x00usb_register_read(rt2x00dev, MAC_CSR1, &reg);
1318 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1); 1220 rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1319 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg); 1221 rt2x00usb_register_write(rt2x00dev, MAC_CSR1, reg);
1320 1222
1321 return 0; 1223 return 0;
1322} 1224}
@@ -1394,11 +1296,11 @@ static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1394{ 1296{
1395 u32 reg; 1297 u32 reg;
1396 1298
1397 rt73usb_register_read(rt2x00dev, TXRX_CSR0, &reg); 1299 rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
1398 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1300 rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1399 (state == STATE_RADIO_RX_OFF) || 1301 (state == STATE_RADIO_RX_OFF) ||
1400 (state == STATE_RADIO_RX_OFF_LINK)); 1302 (state == STATE_RADIO_RX_OFF_LINK));
1401 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg); 1303 rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1402} 1304}
1403 1305
1404static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev) 1306static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -1415,12 +1317,12 @@ static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1415 1317
1416static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev) 1318static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1417{ 1319{
1418 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818); 1320 rt2x00usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1419 1321
1420 /* 1322 /*
1421 * Disable synchronisation. 1323 * Disable synchronisation.
1422 */ 1324 */
1423 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0); 1325 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1424 1326
1425 rt2x00usb_disable_radio(rt2x00dev); 1327 rt2x00usb_disable_radio(rt2x00dev);
1426} 1328}
@@ -1433,10 +1335,10 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1433 1335
1434 put_to_sleep = (state != STATE_AWAKE); 1336 put_to_sleep = (state != STATE_AWAKE);
1435 1337
1436 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); 1338 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1437 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); 1339 rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1438 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); 1340 rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1439 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg); 1341 rt2x00usb_register_write(rt2x00dev, MAC_CSR12, reg);
1440 1342
1441 /* 1343 /*
1442 * Device is not guaranteed to be in the requested state yet. 1344 * Device is not guaranteed to be in the requested state yet.
@@ -1444,7 +1346,7 @@ static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1444 * device has entered the correct state. 1346 * device has entered the correct state.
1445 */ 1347 */
1446 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 1348 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1447 rt73usb_register_read(rt2x00dev, MAC_CSR12, &reg); 1349 rt2x00usb_register_read(rt2x00dev, MAC_CSR12, &reg);
1448 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE); 1350 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1449 if (state == !put_to_sleep) 1351 if (state == !put_to_sleep)
1450 return 0; 1352 return 0;
@@ -1526,8 +1428,8 @@ static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1526 rt2x00_desc_write(txd, 2, word); 1428 rt2x00_desc_write(txd, 2, word);
1527 1429
1528 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { 1430 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1529 _rt2x00_desc_write(txd, 3, skbdesc->iv); 1431 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1530 _rt2x00_desc_write(txd, 4, skbdesc->eiv); 1432 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1531 } 1433 }
1532 1434
1533 rt2x00_desc_read(txd, 5, &word); 1435 rt2x00_desc_read(txd, 5, &word);
@@ -1584,11 +1486,11 @@ static void rt73usb_write_beacon(struct queue_entry *entry)
1584 * Disable beaconing while we are reloading the beacon data, 1486 * Disable beaconing while we are reloading the beacon data,
1585 * otherwise we might be sending out invalid data. 1487 * otherwise we might be sending out invalid data.
1586 */ 1488 */
1587 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1489 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1588 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0); 1490 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1589 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0); 1491 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1590 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0); 1492 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1591 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1493 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1592 1494
1593 /* 1495 /*
1594 * Write entire beacon with descriptor to register. 1496 * Write entire beacon with descriptor to register.
@@ -1606,8 +1508,7 @@ static void rt73usb_write_beacon(struct queue_entry *entry)
1606 entry->skb = NULL; 1508 entry->skb = NULL;
1607} 1509}
1608 1510
1609static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev, 1511static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1610 struct sk_buff *skb)
1611{ 1512{
1612 int length; 1513 int length;
1613 1514
@@ -1615,8 +1516,8 @@ static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1615 * The length _must_ be a multiple of 4, 1516 * The length _must_ be a multiple of 4,
1616 * but it must _not_ be a multiple of the USB packet size. 1517 * but it must _not_ be a multiple of the USB packet size.
1617 */ 1518 */
1618 length = roundup(skb->len, 4); 1519 length = roundup(entry->skb->len, 4);
1619 length += (4 * !(length % rt2x00dev->usb_maxpacket)); 1520 length += (4 * !(length % entry->queue->usb_maxpacket));
1620 1521
1621 return length; 1522 return length;
1622} 1523}
@@ -1635,14 +1536,14 @@ static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1635 * For Wi-Fi faily generated beacons between participating stations. 1536 * For Wi-Fi faily generated beacons between participating stations.
1636 * Set TBTT phase adaptive adjustment step to 8us (default 16us) 1537 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1637 */ 1538 */
1638 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); 1539 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1639 1540
1640 rt73usb_register_read(rt2x00dev, TXRX_CSR9, &reg); 1541 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1641 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) { 1542 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1642 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1); 1543 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1643 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1); 1544 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1644 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1); 1545 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1645 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1546 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1646 } 1547 }
1647} 1548}
1648 1549
@@ -1685,7 +1586,7 @@ static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1685} 1586}
1686 1587
1687static void rt73usb_fill_rxdone(struct queue_entry *entry, 1588static void rt73usb_fill_rxdone(struct queue_entry *entry,
1688 struct rxdone_entry_desc *rxdesc) 1589 struct rxdone_entry_desc *rxdesc)
1689{ 1590{
1690 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1591 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1691 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1592 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
@@ -1717,9 +1618,12 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry,
1717 } 1618 }
1718 1619
1719 if (rxdesc->cipher != CIPHER_NONE) { 1620 if (rxdesc->cipher != CIPHER_NONE) {
1720 _rt2x00_desc_read(rxd, 2, &rxdesc->iv); 1621 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
1721 _rt2x00_desc_read(rxd, 3, &rxdesc->eiv); 1622 _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]);
1623 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1624
1722 _rt2x00_desc_read(rxd, 4, &rxdesc->icv); 1625 _rt2x00_desc_read(rxd, 4, &rxdesc->icv);
1626 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1723 1627
1724 /* 1628 /*
1725 * Hardware has stripped IV/EIV data from 802.11 frame during 1629 * Hardware has stripped IV/EIV data from 802.11 frame during
@@ -1781,10 +1685,8 @@ static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1781 */ 1685 */
1782 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 1686 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1783 if (!is_valid_ether_addr(mac)) { 1687 if (!is_valid_ether_addr(mac)) {
1784 DECLARE_MAC_BUF(macbuf);
1785
1786 random_ether_addr(mac); 1688 random_ether_addr(mac);
1787 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac)); 1689 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1788 } 1690 }
1789 1691
1790 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word); 1692 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
@@ -1883,7 +1785,7 @@ static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1883 * Identify RF chipset. 1785 * Identify RF chipset.
1884 */ 1786 */
1885 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1787 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1886 rt73usb_register_read(rt2x00dev, MAC_CSR0, &reg); 1788 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1887 rt2x00_set_chip(rt2x00dev, RT2571, value, reg); 1789 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1888 1790
1889 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) { 1791 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
@@ -2211,20 +2113,6 @@ static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2211/* 2113/*
2212 * IEEE80211 stack callback functions. 2114 * IEEE80211 stack callback functions.
2213 */ 2115 */
2214static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
2215 u32 short_retry, u32 long_retry)
2216{
2217 struct rt2x00_dev *rt2x00dev = hw->priv;
2218 u32 reg;
2219
2220 rt73usb_register_read(rt2x00dev, TXRX_CSR4, &reg);
2221 rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2222 rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2223 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
2224
2225 return 0;
2226}
2227
2228static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx, 2116static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2229 const struct ieee80211_tx_queue_params *params) 2117 const struct ieee80211_tx_queue_params *params)
2230{ 2118{
@@ -2251,33 +2139,33 @@ static int rt73usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2251 field.bit_offset = queue_idx * 16; 2139 field.bit_offset = queue_idx * 16;
2252 field.bit_mask = 0xffff << field.bit_offset; 2140 field.bit_mask = 0xffff << field.bit_offset;
2253 2141
2254 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg); 2142 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2255 rt2x00_set_field32(&reg, field, queue->txop); 2143 rt2x00_set_field32(&reg, field, queue->txop);
2256 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg); 2144 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2257 } else if (queue_idx < 4) { 2145 } else if (queue_idx < 4) {
2258 field.bit_offset = (queue_idx - 2) * 16; 2146 field.bit_offset = (queue_idx - 2) * 16;
2259 field.bit_mask = 0xffff << field.bit_offset; 2147 field.bit_mask = 0xffff << field.bit_offset;
2260 2148
2261 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg); 2149 rt2x00usb_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2262 rt2x00_set_field32(&reg, field, queue->txop); 2150 rt2x00_set_field32(&reg, field, queue->txop);
2263 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg); 2151 rt2x00usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2264 } 2152 }
2265 2153
2266 /* Update WMM registers */ 2154 /* Update WMM registers */
2267 field.bit_offset = queue_idx * 4; 2155 field.bit_offset = queue_idx * 4;
2268 field.bit_mask = 0xf << field.bit_offset; 2156 field.bit_mask = 0xf << field.bit_offset;
2269 2157
2270 rt73usb_register_read(rt2x00dev, AIFSN_CSR, &reg); 2158 rt2x00usb_register_read(rt2x00dev, AIFSN_CSR, &reg);
2271 rt2x00_set_field32(&reg, field, queue->aifs); 2159 rt2x00_set_field32(&reg, field, queue->aifs);
2272 rt73usb_register_write(rt2x00dev, AIFSN_CSR, reg); 2160 rt2x00usb_register_write(rt2x00dev, AIFSN_CSR, reg);
2273 2161
2274 rt73usb_register_read(rt2x00dev, CWMIN_CSR, &reg); 2162 rt2x00usb_register_read(rt2x00dev, CWMIN_CSR, &reg);
2275 rt2x00_set_field32(&reg, field, queue->cw_min); 2163 rt2x00_set_field32(&reg, field, queue->cw_min);
2276 rt73usb_register_write(rt2x00dev, CWMIN_CSR, reg); 2164 rt2x00usb_register_write(rt2x00dev, CWMIN_CSR, reg);
2277 2165
2278 rt73usb_register_read(rt2x00dev, CWMAX_CSR, &reg); 2166 rt2x00usb_register_read(rt2x00dev, CWMAX_CSR, &reg);
2279 rt2x00_set_field32(&reg, field, queue->cw_max); 2167 rt2x00_set_field32(&reg, field, queue->cw_max);
2280 rt73usb_register_write(rt2x00dev, CWMAX_CSR, reg); 2168 rt2x00usb_register_write(rt2x00dev, CWMAX_CSR, reg);
2281 2169
2282 return 0; 2170 return 0;
2283} 2171}
@@ -2295,9 +2183,9 @@ static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
2295 u64 tsf; 2183 u64 tsf;
2296 u32 reg; 2184 u32 reg;
2297 2185
2298 rt73usb_register_read(rt2x00dev, TXRX_CSR13, &reg); 2186 rt2x00usb_register_read(rt2x00dev, TXRX_CSR13, &reg);
2299 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; 2187 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2300 rt73usb_register_read(rt2x00dev, TXRX_CSR12, &reg); 2188 rt2x00usb_register_read(rt2x00dev, TXRX_CSR12, &reg);
2301 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); 2189 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2302 2190
2303 return tsf; 2191 return tsf;
@@ -2317,7 +2205,6 @@ static const struct ieee80211_ops rt73usb_mac80211_ops = {
2317 .configure_filter = rt2x00mac_configure_filter, 2205 .configure_filter = rt2x00mac_configure_filter,
2318 .set_key = rt2x00mac_set_key, 2206 .set_key = rt2x00mac_set_key,
2319 .get_stats = rt2x00mac_get_stats, 2207 .get_stats = rt2x00mac_get_stats,
2320 .set_retry_limit = rt73usb_set_retry_limit,
2321 .bss_info_changed = rt2x00mac_bss_info_changed, 2208 .bss_info_changed = rt2x00mac_bss_info_changed,
2322 .conf_tx = rt73usb_conf_tx, 2209 .conf_tx = rt73usb_conf_tx,
2323 .get_tx_stats = rt2x00mac_get_tx_stats, 2210 .get_tx_stats = rt2x00mac_get_tx_stats,
@@ -2331,8 +2218,7 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2331 .load_firmware = rt73usb_load_firmware, 2218 .load_firmware = rt73usb_load_firmware,
2332 .initialize = rt2x00usb_initialize, 2219 .initialize = rt2x00usb_initialize,
2333 .uninitialize = rt2x00usb_uninitialize, 2220 .uninitialize = rt2x00usb_uninitialize,
2334 .init_rxentry = rt2x00usb_init_rxentry, 2221 .clear_entry = rt2x00usb_clear_entry,
2335 .init_txentry = rt2x00usb_init_txentry,
2336 .set_device_state = rt73usb_set_device_state, 2222 .set_device_state = rt73usb_set_device_state,
2337 .link_stats = rt73usb_link_stats, 2223 .link_stats = rt73usb_link_stats,
2338 .reset_tuner = rt73usb_reset_tuner, 2224 .reset_tuner = rt73usb_reset_tuner,
@@ -2348,6 +2234,7 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2348 .config_filter = rt73usb_config_filter, 2234 .config_filter = rt73usb_config_filter,
2349 .config_intf = rt73usb_config_intf, 2235 .config_intf = rt73usb_config_intf,
2350 .config_erp = rt73usb_config_erp, 2236 .config_erp = rt73usb_config_erp,
2237 .config_ant = rt73usb_config_ant,
2351 .config = rt73usb_config, 2238 .config = rt73usb_config,
2352}; 2239};
2353 2240
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-18 00:05:31 -0500