diff options
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt61pci.c | 37 |
1 files changed, 21 insertions, 16 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c index d81a8de9dc17..c7ad1b3d4765 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.c +++ b/drivers/net/wireless/rt2x00/rt61pci.c | |||
@@ -1696,24 +1696,10 @@ static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) | |||
1696 | 1696 | ||
1697 | static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) | 1697 | static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) |
1698 | { | 1698 | { |
1699 | u32 reg; | ||
1700 | |||
1701 | rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818); | ||
1702 | |||
1703 | /* | ||
1704 | * Disable synchronisation. | ||
1705 | */ | ||
1706 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); | ||
1707 | |||
1708 | /* | 1699 | /* |
1709 | * Cancel RX and TX. | 1700 | * Disable power |
1710 | */ | 1701 | */ |
1711 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); | 1702 | rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818); |
1712 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); | ||
1713 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); | ||
1714 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); | ||
1715 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); | ||
1716 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); | ||
1717 | } | 1703 | } |
1718 | 1704 | ||
1719 | static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) | 1705 | static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) |
@@ -1936,6 +1922,24 @@ static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, | |||
1936 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); | 1922 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); |
1937 | } | 1923 | } |
1938 | 1924 | ||
1925 | static void rt61pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, | ||
1926 | const enum data_queue_qid qid) | ||
1927 | { | ||
1928 | u32 reg; | ||
1929 | |||
1930 | if (qid == QID_BEACON) { | ||
1931 | rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0); | ||
1932 | return; | ||
1933 | } | ||
1934 | |||
1935 | rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®); | ||
1936 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, (qid == QID_AC_BE)); | ||
1937 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, (qid == QID_AC_BK)); | ||
1938 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, (qid == QID_AC_VI)); | ||
1939 | rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, (qid == QID_AC_VO)); | ||
1940 | rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg); | ||
1941 | } | ||
1942 | |||
1939 | /* | 1943 | /* |
1940 | * RX control handlers | 1944 | * RX control handlers |
1941 | */ | 1945 | */ |
@@ -2761,6 +2765,7 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = { | |||
2761 | .write_tx_data = rt2x00pci_write_tx_data, | 2765 | .write_tx_data = rt2x00pci_write_tx_data, |
2762 | .write_beacon = rt61pci_write_beacon, | 2766 | .write_beacon = rt61pci_write_beacon, |
2763 | .kick_tx_queue = rt61pci_kick_tx_queue, | 2767 | .kick_tx_queue = rt61pci_kick_tx_queue, |
2768 | .kill_tx_queue = rt61pci_kill_tx_queue, | ||
2764 | .fill_rxdone = rt61pci_fill_rxdone, | 2769 | .fill_rxdone = rt61pci_fill_rxdone, |
2765 | .config_shared_key = rt61pci_config_shared_key, | 2770 | .config_shared_key = rt61pci_config_shared_key, |
2766 | .config_pairwise_key = rt61pci_config_pairwise_key, | 2771 | .config_pairwise_key = rt61pci_config_pairwise_key, |