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path: root/drivers/net/wireless/rt2x00/rt61pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt61pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c69
1 files changed, 34 insertions, 35 deletions
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 2e5e45cbd2e5..7598b6e15784 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -1018,35 +1018,34 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
1018static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 1018static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1019 struct queue_entry *entry) 1019 struct queue_entry *entry)
1020{ 1020{
1021 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1021 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1022 u32 word; 1022 u32 word;
1023 1023
1024 rt2x00_desc_read(priv_rx->desc, 5, &word); 1024 rt2x00_desc_read(entry_priv->desc, 5, &word);
1025 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, 1025 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1026 priv_rx->data_dma); 1026 entry_priv->data_dma);
1027 rt2x00_desc_write(priv_rx->desc, 5, word); 1027 rt2x00_desc_write(entry_priv->desc, 5, word);
1028 1028
1029 rt2x00_desc_read(priv_rx->desc, 0, &word); 1029 rt2x00_desc_read(entry_priv->desc, 0, &word);
1030 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 1030 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1031 rt2x00_desc_write(priv_rx->desc, 0, word); 1031 rt2x00_desc_write(entry_priv->desc, 0, word);
1032} 1032}
1033 1033
1034static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev, 1034static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1035 struct queue_entry *entry) 1035 struct queue_entry *entry)
1036{ 1036{
1037 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; 1037 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1038 u32 word; 1038 u32 word;
1039 1039
1040 rt2x00_desc_read(priv_tx->desc, 0, &word); 1040 rt2x00_desc_read(entry_priv->desc, 0, &word);
1041 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 1041 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1042 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 1042 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1043 rt2x00_desc_write(priv_tx->desc, 0, word); 1043 rt2x00_desc_write(entry_priv->desc, 0, word);
1044} 1044}
1045 1045
1046static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) 1046static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1047{ 1047{
1048 struct queue_entry_priv_pci_rx *priv_rx; 1048 struct queue_entry_priv_pci *entry_priv;
1049 struct queue_entry_priv_pci_tx *priv_tx;
1050 u32 reg; 1049 u32 reg;
1051 1050
1052 /* 1051 /*
@@ -1068,28 +1067,28 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1068 rt2x00dev->tx[0].desc_size / 4); 1067 rt2x00dev->tx[0].desc_size / 4);
1069 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg); 1068 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1070 1069
1071 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 1070 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1072 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg); 1071 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1073 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER, 1072 rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1074 priv_tx->desc_dma); 1073 entry_priv->desc_dma);
1075 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg); 1074 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1076 1075
1077 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 1076 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1078 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg); 1077 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1079 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER, 1078 rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1080 priv_tx->desc_dma); 1079 entry_priv->desc_dma);
1081 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg); 1080 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1082 1081
1083 priv_tx = rt2x00dev->tx[2].entries[0].priv_data; 1082 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1084 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg); 1083 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1085 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER, 1084 rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1086 priv_tx->desc_dma); 1085 entry_priv->desc_dma);
1087 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg); 1086 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1088 1087
1089 priv_tx = rt2x00dev->tx[3].entries[0].priv_data; 1088 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1090 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg); 1089 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1091 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER, 1090 rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1092 priv_tx->desc_dma); 1091 entry_priv->desc_dma);
1093 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg); 1092 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1094 1093
1095 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg); 1094 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
@@ -1099,10 +1098,10 @@ static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1099 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); 1098 rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1100 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg); 1099 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1101 1100
1102 priv_rx = rt2x00dev->rx->entries[0].priv_data; 1101 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1103 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg); 1102 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1104 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER, 1103 rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1105 priv_rx->desc_dma); 1104 entry_priv->desc_dma);
1106 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg); 1105 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1107 1106
1108 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg); 1107 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
@@ -1515,7 +1514,7 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1515 struct txentry_desc *txdesc) 1514 struct txentry_desc *txdesc)
1516{ 1515{
1517 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1516 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1518 struct queue_entry_priv_pci_tx *entry_priv = skbdesc->entry->priv_data; 1517 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1519 __le32 *txd = skbdesc->desc; 1518 __le32 *txd = skbdesc->desc;
1520 u32 word; 1519 u32 word;
1521 1520
@@ -1661,12 +1660,12 @@ static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1661static void rt61pci_fill_rxdone(struct queue_entry *entry, 1660static void rt61pci_fill_rxdone(struct queue_entry *entry,
1662 struct rxdone_entry_desc *rxdesc) 1661 struct rxdone_entry_desc *rxdesc)
1663{ 1662{
1664 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1663 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1665 u32 word0; 1664 u32 word0;
1666 u32 word1; 1665 u32 word1;
1667 1666
1668 rt2x00_desc_read(priv_rx->desc, 0, &word0); 1667 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1669 rt2x00_desc_read(priv_rx->desc, 1, &word1); 1668 rt2x00_desc_read(entry_priv->desc, 1, &word1);
1670 1669
1671 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1670 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1672 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1671 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
@@ -1695,7 +1694,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1695 struct data_queue *queue; 1694 struct data_queue *queue;
1696 struct queue_entry *entry; 1695 struct queue_entry *entry;
1697 struct queue_entry *entry_done; 1696 struct queue_entry *entry_done;
1698 struct queue_entry_priv_pci_tx *priv_tx; 1697 struct queue_entry_priv_pci *entry_priv;
1699 struct txdone_entry_desc txdesc; 1698 struct txdone_entry_desc txdesc;
1700 u32 word; 1699 u32 word;
1701 u32 reg; 1700 u32 reg;
@@ -1740,8 +1739,8 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1740 continue; 1739 continue;
1741 1740
1742 entry = &queue->entries[index]; 1741 entry = &queue->entries[index];
1743 priv_tx = entry->priv_data; 1742 entry_priv = entry->priv_data;
1744 rt2x00_desc_read(priv_tx->desc, 0, &word); 1743 rt2x00_desc_read(entry_priv->desc, 0, &word);
1745 1744
1746 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1745 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1747 !rt2x00_get_field32(word, TXD_W0_VALID)) 1746 !rt2x00_get_field32(word, TXD_W0_VALID))
@@ -2363,7 +2362,7 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2363{ 2362{
2364 struct rt2x00_dev *rt2x00dev = hw->priv; 2363 struct rt2x00_dev *rt2x00dev = hw->priv;
2365 struct rt2x00_intf *intf = vif_to_intf(control->vif); 2364 struct rt2x00_intf *intf = vif_to_intf(control->vif);
2366 struct queue_entry_priv_pci_tx *priv_tx; 2365 struct queue_entry_priv_pci *entry_priv;
2367 struct skb_frame_desc *skbdesc; 2366 struct skb_frame_desc *skbdesc;
2368 struct txentry_desc txdesc; 2367 struct txentry_desc txdesc;
2369 unsigned int beacon_base; 2368 unsigned int beacon_base;
@@ -2380,8 +2379,8 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2380 intf->beacon->skb = skb; 2379 intf->beacon->skb = skb;
2381 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc, control); 2380 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc, control);
2382 2381
2383 priv_tx = intf->beacon->priv_data; 2382 entry_priv = intf->beacon->priv_data;
2384 memset(priv_tx->desc, 0, intf->beacon->queue->desc_size); 2383 memset(entry_priv->desc, 0, intf->beacon->queue->desc_size);
2385 2384
2386 /* 2385 /*
2387 * Fill in skb descriptor 2386 * Fill in skb descriptor
@@ -2391,7 +2390,7 @@ static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2391 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED; 2390 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2392 skbdesc->data = skb->data; 2391 skbdesc->data = skb->data;
2393 skbdesc->data_len = skb->len; 2392 skbdesc->data_len = skb->len;
2394 skbdesc->desc = priv_tx->desc; 2393 skbdesc->desc = entry_priv->desc;
2395 skbdesc->desc_len = intf->beacon->queue->desc_size; 2394 skbdesc->desc_len = intf->beacon->queue->desc_size;
2396 skbdesc->entry = intf->beacon; 2395 skbdesc->entry = intf->beacon;
2397 2396
@@ -2468,21 +2467,21 @@ static const struct data_queue_desc rt61pci_queue_rx = {
2468 .entry_num = RX_ENTRIES, 2467 .entry_num = RX_ENTRIES,
2469 .data_size = DATA_FRAME_SIZE, 2468 .data_size = DATA_FRAME_SIZE,
2470 .desc_size = RXD_DESC_SIZE, 2469 .desc_size = RXD_DESC_SIZE,
2471 .priv_size = sizeof(struct queue_entry_priv_pci_rx), 2470 .priv_size = sizeof(struct queue_entry_priv_pci),
2472}; 2471};
2473 2472
2474static const struct data_queue_desc rt61pci_queue_tx = { 2473static const struct data_queue_desc rt61pci_queue_tx = {
2475 .entry_num = TX_ENTRIES, 2474 .entry_num = TX_ENTRIES,
2476 .data_size = DATA_FRAME_SIZE, 2475 .data_size = DATA_FRAME_SIZE,
2477 .desc_size = TXD_DESC_SIZE, 2476 .desc_size = TXD_DESC_SIZE,
2478 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 2477 .priv_size = sizeof(struct queue_entry_priv_pci),
2479}; 2478};
2480 2479
2481static const struct data_queue_desc rt61pci_queue_bcn = { 2480static const struct data_queue_desc rt61pci_queue_bcn = {
2482 .entry_num = 4 * BEACON_ENTRIES, 2481 .entry_num = 4 * BEACON_ENTRIES,
2483 .data_size = 0, /* No DMA required for beacons */ 2482 .data_size = 0, /* No DMA required for beacons */
2484 .desc_size = TXINFO_SIZE, 2483 .desc_size = TXINFO_SIZE,
2485 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 2484 .priv_size = sizeof(struct queue_entry_priv_pci),
2486}; 2485};
2487 2486
2488static const struct rt2x00_ops rt61pci_ops = { 2487static const struct rt2x00_ops rt61pci_ops = {