1 files changed, 17 insertions, 24 deletions

diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 26ee7911fba9..86c75b9c3f25 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -1843,7 +1843,8 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 /*
  * TX data initialization
  */
-static void rt61pci_write_beacon(struct queue_entry *entry)
+static void rt61pci_write_beacon(struct queue_entry *entry,
+                                 struct txentry_desc *txdesc)
 {
         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
@@ -1870,6 +1871,19 @@ static void rt61pci_write_beacon(struct queue_entry *entry)
                                       entry->skb->data, entry->skb->len);
 
         /*
+         * Enable beaconing again.
+         *
+         * For Wi-Fi faily generated beacons between participating
+         * stations. Set TBTT phase adaptive adjustment step to 8us.
+         */
+        rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
+
+        rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
+        rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
+        rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
+        rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
+
+        /*
          * Clean up beacon skb.
          */
         dev_kfree_skb_any(entry->skb);
@@ -1881,23 +1895,6 @@ static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
 {
         u32 reg;
 
-        if (queue == QID_BEACON) {
-                /*
-                 * For Wi-Fi faily generated beacons between participating
-                 * stations. Set TBTT phase adaptive adjustment step to 8us.
-                 */
-                rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
-
-                rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
-                if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
-                        rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
-                        rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
-                        rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
-                        rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
-                }
-                return;
-        }
-
         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
@@ -1969,12 +1966,8 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 
-        if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
-                rxdesc->cipher =
-                    rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
-                rxdesc->cipher_status =
-                    rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
-        }
+        rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
+        rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
 
         if (rxdesc->cipher != CIPHER_NONE) {
                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);