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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800usb.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c3071
1 files changed, 3071 insertions, 0 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
new file mode 100644
index 000000000000..257bfb5483c9
--- /dev/null
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -0,0 +1,3071 @@
1/*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2800usb
23 Abstract: rt2800usb device specific routines.
24 Supported chipsets: RT2800U.
25 */
26
27#include <linux/crc-ccitt.h>
28#include <linux/delay.h>
29#include <linux/etherdevice.h>
30#include <linux/init.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/usb.h>
34
35#include "rt2x00.h"
36#include "rt2x00usb.h"
37#include "rt2800usb.h"
38
39/*
40 * Allow hardware encryption to be disabled.
41 */
42static int modparam_nohwcrypt = 1;
43module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
44MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
45
46/*
47 * Register access.
48 * All access to the CSR registers will go through the methods
49 * rt2x00usb_register_read and rt2x00usb_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
59 */
60#define WAIT_FOR_BBP(__dev, __reg) \
61 rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64#define WAIT_FOR_RF(__dev, __reg) \
65 rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66#define WAIT_FOR_MCU(__dev, __reg) \
67 rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
69
70static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
72{
73 u32 reg;
74
75 mutex_lock(&rt2x00dev->csr_mutex);
76
77 /*
78 * Wait until the BBP becomes available, afterwards we
79 * can safely write the new data into the register.
80 */
81 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
82 reg = 0;
83 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
84 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
85 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
86 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
87
88 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
89 }
90
91 mutex_unlock(&rt2x00dev->csr_mutex);
92}
93
94static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
95 const unsigned int word, u8 *value)
96{
97 u32 reg;
98
99 mutex_lock(&rt2x00dev->csr_mutex);
100
101 /*
102 * Wait until the BBP becomes available, afterwards we
103 * can safely write the read request into the register.
104 * After the data has been written, we wait until hardware
105 * returns the correct value, if at any time the register
106 * doesn't become available in time, reg will be 0xffffffff
107 * which means we return 0xff to the caller.
108 */
109 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
110 reg = 0;
111 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
112 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
113 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
114
115 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
116
117 WAIT_FOR_BBP(rt2x00dev, &reg);
118 }
119
120 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
121
122 mutex_unlock(&rt2x00dev->csr_mutex);
123}
124
125static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
126 const unsigned int word, const u8 value)
127{
128 u32 reg;
129
130 mutex_lock(&rt2x00dev->csr_mutex);
131
132 /*
133 * Wait until the RFCSR becomes available, afterwards we
134 * can safely write the new data into the register.
135 */
136 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
137 reg = 0;
138 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
139 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
140 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
141 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
142
143 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
144 }
145
146 mutex_unlock(&rt2x00dev->csr_mutex);
147}
148
149static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
150 const unsigned int word, u8 *value)
151{
152 u32 reg;
153
154 mutex_lock(&rt2x00dev->csr_mutex);
155
156 /*
157 * Wait until the RFCSR becomes available, afterwards we
158 * can safely write the read request into the register.
159 * After the data has been written, we wait until hardware
160 * returns the correct value, if at any time the register
161 * doesn't become available in time, reg will be 0xffffffff
162 * which means we return 0xff to the caller.
163 */
164 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
165 reg = 0;
166 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
167 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
168 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
169
170 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
171
172 WAIT_FOR_RFCSR(rt2x00dev, &reg);
173 }
174
175 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
176
177 mutex_unlock(&rt2x00dev->csr_mutex);
178}
179
180static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
181 const unsigned int word, const u32 value)
182{
183 u32 reg;
184
185 mutex_lock(&rt2x00dev->csr_mutex);
186
187 /*
188 * Wait until the RF becomes available, afterwards we
189 * can safely write the new data into the register.
190 */
191 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
192 reg = 0;
193 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
194 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
195 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
196 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
197
198 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
199 rt2x00_rf_write(rt2x00dev, word, value);
200 }
201
202 mutex_unlock(&rt2x00dev->csr_mutex);
203}
204
205static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
206 const u8 command, const u8 token,
207 const u8 arg0, const u8 arg1)
208{
209 u32 reg;
210
211 mutex_lock(&rt2x00dev->csr_mutex);
212
213 /*
214 * Wait until the MCU becomes available, afterwards we
215 * can safely write the new data into the register.
216 */
217 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
218 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
219 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
220 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
221 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
222 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
223
224 reg = 0;
225 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
226 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
227 }
228
229 mutex_unlock(&rt2x00dev->csr_mutex);
230}
231
232#ifdef CONFIG_RT2X00_LIB_DEBUGFS
233static const struct rt2x00debug rt2800usb_rt2x00debug = {
234 .owner = THIS_MODULE,
235 .csr = {
236 .read = rt2x00usb_register_read,
237 .write = rt2x00usb_register_write,
238 .flags = RT2X00DEBUGFS_OFFSET,
239 .word_base = CSR_REG_BASE,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
242 },
243 .eeprom = {
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_base = EEPROM_BASE,
247 .word_size = sizeof(u16),
248 .word_count = EEPROM_SIZE / sizeof(u16),
249 },
250 .bbp = {
251 .read = rt2800usb_bbp_read,
252 .write = rt2800usb_bbp_write,
253 .word_base = BBP_BASE,
254 .word_size = sizeof(u8),
255 .word_count = BBP_SIZE / sizeof(u8),
256 },
257 .rf = {
258 .read = rt2x00_rf_read,
259 .write = rt2800usb_rf_write,
260 .word_base = RF_BASE,
261 .word_size = sizeof(u32),
262 .word_count = RF_SIZE / sizeof(u32),
263 },
264};
265#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
266
267#ifdef CONFIG_RT2X00_LIB_RFKILL
268static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269{
270 u32 reg;
271
272 rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
273 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
274}
275#else
276#define rt2800usb_rfkill_poll NULL
277#endif /* CONFIG_RT2X00_LIB_RFKILL */
278
279#ifdef CONFIG_RT2X00_LIB_LEDS
280static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
281 enum led_brightness brightness)
282{
283 struct rt2x00_led *led =
284 container_of(led_cdev, struct rt2x00_led, led_dev);
285 unsigned int enabled = brightness != LED_OFF;
286 unsigned int bg_mode =
287 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
288 unsigned int polarity =
289 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
290 EEPROM_FREQ_LED_POLARITY);
291 unsigned int ledmode =
292 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
293 EEPROM_FREQ_LED_MODE);
294
295 if (led->type == LED_TYPE_RADIO) {
296 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
297 enabled ? 0x20 : 0);
298 } else if (led->type == LED_TYPE_ASSOC) {
299 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
300 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
301 } else if (led->type == LED_TYPE_QUALITY) {
302 /*
303 * The brightness is divided into 6 levels (0 - 5),
304 * The specs tell us the following levels:
305 * 0, 1 ,3, 7, 15, 31
306 * to determine the level in a simple way we can simply
307 * work with bitshifting:
308 * (1 << level) - 1
309 */
310 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
311 (1 << brightness / (LED_FULL / 6)) - 1,
312 polarity);
313 }
314}
315
316static int rt2800usb_blink_set(struct led_classdev *led_cdev,
317 unsigned long *delay_on,
318 unsigned long *delay_off)
319{
320 struct rt2x00_led *led =
321 container_of(led_cdev, struct rt2x00_led, led_dev);
322 u32 reg;
323
324 rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
325 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
326 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
327 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
328 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
329 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
330 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
331 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
332 rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
333
334 return 0;
335}
336
337static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
338 struct rt2x00_led *led,
339 enum led_type type)
340{
341 led->rt2x00dev = rt2x00dev;
342 led->type = type;
343 led->led_dev.brightness_set = rt2800usb_brightness_set;
344 led->led_dev.blink_set = rt2800usb_blink_set;
345 led->flags = LED_INITIALIZED;
346}
347#endif /* CONFIG_RT2X00_LIB_LEDS */
348
349/*
350 * Configuration handlers.
351 */
352static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
353 struct rt2x00lib_crypto *crypto,
354 struct ieee80211_key_conf *key)
355{
356 struct mac_wcid_entry wcid_entry;
357 struct mac_iveiv_entry iveiv_entry;
358 u32 offset;
359 u32 reg;
360
361 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
362
363 rt2x00usb_register_read(rt2x00dev, offset, &reg);
364 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
365 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
366 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
367 (crypto->cmd == SET_KEY) * crypto->cipher);
368 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
369 (crypto->cmd == SET_KEY) * crypto->bssidx);
370 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
371 rt2x00usb_register_write(rt2x00dev, offset, reg);
372
373 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
374
375 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
376 if ((crypto->cipher == CIPHER_TKIP) ||
377 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
378 (crypto->cipher == CIPHER_AES))
379 iveiv_entry.iv[3] |= 0x20;
380 iveiv_entry.iv[3] |= key->keyidx << 6;
381 rt2x00usb_register_multiwrite(rt2x00dev, offset,
382 &iveiv_entry, sizeof(iveiv_entry));
383
384 offset = MAC_WCID_ENTRY(key->hw_key_idx);
385
386 memset(&wcid_entry, 0, sizeof(wcid_entry));
387 if (crypto->cmd == SET_KEY)
388 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
389 rt2x00usb_register_multiwrite(rt2x00dev, offset,
390 &wcid_entry, sizeof(wcid_entry));
391}
392
393static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
394 struct rt2x00lib_crypto *crypto,
395 struct ieee80211_key_conf *key)
396{
397 struct hw_key_entry key_entry;
398 struct rt2x00_field32 field;
399 int timeout;
400 u32 offset;
401 u32 reg;
402
403 if (crypto->cmd == SET_KEY) {
404 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
405
406 memcpy(key_entry.key, crypto->key,
407 sizeof(key_entry.key));
408 memcpy(key_entry.tx_mic, crypto->tx_mic,
409 sizeof(key_entry.tx_mic));
410 memcpy(key_entry.rx_mic, crypto->rx_mic,
411 sizeof(key_entry.rx_mic));
412
413 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
414 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
415 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
416 USB_VENDOR_REQUEST_OUT,
417 offset, &key_entry,
418 sizeof(key_entry),
419 timeout);
420 }
421
422 /*
423 * The cipher types are stored over multiple registers
424 * starting with SHARED_KEY_MODE_BASE each word will have
425 * 32 bits and contains the cipher types for 2 bssidx each.
426 * Using the correct defines correctly will cause overhead,
427 * so just calculate the correct offset.
428 */
429 field.bit_offset = 4 * (key->hw_key_idx % 8);
430 field.bit_mask = 0x7 << field.bit_offset;
431
432 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
433
434 rt2x00usb_register_read(rt2x00dev, offset, &reg);
435 rt2x00_set_field32(&reg, field,
436 (crypto->cmd == SET_KEY) * crypto->cipher);
437 rt2x00usb_register_write(rt2x00dev, offset, reg);
438
439 /*
440 * Update WCID information
441 */
442 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
443
444 return 0;
445}
446
447static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
448 struct rt2x00lib_crypto *crypto,
449 struct ieee80211_key_conf *key)
450{
451 struct hw_key_entry key_entry;
452 int timeout;
453 u32 offset;
454
455 if (crypto->cmd == SET_KEY) {
456 /*
457 * 1 pairwise key is possible per AID, this means that the AID
458 * equals our hw_key_idx. Make sure the WCID starts _after_ the
459 * last possible shared key entry.
460 */
461 if (crypto->aid > (256 - 32))
462 return -ENOSPC;
463
464 key->hw_key_idx = 32 + crypto->aid;
465
466 memcpy(key_entry.key, crypto->key,
467 sizeof(key_entry.key));
468 memcpy(key_entry.tx_mic, crypto->tx_mic,
469 sizeof(key_entry.tx_mic));
470 memcpy(key_entry.rx_mic, crypto->rx_mic,
471 sizeof(key_entry.rx_mic));
472
473 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
474 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
475 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
476 USB_VENDOR_REQUEST_OUT,
477 offset, &key_entry,
478 sizeof(key_entry),
479 timeout);
480 }
481
482 /*
483 * Update WCID information
484 */
485 rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
486
487 return 0;
488}
489
490static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
491 const unsigned int filter_flags)
492{
493 u32 reg;
494
495 /*
496 * Start configuration steps.
497 * Note that the version error will always be dropped
498 * and broadcast frames will always be accepted since
499 * there is no filter for it at this time.
500 */
501 rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
502 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
503 !(filter_flags & FIF_FCSFAIL));
504 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
505 !(filter_flags & FIF_PLCPFAIL));
506 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
507 !(filter_flags & FIF_PROMISC_IN_BSS));
508 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
509 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
510 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
511 !(filter_flags & FIF_ALLMULTI));
512 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
513 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
514 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
515 !(filter_flags & FIF_CONTROL));
516 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
517 !(filter_flags & FIF_CONTROL));
518 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
519 !(filter_flags & FIF_CONTROL));
520 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
521 !(filter_flags & FIF_CONTROL));
522 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
523 !(filter_flags & FIF_CONTROL));
524 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
525 !(filter_flags & FIF_CONTROL));
526 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
527 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
528 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
529 !(filter_flags & FIF_CONTROL));
530 rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
531}
532
533static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
534 struct rt2x00_intf *intf,
535 struct rt2x00intf_conf *conf,
536 const unsigned int flags)
537{
538 unsigned int beacon_base;
539 u32 reg;
540
541 if (flags & CONFIG_UPDATE_TYPE) {
542 /*
543 * Clear current synchronisation setup.
544 * For the Beacon base registers we only need to clear
545 * the first byte since that byte contains the VALID and OWNER
546 * bits which (when set to 0) will invalidate the entire beacon.
547 */
548 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
549 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
550
551 /*
552 * Enable synchronisation.
553 */
554 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
555 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
556 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
557 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
558 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
559 }
560
561 if (flags & CONFIG_UPDATE_MAC) {
562 reg = le32_to_cpu(conf->mac[1]);
563 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
564 conf->mac[1] = cpu_to_le32(reg);
565
566 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
567 conf->mac, sizeof(conf->mac));
568 }
569
570 if (flags & CONFIG_UPDATE_BSSID) {
571 reg = le32_to_cpu(conf->bssid[1]);
572 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
573 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
574 conf->bssid[1] = cpu_to_le32(reg);
575
576 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
577 conf->bssid, sizeof(conf->bssid));
578 }
579}
580
581static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
582 struct rt2x00lib_erp *erp)
583{
584 u32 reg;
585
586 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
587 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
588 DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
589 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
590
591 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
592 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
593 !!erp->short_preamble);
594 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
595 !!erp->short_preamble);
596 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
597
598 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
599 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
600 erp->cts_protection ? 2 : 0);
601 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
602
603 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
604 erp->basic_rates);
605 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
606
607 rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
608 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
609 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
610 rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
611
612 rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
613 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
614 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
615 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
616 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
617 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
618 rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
619}
620
621static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
622 struct antenna_setup *ant)
623{
624 u8 r1;
625 u8 r3;
626
627 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
628 rt2800usb_bbp_read(rt2x00dev, 3, &r3);
629
630 /*
631 * Configure the TX antenna.
632 */
633 switch ((int)ant->tx) {
634 case 1:
635 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
636 break;
637 case 2:
638 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
639 break;
640 case 3:
641 /* Do nothing */
642 break;
643 }
644
645 /*
646 * Configure the RX antenna.
647 */
648 switch ((int)ant->rx) {
649 case 1:
650 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
651 break;
652 case 2:
653 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
654 break;
655 case 3:
656 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
657 break;
658 }
659
660 rt2800usb_bbp_write(rt2x00dev, 3, r3);
661 rt2800usb_bbp_write(rt2x00dev, 1, r1);
662}
663
664static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
665 struct rt2x00lib_conf *libconf)
666{
667 u16 eeprom;
668 short lna_gain;
669
670 if (libconf->rf.channel <= 14) {
671 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
672 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
673 } else if (libconf->rf.channel <= 64) {
674 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
675 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
676 } else if (libconf->rf.channel <= 128) {
677 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
678 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
679 } else {
680 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
681 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
682 }
683
684 rt2x00dev->lna_gain = lna_gain;
685}
686
687static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
688 struct ieee80211_conf *conf,
689 struct rf_channel *rf,
690 struct channel_info *info)
691{
692 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
693
694 if (rt2x00dev->default_ant.tx == 1)
695 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
696
697 if (rt2x00dev->default_ant.rx == 1) {
698 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
699 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
700 } else if (rt2x00dev->default_ant.rx == 2)
701 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
702
703 if (rf->channel > 14) {
704 /*
705 * When TX power is below 0, we should increase it by 7 to
706 * make it a positive value (Minumum value is -7).
707 * However this means that values between 0 and 7 have
708 * double meaning, and we should set a 7DBm boost flag.
709 */
710 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
711 (info->tx_power1 >= 0));
712
713 if (info->tx_power1 < 0)
714 info->tx_power1 += 7;
715
716 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
717 TXPOWER_A_TO_DEV(info->tx_power1));
718
719 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
720 (info->tx_power2 >= 0));
721
722 if (info->tx_power2 < 0)
723 info->tx_power2 += 7;
724
725 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
726 TXPOWER_A_TO_DEV(info->tx_power2));
727 } else {
728 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
729 TXPOWER_G_TO_DEV(info->tx_power1));
730 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
731 TXPOWER_G_TO_DEV(info->tx_power2));
732 }
733
734 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
735
736 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
737 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
738 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
739 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
740
741 udelay(200);
742
743 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
744 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
745 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
746 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
747
748 udelay(200);
749
750 rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
751 rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
752 rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
753 rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
754}
755
756static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
757 struct ieee80211_conf *conf,
758 struct rf_channel *rf,
759 struct channel_info *info)
760{
761 u8 rfcsr;
762
763 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
764 rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
765
766 rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
767 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
768 rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
769
770 rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
771 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
772 TXPOWER_G_TO_DEV(info->tx_power1));
773 rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
774
775 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
776 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
777 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
778
779 rt2800usb_rfcsr_write(rt2x00dev, 24,
780 rt2x00dev->calibration[conf_is_ht40(conf)]);
781
782 rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
783 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
784 rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
785}
786
787static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
788 struct ieee80211_conf *conf,
789 struct rf_channel *rf,
790 struct channel_info *info)
791{
792 u32 reg;
793 unsigned int tx_pin;
794 u8 bbp;
795
796 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
797 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
798 else
799 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
800
801 /*
802 * Change BBP settings
803 */
804 rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
805 rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
806 rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
807 rt2800usb_bbp_write(rt2x00dev, 86, 0);
808
809 if (rf->channel <= 14) {
810 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
811 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
812 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
813 } else {
814 rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
815 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
816 }
817 } else {
818 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
819
820 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
821 rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
822 else
823 rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
824 }
825
826 rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
827 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
828 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
829 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
830 rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
831
832 tx_pin = 0;
833
834 /* Turn on unused PA or LNA when not using 1T or 1R */
835 if (rt2x00dev->default_ant.tx != 1) {
836 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
837 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
838 }
839
840 /* Turn on unused PA or LNA when not using 1T or 1R */
841 if (rt2x00dev->default_ant.rx != 1) {
842 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
843 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
844 }
845
846 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
847 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
848 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
849 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
850 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
851 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
852
853 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
854
855 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
856 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
857 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
858
859 rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
860 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
861 rt2800usb_bbp_write(rt2x00dev, 3, bbp);
862
863 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
864 if (conf_is_ht40(conf)) {
865 rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
866 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
867 rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
868 } else {
869 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
870 rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
871 rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
872 }
873 }
874
875 msleep(1);
876}
877
878static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
879 const int txpower)
880{
881 u32 reg;
882 u32 value = TXPOWER_G_TO_DEV(txpower);
883 u8 r1;
884
885 rt2800usb_bbp_read(rt2x00dev, 1, &r1);
886 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
887 rt2800usb_bbp_write(rt2x00dev, 1, r1);
888
889 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
890 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
891 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
892 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
893 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
894 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
895 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
896 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
897 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
898 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
899
900 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
901 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
902 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
903 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
904 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
905 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
906 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
907 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
908 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
909 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
910
911 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
912 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
913 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
914 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
915 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
916 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
917 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
918 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
919 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
920 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
921
922 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
923 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
924 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
925 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
926 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
927 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
928 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
929 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
930 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
931 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
932
933 rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
934 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
935 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
936 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
937 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
938 rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
939}
940
941static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
942 struct rt2x00lib_conf *libconf)
943{
944 u32 reg;
945
946 rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
947 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
948 libconf->conf->short_frame_max_tx_count);
949 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
950 libconf->conf->long_frame_max_tx_count);
951 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
952 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
953 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
954 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
955 rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
956}
957
958static void rt2800usb_config_duration(struct rt2x00_dev *rt2x00dev,
959 struct rt2x00lib_conf *libconf)
960{
961 u32 reg;
962
963 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
964 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
965 libconf->conf->beacon_int * 16);
966 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
967}
968
969static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
970 struct rt2x00lib_conf *libconf)
971{
972 enum dev_state state =
973 (libconf->conf->flags & IEEE80211_CONF_PS) ?
974 STATE_SLEEP : STATE_AWAKE;
975 u32 reg;
976
977 if (state == STATE_SLEEP) {
978 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
979
980 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
981 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
982 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
983 libconf->conf->listen_interval - 1);
984 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
985 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
986
987 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
988 } else {
989 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
990
991 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
992 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
993 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
994 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
995 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
996 }
997}
998
999static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
1000 struct rt2x00lib_conf *libconf,
1001 const unsigned int flags)
1002{
1003 /* Always recalculate LNA gain before changing configuration */
1004 rt2800usb_config_lna_gain(rt2x00dev, libconf);
1005
1006 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1007 rt2800usb_config_channel(rt2x00dev, libconf->conf,
1008 &libconf->rf, &libconf->channel);
1009 if (flags & IEEE80211_CONF_CHANGE_POWER)
1010 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1011 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1012 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1013 if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1014 rt2800usb_config_duration(rt2x00dev, libconf);
1015 if (flags & IEEE80211_CONF_CHANGE_PS)
1016 rt2800usb_config_ps(rt2x00dev, libconf);
1017}
1018
1019/*
1020 * Link tuning
1021 */
1022static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1023 struct link_qual *qual)
1024{
1025 u32 reg;
1026
1027 /*
1028 * Update FCS error count from register.
1029 */
1030 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1031 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1032}
1033
1034static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1035{
1036 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1037 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1038 return 0x1c + (2 * rt2x00dev->lna_gain);
1039 else
1040 return 0x2e + rt2x00dev->lna_gain;
1041 }
1042
1043 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1044 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1045 else
1046 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1047}
1048
1049static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1050 struct link_qual *qual, u8 vgc_level)
1051{
1052 if (qual->vgc_level != vgc_level) {
1053 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1054 qual->vgc_level = vgc_level;
1055 qual->vgc_level_reg = vgc_level;
1056 }
1057}
1058
1059static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1060 struct link_qual *qual)
1061{
1062 rt2800usb_set_vgc(rt2x00dev, qual,
1063 rt2800usb_get_default_vgc(rt2x00dev));
1064}
1065
1066static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1067 struct link_qual *qual, const u32 count)
1068{
1069 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1070 return;
1071
1072 /*
1073 * When RSSI is better then -80 increase VGC level with 0x10
1074 */
1075 rt2800usb_set_vgc(rt2x00dev, qual,
1076 rt2800usb_get_default_vgc(rt2x00dev) +
1077 ((qual->rssi > -80) * 0x10));
1078}
1079
1080/*
1081 * Firmware functions
1082 */
1083static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1084{
1085 return FIRMWARE_RT2870;
1086}
1087
1088static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1089{
1090 u16 fw_crc;
1091 u16 crc;
1092
1093 /*
1094 * The last 2 bytes in the firmware array are the crc checksum itself,
1095 * this means that we should never pass those 2 bytes to the crc
1096 * algorithm.
1097 */
1098 fw_crc = (data[len - 2] << 8 | data[len - 1]);
1099
1100 /*
1101 * Use the crc ccitt algorithm.
1102 * This will return the same value as the legacy driver which
1103 * used bit ordering reversion on the both the firmware bytes
1104 * before input input as well as on the final output.
1105 * Obviously using crc ccitt directly is much more efficient.
1106 */
1107 crc = crc_ccitt(~0, data, len - 2);
1108
1109 /*
1110 * There is a small difference between the crc-itu-t + bitrev and
1111 * the crc-ccitt crc calculation. In the latter method the 2 bytes
1112 * will be swapped, use swab16 to convert the crc to the correct
1113 * value.
1114 */
1115 crc = swab16(crc);
1116
1117 return fw_crc == crc;
1118}
1119
1120static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1121 const u8 *data, const size_t len)
1122{
1123 u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1124 size_t offset = 0;
1125
1126 /*
1127 * Firmware files:
1128 * There are 2 variations of the rt2870 firmware.
1129 * a) size: 4kb
1130 * b) size: 8kb
1131 * Note that (b) contains 2 seperate firmware blobs of 4k
1132 * within the file. The first blob is the same firmware as (a),
1133 * but the second blob is for the additional chipsets.
1134 */
1135 if (len != 4096 && len != 8192)
1136 return FW_BAD_LENGTH;
1137
1138 /*
1139 * Check if we need the upper 4kb firmware data or not.
1140 */
1141 if ((len == 4096) &&
1142 (chipset != 0x2860) &&
1143 (chipset != 0x2872) &&
1144 (chipset != 0x3070))
1145 return FW_BAD_VERSION;
1146
1147 /*
1148 * 8kb firmware files must be checked as if it were
1149 * 2 seperate firmware files.
1150 */
1151 while (offset < len) {
1152 if (!rt2800usb_check_crc(data + offset, 4096))
1153 return FW_BAD_CRC;
1154
1155 offset += 4096;
1156 }
1157
1158 return FW_OK;
1159}
1160
1161static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1162 const u8 *data, const size_t len)
1163{
1164 unsigned int i;
1165 int status;
1166 u32 reg;
1167 u32 offset;
1168 u32 length;
1169 u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1170
1171 /*
1172 * Check which section of the firmware we need.
1173 */
1174 if ((chipset == 0x2860) ||
1175 (chipset == 0x2872) ||
1176 (chipset == 0x3070)) {
1177 offset = 0;
1178 length = 4096;
1179 } else {
1180 offset = 4096;
1181 length = 4096;
1182 }
1183
1184 /*
1185 * Wait for stable hardware.
1186 */
1187 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1188 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1189 if (reg && reg != ~0)
1190 break;
1191 msleep(1);
1192 }
1193
1194 if (i == REGISTER_BUSY_COUNT) {
1195 ERROR(rt2x00dev, "Unstable hardware.\n");
1196 return -EBUSY;
1197 }
1198
1199 /*
1200 * Write firmware to device.
1201 */
1202 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1203 USB_VENDOR_REQUEST_OUT,
1204 FIRMWARE_IMAGE_BASE,
1205 data + offset, length,
1206 REGISTER_TIMEOUT32(length));
1207
1208 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1209 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1210
1211 /*
1212 * Send firmware request to device to load firmware,
1213 * we need to specify a long timeout time.
1214 */
1215 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1216 0, USB_MODE_FIRMWARE,
1217 REGISTER_TIMEOUT_FIRMWARE);
1218 if (status < 0) {
1219 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1220 return status;
1221 }
1222
1223 msleep(10);
1224 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1225
1226 /*
1227 * Send signal to firmware during boot time.
1228 */
1229 rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1230
1231 if ((chipset == 0x3070) ||
1232 (chipset == 0x3071) ||
1233 (chipset == 0x3572)) {
1234 udelay(200);
1235 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1236 udelay(10);
1237 }
1238
1239 /*
1240 * Wait for device to stabilize.
1241 */
1242 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1243 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1244 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1245 break;
1246 msleep(1);
1247 }
1248
1249 if (i == REGISTER_BUSY_COUNT) {
1250 ERROR(rt2x00dev, "PBF system register not ready.\n");
1251 return -EBUSY;
1252 }
1253
1254 /*
1255 * Initialize firmware.
1256 */
1257 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1258 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1259 msleep(1);
1260
1261 return 0;
1262}
1263
1264/*
1265 * Initialization functions.
1266 */
1267static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1268{
1269 u32 reg;
1270 unsigned int i;
1271
1272 /*
1273 * Wait untill BBP and RF are ready.
1274 */
1275 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1276 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1277 if (reg && reg != ~0)
1278 break;
1279 msleep(1);
1280 }
1281
1282 if (i == REGISTER_BUSY_COUNT) {
1283 ERROR(rt2x00dev, "Unstable hardware.\n");
1284 return -EBUSY;
1285 }
1286
1287 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1288 rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1289
1290 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1291 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1292 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1293 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1294
1295 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1296
1297 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1298 USB_MODE_RESET, REGISTER_TIMEOUT);
1299
1300 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1301
1302 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1303 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1304 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1305 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1306 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1307 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1308
1309 rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1310 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1311 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1312 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1313 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1314 rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1315
1316 rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1317 rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1318
1319 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1320
1321 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1322 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1323 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1324 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1325 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1326 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1327 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1328 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1329
1330 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1331 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1332 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1333 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1334 } else {
1335 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1336 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1337 }
1338
1339 rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1340 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1341 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1342 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1343 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1344 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1345 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1346 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1347 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1348 rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1349
1350 rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1351 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1352 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1353 rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1354
1355 rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1356 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1357 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1358 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1359 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1360 else
1361 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1362 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1363 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1364 rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1365
1366 rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1367
1368 rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1369 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1370 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1371 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1372 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1373 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1374 rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1375
1376 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1377 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1378 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1379 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1380 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1381 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1382 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1383 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1384 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1385 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1386 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1387
1388 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1389 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1390 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1391 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1392 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1393 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1394 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1395 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1396 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1397 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1398 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1399
1400 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1401 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1402 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1403 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1404 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1405 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1406 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1407 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1408 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1409 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1410 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1411
1412 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1413 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1414 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1415 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1416 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1417 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1418 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1419 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1420 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1421 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1422 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1423
1424 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1425 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1426 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1427 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1428 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1429 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1430 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1431 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1432 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1433 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1434 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1435
1436 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1437 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1438 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1439 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1440 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1441 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1442 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1443 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1444 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1445 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1446 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1447
1448 rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1449
1450 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1451 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1452 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1453 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1454 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1455 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1456 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1457 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1458 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1459 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1460 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1461
1462 rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1463 rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1464
1465 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1466 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1467 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1468 IEEE80211_MAX_RTS_THRESHOLD);
1469 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1470 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1471
1472 rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1473 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1474
1475 /*
1476 * ASIC will keep garbage value after boot, clear encryption keys.
1477 */
1478 for (i = 0; i < 256; i++) {
1479 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1480 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1481 wcid, sizeof(wcid));
1482
1483 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1484 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1485 }
1486
1487 for (i = 0; i < 16; i++)
1488 rt2x00usb_register_write(rt2x00dev,
1489 SHARED_KEY_MODE_ENTRY(i), 0);
1490
1491 /*
1492 * Clear all beacons
1493 * For the Beacon base registers we only need to clear
1494 * the first byte since that byte contains the VALID and OWNER
1495 * bits which (when set to 0) will invalidate the entire beacon.
1496 */
1497 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1498 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1499 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1500 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1501 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1502 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1503 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1504 rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1505
1506 rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1507 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1508 rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1509
1510 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1511 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1512 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1513 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1514 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1515 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1516 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1517 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1518 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1519 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1520
1521 rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1522 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1523 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1524 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1525 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1526 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1527 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1528 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1529 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1530 rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1531
1532 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1533 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1534 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1535 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1536 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1537 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1538 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1539 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1540 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1541 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1542
1543 rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1544 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1545 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1546 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1547 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1548 rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1549
1550 /*
1551 * We must clear the error counters.
1552 * These registers are cleared on read,
1553 * so we may pass a useless variable to store the value.
1554 */
1555 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1556 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1557 rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1558 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1559 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1560 rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1561
1562 return 0;
1563}
1564
1565static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1566{
1567 unsigned int i;
1568 u32 reg;
1569
1570 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1571 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1572 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1573 return 0;
1574
1575 udelay(REGISTER_BUSY_DELAY);
1576 }
1577
1578 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1579 return -EACCES;
1580}
1581
1582static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1583{
1584 unsigned int i;
1585 u8 value;
1586
1587 /*
1588 * BBP was enabled after firmware was loaded,
1589 * but we need to reactivate it now.
1590 */
1591 rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1592 rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1593 msleep(1);
1594
1595 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1596 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1597 if ((value != 0xff) && (value != 0x00))
1598 return 0;
1599 udelay(REGISTER_BUSY_DELAY);
1600 }
1601
1602 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1603 return -EACCES;
1604}
1605
1606static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1607{
1608 unsigned int i;
1609 u16 eeprom;
1610 u8 reg_id;
1611 u8 value;
1612
1613 if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1614 rt2800usb_wait_bbp_ready(rt2x00dev)))
1615 return -EACCES;
1616
1617 rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1618 rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1619 rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1620 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1621 rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1622 rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1623 rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1624 rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1625 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1626 rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1627 rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1628 rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1629 rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1630 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1631
1632 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1633 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1634 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1635 }
1636
1637 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1638 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1639 }
1640
1641 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1642 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1643 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1644 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1645 }
1646
1647 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1648 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1649
1650 if (eeprom != 0xffff && eeprom != 0x0000) {
1651 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1652 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1653 rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1654 }
1655 }
1656
1657 return 0;
1658}
1659
1660static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1661 bool bw40, u8 rfcsr24, u8 filter_target)
1662{
1663 unsigned int i;
1664 u8 bbp;
1665 u8 rfcsr;
1666 u8 passband;
1667 u8 stopband;
1668 u8 overtuned = 0;
1669
1670 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1671
1672 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1673 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1674 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1675
1676 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1677 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1678 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1679
1680 /*
1681 * Set power & frequency of passband test tone
1682 */
1683 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1684
1685 for (i = 0; i < 100; i++) {
1686 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1687 msleep(1);
1688
1689 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1690 if (passband)
1691 break;
1692 }
1693
1694 /*
1695 * Set power & frequency of stopband test tone
1696 */
1697 rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1698
1699 for (i = 0; i < 100; i++) {
1700 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1701 msleep(1);
1702
1703 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1704
1705 if ((passband - stopband) <= filter_target) {
1706 rfcsr24++;
1707 overtuned += ((passband - stopband) == filter_target);
1708 } else
1709 break;
1710
1711 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1712 }
1713
1714 rfcsr24 -= !!overtuned;
1715
1716 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1717 return rfcsr24;
1718}
1719
1720static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1721{
1722 u8 rfcsr;
1723 u8 bbp;
1724
1725 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1726 return 0;
1727
1728 /*
1729 * Init RF calibration.
1730 */
1731 rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1732 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1733 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1734 msleep(1);
1735 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1736 rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1737
1738 rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1739 rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1740 rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1741 rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1742 rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1743 rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1744 rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1745 rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1746 rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1747 rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1748 rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1749 rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1750 rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1751 rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1752 rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1753 rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1754 rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1755 rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1756 rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1757 rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1758
1759 /*
1760 * Set RX Filter calibration for 20MHz and 40MHz
1761 */
1762 rt2x00dev->calibration[0] =
1763 rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1764 rt2x00dev->calibration[1] =
1765 rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1766
1767 /*
1768 * Set back to initial state
1769 */
1770 rt2800usb_bbp_write(rt2x00dev, 24, 0);
1771
1772 rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1773 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1774 rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1775
1776 /*
1777 * set BBP back to BW20
1778 */
1779 rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1780 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1781 rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1782
1783 return 0;
1784}
1785
1786/*
1787 * Device state switch handlers.
1788 */
1789static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1790 enum dev_state state)
1791{
1792 u32 reg;
1793
1794 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1795 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1796 (state == STATE_RADIO_RX_ON) ||
1797 (state == STATE_RADIO_RX_ON_LINK));
1798 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1799}
1800
1801static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1802{
1803 unsigned int i;
1804 u32 reg;
1805
1806 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1807 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1808 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1809 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1810 return 0;
1811
1812 msleep(1);
1813 }
1814
1815 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1816 return -EACCES;
1817}
1818
1819static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1820{
1821 u32 reg;
1822 u16 word;
1823
1824 /*
1825 * Initialize all registers.
1826 */
1827 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1828 rt2800usb_init_registers(rt2x00dev) ||
1829 rt2800usb_init_bbp(rt2x00dev) ||
1830 rt2800usb_init_rfcsr(rt2x00dev)))
1831 return -EIO;
1832
1833 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1834 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1835 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1836
1837 udelay(50);
1838
1839 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1840 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1841 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1842 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1843 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1844
1845
1846 rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1847 rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1848 /* Don't use bulk in aggregation when working with USB 1.1 */
1849 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1850 (rt2x00dev->rx->usb_maxpacket == 512));
1851 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1852 /*
1853 * Total room for RX frames in kilobytes, PBF might still exceed
1854 * this limit so reduce the number to prevent errors.
1855 */
1856 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1857 ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1858 rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1859 rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1860 rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1861
1862 rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1863 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1864 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1865 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1866
1867 /*
1868 * Initialize LED control
1869 */
1870 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1871 rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1872 word & 0xff, (word >> 8) & 0xff);
1873
1874 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1875 rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1876 word & 0xff, (word >> 8) & 0xff);
1877
1878 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1879 rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1880 word & 0xff, (word >> 8) & 0xff);
1881
1882 return 0;
1883}
1884
1885static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1886{
1887 u32 reg;
1888
1889 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1890 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1891 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1892 rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1893
1894 rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1895 rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1896 rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1897
1898 /* Wait for DMA, ignore error */
1899 rt2800usb_wait_wpdma_ready(rt2x00dev);
1900
1901 rt2x00usb_disable_radio(rt2x00dev);
1902}
1903
1904static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1905 enum dev_state state)
1906{
1907 if (state == STATE_AWAKE)
1908 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1909 else
1910 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1911
1912 return 0;
1913}
1914
1915static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1916 enum dev_state state)
1917{
1918 int retval = 0;
1919
1920 switch (state) {
1921 case STATE_RADIO_ON:
1922 /*
1923 * Before the radio can be enabled, the device first has
1924 * to be woken up. After that it needs a bit of time
1925 * to be fully awake and the radio can be enabled.
1926 */
1927 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1928 msleep(1);
1929 retval = rt2800usb_enable_radio(rt2x00dev);
1930 break;
1931 case STATE_RADIO_OFF:
1932 /*
1933 * After the radio has been disablee, the device should
1934 * be put to sleep for powersaving.
1935 */
1936 rt2800usb_disable_radio(rt2x00dev);
1937 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1938 break;
1939 case STATE_RADIO_RX_ON:
1940 case STATE_RADIO_RX_ON_LINK:
1941 case STATE_RADIO_RX_OFF:
1942 case STATE_RADIO_RX_OFF_LINK:
1943 rt2800usb_toggle_rx(rt2x00dev, state);
1944 break;
1945 case STATE_RADIO_IRQ_ON:
1946 case STATE_RADIO_IRQ_OFF:
1947 /* No support, but no error either */
1948 break;
1949 case STATE_DEEP_SLEEP:
1950 case STATE_SLEEP:
1951 case STATE_STANDBY:
1952 case STATE_AWAKE:
1953 retval = rt2800usb_set_state(rt2x00dev, state);
1954 break;
1955 default:
1956 retval = -ENOTSUPP;
1957 break;
1958 }
1959
1960 if (unlikely(retval))
1961 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1962 state, retval);
1963
1964 return retval;
1965}
1966
1967/*
1968 * TX descriptor initialization
1969 */
1970static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1971 struct sk_buff *skb,
1972 struct txentry_desc *txdesc)
1973{
1974 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1975 __le32 *txi = skbdesc->desc;
1976 __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1977 u32 word;
1978
1979 /*
1980 * Initialize TX Info descriptor
1981 */
1982 rt2x00_desc_read(txwi, 0, &word);
1983 rt2x00_set_field32(&word, TXWI_W0_FRAG,
1984 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1985 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1986 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1987 rt2x00_set_field32(&word, TXWI_W0_TS,
1988 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1989 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1990 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1991 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1992 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1993 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1994 rt2x00_set_field32(&word, TXWI_W0_BW,
1995 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1996 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1997 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1998 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1999 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2000 rt2x00_desc_write(txwi, 0, word);
2001
2002 rt2x00_desc_read(txwi, 1, &word);
2003 rt2x00_set_field32(&word, TXWI_W1_ACK,
2004 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2005 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2006 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2007 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2008 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2009 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2010 txdesc->key_idx : 0xff);
2011 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2012 skb->len - txdesc->l2pad);
2013 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2014 skbdesc->entry->entry_idx);
2015 rt2x00_desc_write(txwi, 1, word);
2016
2017 /*
2018 * Always write 0 to IV/EIV fields, hardware will insert the IV
2019 * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2020 * When TXINFO_W0_WIV is set to 1 it will use the IV data
2021 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2022 * crypto entry in the registers should be used to encrypt the frame.
2023 */
2024 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2025 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2026
2027 /*
2028 * Initialize TX descriptor
2029 */
2030 rt2x00_desc_read(txi, 0, &word);
2031 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2032 skb->len + TXWI_DESC_SIZE);
2033 rt2x00_set_field32(&word, TXINFO_W0_WIV,
2034 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2035 rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2036 rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2037 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2038 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2039 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2040 rt2x00_desc_write(txi, 0, word);
2041}
2042
2043/*
2044 * TX data initialization
2045 */
2046static void rt2800usb_write_beacon(struct queue_entry *entry)
2047{
2048 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2049 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2050 unsigned int beacon_base;
2051 u32 reg;
2052
2053 /*
2054 * Add the descriptor in front of the skb.
2055 */
2056 skb_push(entry->skb, entry->queue->desc_size);
2057 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2058 skbdesc->desc = entry->skb->data;
2059
2060 /*
2061 * Disable beaconing while we are reloading the beacon data,
2062 * otherwise we might be sending out invalid data.
2063 */
2064 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2065 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2066 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2067 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2068 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2069
2070 /*
2071 * Write entire beacon with descriptor to register.
2072 */
2073 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2074 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2075 USB_VENDOR_REQUEST_OUT, beacon_base,
2076 entry->skb->data, entry->skb->len,
2077 REGISTER_TIMEOUT32(entry->skb->len));
2078
2079 /*
2080 * Clean up the beacon skb.
2081 */
2082 dev_kfree_skb(entry->skb);
2083 entry->skb = NULL;
2084}
2085
2086static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2087{
2088 int length;
2089
2090 /*
2091 * The length _must_ include 4 bytes padding,
2092 * it should always be multiple of 4,
2093 * but it must _not_ be a multiple of the USB packet size.
2094 */
2095 length = roundup(entry->skb->len + 4, 4);
2096 length += (4 * !(length % entry->queue->usb_maxpacket));
2097
2098 return length;
2099}
2100
2101static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2102 const enum data_queue_qid queue)
2103{
2104 u32 reg;
2105
2106 if (queue != QID_BEACON) {
2107 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2108 return;
2109 }
2110
2111 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2112 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2113 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2114 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2115 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2116 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2117 }
2118}
2119
2120/*
2121 * RX control handlers
2122 */
2123static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2124 struct rxdone_entry_desc *rxdesc)
2125{
2126 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2127 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2128 __le32 *rxd = (__le32 *)entry->skb->data;
2129 __le32 *rxwi;
2130 u32 rxd0;
2131 u32 rxwi0;
2132 u32 rxwi1;
2133 u32 rxwi2;
2134 u32 rxwi3;
2135
2136 /*
2137 * Copy descriptor to the skbdesc->desc buffer, making it safe from
2138 * moving of frame data in rt2x00usb.
2139 */
2140 memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2141 rxd = (__le32 *)skbdesc->desc;
2142 rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2143
2144 /*
2145 * It is now safe to read the descriptor on all architectures.
2146 */
2147 rt2x00_desc_read(rxd, 0, &rxd0);
2148 rt2x00_desc_read(rxwi, 0, &rxwi0);
2149 rt2x00_desc_read(rxwi, 1, &rxwi1);
2150 rt2x00_desc_read(rxwi, 2, &rxwi2);
2151 rt2x00_desc_read(rxwi, 3, &rxwi3);
2152
2153 if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2154 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2155
2156 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2157 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2158 rxdesc->cipher_status =
2159 rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2160 }
2161
2162 if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2163 /*
2164 * Hardware has stripped IV/EIV data from 802.11 frame during
2165 * decryption. Unfortunately the descriptor doesn't contain
2166 * any fields with the EIV/IV data either, so they can't
2167 * be restored by rt2x00lib.
2168 */
2169 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2170
2171 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2172 rxdesc->flags |= RX_FLAG_DECRYPTED;
2173 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2174 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2175 }
2176
2177 if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2178 rxdesc->dev_flags |= RXDONE_MY_BSS;
2179
2180 if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD))
2181 rxdesc->dev_flags |= RXDONE_L2PAD;
2182
2183 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2184 rxdesc->flags |= RX_FLAG_SHORT_GI;
2185
2186 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2187 rxdesc->flags |= RX_FLAG_40MHZ;
2188
2189 /*
2190 * Detect RX rate, always use MCS as signal type.
2191 */
2192 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2193 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2194 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2195
2196 /*
2197 * Mask of 0x8 bit to remove the short preamble flag.
2198 */
2199 if (rxdesc->rate_mode == RATE_MODE_CCK)
2200 rxdesc->signal &= ~0x8;
2201
2202 rxdesc->rssi =
2203 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2204 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2205
2206 rxdesc->noise =
2207 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2208 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2209
2210 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2211
2212 /*
2213 * Remove RXWI descriptor from start of buffer.
2214 */
2215 skb_pull(entry->skb, skbdesc->desc_len);
2216 skb_trim(entry->skb, rxdesc->size);
2217}
2218
2219/*
2220 * Device probe functions.
2221 */
2222static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2223{
2224 u16 word;
2225 u8 *mac;
2226 u8 default_lna_gain;
2227
2228 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2229
2230 /*
2231 * Start validation of the data that has been read.
2232 */
2233 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2234 if (!is_valid_ether_addr(mac)) {
2235 DECLARE_MAC_BUF(macbuf);
2236
2237 random_ether_addr(mac);
2238 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2239 }
2240
2241 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2242 if (word == 0xffff) {
2243 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2244 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2245 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2246 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2247 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2248 } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2249 /*
2250 * There is a max of 2 RX streams for RT2870 series
2251 */
2252 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2253 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2254 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2255 }
2256
2257 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2258 if (word == 0xffff) {
2259 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2260 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2261 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2262 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2263 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2264 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2265 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2266 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2267 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2268 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2269 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2270 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2271 }
2272
2273 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2274 if ((word & 0x00ff) == 0x00ff) {
2275 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2276 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2277 LED_MODE_TXRX_ACTIVITY);
2278 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2279 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2280 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2281 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2282 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2283 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2284 }
2285
2286 /*
2287 * During the LNA validation we are going to use
2288 * lna0 as correct value. Note that EEPROM_LNA
2289 * is never validated.
2290 */
2291 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2292 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2293
2294 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2295 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2296 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2297 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2298 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2299 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2300
2301 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2302 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2303 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2304 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2305 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2306 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2307 default_lna_gain);
2308 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2309
2310 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2311 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2312 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2313 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2314 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2315 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2316
2317 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2318 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2319 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2320 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2321 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2322 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2323 default_lna_gain);
2324 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2325
2326 return 0;
2327}
2328
2329static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2330{
2331 u32 reg;
2332 u16 value;
2333 u16 eeprom;
2334
2335 /*
2336 * Read EEPROM word for configuration.
2337 */
2338 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2339
2340 /*
2341 * Identify RF chipset.
2342 */
2343 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2344 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2345 rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2346
2347 /*
2348 * The check for rt2860 is not a typo, some rt2870 hardware
2349 * identifies itself as rt2860 in the CSR register.
2350 */
2351 if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2352 !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2353 !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2354 !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2355 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2356 return -ENODEV;
2357 }
2358
2359 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2360 !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2361 !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2362 !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2363 !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2364 !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2365 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2366 return -ENODEV;
2367 }
2368
2369 /*
2370 * Identify default antenna configuration.
2371 */
2372 rt2x00dev->default_ant.tx =
2373 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2374 rt2x00dev->default_ant.rx =
2375 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2376
2377 /*
2378 * Read frequency offset and RF programming sequence.
2379 */
2380 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2381 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2382
2383 /*
2384 * Read external LNA informations.
2385 */
2386 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2387
2388 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2389 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2390 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2391 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2392
2393 /*
2394 * Detect if this device has an hardware controlled radio.
2395 */
2396#ifdef CONFIG_RT2X00_LIB_RFKILL
2397 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2398 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2399#endif /* CONFIG_RT2X00_LIB_RFKILL */
2400
2401 /*
2402 * Store led settings, for correct led behaviour.
2403 */
2404#ifdef CONFIG_RT2X00_LIB_LEDS
2405 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2406 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2407 rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2408
2409 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2410 &rt2x00dev->led_mcu_reg);
2411#endif /* CONFIG_RT2X00_LIB_LEDS */
2412
2413 return 0;
2414}
2415
2416/*
2417 * RF value list for rt2870
2418 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2419 */
2420static const struct rf_channel rf_vals[] = {
2421 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2422 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2423 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2424 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2425 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2426 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2427 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2428 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2429 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2430 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2431 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2432 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2433 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2434 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2435
2436 /* 802.11 UNI / HyperLan 2 */
2437 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2438 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2439 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2440 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2441 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2442 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2443 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2444 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2445 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2446 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2447 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2448 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2449
2450 /* 802.11 HyperLan 2 */
2451 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2452 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2453 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2454 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2455 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2456 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2457 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2458 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2459 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2460 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2461 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2462 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2463 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2464 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2465 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2466 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2467
2468 /* 802.11 UNII */
2469 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2470 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2471 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2472 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2473 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2474 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2475 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2476 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2477 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2478 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2479 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2480
2481 /* 802.11 Japan */
2482 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2483 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2484 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2485 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2486 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2487 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2488 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2489};
2490
2491/*
2492 * RF value list for rt3070
2493 * Supports: 2.4 GHz
2494 */
2495static const struct rf_channel rf_vals_3070[] = {
2496 {1, 241, 2, 2 },
2497 {2, 241, 2, 7 },
2498 {3, 242, 2, 2 },
2499 {4, 242, 2, 7 },
2500 {5, 243, 2, 2 },
2501 {6, 243, 2, 7 },
2502 {7, 244, 2, 2 },
2503 {8, 244, 2, 7 },
2504 {9, 245, 2, 2 },
2505 {10, 245, 2, 7 },
2506 {11, 246, 2, 2 },
2507 {12, 246, 2, 7 },
2508 {13, 247, 2, 2 },
2509 {14, 248, 2, 4 },
2510};
2511
2512static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2513{
2514 struct hw_mode_spec *spec = &rt2x00dev->spec;
2515 struct channel_info *info;
2516 char *tx_power1;
2517 char *tx_power2;
2518 unsigned int i;
2519 u16 eeprom;
2520
2521 /*
2522 * Initialize all hw fields.
2523 */
2524 rt2x00dev->hw->flags =
2525 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2526 IEEE80211_HW_SIGNAL_DBM |
2527 IEEE80211_HW_SUPPORTS_PS |
2528 IEEE80211_HW_PS_NULLFUNC_STACK;
2529 rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2530
2531 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2532 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2533 rt2x00_eeprom_addr(rt2x00dev,
2534 EEPROM_MAC_ADDR_0));
2535
2536 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2537
2538 /*
2539 * Initialize HT information.
2540 */
2541 spec->ht.ht_supported = true;
2542 spec->ht.cap =
2543 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2544 IEEE80211_HT_CAP_GRN_FLD |
2545 IEEE80211_HT_CAP_SGI_20 |
2546 IEEE80211_HT_CAP_SGI_40 |
2547 IEEE80211_HT_CAP_TX_STBC |
2548 IEEE80211_HT_CAP_RX_STBC |
2549 IEEE80211_HT_CAP_PSMP_SUPPORT;
2550 spec->ht.ampdu_factor = 3;
2551 spec->ht.ampdu_density = 4;
2552 spec->ht.mcs.tx_params =
2553 IEEE80211_HT_MCS_TX_DEFINED |
2554 IEEE80211_HT_MCS_TX_RX_DIFF |
2555 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2556 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2557
2558 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2559 case 3:
2560 spec->ht.mcs.rx_mask[2] = 0xff;
2561 case 2:
2562 spec->ht.mcs.rx_mask[1] = 0xff;
2563 case 1:
2564 spec->ht.mcs.rx_mask[0] = 0xff;
2565 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2566 break;
2567 }
2568
2569 /*
2570 * Initialize hw_mode information.
2571 */
2572 spec->supported_bands = SUPPORT_BAND_2GHZ;
2573 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2574
2575 if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2576 rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2577 spec->num_channels = 14;
2578 spec->channels = rf_vals;
2579 } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2580 rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2581 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2582 spec->num_channels = ARRAY_SIZE(rf_vals);
2583 spec->channels = rf_vals;
2584 } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2585 rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2586 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2587 spec->channels = rf_vals_3070;
2588 }
2589
2590 /*
2591 * Create channel information array
2592 */
2593 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2594 if (!info)
2595 return -ENOMEM;
2596
2597 spec->channels_info = info;
2598
2599 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2600 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2601
2602 for (i = 0; i < 14; i++) {
2603 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2604 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2605 }
2606
2607 if (spec->num_channels > 14) {
2608 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2609 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2610
2611 for (i = 14; i < spec->num_channels; i++) {
2612 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2613 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2614 }
2615 }
2616
2617 return 0;
2618}
2619
2620static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2621{
2622 int retval;
2623
2624 /*
2625 * Allocate eeprom data.
2626 */
2627 retval = rt2800usb_validate_eeprom(rt2x00dev);
2628 if (retval)
2629 return retval;
2630
2631 retval = rt2800usb_init_eeprom(rt2x00dev);
2632 if (retval)
2633 return retval;
2634
2635 /*
2636 * Initialize hw specifications.
2637 */
2638 retval = rt2800usb_probe_hw_mode(rt2x00dev);
2639 if (retval)
2640 return retval;
2641
2642 /*
2643 * This device requires firmware.
2644 */
2645 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2646 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
2647 __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2648 if (!modparam_nohwcrypt)
2649 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2650
2651 /*
2652 * Set the rssi offset.
2653 */
2654 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2655
2656 return 0;
2657}
2658
2659/*
2660 * IEEE80211 stack callback functions.
2661 */
2662static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2663 u32 *iv32, u16 *iv16)
2664{
2665 struct rt2x00_dev *rt2x00dev = hw->priv;
2666 struct mac_iveiv_entry iveiv_entry;
2667 u32 offset;
2668
2669 offset = MAC_IVEIV_ENTRY(hw_key_idx);
2670 rt2x00usb_register_multiread(rt2x00dev, offset,
2671 &iveiv_entry, sizeof(iveiv_entry));
2672
2673 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2674 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2675}
2676
2677static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2678{
2679 struct rt2x00_dev *rt2x00dev = hw->priv;
2680 u32 reg;
2681 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2682
2683 rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2684 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2685 rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2686
2687 rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2688 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2689 rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2690
2691 rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2692 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2693 rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2694
2695 rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2696 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2697 rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2698
2699 rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2700 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2701 rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2702
2703 rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2704 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2705 rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2706
2707 rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2708 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2709 rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2710
2711 return 0;
2712}
2713
2714static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2715 const struct ieee80211_tx_queue_params *params)
2716{
2717 struct rt2x00_dev *rt2x00dev = hw->priv;
2718 struct data_queue *queue;
2719 struct rt2x00_field32 field;
2720 int retval;
2721 u32 reg;
2722 u32 offset;
2723
2724 /*
2725 * First pass the configuration through rt2x00lib, that will
2726 * update the queue settings and validate the input. After that
2727 * we are free to update the registers based on the value
2728 * in the queue parameter.
2729 */
2730 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2731 if (retval)
2732 return retval;
2733
2734 /*
2735 * We only need to perform additional register initialization
2736 * for WMM queues/
2737 */
2738 if (queue_idx >= 4)
2739 return 0;
2740
2741 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2742
2743 /* Update WMM TXOP register */
2744 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2745 field.bit_offset = (queue_idx & 1) * 16;
2746 field.bit_mask = 0xffff << field.bit_offset;
2747
2748 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2749 rt2x00_set_field32(&reg, field, queue->txop);
2750 rt2x00usb_register_write(rt2x00dev, offset, reg);
2751
2752 /* Update WMM registers */
2753 field.bit_offset = queue_idx * 4;
2754 field.bit_mask = 0xf << field.bit_offset;
2755
2756 rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2757 rt2x00_set_field32(&reg, field, queue->aifs);
2758 rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2759
2760 rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2761 rt2x00_set_field32(&reg, field, queue->cw_min);
2762 rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2763
2764 rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2765 rt2x00_set_field32(&reg, field, queue->cw_max);
2766 rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2767
2768 /* Update EDCA registers */
2769 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2770
2771 rt2x00usb_register_read(rt2x00dev, offset, &reg);
2772 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2773 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2774 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2775 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2776 rt2x00usb_register_write(rt2x00dev, offset, reg);
2777
2778 return 0;
2779}
2780
2781static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2782{
2783 struct rt2x00_dev *rt2x00dev = hw->priv;
2784 u64 tsf;
2785 u32 reg;
2786
2787 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2788 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2789 rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2790 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2791
2792 return tsf;
2793}
2794
2795static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2796 .tx = rt2x00mac_tx,
2797 .start = rt2x00mac_start,
2798 .stop = rt2x00mac_stop,
2799 .add_interface = rt2x00mac_add_interface,
2800 .remove_interface = rt2x00mac_remove_interface,
2801 .config = rt2x00mac_config,
2802 .configure_filter = rt2x00mac_configure_filter,
2803 .set_key = rt2x00mac_set_key,
2804 .get_stats = rt2x00mac_get_stats,
2805 .get_tkip_seq = rt2800usb_get_tkip_seq,
2806 .set_rts_threshold = rt2800usb_set_rts_threshold,
2807 .bss_info_changed = rt2x00mac_bss_info_changed,
2808 .conf_tx = rt2800usb_conf_tx,
2809 .get_tx_stats = rt2x00mac_get_tx_stats,
2810 .get_tsf = rt2800usb_get_tsf,
2811};
2812
2813static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2814 .probe_hw = rt2800usb_probe_hw,
2815 .get_firmware_name = rt2800usb_get_firmware_name,
2816 .check_firmware = rt2800usb_check_firmware,
2817 .load_firmware = rt2800usb_load_firmware,
2818 .initialize = rt2x00usb_initialize,
2819 .uninitialize = rt2x00usb_uninitialize,
2820 .clear_entry = rt2x00usb_clear_entry,
2821 .set_device_state = rt2800usb_set_device_state,
2822 .rfkill_poll = rt2800usb_rfkill_poll,
2823 .link_stats = rt2800usb_link_stats,
2824 .reset_tuner = rt2800usb_reset_tuner,
2825 .link_tuner = rt2800usb_link_tuner,
2826 .write_tx_desc = rt2800usb_write_tx_desc,
2827 .write_tx_data = rt2x00usb_write_tx_data,
2828 .write_beacon = rt2800usb_write_beacon,
2829 .get_tx_data_len = rt2800usb_get_tx_data_len,
2830 .kick_tx_queue = rt2800usb_kick_tx_queue,
2831 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2832 .fill_rxdone = rt2800usb_fill_rxdone,
2833 .config_shared_key = rt2800usb_config_shared_key,
2834 .config_pairwise_key = rt2800usb_config_pairwise_key,
2835 .config_filter = rt2800usb_config_filter,
2836 .config_intf = rt2800usb_config_intf,
2837 .config_erp = rt2800usb_config_erp,
2838 .config_ant = rt2800usb_config_ant,
2839 .config = rt2800usb_config,
2840};
2841
2842static const struct data_queue_desc rt2800usb_queue_rx = {
2843 .entry_num = RX_ENTRIES,
2844 .data_size = AGGREGATION_SIZE,
2845 .desc_size = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2846 .priv_size = sizeof(struct queue_entry_priv_usb),
2847};
2848
2849static const struct data_queue_desc rt2800usb_queue_tx = {
2850 .entry_num = TX_ENTRIES,
2851 .data_size = AGGREGATION_SIZE,
2852 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2853 .priv_size = sizeof(struct queue_entry_priv_usb),
2854};
2855
2856static const struct data_queue_desc rt2800usb_queue_bcn = {
2857 .entry_num = 8 * BEACON_ENTRIES,
2858 .data_size = MGMT_FRAME_SIZE,
2859 .desc_size = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2860 .priv_size = sizeof(struct queue_entry_priv_usb),
2861};
2862
2863static const struct rt2x00_ops rt2800usb_ops = {
2864 .name = KBUILD_MODNAME,
2865 .max_sta_intf = 1,
2866 .max_ap_intf = 8,
2867 .eeprom_size = EEPROM_SIZE,
2868 .rf_size = RF_SIZE,
2869 .tx_queues = NUM_TX_QUEUES,
2870 .rx = &rt2800usb_queue_rx,
2871 .tx = &rt2800usb_queue_tx,
2872 .bcn = &rt2800usb_queue_bcn,
2873 .lib = &rt2800usb_rt2x00_ops,
2874 .hw = &rt2800usb_mac80211_ops,
2875#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2876 .debugfs = &rt2800usb_rt2x00debug,
2877#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2878};
2879
2880/*
2881 * rt2800usb module information.
2882 */
2883static struct usb_device_id rt2800usb_device_table[] = {
2884 /* ??? */
2885 { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
2886 /* Abocom */
2887 { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2888 { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2889 { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2890 { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2891 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2892 { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2893 /* AirTies */
2894 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2895 /* Amigo */
2896 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2897 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2898 /* Amit */
2899 { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2900 /* ASUS */
2901 { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2902 { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2903 { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2904 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2905 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2906 /* AzureWave */
2907 { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2908 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2909 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2910 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2911 /* Belkin */
2912 { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2913 { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2914 { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2915 /* Buffalo */
2916 { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2917 { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2918 /* Conceptronic */
2919 { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2920 { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2921 { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2922 { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2923 { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2924 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2925 { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2926 { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2927 { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2928 { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2929 /* Corega */
2930 { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2931 { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2932 { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2933 { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2934 { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2935 /* D-Link */
2936 { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2937 { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2938 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2939 { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2940 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2941 /* Edimax */
2942 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2943 { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2944 { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2945 /* EnGenius */
2946 { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2947 { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2948 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2949 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2950 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2951 { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2952 /* Gemtek */
2953 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2954 /* Gigabyte */
2955 { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2956 { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2957 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2958 /* Hawking */
2959 { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2960 { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2961 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2962 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2963 /* LevelOne */
2964 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2965 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2966 /* Linksys */
2967 { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2968 { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2969 { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2970 /* Logitec */
2971 { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2972 { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2973 { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2974 /* Motorola */
2975 { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2976 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2977 /* Ovislink */
2978 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2979 /* Pegatron */
2980 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2981 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2982 /* Philips */
2983 { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2984 /* Planex */
2985 { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2986 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2987 { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2988 /* Qcom */
2989 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2990 /* Quanta */
2991 { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2992 /* Ralink */
2993 { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2994 { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2995 { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2996 { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2997 { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2998 { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2999 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
3000 { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
3001 /* Samsung */
3002 { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3003 /* Siemens */
3004 { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3005 /* Sitecom */
3006 { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3007 { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3008 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3009 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3010 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3011 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3012 { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3013 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3014 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3015 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3016 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3017 /* SMC */
3018 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3019 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3020 { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3021 { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3022 { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3023 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3024 { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3025 { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3026 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3027 /* Sparklan */
3028 { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3029 /* U-Media*/
3030 { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3031 /* ZCOM */
3032 { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3033 { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3034 /* Zinwell */
3035 { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3036 { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3037 /* Zyxel */
3038 { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3039 { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3040 { 0, }
3041};
3042
3043MODULE_AUTHOR(DRV_PROJECT);
3044MODULE_VERSION(DRV_VERSION);
3045MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3046MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3047MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3048MODULE_FIRMWARE(FIRMWARE_RT2870);
3049MODULE_LICENSE("GPL");
3050
3051static struct usb_driver rt2800usb_driver = {
3052 .name = KBUILD_MODNAME,
3053 .id_table = rt2800usb_device_table,
3054 .probe = rt2x00usb_probe,
3055 .disconnect = rt2x00usb_disconnect,
3056 .suspend = rt2x00usb_suspend,
3057 .resume = rt2x00usb_resume,
3058};
3059
3060static int __init rt2800usb_init(void)
3061{
3062 return usb_register(&rt2800usb_driver);
3063}
3064
3065static void __exit rt2800usb_exit(void)
3066{
3067 usb_deregister(&rt2800usb_driver);
3068}
3069
3070module_init(rt2800usb_init);
3071module_exit(rt2800usb_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-01 07:59:07 -0500