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path: root/drivers/net/wireless/rt2x00/rt2800usb.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800usb.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c541
1 files changed, 3 insertions, 538 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 365f66fe7c68..f5b864b1a55d 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -230,541 +230,6 @@ static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
230} 230}
231 231
232/* 232/*
233 * Initialization functions.
234 */
235static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238 unsigned int i;
239
240 if (rt2x00_intf_is_usb(rt2x00dev)) {
241 /*
242 * Wait untill BBP and RF are ready.
243 */
244 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
245 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
246 if (reg && reg != ~0)
247 break;
248 msleep(1);
249 }
250
251 if (i == REGISTER_BUSY_COUNT) {
252 ERROR(rt2x00dev, "Unstable hardware.\n");
253 return -EBUSY;
254 }
255
256 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
257 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
258 reg & ~0x00002000);
259 }
260
261 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
262 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
263 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
264 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
265
266 if (rt2x00_intf_is_usb(rt2x00dev)) {
267 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
268
269 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
270 USB_MODE_RESET, REGISTER_TIMEOUT);
271 }
272
273 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
274
275 rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
276 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
277 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
278 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
279 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
280 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
281
282 rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
283 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
284 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
285 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
286 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
287 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
288
289 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
290 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
291
292 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
293
294 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
295 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
296 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
297 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
298 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
299 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
300 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
301 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
302
303 if (rt2x00_intf_is_usb(rt2x00dev) &&
304 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
305 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
306 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
307 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
308 } else {
309 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
310 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
311 }
312
313 rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
314 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
315 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
316 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
317 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
318 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
319 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
320 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
321 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
322 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
323
324 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
325 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
326 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
327 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
328
329 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
330 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
331 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
332 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
333 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
334 else
335 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
336 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
337 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
338 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
339
340 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
341
342 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
343 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
344 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
345 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
346 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
347 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
348 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
349
350 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
351 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
352 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
353 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
354 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
355 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
356 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
357 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
358 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
359 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
360 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
361
362 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
363 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
364 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
365 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
366 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
367 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
368 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
369 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
370 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
371 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
372 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
373
374 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
375 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
376 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
377 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
378 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
379 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
380 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
381 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
382 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
383 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
384 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
385
386 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
387 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
388 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
389 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
390 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
391 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
392 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
393 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
394 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
395 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
396 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
397
398 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
399 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
400 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
401 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
402 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
403 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
404 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
405 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
406 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
407 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
408 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
409
410 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
411 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
412 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
413 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
414 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
415 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
416 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
417 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
418 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
419 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
420 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
421
422 if (rt2x00_intf_is_usb(rt2x00dev)) {
423 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
424
425 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
426 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
427 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
428 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
429 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
430 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
431 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
432 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
433 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
434 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
435 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
436 }
437
438 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
439 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
440
441 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
442 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
443 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
444 IEEE80211_MAX_RTS_THRESHOLD);
445 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
446 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
447
448 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
449 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
450
451 /*
452 * ASIC will keep garbage value after boot, clear encryption keys.
453 */
454 for (i = 0; i < 4; i++)
455 rt2800_register_write(rt2x00dev,
456 SHARED_KEY_MODE_ENTRY(i), 0);
457
458 for (i = 0; i < 256; i++) {
459 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
460 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
461 wcid, sizeof(wcid));
462
463 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
464 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
465 }
466
467 /*
468 * Clear all beacons
469 * For the Beacon base registers we only need to clear
470 * the first byte since that byte contains the VALID and OWNER
471 * bits which (when set to 0) will invalidate the entire beacon.
472 */
473 rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
474 rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
475 rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
476 rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
477 rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
478 rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
479 rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
480 rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
481
482 if (rt2x00_intf_is_usb(rt2x00dev)) {
483 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
484 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
485 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
486 }
487
488 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
489 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
490 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
491 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
492 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
493 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
494 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
495 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
496 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
497 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
498
499 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
500 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
501 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
502 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
503 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
504 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
505 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
506 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
507 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
508 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
509
510 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
511 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
512 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
513 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
514 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
515 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
516 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
517 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
518 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
519 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
520
521 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
522 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
523 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
524 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
525 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
526 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
527
528 /*
529 * We must clear the error counters.
530 * These registers are cleared on read,
531 * so we may pass a useless variable to store the value.
532 */
533 rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
534 rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
535 rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
536 rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
537 rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
538 rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
539
540 return 0;
541}
542
543static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
544{
545 unsigned int i;
546 u32 reg;
547
548 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
549 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
550 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
551 return 0;
552
553 udelay(REGISTER_BUSY_DELAY);
554 }
555
556 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
557 return -EACCES;
558}
559
560static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
561{
562 unsigned int i;
563 u8 value;
564
565 /*
566 * BBP was enabled after firmware was loaded,
567 * but we need to reactivate it now.
568 */
569 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
570 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
571 msleep(1);
572
573 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
574 rt2800_bbp_read(rt2x00dev, 0, &value);
575 if ((value != 0xff) && (value != 0x00))
576 return 0;
577 udelay(REGISTER_BUSY_DELAY);
578 }
579
580 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
581 return -EACCES;
582}
583
584static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
585{
586 unsigned int i;
587 u16 eeprom;
588 u8 reg_id;
589 u8 value;
590
591 if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
592 rt2800usb_wait_bbp_ready(rt2x00dev)))
593 return -EACCES;
594
595 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
596 rt2800_bbp_write(rt2x00dev, 66, 0x38);
597 rt2800_bbp_write(rt2x00dev, 69, 0x12);
598 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
599 rt2800_bbp_write(rt2x00dev, 73, 0x10);
600 rt2800_bbp_write(rt2x00dev, 81, 0x37);
601 rt2800_bbp_write(rt2x00dev, 82, 0x62);
602 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
603 rt2800_bbp_write(rt2x00dev, 84, 0x99);
604 rt2800_bbp_write(rt2x00dev, 86, 0x00);
605 rt2800_bbp_write(rt2x00dev, 91, 0x04);
606 rt2800_bbp_write(rt2x00dev, 92, 0x00);
607 rt2800_bbp_write(rt2x00dev, 103, 0x00);
608 rt2800_bbp_write(rt2x00dev, 105, 0x05);
609
610 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
611 rt2800_bbp_write(rt2x00dev, 69, 0x16);
612 rt2800_bbp_write(rt2x00dev, 73, 0x12);
613 }
614
615 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
616 rt2800_bbp_write(rt2x00dev, 84, 0x19);
617
618 if (rt2x00_intf_is_usb(rt2x00dev) &&
619 rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
620 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
621 rt2800_bbp_write(rt2x00dev, 84, 0x99);
622 rt2800_bbp_write(rt2x00dev, 105, 0x05);
623 }
624
625 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
626 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
627
628 if (eeprom != 0xffff && eeprom != 0x0000) {
629 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
630 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
631 rt2800_bbp_write(rt2x00dev, reg_id, value);
632 }
633 }
634
635 return 0;
636}
637
638static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
639 bool bw40, u8 rfcsr24, u8 filter_target)
640{
641 unsigned int i;
642 u8 bbp;
643 u8 rfcsr;
644 u8 passband;
645 u8 stopband;
646 u8 overtuned = 0;
647
648 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
649
650 rt2800_bbp_read(rt2x00dev, 4, &bbp);
651 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
652 rt2800_bbp_write(rt2x00dev, 4, bbp);
653
654 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
655 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
656 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
657
658 /*
659 * Set power & frequency of passband test tone
660 */
661 rt2800_bbp_write(rt2x00dev, 24, 0);
662
663 for (i = 0; i < 100; i++) {
664 rt2800_bbp_write(rt2x00dev, 25, 0x90);
665 msleep(1);
666
667 rt2800_bbp_read(rt2x00dev, 55, &passband);
668 if (passband)
669 break;
670 }
671
672 /*
673 * Set power & frequency of stopband test tone
674 */
675 rt2800_bbp_write(rt2x00dev, 24, 0x06);
676
677 for (i = 0; i < 100; i++) {
678 rt2800_bbp_write(rt2x00dev, 25, 0x90);
679 msleep(1);
680
681 rt2800_bbp_read(rt2x00dev, 55, &stopband);
682
683 if ((passband - stopband) <= filter_target) {
684 rfcsr24++;
685 overtuned += ((passband - stopband) == filter_target);
686 } else
687 break;
688
689 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
690 }
691
692 rfcsr24 -= !!overtuned;
693
694 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
695 return rfcsr24;
696}
697
698static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
699{
700 u8 rfcsr;
701 u8 bbp;
702
703 if (rt2x00_intf_is_usb(rt2x00dev) &&
704 rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
705 return 0;
706
707 /*
708 * Init RF calibration.
709 */
710 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
711 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
712 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
713 msleep(1);
714 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
715 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
716
717 if (rt2x00_intf_is_usb(rt2x00dev)) {
718 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
719 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
720 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
721 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
722 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
723 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
724 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
725 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
726 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
727 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
728 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
729 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
730 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
731 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
732 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
733 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
734 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
735 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
736 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
737 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
738 }
739
740 /*
741 * Set RX Filter calibration for 20MHz and 40MHz
742 */
743 rt2x00dev->calibration[0] =
744 rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
745 rt2x00dev->calibration[1] =
746 rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
747
748 /*
749 * Set back to initial state
750 */
751 rt2800_bbp_write(rt2x00dev, 24, 0);
752
753 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
754 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
755 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
756
757 /*
758 * set BBP back to BW20
759 */
760 rt2800_bbp_read(rt2x00dev, 4, &bbp);
761 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
762 rt2800_bbp_write(rt2x00dev, 4, bbp);
763
764 return 0;
765}
766
767/*
768 * Device state switch handlers. 233 * Device state switch handlers.
769 */ 234 */
770static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev, 235static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
@@ -806,9 +271,9 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
806 * Initialize all registers. 271 * Initialize all registers.
807 */ 272 */
808 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) || 273 if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
809 rt2800usb_init_registers(rt2x00dev) || 274 rt2800_init_registers(rt2x00dev) ||
810 rt2800usb_init_bbp(rt2x00dev) || 275 rt2800_init_bbp(rt2x00dev) ||
811 rt2800usb_init_rfcsr(rt2x00dev))) 276 rt2800_init_rfcsr(rt2x00dev)))
812 return -EIO; 277 return -EIO;
813 278
814 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 279 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 11:50:01 -0500