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path: root/drivers/net/wireless/rt2x00/rt2800pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c1908
1 files changed, 135 insertions, 1773 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index be81788b80c7..3c5b875cdee8 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -37,6 +37,8 @@
37#include "rt2x00.h" 37#include "rt2x00.h"
38#include "rt2x00pci.h" 38#include "rt2x00pci.h"
39#include "rt2x00soc.h" 39#include "rt2x00soc.h"
40#include "rt2800lib.h"
41#include "rt2800.h"
40#include "rt2800pci.h" 42#include "rt2800pci.h"
41 43
42#ifdef CONFIG_RT2800PCI_PCI_MODULE 44#ifdef CONFIG_RT2800PCI_PCI_MODULE
@@ -54,205 +56,13 @@ static int modparam_nohwcrypt = 1;
54module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); 56module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 57MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
56 58
57/*
58 * Register access.
59 * BBP and RF register require indirect register access,
60 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
61 * These indirect registers work with busy bits,
62 * and we will try maximal REGISTER_BUSY_COUNT times to access
63 * the register while taking a REGISTER_BUSY_DELAY us delay
64 * between each attampt. When the busy bit is still set at that time,
65 * the access attempt is considered to have failed,
66 * and we will print an error.
67 */
68#define WAIT_FOR_BBP(__dev, __reg) \
69 rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
70#define WAIT_FOR_RFCSR(__dev, __reg) \
71 rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
72#define WAIT_FOR_RF(__dev, __reg) \
73 rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
74#define WAIT_FOR_MCU(__dev, __reg) \
75 rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
76 H2M_MAILBOX_CSR_OWNER, (__reg))
77
78static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
79 const unsigned int word, const u8 value)
80{
81 u32 reg;
82
83 mutex_lock(&rt2x00dev->csr_mutex);
84
85 /*
86 * Wait until the BBP becomes available, afterwards we
87 * can safely write the new data into the register.
88 */
89 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
90 reg = 0;
91 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
92 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
93 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
94 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
95 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
96
97 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
98 }
99
100 mutex_unlock(&rt2x00dev->csr_mutex);
101}
102
103static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
104 const unsigned int word, u8 *value)
105{
106 u32 reg;
107
108 mutex_lock(&rt2x00dev->csr_mutex);
109
110 /*
111 * Wait until the BBP becomes available, afterwards we
112 * can safely write the read request into the register.
113 * After the data has been written, we wait until hardware
114 * returns the correct value, if at any time the register
115 * doesn't become available in time, reg will be 0xffffffff
116 * which means we return 0xff to the caller.
117 */
118 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
119 reg = 0;
120 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
121 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
122 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
123 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
124
125 rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
126
127 WAIT_FOR_BBP(rt2x00dev, &reg);
128 }
129
130 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
131
132 mutex_unlock(&rt2x00dev->csr_mutex);
133}
134
135static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u8 value)
137{
138 u32 reg;
139
140 mutex_lock(&rt2x00dev->csr_mutex);
141
142 /*
143 * Wait until the RFCSR becomes available, afterwards we
144 * can safely write the new data into the register.
145 */
146 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
147 reg = 0;
148 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
149 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
150 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
151 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
152
153 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
154 }
155
156 mutex_unlock(&rt2x00dev->csr_mutex);
157}
158
159static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
160 const unsigned int word, u8 *value)
161{
162 u32 reg;
163
164 mutex_lock(&rt2x00dev->csr_mutex);
165
166 /*
167 * Wait until the RFCSR becomes available, afterwards we
168 * can safely write the read request into the register.
169 * After the data has been written, we wait until hardware
170 * returns the correct value, if at any time the register
171 * doesn't become available in time, reg will be 0xffffffff
172 * which means we return 0xff to the caller.
173 */
174 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
175 reg = 0;
176 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
177 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
178 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
179
180 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
181
182 WAIT_FOR_RFCSR(rt2x00dev, &reg);
183 }
184
185 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
186
187 mutex_unlock(&rt2x00dev->csr_mutex);
188}
189
190static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
191 const unsigned int word, const u32 value)
192{
193 u32 reg;
194
195 mutex_lock(&rt2x00dev->csr_mutex);
196
197 /*
198 * Wait until the RF becomes available, afterwards we
199 * can safely write the new data into the register.
200 */
201 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
202 reg = 0;
203 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
204 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
205 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
206 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
207
208 rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
209 rt2x00_rf_write(rt2x00dev, word, value);
210 }
211
212 mutex_unlock(&rt2x00dev->csr_mutex);
213}
214
215static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
216 const u8 command, const u8 token,
217 const u8 arg0, const u8 arg1)
218{
219 u32 reg;
220
221 /*
222 * RT2880 and RT3052 don't support MCU requests.
223 */
224 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
225 rt2x00_rt(&rt2x00dev->chip, RT3052))
226 return;
227
228 mutex_lock(&rt2x00dev->csr_mutex);
229
230 /*
231 * Wait until the MCU becomes available, afterwards we
232 * can safely write the new data into the register.
233 */
234 if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
235 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
236 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
237 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
238 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
239 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
240
241 reg = 0;
242 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
243 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
244 }
245
246 mutex_unlock(&rt2x00dev->csr_mutex);
247}
248
249static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token) 59static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
250{ 60{
251 unsigned int i; 61 unsigned int i;
252 u32 reg; 62 u32 reg;
253 63
254 for (i = 0; i < 200; i++) { 64 for (i = 0; i < 200; i++) {
255 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 65 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
256 66
257 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) || 67 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
258 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) || 68 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
@@ -266,8 +76,8 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
266 if (i == 200) 76 if (i == 200)
267 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n"); 77 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
268 78
269 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0); 79 rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
270 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0); 80 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
271} 81}
272 82
273#ifdef CONFIG_RT2800PCI_WISOC 83#ifdef CONFIG_RT2800PCI_WISOC
@@ -289,7 +99,7 @@ static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
289 struct rt2x00_dev *rt2x00dev = eeprom->data; 99 struct rt2x00_dev *rt2x00dev = eeprom->data;
290 u32 reg; 100 u32 reg;
291 101
292 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 102 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
293 103
294 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); 104 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
295 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); 105 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
@@ -311,7 +121,7 @@ static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
311 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT, 121 rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
312 !!eeprom->reg_chip_select); 122 !!eeprom->reg_chip_select);
313 123
314 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg); 124 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
315} 125}
316 126
317static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev) 127static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
@@ -319,7 +129,7 @@ static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
319 struct eeprom_93cx6 eeprom; 129 struct eeprom_93cx6 eeprom;
320 u32 reg; 130 u32 reg;
321 131
322 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg); 132 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
323 133
324 eeprom.data = rt2x00dev; 134 eeprom.data = rt2x00dev;
325 eeprom.register_read = rt2800pci_eepromregister_read; 135 eeprom.register_read = rt2800pci_eepromregister_read;
@@ -340,23 +150,23 @@ static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
340{ 150{
341 u32 reg; 151 u32 reg;
342 152
343 rt2x00pci_register_read(rt2x00dev, EFUSE_CTRL, &reg); 153 rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
344 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i); 154 rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
345 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0); 155 rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
346 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1); 156 rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
347 rt2x00pci_register_write(rt2x00dev, EFUSE_CTRL, reg); 157 rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
348 158
349 /* Wait until the EEPROM has been loaded */ 159 /* Wait until the EEPROM has been loaded */
350 rt2x00pci_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg); 160 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
351 161
352 /* Apparently the data is read from end to start */ 162 /* Apparently the data is read from end to start */
353 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA3, 163 rt2800_register_read(rt2x00dev, EFUSE_DATA3,
354 (u32 *)&rt2x00dev->eeprom[i]); 164 (u32 *)&rt2x00dev->eeprom[i]);
355 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA2, 165 rt2800_register_read(rt2x00dev, EFUSE_DATA2,
356 (u32 *)&rt2x00dev->eeprom[i + 2]); 166 (u32 *)&rt2x00dev->eeprom[i + 2]);
357 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA1, 167 rt2800_register_read(rt2x00dev, EFUSE_DATA1,
358 (u32 *)&rt2x00dev->eeprom[i + 4]); 168 (u32 *)&rt2x00dev->eeprom[i + 4]);
359 rt2x00pci_register_read(rt2x00dev, EFUSE_DATA0, 169 rt2800_register_read(rt2x00dev, EFUSE_DATA0,
360 (u32 *)&rt2x00dev->eeprom[i + 6]); 170 (u32 *)&rt2x00dev->eeprom[i + 6]);
361} 171}
362 172
@@ -377,829 +187,6 @@ static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
377} 187}
378#endif /* CONFIG_RT2800PCI_PCI */ 188#endif /* CONFIG_RT2800PCI_PCI */
379 189
380#ifdef CONFIG_RT2X00_LIB_DEBUGFS
381static const struct rt2x00debug rt2800pci_rt2x00debug = {
382 .owner = THIS_MODULE,
383 .csr = {
384 .read = rt2x00pci_register_read,
385 .write = rt2x00pci_register_write,
386 .flags = RT2X00DEBUGFS_OFFSET,
387 .word_base = CSR_REG_BASE,
388 .word_size = sizeof(u32),
389 .word_count = CSR_REG_SIZE / sizeof(u32),
390 },
391 .eeprom = {
392 .read = rt2x00_eeprom_read,
393 .write = rt2x00_eeprom_write,
394 .word_base = EEPROM_BASE,
395 .word_size = sizeof(u16),
396 .word_count = EEPROM_SIZE / sizeof(u16),
397 },
398 .bbp = {
399 .read = rt2800pci_bbp_read,
400 .write = rt2800pci_bbp_write,
401 .word_base = BBP_BASE,
402 .word_size = sizeof(u8),
403 .word_count = BBP_SIZE / sizeof(u8),
404 },
405 .rf = {
406 .read = rt2x00_rf_read,
407 .write = rt2800pci_rf_write,
408 .word_base = RF_BASE,
409 .word_size = sizeof(u32),
410 .word_count = RF_SIZE / sizeof(u32),
411 },
412};
413#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
414
415static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
416{
417 u32 reg;
418
419 rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
420 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
421}
422
423#ifdef CONFIG_RT2X00_LIB_LEDS
424static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
425 enum led_brightness brightness)
426{
427 struct rt2x00_led *led =
428 container_of(led_cdev, struct rt2x00_led, led_dev);
429 unsigned int enabled = brightness != LED_OFF;
430 unsigned int bg_mode =
431 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
432 unsigned int polarity =
433 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
434 EEPROM_FREQ_LED_POLARITY);
435 unsigned int ledmode =
436 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
437 EEPROM_FREQ_LED_MODE);
438
439 if (led->type == LED_TYPE_RADIO) {
440 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
441 enabled ? 0x20 : 0);
442 } else if (led->type == LED_TYPE_ASSOC) {
443 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
444 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
445 } else if (led->type == LED_TYPE_QUALITY) {
446 /*
447 * The brightness is divided into 6 levels (0 - 5),
448 * The specs tell us the following levels:
449 * 0, 1 ,3, 7, 15, 31
450 * to determine the level in a simple way we can simply
451 * work with bitshifting:
452 * (1 << level) - 1
453 */
454 rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
455 (1 << brightness / (LED_FULL / 6)) - 1,
456 polarity);
457 }
458}
459
460static int rt2800pci_blink_set(struct led_classdev *led_cdev,
461 unsigned long *delay_on,
462 unsigned long *delay_off)
463{
464 struct rt2x00_led *led =
465 container_of(led_cdev, struct rt2x00_led, led_dev);
466 u32 reg;
467
468 rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
469 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
470 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
471 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
472 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
473 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
474 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
475 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
476 rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
477
478 return 0;
479}
480
481static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
482 struct rt2x00_led *led,
483 enum led_type type)
484{
485 led->rt2x00dev = rt2x00dev;
486 led->type = type;
487 led->led_dev.brightness_set = rt2800pci_brightness_set;
488 led->led_dev.blink_set = rt2800pci_blink_set;
489 led->flags = LED_INITIALIZED;
490}
491#endif /* CONFIG_RT2X00_LIB_LEDS */
492
493/*
494 * Configuration handlers.
495 */
496static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
497 struct rt2x00lib_crypto *crypto,
498 struct ieee80211_key_conf *key)
499{
500 struct mac_wcid_entry wcid_entry;
501 struct mac_iveiv_entry iveiv_entry;
502 u32 offset;
503 u32 reg;
504
505 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
506
507 rt2x00pci_register_read(rt2x00dev, offset, &reg);
508 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
509 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
510 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
511 (crypto->cmd == SET_KEY) * crypto->cipher);
512 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
513 (crypto->cmd == SET_KEY) * crypto->bssidx);
514 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
515 rt2x00pci_register_write(rt2x00dev, offset, reg);
516
517 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
518
519 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
520 if ((crypto->cipher == CIPHER_TKIP) ||
521 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
522 (crypto->cipher == CIPHER_AES))
523 iveiv_entry.iv[3] |= 0x20;
524 iveiv_entry.iv[3] |= key->keyidx << 6;
525 rt2x00pci_register_multiwrite(rt2x00dev, offset,
526 &iveiv_entry, sizeof(iveiv_entry));
527
528 offset = MAC_WCID_ENTRY(key->hw_key_idx);
529
530 memset(&wcid_entry, 0, sizeof(wcid_entry));
531 if (crypto->cmd == SET_KEY)
532 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
533 rt2x00pci_register_multiwrite(rt2x00dev, offset,
534 &wcid_entry, sizeof(wcid_entry));
535}
536
537static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
538 struct rt2x00lib_crypto *crypto,
539 struct ieee80211_key_conf *key)
540{
541 struct hw_key_entry key_entry;
542 struct rt2x00_field32 field;
543 u32 offset;
544 u32 reg;
545
546 if (crypto->cmd == SET_KEY) {
547 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
548
549 memcpy(key_entry.key, crypto->key,
550 sizeof(key_entry.key));
551 memcpy(key_entry.tx_mic, crypto->tx_mic,
552 sizeof(key_entry.tx_mic));
553 memcpy(key_entry.rx_mic, crypto->rx_mic,
554 sizeof(key_entry.rx_mic));
555
556 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
557 rt2x00pci_register_multiwrite(rt2x00dev, offset,
558 &key_entry, sizeof(key_entry));
559 }
560
561 /*
562 * The cipher types are stored over multiple registers
563 * starting with SHARED_KEY_MODE_BASE each word will have
564 * 32 bits and contains the cipher types for 2 bssidx each.
565 * Using the correct defines correctly will cause overhead,
566 * so just calculate the correct offset.
567 */
568 field.bit_offset = 4 * (key->hw_key_idx % 8);
569 field.bit_mask = 0x7 << field.bit_offset;
570
571 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
572
573 rt2x00pci_register_read(rt2x00dev, offset, &reg);
574 rt2x00_set_field32(&reg, field,
575 (crypto->cmd == SET_KEY) * crypto->cipher);
576 rt2x00pci_register_write(rt2x00dev, offset, reg);
577
578 /*
579 * Update WCID information
580 */
581 rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
582
583 return 0;
584}
585
586static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
587 struct rt2x00lib_crypto *crypto,
588 struct ieee80211_key_conf *key)
589{
590 struct hw_key_entry key_entry;
591 u32 offset;
592
593 if (crypto->cmd == SET_KEY) {
594 /*
595 * 1 pairwise key is possible per AID, this means that the AID
596 * equals our hw_key_idx. Make sure the WCID starts _after_ the
597 * last possible shared key entry.
598 */
599 if (crypto->aid > (256 - 32))
600 return -ENOSPC;
601
602 key->hw_key_idx = 32 + crypto->aid;
603
604
605 memcpy(key_entry.key, crypto->key,
606 sizeof(key_entry.key));
607 memcpy(key_entry.tx_mic, crypto->tx_mic,
608 sizeof(key_entry.tx_mic));
609 memcpy(key_entry.rx_mic, crypto->rx_mic,
610 sizeof(key_entry.rx_mic));
611
612 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
613 rt2x00pci_register_multiwrite(rt2x00dev, offset,
614 &key_entry, sizeof(key_entry));
615 }
616
617 /*
618 * Update WCID information
619 */
620 rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
621
622 return 0;
623}
624
625static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
626 const unsigned int filter_flags)
627{
628 u32 reg;
629
630 /*
631 * Start configuration steps.
632 * Note that the version error will always be dropped
633 * and broadcast frames will always be accepted since
634 * there is no filter for it at this time.
635 */
636 rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
637 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
638 !(filter_flags & FIF_FCSFAIL));
639 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
640 !(filter_flags & FIF_PLCPFAIL));
641 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
642 !(filter_flags & FIF_PROMISC_IN_BSS));
643 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
644 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
645 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
646 !(filter_flags & FIF_ALLMULTI));
647 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
648 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
649 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
650 !(filter_flags & FIF_CONTROL));
651 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
652 !(filter_flags & FIF_CONTROL));
653 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
654 !(filter_flags & FIF_CONTROL));
655 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
656 !(filter_flags & FIF_CONTROL));
657 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
658 !(filter_flags & FIF_CONTROL));
659 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
660 !(filter_flags & FIF_PSPOLL));
661 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
662 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
663 rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
664 !(filter_flags & FIF_CONTROL));
665 rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
666}
667
668static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
669 struct rt2x00_intf *intf,
670 struct rt2x00intf_conf *conf,
671 const unsigned int flags)
672{
673 unsigned int beacon_base;
674 u32 reg;
675
676 if (flags & CONFIG_UPDATE_TYPE) {
677 /*
678 * Clear current synchronisation setup.
679 * For the Beacon base registers we only need to clear
680 * the first byte since that byte contains the VALID and OWNER
681 * bits which (when set to 0) will invalidate the entire beacon.
682 */
683 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
684 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
685
686 /*
687 * Enable synchronisation.
688 */
689 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
690 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
691 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
692 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
693 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
694 }
695
696 if (flags & CONFIG_UPDATE_MAC) {
697 reg = le32_to_cpu(conf->mac[1]);
698 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
699 conf->mac[1] = cpu_to_le32(reg);
700
701 rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
702 conf->mac, sizeof(conf->mac));
703 }
704
705 if (flags & CONFIG_UPDATE_BSSID) {
706 reg = le32_to_cpu(conf->bssid[1]);
707 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
708 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
709 conf->bssid[1] = cpu_to_le32(reg);
710
711 rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
712 conf->bssid, sizeof(conf->bssid));
713 }
714}
715
716static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
717 struct rt2x00lib_erp *erp)
718{
719 u32 reg;
720
721 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
722 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
723 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
724
725 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
726 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
727 !!erp->short_preamble);
728 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
729 !!erp->short_preamble);
730 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
731
732 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
733 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
734 erp->cts_protection ? 2 : 0);
735 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
736
737 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
738 erp->basic_rates);
739 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
740
741 rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
742 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
743 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
744 rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
745
746 rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
747 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
748 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
749 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
750 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
751 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
752 rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
753
754 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
755 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
756 erp->beacon_int * 16);
757 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
758}
759
760static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
761 struct antenna_setup *ant)
762{
763 u8 r1;
764 u8 r3;
765
766 rt2800pci_bbp_read(rt2x00dev, 1, &r1);
767 rt2800pci_bbp_read(rt2x00dev, 3, &r3);
768
769 /*
770 * Configure the TX antenna.
771 */
772 switch ((int)ant->tx) {
773 case 1:
774 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
775 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
776 break;
777 case 2:
778 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
779 break;
780 case 3:
781 /* Do nothing */
782 break;
783 }
784
785 /*
786 * Configure the RX antenna.
787 */
788 switch ((int)ant->rx) {
789 case 1:
790 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
791 break;
792 case 2:
793 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
794 break;
795 case 3:
796 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
797 break;
798 }
799
800 rt2800pci_bbp_write(rt2x00dev, 3, r3);
801 rt2800pci_bbp_write(rt2x00dev, 1, r1);
802}
803
804static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
805 struct rt2x00lib_conf *libconf)
806{
807 u16 eeprom;
808 short lna_gain;
809
810 if (libconf->rf.channel <= 14) {
811 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
812 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
813 } else if (libconf->rf.channel <= 64) {
814 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
815 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
816 } else if (libconf->rf.channel <= 128) {
817 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
818 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
819 } else {
820 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
821 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
822 }
823
824 rt2x00dev->lna_gain = lna_gain;
825}
826
827static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
828 struct ieee80211_conf *conf,
829 struct rf_channel *rf,
830 struct channel_info *info)
831{
832 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
833
834 if (rt2x00dev->default_ant.tx == 1)
835 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
836
837 if (rt2x00dev->default_ant.rx == 1) {
838 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
839 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
840 } else if (rt2x00dev->default_ant.rx == 2)
841 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
842
843 if (rf->channel > 14) {
844 /*
845 * When TX power is below 0, we should increase it by 7 to
846 * make it a positive value (Minumum value is -7).
847 * However this means that values between 0 and 7 have
848 * double meaning, and we should set a 7DBm boost flag.
849 */
850 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
851 (info->tx_power1 >= 0));
852
853 if (info->tx_power1 < 0)
854 info->tx_power1 += 7;
855
856 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
857 TXPOWER_A_TO_DEV(info->tx_power1));
858
859 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
860 (info->tx_power2 >= 0));
861
862 if (info->tx_power2 < 0)
863 info->tx_power2 += 7;
864
865 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
866 TXPOWER_A_TO_DEV(info->tx_power2));
867 } else {
868 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
869 TXPOWER_G_TO_DEV(info->tx_power1));
870 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
871 TXPOWER_G_TO_DEV(info->tx_power2));
872 }
873
874 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
875
876 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
877 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
878 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
879 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
880
881 udelay(200);
882
883 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
884 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
885 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
886 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
887
888 udelay(200);
889
890 rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
891 rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
892 rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
893 rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
894}
895
896static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
897 struct ieee80211_conf *conf,
898 struct rf_channel *rf,
899 struct channel_info *info)
900{
901 u8 rfcsr;
902
903 rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
904 rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
905
906 rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
907 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
908 rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
909
910 rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
911 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
912 TXPOWER_G_TO_DEV(info->tx_power1));
913 rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
914
915 rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
916 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
917 rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
918
919 rt2800pci_rfcsr_write(rt2x00dev, 24,
920 rt2x00dev->calibration[conf_is_ht40(conf)]);
921
922 rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
923 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
924 rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
925}
926
927static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
928 struct ieee80211_conf *conf,
929 struct rf_channel *rf,
930 struct channel_info *info)
931{
932 u32 reg;
933 unsigned int tx_pin;
934 u8 bbp;
935
936 if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
937 rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
938 else
939 rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
940
941 /*
942 * Change BBP settings
943 */
944 rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
945 rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
946 rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
947 rt2800pci_bbp_write(rt2x00dev, 86, 0);
948
949 if (rf->channel <= 14) {
950 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
951 rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
952 rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
953 } else {
954 rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
955 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
956 }
957 } else {
958 rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
959
960 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
961 rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
962 else
963 rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
964 }
965
966 rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
967 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
968 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
969 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
970 rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
971
972 tx_pin = 0;
973
974 /* Turn on unused PA or LNA when not using 1T or 1R */
975 if (rt2x00dev->default_ant.tx != 1) {
976 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
977 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
978 }
979
980 /* Turn on unused PA or LNA when not using 1T or 1R */
981 if (rt2x00dev->default_ant.rx != 1) {
982 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
983 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
984 }
985
986 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
987 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
988 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
989 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
990 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
991 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
992
993 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
994
995 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
996 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
997 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
998
999 rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1000 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1001 rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1002
1003 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1004 if (conf_is_ht40(conf)) {
1005 rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1006 rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1007 rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1008 } else {
1009 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1010 rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1011 rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1012 }
1013 }
1014
1015 msleep(1);
1016}
1017
1018static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1019 const int txpower)
1020{
1021 u32 reg;
1022 u32 value = TXPOWER_G_TO_DEV(txpower);
1023 u8 r1;
1024
1025 rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1026 rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1027 rt2800pci_bbp_write(rt2x00dev, 1, r1);
1028
1029 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1030 rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1031 rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1032 rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1033 rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1034 rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1035 rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1036 rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1037 rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1038 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1039
1040 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1041 rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1042 rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1043 rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1044 rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1045 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1046 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1047 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1048 rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1049 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1050
1051 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1052 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1053 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1054 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1055 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1056 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1057 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1058 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1059 rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1060 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1061
1062 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1063 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1064 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1065 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1066 rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1067 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1068 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1069 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1070 rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1071 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1072
1073 rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1074 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1075 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1076 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1077 rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1078 rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1079}
1080
1081static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1082 struct rt2x00lib_conf *libconf)
1083{
1084 u32 reg;
1085
1086 rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1087 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1088 libconf->conf->short_frame_max_tx_count);
1089 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1090 libconf->conf->long_frame_max_tx_count);
1091 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1092 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1093 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1094 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1095 rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1096}
1097
1098static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1099 struct rt2x00lib_conf *libconf)
1100{
1101 enum dev_state state =
1102 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1103 STATE_SLEEP : STATE_AWAKE;
1104 u32 reg;
1105
1106 if (state == STATE_SLEEP) {
1107 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1108
1109 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1110 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1111 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1112 libconf->conf->listen_interval - 1);
1113 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1114 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1115
1116 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1117 } else {
1118 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1119
1120 rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1121 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1122 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1123 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1124 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1125 }
1126}
1127
1128static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1129 struct rt2x00lib_conf *libconf,
1130 const unsigned int flags)
1131{
1132 /* Always recalculate LNA gain before changing configuration */
1133 rt2800pci_config_lna_gain(rt2x00dev, libconf);
1134
1135 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1136 rt2800pci_config_channel(rt2x00dev, libconf->conf,
1137 &libconf->rf, &libconf->channel);
1138 if (flags & IEEE80211_CONF_CHANGE_POWER)
1139 rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1140 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1141 rt2800pci_config_retry_limit(rt2x00dev, libconf);
1142 if (flags & IEEE80211_CONF_CHANGE_PS)
1143 rt2800pci_config_ps(rt2x00dev, libconf);
1144}
1145
1146/*
1147 * Link tuning
1148 */
1149static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1150 struct link_qual *qual)
1151{
1152 u32 reg;
1153
1154 /*
1155 * Update FCS error count from register.
1156 */
1157 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1158 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1159}
1160
1161static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1162{
1163 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1164 return 0x2e + rt2x00dev->lna_gain;
1165
1166 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1167 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1168 else
1169 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1170}
1171
1172static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1173 struct link_qual *qual, u8 vgc_level)
1174{
1175 if (qual->vgc_level != vgc_level) {
1176 rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1177 qual->vgc_level = vgc_level;
1178 qual->vgc_level_reg = vgc_level;
1179 }
1180}
1181
1182static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1183 struct link_qual *qual)
1184{
1185 rt2800pci_set_vgc(rt2x00dev, qual,
1186 rt2800pci_get_default_vgc(rt2x00dev));
1187}
1188
1189static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1190 struct link_qual *qual, const u32 count)
1191{
1192 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1193 return;
1194
1195 /*
1196 * When RSSI is better then -80 increase VGC level with 0x10
1197 */
1198 rt2800pci_set_vgc(rt2x00dev, qual,
1199 rt2800pci_get_default_vgc(rt2x00dev) +
1200 ((qual->rssi > -80) * 0x10));
1201}
1202
1203/* 190/*
1204 * Firmware functions 191 * Firmware functions
1205 */ 192 */
@@ -1257,7 +244,7 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1257 * Wait for stable hardware. 244 * Wait for stable hardware.
1258 */ 245 */
1259 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 246 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1260 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 247 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1261 if (reg && reg != ~0) 248 if (reg && reg != ~0)
1262 break; 249 break;
1263 msleep(1); 250 msleep(1);
@@ -1268,42 +255,42 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1268 return -EBUSY; 255 return -EBUSY;
1269 } 256 }
1270 257
1271 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002); 258 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1272 rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000); 259 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1273 260
1274 /* 261 /*
1275 * Disable DMA, will be reenabled later when enabling 262 * Disable DMA, will be reenabled later when enabling
1276 * the radio. 263 * the radio.
1277 */ 264 */
1278 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 265 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1279 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 266 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1280 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 267 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1281 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 268 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1282 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 269 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1283 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 270 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1284 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 271 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1285 272
1286 /* 273 /*
1287 * enable Host program ram write selection 274 * enable Host program ram write selection
1288 */ 275 */
1289 reg = 0; 276 reg = 0;
1290 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1); 277 rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1291 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg); 278 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1292 279
1293 /* 280 /*
1294 * Write firmware to device. 281 * Write firmware to device.
1295 */ 282 */
1296 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, 283 rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1297 data, len); 284 data, len);
1298 285
1299 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000); 286 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1300 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001); 287 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1301 288
1302 /* 289 /*
1303 * Wait for device to stabilize. 290 * Wait for device to stabilize.
1304 */ 291 */
1305 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 292 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1306 rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 293 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1307 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) 294 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1308 break; 295 break;
1309 msleep(1); 296 msleep(1);
@@ -1322,8 +309,8 @@ static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1322 /* 309 /*
1323 * Initialize BBP R/W access agent 310 * Initialize BBP R/W access agent
1324 */ 311 */
1325 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 312 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1326 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 313 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1327 314
1328 return 0; 315 return 0;
1329} 316}
@@ -1373,7 +360,7 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1373 struct queue_entry_priv_pci *entry_priv; 360 struct queue_entry_priv_pci *entry_priv;
1374 u32 reg; 361 u32 reg;
1375 362
1376 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 363 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1377 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 364 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1378 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 365 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1379 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 366 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -1381,539 +368,54 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1381 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 368 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1382 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 369 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1383 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 370 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1384 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 371 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1385 372
1386 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 373 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1387 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 374 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1388 375
1389 /* 376 /*
1390 * Initialize registers. 377 * Initialize registers.
1391 */ 378 */
1392 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; 379 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1393 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma); 380 rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1394 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit); 381 rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1395 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0); 382 rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1396 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0); 383 rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1397 384
1398 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; 385 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1399 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma); 386 rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1400 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit); 387 rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1401 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0); 388 rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1402 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0); 389 rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1403 390
1404 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; 391 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1405 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma); 392 rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1406 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit); 393 rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1407 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0); 394 rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1408 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0); 395 rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1409 396
1410 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; 397 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1411 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma); 398 rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1412 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit); 399 rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1413 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0); 400 rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1414 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0); 401 rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1415 402
1416 entry_priv = rt2x00dev->rx->entries[0].priv_data; 403 entry_priv = rt2x00dev->rx->entries[0].priv_data;
1417 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma); 404 rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1418 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit); 405 rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1419 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1); 406 rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1420 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0); 407 rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
1421 408
1422 /* 409 /*
1423 * Enable global DMA configuration 410 * Enable global DMA configuration
1424 */ 411 */
1425 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 412 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1426 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 413 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1427 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 414 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1428 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 415 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1429 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1430
1431 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1432
1433 return 0;
1434}
1435
1436static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1437{
1438 u32 reg;
1439 unsigned int i;
1440
1441 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1442
1443 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1444 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1445 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1446 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1447
1448 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1449
1450 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1451 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1452 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1453 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1454 rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1455 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1456
1457 rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1458 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1459 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1460 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1461 rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1462 rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1463
1464 rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1465 rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1466
1467 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1468
1469 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1470 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1471 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1472 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1473 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1474 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1475 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1476 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1477
1478 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1479 rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1480
1481 rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1482 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1483 rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1484 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1485 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1486 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1487 rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1488 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1489 rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1490 rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1491
1492 rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1493 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1494 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1495 rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1496
1497 rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1498 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1499 if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1500 rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1501 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1502 else
1503 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1504 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1505 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1506 rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1507
1508 rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1509
1510 rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1511 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1512 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1513 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1514 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1515 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1516 rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1517
1518 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1519 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1520 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1521 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1522 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1523 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1524 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1525 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1526 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1527 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1528 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1529
1530 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1531 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1532 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1533 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1534 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1535 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1536 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1537 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1538 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1539 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1540 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1541
1542 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1543 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1544 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1545 rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1546 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1547 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1548 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1549 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1550 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1551 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1552 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1553
1554 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1555 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1556 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1557 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1558 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1559 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1560 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1561 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1562 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1563 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1564 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1565
1566 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1567 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1568 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1569 rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1570 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1571 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1572 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1573 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1574 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1575 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1576 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1577
1578 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1579 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1580 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1581 rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1582 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1583 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1584 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1585 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1586 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1587 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1588 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1589
1590 rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1591 rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1592
1593 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1594 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1595 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1596 IEEE80211_MAX_RTS_THRESHOLD);
1597 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1598 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1599
1600 rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1601 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1602
1603 /*
1604 * ASIC will keep garbage value after boot, clear encryption keys.
1605 */
1606 for (i = 0; i < 4; i++)
1607 rt2x00pci_register_write(rt2x00dev,
1608 SHARED_KEY_MODE_ENTRY(i), 0);
1609
1610 for (i = 0; i < 256; i++) {
1611 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1612 rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1613 wcid, sizeof(wcid));
1614
1615 rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1616 rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1617 }
1618
1619 /*
1620 * Clear all beacons
1621 * For the Beacon base registers we only need to clear
1622 * the first byte since that byte contains the VALID and OWNER
1623 * bits which (when set to 0) will invalidate the entire beacon.
1624 */
1625 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1626 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1627 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1628 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1629 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1630 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1631 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1632 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1633
1634 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1635 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1636 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1637 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1638 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1639 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1640 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1641 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1642 rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1643 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1644
1645 rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1646 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1647 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1648 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1649 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1650 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1651 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1652 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1653 rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1654 rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1655
1656 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1657 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1658 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1659 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1660 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1661 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1662 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1663 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1664 rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1665 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1666
1667 rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1668 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1669 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1670 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1671 rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1672 rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1673
1674 /*
1675 * We must clear the error counters.
1676 * These registers are cleared on read,
1677 * so we may pass a useless variable to store the value.
1678 */
1679 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1680 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1681 rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1682 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1683 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1684 rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1685
1686 return 0;
1687}
1688
1689static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1690{
1691 unsigned int i;
1692 u32 reg;
1693
1694 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1695 rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1696 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1697 return 0;
1698
1699 udelay(REGISTER_BUSY_DELAY);
1700 }
1701
1702 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1703 return -EACCES;
1704}
1705
1706static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1707{
1708 unsigned int i;
1709 u8 value;
1710
1711 /*
1712 * BBP was enabled after firmware was loaded,
1713 * but we need to reactivate it now.
1714 */
1715 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1716 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1717 msleep(1);
1718
1719 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1720 rt2800pci_bbp_read(rt2x00dev, 0, &value);
1721 if ((value != 0xff) && (value != 0x00))
1722 return 0;
1723 udelay(REGISTER_BUSY_DELAY);
1724 }
1725
1726 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1727 return -EACCES;
1728}
1729
1730static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1731{
1732 unsigned int i;
1733 u16 eeprom;
1734 u8 reg_id;
1735 u8 value;
1736
1737 if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1738 rt2800pci_wait_bbp_ready(rt2x00dev)))
1739 return -EACCES;
1740
1741 rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1742 rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1743 rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1744 rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1745 rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1746 rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1747 rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1748 rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1749 rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1750 rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1751 rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1752 rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1753 rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1754 rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1755
1756 if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1757 rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1758 rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1759 }
1760
1761 if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1762 rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1763
1764 if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1765 rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1766 rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1767 rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1768 }
1769
1770 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1771 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1772
1773 if (eeprom != 0xffff && eeprom != 0x0000) {
1774 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1775 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1776 rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1777 }
1778 }
1779 417
1780 return 0; 418 rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1781}
1782
1783static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1784 bool bw40, u8 rfcsr24, u8 filter_target)
1785{
1786 unsigned int i;
1787 u8 bbp;
1788 u8 rfcsr;
1789 u8 passband;
1790 u8 stopband;
1791 u8 overtuned = 0;
1792
1793 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1794
1795 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1796 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1797 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1798
1799 rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1800 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1801 rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1802
1803 /*
1804 * Set power & frequency of passband test tone
1805 */
1806 rt2800pci_bbp_write(rt2x00dev, 24, 0);
1807
1808 for (i = 0; i < 100; i++) {
1809 rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1810 msleep(1);
1811
1812 rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1813 if (passband)
1814 break;
1815 }
1816
1817 /*
1818 * Set power & frequency of stopband test tone
1819 */
1820 rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1821
1822 for (i = 0; i < 100; i++) {
1823 rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1824 msleep(1);
1825
1826 rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1827
1828 if ((passband - stopband) <= filter_target) {
1829 rfcsr24++;
1830 overtuned += ((passband - stopband) == filter_target);
1831 } else
1832 break;
1833
1834 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1835 }
1836
1837 rfcsr24 -= !!overtuned;
1838
1839 rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1840 return rfcsr24;
1841}
1842
1843static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1844{
1845 u8 rfcsr;
1846 u8 bbp;
1847
1848 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1849 !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1850 !rt2x00_rf(&rt2x00dev->chip, RF3022))
1851 return 0;
1852
1853 /*
1854 * Init RF calibration.
1855 */
1856 rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1857 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1858 rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1859 msleep(1);
1860 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1861 rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1862
1863 rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1864 rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1865 rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1866 rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1867 rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1868 rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1869 rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1870 rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1871 rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1872 rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1873 rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1874 rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1875 rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1876 rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1877 rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1878 rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1879 rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1880 rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1881 rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1882 rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1883 rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1884 rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1885 rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1886 rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1887 rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1888 rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1889 rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1890 rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1891 rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1892 rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1893
1894 /*
1895 * Set RX Filter calibration for 20MHz and 40MHz
1896 */
1897 rt2x00dev->calibration[0] =
1898 rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1899 rt2x00dev->calibration[1] =
1900 rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1901
1902 /*
1903 * Set back to initial state
1904 */
1905 rt2800pci_bbp_write(rt2x00dev, 24, 0);
1906
1907 rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1908 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1909 rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1910
1911 /*
1912 * set BBP back to BW20
1913 */
1914 rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1915 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1916 rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1917 419
1918 return 0; 420 return 0;
1919} 421}
@@ -1926,11 +428,11 @@ static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1926{ 428{
1927 u32 reg; 429 u32 reg;
1928 430
1929 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 431 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1930 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 432 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1931 (state == STATE_RADIO_RX_ON) || 433 (state == STATE_RADIO_RX_ON) ||
1932 (state == STATE_RADIO_RX_ON_LINK)); 434 (state == STATE_RADIO_RX_ON_LINK));
1933 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 435 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1934} 436}
1935 437
1936static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev, 438static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
@@ -1944,11 +446,11 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1944 * should clear the register to assure a clean state. 446 * should clear the register to assure a clean state.
1945 */ 447 */
1946 if (state == STATE_RADIO_IRQ_ON) { 448 if (state == STATE_RADIO_IRQ_ON) {
1947 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 449 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1948 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 450 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1949 } 451 }
1950 452
1951 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg); 453 rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1952 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask); 454 rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1953 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask); 455 rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1954 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask); 456 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
@@ -1967,7 +469,7 @@ static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1967 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask); 469 rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1968 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask); 470 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1969 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask); 471 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1970 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg); 472 rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
1971} 473}
1972 474
1973static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) 475static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
@@ -1976,7 +478,7 @@ static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1976 u32 reg; 478 u32 reg;
1977 479
1978 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 480 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1979 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 481 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1980 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && 482 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1981 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) 483 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1982 return 0; 484 return 0;
@@ -1998,50 +500,50 @@ static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1998 */ 500 */
1999 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) || 501 if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2000 rt2800pci_init_queues(rt2x00dev) || 502 rt2800pci_init_queues(rt2x00dev) ||
2001 rt2800pci_init_registers(rt2x00dev) || 503 rt2800_init_registers(rt2x00dev) ||
2002 rt2800pci_wait_wpdma_ready(rt2x00dev) || 504 rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2003 rt2800pci_init_bbp(rt2x00dev) || 505 rt2800_init_bbp(rt2x00dev) ||
2004 rt2800pci_init_rfcsr(rt2x00dev))) 506 rt2800_init_rfcsr(rt2x00dev)))
2005 return -EIO; 507 return -EIO;
2006 508
2007 /* 509 /*
2008 * Send signal to firmware during boot time. 510 * Send signal to firmware during boot time.
2009 */ 511 */
2010 rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0); 512 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2011 513
2012 /* 514 /*
2013 * Enable RX. 515 * Enable RX.
2014 */ 516 */
2015 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 517 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2016 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 518 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2017 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); 519 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2018 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 520 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2019 521
2020 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 522 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2021 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); 523 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2022 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); 524 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2023 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); 525 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2024 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 526 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2025 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 527 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2026 528
2027 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 529 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2028 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1); 530 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2029 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1); 531 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2030 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg); 532 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2031 533
2032 /* 534 /*
2033 * Initialize LED control 535 * Initialize LED control
2034 */ 536 */
2035 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word); 537 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2036 rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff, 538 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2037 word & 0xff, (word >> 8) & 0xff); 539 word & 0xff, (word >> 8) & 0xff);
2038 540
2039 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word); 541 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2040 rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff, 542 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2041 word & 0xff, (word >> 8) & 0xff); 543 word & 0xff, (word >> 8) & 0xff);
2042 544
2043 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word); 545 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2044 rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff, 546 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2045 word & 0xff, (word >> 8) & 0xff); 547 word & 0xff, (word >> 8) & 0xff);
2046 548
2047 return 0; 549 return 0;
@@ -2051,21 +553,21 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2051{ 553{
2052 u32 reg; 554 u32 reg;
2053 555
2054 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg); 556 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2055 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 557 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2056 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 558 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2057 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 559 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2058 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 560 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2059 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); 561 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2060 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 562 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2061 563
2062 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0); 564 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2063 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0); 565 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2064 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0); 566 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2065 567
2066 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280); 568 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2067 569
2068 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 570 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2069 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1); 571 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
2070 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1); 572 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
2071 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1); 573 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
@@ -2073,10 +575,10 @@ static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2073 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1); 575 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
2074 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1); 576 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
2075 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1); 577 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
2076 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 578 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2077 579
2078 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f); 580 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
2079 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00); 581 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
2080 582
2081 /* Wait for DMA, ignore error */ 583 /* Wait for DMA, ignore error */
2082 rt2800pci_wait_wpdma_ready(rt2x00dev); 584 rt2800pci_wait_wpdma_ready(rt2x00dev);
@@ -2090,10 +592,10 @@ static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2090 * if the device is booting and wasn't asleep it will return 592 * if the device is booting and wasn't asleep it will return
2091 * failure when attempting to wakeup. 593 * failure when attempting to wakeup.
2092 */ 594 */
2093 rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2); 595 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2094 596
2095 if (state == STATE_AWAKE) { 597 if (state == STATE_AWAKE) {
2096 rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0); 598 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2097 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP); 599 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2098 } 600 }
2099 601
@@ -2195,7 +697,7 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2195 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size); 697 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2196 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, 698 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2197 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ? 699 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2198 (skbdesc->entry->entry_idx + 1) : 0xff); 700 txdesc->key_idx : 0xff);
2199 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, 701 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2200 skb->len - txdesc->l2pad); 702 skb->len - txdesc->l2pad);
2201 rt2x00_set_field32(&word, TXWI_W1_PACKETID, 703 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
@@ -2204,8 +706,8 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2204 706
2205 /* 707 /*
2206 * Always write 0 to IV/EIV fields, hardware will insert the IV 708 * Always write 0 to IV/EIV fields, hardware will insert the IV
2207 * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0. 709 * from the IVEIV register when TXD_W3_WIV is set to 0.
2208 * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data 710 * When TXD_W3_WIV is set to 1 it will use the IV data
2209 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 711 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2210 * crypto entry in the registers should be used to encrypt the frame. 712 * crypto entry in the registers should be used to encrypt the frame.
2211 */ 713 */
@@ -2265,18 +767,18 @@ static void rt2800pci_write_beacon(struct queue_entry *entry)
2265 * Disable beaconing while we are reloading the beacon data, 767 * Disable beaconing while we are reloading the beacon data,
2266 * otherwise we might be sending out invalid data. 768 * otherwise we might be sending out invalid data.
2267 */ 769 */
2268 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 770 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2269 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); 771 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2270 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 772 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2271 773
2272 /* 774 /*
2273 * Write entire beacon with descriptor to register. 775 * Write entire beacon with descriptor to register.
2274 */ 776 */
2275 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 777 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2276 rt2x00pci_register_multiwrite(rt2x00dev, 778 rt2800_register_multiwrite(rt2x00dev,
2277 beacon_base, 779 beacon_base,
2278 skbdesc->desc, skbdesc->desc_len); 780 skbdesc->desc, skbdesc->desc_len);
2279 rt2x00pci_register_multiwrite(rt2x00dev, 781 rt2800_register_multiwrite(rt2x00dev,
2280 beacon_base + skbdesc->desc_len, 782 beacon_base + skbdesc->desc_len,
2281 entry->skb->data, entry->skb->len); 783 entry->skb->data, entry->skb->len);
2282 784
@@ -2295,12 +797,12 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2295 u32 reg; 797 u32 reg;
2296 798
2297 if (queue_idx == QID_BEACON) { 799 if (queue_idx == QID_BEACON) {
2298 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 800 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2299 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) { 801 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2300 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1); 802 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2301 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1); 803 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2302 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1); 804 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2303 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg); 805 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2304 } 806 }
2305 return; 807 return;
2306 } 808 }
@@ -2316,7 +818,7 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2316 else 818 else
2317 qidx = queue_idx; 819 qidx = queue_idx;
2318 820
2319 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx); 821 rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2320} 822}
2321 823
2322static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev, 824static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
@@ -2325,16 +827,16 @@ static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2325 u32 reg; 827 u32 reg;
2326 828
2327 if (qid == QID_BEACON) { 829 if (qid == QID_BEACON) {
2328 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0); 830 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2329 return; 831 return;
2330 } 832 }
2331 833
2332 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg); 834 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2333 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE)); 835 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2334 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK)); 836 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2335 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI)); 837 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2336 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO)); 838 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2337 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg); 839 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2338} 840}
2339 841
2340/* 842/*
@@ -2430,7 +932,7 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2430 * Set RX IDX in register to inform hardware that we have handled 932 * Set RX IDX in register to inform hardware that we have handled
2431 * this entry and it is available for reuse again. 933 * this entry and it is available for reuse again.
2432 */ 934 */
2433 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx); 935 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2434 936
2435 /* 937 /*
2436 * Remove TXWI descriptor from start of buffer. 938 * Remove TXWI descriptor from start of buffer.
@@ -2467,7 +969,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2467 old_reg = 0; 969 old_reg = 0;
2468 970
2469 while (1) { 971 while (1) {
2470 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg); 972 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2471 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID)) 973 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2472 break; 974 break;
2473 975
@@ -2551,8 +1053,8 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2551 u32 reg; 1053 u32 reg;
2552 1054
2553 /* Read status and ACK all interrupts */ 1055 /* Read status and ACK all interrupts */
2554 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg); 1056 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2555 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg); 1057 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2556 1058
2557 if (!reg) 1059 if (!reg)
2558 return IRQ_NONE; 1060 return IRQ_NONE;
@@ -2709,7 +1211,7 @@ static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2709 * Identify RF chipset. 1211 * Identify RF chipset.
2710 */ 1212 */
2711 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE); 1213 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2712 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg); 1214 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2713 rt2x00_set_chip_rf(rt2x00dev, value, reg); 1215 rt2x00_set_chip_rf(rt2x00dev, value, reg);
2714 1216
2715 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) && 1217 if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
@@ -2758,9 +1260,9 @@ static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2758 * Store led settings, for correct led behaviour. 1260 * Store led settings, for correct led behaviour.
2759 */ 1261 */
2760#ifdef CONFIG_RT2X00_LIB_LEDS 1262#ifdef CONFIG_RT2X00_LIB_LEDS
2761 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); 1263 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2762 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); 1264 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2763 rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY); 1265 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2764 1266
2765 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg); 1267 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2766#endif /* CONFIG_RT2X00_LIB_LEDS */ 1268#endif /* CONFIG_RT2X00_LIB_LEDS */
@@ -2948,10 +1450,25 @@ static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2948 return 0; 1450 return 0;
2949} 1451}
2950 1452
1453static const struct rt2800_ops rt2800pci_rt2800_ops = {
1454 .register_read = rt2x00pci_register_read,
1455 .register_write = rt2x00pci_register_write,
1456 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1457
1458 .register_multiread = rt2x00pci_register_multiread,
1459 .register_multiwrite = rt2x00pci_register_multiwrite,
1460
1461 .regbusy_read = rt2x00pci_regbusy_read,
1462};
1463
2951static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev) 1464static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2952{ 1465{
2953 int retval; 1466 int retval;
2954 1467
1468 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
1469
1470 rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
1471
2955 /* 1472 /*
2956 * Allocate eeprom data. 1473 * Allocate eeprom data.
2957 */ 1474 */
@@ -2996,161 +1513,6 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2996 return 0; 1513 return 0;
2997} 1514}
2998 1515
2999/*
3000 * IEEE80211 stack callback functions.
3001 */
3002static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
3003 u32 *iv32, u16 *iv16)
3004{
3005 struct rt2x00_dev *rt2x00dev = hw->priv;
3006 struct mac_iveiv_entry iveiv_entry;
3007 u32 offset;
3008
3009 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3010 rt2x00pci_register_multiread(rt2x00dev, offset,
3011 &iveiv_entry, sizeof(iveiv_entry));
3012
3013 memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
3014 memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
3015}
3016
3017static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3018{
3019 struct rt2x00_dev *rt2x00dev = hw->priv;
3020 u32 reg;
3021 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3022
3023 rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3024 rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3025 rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
3026
3027 rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3028 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3029 rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3030
3031 rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3032 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3033 rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3034
3035 rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3036 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3037 rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3038
3039 rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3040 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3041 rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3042
3043 rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3044 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3045 rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3046
3047 rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3048 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3049 rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3050
3051 return 0;
3052}
3053
3054static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3055 const struct ieee80211_tx_queue_params *params)
3056{
3057 struct rt2x00_dev *rt2x00dev = hw->priv;
3058 struct data_queue *queue;
3059 struct rt2x00_field32 field;
3060 int retval;
3061 u32 reg;
3062 u32 offset;
3063
3064 /*
3065 * First pass the configuration through rt2x00lib, that will
3066 * update the queue settings and validate the input. After that
3067 * we are free to update the registers based on the value
3068 * in the queue parameter.
3069 */
3070 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3071 if (retval)
3072 return retval;
3073
3074 /*
3075 * We only need to perform additional register initialization
3076 * for WMM queues/
3077 */
3078 if (queue_idx >= 4)
3079 return 0;
3080
3081 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3082
3083 /* Update WMM TXOP register */
3084 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3085 field.bit_offset = (queue_idx & 1) * 16;
3086 field.bit_mask = 0xffff << field.bit_offset;
3087
3088 rt2x00pci_register_read(rt2x00dev, offset, &reg);
3089 rt2x00_set_field32(&reg, field, queue->txop);
3090 rt2x00pci_register_write(rt2x00dev, offset, reg);
3091
3092 /* Update WMM registers */
3093 field.bit_offset = queue_idx * 4;
3094 field.bit_mask = 0xf << field.bit_offset;
3095
3096 rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3097 rt2x00_set_field32(&reg, field, queue->aifs);
3098 rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3099
3100 rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3101 rt2x00_set_field32(&reg, field, queue->cw_min);
3102 rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3103
3104 rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3105 rt2x00_set_field32(&reg, field, queue->cw_max);
3106 rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3107
3108 /* Update EDCA registers */
3109 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3110
3111 rt2x00pci_register_read(rt2x00dev, offset, &reg);
3112 rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3113 rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3114 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3115 rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3116 rt2x00pci_register_write(rt2x00dev, offset, reg);
3117
3118 return 0;
3119}
3120
3121static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3122{
3123 struct rt2x00_dev *rt2x00dev = hw->priv;
3124 u64 tsf;
3125 u32 reg;
3126
3127 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3128 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3129 rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3130 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3131
3132 return tsf;
3133}
3134
3135static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3136 .tx = rt2x00mac_tx,
3137 .start = rt2x00mac_start,
3138 .stop = rt2x00mac_stop,
3139 .add_interface = rt2x00mac_add_interface,
3140 .remove_interface = rt2x00mac_remove_interface,
3141 .config = rt2x00mac_config,
3142 .configure_filter = rt2x00mac_configure_filter,
3143 .set_key = rt2x00mac_set_key,
3144 .get_stats = rt2x00mac_get_stats,
3145 .get_tkip_seq = rt2800pci_get_tkip_seq,
3146 .set_rts_threshold = rt2800pci_set_rts_threshold,
3147 .bss_info_changed = rt2x00mac_bss_info_changed,
3148 .conf_tx = rt2800pci_conf_tx,
3149 .get_tx_stats = rt2x00mac_get_tx_stats,
3150 .get_tsf = rt2800pci_get_tsf,
3151 .rfkill_poll = rt2x00mac_rfkill_poll,
3152};
3153
3154static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = { 1516static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3155 .irq_handler = rt2800pci_interrupt, 1517 .irq_handler = rt2800pci_interrupt,
3156 .probe_hw = rt2800pci_probe_hw, 1518 .probe_hw = rt2800pci_probe_hw,
@@ -3162,23 +1524,23 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3162 .get_entry_state = rt2800pci_get_entry_state, 1524 .get_entry_state = rt2800pci_get_entry_state,
3163 .clear_entry = rt2800pci_clear_entry, 1525 .clear_entry = rt2800pci_clear_entry,
3164 .set_device_state = rt2800pci_set_device_state, 1526 .set_device_state = rt2800pci_set_device_state,
3165 .rfkill_poll = rt2800pci_rfkill_poll, 1527 .rfkill_poll = rt2800_rfkill_poll,
3166 .link_stats = rt2800pci_link_stats, 1528 .link_stats = rt2800_link_stats,
3167 .reset_tuner = rt2800pci_reset_tuner, 1529 .reset_tuner = rt2800_reset_tuner,
3168 .link_tuner = rt2800pci_link_tuner, 1530 .link_tuner = rt2800_link_tuner,
3169 .write_tx_desc = rt2800pci_write_tx_desc, 1531 .write_tx_desc = rt2800pci_write_tx_desc,
3170 .write_tx_data = rt2x00pci_write_tx_data, 1532 .write_tx_data = rt2x00pci_write_tx_data,
3171 .write_beacon = rt2800pci_write_beacon, 1533 .write_beacon = rt2800pci_write_beacon,
3172 .kick_tx_queue = rt2800pci_kick_tx_queue, 1534 .kick_tx_queue = rt2800pci_kick_tx_queue,
3173 .kill_tx_queue = rt2800pci_kill_tx_queue, 1535 .kill_tx_queue = rt2800pci_kill_tx_queue,
3174 .fill_rxdone = rt2800pci_fill_rxdone, 1536 .fill_rxdone = rt2800pci_fill_rxdone,
3175 .config_shared_key = rt2800pci_config_shared_key, 1537 .config_shared_key = rt2800_config_shared_key,
3176 .config_pairwise_key = rt2800pci_config_pairwise_key, 1538 .config_pairwise_key = rt2800_config_pairwise_key,
3177 .config_filter = rt2800pci_config_filter, 1539 .config_filter = rt2800_config_filter,
3178 .config_intf = rt2800pci_config_intf, 1540 .config_intf = rt2800_config_intf,
3179 .config_erp = rt2800pci_config_erp, 1541 .config_erp = rt2800_config_erp,
3180 .config_ant = rt2800pci_config_ant, 1542 .config_ant = rt2800_config_ant,
3181 .config = rt2800pci_config, 1543 .config = rt2800_config,
3182}; 1544};
3183 1545
3184static const struct data_queue_desc rt2800pci_queue_rx = { 1546static const struct data_queue_desc rt2800pci_queue_rx = {
@@ -3213,9 +1575,9 @@ static const struct rt2x00_ops rt2800pci_ops = {
3213 .tx = &rt2800pci_queue_tx, 1575 .tx = &rt2800pci_queue_tx,
3214 .bcn = &rt2800pci_queue_bcn, 1576 .bcn = &rt2800pci_queue_bcn,
3215 .lib = &rt2800pci_rt2x00_ops, 1577 .lib = &rt2800pci_rt2x00_ops,
3216 .hw = &rt2800pci_mac80211_ops, 1578 .hw = &rt2800_mac80211_ops,
3217#ifdef CONFIG_RT2X00_LIB_DEBUGFS 1579#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3218 .debugfs = &rt2800pci_rt2x00debug, 1580 .debugfs = &rt2800_rt2x00debug,
3219#endif /* CONFIG_RT2X00_LIB_DEBUGFS */ 1581#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3220}; 1582};
3221 1583
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 23:53:42 -0500