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path: root/drivers/net/wireless/rt2x00/rt2800pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c190
1 files changed, 1 insertions, 189 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index c60779069508..e8fe2eabebbd 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -1112,194 +1112,6 @@ static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1112 return rt2800_validate_eeprom(rt2x00dev); 1112 return rt2800_validate_eeprom(rt2x00dev);
1113} 1113}
1114 1114
1115/*
1116 * RF value list for rt2860
1117 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1118 */
1119static const struct rf_channel rf_vals[] = {
1120 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1121 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1122 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1123 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1124 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1125 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1126 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1127 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1128 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1129 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1130 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1131 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1132 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1133 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1134
1135 /* 802.11 UNI / HyperLan 2 */
1136 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1137 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1138 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1139 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1140 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1141 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1142 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1143 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1144 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1145 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1146 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1147 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1148
1149 /* 802.11 HyperLan 2 */
1150 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1151 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1152 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1153 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1154 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1155 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1156 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1157 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1158 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1159 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1160 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1161 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1162 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1163 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1164 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1165 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1166
1167 /* 802.11 UNII */
1168 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1169 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1170 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1171 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1172 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1173 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1174 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1175 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
1176 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
1177 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
1178 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
1179
1180 /* 802.11 Japan */
1181 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1182 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1183 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1184 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1185 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1186 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1187 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1188};
1189
1190static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1191{
1192 struct rt2x00_chip *chip = &rt2x00dev->chip;
1193 struct hw_mode_spec *spec = &rt2x00dev->spec;
1194 struct channel_info *info;
1195 char *tx_power1;
1196 char *tx_power2;
1197 unsigned int i;
1198 u16 eeprom;
1199
1200 /*
1201 * Initialize all hw fields.
1202 */
1203 rt2x00dev->hw->flags =
1204 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1205 IEEE80211_HW_SIGNAL_DBM |
1206 IEEE80211_HW_SUPPORTS_PS |
1207 IEEE80211_HW_PS_NULLFUNC_STACK;
1208
1209 if (rt2x00_intf_is_pci(rt2x00dev))
1210 rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
1211
1212 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1213 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1214 rt2x00_eeprom_addr(rt2x00dev,
1215 EEPROM_MAC_ADDR_0));
1216
1217 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1218
1219 /*
1220 * Initialize hw_mode information.
1221 */
1222 spec->supported_bands = SUPPORT_BAND_2GHZ;
1223 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1224
1225 if (rt2x00_rf(chip, RF2820) ||
1226 rt2x00_rf(chip, RF2720) ||
1227 (rt2x00_intf_is_pci(rt2x00dev) &&
1228 (rt2x00_rf(chip, RF3020) ||
1229 rt2x00_rf(chip, RF3021) ||
1230 rt2x00_rf(chip, RF3022) ||
1231 rt2x00_rf(chip, RF2020) ||
1232 rt2x00_rf(chip, RF3052)))) {
1233 spec->num_channels = 14;
1234 spec->channels = rf_vals;
1235 } else if (rt2x00_rf(chip, RF2850) ||
1236 rt2x00_rf(chip, RF2750)) {
1237 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1238 spec->num_channels = ARRAY_SIZE(rf_vals);
1239 spec->channels = rf_vals;
1240 }
1241
1242 /*
1243 * Initialize HT information.
1244 */
1245 spec->ht.ht_supported = true;
1246 spec->ht.cap =
1247 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1248 IEEE80211_HT_CAP_GRN_FLD |
1249 IEEE80211_HT_CAP_SGI_20 |
1250 IEEE80211_HT_CAP_SGI_40 |
1251 IEEE80211_HT_CAP_TX_STBC |
1252 IEEE80211_HT_CAP_RX_STBC |
1253 IEEE80211_HT_CAP_PSMP_SUPPORT;
1254 spec->ht.ampdu_factor = 3;
1255 spec->ht.ampdu_density = 4;
1256 spec->ht.mcs.tx_params =
1257 IEEE80211_HT_MCS_TX_DEFINED |
1258 IEEE80211_HT_MCS_TX_RX_DIFF |
1259 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
1260 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
1261
1262 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
1263 case 3:
1264 spec->ht.mcs.rx_mask[2] = 0xff;
1265 case 2:
1266 spec->ht.mcs.rx_mask[1] = 0xff;
1267 case 1:
1268 spec->ht.mcs.rx_mask[0] = 0xff;
1269 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
1270 break;
1271 }
1272
1273 /*
1274 * Create channel information array
1275 */
1276 info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
1277 if (!info)
1278 return -ENOMEM;
1279
1280 spec->channels_info = info;
1281
1282 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
1283 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
1284
1285 for (i = 0; i < 14; i++) {
1286 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
1287 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
1288 }
1289
1290 if (spec->num_channels > 14) {
1291 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
1292 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
1293
1294 for (i = 14; i < spec->num_channels; i++) {
1295 info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
1296 info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
1297 }
1298 }
1299
1300 return 0;
1301}
1302
1303static const struct rt2800_ops rt2800pci_rt2800_ops = { 1115static const struct rt2800_ops rt2800pci_rt2800_ops = {
1304 .register_read = rt2x00pci_register_read, 1116 .register_read = rt2x00pci_register_read,
1305 .register_write = rt2x00pci_register_write, 1117 .register_write = rt2x00pci_register_write,
@@ -1331,7 +1143,7 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1331 /* 1143 /*
1332 * Initialize hw specifications. 1144 * Initialize hw specifications.
1333 */ 1145 */
1334 retval = rt2800pci_probe_hw_mode(rt2x00dev); 1146 retval = rt2800_probe_hw_mode(rt2x00dev);
1335 if (retval) 1147 if (retval)
1336 return retval; 1148 return retval;
1337 1149
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 17:16:00 -0500