diff options
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800lib.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2800lib.c | 289 |
1 files changed, 135 insertions, 154 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c index 88ce656f96cd..c5738f14c4ba 100644 --- a/drivers/net/wireless/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/rt2x00/rt2800lib.c | |||
@@ -278,12 +278,9 @@ static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = { | |||
278 | [EEPROM_LNA] = 0x0026, | 278 | [EEPROM_LNA] = 0x0026, |
279 | [EEPROM_EXT_LNA2] = 0x0027, | 279 | [EEPROM_EXT_LNA2] = 0x0027, |
280 | [EEPROM_RSSI_BG] = 0x0028, | 280 | [EEPROM_RSSI_BG] = 0x0028, |
281 | [EEPROM_TXPOWER_DELTA] = 0x0028, /* Overlaps with RSSI_BG */ | ||
282 | [EEPROM_RSSI_BG2] = 0x0029, | 281 | [EEPROM_RSSI_BG2] = 0x0029, |
283 | [EEPROM_TXMIXER_GAIN_BG] = 0x0029, /* Overlaps with RSSI_BG2 */ | ||
284 | [EEPROM_RSSI_A] = 0x002a, | 282 | [EEPROM_RSSI_A] = 0x002a, |
285 | [EEPROM_RSSI_A2] = 0x002b, | 283 | [EEPROM_RSSI_A2] = 0x002b, |
286 | [EEPROM_TXMIXER_GAIN_A] = 0x002b, /* Overlaps with RSSI_A2 */ | ||
287 | [EEPROM_TXPOWER_BG1] = 0x0030, | 284 | [EEPROM_TXPOWER_BG1] = 0x0030, |
288 | [EEPROM_TXPOWER_BG2] = 0x0037, | 285 | [EEPROM_TXPOWER_BG2] = 0x0037, |
289 | [EEPROM_EXT_TXPOWER_BG3] = 0x003e, | 286 | [EEPROM_EXT_TXPOWER_BG3] = 0x003e, |
@@ -1783,7 +1780,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) | |||
1783 | rt2800_bbp_read(rt2x00dev, 3, &r3); | 1780 | rt2800_bbp_read(rt2x00dev, 3, &r3); |
1784 | 1781 | ||
1785 | if (rt2x00_rt(rt2x00dev, RT3572) && | 1782 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1786 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | 1783 | rt2x00_has_cap_bt_coexist(rt2x00dev)) |
1787 | rt2800_config_3572bt_ant(rt2x00dev); | 1784 | rt2800_config_3572bt_ant(rt2x00dev); |
1788 | 1785 | ||
1789 | /* | 1786 | /* |
@@ -1795,7 +1792,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) | |||
1795 | break; | 1792 | break; |
1796 | case 2: | 1793 | case 2: |
1797 | if (rt2x00_rt(rt2x00dev, RT3572) && | 1794 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1798 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | 1795 | rt2x00_has_cap_bt_coexist(rt2x00dev)) |
1799 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); | 1796 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); |
1800 | else | 1797 | else |
1801 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); | 1798 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); |
@@ -1825,7 +1822,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) | |||
1825 | break; | 1822 | break; |
1826 | case 2: | 1823 | case 2: |
1827 | if (rt2x00_rt(rt2x00dev, RT3572) && | 1824 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1828 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | 1825 | rt2x00_has_cap_bt_coexist(rt2x00dev)) { |
1829 | rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); | 1826 | rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); |
1830 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, | 1827 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, |
1831 | rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | 1828 | rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); |
@@ -2029,13 +2026,6 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, | |||
2029 | rt2x00dev->default_ant.tx_chain_num <= 2); | 2026 | rt2x00dev->default_ant.tx_chain_num <= 2); |
2030 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | 2027 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); |
2031 | 2028 | ||
2032 | rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr); | ||
2033 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1); | ||
2034 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | ||
2035 | msleep(1); | ||
2036 | rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); | ||
2037 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | ||
2038 | |||
2039 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); | 2029 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); |
2040 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); | 2030 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); |
2041 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | 2031 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); |
@@ -2141,7 +2131,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, | |||
2141 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); | 2131 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); |
2142 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); | 2132 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0); |
2143 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); | 2133 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0); |
2144 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | 2134 | if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { |
2145 | if (rf->channel <= 14) { | 2135 | if (rf->channel <= 14) { |
2146 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | 2136 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); |
2147 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | 2137 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); |
@@ -2674,7 +2664,7 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, | |||
2674 | if (rf->channel <= 14) { | 2664 | if (rf->channel <= 14) { |
2675 | int idx = rf->channel-1; | 2665 | int idx = rf->channel-1; |
2676 | 2666 | ||
2677 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | 2667 | if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { |
2678 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { | 2668 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) { |
2679 | /* r55/r59 value array of channel 1~14 */ | 2669 | /* r55/r59 value array of channel 1~14 */ |
2680 | static const char r55_bt_rev[] = {0x83, 0x83, | 2670 | static const char r55_bt_rev[] = {0x83, 0x83, |
@@ -3152,6 +3142,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
3152 | case RF3322: | 3142 | case RF3322: |
3153 | rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); | 3143 | rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info); |
3154 | break; | 3144 | break; |
3145 | case RF3070: | ||
3155 | case RF5360: | 3146 | case RF5360: |
3156 | case RF5370: | 3147 | case RF5370: |
3157 | case RF5372: | 3148 | case RF5372: |
@@ -3166,7 +3157,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
3166 | rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); | 3157 | rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); |
3167 | } | 3158 | } |
3168 | 3159 | ||
3169 | if (rt2x00_rf(rt2x00dev, RF3290) || | 3160 | if (rt2x00_rf(rt2x00dev, RF3070) || |
3161 | rt2x00_rf(rt2x00dev, RF3290) || | ||
3170 | rt2x00_rf(rt2x00dev, RF3322) || | 3162 | rt2x00_rf(rt2x00dev, RF3322) || |
3171 | rt2x00_rf(rt2x00dev, RF5360) || | 3163 | rt2x00_rf(rt2x00dev, RF5360) || |
3172 | rt2x00_rf(rt2x00dev, RF5370) || | 3164 | rt2x00_rf(rt2x00dev, RF5370) || |
@@ -3218,8 +3210,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
3218 | if (rf->channel <= 14) { | 3210 | if (rf->channel <= 14) { |
3219 | if (!rt2x00_rt(rt2x00dev, RT5390) && | 3211 | if (!rt2x00_rt(rt2x00dev, RT5390) && |
3220 | !rt2x00_rt(rt2x00dev, RT5392)) { | 3212 | !rt2x00_rt(rt2x00dev, RT5392)) { |
3221 | if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, | 3213 | if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { |
3222 | &rt2x00dev->cap_flags)) { | ||
3223 | rt2800_bbp_write(rt2x00dev, 82, 0x62); | 3214 | rt2800_bbp_write(rt2x00dev, 82, 0x62); |
3224 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | 3215 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
3225 | } else { | 3216 | } else { |
@@ -3244,7 +3235,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
3244 | if (rt2x00_rt(rt2x00dev, RT3593)) | 3235 | if (rt2x00_rt(rt2x00dev, RT3593)) |
3245 | rt2800_bbp_write(rt2x00dev, 83, 0x9a); | 3236 | rt2800_bbp_write(rt2x00dev, 83, 0x9a); |
3246 | 3237 | ||
3247 | if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) | 3238 | if (rt2x00_has_cap_external_lna_a(rt2x00dev)) |
3248 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | 3239 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
3249 | else | 3240 | else |
3250 | rt2800_bbp_write(rt2x00dev, 75, 0x50); | 3241 | rt2800_bbp_write(rt2x00dev, 75, 0x50); |
@@ -3280,7 +3271,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
3280 | /* Turn on primary PAs */ | 3271 | /* Turn on primary PAs */ |
3281 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, | 3272 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, |
3282 | rf->channel > 14); | 3273 | rf->channel > 14); |
3283 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | 3274 | if (rt2x00_has_cap_bt_coexist(rt2x00dev)) |
3284 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); | 3275 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); |
3285 | else | 3276 | else |
3286 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, | 3277 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, |
@@ -3311,33 +3302,50 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
3311 | 3302 | ||
3312 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); | 3303 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); |
3313 | 3304 | ||
3314 | if (rt2x00_rt(rt2x00dev, RT3572)) | 3305 | if (rt2x00_rt(rt2x00dev, RT3572)) { |
3315 | rt2800_rfcsr_write(rt2x00dev, 8, 0x80); | 3306 | rt2800_rfcsr_write(rt2x00dev, 8, 0x80); |
3316 | 3307 | ||
3308 | /* AGC init */ | ||
3309 | if (rf->channel <= 14) | ||
3310 | reg = 0x1c + (2 * rt2x00dev->lna_gain); | ||
3311 | else | ||
3312 | reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); | ||
3313 | |||
3314 | rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); | ||
3315 | } | ||
3316 | |||
3317 | if (rt2x00_rt(rt2x00dev, RT3593)) { | 3317 | if (rt2x00_rt(rt2x00dev, RT3593)) { |
3318 | if (rt2x00_is_usb(rt2x00dev)) { | 3318 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); |
3319 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); | ||
3320 | 3319 | ||
3321 | /* Band selection. GPIO #8 controls all paths */ | 3320 | /* Band selection */ |
3321 | if (rt2x00_is_usb(rt2x00dev) || | ||
3322 | rt2x00_is_pcie(rt2x00dev)) { | ||
3323 | /* GPIO #8 controls all paths */ | ||
3322 | rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); | 3324 | rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); |
3323 | if (rf->channel <= 14) | 3325 | if (rf->channel <= 14) |
3324 | rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); | 3326 | rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); |
3325 | else | 3327 | else |
3326 | rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); | 3328 | rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); |
3329 | } | ||
3327 | 3330 | ||
3331 | /* LNA PE control. */ | ||
3332 | if (rt2x00_is_usb(rt2x00dev)) { | ||
3333 | /* GPIO #4 controls PE0 and PE1, | ||
3334 | * GPIO #7 controls PE2 | ||
3335 | */ | ||
3328 | rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); | 3336 | rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); |
3329 | rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); | 3337 | rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); |
3330 | 3338 | ||
3331 | /* LNA PE control. | ||
3332 | * GPIO #4 controls PE0 and PE1, | ||
3333 | * GPIO #7 controls PE2 | ||
3334 | */ | ||
3335 | rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); | 3339 | rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); |
3336 | rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); | 3340 | rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); |
3337 | 3341 | } else if (rt2x00_is_pcie(rt2x00dev)) { | |
3338 | rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); | 3342 | /* GPIO #4 controls PE0, PE1 and PE2 */ |
3343 | rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); | ||
3344 | rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); | ||
3339 | } | 3345 | } |
3340 | 3346 | ||
3347 | rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); | ||
3348 | |||
3341 | /* AGC init */ | 3349 | /* AGC init */ |
3342 | if (rf->channel <= 14) | 3350 | if (rf->channel <= 14) |
3343 | reg = 0x1c + 2 * rt2x00dev->lna_gain; | 3351 | reg = 0x1c + 2 * rt2x00dev->lna_gain; |
@@ -3565,7 +3573,7 @@ static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev, | |||
3565 | { | 3573 | { |
3566 | int delta; | 3574 | int delta; |
3567 | 3575 | ||
3568 | if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) | 3576 | if (rt2x00_has_cap_power_limit(rt2x00dev)) |
3569 | return 0; | 3577 | return 0; |
3570 | 3578 | ||
3571 | /* | 3579 | /* |
@@ -3594,7 +3602,7 @@ static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b, | |||
3594 | if (rt2x00_rt(rt2x00dev, RT3593)) | 3602 | if (rt2x00_rt(rt2x00dev, RT3593)) |
3595 | return min_t(u8, txpower, 0xc); | 3603 | return min_t(u8, txpower, 0xc); |
3596 | 3604 | ||
3597 | if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) { | 3605 | if (rt2x00_has_cap_power_limit(rt2x00dev)) { |
3598 | /* | 3606 | /* |
3599 | * Check if eirp txpower exceed txpower_limit. | 3607 | * Check if eirp txpower exceed txpower_limit. |
3600 | * We use OFDM 6M as criterion and its eirp txpower | 3608 | * We use OFDM 6M as criterion and its eirp txpower |
@@ -4264,6 +4272,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) | |||
4264 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); | 4272 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); |
4265 | break; | 4273 | break; |
4266 | case RF3053: | 4274 | case RF3053: |
4275 | case RF3070: | ||
4267 | case RF3290: | 4276 | case RF3290: |
4268 | case RF5360: | 4277 | case RF5360: |
4269 | case RF5370: | 4278 | case RF5370: |
@@ -4405,6 +4414,7 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) | |||
4405 | rt2x00_rt(rt2x00dev, RT3290) || | 4414 | rt2x00_rt(rt2x00dev, RT3290) || |
4406 | rt2x00_rt(rt2x00dev, RT3390) || | 4415 | rt2x00_rt(rt2x00dev, RT3390) || |
4407 | rt2x00_rt(rt2x00dev, RT3572) || | 4416 | rt2x00_rt(rt2x00dev, RT3572) || |
4417 | rt2x00_rt(rt2x00dev, RT3593) || | ||
4408 | rt2x00_rt(rt2x00dev, RT5390) || | 4418 | rt2x00_rt(rt2x00dev, RT5390) || |
4409 | rt2x00_rt(rt2x00dev, RT5392) || | 4419 | rt2x00_rt(rt2x00dev, RT5392) || |
4410 | rt2x00_rt(rt2x00dev, RT5592)) | 4420 | rt2x00_rt(rt2x00dev, RT5592)) |
@@ -4412,8 +4422,8 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) | |||
4412 | else | 4422 | else |
4413 | vgc = 0x2e + rt2x00dev->lna_gain; | 4423 | vgc = 0x2e + rt2x00dev->lna_gain; |
4414 | } else { /* 5GHZ band */ | 4424 | } else { /* 5GHZ band */ |
4415 | if (rt2x00_rt(rt2x00dev, RT3572)) | 4425 | if (rt2x00_rt(rt2x00dev, RT3593)) |
4416 | vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3; | 4426 | vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3; |
4417 | else if (rt2x00_rt(rt2x00dev, RT5592)) | 4427 | else if (rt2x00_rt(rt2x00dev, RT5592)) |
4418 | vgc = 0x24 + (2 * rt2x00dev->lna_gain); | 4428 | vgc = 0x24 + (2 * rt2x00dev->lna_gain); |
4419 | else { | 4429 | else { |
@@ -4431,11 +4441,17 @@ static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev, | |||
4431 | struct link_qual *qual, u8 vgc_level) | 4441 | struct link_qual *qual, u8 vgc_level) |
4432 | { | 4442 | { |
4433 | if (qual->vgc_level != vgc_level) { | 4443 | if (qual->vgc_level != vgc_level) { |
4434 | if (rt2x00_rt(rt2x00dev, RT5592)) { | 4444 | if (rt2x00_rt(rt2x00dev, RT3572) || |
4445 | rt2x00_rt(rt2x00dev, RT3593)) { | ||
4446 | rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, | ||
4447 | vgc_level); | ||
4448 | } else if (rt2x00_rt(rt2x00dev, RT5592)) { | ||
4435 | rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); | 4449 | rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a); |
4436 | rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); | 4450 | rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level); |
4437 | } else | 4451 | } else { |
4438 | rt2800_bbp_write(rt2x00dev, 66, vgc_level); | 4452 | rt2800_bbp_write(rt2x00dev, 66, vgc_level); |
4453 | } | ||
4454 | |||
4439 | qual->vgc_level = vgc_level; | 4455 | qual->vgc_level = vgc_level; |
4440 | qual->vgc_level_reg = vgc_level; | 4456 | qual->vgc_level_reg = vgc_level; |
4441 | } | 4457 | } |
@@ -4454,17 +4470,35 @@ void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, | |||
4454 | 4470 | ||
4455 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) | 4471 | if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) |
4456 | return; | 4472 | return; |
4457 | /* | 4473 | |
4458 | * When RSSI is better then -80 increase VGC level with 0x10, except | 4474 | /* When RSSI is better than a certain threshold, increase VGC |
4459 | * for rt5592 chip. | 4475 | * with a chip specific value in order to improve the balance |
4476 | * between sensibility and noise isolation. | ||
4460 | */ | 4477 | */ |
4461 | 4478 | ||
4462 | vgc = rt2800_get_default_vgc(rt2x00dev); | 4479 | vgc = rt2800_get_default_vgc(rt2x00dev); |
4463 | 4480 | ||
4464 | if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65) | 4481 | switch (rt2x00dev->chip.rt) { |
4465 | vgc += 0x20; | 4482 | case RT3572: |
4466 | else if (qual->rssi > -80) | 4483 | case RT3593: |
4467 | vgc += 0x10; | 4484 | if (qual->rssi > -65) { |
4485 | if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) | ||
4486 | vgc += 0x20; | ||
4487 | else | ||
4488 | vgc += 0x10; | ||
4489 | } | ||
4490 | break; | ||
4491 | |||
4492 | case RT5592: | ||
4493 | if (qual->rssi > -65) | ||
4494 | vgc += 0x20; | ||
4495 | break; | ||
4496 | |||
4497 | default: | ||
4498 | if (qual->rssi > -80) | ||
4499 | vgc += 0x10; | ||
4500 | break; | ||
4501 | } | ||
4468 | 4502 | ||
4469 | rt2800_set_vgc(rt2x00dev, qual, vgc); | 4503 | rt2800_set_vgc(rt2x00dev, qual, vgc); |
4470 | } | 4504 | } |
@@ -5489,7 +5523,7 @@ static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) | |||
5489 | ant = (div_mode == 3) ? 1 : 0; | 5523 | ant = (div_mode == 3) ? 1 : 0; |
5490 | 5524 | ||
5491 | /* check if this is a Bluetooth combo card */ | 5525 | /* check if this is a Bluetooth combo card */ |
5492 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | 5526 | if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { |
5493 | u32 reg; | 5527 | u32 reg; |
5494 | 5528 | ||
5495 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); | 5529 | rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); |
@@ -5798,7 +5832,7 @@ static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev) | |||
5798 | rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || | 5832 | rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || |
5799 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || | 5833 | rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) || |
5800 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { | 5834 | rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) { |
5801 | if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) | 5835 | if (!rt2x00_has_cap_external_lna_bg(rt2x00dev)) |
5802 | rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); | 5836 | rt2x00_set_field8(&rfcsr, RFCSR17_R, 1); |
5803 | } | 5837 | } |
5804 | 5838 | ||
@@ -5985,7 +6019,7 @@ static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) | |||
5985 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | 6019 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); |
5986 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | 6020 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); |
5987 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | 6021 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); |
5988 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | 6022 | rt2800_rfcsr_write(rt2x00dev, 25, 0x03); |
5989 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); | 6023 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); |
5990 | 6024 | ||
5991 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { | 6025 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { |
@@ -6441,7 +6475,7 @@ static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) | |||
6441 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | 6475 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); |
6442 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | 6476 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); |
6443 | 6477 | ||
6444 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | 6478 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); |
6445 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | 6479 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); |
6446 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | 6480 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); |
6447 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | 6481 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); |
@@ -6479,7 +6513,7 @@ static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) | |||
6479 | rt2800_rfcsr_write(rt2x00dev, 56, 0x22); | 6513 | rt2800_rfcsr_write(rt2x00dev, 56, 0x22); |
6480 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | 6514 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); |
6481 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | 6515 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); |
6482 | rt2800_rfcsr_write(rt2x00dev, 59, 0x63); | 6516 | rt2800_rfcsr_write(rt2x00dev, 59, 0x8f); |
6483 | 6517 | ||
6484 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | 6518 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); |
6485 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | 6519 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) |
@@ -6499,7 +6533,6 @@ static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) | |||
6499 | rt2800_rf_init_calibration(rt2x00dev, 2); | 6533 | rt2800_rf_init_calibration(rt2x00dev, 2); |
6500 | 6534 | ||
6501 | rt2800_rfcsr_write(rt2x00dev, 1, 0x17); | 6535 | rt2800_rfcsr_write(rt2x00dev, 1, 0x17); |
6502 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | ||
6503 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | 6536 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); |
6504 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | 6537 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); |
6505 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | 6538 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); |
@@ -6653,17 +6686,20 @@ int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) | |||
6653 | u16 word; | 6686 | u16 word; |
6654 | 6687 | ||
6655 | /* | 6688 | /* |
6656 | * Initialize all registers. | 6689 | * Initialize MAC registers. |
6657 | */ | 6690 | */ |
6658 | if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || | 6691 | if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || |
6659 | rt2800_init_registers(rt2x00dev))) | 6692 | rt2800_init_registers(rt2x00dev))) |
6660 | return -EIO; | 6693 | return -EIO; |
6661 | 6694 | ||
6695 | /* | ||
6696 | * Wait BBP/RF to wake up. | ||
6697 | */ | ||
6662 | if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) | 6698 | if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev))) |
6663 | return -EIO; | 6699 | return -EIO; |
6664 | 6700 | ||
6665 | /* | 6701 | /* |
6666 | * Send signal to firmware during boot time. | 6702 | * Send signal during boot time to initialize firmware. |
6667 | */ | 6703 | */ |
6668 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); | 6704 | rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); |
6669 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); | 6705 | rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); |
@@ -6672,9 +6708,15 @@ int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) | |||
6672 | rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); | 6708 | rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); |
6673 | msleep(1); | 6709 | msleep(1); |
6674 | 6710 | ||
6711 | /* | ||
6712 | * Make sure BBP is up and running. | ||
6713 | */ | ||
6675 | if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) | 6714 | if (unlikely(rt2800_wait_bbp_ready(rt2x00dev))) |
6676 | return -EIO; | 6715 | return -EIO; |
6677 | 6716 | ||
6717 | /* | ||
6718 | * Initialize BBP/RF registers. | ||
6719 | */ | ||
6678 | rt2800_init_bbp(rt2x00dev); | 6720 | rt2800_init_bbp(rt2x00dev); |
6679 | rt2800_init_rfcsr(rt2x00dev); | 6721 | rt2800_init_rfcsr(rt2x00dev); |
6680 | 6722 | ||
@@ -7021,6 +7063,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) | |||
7021 | case RF3022: | 7063 | case RF3022: |
7022 | case RF3052: | 7064 | case RF3052: |
7023 | case RF3053: | 7065 | case RF3053: |
7066 | case RF3070: | ||
7024 | case RF3290: | 7067 | case RF3290: |
7025 | case RF3320: | 7068 | case RF3320: |
7026 | case RF3322: | 7069 | case RF3322: |
@@ -7203,7 +7246,7 @@ static const struct rf_channel rf_vals[] = { | |||
7203 | 7246 | ||
7204 | /* | 7247 | /* |
7205 | * RF value list for rt3xxx | 7248 | * RF value list for rt3xxx |
7206 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052) | 7249 | * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053) |
7207 | */ | 7250 | */ |
7208 | static const struct rf_channel rf_vals_3x[] = { | 7251 | static const struct rf_channel rf_vals_3x[] = { |
7209 | {1, 241, 2, 2 }, | 7252 | {1, 241, 2, 2 }, |
@@ -7399,72 +7442,6 @@ static const struct rf_channel rf_vals_5592_xtal40[] = { | |||
7399 | {196, 83, 0, 12, 1}, | 7442 | {196, 83, 0, 12, 1}, |
7400 | }; | 7443 | }; |
7401 | 7444 | ||
7402 | static const struct rf_channel rf_vals_3053[] = { | ||
7403 | /* Channel, N, R, K */ | ||
7404 | {1, 241, 2, 2}, | ||
7405 | {2, 241, 2, 7}, | ||
7406 | {3, 242, 2, 2}, | ||
7407 | {4, 242, 2, 7}, | ||
7408 | {5, 243, 2, 2}, | ||
7409 | {6, 243, 2, 7}, | ||
7410 | {7, 244, 2, 2}, | ||
7411 | {8, 244, 2, 7}, | ||
7412 | {9, 245, 2, 2}, | ||
7413 | {10, 245, 2, 7}, | ||
7414 | {11, 246, 2, 2}, | ||
7415 | {12, 246, 2, 7}, | ||
7416 | {13, 247, 2, 2}, | ||
7417 | {14, 248, 2, 4}, | ||
7418 | |||
7419 | {36, 0x56, 0, 4}, | ||
7420 | {38, 0x56, 0, 6}, | ||
7421 | {40, 0x56, 0, 8}, | ||
7422 | {44, 0x57, 0, 0}, | ||
7423 | {46, 0x57, 0, 2}, | ||
7424 | {48, 0x57, 0, 4}, | ||
7425 | {52, 0x57, 0, 8}, | ||
7426 | {54, 0x57, 0, 10}, | ||
7427 | {56, 0x58, 0, 0}, | ||
7428 | {60, 0x58, 0, 4}, | ||
7429 | {62, 0x58, 0, 6}, | ||
7430 | {64, 0x58, 0, 8}, | ||
7431 | |||
7432 | {100, 0x5B, 0, 8}, | ||
7433 | {102, 0x5B, 0, 10}, | ||
7434 | {104, 0x5C, 0, 0}, | ||
7435 | {108, 0x5C, 0, 4}, | ||
7436 | {110, 0x5C, 0, 6}, | ||
7437 | {112, 0x5C, 0, 8}, | ||
7438 | |||
7439 | /* NOTE: Channel 114 has been removed intentionally. | ||
7440 | * The EEPROM contains no TX power values for that, | ||
7441 | * and it is disabled in the vendor driver as well. | ||
7442 | */ | ||
7443 | |||
7444 | {116, 0x5D, 0, 0}, | ||
7445 | {118, 0x5D, 0, 2}, | ||
7446 | {120, 0x5D, 0, 4}, | ||
7447 | {124, 0x5D, 0, 8}, | ||
7448 | {126, 0x5D, 0, 10}, | ||
7449 | {128, 0x5E, 0, 0}, | ||
7450 | {132, 0x5E, 0, 4}, | ||
7451 | {134, 0x5E, 0, 6}, | ||
7452 | {136, 0x5E, 0, 8}, | ||
7453 | {140, 0x5F, 0, 0}, | ||
7454 | |||
7455 | {149, 0x5F, 0, 9}, | ||
7456 | {151, 0x5F, 0, 11}, | ||
7457 | {153, 0x60, 0, 1}, | ||
7458 | {157, 0x60, 0, 5}, | ||
7459 | {159, 0x60, 0, 7}, | ||
7460 | {161, 0x60, 0, 9}, | ||
7461 | {165, 0x61, 0, 1}, | ||
7462 | {167, 0x61, 0, 3}, | ||
7463 | {169, 0x61, 0, 5}, | ||
7464 | {171, 0x61, 0, 7}, | ||
7465 | {173, 0x61, 0, 9}, | ||
7466 | }; | ||
7467 | |||
7468 | static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | 7445 | static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) |
7469 | { | 7446 | { |
7470 | struct hw_mode_spec *spec = &rt2x00dev->spec; | 7447 | struct hw_mode_spec *spec = &rt2x00dev->spec; |
@@ -7473,7 +7450,6 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |||
7473 | char *default_power2; | 7450 | char *default_power2; |
7474 | char *default_power3; | 7451 | char *default_power3; |
7475 | unsigned int i; | 7452 | unsigned int i; |
7476 | u16 eeprom; | ||
7477 | u32 reg; | 7453 | u32 reg; |
7478 | 7454 | ||
7479 | /* | 7455 | /* |
@@ -7522,48 +7498,48 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |||
7522 | rt2x00dev->hw->max_report_rates = 7; | 7498 | rt2x00dev->hw->max_report_rates = 7; |
7523 | rt2x00dev->hw->max_rate_tries = 1; | 7499 | rt2x00dev->hw->max_rate_tries = 1; |
7524 | 7500 | ||
7525 | rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); | ||
7526 | |||
7527 | /* | 7501 | /* |
7528 | * Initialize hw_mode information. | 7502 | * Initialize hw_mode information. |
7529 | */ | 7503 | */ |
7530 | spec->supported_bands = SUPPORT_BAND_2GHZ; | ||
7531 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; | 7504 | spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; |
7532 | 7505 | ||
7533 | if (rt2x00_rf(rt2x00dev, RF2820) || | 7506 | switch (rt2x00dev->chip.rf) { |
7534 | rt2x00_rf(rt2x00dev, RF2720)) { | 7507 | case RF2720: |
7508 | case RF2820: | ||
7535 | spec->num_channels = 14; | 7509 | spec->num_channels = 14; |
7536 | spec->channels = rf_vals; | 7510 | spec->channels = rf_vals; |
7537 | } else if (rt2x00_rf(rt2x00dev, RF2850) || | 7511 | break; |
7538 | rt2x00_rf(rt2x00dev, RF2750)) { | 7512 | |
7539 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | 7513 | case RF2750: |
7514 | case RF2850: | ||
7540 | spec->num_channels = ARRAY_SIZE(rf_vals); | 7515 | spec->num_channels = ARRAY_SIZE(rf_vals); |
7541 | spec->channels = rf_vals; | 7516 | spec->channels = rf_vals; |
7542 | } else if (rt2x00_rf(rt2x00dev, RF3020) || | 7517 | break; |
7543 | rt2x00_rf(rt2x00dev, RF2020) || | 7518 | |
7544 | rt2x00_rf(rt2x00dev, RF3021) || | 7519 | case RF2020: |
7545 | rt2x00_rf(rt2x00dev, RF3022) || | 7520 | case RF3020: |
7546 | rt2x00_rf(rt2x00dev, RF3290) || | 7521 | case RF3021: |
7547 | rt2x00_rf(rt2x00dev, RF3320) || | 7522 | case RF3022: |
7548 | rt2x00_rf(rt2x00dev, RF3322) || | 7523 | case RF3070: |
7549 | rt2x00_rf(rt2x00dev, RF5360) || | 7524 | case RF3290: |
7550 | rt2x00_rf(rt2x00dev, RF5370) || | 7525 | case RF3320: |
7551 | rt2x00_rf(rt2x00dev, RF5372) || | 7526 | case RF3322: |
7552 | rt2x00_rf(rt2x00dev, RF5390) || | 7527 | case RF5360: |
7553 | rt2x00_rf(rt2x00dev, RF5392)) { | 7528 | case RF5370: |
7529 | case RF5372: | ||
7530 | case RF5390: | ||
7531 | case RF5392: | ||
7554 | spec->num_channels = 14; | 7532 | spec->num_channels = 14; |
7555 | spec->channels = rf_vals_3x; | 7533 | spec->channels = rf_vals_3x; |
7556 | } else if (rt2x00_rf(rt2x00dev, RF3052)) { | 7534 | break; |
7557 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | 7535 | |
7536 | case RF3052: | ||
7537 | case RF3053: | ||
7558 | spec->num_channels = ARRAY_SIZE(rf_vals_3x); | 7538 | spec->num_channels = ARRAY_SIZE(rf_vals_3x); |
7559 | spec->channels = rf_vals_3x; | 7539 | spec->channels = rf_vals_3x; |
7560 | } else if (rt2x00_rf(rt2x00dev, RF3053)) { | 7540 | break; |
7561 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | ||
7562 | spec->num_channels = ARRAY_SIZE(rf_vals_3053); | ||
7563 | spec->channels = rf_vals_3053; | ||
7564 | } else if (rt2x00_rf(rt2x00dev, RF5592)) { | ||
7565 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | ||
7566 | 7541 | ||
7542 | case RF5592: | ||
7567 | rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); | 7543 | rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); |
7568 | if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { | 7544 | if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { |
7569 | spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); | 7545 | spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); |
@@ -7572,11 +7548,16 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |||
7572 | spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); | 7548 | spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20); |
7573 | spec->channels = rf_vals_5592_xtal20; | 7549 | spec->channels = rf_vals_5592_xtal20; |
7574 | } | 7550 | } |
7551 | break; | ||
7575 | } | 7552 | } |
7576 | 7553 | ||
7577 | if (WARN_ON_ONCE(!spec->channels)) | 7554 | if (WARN_ON_ONCE(!spec->channels)) |
7578 | return -ENODEV; | 7555 | return -ENODEV; |
7579 | 7556 | ||
7557 | spec->supported_bands = SUPPORT_BAND_2GHZ; | ||
7558 | if (spec->num_channels > 14) | ||
7559 | spec->supported_bands |= SUPPORT_BAND_5GHZ; | ||
7560 | |||
7580 | /* | 7561 | /* |
7581 | * Initialize HT information. | 7562 | * Initialize HT information. |
7582 | */ | 7563 | */ |
@@ -7591,22 +7572,21 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |||
7591 | IEEE80211_HT_CAP_SGI_20 | | 7572 | IEEE80211_HT_CAP_SGI_20 | |
7592 | IEEE80211_HT_CAP_SGI_40; | 7573 | IEEE80211_HT_CAP_SGI_40; |
7593 | 7574 | ||
7594 | if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2) | 7575 | if (rt2x00dev->default_ant.tx_chain_num >= 2) |
7595 | spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; | 7576 | spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC; |
7596 | 7577 | ||
7597 | spec->ht.cap |= | 7578 | spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num << |
7598 | rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) << | 7579 | IEEE80211_HT_CAP_RX_STBC_SHIFT; |
7599 | IEEE80211_HT_CAP_RX_STBC_SHIFT; | ||
7600 | 7580 | ||
7601 | spec->ht.ampdu_factor = 3; | 7581 | spec->ht.ampdu_factor = 3; |
7602 | spec->ht.ampdu_density = 4; | 7582 | spec->ht.ampdu_density = 4; |
7603 | spec->ht.mcs.tx_params = | 7583 | spec->ht.mcs.tx_params = |
7604 | IEEE80211_HT_MCS_TX_DEFINED | | 7584 | IEEE80211_HT_MCS_TX_DEFINED | |
7605 | IEEE80211_HT_MCS_TX_RX_DIFF | | 7585 | IEEE80211_HT_MCS_TX_RX_DIFF | |
7606 | ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) << | 7586 | ((rt2x00dev->default_ant.tx_chain_num - 1) << |
7607 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | 7587 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); |
7608 | 7588 | ||
7609 | switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) { | 7589 | switch (rt2x00dev->default_ant.rx_chain_num) { |
7610 | case 3: | 7590 | case 3: |
7611 | spec->ht.mcs.rx_mask[2] = 0xff; | 7591 | spec->ht.mcs.rx_mask[2] = 0xff; |
7612 | case 2: | 7592 | case 2: |
@@ -7671,6 +7651,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |||
7671 | case RF3320: | 7651 | case RF3320: |
7672 | case RF3052: | 7652 | case RF3052: |
7673 | case RF3053: | 7653 | case RF3053: |
7654 | case RF3070: | ||
7674 | case RF3290: | 7655 | case RF3290: |
7675 | case RF5360: | 7656 | case RF5360: |
7676 | case RF5370: | 7657 | case RF5370: |