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path: root/drivers/net/wireless/rt2x00/rt2800lib.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800lib.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c467
1 files changed, 337 insertions, 130 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index c015ce9fdd09..2648f315a934 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -360,11 +360,6 @@ static int rt2800_blink_set(struct led_classdev *led_cdev,
360 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg); 360 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
361 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on); 361 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
362 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off); 362 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
363 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
364 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
365 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
366 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
367 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
368 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 363 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
369 364
370 return 0; 365 return 0;
@@ -610,10 +605,6 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
610{ 605{
611 u32 reg; 606 u32 reg;
612 607
613 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
614 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
615 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
616
617 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 608 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
618 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 609 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
619 !!erp->short_preamble); 610 !!erp->short_preamble);
@@ -632,15 +623,12 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
632 623
633 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); 624 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
634 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); 625 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
635 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
636 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 626 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
637 627
638 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); 628 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
639 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs); 629 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
640 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs); 630 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
641 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
642 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs); 631 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
643 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
644 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 632 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
645 633
646 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 634 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
@@ -718,10 +706,10 @@ static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
718 rt2x00dev->lna_gain = lna_gain; 706 rt2x00dev->lna_gain = lna_gain;
719} 707}
720 708
721static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev, 709static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
722 struct ieee80211_conf *conf, 710 struct ieee80211_conf *conf,
723 struct rf_channel *rf, 711 struct rf_channel *rf,
724 struct channel_info *info) 712 struct channel_info *info)
725{ 713{
726 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 714 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
727 715
@@ -787,10 +775,10 @@ static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
787 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 775 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
788} 776}
789 777
790static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev, 778static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
791 struct ieee80211_conf *conf, 779 struct ieee80211_conf *conf,
792 struct rf_channel *rf, 780 struct rf_channel *rf,
793 struct channel_info *info) 781 struct channel_info *info)
794{ 782{
795 u8 rfcsr; 783 u8 rfcsr;
796 784
@@ -798,7 +786,7 @@ static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
798 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 786 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
799 787
800 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 788 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
801 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2); 789 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
802 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 790 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
803 791
804 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 792 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
@@ -827,15 +815,13 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
827 unsigned int tx_pin; 815 unsigned int tx_pin;
828 u8 bbp; 816 u8 bbp;
829 817
830 if ((rt2x00_rt(rt2x00dev, RT3070) || 818 if (rt2x00_rf(rt2x00dev, RF2020) ||
831 rt2x00_rt(rt2x00dev, RT3090)) && 819 rt2x00_rf(rt2x00dev, RF3020) ||
832 (rt2x00_rf(rt2x00dev, RF2020) || 820 rt2x00_rf(rt2x00dev, RF3021) ||
833 rt2x00_rf(rt2x00dev, RF3020) || 821 rt2x00_rf(rt2x00dev, RF3022))
834 rt2x00_rf(rt2x00dev, RF3021) || 822 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
835 rt2x00_rf(rt2x00dev, RF3022)))
836 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
837 else 823 else
838 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info); 824 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
839 825
840 /* 826 /*
841 * Change BBP settings 827 * Change BBP settings
@@ -899,8 +885,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
899 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf)); 885 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
900 rt2800_bbp_write(rt2x00dev, 3, bbp); 886 rt2800_bbp_write(rt2x00dev, 3, bbp);
901 887
902 if (rt2x00_rt(rt2x00dev, RT2860) && 888 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
903 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
904 if (conf_is_ht40(conf)) { 889 if (conf_is_ht40(conf)) {
905 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 890 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
906 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 891 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
@@ -988,10 +973,6 @@ static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
988 libconf->conf->short_frame_max_tx_count); 973 libconf->conf->short_frame_max_tx_count);
989 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 974 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
990 libconf->conf->long_frame_max_tx_count); 975 libconf->conf->long_frame_max_tx_count);
991 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
992 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
993 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
994 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
995 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 976 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
996} 977}
997 978
@@ -1015,13 +996,13 @@ static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1015 996
1016 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 997 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1017 } else { 998 } else {
1018 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1019
1020 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); 999 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1021 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 1000 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1022 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 1001 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1023 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0); 1002 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1024 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 1003 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1004
1005 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1025 } 1006 }
1026} 1007}
1027 1008
@@ -1062,9 +1043,10 @@ EXPORT_SYMBOL_GPL(rt2800_link_stats);
1062static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 1043static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1063{ 1044{
1064 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 1045 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1065 if (rt2x00_is_usb(rt2x00dev) && 1046 if (rt2x00_rt(rt2x00dev, RT3070) ||
1066 rt2x00_rt(rt2x00dev, RT3070) && 1047 rt2x00_rt(rt2x00dev, RT3071) ||
1067 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) 1048 rt2x00_rt(rt2x00dev, RT3090) ||
1049 rt2x00_rt(rt2x00dev, RT3390))
1068 return 0x1c + (2 * rt2x00dev->lna_gain); 1050 return 0x1c + (2 * rt2x00dev->lna_gain);
1069 else 1051 else
1070 return 0x2e + rt2x00dev->lna_gain; 1052 return 0x2e + rt2x00dev->lna_gain;
@@ -1095,8 +1077,7 @@ EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1095void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 1077void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1096 const u32 count) 1078 const u32 count)
1097{ 1079{
1098 if (rt2x00_rt(rt2x00dev, RT2860) && 1080 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1099 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION))
1100 return; 1081 return;
1101 1082
1102 /* 1083 /*
@@ -1114,8 +1095,17 @@ EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1114int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 1095int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1115{ 1096{
1116 u32 reg; 1097 u32 reg;
1098 u16 eeprom;
1117 unsigned int i; 1099 unsigned int i;
1118 1100
1101 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1102 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1103 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1104 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1105 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1106 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1107 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1108
1119 if (rt2x00_is_usb(rt2x00dev)) { 1109 if (rt2x00_is_usb(rt2x00dev)) {
1120 /* 1110 /*
1121 * Wait until BBP and RF are ready. 1111 * Wait until BBP and RF are ready.
@@ -1135,8 +1125,25 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1135 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 1125 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1136 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 1126 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1137 reg & ~0x00002000); 1127 reg & ~0x00002000);
1138 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) 1128 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1129 /*
1130 * Reset DMA indexes
1131 */
1132 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1133 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1134 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1135 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1136 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1137 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1138 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1139 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1140 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1141
1142 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1143 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1144
1139 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1145 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1146 }
1140 1147
1141 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 1148 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1142 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 1149 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
@@ -1181,12 +1188,42 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1181 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 1188 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1182 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1189 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1183 1190
1184 if (rt2x00_is_usb(rt2x00dev) && 1191 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1185 rt2x00_rt(rt2x00dev, RT3070) && 1192
1186 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) { 1193 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1194 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1195 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1196 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1197
1198 if (rt2x00_rt(rt2x00dev, RT3071) ||
1199 rt2x00_rt(rt2x00dev, RT3090) ||
1200 rt2x00_rt(rt2x00dev, RT3390)) {
1187 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 1201 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1188 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 1202 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1189 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 1203 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1204 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1205 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1206 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1207 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1208 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1209 0x0000002c);
1210 else
1211 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1212 0x0000000f);
1213 } else {
1214 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1215 }
1216 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1217 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1218 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1219
1220 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1221 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1222 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1223 } else {
1224 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1225 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1226 }
1190 } else { 1227 } else {
1191 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 1228 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1192 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 1229 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -1205,19 +1242,15 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1205 1242
1206 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg); 1243 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1207 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 1244 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1245 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1208 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 1246 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1209 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 1247 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1210 1248
1211 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg); 1249 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1212 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 1250 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1213 if ((rt2x00_rt(rt2x00dev, RT2872) && 1251 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1214 (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION)) ||
1215 rt2x00_rt(rt2x00dev, RT2880) ||
1216 rt2x00_rt(rt2x00dev, RT2883) || 1252 rt2x00_rt(rt2x00dev, RT2883) ||
1217 rt2x00_rt(rt2x00dev, RT2890) || 1253 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1218 rt2x00_rt(rt2x00dev, RT3052) ||
1219 (rt2x00_rt(rt2x00dev, RT3070) &&
1220 (rt2x00_rev(rt2x00dev) < RT3070_VERSION)))
1221 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2); 1254 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1222 else 1255 else
1223 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1); 1256 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
@@ -1225,38 +1258,61 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1225 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0); 1258 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1226 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1259 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1227 1260
1261 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1262 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1263 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1264 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1265 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1266 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1267 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1268 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1269 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1270
1228 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 1271 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1229 1272
1273 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1274 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1275 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1276 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1277 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1278 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1279 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1280 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1281
1230 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 1282 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1231 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1); 1283 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1284 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1232 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0); 1285 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1233 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0); 1286 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1287 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1234 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 1288 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1235 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 1289 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1236 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1290 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1237 1291
1238 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 1292 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1239 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8); 1293 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1240 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0); 1294 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1241 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1); 1295 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1242 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1296 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1243 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1297 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1244 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1298 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1245 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1299 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1246 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1300 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1247 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1301 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1302 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1248 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 1303 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1249 1304
1250 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 1305 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1251 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8); 1306 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1252 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0); 1307 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1253 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1); 1308 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1254 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1309 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1255 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1310 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1256 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1311 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1257 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1312 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1258 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1313 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1259 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1314 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1315 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1260 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1316 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1261 1317
1262 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 1318 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
@@ -1269,11 +1325,13 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1269 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1325 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1270 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1326 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1271 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1327 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1328 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1272 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1329 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1273 1330
1274 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 1331 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1275 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 1332 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1276 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0); 1333 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1334 !rt2x00_is_usb(rt2x00dev));
1277 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1); 1335 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1278 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1336 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1279 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1337 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
@@ -1281,6 +1339,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1281 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1339 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1282 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1340 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1283 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1341 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1342 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1284 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1343 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1285 1344
1286 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 1345 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
@@ -1293,6 +1352,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1293 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1352 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1294 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1353 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1295 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1354 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1355 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1296 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1356 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1297 1357
1298 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 1358 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
@@ -1305,6 +1365,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1305 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1365 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1306 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1366 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1307 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1367 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1368 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1308 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1369 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1309 1370
1310 if (rt2x00_is_usb(rt2x00dev)) { 1371 if (rt2x00_is_usb(rt2x00dev)) {
@@ -1334,6 +1395,15 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1334 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 1395 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1335 1396
1336 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 1397 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1398
1399 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1400 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 32);
1401 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 32);
1402 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1403 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1404 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1405 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1406
1337 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1407 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1338 1408
1339 /* 1409 /*
@@ -1483,38 +1553,67 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1483 1553
1484 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 1554 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1485 rt2800_bbp_write(rt2x00dev, 66, 0x38); 1555 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1486 rt2800_bbp_write(rt2x00dev, 69, 0x12); 1556
1557 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1558 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1559 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1560 } else {
1561 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1562 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1563 }
1564
1487 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1565 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1488 rt2800_bbp_write(rt2x00dev, 73, 0x10); 1566
1489 rt2800_bbp_write(rt2x00dev, 81, 0x37); 1567 if (rt2x00_rt(rt2x00dev, RT3070) ||
1568 rt2x00_rt(rt2x00dev, RT3071) ||
1569 rt2x00_rt(rt2x00dev, RT3090) ||
1570 rt2x00_rt(rt2x00dev, RT3390)) {
1571 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1572 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1573 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1574 } else {
1575 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1576 }
1577
1490 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1578 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1491 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 1579 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1492 rt2800_bbp_write(rt2x00dev, 84, 0x99); 1580
1581 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1582 rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1583 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1584 else
1585 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1586
1493 rt2800_bbp_write(rt2x00dev, 86, 0x00); 1587 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1494 rt2800_bbp_write(rt2x00dev, 91, 0x04); 1588 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1495 rt2800_bbp_write(rt2x00dev, 92, 0x00); 1589 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1496 rt2800_bbp_write(rt2x00dev, 103, 0x00); 1590
1591 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1592 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1593 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1594 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
1595 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1596 else
1597 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1598
1497 rt2800_bbp_write(rt2x00dev, 105, 0x05); 1599 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1600 rt2800_bbp_write(rt2x00dev, 106, 0x35);
1498 1601
1499 if (rt2x00_rt(rt2x00dev, RT2860) && 1602 if (rt2x00_rt(rt2x00dev, RT3071) ||
1500 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) { 1603 rt2x00_rt(rt2x00dev, RT3090) ||
1501 rt2800_bbp_write(rt2x00dev, 69, 0x16); 1604 rt2x00_rt(rt2x00dev, RT3390)) {
1502 rt2800_bbp_write(rt2x00dev, 73, 0x12); 1605 rt2800_bbp_read(rt2x00dev, 138, &value);
1503 }
1504 1606
1505 if (rt2x00_rt(rt2x00dev, RT2860) && 1607 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1506 (rt2x00_rev(rt2x00dev) > RT2860D_VERSION)) 1608 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1507 rt2800_bbp_write(rt2x00dev, 84, 0x19); 1609 value |= 0x20;
1610 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1611 value &= ~0x02;
1508 1612
1509 if (rt2x00_is_usb(rt2x00dev) && 1613 rt2800_bbp_write(rt2x00dev, 138, value);
1510 rt2x00_rt(rt2x00dev, RT3070) &&
1511 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) {
1512 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1513 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1514 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1515 } 1614 }
1516 1615
1517 if (rt2x00_rt(rt2x00dev, RT3052)) { 1616 if (rt2x00_rt(rt2x00dev, RT2872)) {
1518 rt2800_bbp_write(rt2x00dev, 31, 0x08); 1617 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1519 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 1618 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1520 rt2800_bbp_write(rt2x00dev, 80, 0x08); 1619 rt2800_bbp_write(rt2x00dev, 80, 0x08);
@@ -1598,19 +1697,15 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1598{ 1697{
1599 u8 rfcsr; 1698 u8 rfcsr;
1600 u8 bbp; 1699 u8 bbp;
1700 u32 reg;
1701 u16 eeprom;
1601 1702
1602 if (rt2x00_is_usb(rt2x00dev) && 1703 if (!rt2x00_rt(rt2x00dev, RT3070) &&
1603 rt2x00_rt(rt2x00dev, RT3070) && 1704 !rt2x00_rt(rt2x00dev, RT3071) &&
1604 (rt2x00_rev(rt2x00dev) != RT3070_VERSION)) 1705 !rt2x00_rt(rt2x00dev, RT3090) &&
1706 !rt2x00_rt(rt2x00dev, RT3390))
1605 return 0; 1707 return 0;
1606 1708
1607 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1608 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1609 !rt2x00_rf(rt2x00dev, RF3021) &&
1610 !rt2x00_rf(rt2x00dev, RF3022))
1611 return 0;
1612 }
1613
1614 /* 1709 /*
1615 * Init RF calibration. 1710 * Init RF calibration.
1616 */ 1711 */
@@ -1621,13 +1716,15 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1621 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 1716 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1622 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1717 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1623 1718
1624 if (rt2x00_is_usb(rt2x00dev)) { 1719 if (rt2x00_rt(rt2x00dev, RT3070) ||
1720 rt2x00_rt(rt2x00dev, RT3071) ||
1721 rt2x00_rt(rt2x00dev, RT3090)) {
1625 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1722 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1626 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1723 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1627 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1724 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1628 rt2800_rfcsr_write(rt2x00dev, 7, 0x70); 1725 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1629 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1726 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1630 rt2800_rfcsr_write(rt2x00dev, 10, 0x71); 1727 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1631 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1728 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1632 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 1729 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1633 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1730 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
@@ -1640,48 +1737,88 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1640 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1737 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1641 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 1738 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1642 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1739 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1643 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1644 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 1740 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1645 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) { 1741 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1646 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 1742 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1647 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 1743 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1648 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 1744 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1649 rt2800_rfcsr_write(rt2x00dev, 3, 0x75); 1745 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1650 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1746 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1651 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1747 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1652 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1748 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1653 rt2800_rfcsr_write(rt2x00dev, 7, 0x50); 1749 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1654 rt2800_rfcsr_write(rt2x00dev, 8, 0x39); 1750 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1655 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1751 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1656 rt2800_rfcsr_write(rt2x00dev, 10, 0x60); 1752 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1657 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1753 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1658 rt2800_rfcsr_write(rt2x00dev, 12, 0x75); 1754 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1659 rt2800_rfcsr_write(rt2x00dev, 13, 0x75); 1755 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1660 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1756 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1661 rt2800_rfcsr_write(rt2x00dev, 15, 0x58); 1757 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1662 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); 1758 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1663 rt2800_rfcsr_write(rt2x00dev, 17, 0x92); 1759 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1664 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); 1760 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1665 rt2800_rfcsr_write(rt2x00dev, 19, 0x02); 1761 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1666 rt2800_rfcsr_write(rt2x00dev, 20, 0xba); 1762 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1667 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1763 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1668 rt2800_rfcsr_write(rt2x00dev, 22, 0x00); 1764 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1669 rt2800_rfcsr_write(rt2x00dev, 23, 0x31); 1765 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1670 rt2800_rfcsr_write(rt2x00dev, 24, 0x08); 1766 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1671 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1767 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1672 rt2800_rfcsr_write(rt2x00dev, 26, 0x25); 1768 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1673 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 1769 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1674 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 1770 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1675 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 1771 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1772 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1773 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
1774 }
1775
1776 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1777 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1778 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1779 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1780 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1781 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1782 rt2x00_rt(rt2x00dev, RT3090)) {
1783 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1784 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1785 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1786
1787 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1788
1789 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1790 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1791 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1792 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1793 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1794 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1795 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1796 else
1797 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1798 }
1799 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1800 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1801 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1802 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1803 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1676 } 1804 }
1677 1805
1678 /* 1806 /*
1679 * Set RX Filter calibration for 20MHz and 40MHz 1807 * Set RX Filter calibration for 20MHz and 40MHz
1680 */ 1808 */
1681 rt2x00dev->calibration[0] = 1809 if (rt2x00_rt(rt2x00dev, RT3070)) {
1682 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); 1810 rt2x00dev->calibration[0] =
1683 rt2x00dev->calibration[1] = 1811 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1684 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 1812 rt2x00dev->calibration[1] =
1813 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1814 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1815 rt2x00_rt(rt2x00dev, RT3090) ||
1816 rt2x00_rt(rt2x00dev, RT3390)) {
1817 rt2x00dev->calibration[0] =
1818 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1819 rt2x00dev->calibration[1] =
1820 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
1821 }
1685 1822
1686 /* 1823 /*
1687 * Set back to initial state 1824 * Set back to initial state
@@ -1699,6 +1836,81 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1699 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 1836 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1700 rt2800_bbp_write(rt2x00dev, 4, bbp); 1837 rt2800_bbp_write(rt2x00dev, 4, bbp);
1701 1838
1839 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1840 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1841 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1842 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
1843 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1844
1845 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
1846 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
1847 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
1848
1849 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1850 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
1851 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1852 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1853 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1854 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1855 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1856 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
1857 }
1858 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
1859 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
1860 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
1861 rt2x00_get_field16(eeprom,
1862 EEPROM_TXMIXER_GAIN_BG_VAL));
1863 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1864
1865 if (rt2x00_rt(rt2x00dev, RT3090)) {
1866 rt2800_bbp_read(rt2x00dev, 138, &bbp);
1867
1868 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1869 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1870 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
1871 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1872 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
1873
1874 rt2800_bbp_write(rt2x00dev, 138, bbp);
1875 }
1876
1877 if (rt2x00_rt(rt2x00dev, RT3071) ||
1878 rt2x00_rt(rt2x00dev, RT3090) ||
1879 rt2x00_rt(rt2x00dev, RT3390)) {
1880 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1881 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1882 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1883 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1884 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1885 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1886 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1887
1888 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
1889 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
1890 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
1891
1892 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
1893 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
1894 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
1895
1896 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
1897 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
1898 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
1899 }
1900
1901 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
1902 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
1903 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
1904 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
1905 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
1906 else
1907 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
1908 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
1909 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
1910 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
1911 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
1912 }
1913
1702 return 0; 1914 return 0;
1703} 1915}
1704EXPORT_SYMBOL_GPL(rt2800_init_rfcsr); 1916EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
@@ -1775,9 +1987,7 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1775 } else if (rt2x00_rt(rt2x00dev, RT2860) || 1987 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1776 rt2x00_rt(rt2x00dev, RT2870) || 1988 rt2x00_rt(rt2x00dev, RT2870) ||
1777 rt2x00_rt(rt2x00dev, RT2872) || 1989 rt2x00_rt(rt2x00dev, RT2872) ||
1778 rt2x00_rt(rt2x00dev, RT2880) || 1990 rt2x00_rt(rt2x00dev, RT2872)) {
1779 (rt2x00_rt(rt2x00dev, RT2883) &&
1780 (rt2x00_rev(rt2x00dev) < RT2883_VERSION))) {
1781 /* 1991 /*
1782 * There is a max of 2 RX streams for RT28x0 series 1992 * There is a max of 2 RX streams for RT28x0 series
1783 */ 1993 */
@@ -1882,10 +2092,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1882 if (!rt2x00_rt(rt2x00dev, RT2860) && 2092 if (!rt2x00_rt(rt2x00dev, RT2860) &&
1883 !rt2x00_rt(rt2x00dev, RT2870) && 2093 !rt2x00_rt(rt2x00dev, RT2870) &&
1884 !rt2x00_rt(rt2x00dev, RT2872) && 2094 !rt2x00_rt(rt2x00dev, RT2872) &&
1885 !rt2x00_rt(rt2x00dev, RT2880) &&
1886 !rt2x00_rt(rt2x00dev, RT2883) && 2095 !rt2x00_rt(rt2x00dev, RT2883) &&
1887 !rt2x00_rt(rt2x00dev, RT2890) &&
1888 !rt2x00_rt(rt2x00dev, RT3052) &&
1889 !rt2x00_rt(rt2x00dev, RT3070) && 2096 !rt2x00_rt(rt2x00dev, RT3070) &&
1890 !rt2x00_rt(rt2x00dev, RT3071) && 2097 !rt2x00_rt(rt2x00dev, RT3071) &&
1891 !rt2x00_rt(rt2x00dev, RT3090) && 2098 !rt2x00_rt(rt2x00dev, RT3090) &&
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 22:43:45 -0500