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path: root/drivers/net/wireless/rt2x00/rt2800lib.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800lib.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c1489
1 files changed, 1154 insertions, 335 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index a658b4bc7da2..b52d70c75e1a 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -80,7 +80,7 @@ static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
80 rt2x00_rf(rt2x00dev, RF3022)) 80 rt2x00_rf(rt2x00dev, RF3022))
81 return true; 81 return true;
82 82
83 WARNING(rt2x00dev, "Unknown RF chipset on rt305x\n"); 83 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
84 return false; 84 return false;
85} 85}
86 86
@@ -328,7 +328,7 @@ int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
328 msleep(1); 328 msleep(1);
329 } 329 }
330 330
331 ERROR(rt2x00dev, "Unstable hardware.\n"); 331 rt2x00_err(rt2x00dev, "Unstable hardware\n");
332 return -EBUSY; 332 return -EBUSY;
333} 333}
334EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready); 334EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
@@ -351,7 +351,7 @@ int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
351 msleep(10); 351 msleep(10);
352 } 352 }
353 353
354 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg); 354 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
355 return -EACCES; 355 return -EACCES;
356} 356}
357EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 357EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
@@ -512,7 +512,7 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
512 } 512 }
513 513
514 if (i == REGISTER_BUSY_COUNT) { 514 if (i == REGISTER_BUSY_COUNT) {
515 ERROR(rt2x00dev, "PBF system register not ready.\n"); 515 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
516 return -EBUSY; 516 return -EBUSY;
517 } 517 }
518 518
@@ -527,8 +527,10 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
527 */ 527 */
528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0); 528 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); 529 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
530 if (rt2x00_is_usb(rt2x00dev)) 530 if (rt2x00_is_usb(rt2x00dev)) {
531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0); 531 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
532 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
533 }
532 msleep(1); 534 msleep(1);
533 535
534 return 0; 536 return 0;
@@ -540,6 +542,7 @@ void rt2800_write_tx_data(struct queue_entry *entry,
540{ 542{
541 __le32 *txwi = rt2800_drv_get_txwi(entry); 543 __le32 *txwi = rt2800_drv_get_txwi(entry);
542 u32 word; 544 u32 word;
545 int i;
543 546
544 /* 547 /*
545 * Initialize TX Info descriptor 548 * Initialize TX Info descriptor
@@ -582,14 +585,16 @@ void rt2800_write_tx_data(struct queue_entry *entry,
582 rt2x00_desc_write(txwi, 1, word); 585 rt2x00_desc_write(txwi, 1, word);
583 586
584 /* 587 /*
585 * Always write 0 to IV/EIV fields, hardware will insert the IV 588 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
586 * from the IVEIV register when TXD_W3_WIV is set to 0. 589 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
587 * When TXD_W3_WIV is set to 1 it will use the IV data 590 * When TXD_W3_WIV is set to 1 it will use the IV data
588 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which 591 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
589 * crypto entry in the registers should be used to encrypt the frame. 592 * crypto entry in the registers should be used to encrypt the frame.
593 *
594 * Nulify all remaining words as well, we don't know how to program them.
590 */ 595 */
591 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */); 596 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
592 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */); 597 _rt2x00_desc_write(txwi, i, 0);
593} 598}
594EXPORT_SYMBOL_GPL(rt2800_write_tx_data); 599EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
595 600
@@ -674,11 +679,10 @@ void rt2800_process_rxwi(struct queue_entry *entry,
674 * Convert descriptor AGC value to RSSI value. 679 * Convert descriptor AGC value to RSSI value.
675 */ 680 */
676 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word); 681 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
677
678 /* 682 /*
679 * Remove RXWI descriptor from start of buffer. 683 * Remove RXWI descriptor from start of the buffer.
680 */ 684 */
681 skb_pull(entry->skb, RXWI_DESC_SIZE); 685 skb_pull(entry->skb, entry->queue->winfo_size);
682} 686}
683EXPORT_SYMBOL_GPL(rt2800_process_rxwi); 687EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
684 688
@@ -769,6 +773,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
769 unsigned int beacon_base; 773 unsigned int beacon_base;
770 unsigned int padding_len; 774 unsigned int padding_len;
771 u32 orig_reg, reg; 775 u32 orig_reg, reg;
776 const int txwi_desc_size = entry->queue->winfo_size;
772 777
773 /* 778 /*
774 * Disable beaconing while we are reloading the beacon data, 779 * Disable beaconing while we are reloading the beacon data,
@@ -782,14 +787,14 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
782 /* 787 /*
783 * Add space for the TXWI in front of the skb. 788 * Add space for the TXWI in front of the skb.
784 */ 789 */
785 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE); 790 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
786 791
787 /* 792 /*
788 * Register descriptor details in skb frame descriptor. 793 * Register descriptor details in skb frame descriptor.
789 */ 794 */
790 skbdesc->flags |= SKBDESC_DESC_IN_SKB; 795 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
791 skbdesc->desc = entry->skb->data; 796 skbdesc->desc = entry->skb->data;
792 skbdesc->desc_len = TXWI_DESC_SIZE; 797 skbdesc->desc_len = txwi_desc_size;
793 798
794 /* 799 /*
795 * Add the TXWI for the beacon to the skb. 800 * Add the TXWI for the beacon to the skb.
@@ -806,7 +811,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
806 */ 811 */
807 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; 812 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
808 if (padding_len && skb_pad(entry->skb, padding_len)) { 813 if (padding_len && skb_pad(entry->skb, padding_len)) {
809 ERROR(rt2x00dev, "Failure padding beacon, aborting\n"); 814 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
810 /* skb freed by skb_pad() on failure */ 815 /* skb freed by skb_pad() on failure */
811 entry->skb = NULL; 816 entry->skb = NULL;
812 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg); 817 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
@@ -835,13 +840,14 @@ static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
835 unsigned int beacon_base) 840 unsigned int beacon_base)
836{ 841{
837 int i; 842 int i;
843 const int txwi_desc_size = rt2x00dev->ops->bcn->winfo_size;
838 844
839 /* 845 /*
840 * For the Beacon base registers we only need to clear 846 * For the Beacon base registers we only need to clear
841 * the whole TXWI which (when set to 0) will invalidate 847 * the whole TXWI which (when set to 0) will invalidate
842 * the entire beacon. 848 * the entire beacon.
843 */ 849 */
844 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32)) 850 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
845 rt2800_register_write(rt2x00dev, beacon_base + i, 0); 851 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
846} 852}
847 853
@@ -1988,8 +1994,21 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1988} 1994}
1989 1995
1990#define POWER_BOUND 0x27 1996#define POWER_BOUND 0x27
1997#define POWER_BOUND_5G 0x2b
1991#define FREQ_OFFSET_BOUND 0x5f 1998#define FREQ_OFFSET_BOUND 0x5f
1992 1999
2000static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2001{
2002 u8 rfcsr;
2003
2004 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2005 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2006 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2007 else
2008 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2009 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2010}
2011
1993static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev, 2012static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1994 struct ieee80211_conf *conf, 2013 struct ieee80211_conf *conf,
1995 struct rf_channel *rf, 2014 struct rf_channel *rf,
@@ -2010,12 +2029,7 @@ static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2010 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1); 2029 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2011 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr); 2030 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2012 2031
2013 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 2032 rt2800_adjust_freq_offset(rt2x00dev);
2014 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2015 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2016 else
2017 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2018 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2019 2033
2020 if (rf->channel <= 14) { 2034 if (rf->channel <= 14) {
2021 if (rf->channel == 6) 2035 if (rf->channel == 6)
@@ -2056,13 +2070,7 @@ static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2056 else 2070 else
2057 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2); 2071 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2058 2072
2059 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 2073 rt2800_adjust_freq_offset(rt2x00dev);
2060 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2061 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2062 else
2063 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2064
2065 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2066 2074
2067 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); 2075 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2068 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); 2076 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
@@ -2127,12 +2135,7 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2127 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); 2135 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2128 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); 2136 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2129 2137
2130 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); 2138 rt2800_adjust_freq_offset(rt2x00dev);
2131 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2132 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2133 else
2134 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2135 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2136 2139
2137 if (rf->channel <= 14) { 2140 if (rf->channel <= 14) {
2138 int idx = rf->channel-1; 2141 int idx = rf->channel-1;
@@ -2184,6 +2187,382 @@ static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2184 } 2187 }
2185} 2188}
2186 2189
2190static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2191 struct ieee80211_conf *conf,
2192 struct rf_channel *rf,
2193 struct channel_info *info)
2194{
2195 u8 rfcsr, ep_reg;
2196 u32 reg;
2197 int power_bound;
2198
2199 /* TODO */
2200 const bool is_11b = false;
2201 const bool is_type_ep = false;
2202
2203 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2204 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2205 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2206 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2207
2208 /* Order of values on rf_channel entry: N, K, mod, R */
2209 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2210
2211 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2212 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2213 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2214 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2215 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2216
2217 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2218 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2219 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2220 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2221
2222 if (rf->channel <= 14) {
2223 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2224 /* FIXME: RF11 owerwrite ? */
2225 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2226 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2227 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2228 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2229 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2230 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2231 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2232 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2233 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2234 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2235 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2236 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2237 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2238 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2239 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2240 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2241 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2242 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2243 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2244 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2245 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2246 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2247 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2248 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2249 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2250 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2251 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2252 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2253
2254 /* TODO RF27 <- tssi */
2255
2256 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2257 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2258 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2259
2260 if (is_11b) {
2261 /* CCK */
2262 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2263 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2264 if (is_type_ep)
2265 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2266 else
2267 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2268 } else {
2269 /* OFDM */
2270 if (is_type_ep)
2271 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2272 else
2273 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2274 }
2275
2276 power_bound = POWER_BOUND;
2277 ep_reg = 0x2;
2278 } else {
2279 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2280 /* FIMXE: RF11 overwrite */
2281 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2282 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2283 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2284 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2285 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2286 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2287 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2288 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2289 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2290 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2291 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2292 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2293 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2294 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2295
2296 /* TODO RF27 <- tssi */
2297
2298 if (rf->channel >= 36 && rf->channel <= 64) {
2299
2300 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2301 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2302 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2303 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2304 if (rf->channel <= 50)
2305 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2306 else if (rf->channel >= 52)
2307 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2308 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2309 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2310 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2311 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2312 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2313 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2314 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2315 if (rf->channel <= 50) {
2316 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2317 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2318 } else if (rf->channel >= 52) {
2319 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2320 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2321 }
2322
2323 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2324 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2325 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2326
2327 } else if (rf->channel >= 100 && rf->channel <= 165) {
2328
2329 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2330 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2331 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2332 if (rf->channel <= 153) {
2333 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2334 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2335 } else if (rf->channel >= 155) {
2336 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2337 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2338 }
2339 if (rf->channel <= 138) {
2340 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2341 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2342 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2343 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2344 } else if (rf->channel >= 140) {
2345 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2346 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2347 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2348 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2349 }
2350 if (rf->channel <= 124)
2351 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2352 else if (rf->channel >= 126)
2353 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2354 if (rf->channel <= 138)
2355 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2356 else if (rf->channel >= 140)
2357 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2358 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2359 if (rf->channel <= 138)
2360 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2361 else if (rf->channel >= 140)
2362 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2363 if (rf->channel <= 128)
2364 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2365 else if (rf->channel >= 130)
2366 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2367 if (rf->channel <= 116)
2368 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2369 else if (rf->channel >= 118)
2370 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2371 if (rf->channel <= 138)
2372 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2373 else if (rf->channel >= 140)
2374 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2375 if (rf->channel <= 116)
2376 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2377 else if (rf->channel >= 118)
2378 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2379 }
2380
2381 power_bound = POWER_BOUND_5G;
2382 ep_reg = 0x3;
2383 }
2384
2385 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2386 if (info->default_power1 > power_bound)
2387 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2388 else
2389 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2390 if (is_type_ep)
2391 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2392 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2393
2394 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2395 if (info->default_power1 > power_bound)
2396 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2397 else
2398 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2399 if (is_type_ep)
2400 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2401 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2402
2403 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2404 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2405 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2406
2407 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2408 rt2x00dev->default_ant.tx_chain_num >= 1);
2409 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2410 rt2x00dev->default_ant.tx_chain_num == 2);
2411 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2412
2413 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2414 rt2x00dev->default_ant.rx_chain_num >= 1);
2415 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2416 rt2x00dev->default_ant.rx_chain_num == 2);
2417 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2418
2419 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2420 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2421
2422 if (conf_is_ht40(conf))
2423 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2424 else
2425 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2426
2427 if (!is_11b) {
2428 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2429 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2430 }
2431
2432 /* TODO proper frequency adjustment */
2433 rt2800_adjust_freq_offset(rt2x00dev);
2434
2435 /* TODO merge with others */
2436 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2437 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2438 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2439
2440 /* BBP settings */
2441 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2442 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2443 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2444
2445 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2446 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2447 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2448 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2449
2450 /* GLRT band configuration */
2451 rt2800_bbp_write(rt2x00dev, 195, 128);
2452 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2453 rt2800_bbp_write(rt2x00dev, 195, 129);
2454 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2455 rt2800_bbp_write(rt2x00dev, 195, 130);
2456 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2457 rt2800_bbp_write(rt2x00dev, 195, 131);
2458 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2459 rt2800_bbp_write(rt2x00dev, 195, 133);
2460 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2461 rt2800_bbp_write(rt2x00dev, 195, 124);
2462 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2463}
2464
2465static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2466 const unsigned int word,
2467 const u8 value)
2468{
2469 u8 chain, reg;
2470
2471 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2472 rt2800_bbp_read(rt2x00dev, 27, &reg);
2473 rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
2474 rt2800_bbp_write(rt2x00dev, 27, reg);
2475
2476 rt2800_bbp_write(rt2x00dev, word, value);
2477 }
2478}
2479
2480static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2481{
2482 u8 cal;
2483
2484 /* TX0 IQ Gain */
2485 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2486 if (channel <= 14)
2487 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2488 else if (channel >= 36 && channel <= 64)
2489 cal = rt2x00_eeprom_byte(rt2x00dev,
2490 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2491 else if (channel >= 100 && channel <= 138)
2492 cal = rt2x00_eeprom_byte(rt2x00dev,
2493 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2494 else if (channel >= 140 && channel <= 165)
2495 cal = rt2x00_eeprom_byte(rt2x00dev,
2496 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2497 else
2498 cal = 0;
2499 rt2800_bbp_write(rt2x00dev, 159, cal);
2500
2501 /* TX0 IQ Phase */
2502 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2503 if (channel <= 14)
2504 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2505 else if (channel >= 36 && channel <= 64)
2506 cal = rt2x00_eeprom_byte(rt2x00dev,
2507 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2508 else if (channel >= 100 && channel <= 138)
2509 cal = rt2x00_eeprom_byte(rt2x00dev,
2510 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2511 else if (channel >= 140 && channel <= 165)
2512 cal = rt2x00_eeprom_byte(rt2x00dev,
2513 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2514 else
2515 cal = 0;
2516 rt2800_bbp_write(rt2x00dev, 159, cal);
2517
2518 /* TX1 IQ Gain */
2519 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
2520 if (channel <= 14)
2521 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2522 else if (channel >= 36 && channel <= 64)
2523 cal = rt2x00_eeprom_byte(rt2x00dev,
2524 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2525 else if (channel >= 100 && channel <= 138)
2526 cal = rt2x00_eeprom_byte(rt2x00dev,
2527 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2528 else if (channel >= 140 && channel <= 165)
2529 cal = rt2x00_eeprom_byte(rt2x00dev,
2530 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2531 else
2532 cal = 0;
2533 rt2800_bbp_write(rt2x00dev, 159, cal);
2534
2535 /* TX1 IQ Phase */
2536 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
2537 if (channel <= 14)
2538 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2539 else if (channel >= 36 && channel <= 64)
2540 cal = rt2x00_eeprom_byte(rt2x00dev,
2541 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2542 else if (channel >= 100 && channel <= 138)
2543 cal = rt2x00_eeprom_byte(rt2x00dev,
2544 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2545 else if (channel >= 140 && channel <= 165)
2546 cal = rt2x00_eeprom_byte(rt2x00dev,
2547 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2548 else
2549 cal = 0;
2550 rt2800_bbp_write(rt2x00dev, 159, cal);
2551
2552 /* FIXME: possible RX0, RX1 callibration ? */
2553
2554 /* RF IQ compensation control */
2555 rt2800_bbp_write(rt2x00dev, 158, 0x04);
2556 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2557 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2558
2559 /* RF IQ imbalance compensation control */
2560 rt2800_bbp_write(rt2x00dev, 158, 0x03);
2561 cal = rt2x00_eeprom_byte(rt2x00dev,
2562 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
2563 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2564}
2565
2187static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, 2566static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2188 struct ieee80211_conf *conf, 2567 struct ieee80211_conf *conf,
2189 struct rf_channel *rf, 2568 struct rf_channel *rf,
@@ -2225,6 +2604,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2225 case RF5392: 2604 case RF5392:
2226 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); 2605 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2227 break; 2606 break;
2607 case RF5592:
2608 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2609 break;
2228 default: 2610 default:
2229 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); 2611 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2230 } 2612 }
@@ -2326,6 +2708,17 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2326 if (rt2x00_rt(rt2x00dev, RT3572)) 2708 if (rt2x00_rt(rt2x00dev, RT3572))
2327 rt2800_rfcsr_write(rt2x00dev, 8, 0x80); 2709 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2328 2710
2711 if (rt2x00_rt(rt2x00dev, RT5592)) {
2712 rt2800_bbp_write(rt2x00dev, 195, 141);
2713 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2714
2715 /* AGC init */
2716 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2717 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2718
2719 rt2800_iq_calibrate(rt2x00dev, rf->channel);
2720 }
2721
2329 rt2800_bbp_read(rt2x00dev, 4, &bbp); 2722 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2330 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); 2723 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2331 rt2800_bbp_write(rt2x00dev, 4, bbp); 2724 rt2800_bbp_write(rt2x00dev, 4, bbp);
@@ -2763,7 +3156,7 @@ static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2763 3156
2764void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev) 3157void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2765{ 3158{
2766 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.channel, 3159 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
2767 rt2x00dev->tx_power); 3160 rt2x00dev->tx_power);
2768} 3161}
2769EXPORT_SYMBOL_GPL(rt2800_gain_calibration); 3162EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
@@ -2898,11 +3291,11 @@ void rt2800_config(struct rt2x00_dev *rt2x00dev,
2898 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) { 3291 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2899 rt2800_config_channel(rt2x00dev, libconf->conf, 3292 rt2800_config_channel(rt2x00dev, libconf->conf,
2900 &libconf->rf, &libconf->channel); 3293 &libconf->rf, &libconf->channel);
2901 rt2800_config_txpower(rt2x00dev, libconf->conf->channel, 3294 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
2902 libconf->conf->power_level); 3295 libconf->conf->power_level);
2903 } 3296 }
2904 if (flags & IEEE80211_CONF_CHANGE_POWER) 3297 if (flags & IEEE80211_CONF_CHANGE_POWER)
2905 rt2800_config_txpower(rt2x00dev, libconf->conf->channel, 3298 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
2906 libconf->conf->power_level); 3299 libconf->conf->power_level);
2907 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS) 3300 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2908 rt2800_config_retry_limit(rt2x00dev, libconf); 3301 rt2800_config_retry_limit(rt2x00dev, libconf);
@@ -2938,13 +3331,16 @@ static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2938 rt2x00_rt(rt2x00dev, RT3390) || 3331 rt2x00_rt(rt2x00dev, RT3390) ||
2939 rt2x00_rt(rt2x00dev, RT3572) || 3332 rt2x00_rt(rt2x00dev, RT3572) ||
2940 rt2x00_rt(rt2x00dev, RT5390) || 3333 rt2x00_rt(rt2x00dev, RT5390) ||
2941 rt2x00_rt(rt2x00dev, RT5392)) 3334 rt2x00_rt(rt2x00dev, RT5392) ||
3335 rt2x00_rt(rt2x00dev, RT5592))
2942 vgc = 0x1c + (2 * rt2x00dev->lna_gain); 3336 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
2943 else 3337 else
2944 vgc = 0x2e + rt2x00dev->lna_gain; 3338 vgc = 0x2e + rt2x00dev->lna_gain;
2945 } else { /* 5GHZ band */ 3339 } else { /* 5GHZ band */
2946 if (rt2x00_rt(rt2x00dev, RT3572)) 3340 if (rt2x00_rt(rt2x00dev, RT3572))
2947 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3; 3341 vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3342 else if (rt2x00_rt(rt2x00dev, RT5592))
3343 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
2948 else { 3344 else {
2949 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) 3345 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2950 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3; 3346 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
@@ -2960,7 +3356,11 @@ static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2960 struct link_qual *qual, u8 vgc_level) 3356 struct link_qual *qual, u8 vgc_level)
2961{ 3357{
2962 if (qual->vgc_level != vgc_level) { 3358 if (qual->vgc_level != vgc_level) {
2963 rt2800_bbp_write(rt2x00dev, 66, vgc_level); 3359 if (rt2x00_rt(rt2x00dev, RT5592)) {
3360 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3361 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
3362 } else
3363 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2964 qual->vgc_level = vgc_level; 3364 qual->vgc_level = vgc_level;
2965 qual->vgc_level_reg = vgc_level; 3365 qual->vgc_level_reg = vgc_level;
2966 } 3366 }
@@ -2975,15 +3375,23 @@ EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2975void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 3375void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2976 const u32 count) 3376 const u32 count)
2977{ 3377{
3378 u8 vgc;
3379
2978 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) 3380 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2979 return; 3381 return;
2980
2981 /* 3382 /*
2982 * When RSSI is better then -80 increase VGC level with 0x10 3383 * When RSSI is better then -80 increase VGC level with 0x10, except
3384 * for rt5592 chip.
2983 */ 3385 */
2984 rt2800_set_vgc(rt2x00dev, qual, 3386
2985 rt2800_get_default_vgc(rt2x00dev) + 3387 vgc = rt2800_get_default_vgc(rt2x00dev);
2986 ((qual->rssi > -80) * 0x10)); 3388
3389 if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
3390 vgc += 0x20;
3391 else if (qual->rssi > -80)
3392 vgc += 0x10;
3393
3394 rt2800_set_vgc(rt2x00dev, qual, vgc);
2987} 3395}
2988EXPORT_SYMBOL_GPL(rt2800_link_tuner); 3396EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2989 3397
@@ -3122,7 +3530,8 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3122 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 3530 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3123 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 3531 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3124 } else if (rt2x00_rt(rt2x00dev, RT5390) || 3532 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3125 rt2x00_rt(rt2x00dev, RT5392)) { 3533 rt2x00_rt(rt2x00dev, RT5392) ||
3534 rt2x00_rt(rt2x00dev, RT5592)) {
3126 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 3535 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3127 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 3536 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3128 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 3537 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
@@ -3302,7 +3711,8 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3302 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0); 3711 rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3303 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 3712 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3304 3713
3305 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002); 3714 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3715 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3306 3716
3307 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg); 3717 rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3308 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); 3718 rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
@@ -3459,7 +3869,7 @@ static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3459 udelay(REGISTER_BUSY_DELAY); 3869 udelay(REGISTER_BUSY_DELAY);
3460 } 3870 }
3461 3871
3462 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n"); 3872 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
3463 return -EACCES; 3873 return -EACCES;
3464} 3874}
3465 3875
@@ -3483,10 +3893,140 @@ static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3483 udelay(REGISTER_BUSY_DELAY); 3893 udelay(REGISTER_BUSY_DELAY);
3484 } 3894 }
3485 3895
3486 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 3896 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
3487 return -EACCES; 3897 return -EACCES;
3488} 3898}
3489 3899
3900static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3901{
3902 u8 value;
3903
3904 rt2800_bbp_read(rt2x00dev, 4, &value);
3905 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3906 rt2800_bbp_write(rt2x00dev, 4, value);
3907}
3908
3909static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3910{
3911 rt2800_bbp_write(rt2x00dev, 142, 1);
3912 rt2800_bbp_write(rt2x00dev, 143, 57);
3913}
3914
3915static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3916{
3917 const u8 glrt_table[] = {
3918 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3919 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3920 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3921 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3922 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3923 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3924 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3925 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3926 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
3927 };
3928 int i;
3929
3930 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3931 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3932 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3933 }
3934};
3935
3936static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
3937{
3938 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3939 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3940 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3941 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3942 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3943 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3944 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3945 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3946 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3947 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3948 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3949 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3950 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3951 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3952 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3953 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3954}
3955
3956static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3957{
3958 int ant, div_mode;
3959 u16 eeprom;
3960 u8 value;
3961
3962 rt2800_init_bbp_early(rt2x00dev);
3963
3964 rt2800_bbp_read(rt2x00dev, 105, &value);
3965 rt2x00_set_field8(&value, BBP105_MLD,
3966 rt2x00dev->default_ant.rx_chain_num == 2);
3967 rt2800_bbp_write(rt2x00dev, 105, value);
3968
3969 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3970
3971 rt2800_bbp_write(rt2x00dev, 20, 0x06);
3972 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3973 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3974 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3975 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3976 rt2800_bbp_write(rt2x00dev, 70, 0x05);
3977 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3978 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3979 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3980 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3981 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3982 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3983 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3984 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3985 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3986 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3987 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3988 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3989 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3990 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3991 /* FIXME BBP105 owerwrite */
3992 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3993 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3994 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3995 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3996 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3997 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3998
3999 /* Initialize GLRT (Generalized Likehood Radio Test) */
4000 rt2800_init_bbp_5592_glrt(rt2x00dev);
4001
4002 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4003
4004 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4005 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
4006 ant = (div_mode == 3) ? 1 : 0;
4007 rt2800_bbp_read(rt2x00dev, 152, &value);
4008 if (ant == 0) {
4009 /* Main antenna */
4010 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4011 } else {
4012 /* Auxiliary antenna */
4013 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4014 }
4015 rt2800_bbp_write(rt2x00dev, 152, value);
4016
4017 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
4018 rt2800_bbp_read(rt2x00dev, 254, &value);
4019 rt2x00_set_field8(&value, BBP254_BIT7, 1);
4020 rt2800_bbp_write(rt2x00dev, 254, value);
4021 }
4022
4023 rt2800_init_freq_calibration(rt2x00dev);
4024
4025 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4026 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4027 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4028}
4029
3490static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) 4030static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3491{ 4031{
3492 unsigned int i; 4032 unsigned int i;
@@ -3498,6 +4038,11 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3498 rt2800_wait_bbp_ready(rt2x00dev))) 4038 rt2800_wait_bbp_ready(rt2x00dev)))
3499 return -EACCES; 4039 return -EACCES;
3500 4040
4041 if (rt2x00_rt(rt2x00dev, RT5592)) {
4042 rt2800_init_bbp_5592(rt2x00dev);
4043 return 0;
4044 }
4045
3501 if (rt2x00_rt(rt2x00dev, RT3352)) { 4046 if (rt2x00_rt(rt2x00dev, RT3352)) {
3502 rt2800_bbp_write(rt2x00dev, 3, 0x00); 4047 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3503 rt2800_bbp_write(rt2x00dev, 4, 0x50); 4048 rt2800_bbp_write(rt2x00dev, 4, 0x50);
@@ -3505,11 +4050,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3505 4050
3506 if (rt2x00_rt(rt2x00dev, RT3290) || 4051 if (rt2x00_rt(rt2x00dev, RT3290) ||
3507 rt2x00_rt(rt2x00dev, RT5390) || 4052 rt2x00_rt(rt2x00dev, RT5390) ||
3508 rt2x00_rt(rt2x00dev, RT5392)) { 4053 rt2x00_rt(rt2x00dev, RT5392))
3509 rt2800_bbp_read(rt2x00dev, 4, &value); 4054 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3510 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3511 rt2800_bbp_write(rt2x00dev, 4, value);
3512 }
3513 4055
3514 if (rt2800_is_305x_soc(rt2x00dev) || 4056 if (rt2800_is_305x_soc(rt2x00dev) ||
3515 rt2x00_rt(rt2x00dev, RT3290) || 4057 rt2x00_rt(rt2x00dev, RT3290) ||
@@ -3783,9 +4325,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3783 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0); 4325 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3784 rt2800_bbp_write(rt2x00dev, 152, value); 4326 rt2800_bbp_write(rt2x00dev, 152, value);
3785 4327
3786 /* Init frequency calibration */ 4328 rt2800_init_freq_calibration(rt2x00dev);
3787 rt2800_bbp_write(rt2x00dev, 142, 1);
3788 rt2800_bbp_write(rt2x00dev, 143, 57);
3789 } 4329 }
3790 4330
3791 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 4331 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
@@ -3801,8 +4341,17 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3801 return 0; 4341 return 0;
3802} 4342}
3803 4343
3804static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, 4344static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
3805 bool bw40, u8 rfcsr24, u8 filter_target) 4345{
4346 u32 reg;
4347
4348 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4349 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4350 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4351}
4352
4353static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
4354 u8 filter_target)
3806{ 4355{
3807 unsigned int i; 4356 unsigned int i;
3808 u8 bbp; 4357 u8 bbp;
@@ -3810,6 +4359,7 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3810 u8 passband; 4359 u8 passband;
3811 u8 stopband; 4360 u8 stopband;
3812 u8 overtuned = 0; 4361 u8 overtuned = 0;
4362 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
3813 4363
3814 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24); 4364 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3815 4365
@@ -3865,8 +4415,169 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3865 return rfcsr24; 4415 return rfcsr24;
3866} 4416}
3867 4417
4418static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
4419 const unsigned int rf_reg)
4420{
4421 u8 rfcsr;
4422
4423 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
4424 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
4425 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4426 msleep(1);
4427 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
4428 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4429}
4430
4431static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
4432{
4433 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4434 u8 filter_tgt_bw20;
4435 u8 filter_tgt_bw40;
4436 u8 rfcsr, bbp;
4437
4438 /*
4439 * TODO: sync filter_tgt values with vendor driver
4440 */
4441 if (rt2x00_rt(rt2x00dev, RT3070)) {
4442 filter_tgt_bw20 = 0x16;
4443 filter_tgt_bw40 = 0x19;
4444 } else {
4445 filter_tgt_bw20 = 0x13;
4446 filter_tgt_bw40 = 0x15;
4447 }
4448
4449 drv_data->calibration_bw20 =
4450 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
4451 drv_data->calibration_bw40 =
4452 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
4453
4454 /*
4455 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
4456 */
4457 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4458 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4459
4460 /*
4461 * Set back to initial state
4462 */
4463 rt2800_bbp_write(rt2x00dev, 24, 0);
4464
4465 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4466 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4467 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4468
4469 /*
4470 * Set BBP back to BW20
4471 */
4472 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4473 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4474 rt2800_bbp_write(rt2x00dev, 4, bbp);
4475}
4476
4477static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
4478{
4479 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4480 u8 min_gain, rfcsr, bbp;
4481 u16 eeprom;
4482
4483 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4484
4485 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4486 if (rt2x00_rt(rt2x00dev, RT3070) ||
4487 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4488 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4489 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4490 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
4491 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4492 }
4493
4494 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
4495 if (drv_data->txmixer_gain_24g >= min_gain) {
4496 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4497 drv_data->txmixer_gain_24g);
4498 }
4499
4500 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4501
4502 if (rt2x00_rt(rt2x00dev, RT3090)) {
4503 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4504 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4505 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4506 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4507 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4508 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4509 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4510 rt2800_bbp_write(rt2x00dev, 138, bbp);
4511 }
4512
4513 if (rt2x00_rt(rt2x00dev, RT3070)) {
4514 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4515 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4516 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4517 else
4518 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4519 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4520 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4521 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4522 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4523 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4524 rt2x00_rt(rt2x00dev, RT3090) ||
4525 rt2x00_rt(rt2x00dev, RT3390)) {
4526 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4527 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4528 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4529 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4530 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4531 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4532 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4533
4534 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4535 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4536 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4537
4538 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4539 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4540 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4541
4542 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4543 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4544 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4545 }
4546}
4547
4548static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
4549{
4550 u8 reg;
4551 u16 eeprom;
4552
4553 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4554 rt2800_bbp_read(rt2x00dev, 138, &reg);
4555 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4556 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4557 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
4558 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4559 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
4560 rt2800_bbp_write(rt2x00dev, 138, reg);
4561
4562 rt2800_rfcsr_read(rt2x00dev, 38, &reg);
4563 rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
4564 rt2800_rfcsr_write(rt2x00dev, 38, reg);
4565
4566 rt2800_rfcsr_read(rt2x00dev, 39, &reg);
4567 rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
4568 rt2800_rfcsr_write(rt2x00dev, 39, reg);
4569
4570 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4571
4572 rt2800_rfcsr_read(rt2x00dev, 30, &reg);
4573 rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
4574 rt2800_rfcsr_write(rt2x00dev, 30, reg);
4575}
4576
3868static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) 4577static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
3869{ 4578{
4579 rt2800_rf_init_calibration(rt2x00dev, 30);
4580
3870 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 4581 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3871 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 4582 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3872 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 4583 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
@@ -3903,6 +4614,13 @@ static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
3903 4614
3904static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) 4615static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
3905{ 4616{
4617 u8 rfcsr;
4618 u16 eeprom;
4619 u32 reg;
4620
4621 /* XXX vendor driver do this only for 3070 */
4622 rt2800_rf_init_calibration(rt2x00dev, 30);
4623
3906 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 4624 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3907 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 4625 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3908 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 4626 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
@@ -3922,10 +4640,54 @@ static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
3922 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 4640 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3923 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 4641 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3924 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 4642 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4643
4644 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4645 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4646 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4647 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4648 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4649 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4650 rt2x00_rt(rt2x00dev, RT3090)) {
4651 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4652
4653 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4654 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4655 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4656
4657 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4658 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4659 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4660 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4661 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4662 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4663 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4664 else
4665 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4666 }
4667 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4668
4669 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4670 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4671 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4672 }
4673
4674 rt2800_rx_filter_calibration(rt2x00dev);
4675
4676 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4677 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4678 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
4679 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4680
4681 rt2800_led_open_drain_enable(rt2x00dev);
4682 rt2800_normal_mode_setup_3xxx(rt2x00dev);
3925} 4683}
3926 4684
3927static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) 4685static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
3928{ 4686{
4687 u8 rfcsr;
4688
4689 rt2800_rf_init_calibration(rt2x00dev, 2);
4690
3929 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 4691 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3930 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 4692 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3931 rt2800_rfcsr_write(rt2x00dev, 3, 0x08); 4693 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
@@ -3972,10 +4734,19 @@ static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
3972 rt2800_rfcsr_write(rt2x00dev, 59, 0x09); 4734 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3973 rt2800_rfcsr_write(rt2x00dev, 60, 0x45); 4735 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3974 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); 4736 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4737
4738 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4739 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4740 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4741
4742 rt2800_led_open_drain_enable(rt2x00dev);
4743 rt2800_normal_mode_setup_3xxx(rt2x00dev);
3975} 4744}
3976 4745
3977static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) 4746static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
3978{ 4747{
4748 rt2800_rf_init_calibration(rt2x00dev, 30);
4749
3979 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); 4750 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
3980 rt2800_rfcsr_write(rt2x00dev, 1, 0x23); 4751 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
3981 rt2800_rfcsr_write(rt2x00dev, 2, 0x50); 4752 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
@@ -4039,10 +4810,18 @@ static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4039 rt2800_rfcsr_write(rt2x00dev, 61, 0x00); 4810 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4040 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 4811 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4041 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 4812 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4813
4814 rt2800_rx_filter_calibration(rt2x00dev);
4815 rt2800_led_open_drain_enable(rt2x00dev);
4816 rt2800_normal_mode_setup_3xxx(rt2x00dev);
4042} 4817}
4043 4818
4044static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) 4819static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4045{ 4820{
4821 u32 reg;
4822
4823 rt2800_rf_init_calibration(rt2x00dev, 30);
4824
4046 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); 4825 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4047 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); 4826 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4048 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 4827 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
@@ -4075,10 +4854,27 @@ static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4075 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); 4854 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4076 rt2800_rfcsr_write(rt2x00dev, 30, 0x20); 4855 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4077 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); 4856 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4857
4858 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4859 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4860 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4861
4862 rt2800_rx_filter_calibration(rt2x00dev);
4863
4864 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4865 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4866
4867 rt2800_led_open_drain_enable(rt2x00dev);
4868 rt2800_normal_mode_setup_3xxx(rt2x00dev);
4078} 4869}
4079 4870
4080static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) 4871static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4081{ 4872{
4873 u8 rfcsr;
4874 u32 reg;
4875
4876 rt2800_rf_init_calibration(rt2x00dev, 30);
4877
4082 rt2800_rfcsr_write(rt2x00dev, 0, 0x70); 4878 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4083 rt2800_rfcsr_write(rt2x00dev, 1, 0x81); 4879 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4084 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); 4880 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
@@ -4110,10 +4906,30 @@ static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4110 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); 4906 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4111 rt2800_rfcsr_write(rt2x00dev, 30, 0x09); 4907 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4112 rt2800_rfcsr_write(rt2x00dev, 31, 0x10); 4908 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4909
4910 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4911 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4912 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4913
4914 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4915 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4916 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4917 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4918 msleep(1);
4919 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4920 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4921 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4922 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4923
4924 rt2800_rx_filter_calibration(rt2x00dev);
4925 rt2800_led_open_drain_enable(rt2x00dev);
4926 rt2800_normal_mode_setup_3xxx(rt2x00dev);
4113} 4927}
4114 4928
4115static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) 4929static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4116{ 4930{
4931 rt2800_rf_init_calibration(rt2x00dev, 2);
4932
4117 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 4933 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4118 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 4934 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4119 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 4935 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
@@ -4194,10 +5010,16 @@ static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4194 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); 5010 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4195 rt2800_rfcsr_write(rt2x00dev, 62, 0x00); 5011 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4196 rt2800_rfcsr_write(rt2x00dev, 63, 0x00); 5012 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
5013
5014 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5015
5016 rt2800_led_open_drain_enable(rt2x00dev);
4197} 5017}
4198 5018
4199static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) 5019static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4200{ 5020{
5021 rt2800_rf_init_calibration(rt2x00dev, 2);
5022
4201 rt2800_rfcsr_write(rt2x00dev, 1, 0x17); 5023 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4202 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 5024 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4203 rt2800_rfcsr_write(rt2x00dev, 3, 0x88); 5025 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
@@ -4257,53 +5079,61 @@ static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
4257 rt2800_rfcsr_write(rt2x00dev, 61, 0x91); 5079 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4258 rt2800_rfcsr_write(rt2x00dev, 62, 0x39); 5080 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4259 rt2800_rfcsr_write(rt2x00dev, 63, 0x07); 5081 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
5082
5083 rt2800_normal_mode_setup_5xxx(rt2x00dev);
5084
5085 rt2800_led_open_drain_enable(rt2x00dev);
4260} 5086}
4261 5087
4262static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) 5088static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
4263{ 5089{
4264 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; 5090 rt2800_rf_init_calibration(rt2x00dev, 30);
4265 u8 rfcsr;
4266 u8 bbp;
4267 u32 reg;
4268 u16 eeprom;
4269 5091
4270 if (!rt2x00_rt(rt2x00dev, RT3070) && 5092 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
4271 !rt2x00_rt(rt2x00dev, RT3071) && 5093 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4272 !rt2x00_rt(rt2x00dev, RT3090) && 5094 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4273 !rt2x00_rt(rt2x00dev, RT3290) && 5095 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4274 !rt2x00_rt(rt2x00dev, RT3352) && 5096 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
4275 !rt2x00_rt(rt2x00dev, RT3390) && 5097 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4276 !rt2x00_rt(rt2x00dev, RT3572) && 5098 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4277 !rt2x00_rt(rt2x00dev, RT5390) && 5099 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4278 !rt2x00_rt(rt2x00dev, RT5392) && 5100 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4279 !rt2800_is_305x_soc(rt2x00dev)) 5101 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4280 return 0; 5102 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
5103 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
5104 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
5105 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5106 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5107 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5108 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5109 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5110 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5111 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
5112 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
5113 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4281 5114
4282 /* 5115 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4283 * Init RF calibration. 5116 msleep(1);
4284 */
4285 5117
4286 if (rt2x00_rt(rt2x00dev, RT3290) || 5118 rt2800_adjust_freq_offset(rt2x00dev);
4287 rt2x00_rt(rt2x00dev, RT5390) || 5119
4288 rt2x00_rt(rt2x00dev, RT5392)) { 5120 /* Enable DC filter */
4289 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); 5121 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4290 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); 5122 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4291 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 5123
4292 msleep(1); 5124 rt2800_normal_mode_setup_5xxx(rt2x00dev);
4293 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0); 5125
4294 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); 5126 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
4295 } else { 5127 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4296 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4297 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
4298 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4299 msleep(1);
4300 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
4301 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4302 }
4303 5128
5129 rt2800_led_open_drain_enable(rt2x00dev);
5130}
5131
5132static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
5133{
4304 if (rt2800_is_305x_soc(rt2x00dev)) { 5134 if (rt2800_is_305x_soc(rt2x00dev)) {
4305 rt2800_init_rfcsr_305x_soc(rt2x00dev); 5135 rt2800_init_rfcsr_305x_soc(rt2x00dev);
4306 return 0; 5136 return;
4307 } 5137 }
4308 5138
4309 switch (rt2x00dev->chip.rt) { 5139 switch (rt2x00dev->chip.rt) {
@@ -4330,198 +5160,10 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4330 case RT5392: 5160 case RT5392:
4331 rt2800_init_rfcsr_5392(rt2x00dev); 5161 rt2800_init_rfcsr_5392(rt2x00dev);
4332 break; 5162 break;
5163 case RT5592:
5164 rt2800_init_rfcsr_5592(rt2x00dev);
5165 break;
4333 } 5166 }
4334
4335 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4336 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4337 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4338 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4339 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4340 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4341 rt2x00_rt(rt2x00dev, RT3090)) {
4342 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4343
4344 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4345 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4346 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4347
4348 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4349 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4350 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4351 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4352 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4353 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4354 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4355 else
4356 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4357 }
4358 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4359
4360 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4361 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4362 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4363 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4364 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4365 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4366 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4367 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4368 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4369 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4370 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4371
4372 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4373 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4374 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4375 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4376 msleep(1);
4377 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4378 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4379 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4380 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4381 }
4382
4383 /*
4384 * Set RX Filter calibration for 20MHz and 40MHz
4385 */
4386 if (rt2x00_rt(rt2x00dev, RT3070)) {
4387 drv_data->calibration_bw20 =
4388 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4389 drv_data->calibration_bw40 =
4390 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4391 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4392 rt2x00_rt(rt2x00dev, RT3090) ||
4393 rt2x00_rt(rt2x00dev, RT3352) ||
4394 rt2x00_rt(rt2x00dev, RT3390) ||
4395 rt2x00_rt(rt2x00dev, RT3572)) {
4396 drv_data->calibration_bw20 =
4397 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4398 drv_data->calibration_bw40 =
4399 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4400 }
4401
4402 /*
4403 * Save BBP 25 & 26 values for later use in channel switching
4404 */
4405 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4406 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4407
4408 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4409 !rt2x00_rt(rt2x00dev, RT5392)) {
4410 /*
4411 * Set back to initial state
4412 */
4413 rt2800_bbp_write(rt2x00dev, 24, 0);
4414
4415 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4416 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4417 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4418
4419 /*
4420 * Set BBP back to BW20
4421 */
4422 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4423 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4424 rt2800_bbp_write(rt2x00dev, 4, bbp);
4425 }
4426
4427 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4428 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4429 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4430 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4431 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4432
4433 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4434 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4435 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4436
4437 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4438 !rt2x00_rt(rt2x00dev, RT5392)) {
4439 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4440 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4441 if (rt2x00_rt(rt2x00dev, RT3070) ||
4442 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4443 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4444 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4445 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4446 &rt2x00dev->cap_flags))
4447 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4448 }
4449 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4450 drv_data->txmixer_gain_24g);
4451 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4452 }
4453
4454 if (rt2x00_rt(rt2x00dev, RT3090)) {
4455 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4456
4457 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4458 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4459 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4460 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4461 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4462 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4463
4464 rt2800_bbp_write(rt2x00dev, 138, bbp);
4465 }
4466
4467 if (rt2x00_rt(rt2x00dev, RT3071) ||
4468 rt2x00_rt(rt2x00dev, RT3090) ||
4469 rt2x00_rt(rt2x00dev, RT3390)) {
4470 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4471 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4472 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4473 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4474 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4475 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4476 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4477
4478 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4479 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4480 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4481
4482 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4483 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4484 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4485
4486 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4487 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4488 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4489 }
4490
4491 if (rt2x00_rt(rt2x00dev, RT3070)) {
4492 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4493 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4494 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4495 else
4496 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4497 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4498 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4499 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4500 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4501 }
4502
4503 if (rt2x00_rt(rt2x00dev, RT3290)) {
4504 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4505 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4506 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4507 }
4508
4509 if (rt2x00_rt(rt2x00dev, RT5390) ||
4510 rt2x00_rt(rt2x00dev, RT5392)) {
4511 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4512 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4513 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
4514
4515 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4516 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4517 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
4518
4519 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4520 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4521 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4522 }
4523
4524 return 0;
4525} 5167}
4526 5168
4527int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) 5169int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
@@ -4533,15 +5175,24 @@ int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4533 * Initialize all registers. 5175 * Initialize all registers.
4534 */ 5176 */
4535 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) || 5177 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4536 rt2800_init_registers(rt2x00dev) || 5178 rt2800_init_registers(rt2x00dev)))
4537 rt2800_init_bbp(rt2x00dev) ||
4538 rt2800_init_rfcsr(rt2x00dev)))
4539 return -EIO; 5179 return -EIO;
4540 5180
4541 /* 5181 /*
4542 * Send signal to firmware during boot time. 5182 * Send signal to firmware during boot time.
4543 */ 5183 */
4544 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0); 5184 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5185 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5186 if (rt2x00_is_usb(rt2x00dev)) {
5187 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
5188 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5189 }
5190 msleep(1);
5191
5192 if (unlikely(rt2800_init_bbp(rt2x00dev)))
5193 return -EIO;
5194
5195 rt2800_init_rfcsr(rt2x00dev);
4545 5196
4546 if (rt2x00_is_usb(rt2x00dev) && 5197 if (rt2x00_is_usb(rt2x00dev) &&
4547 (rt2x00_rt(rt2x00dev, RT3070) || 5198 (rt2x00_rt(rt2x00dev, RT3070) ||
@@ -4702,7 +5353,7 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4702 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); 5353 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4703 if (!is_valid_ether_addr(mac)) { 5354 if (!is_valid_ether_addr(mac)) {
4704 eth_random_addr(mac); 5355 eth_random_addr(mac);
4705 EEPROM(rt2x00dev, "MAC: %pM\n", mac); 5356 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
4706 } 5357 }
4707 5358
4708 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word); 5359 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
@@ -4711,7 +5362,7 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4711 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1); 5362 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4712 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820); 5363 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4713 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word); 5364 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4714 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); 5365 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
4715 } else if (rt2x00_rt(rt2x00dev, RT2860) || 5366 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
4716 rt2x00_rt(rt2x00dev, RT2872)) { 5367 rt2x00_rt(rt2x00dev, RT2872)) {
4717 /* 5368 /*
@@ -4740,14 +5391,14 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4740 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0); 5391 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4741 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0); 5392 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4742 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word); 5393 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
4743 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word); 5394 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
4744 } 5395 }
4745 5396
4746 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word); 5397 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4747 if ((word & 0x00ff) == 0x00ff) { 5398 if ((word & 0x00ff) == 0x00ff) {
4748 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0); 5399 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
4749 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); 5400 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4750 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word); 5401 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
4751 } 5402 }
4752 if ((word & 0xff00) == 0xff00) { 5403 if ((word & 0xff00) == 0xff00) {
4753 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE, 5404 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
@@ -4757,7 +5408,7 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4757 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555); 5408 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4758 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221); 5409 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4759 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8); 5410 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
4760 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word); 5411 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
4761 } 5412 }
4762 5413
4763 /* 5414 /*
@@ -4821,9 +5472,9 @@ static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4821 5472
4822static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) 5473static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4823{ 5474{
4824 u32 reg;
4825 u16 value; 5475 u16 value;
4826 u16 eeprom; 5476 u16 eeprom;
5477 u16 rf;
4827 5478
4828 /* 5479 /*
4829 * Read EEPROM word for configuration. 5480 * Read EEPROM word for configuration.
@@ -4835,41 +5486,14 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4835 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field 5486 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4836 * RT53xx: defined in "EEPROM_CHIP_ID" field 5487 * RT53xx: defined in "EEPROM_CHIP_ID" field
4837 */ 5488 */
4838 if (rt2x00_rt(rt2x00dev, RT3290)) 5489 if (rt2x00_rt(rt2x00dev, RT3290) ||
4839 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg); 5490 rt2x00_rt(rt2x00dev, RT5390) ||
4840 else 5491 rt2x00_rt(rt2x00dev, RT5392))
4841 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg); 5492 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
4842
4843 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4844 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4845 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4846 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4847 else 5493 else
4848 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); 5494 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4849 5495
4850 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), 5496 switch (rf) {
4851 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4852
4853 switch (rt2x00dev->chip.rt) {
4854 case RT2860:
4855 case RT2872:
4856 case RT2883:
4857 case RT3070:
4858 case RT3071:
4859 case RT3090:
4860 case RT3290:
4861 case RT3352:
4862 case RT3390:
4863 case RT3572:
4864 case RT5390:
4865 case RT5392:
4866 break;
4867 default:
4868 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
4869 return -ENODEV;
4870 }
4871
4872 switch (rt2x00dev->chip.rf) {
4873 case RF2820: 5497 case RF2820:
4874 case RF2850: 5498 case RF2850:
4875 case RF2720: 5499 case RF2720:
@@ -4887,13 +5511,16 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4887 case RF5372: 5511 case RF5372:
4888 case RF5390: 5512 case RF5390:
4889 case RF5392: 5513 case RF5392:
5514 case RF5592:
4890 break; 5515 break;
4891 default: 5516 default:
4892 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n", 5517 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
4893 rt2x00dev->chip.rf); 5518 rf);
4894 return -ENODEV; 5519 return -ENODEV;
4895 } 5520 }
4896 5521
5522 rt2x00_set_rf(rt2x00dev, rf);
5523
4897 /* 5524 /*
4898 * Identify default antenna configuration. 5525 * Identify default antenna configuration.
4899 */ 5526 */
@@ -5122,6 +5749,138 @@ static const struct rf_channel rf_vals_3x[] = {
5122 {173, 0x61, 0, 9}, 5749 {173, 0x61, 0, 9},
5123}; 5750};
5124 5751
5752static const struct rf_channel rf_vals_5592_xtal20[] = {
5753 /* Channel, N, K, mod, R */
5754 {1, 482, 4, 10, 3},
5755 {2, 483, 4, 10, 3},
5756 {3, 484, 4, 10, 3},
5757 {4, 485, 4, 10, 3},
5758 {5, 486, 4, 10, 3},
5759 {6, 487, 4, 10, 3},
5760 {7, 488, 4, 10, 3},
5761 {8, 489, 4, 10, 3},
5762 {9, 490, 4, 10, 3},
5763 {10, 491, 4, 10, 3},
5764 {11, 492, 4, 10, 3},
5765 {12, 493, 4, 10, 3},
5766 {13, 494, 4, 10, 3},
5767 {14, 496, 8, 10, 3},
5768 {36, 172, 8, 12, 1},
5769 {38, 173, 0, 12, 1},
5770 {40, 173, 4, 12, 1},
5771 {42, 173, 8, 12, 1},
5772 {44, 174, 0, 12, 1},
5773 {46, 174, 4, 12, 1},
5774 {48, 174, 8, 12, 1},
5775 {50, 175, 0, 12, 1},
5776 {52, 175, 4, 12, 1},
5777 {54, 175, 8, 12, 1},
5778 {56, 176, 0, 12, 1},
5779 {58, 176, 4, 12, 1},
5780 {60, 176, 8, 12, 1},
5781 {62, 177, 0, 12, 1},
5782 {64, 177, 4, 12, 1},
5783 {100, 183, 4, 12, 1},
5784 {102, 183, 8, 12, 1},
5785 {104, 184, 0, 12, 1},
5786 {106, 184, 4, 12, 1},
5787 {108, 184, 8, 12, 1},
5788 {110, 185, 0, 12, 1},
5789 {112, 185, 4, 12, 1},
5790 {114, 185, 8, 12, 1},
5791 {116, 186, 0, 12, 1},
5792 {118, 186, 4, 12, 1},
5793 {120, 186, 8, 12, 1},
5794 {122, 187, 0, 12, 1},
5795 {124, 187, 4, 12, 1},
5796 {126, 187, 8, 12, 1},
5797 {128, 188, 0, 12, 1},
5798 {130, 188, 4, 12, 1},
5799 {132, 188, 8, 12, 1},
5800 {134, 189, 0, 12, 1},
5801 {136, 189, 4, 12, 1},
5802 {138, 189, 8, 12, 1},
5803 {140, 190, 0, 12, 1},
5804 {149, 191, 6, 12, 1},
5805 {151, 191, 10, 12, 1},
5806 {153, 192, 2, 12, 1},
5807 {155, 192, 6, 12, 1},
5808 {157, 192, 10, 12, 1},
5809 {159, 193, 2, 12, 1},
5810 {161, 193, 6, 12, 1},
5811 {165, 194, 2, 12, 1},
5812 {184, 164, 0, 12, 1},
5813 {188, 164, 4, 12, 1},
5814 {192, 165, 8, 12, 1},
5815 {196, 166, 0, 12, 1},
5816};
5817
5818static const struct rf_channel rf_vals_5592_xtal40[] = {
5819 /* Channel, N, K, mod, R */
5820 {1, 241, 2, 10, 3},
5821 {2, 241, 7, 10, 3},
5822 {3, 242, 2, 10, 3},
5823 {4, 242, 7, 10, 3},
5824 {5, 243, 2, 10, 3},
5825 {6, 243, 7, 10, 3},
5826 {7, 244, 2, 10, 3},
5827 {8, 244, 7, 10, 3},
5828 {9, 245, 2, 10, 3},
5829 {10, 245, 7, 10, 3},
5830 {11, 246, 2, 10, 3},
5831 {12, 246, 7, 10, 3},
5832 {13, 247, 2, 10, 3},
5833 {14, 248, 4, 10, 3},
5834 {36, 86, 4, 12, 1},
5835 {38, 86, 6, 12, 1},
5836 {40, 86, 8, 12, 1},
5837 {42, 86, 10, 12, 1},
5838 {44, 87, 0, 12, 1},
5839 {46, 87, 2, 12, 1},
5840 {48, 87, 4, 12, 1},
5841 {50, 87, 6, 12, 1},
5842 {52, 87, 8, 12, 1},
5843 {54, 87, 10, 12, 1},
5844 {56, 88, 0, 12, 1},
5845 {58, 88, 2, 12, 1},
5846 {60, 88, 4, 12, 1},
5847 {62, 88, 6, 12, 1},
5848 {64, 88, 8, 12, 1},
5849 {100, 91, 8, 12, 1},
5850 {102, 91, 10, 12, 1},
5851 {104, 92, 0, 12, 1},
5852 {106, 92, 2, 12, 1},
5853 {108, 92, 4, 12, 1},
5854 {110, 92, 6, 12, 1},
5855 {112, 92, 8, 12, 1},
5856 {114, 92, 10, 12, 1},
5857 {116, 93, 0, 12, 1},
5858 {118, 93, 2, 12, 1},
5859 {120, 93, 4, 12, 1},
5860 {122, 93, 6, 12, 1},
5861 {124, 93, 8, 12, 1},
5862 {126, 93, 10, 12, 1},
5863 {128, 94, 0, 12, 1},
5864 {130, 94, 2, 12, 1},
5865 {132, 94, 4, 12, 1},
5866 {134, 94, 6, 12, 1},
5867 {136, 94, 8, 12, 1},
5868 {138, 94, 10, 12, 1},
5869 {140, 95, 0, 12, 1},
5870 {149, 95, 9, 12, 1},
5871 {151, 95, 11, 12, 1},
5872 {153, 96, 1, 12, 1},
5873 {155, 96, 3, 12, 1},
5874 {157, 96, 5, 12, 1},
5875 {159, 96, 7, 12, 1},
5876 {161, 96, 9, 12, 1},
5877 {165, 97, 1, 12, 1},
5878 {184, 82, 0, 12, 1},
5879 {188, 82, 4, 12, 1},
5880 {192, 82, 8, 12, 1},
5881 {196, 83, 0, 12, 1},
5882};
5883
5125static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 5884static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5126{ 5885{
5127 struct hw_mode_spec *spec = &rt2x00dev->spec; 5886 struct hw_mode_spec *spec = &rt2x00dev->spec;
@@ -5130,6 +5889,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5130 char *default_power2; 5889 char *default_power2;
5131 unsigned int i; 5890 unsigned int i;
5132 u16 eeprom; 5891 u16 eeprom;
5892 u32 reg;
5133 5893
5134 /* 5894 /*
5135 * Disable powersaving as default on PCI devices. 5895 * Disable powersaving as default on PCI devices.
@@ -5211,8 +5971,22 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5211 spec->supported_bands |= SUPPORT_BAND_5GHZ; 5971 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5212 spec->num_channels = ARRAY_SIZE(rf_vals_3x); 5972 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5213 spec->channels = rf_vals_3x; 5973 spec->channels = rf_vals_3x;
5974 } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5975 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5976
5977 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5978 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5979 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5980 spec->channels = rf_vals_5592_xtal40;
5981 } else {
5982 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5983 spec->channels = rf_vals_5592_xtal20;
5984 }
5214 } 5985 }
5215 5986
5987 if (WARN_ON_ONCE(!spec->channels))
5988 return -ENODEV;
5989
5216 /* 5990 /*
5217 * Initialize HT information. 5991 * Initialize HT information.
5218 */ 5992 */
@@ -5300,11 +6074,55 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5300 return 0; 6074 return 0;
5301} 6075}
5302 6076
6077static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
6078{
6079 u32 reg;
6080 u32 rt;
6081 u32 rev;
6082
6083 if (rt2x00_rt(rt2x00dev, RT3290))
6084 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
6085 else
6086 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
6087
6088 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
6089 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
6090
6091 switch (rt) {
6092 case RT2860:
6093 case RT2872:
6094 case RT2883:
6095 case RT3070:
6096 case RT3071:
6097 case RT3090:
6098 case RT3290:
6099 case RT3352:
6100 case RT3390:
6101 case RT3572:
6102 case RT5390:
6103 case RT5392:
6104 case RT5592:
6105 break;
6106 default:
6107 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
6108 rt, rev);
6109 return -ENODEV;
6110 }
6111
6112 rt2x00_set_rt(rt2x00dev, rt, rev);
6113
6114 return 0;
6115}
6116
5303int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) 6117int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5304{ 6118{
5305 int retval; 6119 int retval;
5306 u32 reg; 6120 u32 reg;
5307 6121
6122 retval = rt2800_probe_rt(rt2x00dev);
6123 if (retval)
6124 return retval;
6125
5308 /* 6126 /*
5309 * Allocate eeprom data. 6127 * Allocate eeprom data.
5310 */ 6128 */
@@ -5546,7 +6364,8 @@ int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5546 case IEEE80211_AMPDU_TX_OPERATIONAL: 6364 case IEEE80211_AMPDU_TX_OPERATIONAL:
5547 break; 6365 break;
5548 default: 6366 default:
5549 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n"); 6367 rt2x00_warn((struct rt2x00_dev *)hw->priv,
6368 "Unknown AMPDU action\n");
5550 } 6369 }
5551 6370
5552 return ret; 6371 return ret;
@@ -5563,7 +6382,7 @@ int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
5563 if (idx != 0) 6382 if (idx != 0)
5564 return -ENOENT; 6383 return -ENOENT;
5565 6384
5566 survey->channel = conf->channel; 6385 survey->channel = conf->chandef.chan;
5567 6386
5568 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); 6387 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
5569 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); 6388 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 04:48:06 -0500