1 files changed, 172 insertions, 1 deletions

diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 1ca88cdc6ece..e252e9bafd0e 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -68,6 +68,7 @@
 #define RF3320                          0x000b
 #define RF3322                          0x000c
 #define RF3053                          0x000d
+#define RF3290                          0x3290
 #define RF5360                          0x5360
 #define RF5370                          0x5370
 #define RF5372                          0x5372
@@ -117,6 +118,12 @@
  * Registers.
  */
 
+
+/*
+ * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number.
+ */
+#define MAC_CSR0_3290                           0x0000
+
 /*
  * E2PROM_CSR: PCI EEPROM control register.
  * RELOAD: Write 1 to reload eeprom content.
@@ -133,6 +140,150 @@
 #define E2PROM_CSR_RELOAD               FIELD32(0x00000080)
 
 /*
+ * CMB_CTRL_CFG
+ */
+#define CMB_CTRL                0x0020
+#define AUX_OPT_BIT0            FIELD32(0x00000001)
+#define AUX_OPT_BIT1            FIELD32(0x00000002)
+#define AUX_OPT_BIT2            FIELD32(0x00000004)
+#define AUX_OPT_BIT3            FIELD32(0x00000008)
+#define AUX_OPT_BIT4            FIELD32(0x00000010)
+#define AUX_OPT_BIT5            FIELD32(0x00000020)
+#define AUX_OPT_BIT6            FIELD32(0x00000040)
+#define AUX_OPT_BIT7            FIELD32(0x00000080)
+#define AUX_OPT_BIT8            FIELD32(0x00000100)
+#define AUX_OPT_BIT9            FIELD32(0x00000200)
+#define AUX_OPT_BIT10           FIELD32(0x00000400)
+#define AUX_OPT_BIT11           FIELD32(0x00000800)
+#define AUX_OPT_BIT12           FIELD32(0x00001000)
+#define AUX_OPT_BIT13           FIELD32(0x00002000)
+#define AUX_OPT_BIT14           FIELD32(0x00004000)
+#define AUX_OPT_BIT15           FIELD32(0x00008000)
+#define LDO25_LEVEL             FIELD32(0x00030000)
+#define LDO25_LARGEA            FIELD32(0x00040000)
+#define LDO25_FRC_ON            FIELD32(0x00080000)
+#define CMB_RSV                 FIELD32(0x00300000)
+#define XTAL_RDY                FIELD32(0x00400000)
+#define PLL_LD                  FIELD32(0x00800000)
+#define LDO_CORE_LEVEL          FIELD32(0x0F000000)
+#define LDO_BGSEL               FIELD32(0x30000000)
+#define LDO3_EN                 FIELD32(0x40000000)
+#define LDO0_EN                 FIELD32(0x80000000)
+
+/*
+ * EFUSE_CSR_3290: RT3290 EEPROM
+ */
+#define EFUSE_CTRL_3290                 0x0024
+
+/*
+ * EFUSE_DATA3 of 3290
+ */
+#define EFUSE_DATA3_3290                0x0028
+
+/*
+ * EFUSE_DATA2 of 3290
+ */
+#define EFUSE_DATA2_3290                0x002c
+
+/*
+ * EFUSE_DATA1 of 3290
+ */
+#define EFUSE_DATA1_3290                0x0030
+
+/*
+ * EFUSE_DATA0 of 3290
+ */
+#define EFUSE_DATA0_3290                0x0034
+
+/*
+ * OSC_CTRL_CFG
+ * Ring oscillator configuration
+ */
+#define OSC_CTRL                0x0038
+#define OSC_REF_CYCLE           FIELD32(0x00001fff)
+#define OSC_RSV                 FIELD32(0x0000e000)
+#define OSC_CAL_CNT             FIELD32(0x0fff0000)
+#define OSC_CAL_ACK             FIELD32(0x10000000)
+#define OSC_CLK_32K_VLD         FIELD32(0x20000000)
+#define OSC_CAL_REQ             FIELD32(0x40000000)
+#define OSC_ROSC_EN             FIELD32(0x80000000)
+
+/*
+ * COEX_CFG_0
+ */
+#define COEX_CFG0                       0x0040
+#define COEX_CFG_ANT            FIELD32(0xff000000)
+/*
+ * COEX_CFG_1
+ */
+#define COEX_CFG1                       0x0044
+
+/*
+ * COEX_CFG_2
+ */
+#define COEX_CFG2                       0x0048
+#define BT_COEX_CFG1            FIELD32(0xff000000)
+#define BT_COEX_CFG0            FIELD32(0x00ff0000)
+#define WL_COEX_CFG1            FIELD32(0x0000ff00)
+#define WL_COEX_CFG0            FIELD32(0x000000ff)
+/*
+ * PLL_CTRL_CFG
+ * PLL configuration register
+ */
+#define PLL_CTRL                0x0050
+#define PLL_RESERVED_INPUT1     FIELD32(0x000000ff)
+#define PLL_RESERVED_INPUT2     FIELD32(0x0000ff00)
+#define PLL_CONTROL             FIELD32(0x00070000)
+#define PLL_LPF_R1              FIELD32(0x00080000)
+#define PLL_LPF_C1_CTRL FIELD32(0x00300000)
+#define PLL_LPF_C2_CTRL FIELD32(0x00c00000)
+#define PLL_CP_CURRENT_CTRL     FIELD32(0x03000000)
+#define PLL_PFD_DELAY_CTRL      FIELD32(0x0c000000)
+#define PLL_LOCK_CTRL           FIELD32(0x70000000)
+#define PLL_VBGBK_EN            FIELD32(0x80000000)
+
+
+/*
+ * WLAN_CTRL_CFG
+ * RT3290 wlan configuration
+ */
+#define WLAN_FUN_CTRL                   0x0080
+#define WLAN_EN                         FIELD32(0x00000001)
+#define WLAN_CLK_EN                     FIELD32(0x00000002)
+#define WLAN_RSV1                       FIELD32(0x00000004)
+#define WLAN_RESET                      FIELD32(0x00000008)
+#define PCIE_APP0_CLK_REQ               FIELD32(0x00000010)
+#define FRC_WL_ANT_SET                  FIELD32(0x00000020)
+#define INV_TR_SW0                      FIELD32(0x00000040)
+#define WLAN_GPIO_IN_BIT0               FIELD32(0x00000100)
+#define WLAN_GPIO_IN_BIT1               FIELD32(0x00000200)
+#define WLAN_GPIO_IN_BIT2               FIELD32(0x00000400)
+#define WLAN_GPIO_IN_BIT3               FIELD32(0x00000800)
+#define WLAN_GPIO_IN_BIT4               FIELD32(0x00001000)
+#define WLAN_GPIO_IN_BIT5               FIELD32(0x00002000)
+#define WLAN_GPIO_IN_BIT6               FIELD32(0x00004000)
+#define WLAN_GPIO_IN_BIT7               FIELD32(0x00008000)
+#define WLAN_GPIO_IN_BIT_ALL            FIELD32(0x0000ff00)
+#define WLAN_GPIO_OUT_BIT0              FIELD32(0x00010000)
+#define WLAN_GPIO_OUT_BIT1              FIELD32(0x00020000)
+#define WLAN_GPIO_OUT_BIT2              FIELD32(0x00040000)
+#define WLAN_GPIO_OUT_BIT3              FIELD32(0x00050000)
+#define WLAN_GPIO_OUT_BIT4              FIELD32(0x00100000)
+#define WLAN_GPIO_OUT_BIT5              FIELD32(0x00200000)
+#define WLAN_GPIO_OUT_BIT6              FIELD32(0x00400000)
+#define WLAN_GPIO_OUT_BIT7              FIELD32(0x00800000)
+#define WLAN_GPIO_OUT_BIT_ALL           FIELD32(0x00ff0000)
+#define WLAN_GPIO_OUT_OE_BIT0           FIELD32(0x01000000)
+#define WLAN_GPIO_OUT_OE_BIT1           FIELD32(0x02000000)
+#define WLAN_GPIO_OUT_OE_BIT2           FIELD32(0x04000000)
+#define WLAN_GPIO_OUT_OE_BIT3           FIELD32(0x08000000)
+#define WLAN_GPIO_OUT_OE_BIT4           FIELD32(0x10000000)
+#define WLAN_GPIO_OUT_OE_BIT5           FIELD32(0x20000000)
+#define WLAN_GPIO_OUT_OE_BIT6           FIELD32(0x40000000)
+#define WLAN_GPIO_OUT_OE_BIT7           FIELD32(0x80000000)
+#define WLAN_GPIO_OUT_OE_BIT_ALL        FIELD32(0xff000000)
+
+/*
  * AUX_CTRL: Aux/PCI-E related configuration
  */
 #define AUX_CTRL                        0x10c
@@ -1763,9 +1914,11 @@ struct mac_iveiv_entry {
 /*
  * BBP 3: RX Antenna
  */
-#define BBP3_RX_ADC                             FIELD8(0x03)
+#define BBP3_RX_ADC                     FIELD8(0x03)
 #define BBP3_RX_ANTENNA                 FIELD8(0x18)
 #define BBP3_HT40_MINUS                 FIELD8(0x20)
+#define BBP3_ADC_MODE_SWITCH            FIELD8(0x40)
+#define BBP3_ADC_INIT_MODE              FIELD8(0x80)
 
 /*
  * BBP 4: Bandwidth
@@ -1775,6 +1928,14 @@ struct mac_iveiv_entry {
 #define BBP4_MAC_IF_CTRL                FIELD8(0x40)
 
 /*
+ * BBP 47: Bandwidth
+ */
+#define BBP47_TSSI_REPORT_SEL           FIELD8(0x03)
+#define BBP47_TSSI_UPDATE_REQ           FIELD8(0x04)
+#define BBP47_TSSI_TSSI_MODE            FIELD8(0x18)
+#define BBP47_TSSI_ADC6                 FIELD8(0x80)
+
+/*
  * BBP 109
  */
 #define BBP109_TX0_POWER                FIELD8(0x0f)
@@ -1917,6 +2078,16 @@ struct mac_iveiv_entry {
 #define RFCSR27_R4                      FIELD8(0x40)
 
 /*
+ * RFCSR 29:
+ */
+#define RFCSR29_ADC6_TEST               FIELD8(0x01)
+#define RFCSR29_ADC6_INT_TEST           FIELD8(0x02)
+#define RFCSR29_RSSI_RESET              FIELD8(0x04)
+#define RFCSR29_RSSI_ON                 FIELD8(0x08)
+#define RFCSR29_RSSI_RIP_CTRL           FIELD8(0x30)
+#define RFCSR29_RSSI_GAIN               FIELD8(0xc0)
+
+/*
  * RFCSR 30:
  */
 #define RFCSR30_TX_H20M                 FIELD8(0x02)