diff options
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2500pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2500pci.c | 179 |
1 files changed, 122 insertions, 57 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c index a9ff26a27724..58277878889e 100644 --- a/drivers/net/wireless/rt2x00/rt2500pci.c +++ b/drivers/net/wireless/rt2x00/rt2500pci.c | |||
@@ -293,7 +293,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, | |||
293 | struct rt2x00intf_conf *conf, | 293 | struct rt2x00intf_conf *conf, |
294 | const unsigned int flags) | 294 | const unsigned int flags) |
295 | { | 295 | { |
296 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON); | 296 | struct data_queue *queue = rt2x00dev->bcn; |
297 | unsigned int bcn_preload; | 297 | unsigned int bcn_preload; |
298 | u32 reg; | 298 | u32 reg; |
299 | 299 | ||
@@ -311,9 +311,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev, | |||
311 | * Enable synchronisation. | 311 | * Enable synchronisation. |
312 | */ | 312 | */ |
313 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | 313 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
314 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); | ||
315 | rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); | 314 | rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); |
316 | rt2x00_set_field32(®, CSR14_TBCN, 1); | ||
317 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | 315 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
318 | } | 316 | } |
319 | 317 | ||
@@ -737,6 +735,11 @@ static void rt2500pci_start_queue(struct data_queue *queue) | |||
737 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | 735 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); |
738 | break; | 736 | break; |
739 | case QID_BEACON: | 737 | case QID_BEACON: |
738 | /* | ||
739 | * Allow the tbtt tasklet to be scheduled. | ||
740 | */ | ||
741 | tasklet_enable(&rt2x00dev->tbtt_tasklet); | ||
742 | |||
740 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | 743 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
741 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); | 744 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
742 | rt2x00_set_field32(®, CSR14_TBCN, 1); | 745 | rt2x00_set_field32(®, CSR14_TBCN, 1); |
@@ -798,6 +801,11 @@ static void rt2500pci_stop_queue(struct data_queue *queue) | |||
798 | rt2x00_set_field32(®, CSR14_TBCN, 0); | 801 | rt2x00_set_field32(®, CSR14_TBCN, 0); |
799 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | 802 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); |
800 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | 803 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
804 | |||
805 | /* | ||
806 | * Wait for possibly running tbtt tasklets. | ||
807 | */ | ||
808 | tasklet_disable(&rt2x00dev->tbtt_tasklet); | ||
801 | break; | 809 | break; |
802 | default: | 810 | default: |
803 | break; | 811 | break; |
@@ -857,7 +865,7 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) | |||
857 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); | 865 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); |
858 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); | 866 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); |
859 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); | 867 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); |
860 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); | 868 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); |
861 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); | 869 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
862 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); | 870 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
863 | 871 | ||
@@ -873,13 +881,13 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) | |||
873 | entry_priv->desc_dma); | 881 | entry_priv->desc_dma); |
874 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); | 882 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
875 | 883 | ||
876 | entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; | 884 | entry_priv = rt2x00dev->atim->entries[0].priv_data; |
877 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); | 885 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
878 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, | 886 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
879 | entry_priv->desc_dma); | 887 | entry_priv->desc_dma); |
880 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); | 888 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
881 | 889 | ||
882 | entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; | 890 | entry_priv = rt2x00dev->bcn->entries[0].priv_data; |
883 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); | 891 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
884 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, | 892 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
885 | entry_priv->desc_dma); | 893 | entry_priv->desc_dma); |
@@ -1118,9 +1126,9 @@ static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) | |||
1118 | static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, | 1126 | static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
1119 | enum dev_state state) | 1127 | enum dev_state state) |
1120 | { | 1128 | { |
1121 | int mask = (state == STATE_RADIO_IRQ_OFF) || | 1129 | int mask = (state == STATE_RADIO_IRQ_OFF); |
1122 | (state == STATE_RADIO_IRQ_OFF_ISR); | ||
1123 | u32 reg; | 1130 | u32 reg; |
1131 | unsigned long flags; | ||
1124 | 1132 | ||
1125 | /* | 1133 | /* |
1126 | * When interrupts are being enabled, the interrupt registers | 1134 | * When interrupts are being enabled, the interrupt registers |
@@ -1129,12 +1137,20 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, | |||
1129 | if (state == STATE_RADIO_IRQ_ON) { | 1137 | if (state == STATE_RADIO_IRQ_ON) { |
1130 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); | 1138 | rt2x00pci_register_read(rt2x00dev, CSR7, ®); |
1131 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); | 1139 | rt2x00pci_register_write(rt2x00dev, CSR7, reg); |
1140 | |||
1141 | /* | ||
1142 | * Enable tasklets. | ||
1143 | */ | ||
1144 | tasklet_enable(&rt2x00dev->txstatus_tasklet); | ||
1145 | tasklet_enable(&rt2x00dev->rxdone_tasklet); | ||
1132 | } | 1146 | } |
1133 | 1147 | ||
1134 | /* | 1148 | /* |
1135 | * Only toggle the interrupts bits we are going to use. | 1149 | * Only toggle the interrupts bits we are going to use. |
1136 | * Non-checked interrupt bits are disabled by default. | 1150 | * Non-checked interrupt bits are disabled by default. |
1137 | */ | 1151 | */ |
1152 | spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); | ||
1153 | |||
1138 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); | 1154 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1139 | rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); | 1155 | rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); |
1140 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); | 1156 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); |
@@ -1142,6 +1158,16 @@ static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev, | |||
1142 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); | 1158 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); |
1143 | rt2x00_set_field32(®, CSR8_RXDONE, mask); | 1159 | rt2x00_set_field32(®, CSR8_RXDONE, mask); |
1144 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | 1160 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); |
1161 | |||
1162 | spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); | ||
1163 | |||
1164 | if (state == STATE_RADIO_IRQ_OFF) { | ||
1165 | /* | ||
1166 | * Ensure that all tasklets are finished. | ||
1167 | */ | ||
1168 | tasklet_disable(&rt2x00dev->txstatus_tasklet); | ||
1169 | tasklet_disable(&rt2x00dev->rxdone_tasklet); | ||
1170 | } | ||
1145 | } | 1171 | } |
1146 | 1172 | ||
1147 | static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) | 1173 | static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) |
@@ -1214,9 +1240,7 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1214 | rt2500pci_disable_radio(rt2x00dev); | 1240 | rt2500pci_disable_radio(rt2x00dev); |
1215 | break; | 1241 | break; |
1216 | case STATE_RADIO_IRQ_ON: | 1242 | case STATE_RADIO_IRQ_ON: |
1217 | case STATE_RADIO_IRQ_ON_ISR: | ||
1218 | case STATE_RADIO_IRQ_OFF: | 1243 | case STATE_RADIO_IRQ_OFF: |
1219 | case STATE_RADIO_IRQ_OFF_ISR: | ||
1220 | rt2500pci_toggle_irq(rt2x00dev, state); | 1244 | rt2500pci_toggle_irq(rt2x00dev, state); |
1221 | break; | 1245 | break; |
1222 | case STATE_DEEP_SLEEP: | 1246 | case STATE_DEEP_SLEEP: |
@@ -1263,10 +1287,12 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry, | |||
1263 | rt2x00_desc_write(txd, 2, word); | 1287 | rt2x00_desc_write(txd, 2, word); |
1264 | 1288 | ||
1265 | rt2x00_desc_read(txd, 3, &word); | 1289 | rt2x00_desc_read(txd, 3, &word); |
1266 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); | 1290 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); |
1267 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); | 1291 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); |
1268 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low); | 1292 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, |
1269 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high); | 1293 | txdesc->u.plcp.length_low); |
1294 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, | ||
1295 | txdesc->u.plcp.length_high); | ||
1270 | rt2x00_desc_write(txd, 3, word); | 1296 | rt2x00_desc_write(txd, 3, word); |
1271 | 1297 | ||
1272 | rt2x00_desc_read(txd, 10, &word); | 1298 | rt2x00_desc_read(txd, 10, &word); |
@@ -1291,7 +1317,7 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry, | |||
1291 | rt2x00_set_field32(&word, TXD_W0_OFDM, | 1317 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
1292 | (txdesc->rate_mode == RATE_MODE_OFDM)); | 1318 | (txdesc->rate_mode == RATE_MODE_OFDM)); |
1293 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); | 1319 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); |
1294 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); | 1320 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); |
1295 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, | 1321 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
1296 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); | 1322 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
1297 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); | 1323 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); |
@@ -1337,8 +1363,6 @@ static void rt2500pci_write_beacon(struct queue_entry *entry, | |||
1337 | /* | 1363 | /* |
1338 | * Enable beaconing again. | 1364 | * Enable beaconing again. |
1339 | */ | 1365 | */ |
1340 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); | ||
1341 | rt2x00_set_field32(®, CSR14_TBCN, 1); | ||
1342 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); | 1366 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); |
1343 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | 1367 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
1344 | } | 1368 | } |
@@ -1386,7 +1410,7 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry, | |||
1386 | static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, | 1410 | static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, |
1387 | const enum data_queue_qid queue_idx) | 1411 | const enum data_queue_qid queue_idx) |
1388 | { | 1412 | { |
1389 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); | 1413 | struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
1390 | struct queue_entry_priv_pci *entry_priv; | 1414 | struct queue_entry_priv_pci *entry_priv; |
1391 | struct queue_entry *entry; | 1415 | struct queue_entry *entry; |
1392 | struct txdone_entry_desc txdesc; | 1416 | struct txdone_entry_desc txdesc; |
@@ -1422,58 +1446,68 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, | |||
1422 | } | 1446 | } |
1423 | } | 1447 | } |
1424 | 1448 | ||
1425 | static irqreturn_t rt2500pci_interrupt_thread(int irq, void *dev_instance) | 1449 | static void rt2500pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, |
1450 | struct rt2x00_field32 irq_field) | ||
1426 | { | 1451 | { |
1427 | struct rt2x00_dev *rt2x00dev = dev_instance; | 1452 | u32 reg; |
1428 | u32 reg = rt2x00dev->irqvalue[0]; | ||
1429 | 1453 | ||
1430 | /* | 1454 | /* |
1431 | * Handle interrupts, walk through all bits | 1455 | * Enable a single interrupt. The interrupt mask register |
1432 | * and run the tasks, the bits are checked in order of | 1456 | * access needs locking. |
1433 | * priority. | ||
1434 | */ | 1457 | */ |
1458 | spin_lock_irq(&rt2x00dev->irqmask_lock); | ||
1435 | 1459 | ||
1436 | /* | 1460 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1437 | * 1 - Beacon timer expired interrupt. | 1461 | rt2x00_set_field32(®, irq_field, 0); |
1438 | */ | 1462 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); |
1439 | if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) | ||
1440 | rt2x00lib_beacondone(rt2x00dev); | ||
1441 | 1463 | ||
1442 | /* | 1464 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
1443 | * 2 - Rx ring done interrupt. | 1465 | } |
1444 | */ | ||
1445 | if (rt2x00_get_field32(reg, CSR7_RXDONE)) | ||
1446 | rt2x00pci_rxdone(rt2x00dev); | ||
1447 | 1466 | ||
1448 | /* | 1467 | static void rt2500pci_txstatus_tasklet(unsigned long data) |
1449 | * 3 - Atim ring transmit done interrupt. | 1468 | { |
1450 | */ | 1469 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; |
1451 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) | 1470 | u32 reg; |
1452 | rt2500pci_txdone(rt2x00dev, QID_ATIM); | ||
1453 | 1471 | ||
1454 | /* | 1472 | /* |
1455 | * 4 - Priority ring transmit done interrupt. | 1473 | * Handle all tx queues. |
1456 | */ | 1474 | */ |
1457 | if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) | 1475 | rt2500pci_txdone(rt2x00dev, QID_ATIM); |
1458 | rt2500pci_txdone(rt2x00dev, QID_AC_VO); | 1476 | rt2500pci_txdone(rt2x00dev, QID_AC_VO); |
1477 | rt2500pci_txdone(rt2x00dev, QID_AC_VI); | ||
1459 | 1478 | ||
1460 | /* | 1479 | /* |
1461 | * 5 - Tx ring transmit done interrupt. | 1480 | * Enable all TXDONE interrupts again. |
1462 | */ | 1481 | */ |
1463 | if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) | 1482 | spin_lock_irq(&rt2x00dev->irqmask_lock); |
1464 | rt2500pci_txdone(rt2x00dev, QID_AC_VI); | 1483 | |
1484 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); | ||
1485 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); | ||
1486 | rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); | ||
1487 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); | ||
1488 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | ||
1465 | 1489 | ||
1466 | /* Enable interrupts again. */ | 1490 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
1467 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, | 1491 | } |
1468 | STATE_RADIO_IRQ_ON_ISR); | ||
1469 | 1492 | ||
1470 | return IRQ_HANDLED; | 1493 | static void rt2500pci_tbtt_tasklet(unsigned long data) |
1494 | { | ||
1495 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | ||
1496 | rt2x00lib_beacondone(rt2x00dev); | ||
1497 | rt2500pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE); | ||
1498 | } | ||
1499 | |||
1500 | static void rt2500pci_rxdone_tasklet(unsigned long data) | ||
1501 | { | ||
1502 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | ||
1503 | rt2x00pci_rxdone(rt2x00dev); | ||
1504 | rt2500pci_enable_interrupt(rt2x00dev, CSR8_RXDONE); | ||
1471 | } | 1505 | } |
1472 | 1506 | ||
1473 | static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) | 1507 | static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) |
1474 | { | 1508 | { |
1475 | struct rt2x00_dev *rt2x00dev = dev_instance; | 1509 | struct rt2x00_dev *rt2x00dev = dev_instance; |
1476 | u32 reg; | 1510 | u32 reg, mask; |
1477 | 1511 | ||
1478 | /* | 1512 | /* |
1479 | * Get the interrupt sources & saved to local variable. | 1513 | * Get the interrupt sources & saved to local variable. |
@@ -1488,14 +1522,42 @@ static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance) | |||
1488 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) | 1522 | if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) |
1489 | return IRQ_HANDLED; | 1523 | return IRQ_HANDLED; |
1490 | 1524 | ||
1491 | /* Store irqvalues for use in the interrupt thread. */ | 1525 | mask = reg; |
1492 | rt2x00dev->irqvalue[0] = reg; | ||
1493 | 1526 | ||
1494 | /* Disable interrupts, will be enabled again in the interrupt thread. */ | 1527 | /* |
1495 | rt2x00dev->ops->lib->set_device_state(rt2x00dev, | 1528 | * Schedule tasklets for interrupt handling. |
1496 | STATE_RADIO_IRQ_OFF_ISR); | 1529 | */ |
1530 | if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) | ||
1531 | tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); | ||
1497 | 1532 | ||
1498 | return IRQ_WAKE_THREAD; | 1533 | if (rt2x00_get_field32(reg, CSR7_RXDONE)) |
1534 | tasklet_schedule(&rt2x00dev->rxdone_tasklet); | ||
1535 | |||
1536 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || | ||
1537 | rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || | ||
1538 | rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { | ||
1539 | tasklet_schedule(&rt2x00dev->txstatus_tasklet); | ||
1540 | /* | ||
1541 | * Mask out all txdone interrupts. | ||
1542 | */ | ||
1543 | rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1); | ||
1544 | rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1); | ||
1545 | rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1); | ||
1546 | } | ||
1547 | |||
1548 | /* | ||
1549 | * Disable all interrupts for which a tasklet was scheduled right now, | ||
1550 | * the tasklet will reenable the appropriate interrupts. | ||
1551 | */ | ||
1552 | spin_lock(&rt2x00dev->irqmask_lock); | ||
1553 | |||
1554 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); | ||
1555 | reg |= mask; | ||
1556 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | ||
1557 | |||
1558 | spin_unlock(&rt2x00dev->irqmask_lock); | ||
1559 | |||
1560 | return IRQ_HANDLED; | ||
1499 | } | 1561 | } |
1500 | 1562 | ||
1501 | /* | 1563 | /* |
@@ -1896,6 +1958,7 @@ static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |||
1896 | */ | 1958 | */ |
1897 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); | 1959 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); |
1898 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); | 1960 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); |
1961 | __set_bit(DRIVER_REQUIRE_SW_SEQNO, &rt2x00dev->flags); | ||
1899 | 1962 | ||
1900 | /* | 1963 | /* |
1901 | * Set the rssi offset. | 1964 | * Set the rssi offset. |
@@ -1952,7 +2015,9 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = { | |||
1952 | 2015 | ||
1953 | static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { | 2016 | static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { |
1954 | .irq_handler = rt2500pci_interrupt, | 2017 | .irq_handler = rt2500pci_interrupt, |
1955 | .irq_handler_thread = rt2500pci_interrupt_thread, | 2018 | .txstatus_tasklet = rt2500pci_txstatus_tasklet, |
2019 | .tbtt_tasklet = rt2500pci_tbtt_tasklet, | ||
2020 | .rxdone_tasklet = rt2500pci_rxdone_tasklet, | ||
1956 | .probe_hw = rt2500pci_probe_hw, | 2021 | .probe_hw = rt2500pci_probe_hw, |
1957 | .initialize = rt2x00pci_initialize, | 2022 | .initialize = rt2x00pci_initialize, |
1958 | .uninitialize = rt2x00pci_uninitialize, | 2023 | .uninitialize = rt2x00pci_uninitialize, |