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path: root/drivers/net/wireless/rt2x00/rt2500pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2500pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c312
1 files changed, 146 insertions, 166 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index f7731fb82555..aa6dfb811c71 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -277,6 +277,17 @@ static int rt2500pci_blink_set(struct led_classdev *led_cdev,
277 277
278 return 0; 278 return 0;
279} 279}
280
281static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
282 struct rt2x00_led *led,
283 enum led_type type)
284{
285 led->rt2x00dev = rt2x00dev;
286 led->type = type;
287 led->led_dev.brightness_set = rt2500pci_brightness_set;
288 led->led_dev.blink_set = rt2500pci_blink_set;
289 led->flags = LED_INITIALIZED;
290}
280#endif /* CONFIG_RT2500PCI_LEDS */ 291#endif /* CONFIG_RT2500PCI_LEDS */
281 292
282/* 293/*
@@ -317,8 +328,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
317 struct rt2x00intf_conf *conf, 328 struct rt2x00intf_conf *conf,
318 const unsigned int flags) 329 const unsigned int flags)
319{ 330{
320 struct data_queue *queue = 331 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
321 rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
322 unsigned int bcn_preload; 332 unsigned int bcn_preload;
323 u32 reg; 333 u32 reg;
324 334
@@ -716,38 +726,34 @@ dynamic_cca_tune:
716static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 726static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
717 struct queue_entry *entry) 727 struct queue_entry *entry)
718{ 728{
719 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 729 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
730 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
720 u32 word; 731 u32 word;
721 732
722 rt2x00_desc_read(priv_rx->desc, 1, &word); 733 rt2x00_desc_read(entry_priv->desc, 1, &word);
723 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma); 734 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
724 rt2x00_desc_write(priv_rx->desc, 1, word); 735 rt2x00_desc_write(entry_priv->desc, 1, word);
725 736
726 rt2x00_desc_read(priv_rx->desc, 0, &word); 737 rt2x00_desc_read(entry_priv->desc, 0, &word);
727 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 738 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
728 rt2x00_desc_write(priv_rx->desc, 0, word); 739 rt2x00_desc_write(entry_priv->desc, 0, word);
729} 740}
730 741
731static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev, 742static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
732 struct queue_entry *entry) 743 struct queue_entry *entry)
733{ 744{
734 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; 745 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
735 u32 word; 746 u32 word;
736 747
737 rt2x00_desc_read(priv_tx->desc, 1, &word); 748 rt2x00_desc_read(entry_priv->desc, 0, &word);
738 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
739 rt2x00_desc_write(priv_tx->desc, 1, word);
740
741 rt2x00_desc_read(priv_tx->desc, 0, &word);
742 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 749 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
743 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 750 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
744 rt2x00_desc_write(priv_tx->desc, 0, word); 751 rt2x00_desc_write(entry_priv->desc, 0, word);
745} 752}
746 753
747static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) 754static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
748{ 755{
749 struct queue_entry_priv_pci_rx *priv_rx; 756 struct queue_entry_priv_pci *entry_priv;
750 struct queue_entry_priv_pci_tx *priv_tx;
751 u32 reg; 757 u32 reg;
752 758
753 /* 759 /*
@@ -760,28 +766,28 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
760 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 766 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
761 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 767 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
762 768
763 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 769 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
764 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 770 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
765 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, 771 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
766 priv_tx->desc_dma); 772 entry_priv->desc_dma);
767 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 773 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
768 774
769 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 775 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
770 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 776 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
771 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, 777 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
772 priv_tx->desc_dma); 778 entry_priv->desc_dma);
773 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 779 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
774 780
775 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; 781 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
776 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 782 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
777 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 783 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
778 priv_tx->desc_dma); 784 entry_priv->desc_dma);
779 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 785 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
780 786
781 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; 787 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
782 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 788 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
783 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 789 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
784 priv_tx->desc_dma); 790 entry_priv->desc_dma);
785 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 791 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
786 792
787 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 793 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
@@ -789,9 +795,10 @@ static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
789 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); 795 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
790 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); 796 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
791 797
792 priv_rx = rt2x00dev->rx->entries[0].priv_data; 798 entry_priv = rt2x00dev->rx->entries[0].priv_data;
793 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 799 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
794 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma); 800 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
801 entry_priv->desc_dma);
795 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 802 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
796 803
797 return 0; 804 return 0;
@@ -940,25 +947,32 @@ static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
940 return 0; 947 return 0;
941} 948}
942 949
943static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev) 950static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
944{ 951{
945 unsigned int i; 952 unsigned int i;
946 u16 eeprom;
947 u8 reg_id;
948 u8 value; 953 u8 value;
949 954
950 for (i = 0; i < REGISTER_BUSY_COUNT; i++) { 955 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
951 rt2500pci_bbp_read(rt2x00dev, 0, &value); 956 rt2500pci_bbp_read(rt2x00dev, 0, &value);
952 if ((value != 0xff) && (value != 0x00)) 957 if ((value != 0xff) && (value != 0x00))
953 goto continue_csr_init; 958 return 0;
954 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
955 udelay(REGISTER_BUSY_DELAY); 959 udelay(REGISTER_BUSY_DELAY);
956 } 960 }
957 961
958 ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); 962 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
959 return -EACCES; 963 return -EACCES;
964}
965
966static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
967{
968 unsigned int i;
969 u16 eeprom;
970 u8 reg_id;
971 u8 value;
972
973 if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
974 return -EACCES;
960 975
961continue_csr_init:
962 rt2500pci_bbp_write(rt2x00dev, 3, 0x02); 976 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
963 rt2500pci_bbp_write(rt2x00dev, 4, 0x19); 977 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
964 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c); 978 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
@@ -1013,7 +1027,8 @@ static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1013 1027
1014 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg); 1028 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1015 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1029 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1016 state == STATE_RADIO_RX_OFF); 1030 (state == STATE_RADIO_RX_OFF) ||
1031 (state == STATE_RADIO_RX_OFF_LINK));
1017 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); 1032 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1018} 1033}
1019 1034
@@ -1050,17 +1065,10 @@ static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1050 /* 1065 /*
1051 * Initialize all registers. 1066 * Initialize all registers.
1052 */ 1067 */
1053 if (rt2500pci_init_queues(rt2x00dev) || 1068 if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1054 rt2500pci_init_registers(rt2x00dev) || 1069 rt2500pci_init_registers(rt2x00dev) ||
1055 rt2500pci_init_bbp(rt2x00dev)) { 1070 rt2500pci_init_bbp(rt2x00dev)))
1056 ERROR(rt2x00dev, "Register initialization failed.\n");
1057 return -EIO; 1071 return -EIO;
1058 }
1059
1060 /*
1061 * Enable interrupts.
1062 */
1063 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1064 1072
1065 return 0; 1073 return 0;
1066} 1074}
@@ -1082,11 +1090,6 @@ static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1082 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 1090 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1083 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1); 1091 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1084 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 1092 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1085
1086 /*
1087 * Disable interrupts.
1088 */
1089 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1090} 1093}
1091 1094
1092static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev, 1095static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
@@ -1121,10 +1124,6 @@ static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1121 msleep(10); 1124 msleep(10);
1122 } 1125 }
1123 1126
1124 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1125 "current device state: bbp %d and rf %d.\n",
1126 state, bbp_state, rf_state);
1127
1128 return -EBUSY; 1127 return -EBUSY;
1129} 1128}
1130 1129
@@ -1142,11 +1141,13 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1142 break; 1141 break;
1143 case STATE_RADIO_RX_ON: 1142 case STATE_RADIO_RX_ON:
1144 case STATE_RADIO_RX_ON_LINK: 1143 case STATE_RADIO_RX_ON_LINK:
1145 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1146 break;
1147 case STATE_RADIO_RX_OFF: 1144 case STATE_RADIO_RX_OFF:
1148 case STATE_RADIO_RX_OFF_LINK: 1145 case STATE_RADIO_RX_OFF_LINK:
1149 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); 1146 rt2500pci_toggle_rx(rt2x00dev, state);
1147 break;
1148 case STATE_RADIO_IRQ_ON:
1149 case STATE_RADIO_IRQ_OFF:
1150 rt2500pci_toggle_irq(rt2x00dev, state);
1150 break; 1151 break;
1151 case STATE_DEEP_SLEEP: 1152 case STATE_DEEP_SLEEP:
1152 case STATE_SLEEP: 1153 case STATE_SLEEP:
@@ -1159,6 +1160,10 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1159 break; 1160 break;
1160 } 1161 }
1161 1162
1163 if (unlikely(retval))
1164 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1165 state, retval);
1166
1162 return retval; 1167 return retval;
1163} 1168}
1164 1169
@@ -1167,16 +1172,20 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1167 */ 1172 */
1168static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 1173static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1169 struct sk_buff *skb, 1174 struct sk_buff *skb,
1170 struct txentry_desc *txdesc, 1175 struct txentry_desc *txdesc)
1171 struct ieee80211_tx_control *control)
1172{ 1176{
1173 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1177 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1178 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1174 __le32 *txd = skbdesc->desc; 1179 __le32 *txd = skbdesc->desc;
1175 u32 word; 1180 u32 word;
1176 1181
1177 /* 1182 /*
1178 * Start writing the descriptor words. 1183 * Start writing the descriptor words.
1179 */ 1184 */
1185 rt2x00_desc_read(entry_priv->desc, 1, &word);
1186 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1187 rt2x00_desc_write(entry_priv->desc, 1, word);
1188
1180 rt2x00_desc_read(txd, 2, &word); 1189 rt2x00_desc_read(txd, 2, &word);
1181 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); 1190 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1182 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); 1191 rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
@@ -1210,9 +1219,7 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1210 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); 1219 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1211 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1220 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1212 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1221 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1213 !!(control->flags & 1222 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1214 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1215 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1216 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1223 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1217 rt2x00_desc_write(txd, 0, word); 1224 rt2x00_desc_write(txd, 0, word);
1218} 1225}
@@ -1220,12 +1227,46 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1220/* 1227/*
1221 * TX data initialization 1228 * TX data initialization
1222 */ 1229 */
1230static void rt2500pci_write_beacon(struct queue_entry *entry)
1231{
1232 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1233 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1234 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1235 u32 word;
1236 u32 reg;
1237
1238 /*
1239 * Disable beaconing while we are reloading the beacon data,
1240 * otherwise we might be sending out invalid data.
1241 */
1242 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1243 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1244 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1245 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1246 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1247
1248 /*
1249 * Replace rt2x00lib allocated descriptor with the
1250 * pointer to the _real_ hardware descriptor.
1251 * After that, map the beacon to DMA and update the
1252 * descriptor.
1253 */
1254 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1255 skbdesc->desc = entry_priv->desc;
1256
1257 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1258
1259 rt2x00_desc_read(entry_priv->desc, 1, &word);
1260 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1261 rt2x00_desc_write(entry_priv->desc, 1, word);
1262}
1263
1223static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1264static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1224 const unsigned int queue) 1265 const enum data_queue_qid queue)
1225{ 1266{
1226 u32 reg; 1267 u32 reg;
1227 1268
1228 if (queue == RT2X00_BCN_QUEUE_BEACON) { 1269 if (queue == QID_BEACON) {
1229 rt2x00pci_register_read(rt2x00dev, CSR14, &reg); 1270 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1230 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) { 1271 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1231 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1); 1272 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
@@ -1237,12 +1278,9 @@ static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1237 } 1278 }
1238 1279
1239 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 1280 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1240 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1281 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1241 (queue == IEEE80211_TX_QUEUE_DATA0)); 1282 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1242 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1283 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1243 (queue == IEEE80211_TX_QUEUE_DATA1));
1244 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1245 (queue == RT2X00_BCN_QUEUE_ATIM));
1246 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); 1284 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1247} 1285}
1248 1286
@@ -1252,14 +1290,13 @@ static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1252static void rt2500pci_fill_rxdone(struct queue_entry *entry, 1290static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1253 struct rxdone_entry_desc *rxdesc) 1291 struct rxdone_entry_desc *rxdesc)
1254{ 1292{
1255 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1293 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1256 u32 word0; 1294 u32 word0;
1257 u32 word2; 1295 u32 word2;
1258 1296
1259 rt2x00_desc_read(priv_rx->desc, 0, &word0); 1297 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1260 rt2x00_desc_read(priv_rx->desc, 2, &word2); 1298 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1261 1299
1262 rxdesc->flags = 0;
1263 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1300 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1264 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1301 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1265 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1302 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
@@ -1276,7 +1313,6 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1276 entry->queue->rt2x00dev->rssi_offset; 1313 entry->queue->rt2x00dev->rssi_offset;
1277 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1314 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1278 1315
1279 rxdesc->dev_flags = 0;
1280 if (rt2x00_get_field32(word0, RXD_W0_OFDM)) 1316 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1281 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; 1317 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1282 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1318 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
@@ -1287,18 +1323,18 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1287 * Interrupt functions. 1323 * Interrupt functions.
1288 */ 1324 */
1289static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, 1325static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1290 const enum ieee80211_tx_queue queue_idx) 1326 const enum data_queue_qid queue_idx)
1291{ 1327{
1292 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1328 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1293 struct queue_entry_priv_pci_tx *priv_tx; 1329 struct queue_entry_priv_pci *entry_priv;
1294 struct queue_entry *entry; 1330 struct queue_entry *entry;
1295 struct txdone_entry_desc txdesc; 1331 struct txdone_entry_desc txdesc;
1296 u32 word; 1332 u32 word;
1297 1333
1298 while (!rt2x00queue_empty(queue)) { 1334 while (!rt2x00queue_empty(queue)) {
1299 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1335 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1300 priv_tx = entry->priv_data; 1336 entry_priv = entry->priv_data;
1301 rt2x00_desc_read(priv_tx->desc, 0, &word); 1337 rt2x00_desc_read(entry_priv->desc, 0, &word);
1302 1338
1303 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1339 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1304 !rt2x00_get_field32(word, TXD_W0_VALID)) 1340 !rt2x00_get_field32(word, TXD_W0_VALID))
@@ -1307,10 +1343,21 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1307 /* 1343 /*
1308 * Obtain the status about this packet. 1344 * Obtain the status about this packet.
1309 */ 1345 */
1310 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT); 1346 txdesc.flags = 0;
1347 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1348 case 0: /* Success */
1349 case 1: /* Success with retry */
1350 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1351 break;
1352 case 2: /* Failure, excessive retries */
1353 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1354 /* Don't break, this is a failed frame! */
1355 default: /* Failure */
1356 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1357 }
1311 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); 1358 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1312 1359
1313 rt2x00pci_txdone(rt2x00dev, entry, &txdesc); 1360 rt2x00lib_txdone(entry, &txdesc);
1314 } 1361 }
1315} 1362}
1316 1363
@@ -1354,19 +1401,19 @@ static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1354 * 3 - Atim ring transmit done interrupt. 1401 * 3 - Atim ring transmit done interrupt.
1355 */ 1402 */
1356 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) 1403 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1357 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM); 1404 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1358 1405
1359 /* 1406 /*
1360 * 4 - Priority ring transmit done interrupt. 1407 * 4 - Priority ring transmit done interrupt.
1361 */ 1408 */
1362 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) 1409 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1363 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0); 1410 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1364 1411
1365 /* 1412 /*
1366 * 5 - Tx ring transmit done interrupt. 1413 * 5 - Tx ring transmit done interrupt.
1367 */ 1414 */
1368 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) 1415 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1369 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1); 1416 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1370 1417
1371 return IRQ_HANDLED; 1418 return IRQ_HANDLED;
1372} 1419}
@@ -1486,23 +1533,10 @@ static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1486#ifdef CONFIG_RT2500PCI_LEDS 1533#ifdef CONFIG_RT2500PCI_LEDS
1487 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); 1534 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1488 1535
1489 rt2x00dev->led_radio.rt2x00dev = rt2x00dev; 1536 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1490 rt2x00dev->led_radio.type = LED_TYPE_RADIO; 1537 if (value == LED_MODE_TXRX_ACTIVITY)
1491 rt2x00dev->led_radio.led_dev.brightness_set = 1538 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1492 rt2500pci_brightness_set; 1539 LED_TYPE_ACTIVITY);
1493 rt2x00dev->led_radio.led_dev.blink_set =
1494 rt2500pci_blink_set;
1495 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1496
1497 if (value == LED_MODE_TXRX_ACTIVITY) {
1498 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1499 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1500 rt2x00dev->led_qual.led_dev.brightness_set =
1501 rt2500pci_brightness_set;
1502 rt2x00dev->led_qual.led_dev.blink_set =
1503 rt2500pci_blink_set;
1504 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1505 }
1506#endif /* CONFIG_RT2500PCI_LEDS */ 1540#endif /* CONFIG_RT2500PCI_LEDS */
1507 1541
1508 /* 1542 /*
@@ -1695,13 +1729,12 @@ static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1695 /* 1729 /*
1696 * Initialize all hw fields. 1730 * Initialize all hw fields.
1697 */ 1731 */
1698 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; 1732 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1733 IEEE80211_HW_SIGNAL_DBM;
1734
1699 rt2x00dev->hw->extra_tx_headroom = 0; 1735 rt2x00dev->hw->extra_tx_headroom = 0;
1700 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1701 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1702 rt2x00dev->hw->queues = 2;
1703 1736
1704 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); 1737 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1705 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1738 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1706 rt2x00_eeprom_addr(rt2x00dev, 1739 rt2x00_eeprom_addr(rt2x00dev,
1707 EEPROM_MAC_ADDR_0)); 1740 EEPROM_MAC_ADDR_0));
@@ -1765,9 +1798,10 @@ static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1765 rt2500pci_probe_hw_mode(rt2x00dev); 1798 rt2500pci_probe_hw_mode(rt2x00dev);
1766 1799
1767 /* 1800 /*
1768 * This device requires the atim queue 1801 * This device requires the atim queue and DMA-mapped skbs.
1769 */ 1802 */
1770 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); 1803 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1804 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1771 1805
1772 /* 1806 /*
1773 * Set the rssi offset. 1807 * Set the rssi offset.
@@ -1808,61 +1842,6 @@ static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1808 return tsf; 1842 return tsf;
1809} 1843}
1810 1844
1811static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1812 struct ieee80211_tx_control *control)
1813{
1814 struct rt2x00_dev *rt2x00dev = hw->priv;
1815 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1816 struct queue_entry_priv_pci_tx *priv_tx;
1817 struct skb_frame_desc *skbdesc;
1818 u32 reg;
1819
1820 if (unlikely(!intf->beacon))
1821 return -ENOBUFS;
1822
1823 priv_tx = intf->beacon->priv_data;
1824
1825 /*
1826 * Fill in skb descriptor
1827 */
1828 skbdesc = get_skb_frame_desc(skb);
1829 memset(skbdesc, 0, sizeof(*skbdesc));
1830 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1831 skbdesc->data = skb->data;
1832 skbdesc->data_len = skb->len;
1833 skbdesc->desc = priv_tx->desc;
1834 skbdesc->desc_len = intf->beacon->queue->desc_size;
1835 skbdesc->entry = intf->beacon;
1836
1837 /*
1838 * Disable beaconing while we are reloading the beacon data,
1839 * otherwise we might be sending out invalid data.
1840 */
1841 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1842 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1843 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1844 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1845 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1846
1847 /*
1848 * mac80211 doesn't provide the control->queue variable
1849 * for beacons. Set our own queue identification so
1850 * it can be used during descriptor initialization.
1851 */
1852 control->queue = RT2X00_BCN_QUEUE_BEACON;
1853 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1854
1855 /*
1856 * Enable beacon generation.
1857 * Write entire beacon with descriptor to register,
1858 * and kick the beacon generator.
1859 */
1860 memcpy(priv_tx->data, skb->data, skb->len);
1861 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1862
1863 return 0;
1864}
1865
1866static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw) 1845static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1867{ 1846{
1868 struct rt2x00_dev *rt2x00dev = hw->priv; 1847 struct rt2x00_dev *rt2x00dev = hw->priv;
@@ -1887,7 +1866,6 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1887 .conf_tx = rt2x00mac_conf_tx, 1866 .conf_tx = rt2x00mac_conf_tx,
1888 .get_tx_stats = rt2x00mac_get_tx_stats, 1867 .get_tx_stats = rt2x00mac_get_tx_stats,
1889 .get_tsf = rt2500pci_get_tsf, 1868 .get_tsf = rt2500pci_get_tsf,
1890 .beacon_update = rt2500pci_beacon_update,
1891 .tx_last_beacon = rt2500pci_tx_last_beacon, 1869 .tx_last_beacon = rt2500pci_tx_last_beacon,
1892}; 1870};
1893 1871
@@ -1905,6 +1883,7 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1905 .link_tuner = rt2500pci_link_tuner, 1883 .link_tuner = rt2500pci_link_tuner,
1906 .write_tx_desc = rt2500pci_write_tx_desc, 1884 .write_tx_desc = rt2500pci_write_tx_desc,
1907 .write_tx_data = rt2x00pci_write_tx_data, 1885 .write_tx_data = rt2x00pci_write_tx_data,
1886 .write_beacon = rt2500pci_write_beacon,
1908 .kick_tx_queue = rt2500pci_kick_tx_queue, 1887 .kick_tx_queue = rt2500pci_kick_tx_queue,
1909 .fill_rxdone = rt2500pci_fill_rxdone, 1888 .fill_rxdone = rt2500pci_fill_rxdone,
1910 .config_filter = rt2500pci_config_filter, 1889 .config_filter = rt2500pci_config_filter,
@@ -1917,28 +1896,28 @@ static const struct data_queue_desc rt2500pci_queue_rx = {
1917 .entry_num = RX_ENTRIES, 1896 .entry_num = RX_ENTRIES,
1918 .data_size = DATA_FRAME_SIZE, 1897 .data_size = DATA_FRAME_SIZE,
1919 .desc_size = RXD_DESC_SIZE, 1898 .desc_size = RXD_DESC_SIZE,
1920 .priv_size = sizeof(struct queue_entry_priv_pci_rx), 1899 .priv_size = sizeof(struct queue_entry_priv_pci),
1921}; 1900};
1922 1901
1923static const struct data_queue_desc rt2500pci_queue_tx = { 1902static const struct data_queue_desc rt2500pci_queue_tx = {
1924 .entry_num = TX_ENTRIES, 1903 .entry_num = TX_ENTRIES,
1925 .data_size = DATA_FRAME_SIZE, 1904 .data_size = DATA_FRAME_SIZE,
1926 .desc_size = TXD_DESC_SIZE, 1905 .desc_size = TXD_DESC_SIZE,
1927 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1906 .priv_size = sizeof(struct queue_entry_priv_pci),
1928}; 1907};
1929 1908
1930static const struct data_queue_desc rt2500pci_queue_bcn = { 1909static const struct data_queue_desc rt2500pci_queue_bcn = {
1931 .entry_num = BEACON_ENTRIES, 1910 .entry_num = BEACON_ENTRIES,
1932 .data_size = MGMT_FRAME_SIZE, 1911 .data_size = MGMT_FRAME_SIZE,
1933 .desc_size = TXD_DESC_SIZE, 1912 .desc_size = TXD_DESC_SIZE,
1934 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1913 .priv_size = sizeof(struct queue_entry_priv_pci),
1935}; 1914};
1936 1915
1937static const struct data_queue_desc rt2500pci_queue_atim = { 1916static const struct data_queue_desc rt2500pci_queue_atim = {
1938 .entry_num = ATIM_ENTRIES, 1917 .entry_num = ATIM_ENTRIES,
1939 .data_size = DATA_FRAME_SIZE, 1918 .data_size = DATA_FRAME_SIZE,
1940 .desc_size = TXD_DESC_SIZE, 1919 .desc_size = TXD_DESC_SIZE,
1941 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1920 .priv_size = sizeof(struct queue_entry_priv_pci),
1942}; 1921};
1943 1922
1944static const struct rt2x00_ops rt2500pci_ops = { 1923static const struct rt2x00_ops rt2500pci_ops = {
@@ -1947,6 +1926,7 @@ static const struct rt2x00_ops rt2500pci_ops = {
1947 .max_ap_intf = 1, 1926 .max_ap_intf = 1,
1948 .eeprom_size = EEPROM_SIZE, 1927 .eeprom_size = EEPROM_SIZE,
1949 .rf_size = RF_SIZE, 1928 .rf_size = RF_SIZE,
1929 .tx_queues = NUM_TX_QUEUES,
1950 .rx = &rt2500pci_queue_rx, 1930 .rx = &rt2500pci_queue_rx,
1951 .tx = &rt2500pci_queue_tx, 1931 .tx = &rt2500pci_queue_tx,
1952 .bcn = &rt2500pci_queue_bcn, 1932 .bcn = &rt2500pci_queue_bcn,