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path: root/drivers/net/wireless/rt2x00/rt2500pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2500pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index e43ff9c79063..885844c1a3c3 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -327,7 +327,7 @@ static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
327 /* 327 /*
328 * Enable beacon config 328 * Enable beacon config
329 */ 329 */
330 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20); 330 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
331 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg); 331 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
332 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload); 332 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
333 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min); 333 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
@@ -373,25 +373,25 @@ static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
373 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg); 373 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
374 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00); 374 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
375 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04); 375 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
376 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10)); 376 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 10));
377 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg); 377 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
378 378
379 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg); 379 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
380 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask); 380 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
381 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04); 381 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
382 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20)); 382 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 20));
383 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg); 383 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
384 384
385 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg); 385 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
386 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask); 386 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
387 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04); 387 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
388 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55)); 388 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 55));
389 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg); 389 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
390 390
391 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg); 391 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
392 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask); 392 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
393 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84); 393 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
394 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110)); 394 rt2x00_set_field32(&reg, ARCSR2_LENGTH, GET_DURATION(ACK_SIZE, 110));
395 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg); 395 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
396 396
397 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates); 397 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);