diff options
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2500pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2500pci.c | 199 |
1 files changed, 113 insertions, 86 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c index 884e225f7b9f..0a54b6512207 100644 --- a/drivers/net/wireless/rt2x00/rt2500pci.c +++ b/drivers/net/wireless/rt2x00/rt2500pci.c | |||
@@ -263,6 +263,8 @@ static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev, | |||
263 | static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type, | 263 | static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type, |
264 | const int tsf_sync) | 264 | const int tsf_sync) |
265 | { | 265 | { |
266 | struct data_queue *queue = | ||
267 | rt2x00queue_get_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON); | ||
266 | u32 reg; | 268 | u32 reg; |
267 | 269 | ||
268 | rt2x00pci_register_write(rt2x00dev, CSR14, 0); | 270 | rt2x00pci_register_write(rt2x00dev, CSR14, 0); |
@@ -273,10 +275,7 @@ static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type, | |||
273 | rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®); | 275 | rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®); |
274 | rt2x00_set_field32(®, BCNCSR1_PRELOAD, | 276 | rt2x00_set_field32(®, BCNCSR1_PRELOAD, |
275 | PREAMBLE + get_duration(IEEE80211_HEADER, 20)); | 277 | PREAMBLE + get_duration(IEEE80211_HEADER, 20)); |
276 | rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, | 278 | rt2x00_set_field32(®, BCNCSR1_BEACON_CWMIN, queue->cw_min); |
277 | rt2x00lib_get_ring(rt2x00dev, | ||
278 | IEEE80211_TX_QUEUE_BEACON) | ||
279 | ->tx_params.cw_min); | ||
280 | rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); | 279 | rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg); |
281 | 280 | ||
282 | /* | 281 | /* |
@@ -684,82 +683,80 @@ dynamic_cca_tune: | |||
684 | * Initialization functions. | 683 | * Initialization functions. |
685 | */ | 684 | */ |
686 | static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev, | 685 | static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev, |
687 | struct data_entry *entry) | 686 | struct queue_entry *entry) |
688 | { | 687 | { |
689 | __le32 *rxd = entry->priv; | 688 | struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; |
690 | u32 word; | 689 | u32 word; |
691 | 690 | ||
692 | rt2x00_desc_read(rxd, 1, &word); | 691 | rt2x00_desc_read(priv_rx->desc, 1, &word); |
693 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry->data_dma); | 692 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma); |
694 | rt2x00_desc_write(rxd, 1, word); | 693 | rt2x00_desc_write(priv_rx->desc, 1, word); |
695 | 694 | ||
696 | rt2x00_desc_read(rxd, 0, &word); | 695 | rt2x00_desc_read(priv_rx->desc, 0, &word); |
697 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); | 696 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); |
698 | rt2x00_desc_write(rxd, 0, word); | 697 | rt2x00_desc_write(priv_rx->desc, 0, word); |
699 | } | 698 | } |
700 | 699 | ||
701 | static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev, | 700 | static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev, |
702 | struct data_entry *entry) | 701 | struct queue_entry *entry) |
703 | { | 702 | { |
704 | __le32 *txd = entry->priv; | 703 | struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; |
705 | u32 word; | 704 | u32 word; |
706 | 705 | ||
707 | rt2x00_desc_read(txd, 1, &word); | 706 | rt2x00_desc_read(priv_tx->desc, 1, &word); |
708 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry->data_dma); | 707 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma); |
709 | rt2x00_desc_write(txd, 1, word); | 708 | rt2x00_desc_write(priv_tx->desc, 1, word); |
710 | 709 | ||
711 | rt2x00_desc_read(txd, 0, &word); | 710 | rt2x00_desc_read(priv_tx->desc, 0, &word); |
712 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); | 711 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); |
713 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); | 712 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); |
714 | rt2x00_desc_write(txd, 0, word); | 713 | rt2x00_desc_write(priv_tx->desc, 0, word); |
715 | } | 714 | } |
716 | 715 | ||
717 | static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev) | 716 | static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev) |
718 | { | 717 | { |
718 | struct queue_entry_priv_pci_rx *priv_rx; | ||
719 | struct queue_entry_priv_pci_tx *priv_tx; | ||
719 | u32 reg; | 720 | u32 reg; |
720 | 721 | ||
721 | /* | 722 | /* |
722 | * Initialize registers. | 723 | * Initialize registers. |
723 | */ | 724 | */ |
724 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); | 725 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); |
725 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, | 726 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); |
726 | rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size); | 727 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); |
727 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, | 728 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); |
728 | rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit); | 729 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
729 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, | ||
730 | rt2x00dev->bcn[1].stats.limit); | ||
731 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, | ||
732 | rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit); | ||
733 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); | 730 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
734 | 731 | ||
732 | priv_tx = rt2x00dev->tx[1].entries[0].priv_data; | ||
735 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); | 733 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); |
736 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, | 734 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, priv_tx->dma); |
737 | rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma); | ||
738 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); | 735 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); |
739 | 736 | ||
737 | priv_tx = rt2x00dev->tx[0].entries[0].priv_data; | ||
740 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); | 738 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); |
741 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, | 739 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma); |
742 | rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma); | ||
743 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); | 740 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
744 | 741 | ||
742 | priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; | ||
745 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); | 743 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
746 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, | 744 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma); |
747 | rt2x00dev->bcn[1].data_dma); | ||
748 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); | 745 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
749 | 746 | ||
747 | priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; | ||
750 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); | 748 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
751 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, | 749 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma); |
752 | rt2x00dev->bcn[0].data_dma); | ||
753 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); | 750 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); |
754 | 751 | ||
755 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); | 752 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); |
756 | rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); | 753 | rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); |
757 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit); | 754 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); |
758 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); | 755 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); |
759 | 756 | ||
757 | priv_rx = rt2x00dev->rx->entries[0].priv_data; | ||
760 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); | 758 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); |
761 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, | 759 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_tx->dma); |
762 | rt2x00dev->rx->data_dma); | ||
763 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); | 760 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); |
764 | 761 | ||
765 | return 0; | 762 | return 0; |
@@ -1011,7 +1008,7 @@ static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev) | |||
1011 | /* | 1008 | /* |
1012 | * Initialize all registers. | 1009 | * Initialize all registers. |
1013 | */ | 1010 | */ |
1014 | if (rt2500pci_init_rings(rt2x00dev) || | 1011 | if (rt2500pci_init_queues(rt2x00dev) || |
1015 | rt2500pci_init_registers(rt2x00dev) || | 1012 | rt2500pci_init_registers(rt2x00dev) || |
1016 | rt2500pci_init_bbp(rt2x00dev)) { | 1013 | rt2500pci_init_bbp(rt2x00dev)) { |
1017 | ERROR(rt2x00dev, "Register initialization failed.\n"); | 1014 | ERROR(rt2x00dev, "Register initialization failed.\n"); |
@@ -1138,10 +1135,10 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1138 | */ | 1135 | */ |
1139 | static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | 1136 | static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, |
1140 | struct sk_buff *skb, | 1137 | struct sk_buff *skb, |
1141 | struct txdata_entry_desc *desc, | 1138 | struct txentry_desc *txdesc, |
1142 | struct ieee80211_tx_control *control) | 1139 | struct ieee80211_tx_control *control) |
1143 | { | 1140 | { |
1144 | struct skb_desc *skbdesc = get_skb_desc(skb); | 1141 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
1145 | __le32 *txd = skbdesc->desc; | 1142 | __le32 *txd = skbdesc->desc; |
1146 | u32 word; | 1143 | u32 word; |
1147 | 1144 | ||
@@ -1150,36 +1147,36 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |||
1150 | */ | 1147 | */ |
1151 | rt2x00_desc_read(txd, 2, &word); | 1148 | rt2x00_desc_read(txd, 2, &word); |
1152 | rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); | 1149 | rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); |
1153 | rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs); | 1150 | rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs); |
1154 | rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min); | 1151 | rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min); |
1155 | rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max); | 1152 | rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max); |
1156 | rt2x00_desc_write(txd, 2, word); | 1153 | rt2x00_desc_write(txd, 2, word); |
1157 | 1154 | ||
1158 | rt2x00_desc_read(txd, 3, &word); | 1155 | rt2x00_desc_read(txd, 3, &word); |
1159 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal); | 1156 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); |
1160 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service); | 1157 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); |
1161 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low); | 1158 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low); |
1162 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high); | 1159 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high); |
1163 | rt2x00_desc_write(txd, 3, word); | 1160 | rt2x00_desc_write(txd, 3, word); |
1164 | 1161 | ||
1165 | rt2x00_desc_read(txd, 10, &word); | 1162 | rt2x00_desc_read(txd, 10, &word); |
1166 | rt2x00_set_field32(&word, TXD_W10_RTS, | 1163 | rt2x00_set_field32(&word, TXD_W10_RTS, |
1167 | test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags)); | 1164 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); |
1168 | rt2x00_desc_write(txd, 10, word); | 1165 | rt2x00_desc_write(txd, 10, word); |
1169 | 1166 | ||
1170 | rt2x00_desc_read(txd, 0, &word); | 1167 | rt2x00_desc_read(txd, 0, &word); |
1171 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); | 1168 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); |
1172 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); | 1169 | rt2x00_set_field32(&word, TXD_W0_VALID, 1); |
1173 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, | 1170 | rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, |
1174 | test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags)); | 1171 | test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); |
1175 | rt2x00_set_field32(&word, TXD_W0_ACK, | 1172 | rt2x00_set_field32(&word, TXD_W0_ACK, |
1176 | test_bit(ENTRY_TXD_ACK, &desc->flags)); | 1173 | test_bit(ENTRY_TXD_ACK, &txdesc->flags)); |
1177 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, | 1174 | rt2x00_set_field32(&word, TXD_W0_TIMESTAMP, |
1178 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags)); | 1175 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
1179 | rt2x00_set_field32(&word, TXD_W0_OFDM, | 1176 | rt2x00_set_field32(&word, TXD_W0_OFDM, |
1180 | test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags)); | 1177 | test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags)); |
1181 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); | 1178 | rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1); |
1182 | rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs); | 1179 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
1183 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, | 1180 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
1184 | !!(control->flags & | 1181 | !!(control->flags & |
1185 | IEEE80211_TXCTL_LONG_RETRY_LIMIT)); | 1182 | IEEE80211_TXCTL_LONG_RETRY_LIMIT)); |
@@ -1218,46 +1215,46 @@ static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, | |||
1218 | /* | 1215 | /* |
1219 | * RX control handlers | 1216 | * RX control handlers |
1220 | */ | 1217 | */ |
1221 | static void rt2500pci_fill_rxdone(struct data_entry *entry, | 1218 | static void rt2500pci_fill_rxdone(struct queue_entry *entry, |
1222 | struct rxdata_entry_desc *desc) | 1219 | struct rxdone_entry_desc *rxdesc) |
1223 | { | 1220 | { |
1224 | __le32 *rxd = entry->priv; | 1221 | struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; |
1225 | u32 word0; | 1222 | u32 word0; |
1226 | u32 word2; | 1223 | u32 word2; |
1227 | 1224 | ||
1228 | rt2x00_desc_read(rxd, 0, &word0); | 1225 | rt2x00_desc_read(priv_rx->desc, 0, &word0); |
1229 | rt2x00_desc_read(rxd, 2, &word2); | 1226 | rt2x00_desc_read(priv_rx->desc, 2, &word2); |
1230 | 1227 | ||
1231 | desc->flags = 0; | 1228 | rxdesc->flags = 0; |
1232 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) | 1229 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
1233 | desc->flags |= RX_FLAG_FAILED_FCS_CRC; | 1230 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
1234 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) | 1231 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) |
1235 | desc->flags |= RX_FLAG_FAILED_PLCP_CRC; | 1232 | rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; |
1236 | 1233 | ||
1237 | desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); | 1234 | rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL); |
1238 | desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - | 1235 | rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) - |
1239 | entry->ring->rt2x00dev->rssi_offset; | 1236 | entry->queue->rt2x00dev->rssi_offset; |
1240 | desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM); | 1237 | rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM); |
1241 | desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); | 1238 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
1242 | desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS); | 1239 | rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS); |
1243 | } | 1240 | } |
1244 | 1241 | ||
1245 | /* | 1242 | /* |
1246 | * Interrupt functions. | 1243 | * Interrupt functions. |
1247 | */ | 1244 | */ |
1248 | static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue) | 1245 | static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, |
1246 | const enum ieee80211_tx_queue queue_idx) | ||
1249 | { | 1247 | { |
1250 | struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue); | 1248 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
1251 | struct data_entry *entry; | 1249 | struct queue_entry_priv_pci_tx *priv_tx; |
1252 | __le32 *txd; | 1250 | struct queue_entry *entry; |
1251 | struct txdone_entry_desc txdesc; | ||
1253 | u32 word; | 1252 | u32 word; |
1254 | int tx_status; | ||
1255 | int retry; | ||
1256 | 1253 | ||
1257 | while (!rt2x00_ring_empty(ring)) { | 1254 | while (!rt2x00queue_empty(queue)) { |
1258 | entry = rt2x00_get_data_entry_done(ring); | 1255 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
1259 | txd = entry->priv; | 1256 | priv_tx = entry->priv_data; |
1260 | rt2x00_desc_read(txd, 0, &word); | 1257 | rt2x00_desc_read(priv_tx->desc, 0, &word); |
1261 | 1258 | ||
1262 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | 1259 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
1263 | !rt2x00_get_field32(word, TXD_W0_VALID)) | 1260 | !rt2x00_get_field32(word, TXD_W0_VALID)) |
@@ -1266,10 +1263,10 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue) | |||
1266 | /* | 1263 | /* |
1267 | * Obtain the status about this packet. | 1264 | * Obtain the status about this packet. |
1268 | */ | 1265 | */ |
1269 | tx_status = rt2x00_get_field32(word, TXD_W0_RESULT); | 1266 | txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT); |
1270 | retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); | 1267 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); |
1271 | 1268 | ||
1272 | rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry); | 1269 | rt2x00pci_txdone(rt2x00dev, entry, &txdesc); |
1273 | } | 1270 | } |
1274 | } | 1271 | } |
1275 | 1272 | ||
@@ -1705,9 +1702,9 @@ static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |||
1705 | rt2500pci_probe_hw_mode(rt2x00dev); | 1702 | rt2500pci_probe_hw_mode(rt2x00dev); |
1706 | 1703 | ||
1707 | /* | 1704 | /* |
1708 | * This device requires the beacon ring | 1705 | * This device requires the atim queue |
1709 | */ | 1706 | */ |
1710 | __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags); | 1707 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); |
1711 | 1708 | ||
1712 | /* | 1709 | /* |
1713 | * Set the rssi offset. | 1710 | * Set the rssi offset. |
@@ -1871,12 +1868,42 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = { | |||
1871 | .config = rt2500pci_config, | 1868 | .config = rt2500pci_config, |
1872 | }; | 1869 | }; |
1873 | 1870 | ||
1871 | static const struct data_queue_desc rt2500pci_queue_rx = { | ||
1872 | .entry_num = RX_ENTRIES, | ||
1873 | .data_size = DATA_FRAME_SIZE, | ||
1874 | .desc_size = RXD_DESC_SIZE, | ||
1875 | .priv_size = sizeof(struct queue_entry_priv_pci_rx), | ||
1876 | }; | ||
1877 | |||
1878 | static const struct data_queue_desc rt2500pci_queue_tx = { | ||
1879 | .entry_num = TX_ENTRIES, | ||
1880 | .data_size = DATA_FRAME_SIZE, | ||
1881 | .desc_size = TXD_DESC_SIZE, | ||
1882 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | ||
1883 | }; | ||
1884 | |||
1885 | static const struct data_queue_desc rt2500pci_queue_bcn = { | ||
1886 | .entry_num = BEACON_ENTRIES, | ||
1887 | .data_size = MGMT_FRAME_SIZE, | ||
1888 | .desc_size = TXD_DESC_SIZE, | ||
1889 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | ||
1890 | }; | ||
1891 | |||
1892 | static const struct data_queue_desc rt2500pci_queue_atim = { | ||
1893 | .entry_num = ATIM_ENTRIES, | ||
1894 | .data_size = DATA_FRAME_SIZE, | ||
1895 | .desc_size = TXD_DESC_SIZE, | ||
1896 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | ||
1897 | }; | ||
1898 | |||
1874 | static const struct rt2x00_ops rt2500pci_ops = { | 1899 | static const struct rt2x00_ops rt2500pci_ops = { |
1875 | .name = KBUILD_MODNAME, | 1900 | .name = KBUILD_MODNAME, |
1876 | .rxd_size = RXD_DESC_SIZE, | ||
1877 | .txd_size = TXD_DESC_SIZE, | ||
1878 | .eeprom_size = EEPROM_SIZE, | 1901 | .eeprom_size = EEPROM_SIZE, |
1879 | .rf_size = RF_SIZE, | 1902 | .rf_size = RF_SIZE, |
1903 | .rx = &rt2500pci_queue_rx, | ||
1904 | .tx = &rt2500pci_queue_tx, | ||
1905 | .bcn = &rt2500pci_queue_bcn, | ||
1906 | .atim = &rt2500pci_queue_atim, | ||
1880 | .lib = &rt2500pci_rt2x00_ops, | 1907 | .lib = &rt2500pci_rt2x00_ops, |
1881 | .hw = &rt2500pci_mac80211_ops, | 1908 | .hw = &rt2500pci_mac80211_ops, |
1882 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS | 1909 | #ifdef CONFIG_RT2X00_LIB_DEBUGFS |