diff options
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2400pci.c | 131 |
1 files changed, 87 insertions, 44 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c index 62786608951e..35d9a06a76af 100644 --- a/drivers/net/wireless/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/rt2x00/rt2400pci.c | |||
@@ -633,6 +633,88 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev, | |||
633 | } | 633 | } |
634 | 634 | ||
635 | /* | 635 | /* |
636 | * Queue handlers. | ||
637 | */ | ||
638 | static void rt2400pci_start_queue(struct data_queue *queue) | ||
639 | { | ||
640 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | ||
641 | u32 reg; | ||
642 | |||
643 | switch (queue->qid) { | ||
644 | case QID_RX: | ||
645 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | ||
646 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); | ||
647 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | ||
648 | break; | ||
649 | case QID_BEACON: | ||
650 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | ||
651 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); | ||
652 | rt2x00_set_field32(®, CSR14_TBCN, 1); | ||
653 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); | ||
654 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | ||
655 | break; | ||
656 | default: | ||
657 | break; | ||
658 | } | ||
659 | } | ||
660 | |||
661 | static void rt2400pci_kick_queue(struct data_queue *queue) | ||
662 | { | ||
663 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | ||
664 | u32 reg; | ||
665 | |||
666 | switch (queue->qid) { | ||
667 | case QID_AC_BE: | ||
668 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | ||
669 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); | ||
670 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | ||
671 | break; | ||
672 | case QID_AC_BK: | ||
673 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | ||
674 | rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); | ||
675 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | ||
676 | break; | ||
677 | case QID_ATIM: | ||
678 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | ||
679 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); | ||
680 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | ||
681 | break; | ||
682 | default: | ||
683 | break; | ||
684 | } | ||
685 | } | ||
686 | |||
687 | static void rt2400pci_stop_queue(struct data_queue *queue) | ||
688 | { | ||
689 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | ||
690 | u32 reg; | ||
691 | |||
692 | switch (queue->qid) { | ||
693 | case QID_AC_BE: | ||
694 | case QID_AC_BK: | ||
695 | case QID_ATIM: | ||
696 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | ||
697 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); | ||
698 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | ||
699 | break; | ||
700 | case QID_RX: | ||
701 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | ||
702 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); | ||
703 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | ||
704 | break; | ||
705 | case QID_BEACON: | ||
706 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | ||
707 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); | ||
708 | rt2x00_set_field32(®, CSR14_TBCN, 0); | ||
709 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | ||
710 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | ||
711 | break; | ||
712 | default: | ||
713 | break; | ||
714 | } | ||
715 | } | ||
716 | |||
717 | /* | ||
636 | * Initialization functions. | 718 | * Initialization functions. |
637 | */ | 719 | */ |
638 | static bool rt2400pci_get_entry_state(struct queue_entry *entry) | 720 | static bool rt2400pci_get_entry_state(struct queue_entry *entry) |
@@ -878,17 +960,6 @@ static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) | |||
878 | /* | 960 | /* |
879 | * Device state switch handlers. | 961 | * Device state switch handlers. |
880 | */ | 962 | */ |
881 | static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev, | ||
882 | enum dev_state state) | ||
883 | { | ||
884 | u32 reg; | ||
885 | |||
886 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | ||
887 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, | ||
888 | (state == STATE_RADIO_RX_OFF)); | ||
889 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | ||
890 | } | ||
891 | |||
892 | static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, | 963 | static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev, |
893 | enum dev_state state) | 964 | enum dev_state state) |
894 | { | 965 | { |
@@ -988,8 +1059,10 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
988 | rt2400pci_disable_radio(rt2x00dev); | 1059 | rt2400pci_disable_radio(rt2x00dev); |
989 | break; | 1060 | break; |
990 | case STATE_RADIO_RX_ON: | 1061 | case STATE_RADIO_RX_ON: |
1062 | rt2400pci_start_queue(rt2x00dev->rx); | ||
1063 | break; | ||
991 | case STATE_RADIO_RX_OFF: | 1064 | case STATE_RADIO_RX_OFF: |
992 | rt2400pci_toggle_rx(rt2x00dev, state); | 1065 | rt2400pci_stop_queue(rt2x00dev->rx); |
993 | break; | 1066 | break; |
994 | case STATE_RADIO_IRQ_ON: | 1067 | case STATE_RADIO_IRQ_ON: |
995 | case STATE_RADIO_IRQ_ON_ISR: | 1068 | case STATE_RADIO_IRQ_ON_ISR: |
@@ -1122,36 +1195,6 @@ static void rt2400pci_write_beacon(struct queue_entry *entry, | |||
1122 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | 1195 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); |
1123 | } | 1196 | } |
1124 | 1197 | ||
1125 | static void rt2400pci_kick_tx_queue(struct data_queue *queue) | ||
1126 | { | ||
1127 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | ||
1128 | u32 reg; | ||
1129 | |||
1130 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | ||
1131 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE)); | ||
1132 | rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK)); | ||
1133 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM)); | ||
1134 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | ||
1135 | } | ||
1136 | |||
1137 | static void rt2400pci_kill_tx_queue(struct data_queue *queue) | ||
1138 | { | ||
1139 | struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; | ||
1140 | u32 reg; | ||
1141 | |||
1142 | if (queue->qid == QID_BEACON) { | ||
1143 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | ||
1144 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); | ||
1145 | rt2x00_set_field32(®, CSR14_TBCN, 0); | ||
1146 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | ||
1147 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | ||
1148 | } else { | ||
1149 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | ||
1150 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); | ||
1151 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | ||
1152 | } | ||
1153 | } | ||
1154 | |||
1155 | /* | 1198 | /* |
1156 | * RX control handlers | 1199 | * RX control handlers |
1157 | */ | 1200 | */ |
@@ -1631,8 +1674,8 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = { | |||
1631 | .link_tuner = rt2400pci_link_tuner, | 1674 | .link_tuner = rt2400pci_link_tuner, |
1632 | .write_tx_desc = rt2400pci_write_tx_desc, | 1675 | .write_tx_desc = rt2400pci_write_tx_desc, |
1633 | .write_beacon = rt2400pci_write_beacon, | 1676 | .write_beacon = rt2400pci_write_beacon, |
1634 | .kick_tx_queue = rt2400pci_kick_tx_queue, | 1677 | .kick_tx_queue = rt2400pci_kick_queue, |
1635 | .kill_tx_queue = rt2400pci_kill_tx_queue, | 1678 | .kill_tx_queue = rt2400pci_stop_queue, |
1636 | .fill_rxdone = rt2400pci_fill_rxdone, | 1679 | .fill_rxdone = rt2400pci_fill_rxdone, |
1637 | .config_filter = rt2400pci_config_filter, | 1680 | .config_filter = rt2400pci_config_filter, |
1638 | .config_intf = rt2400pci_config_intf, | 1681 | .config_intf = rt2400pci_config_intf, |