diff options
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2400pci.c | 352 |
1 files changed, 176 insertions, 176 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c index b36ed1c6c746..4c0538d6099b 100644 --- a/drivers/net/wireless/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/rt2x00/rt2400pci.c | |||
@@ -277,6 +277,17 @@ static int rt2400pci_blink_set(struct led_classdev *led_cdev, | |||
277 | 277 | ||
278 | return 0; | 278 | return 0; |
279 | } | 279 | } |
280 | |||
281 | static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev, | ||
282 | struct rt2x00_led *led, | ||
283 | enum led_type type) | ||
284 | { | ||
285 | led->rt2x00dev = rt2x00dev; | ||
286 | led->type = type; | ||
287 | led->led_dev.brightness_set = rt2400pci_brightness_set; | ||
288 | led->led_dev.blink_set = rt2400pci_blink_set; | ||
289 | led->flags = LED_INITIALIZED; | ||
290 | } | ||
280 | #endif /* CONFIG_RT2400PCI_LEDS */ | 291 | #endif /* CONFIG_RT2400PCI_LEDS */ |
281 | 292 | ||
282 | /* | 293 | /* |
@@ -620,48 +631,38 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev) | |||
620 | static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev, | 631 | static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev, |
621 | struct queue_entry *entry) | 632 | struct queue_entry *entry) |
622 | { | 633 | { |
623 | struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; | 634 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
635 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | ||
624 | u32 word; | 636 | u32 word; |
625 | 637 | ||
626 | rt2x00_desc_read(priv_rx->desc, 2, &word); | 638 | rt2x00_desc_read(entry_priv->desc, 2, &word); |
627 | rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, | 639 | rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len); |
628 | entry->queue->data_size); | 640 | rt2x00_desc_write(entry_priv->desc, 2, word); |
629 | rt2x00_desc_write(priv_rx->desc, 2, word); | ||
630 | 641 | ||
631 | rt2x00_desc_read(priv_rx->desc, 1, &word); | 642 | rt2x00_desc_read(entry_priv->desc, 1, &word); |
632 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma); | 643 | rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); |
633 | rt2x00_desc_write(priv_rx->desc, 1, word); | 644 | rt2x00_desc_write(entry_priv->desc, 1, word); |
634 | 645 | ||
635 | rt2x00_desc_read(priv_rx->desc, 0, &word); | 646 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
636 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); | 647 | rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); |
637 | rt2x00_desc_write(priv_rx->desc, 0, word); | 648 | rt2x00_desc_write(entry_priv->desc, 0, word); |
638 | } | 649 | } |
639 | 650 | ||
640 | static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev, | 651 | static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev, |
641 | struct queue_entry *entry) | 652 | struct queue_entry *entry) |
642 | { | 653 | { |
643 | struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; | 654 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; |
644 | u32 word; | 655 | u32 word; |
645 | 656 | ||
646 | rt2x00_desc_read(priv_tx->desc, 1, &word); | 657 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
647 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma); | ||
648 | rt2x00_desc_write(priv_tx->desc, 1, word); | ||
649 | |||
650 | rt2x00_desc_read(priv_tx->desc, 2, &word); | ||
651 | rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, | ||
652 | entry->queue->data_size); | ||
653 | rt2x00_desc_write(priv_tx->desc, 2, word); | ||
654 | |||
655 | rt2x00_desc_read(priv_tx->desc, 0, &word); | ||
656 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); | 658 | rt2x00_set_field32(&word, TXD_W0_VALID, 0); |
657 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); | 659 | rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); |
658 | rt2x00_desc_write(priv_tx->desc, 0, word); | 660 | rt2x00_desc_write(entry_priv->desc, 0, word); |
659 | } | 661 | } |
660 | 662 | ||
661 | static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) | 663 | static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) |
662 | { | 664 | { |
663 | struct queue_entry_priv_pci_rx *priv_rx; | 665 | struct queue_entry_priv_pci *entry_priv; |
664 | struct queue_entry_priv_pci_tx *priv_tx; | ||
665 | u32 reg; | 666 | u32 reg; |
666 | 667 | ||
667 | /* | 668 | /* |
@@ -674,28 +675,28 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) | |||
674 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); | 675 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
675 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); | 676 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
676 | 677 | ||
677 | priv_tx = rt2x00dev->tx[1].entries[0].priv_data; | 678 | entry_priv = rt2x00dev->tx[1].entries[0].priv_data; |
678 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); | 679 | rt2x00pci_register_read(rt2x00dev, TXCSR3, ®); |
679 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, | 680 | rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, |
680 | priv_tx->desc_dma); | 681 | entry_priv->desc_dma); |
681 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); | 682 | rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); |
682 | 683 | ||
683 | priv_tx = rt2x00dev->tx[0].entries[0].priv_data; | 684 | entry_priv = rt2x00dev->tx[0].entries[0].priv_data; |
684 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); | 685 | rt2x00pci_register_read(rt2x00dev, TXCSR5, ®); |
685 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, | 686 | rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, |
686 | priv_tx->desc_dma); | 687 | entry_priv->desc_dma); |
687 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); | 688 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
688 | 689 | ||
689 | priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; | 690 | entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; |
690 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); | 691 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
691 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, | 692 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
692 | priv_tx->desc_dma); | 693 | entry_priv->desc_dma); |
693 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); | 694 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
694 | 695 | ||
695 | priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; | 696 | entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; |
696 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); | 697 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
697 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, | 698 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
698 | priv_tx->desc_dma); | 699 | entry_priv->desc_dma); |
699 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); | 700 | rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); |
700 | 701 | ||
701 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); | 702 | rt2x00pci_register_read(rt2x00dev, RXCSR1, ®); |
@@ -703,9 +704,10 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) | |||
703 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); | 704 | rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); |
704 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); | 705 | rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); |
705 | 706 | ||
706 | priv_rx = rt2x00dev->rx->entries[0].priv_data; | 707 | entry_priv = rt2x00dev->rx->entries[0].priv_data; |
707 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); | 708 | rt2x00pci_register_read(rt2x00dev, RXCSR2, ®); |
708 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma); | 709 | rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, |
710 | entry_priv->desc_dma); | ||
709 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); | 711 | rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); |
710 | 712 | ||
711 | return 0; | 713 | return 0; |
@@ -801,25 +803,32 @@ static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev) | |||
801 | return 0; | 803 | return 0; |
802 | } | 804 | } |
803 | 805 | ||
804 | static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) | 806 | static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) |
805 | { | 807 | { |
806 | unsigned int i; | 808 | unsigned int i; |
807 | u16 eeprom; | ||
808 | u8 reg_id; | ||
809 | u8 value; | 809 | u8 value; |
810 | 810 | ||
811 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { | 811 | for (i = 0; i < REGISTER_BUSY_COUNT; i++) { |
812 | rt2400pci_bbp_read(rt2x00dev, 0, &value); | 812 | rt2400pci_bbp_read(rt2x00dev, 0, &value); |
813 | if ((value != 0xff) && (value != 0x00)) | 813 | if ((value != 0xff) && (value != 0x00)) |
814 | goto continue_csr_init; | 814 | return 0; |
815 | NOTICE(rt2x00dev, "Waiting for BBP register.\n"); | ||
816 | udelay(REGISTER_BUSY_DELAY); | 815 | udelay(REGISTER_BUSY_DELAY); |
817 | } | 816 | } |
818 | 817 | ||
819 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); | 818 | ERROR(rt2x00dev, "BBP register access failed, aborting.\n"); |
820 | return -EACCES; | 819 | return -EACCES; |
820 | } | ||
821 | |||
822 | static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev) | ||
823 | { | ||
824 | unsigned int i; | ||
825 | u16 eeprom; | ||
826 | u8 reg_id; | ||
827 | u8 value; | ||
828 | |||
829 | if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev))) | ||
830 | return -EACCES; | ||
821 | 831 | ||
822 | continue_csr_init: | ||
823 | rt2400pci_bbp_write(rt2x00dev, 1, 0x00); | 832 | rt2400pci_bbp_write(rt2x00dev, 1, 0x00); |
824 | rt2400pci_bbp_write(rt2x00dev, 3, 0x27); | 833 | rt2400pci_bbp_write(rt2x00dev, 3, 0x27); |
825 | rt2400pci_bbp_write(rt2x00dev, 4, 0x08); | 834 | rt2400pci_bbp_write(rt2x00dev, 4, 0x08); |
@@ -858,7 +867,8 @@ static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev, | |||
858 | 867 | ||
859 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); | 868 | rt2x00pci_register_read(rt2x00dev, RXCSR0, ®); |
860 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, | 869 | rt2x00_set_field32(®, RXCSR0_DISABLE_RX, |
861 | state == STATE_RADIO_RX_OFF); | 870 | (state == STATE_RADIO_RX_OFF) || |
871 | (state == STATE_RADIO_RX_OFF_LINK)); | ||
862 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); | 872 | rt2x00pci_register_write(rt2x00dev, RXCSR0, reg); |
863 | } | 873 | } |
864 | 874 | ||
@@ -895,17 +905,10 @@ static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev) | |||
895 | /* | 905 | /* |
896 | * Initialize all registers. | 906 | * Initialize all registers. |
897 | */ | 907 | */ |
898 | if (rt2400pci_init_queues(rt2x00dev) || | 908 | if (unlikely(rt2400pci_init_queues(rt2x00dev) || |
899 | rt2400pci_init_registers(rt2x00dev) || | 909 | rt2400pci_init_registers(rt2x00dev) || |
900 | rt2400pci_init_bbp(rt2x00dev)) { | 910 | rt2400pci_init_bbp(rt2x00dev))) |
901 | ERROR(rt2x00dev, "Register initialization failed.\n"); | ||
902 | return -EIO; | 911 | return -EIO; |
903 | } | ||
904 | |||
905 | /* | ||
906 | * Enable interrupts. | ||
907 | */ | ||
908 | rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON); | ||
909 | 912 | ||
910 | return 0; | 913 | return 0; |
911 | } | 914 | } |
@@ -927,11 +930,6 @@ static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev) | |||
927 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | 930 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); |
928 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); | 931 | rt2x00_set_field32(®, TXCSR0_ABORT, 1); |
929 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | 932 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); |
930 | |||
931 | /* | ||
932 | * Disable interrupts. | ||
933 | */ | ||
934 | rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF); | ||
935 | } | 933 | } |
936 | 934 | ||
937 | static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, | 935 | static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, |
@@ -966,10 +964,6 @@ static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev, | |||
966 | msleep(10); | 964 | msleep(10); |
967 | } | 965 | } |
968 | 966 | ||
969 | NOTICE(rt2x00dev, "Device failed to enter state %d, " | ||
970 | "current device state: bbp %d and rf %d.\n", | ||
971 | state, bbp_state, rf_state); | ||
972 | |||
973 | return -EBUSY; | 967 | return -EBUSY; |
974 | } | 968 | } |
975 | 969 | ||
@@ -987,11 +981,13 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
987 | break; | 981 | break; |
988 | case STATE_RADIO_RX_ON: | 982 | case STATE_RADIO_RX_ON: |
989 | case STATE_RADIO_RX_ON_LINK: | 983 | case STATE_RADIO_RX_ON_LINK: |
990 | rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON); | ||
991 | break; | ||
992 | case STATE_RADIO_RX_OFF: | 984 | case STATE_RADIO_RX_OFF: |
993 | case STATE_RADIO_RX_OFF_LINK: | 985 | case STATE_RADIO_RX_OFF_LINK: |
994 | rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF); | 986 | rt2400pci_toggle_rx(rt2x00dev, state); |
987 | break; | ||
988 | case STATE_RADIO_IRQ_ON: | ||
989 | case STATE_RADIO_IRQ_OFF: | ||
990 | rt2400pci_toggle_irq(rt2x00dev, state); | ||
995 | break; | 991 | break; |
996 | case STATE_DEEP_SLEEP: | 992 | case STATE_DEEP_SLEEP: |
997 | case STATE_SLEEP: | 993 | case STATE_SLEEP: |
@@ -1004,6 +1000,10 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1004 | break; | 1000 | break; |
1005 | } | 1001 | } |
1006 | 1002 | ||
1003 | if (unlikely(retval)) | ||
1004 | ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n", | ||
1005 | state, retval); | ||
1006 | |||
1007 | return retval; | 1007 | return retval; |
1008 | } | 1008 | } |
1009 | 1009 | ||
@@ -1012,18 +1012,23 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev, | |||
1012 | */ | 1012 | */ |
1013 | static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | 1013 | static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, |
1014 | struct sk_buff *skb, | 1014 | struct sk_buff *skb, |
1015 | struct txentry_desc *txdesc, | 1015 | struct txentry_desc *txdesc) |
1016 | struct ieee80211_tx_control *control) | ||
1017 | { | 1016 | { |
1018 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); | 1017 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); |
1018 | struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; | ||
1019 | __le32 *txd = skbdesc->desc; | 1019 | __le32 *txd = skbdesc->desc; |
1020 | u32 word; | 1020 | u32 word; |
1021 | 1021 | ||
1022 | /* | 1022 | /* |
1023 | * Start writing the descriptor words. | 1023 | * Start writing the descriptor words. |
1024 | */ | 1024 | */ |
1025 | rt2x00_desc_read(entry_priv->desc, 1, &word); | ||
1026 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); | ||
1027 | rt2x00_desc_write(entry_priv->desc, 1, word); | ||
1028 | |||
1025 | rt2x00_desc_read(txd, 2, &word); | 1029 | rt2x00_desc_read(txd, 2, &word); |
1026 | rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len); | 1030 | rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len); |
1031 | rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len); | ||
1027 | rt2x00_desc_write(txd, 2, word); | 1032 | rt2x00_desc_write(txd, 2, word); |
1028 | 1033 | ||
1029 | rt2x00_desc_read(txd, 3, &word); | 1034 | rt2x00_desc_read(txd, 3, &word); |
@@ -1057,20 +1062,53 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |||
1057 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); | 1062 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); |
1058 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); | 1063 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
1059 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, | 1064 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
1060 | !!(control->flags & | 1065 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
1061 | IEEE80211_TXCTL_LONG_RETRY_LIMIT)); | ||
1062 | rt2x00_desc_write(txd, 0, word); | 1066 | rt2x00_desc_write(txd, 0, word); |
1063 | } | 1067 | } |
1064 | 1068 | ||
1065 | /* | 1069 | /* |
1066 | * TX data initialization | 1070 | * TX data initialization |
1067 | */ | 1071 | */ |
1072 | static void rt2400pci_write_beacon(struct queue_entry *entry) | ||
1073 | { | ||
1074 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | ||
1075 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; | ||
1076 | struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); | ||
1077 | u32 word; | ||
1078 | u32 reg; | ||
1079 | |||
1080 | /* | ||
1081 | * Disable beaconing while we are reloading the beacon data, | ||
1082 | * otherwise we might be sending out invalid data. | ||
1083 | */ | ||
1084 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | ||
1085 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); | ||
1086 | rt2x00_set_field32(®, CSR14_TBCN, 0); | ||
1087 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | ||
1088 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | ||
1089 | |||
1090 | /* | ||
1091 | * Replace rt2x00lib allocated descriptor with the | ||
1092 | * pointer to the _real_ hardware descriptor. | ||
1093 | * After that, map the beacon to DMA and update the | ||
1094 | * descriptor. | ||
1095 | */ | ||
1096 | memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len); | ||
1097 | skbdesc->desc = entry_priv->desc; | ||
1098 | |||
1099 | rt2x00queue_map_txskb(rt2x00dev, entry->skb); | ||
1100 | |||
1101 | rt2x00_desc_read(entry_priv->desc, 1, &word); | ||
1102 | rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); | ||
1103 | rt2x00_desc_write(entry_priv->desc, 1, word); | ||
1104 | } | ||
1105 | |||
1068 | static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, | 1106 | static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, |
1069 | const unsigned int queue) | 1107 | const enum data_queue_qid queue) |
1070 | { | 1108 | { |
1071 | u32 reg; | 1109 | u32 reg; |
1072 | 1110 | ||
1073 | if (queue == RT2X00_BCN_QUEUE_BEACON) { | 1111 | if (queue == QID_BEACON) { |
1074 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | 1112 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); |
1075 | if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) { | 1113 | if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) { |
1076 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); | 1114 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); |
@@ -1082,12 +1120,9 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, | |||
1082 | } | 1120 | } |
1083 | 1121 | ||
1084 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); | 1122 | rt2x00pci_register_read(rt2x00dev, TXCSR0, ®); |
1085 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, | 1123 | rt2x00_set_field32(®, TXCSR0_KICK_PRIO, (queue == QID_AC_BE)); |
1086 | (queue == IEEE80211_TX_QUEUE_DATA0)); | 1124 | rt2x00_set_field32(®, TXCSR0_KICK_TX, (queue == QID_AC_BK)); |
1087 | rt2x00_set_field32(®, TXCSR0_KICK_TX, | 1125 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, (queue == QID_ATIM)); |
1088 | (queue == IEEE80211_TX_QUEUE_DATA1)); | ||
1089 | rt2x00_set_field32(®, TXCSR0_KICK_ATIM, | ||
1090 | (queue == RT2X00_BCN_QUEUE_ATIM)); | ||
1091 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); | 1126 | rt2x00pci_register_write(rt2x00dev, TXCSR0, reg); |
1092 | } | 1127 | } |
1093 | 1128 | ||
@@ -1097,32 +1132,54 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, | |||
1097 | static void rt2400pci_fill_rxdone(struct queue_entry *entry, | 1132 | static void rt2400pci_fill_rxdone(struct queue_entry *entry, |
1098 | struct rxdone_entry_desc *rxdesc) | 1133 | struct rxdone_entry_desc *rxdesc) |
1099 | { | 1134 | { |
1100 | struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; | 1135 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
1136 | struct queue_entry_priv_pci *entry_priv = entry->priv_data; | ||
1101 | u32 word0; | 1137 | u32 word0; |
1102 | u32 word2; | 1138 | u32 word2; |
1103 | u32 word3; | 1139 | u32 word3; |
1140 | u32 word4; | ||
1141 | u64 tsf; | ||
1142 | u32 rx_low; | ||
1143 | u32 rx_high; | ||
1104 | 1144 | ||
1105 | rt2x00_desc_read(priv_rx->desc, 0, &word0); | 1145 | rt2x00_desc_read(entry_priv->desc, 0, &word0); |
1106 | rt2x00_desc_read(priv_rx->desc, 2, &word2); | 1146 | rt2x00_desc_read(entry_priv->desc, 2, &word2); |
1107 | rt2x00_desc_read(priv_rx->desc, 3, &word3); | 1147 | rt2x00_desc_read(entry_priv->desc, 3, &word3); |
1148 | rt2x00_desc_read(entry_priv->desc, 4, &word4); | ||
1108 | 1149 | ||
1109 | rxdesc->flags = 0; | ||
1110 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) | 1150 | if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) |
1111 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; | 1151 | rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; |
1112 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) | 1152 | if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) |
1113 | rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; | 1153 | rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; |
1114 | 1154 | ||
1115 | /* | 1155 | /* |
1156 | * We only get the lower 32bits from the timestamp, | ||
1157 | * to get the full 64bits we must complement it with | ||
1158 | * the timestamp from get_tsf(). | ||
1159 | * Note that when a wraparound of the lower 32bits | ||
1160 | * has occurred between the frame arrival and the get_tsf() | ||
1161 | * call, we must decrease the higher 32bits with 1 to get | ||
1162 | * to correct value. | ||
1163 | */ | ||
1164 | tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw); | ||
1165 | rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME); | ||
1166 | rx_high = upper_32_bits(tsf); | ||
1167 | |||
1168 | if ((u32)tsf <= rx_low) | ||
1169 | rx_high--; | ||
1170 | |||
1171 | /* | ||
1116 | * Obtain the status about this packet. | 1172 | * Obtain the status about this packet. |
1117 | * The signal is the PLCP value, and needs to be stripped | 1173 | * The signal is the PLCP value, and needs to be stripped |
1118 | * of the preamble bit (0x08). | 1174 | * of the preamble bit (0x08). |
1119 | */ | 1175 | */ |
1176 | rxdesc->timestamp = ((u64)rx_high << 32) | rx_low; | ||
1120 | rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08; | 1177 | rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08; |
1121 | rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) - | 1178 | rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) - |
1122 | entry->queue->rt2x00dev->rssi_offset; | 1179 | entry->queue->rt2x00dev->rssi_offset; |
1123 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); | 1180 | rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); |
1124 | 1181 | ||
1125 | rxdesc->dev_flags = RXDONE_SIGNAL_PLCP; | 1182 | rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; |
1126 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) | 1183 | if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) |
1127 | rxdesc->dev_flags |= RXDONE_MY_BSS; | 1184 | rxdesc->dev_flags |= RXDONE_MY_BSS; |
1128 | } | 1185 | } |
@@ -1131,18 +1188,18 @@ static void rt2400pci_fill_rxdone(struct queue_entry *entry, | |||
1131 | * Interrupt functions. | 1188 | * Interrupt functions. |
1132 | */ | 1189 | */ |
1133 | static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, | 1190 | static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, |
1134 | const enum ieee80211_tx_queue queue_idx) | 1191 | const enum data_queue_qid queue_idx) |
1135 | { | 1192 | { |
1136 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); | 1193 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); |
1137 | struct queue_entry_priv_pci_tx *priv_tx; | 1194 | struct queue_entry_priv_pci *entry_priv; |
1138 | struct queue_entry *entry; | 1195 | struct queue_entry *entry; |
1139 | struct txdone_entry_desc txdesc; | 1196 | struct txdone_entry_desc txdesc; |
1140 | u32 word; | 1197 | u32 word; |
1141 | 1198 | ||
1142 | while (!rt2x00queue_empty(queue)) { | 1199 | while (!rt2x00queue_empty(queue)) { |
1143 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); | 1200 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); |
1144 | priv_tx = entry->priv_data; | 1201 | entry_priv = entry->priv_data; |
1145 | rt2x00_desc_read(priv_tx->desc, 0, &word); | 1202 | rt2x00_desc_read(entry_priv->desc, 0, &word); |
1146 | 1203 | ||
1147 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || | 1204 | if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || |
1148 | !rt2x00_get_field32(word, TXD_W0_VALID)) | 1205 | !rt2x00_get_field32(word, TXD_W0_VALID)) |
@@ -1151,10 +1208,21 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, | |||
1151 | /* | 1208 | /* |
1152 | * Obtain the status about this packet. | 1209 | * Obtain the status about this packet. |
1153 | */ | 1210 | */ |
1154 | txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT); | 1211 | txdesc.flags = 0; |
1212 | switch (rt2x00_get_field32(word, TXD_W0_RESULT)) { | ||
1213 | case 0: /* Success */ | ||
1214 | case 1: /* Success with retry */ | ||
1215 | __set_bit(TXDONE_SUCCESS, &txdesc.flags); | ||
1216 | break; | ||
1217 | case 2: /* Failure, excessive retries */ | ||
1218 | __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags); | ||
1219 | /* Don't break, this is a failed frame! */ | ||
1220 | default: /* Failure */ | ||
1221 | __set_bit(TXDONE_FAILURE, &txdesc.flags); | ||
1222 | } | ||
1155 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); | 1223 | txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); |
1156 | 1224 | ||
1157 | rt2x00pci_txdone(rt2x00dev, entry, &txdesc); | 1225 | rt2x00lib_txdone(entry, &txdesc); |
1158 | } | 1226 | } |
1159 | } | 1227 | } |
1160 | 1228 | ||
@@ -1198,19 +1266,19 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) | |||
1198 | * 3 - Atim ring transmit done interrupt. | 1266 | * 3 - Atim ring transmit done interrupt. |
1199 | */ | 1267 | */ |
1200 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) | 1268 | if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING)) |
1201 | rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM); | 1269 | rt2400pci_txdone(rt2x00dev, QID_ATIM); |
1202 | 1270 | ||
1203 | /* | 1271 | /* |
1204 | * 4 - Priority ring transmit done interrupt. | 1272 | * 4 - Priority ring transmit done interrupt. |
1205 | */ | 1273 | */ |
1206 | if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) | 1274 | if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING)) |
1207 | rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0); | 1275 | rt2400pci_txdone(rt2x00dev, QID_AC_BE); |
1208 | 1276 | ||
1209 | /* | 1277 | /* |
1210 | * 5 - Tx ring transmit done interrupt. | 1278 | * 5 - Tx ring transmit done interrupt. |
1211 | */ | 1279 | */ |
1212 | if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) | 1280 | if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) |
1213 | rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1); | 1281 | rt2400pci_txdone(rt2x00dev, QID_AC_BK); |
1214 | 1282 | ||
1215 | return IRQ_HANDLED; | 1283 | return IRQ_HANDLED; |
1216 | } | 1284 | } |
@@ -1309,23 +1377,10 @@ static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev) | |||
1309 | #ifdef CONFIG_RT2400PCI_LEDS | 1377 | #ifdef CONFIG_RT2400PCI_LEDS |
1310 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); | 1378 | value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE); |
1311 | 1379 | ||
1312 | rt2x00dev->led_radio.rt2x00dev = rt2x00dev; | 1380 | rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); |
1313 | rt2x00dev->led_radio.type = LED_TYPE_RADIO; | 1381 | if (value == LED_MODE_TXRX_ACTIVITY) |
1314 | rt2x00dev->led_radio.led_dev.brightness_set = | 1382 | rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual, |
1315 | rt2400pci_brightness_set; | 1383 | LED_TYPE_ACTIVITY); |
1316 | rt2x00dev->led_radio.led_dev.blink_set = | ||
1317 | rt2400pci_blink_set; | ||
1318 | rt2x00dev->led_radio.flags = LED_INITIALIZED; | ||
1319 | |||
1320 | if (value == LED_MODE_TXRX_ACTIVITY) { | ||
1321 | rt2x00dev->led_qual.rt2x00dev = rt2x00dev; | ||
1322 | rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY; | ||
1323 | rt2x00dev->led_qual.led_dev.brightness_set = | ||
1324 | rt2400pci_brightness_set; | ||
1325 | rt2x00dev->led_qual.led_dev.blink_set = | ||
1326 | rt2400pci_blink_set; | ||
1327 | rt2x00dev->led_qual.flags = LED_INITIALIZED; | ||
1328 | } | ||
1329 | #endif /* CONFIG_RT2400PCI_LEDS */ | 1384 | #endif /* CONFIG_RT2400PCI_LEDS */ |
1330 | 1385 | ||
1331 | /* | 1386 | /* |
@@ -1375,13 +1430,11 @@ static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) | |||
1375 | /* | 1430 | /* |
1376 | * Initialize all hw fields. | 1431 | * Initialize all hw fields. |
1377 | */ | 1432 | */ |
1378 | rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING; | 1433 | rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
1434 | IEEE80211_HW_SIGNAL_DBM; | ||
1379 | rt2x00dev->hw->extra_tx_headroom = 0; | 1435 | rt2x00dev->hw->extra_tx_headroom = 0; |
1380 | rt2x00dev->hw->max_signal = MAX_SIGNAL; | ||
1381 | rt2x00dev->hw->max_rssi = MAX_RX_SSI; | ||
1382 | rt2x00dev->hw->queues = 2; | ||
1383 | 1436 | ||
1384 | SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); | 1437 | SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); |
1385 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, | 1438 | SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, |
1386 | rt2x00_eeprom_addr(rt2x00dev, | 1439 | rt2x00_eeprom_addr(rt2x00dev, |
1387 | EEPROM_MAC_ADDR_0)); | 1440 | EEPROM_MAC_ADDR_0)); |
@@ -1427,9 +1480,10 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |||
1427 | rt2400pci_probe_hw_mode(rt2x00dev); | 1480 | rt2400pci_probe_hw_mode(rt2x00dev); |
1428 | 1481 | ||
1429 | /* | 1482 | /* |
1430 | * This device requires the atim queue | 1483 | * This device requires the atim queue and DMA-mapped skbs. |
1431 | */ | 1484 | */ |
1432 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); | 1485 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); |
1486 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); | ||
1433 | 1487 | ||
1434 | /* | 1488 | /* |
1435 | * Set the rssi offset. | 1489 | * Set the rssi offset. |
@@ -1456,8 +1510,7 @@ static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw, | |||
1456 | return 0; | 1510 | return 0; |
1457 | } | 1511 | } |
1458 | 1512 | ||
1459 | static int rt2400pci_conf_tx(struct ieee80211_hw *hw, | 1513 | static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue, |
1460 | int queue, | ||
1461 | const struct ieee80211_tx_queue_params *params) | 1514 | const struct ieee80211_tx_queue_params *params) |
1462 | { | 1515 | { |
1463 | struct rt2x00_dev *rt2x00dev = hw->priv; | 1516 | struct rt2x00_dev *rt2x00dev = hw->priv; |
@@ -1467,7 +1520,7 @@ static int rt2400pci_conf_tx(struct ieee80211_hw *hw, | |||
1467 | * per queue. So by default we only configure the TX queue, | 1520 | * per queue. So by default we only configure the TX queue, |
1468 | * and ignore all other configurations. | 1521 | * and ignore all other configurations. |
1469 | */ | 1522 | */ |
1470 | if (queue != IEEE80211_TX_QUEUE_DATA0) | 1523 | if (queue != 0) |
1471 | return -EINVAL; | 1524 | return -EINVAL; |
1472 | 1525 | ||
1473 | if (rt2x00mac_conf_tx(hw, queue, params)) | 1526 | if (rt2x00mac_conf_tx(hw, queue, params)) |
@@ -1496,60 +1549,6 @@ static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw) | |||
1496 | return tsf; | 1549 | return tsf; |
1497 | } | 1550 | } |
1498 | 1551 | ||
1499 | static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, | ||
1500 | struct ieee80211_tx_control *control) | ||
1501 | { | ||
1502 | struct rt2x00_dev *rt2x00dev = hw->priv; | ||
1503 | struct rt2x00_intf *intf = vif_to_intf(control->vif); | ||
1504 | struct queue_entry_priv_pci_tx *priv_tx; | ||
1505 | struct skb_frame_desc *skbdesc; | ||
1506 | u32 reg; | ||
1507 | |||
1508 | if (unlikely(!intf->beacon)) | ||
1509 | return -ENOBUFS; | ||
1510 | priv_tx = intf->beacon->priv_data; | ||
1511 | |||
1512 | /* | ||
1513 | * Fill in skb descriptor | ||
1514 | */ | ||
1515 | skbdesc = get_skb_frame_desc(skb); | ||
1516 | memset(skbdesc, 0, sizeof(*skbdesc)); | ||
1517 | skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED; | ||
1518 | skbdesc->data = skb->data; | ||
1519 | skbdesc->data_len = skb->len; | ||
1520 | skbdesc->desc = priv_tx->desc; | ||
1521 | skbdesc->desc_len = intf->beacon->queue->desc_size; | ||
1522 | skbdesc->entry = intf->beacon; | ||
1523 | |||
1524 | /* | ||
1525 | * Disable beaconing while we are reloading the beacon data, | ||
1526 | * otherwise we might be sending out invalid data. | ||
1527 | */ | ||
1528 | rt2x00pci_register_read(rt2x00dev, CSR14, ®); | ||
1529 | rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); | ||
1530 | rt2x00_set_field32(®, CSR14_TBCN, 0); | ||
1531 | rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); | ||
1532 | rt2x00pci_register_write(rt2x00dev, CSR14, reg); | ||
1533 | |||
1534 | /* | ||
1535 | * mac80211 doesn't provide the control->queue variable | ||
1536 | * for beacons. Set our own queue identification so | ||
1537 | * it can be used during descriptor initialization. | ||
1538 | */ | ||
1539 | control->queue = RT2X00_BCN_QUEUE_BEACON; | ||
1540 | rt2x00lib_write_tx_desc(rt2x00dev, skb, control); | ||
1541 | |||
1542 | /* | ||
1543 | * Enable beacon generation. | ||
1544 | * Write entire beacon with descriptor to register, | ||
1545 | * and kick the beacon generator. | ||
1546 | */ | ||
1547 | memcpy(priv_tx->data, skb->data, skb->len); | ||
1548 | rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue); | ||
1549 | |||
1550 | return 0; | ||
1551 | } | ||
1552 | |||
1553 | static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw) | 1552 | static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw) |
1554 | { | 1553 | { |
1555 | struct rt2x00_dev *rt2x00dev = hw->priv; | 1554 | struct rt2x00_dev *rt2x00dev = hw->priv; |
@@ -1574,7 +1573,6 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = { | |||
1574 | .conf_tx = rt2400pci_conf_tx, | 1573 | .conf_tx = rt2400pci_conf_tx, |
1575 | .get_tx_stats = rt2x00mac_get_tx_stats, | 1574 | .get_tx_stats = rt2x00mac_get_tx_stats, |
1576 | .get_tsf = rt2400pci_get_tsf, | 1575 | .get_tsf = rt2400pci_get_tsf, |
1577 | .beacon_update = rt2400pci_beacon_update, | ||
1578 | .tx_last_beacon = rt2400pci_tx_last_beacon, | 1576 | .tx_last_beacon = rt2400pci_tx_last_beacon, |
1579 | }; | 1577 | }; |
1580 | 1578 | ||
@@ -1592,6 +1590,7 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = { | |||
1592 | .link_tuner = rt2400pci_link_tuner, | 1590 | .link_tuner = rt2400pci_link_tuner, |
1593 | .write_tx_desc = rt2400pci_write_tx_desc, | 1591 | .write_tx_desc = rt2400pci_write_tx_desc, |
1594 | .write_tx_data = rt2x00pci_write_tx_data, | 1592 | .write_tx_data = rt2x00pci_write_tx_data, |
1593 | .write_beacon = rt2400pci_write_beacon, | ||
1595 | .kick_tx_queue = rt2400pci_kick_tx_queue, | 1594 | .kick_tx_queue = rt2400pci_kick_tx_queue, |
1596 | .fill_rxdone = rt2400pci_fill_rxdone, | 1595 | .fill_rxdone = rt2400pci_fill_rxdone, |
1597 | .config_filter = rt2400pci_config_filter, | 1596 | .config_filter = rt2400pci_config_filter, |
@@ -1604,28 +1603,28 @@ static const struct data_queue_desc rt2400pci_queue_rx = { | |||
1604 | .entry_num = RX_ENTRIES, | 1603 | .entry_num = RX_ENTRIES, |
1605 | .data_size = DATA_FRAME_SIZE, | 1604 | .data_size = DATA_FRAME_SIZE, |
1606 | .desc_size = RXD_DESC_SIZE, | 1605 | .desc_size = RXD_DESC_SIZE, |
1607 | .priv_size = sizeof(struct queue_entry_priv_pci_rx), | 1606 | .priv_size = sizeof(struct queue_entry_priv_pci), |
1608 | }; | 1607 | }; |
1609 | 1608 | ||
1610 | static const struct data_queue_desc rt2400pci_queue_tx = { | 1609 | static const struct data_queue_desc rt2400pci_queue_tx = { |
1611 | .entry_num = TX_ENTRIES, | 1610 | .entry_num = TX_ENTRIES, |
1612 | .data_size = DATA_FRAME_SIZE, | 1611 | .data_size = DATA_FRAME_SIZE, |
1613 | .desc_size = TXD_DESC_SIZE, | 1612 | .desc_size = TXD_DESC_SIZE, |
1614 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | 1613 | .priv_size = sizeof(struct queue_entry_priv_pci), |
1615 | }; | 1614 | }; |
1616 | 1615 | ||
1617 | static const struct data_queue_desc rt2400pci_queue_bcn = { | 1616 | static const struct data_queue_desc rt2400pci_queue_bcn = { |
1618 | .entry_num = BEACON_ENTRIES, | 1617 | .entry_num = BEACON_ENTRIES, |
1619 | .data_size = MGMT_FRAME_SIZE, | 1618 | .data_size = MGMT_FRAME_SIZE, |
1620 | .desc_size = TXD_DESC_SIZE, | 1619 | .desc_size = TXD_DESC_SIZE, |
1621 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | 1620 | .priv_size = sizeof(struct queue_entry_priv_pci), |
1622 | }; | 1621 | }; |
1623 | 1622 | ||
1624 | static const struct data_queue_desc rt2400pci_queue_atim = { | 1623 | static const struct data_queue_desc rt2400pci_queue_atim = { |
1625 | .entry_num = ATIM_ENTRIES, | 1624 | .entry_num = ATIM_ENTRIES, |
1626 | .data_size = DATA_FRAME_SIZE, | 1625 | .data_size = DATA_FRAME_SIZE, |
1627 | .desc_size = TXD_DESC_SIZE, | 1626 | .desc_size = TXD_DESC_SIZE, |
1628 | .priv_size = sizeof(struct queue_entry_priv_pci_tx), | 1627 | .priv_size = sizeof(struct queue_entry_priv_pci), |
1629 | }; | 1628 | }; |
1630 | 1629 | ||
1631 | static const struct rt2x00_ops rt2400pci_ops = { | 1630 | static const struct rt2x00_ops rt2400pci_ops = { |
@@ -1634,6 +1633,7 @@ static const struct rt2x00_ops rt2400pci_ops = { | |||
1634 | .max_ap_intf = 1, | 1633 | .max_ap_intf = 1, |
1635 | .eeprom_size = EEPROM_SIZE, | 1634 | .eeprom_size = EEPROM_SIZE, |
1636 | .rf_size = RF_SIZE, | 1635 | .rf_size = RF_SIZE, |
1636 | .tx_queues = NUM_TX_QUEUES, | ||
1637 | .rx = &rt2400pci_queue_rx, | 1637 | .rx = &rt2400pci_queue_rx, |
1638 | .tx = &rt2400pci_queue_tx, | 1638 | .tx = &rt2400pci_queue_tx, |
1639 | .bcn = &rt2400pci_queue_bcn, | 1639 | .bcn = &rt2400pci_queue_bcn, |