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path: root/drivers/net/wireless/rt2x00/rt2400pci.c
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Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c132
1 files changed, 73 insertions, 59 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index afa565c63621..900140d3b304 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -620,48 +620,38 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
620static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev, 620static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
621 struct queue_entry *entry) 621 struct queue_entry *entry)
622{ 622{
623 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 623 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
624 u32 word; 624 u32 word;
625 625
626 rt2x00_desc_read(priv_rx->desc, 2, &word); 626 rt2x00_desc_read(entry_priv->desc, 2, &word);
627 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, 627 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
628 entry->queue->data_size); 628 entry->queue->data_size);
629 rt2x00_desc_write(priv_rx->desc, 2, word); 629 rt2x00_desc_write(entry_priv->desc, 2, word);
630 630
631 rt2x00_desc_read(priv_rx->desc, 1, &word); 631 rt2x00_desc_read(entry_priv->desc, 1, &word);
632 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma); 632 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
633 rt2x00_desc_write(priv_rx->desc, 1, word); 633 rt2x00_desc_write(entry_priv->desc, 1, word);
634 634
635 rt2x00_desc_read(priv_rx->desc, 0, &word); 635 rt2x00_desc_read(entry_priv->desc, 0, &word);
636 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); 636 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
637 rt2x00_desc_write(priv_rx->desc, 0, word); 637 rt2x00_desc_write(entry_priv->desc, 0, word);
638} 638}
639 639
640static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev, 640static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
641 struct queue_entry *entry) 641 struct queue_entry *entry)
642{ 642{
643 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data; 643 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
644 u32 word; 644 u32 word;
645 645
646 rt2x00_desc_read(priv_tx->desc, 1, &word); 646 rt2x00_desc_read(entry_priv->desc, 0, &word);
647 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
648 rt2x00_desc_write(priv_tx->desc, 1, word);
649
650 rt2x00_desc_read(priv_tx->desc, 2, &word);
651 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
652 entry->queue->data_size);
653 rt2x00_desc_write(priv_tx->desc, 2, word);
654
655 rt2x00_desc_read(priv_tx->desc, 0, &word);
656 rt2x00_set_field32(&word, TXD_W0_VALID, 0); 647 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
657 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); 648 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
658 rt2x00_desc_write(priv_tx->desc, 0, word); 649 rt2x00_desc_write(entry_priv->desc, 0, word);
659} 650}
660 651
661static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) 652static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
662{ 653{
663 struct queue_entry_priv_pci_rx *priv_rx; 654 struct queue_entry_priv_pci *entry_priv;
664 struct queue_entry_priv_pci_tx *priv_tx;
665 u32 reg; 655 u32 reg;
666 656
667 /* 657 /*
@@ -674,28 +664,28 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
674 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); 664 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
675 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); 665 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
676 666
677 priv_tx = rt2x00dev->tx[1].entries[0].priv_data; 667 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
678 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg); 668 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
679 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, 669 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
680 priv_tx->desc_dma); 670 entry_priv->desc_dma);
681 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg); 671 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
682 672
683 priv_tx = rt2x00dev->tx[0].entries[0].priv_data; 673 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
684 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg); 674 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
685 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, 675 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
686 priv_tx->desc_dma); 676 entry_priv->desc_dma);
687 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); 677 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
688 678
689 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data; 679 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
690 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg); 680 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
691 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, 681 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
692 priv_tx->desc_dma); 682 entry_priv->desc_dma);
693 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); 683 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
694 684
695 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data; 685 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
696 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg); 686 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
697 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, 687 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
698 priv_tx->desc_dma); 688 entry_priv->desc_dma);
699 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg); 689 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
700 690
701 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg); 691 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
@@ -703,9 +693,10 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
703 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); 693 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
704 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg); 694 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
705 695
706 priv_rx = rt2x00dev->rx->entries[0].priv_data; 696 entry_priv = rt2x00dev->rx->entries[0].priv_data;
707 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg); 697 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
708 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma); 698 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
699 entry_priv->desc_dma);
709 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg); 700 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
710 701
711 return 0; 702 return 0;
@@ -1001,17 +992,22 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1001 */ 992 */
1002static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 993static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1003 struct sk_buff *skb, 994 struct sk_buff *skb,
1004 struct txentry_desc *txdesc, 995 struct txentry_desc *txdesc)
1005 struct ieee80211_tx_control *control)
1006{ 996{
1007 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 997 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
998 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1008 __le32 *txd = skbdesc->desc; 999 __le32 *txd = skbdesc->desc;
1009 u32 word; 1000 u32 word;
1010 1001
1011 /* 1002 /*
1012 * Start writing the descriptor words. 1003 * Start writing the descriptor words.
1013 */ 1004 */
1005 rt2x00_desc_read(entry_priv->desc, 1, &word);
1006 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
1007 rt2x00_desc_write(entry_priv->desc, 1, word);
1008
1014 rt2x00_desc_read(txd, 2, &word); 1009 rt2x00_desc_read(txd, 2, &word);
1010 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skbdesc->data_len);
1015 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len); 1011 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
1016 rt2x00_desc_write(txd, 2, word); 1012 rt2x00_desc_write(txd, 2, word);
1017 1013
@@ -1046,8 +1042,7 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1046 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); 1042 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1047 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1043 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1048 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1044 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1049 !!(control->flags & 1045 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1050 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1051 rt2x00_desc_write(txd, 0, word); 1046 rt2x00_desc_write(txd, 0, word);
1052} 1047}
1053 1048
@@ -1083,16 +1078,15 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1083static void rt2400pci_fill_rxdone(struct queue_entry *entry, 1078static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1084 struct rxdone_entry_desc *rxdesc) 1079 struct rxdone_entry_desc *rxdesc)
1085{ 1080{
1086 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data; 1081 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1087 u32 word0; 1082 u32 word0;
1088 u32 word2; 1083 u32 word2;
1089 u32 word3; 1084 u32 word3;
1090 1085
1091 rt2x00_desc_read(priv_rx->desc, 0, &word0); 1086 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1092 rt2x00_desc_read(priv_rx->desc, 2, &word2); 1087 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1093 rt2x00_desc_read(priv_rx->desc, 3, &word3); 1088 rt2x00_desc_read(entry_priv->desc, 3, &word3);
1094 1089
1095 rxdesc->flags = 0;
1096 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1090 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1097 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1091 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1098 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1092 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
@@ -1108,7 +1102,7 @@ static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1108 entry->queue->rt2x00dev->rssi_offset; 1102 entry->queue->rt2x00dev->rssi_offset;
1109 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); 1103 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1110 1104
1111 rxdesc->dev_flags = RXDONE_SIGNAL_PLCP; 1105 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1112 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS)) 1106 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1113 rxdesc->dev_flags |= RXDONE_MY_BSS; 1107 rxdesc->dev_flags |= RXDONE_MY_BSS;
1114} 1108}
@@ -1120,15 +1114,15 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1120 const enum data_queue_qid queue_idx) 1114 const enum data_queue_qid queue_idx)
1121{ 1115{
1122 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); 1116 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1123 struct queue_entry_priv_pci_tx *priv_tx; 1117 struct queue_entry_priv_pci *entry_priv;
1124 struct queue_entry *entry; 1118 struct queue_entry *entry;
1125 struct txdone_entry_desc txdesc; 1119 struct txdone_entry_desc txdesc;
1126 u32 word; 1120 u32 word;
1127 1121
1128 while (!rt2x00queue_empty(queue)) { 1122 while (!rt2x00queue_empty(queue)) {
1129 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 1123 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1130 priv_tx = entry->priv_data; 1124 entry_priv = entry->priv_data;
1131 rt2x00_desc_read(priv_tx->desc, 0, &word); 1125 rt2x00_desc_read(entry_priv->desc, 0, &word);
1132 1126
1133 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || 1127 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1134 !rt2x00_get_field32(word, TXD_W0_VALID)) 1128 !rt2x00_get_field32(word, TXD_W0_VALID))
@@ -1137,7 +1131,18 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1137 /* 1131 /*
1138 * Obtain the status about this packet. 1132 * Obtain the status about this packet.
1139 */ 1133 */
1140 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT); 1134 txdesc.flags = 0;
1135 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1136 case 0: /* Success */
1137 case 1: /* Success with retry */
1138 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1139 break;
1140 case 2: /* Failure, excessive retries */
1141 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1142 /* Don't break, this is a failed frame! */
1143 default: /* Failure */
1144 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1145 }
1141 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT); 1146 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1142 1147
1143 rt2x00pci_txdone(rt2x00dev, entry, &txdesc); 1148 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
@@ -1364,7 +1369,6 @@ static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1364 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 1369 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1365 IEEE80211_HW_SIGNAL_DBM; 1370 IEEE80211_HW_SIGNAL_DBM;
1366 rt2x00dev->hw->extra_tx_headroom = 0; 1371 rt2x00dev->hw->extra_tx_headroom = 0;
1367 rt2x00dev->hw->queues = 2;
1368 1372
1369 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev); 1373 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1370 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, 1374 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
@@ -1480,18 +1484,27 @@ static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1480 return tsf; 1484 return tsf;
1481} 1485}
1482 1486
1483static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb, 1487static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
1484 struct ieee80211_tx_control *control)
1485{ 1488{
1486 struct rt2x00_dev *rt2x00dev = hw->priv; 1489 struct rt2x00_dev *rt2x00dev = hw->priv;
1487 struct rt2x00_intf *intf = vif_to_intf(control->vif); 1490 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1488 struct queue_entry_priv_pci_tx *priv_tx; 1491 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
1492 struct queue_entry_priv_pci *entry_priv;
1489 struct skb_frame_desc *skbdesc; 1493 struct skb_frame_desc *skbdesc;
1494 struct txentry_desc txdesc;
1490 u32 reg; 1495 u32 reg;
1491 1496
1492 if (unlikely(!intf->beacon)) 1497 if (unlikely(!intf->beacon))
1493 return -ENOBUFS; 1498 return -ENOBUFS;
1494 priv_tx = intf->beacon->priv_data; 1499 entry_priv = intf->beacon->priv_data;
1500
1501 /*
1502 * Copy all TX descriptor information into txdesc,
1503 * after that we are free to use the skb->cb array
1504 * for our information.
1505 */
1506 intf->beacon->skb = skb;
1507 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
1495 1508
1496 /* 1509 /*
1497 * Fill in skb descriptor 1510 * Fill in skb descriptor
@@ -1501,7 +1514,7 @@ static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1501 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED; 1514 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1502 skbdesc->data = skb->data; 1515 skbdesc->data = skb->data;
1503 skbdesc->data_len = skb->len; 1516 skbdesc->data_len = skb->len;
1504 skbdesc->desc = priv_tx->desc; 1517 skbdesc->desc = entry_priv->desc;
1505 skbdesc->desc_len = intf->beacon->queue->desc_size; 1518 skbdesc->desc_len = intf->beacon->queue->desc_size;
1506 skbdesc->entry = intf->beacon; 1519 skbdesc->entry = intf->beacon;
1507 1520
@@ -1520,8 +1533,8 @@ static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1520 * Write entire beacon with descriptor to register, 1533 * Write entire beacon with descriptor to register,
1521 * and kick the beacon generator. 1534 * and kick the beacon generator.
1522 */ 1535 */
1523 rt2x00lib_write_tx_desc(rt2x00dev, skb, control); 1536 memcpy(entry_priv->data, skb->data, skb->len);
1524 memcpy(priv_tx->data, skb->data, skb->len); 1537 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
1525 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON); 1538 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1526 1539
1527 return 0; 1540 return 0;
@@ -1581,28 +1594,28 @@ static const struct data_queue_desc rt2400pci_queue_rx = {
1581 .entry_num = RX_ENTRIES, 1594 .entry_num = RX_ENTRIES,
1582 .data_size = DATA_FRAME_SIZE, 1595 .data_size = DATA_FRAME_SIZE,
1583 .desc_size = RXD_DESC_SIZE, 1596 .desc_size = RXD_DESC_SIZE,
1584 .priv_size = sizeof(struct queue_entry_priv_pci_rx), 1597 .priv_size = sizeof(struct queue_entry_priv_pci),
1585}; 1598};
1586 1599
1587static const struct data_queue_desc rt2400pci_queue_tx = { 1600static const struct data_queue_desc rt2400pci_queue_tx = {
1588 .entry_num = TX_ENTRIES, 1601 .entry_num = TX_ENTRIES,
1589 .data_size = DATA_FRAME_SIZE, 1602 .data_size = DATA_FRAME_SIZE,
1590 .desc_size = TXD_DESC_SIZE, 1603 .desc_size = TXD_DESC_SIZE,
1591 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1604 .priv_size = sizeof(struct queue_entry_priv_pci),
1592}; 1605};
1593 1606
1594static const struct data_queue_desc rt2400pci_queue_bcn = { 1607static const struct data_queue_desc rt2400pci_queue_bcn = {
1595 .entry_num = BEACON_ENTRIES, 1608 .entry_num = BEACON_ENTRIES,
1596 .data_size = MGMT_FRAME_SIZE, 1609 .data_size = MGMT_FRAME_SIZE,
1597 .desc_size = TXD_DESC_SIZE, 1610 .desc_size = TXD_DESC_SIZE,
1598 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1611 .priv_size = sizeof(struct queue_entry_priv_pci),
1599}; 1612};
1600 1613
1601static const struct data_queue_desc rt2400pci_queue_atim = { 1614static const struct data_queue_desc rt2400pci_queue_atim = {
1602 .entry_num = ATIM_ENTRIES, 1615 .entry_num = ATIM_ENTRIES,
1603 .data_size = DATA_FRAME_SIZE, 1616 .data_size = DATA_FRAME_SIZE,
1604 .desc_size = TXD_DESC_SIZE, 1617 .desc_size = TXD_DESC_SIZE,
1605 .priv_size = sizeof(struct queue_entry_priv_pci_tx), 1618 .priv_size = sizeof(struct queue_entry_priv_pci),
1606}; 1619};
1607 1620
1608static const struct rt2x00_ops rt2400pci_ops = { 1621static const struct rt2x00_ops rt2400pci_ops = {
@@ -1611,6 +1624,7 @@ static const struct rt2x00_ops rt2400pci_ops = {
1611 .max_ap_intf = 1, 1624 .max_ap_intf = 1,
1612 .eeprom_size = EEPROM_SIZE, 1625 .eeprom_size = EEPROM_SIZE,
1613 .rf_size = RF_SIZE, 1626 .rf_size = RF_SIZE,
1627 .tx_queues = NUM_TX_QUEUES,
1614 .rx = &rt2400pci_queue_rx, 1628 .rx = &rt2400pci_queue_rx,
1615 .tx = &rt2400pci_queue_tx, 1629 .tx = &rt2400pci_queue_tx,
1616 .bcn = &rt2400pci_queue_bcn, 1630 .bcn = &rt2400pci_queue_bcn,