diff options
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2400pci.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2400pci.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c index 2725f3c4442e..329f3283697b 100644 --- a/drivers/net/wireless/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/rt2x00/rt2400pci.c | |||
@@ -779,7 +779,7 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) | |||
779 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); | 779 | rt2x00pci_register_read(rt2x00dev, TXCSR2, ®); |
780 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); | 780 | rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); |
781 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); | 781 | rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); |
782 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit); | 782 | rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); |
783 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); | 783 | rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); |
784 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); | 784 | rt2x00pci_register_write(rt2x00dev, TXCSR2, reg); |
785 | 785 | ||
@@ -795,13 +795,13 @@ static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev) | |||
795 | entry_priv->desc_dma); | 795 | entry_priv->desc_dma); |
796 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); | 796 | rt2x00pci_register_write(rt2x00dev, TXCSR5, reg); |
797 | 797 | ||
798 | entry_priv = rt2x00dev->bcn[1].entries[0].priv_data; | 798 | entry_priv = rt2x00dev->atim->entries[0].priv_data; |
799 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); | 799 | rt2x00pci_register_read(rt2x00dev, TXCSR4, ®); |
800 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, | 800 | rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, |
801 | entry_priv->desc_dma); | 801 | entry_priv->desc_dma); |
802 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); | 802 | rt2x00pci_register_write(rt2x00dev, TXCSR4, reg); |
803 | 803 | ||
804 | entry_priv = rt2x00dev->bcn[0].entries[0].priv_data; | 804 | entry_priv = rt2x00dev->bcn->entries[0].priv_data; |
805 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); | 805 | rt2x00pci_register_read(rt2x00dev, TXCSR6, ®); |
806 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, | 806 | rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, |
807 | entry_priv->desc_dma); | 807 | entry_priv->desc_dma); |
@@ -1131,19 +1131,21 @@ static void rt2400pci_write_tx_desc(struct queue_entry *entry, | |||
1131 | rt2x00_desc_write(txd, 2, word); | 1131 | rt2x00_desc_write(txd, 2, word); |
1132 | 1132 | ||
1133 | rt2x00_desc_read(txd, 3, &word); | 1133 | rt2x00_desc_read(txd, 3, &word); |
1134 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal); | 1134 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); |
1135 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); | 1135 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); |
1136 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); | 1136 | rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); |
1137 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service); | 1137 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); |
1138 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); | 1138 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6); |
1139 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); | 1139 | rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); |
1140 | rt2x00_desc_write(txd, 3, word); | 1140 | rt2x00_desc_write(txd, 3, word); |
1141 | 1141 | ||
1142 | rt2x00_desc_read(txd, 4, &word); | 1142 | rt2x00_desc_read(txd, 4, &word); |
1143 | rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low); | 1143 | rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, |
1144 | txdesc->u.plcp.length_low); | ||
1144 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); | 1145 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); |
1145 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); | 1146 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1); |
1146 | rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high); | 1147 | rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, |
1148 | txdesc->u.plcp.length_high); | ||
1147 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); | 1149 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7); |
1148 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); | 1150 | rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); |
1149 | rt2x00_desc_write(txd, 4, word); | 1151 | rt2x00_desc_write(txd, 4, word); |
@@ -1164,7 +1166,7 @@ static void rt2400pci_write_tx_desc(struct queue_entry *entry, | |||
1164 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); | 1166 | test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); |
1165 | rt2x00_set_field32(&word, TXD_W0_RTS, | 1167 | rt2x00_set_field32(&word, TXD_W0_RTS, |
1166 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); | 1168 | test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); |
1167 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); | 1169 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); |
1168 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, | 1170 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
1169 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); | 1171 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
1170 | rt2x00_desc_write(txd, 0, word); | 1172 | rt2x00_desc_write(txd, 0, word); |
@@ -1276,7 +1278,7 @@ static void rt2400pci_fill_rxdone(struct queue_entry *entry, | |||
1276 | static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, | 1278 | static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, |
1277 | const enum data_queue_qid queue_idx) | 1279 | const enum data_queue_qid queue_idx) |
1278 | { | 1280 | { |
1279 | struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx); | 1281 | struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); |
1280 | struct queue_entry_priv_pci *entry_priv; | 1282 | struct queue_entry_priv_pci *entry_priv; |
1281 | struct queue_entry *entry; | 1283 | struct queue_entry *entry; |
1282 | struct txdone_entry_desc txdesc; | 1284 | struct txdone_entry_desc txdesc; |
@@ -1315,27 +1317,25 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, | |||
1315 | static void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, | 1317 | static void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, |
1316 | struct rt2x00_field32 irq_field) | 1318 | struct rt2x00_field32 irq_field) |
1317 | { | 1319 | { |
1318 | unsigned long flags; | ||
1319 | u32 reg; | 1320 | u32 reg; |
1320 | 1321 | ||
1321 | /* | 1322 | /* |
1322 | * Enable a single interrupt. The interrupt mask register | 1323 | * Enable a single interrupt. The interrupt mask register |
1323 | * access needs locking. | 1324 | * access needs locking. |
1324 | */ | 1325 | */ |
1325 | spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); | 1326 | spin_lock_irq(&rt2x00dev->irqmask_lock); |
1326 | 1327 | ||
1327 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); | 1328 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1328 | rt2x00_set_field32(®, irq_field, 0); | 1329 | rt2x00_set_field32(®, irq_field, 0); |
1329 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | 1330 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); |
1330 | 1331 | ||
1331 | spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); | 1332 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
1332 | } | 1333 | } |
1333 | 1334 | ||
1334 | static void rt2400pci_txstatus_tasklet(unsigned long data) | 1335 | static void rt2400pci_txstatus_tasklet(unsigned long data) |
1335 | { | 1336 | { |
1336 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; | 1337 | struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; |
1337 | u32 reg; | 1338 | u32 reg; |
1338 | unsigned long flags; | ||
1339 | 1339 | ||
1340 | /* | 1340 | /* |
1341 | * Handle all tx queues. | 1341 | * Handle all tx queues. |
@@ -1347,7 +1347,7 @@ static void rt2400pci_txstatus_tasklet(unsigned long data) | |||
1347 | /* | 1347 | /* |
1348 | * Enable all TXDONE interrupts again. | 1348 | * Enable all TXDONE interrupts again. |
1349 | */ | 1349 | */ |
1350 | spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); | 1350 | spin_lock_irq(&rt2x00dev->irqmask_lock); |
1351 | 1351 | ||
1352 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); | 1352 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1353 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); | 1353 | rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); |
@@ -1355,7 +1355,7 @@ static void rt2400pci_txstatus_tasklet(unsigned long data) | |||
1355 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); | 1355 | rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); |
1356 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | 1356 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); |
1357 | 1357 | ||
1358 | spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); | 1358 | spin_unlock_irq(&rt2x00dev->irqmask_lock); |
1359 | } | 1359 | } |
1360 | 1360 | ||
1361 | static void rt2400pci_tbtt_tasklet(unsigned long data) | 1361 | static void rt2400pci_tbtt_tasklet(unsigned long data) |
@@ -1376,7 +1376,6 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) | |||
1376 | { | 1376 | { |
1377 | struct rt2x00_dev *rt2x00dev = dev_instance; | 1377 | struct rt2x00_dev *rt2x00dev = dev_instance; |
1378 | u32 reg, mask; | 1378 | u32 reg, mask; |
1379 | unsigned long flags; | ||
1380 | 1379 | ||
1381 | /* | 1380 | /* |
1382 | * Get the interrupt sources & saved to local variable. | 1381 | * Get the interrupt sources & saved to local variable. |
@@ -1418,13 +1417,13 @@ static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance) | |||
1418 | * Disable all interrupts for which a tasklet was scheduled right now, | 1417 | * Disable all interrupts for which a tasklet was scheduled right now, |
1419 | * the tasklet will reenable the appropriate interrupts. | 1418 | * the tasklet will reenable the appropriate interrupts. |
1420 | */ | 1419 | */ |
1421 | spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); | 1420 | spin_lock(&rt2x00dev->irqmask_lock); |
1422 | 1421 | ||
1423 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); | 1422 | rt2x00pci_register_read(rt2x00dev, CSR8, ®); |
1424 | reg |= mask; | 1423 | reg |= mask; |
1425 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); | 1424 | rt2x00pci_register_write(rt2x00dev, CSR8, reg); |
1426 | 1425 | ||
1427 | spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); | 1426 | spin_unlock(&rt2x00dev->irqmask_lock); |
1428 | 1427 | ||
1429 | 1428 | ||
1430 | 1429 | ||
@@ -1641,6 +1640,7 @@ static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev) | |||
1641 | */ | 1640 | */ |
1642 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); | 1641 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); |
1643 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); | 1642 | __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags); |
1643 | __set_bit(DRIVER_REQUIRE_SW_SEQNO, &rt2x00dev->flags); | ||
1644 | 1644 | ||
1645 | /* | 1645 | /* |
1646 | * Set the rssi offset. | 1646 | * Set the rssi offset. |