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path: root/drivers/net/wireless/mwl8k.c
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Diffstat (limited to 'drivers/net/wireless/mwl8k.c')
-rw-r--r--drivers/net/wireless/mwl8k.c51
1 files changed, 10 insertions, 41 deletions
diff --git a/drivers/net/wireless/mwl8k.c b/drivers/net/wireless/mwl8k.c
index 18542fba1f43..8cbb52cc4269 100644
--- a/drivers/net/wireless/mwl8k.c
+++ b/drivers/net/wireless/mwl8k.c
@@ -658,35 +658,6 @@ struct peer_capability_info {
658 __le16 amsdu_enabled; 658 __le16 amsdu_enabled;
659} __attribute__((packed)); 659} __attribute__((packed));
660 660
661/* Inline functions to manipulate QoS field in data descriptor. */
662static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
663{
664 u16 val_mask = 1 << 4;
665
666 /* End of Service Period Bit 4 */
667 return qos | val_mask;
668}
669
670static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
671{
672 u16 val_mask = 0x3;
673 u8 shift = 5;
674 u16 qos_mask = ~(val_mask << shift);
675
676 /* Ack Policy Bit 5-6 */
677 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
678}
679
680static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
681{
682 u16 val_mask = 0xff;
683 u8 shift = 8;
684 u16 qos_mask = ~(val_mask << shift);
685
686 /* Queue Length Bits 8-15 */
687 return (qos & qos_mask) | ((len & val_mask) << shift);
688}
689
690/* DMA header used by firmware and hardware. */ 661/* DMA header used by firmware and hardware. */
691struct mwl8k_dma_data { 662struct mwl8k_dma_data {
692 __le16 fwlen; 663 __le16 fwlen;
@@ -1145,16 +1116,18 @@ static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1145 * Packet transmission. 1116 * Packet transmission.
1146 */ 1117 */
1147 1118
1148/* Transmit packet ACK policy */
1149#define MWL8K_TXD_ACK_POLICY_NORMAL 0
1150#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1151
1152#define MWL8K_TXD_STATUS_OK 0x00000001 1119#define MWL8K_TXD_STATUS_OK 0x00000001
1153#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 1120#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1154#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 1121#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1155#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 1122#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1156#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 1123#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1157 1124
1125#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1126#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1127#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1128#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1129#define MWL8K_QOS_EOSP 0x0010
1130
1158struct mwl8k_tx_desc { 1131struct mwl8k_tx_desc {
1159 __le32 status; 1132 __le32 status;
1160 __u8 data_rate; 1133 __u8 data_rate;
@@ -1451,21 +1424,17 @@ mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1451 if (ieee80211_is_mgmt(wh->frame_control) || 1424 if (ieee80211_is_mgmt(wh->frame_control) ||
1452 ieee80211_is_ctl(wh->frame_control)) { 1425 ieee80211_is_ctl(wh->frame_control)) {
1453 txdatarate = 0; 1426 txdatarate = 0;
1454 qos = mwl8k_qos_setbit_eosp(qos); 1427 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
1455 /* Set Queue size to unspecified */
1456 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1457 } else if (ieee80211_is_data(wh->frame_control)) { 1428 } else if (ieee80211_is_data(wh->frame_control)) {
1458 txdatarate = 1; 1429 txdatarate = 1;
1459 if (is_multicast_ether_addr(wh->addr1)) 1430 if (is_multicast_ether_addr(wh->addr1))
1460 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; 1431 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1461 1432
1462 /* Send pkt in an aggregate if AMPDU frame. */ 1433 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
1463 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) 1434 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1464 qos = mwl8k_qos_setbit_ack(qos, 1435 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
1465 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1466 else 1436 else
1467 qos = mwl8k_qos_setbit_ack(qos, 1437 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
1468 MWL8K_TXD_ACK_POLICY_NORMAL);
1469 } 1438 }
1470 1439
1471 dma = pci_map_single(priv->pdev, skb->data, 1440 dma = pci_map_single(priv->pdev, skb->data,