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-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-hw.h288
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c14
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-fh.h391
3 files changed, 400 insertions, 293 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index 38627040ad59..bea03f682674 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -69,6 +69,8 @@
69#ifndef __iwl_4965_hw_h__ 69#ifndef __iwl_4965_hw_h__
70#define __iwl_4965_hw_h__ 70#define __iwl_4965_hw_h__
71 71
72#include "iwl-fh.h"
73
72/* EERPROM */ 74/* EERPROM */
73#define IWL4965_EEPROM_IMG_SIZE 1024 75#define IWL4965_EEPROM_IMG_SIZE 1024
74 76
@@ -786,292 +788,6 @@ enum {
786 788
787/********************* END TXPOWER *****************************************/ 789/********************* END TXPOWER *****************************************/
788 790
789/****************************/
790/* Flow Handler Definitions */
791/****************************/
792
793/**
794 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
795 * Addresses are offsets from device's PCI hardware base address.
796 */
797#define FH_MEM_LOWER_BOUND (0x1000)
798#define FH_MEM_UPPER_BOUND (0x1EF0)
799
800/**
801 * Keep-Warm (KW) buffer base address.
802 *
803 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
804 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
805 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
806 * from going into a power-savings mode that would cause higher DRAM latency,
807 * and possible data over/under-runs, before all Tx/Rx is complete.
808 *
809 * Driver loads IWL_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
810 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
811 * automatically invokes keep-warm accesses when normal accesses might not
812 * be sufficient to maintain fast DRAM response.
813 *
814 * Bit fields:
815 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
816 */
817#define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
818
819
820/**
821 * TFD Circular Buffers Base (CBBC) addresses
822 *
823 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
824 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
825 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
826 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
827 * aligned (address bits 0-7 must be 0).
828 *
829 * Bit fields in each pointer register:
830 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
831 */
832#define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
833#define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
834
835/* Find TFD CB base pointer for given queue (range 0-15). */
836#define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
837
838
839/**
840 * Rx SRAM Control and Status Registers (RSCSR)
841 *
842 * These registers provide handshake between driver and 4965 for the Rx queue
843 * (this queue handles *all* command responses, notifications, Rx data, etc.
844 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
845 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
846 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
847 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
848 * mapping between RBDs and RBs.
849 *
850 * Driver must allocate host DRAM memory for the following, and set the
851 * physical address of each into 4965 registers:
852 *
853 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
854 * entries (although any power of 2, up to 4096, is selectable by driver).
855 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
856 * (typically 4K, although 8K or 16K are also selectable by driver).
857 * Driver sets up RB size and number of RBDs in the CB via Rx config
858 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
859 *
860 * Bit fields within one RBD:
861 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
862 *
863 * Driver sets physical address [35:8] of base of RBD circular buffer
864 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
865 *
866 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
867 * (RBs) have been filled, via a "write pointer", actually the index of
868 * the RB's corresponding RBD within the circular buffer. Driver sets
869 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
870 *
871 * Bit fields in lower dword of Rx status buffer (upper dword not used
872 * by driver; see struct iwl4965_shared, val0):
873 * 31-12: Not used by driver
874 * 11- 0: Index of last filled Rx buffer descriptor
875 * (4965 writes, driver reads this value)
876 *
877 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
878 * enter pointers to these RBs into contiguous RBD circular buffer entries,
879 * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
880 *
881 * This "write" index corresponds to the *next* RBD that the driver will make
882 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
883 * the circular buffer. This value should initially be 0 (before preparing any
884 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
885 * wrap back to 0 at the end of the circular buffer (but don't wrap before
886 * "read" index has advanced past 1! See below).
887 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
888 *
889 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
890 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
891 * to tell the driver the index of the latest filled RBD. The driver must
892 * read this "read" index from DRAM after receiving an Rx interrupt from 4965.
893 *
894 * The driver must also internally keep track of a third index, which is the
895 * next RBD to process. When receiving an Rx interrupt, driver should process
896 * all filled but unprocessed RBs up to, but not including, the RB
897 * corresponding to the "read" index. For example, if "read" index becomes "1",
898 * driver may process the RB pointed to by RBD 0. Depending on volume of
899 * traffic, there may be many RBs to process.
900 *
901 * If read index == write index, 4965 thinks there is no room to put new data.
902 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
903 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
904 * and "read" indexes; that is, make sure that there are no more than 254
905 * buffers waiting to be filled.
906 */
907#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
908#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
909#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
910
911/**
912 * Physical base address of 8-byte Rx Status buffer.
913 * Bit fields:
914 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
915 */
916#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
917
918/**
919 * Physical base address of Rx Buffer Descriptor Circular Buffer.
920 * Bit fields:
921 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
922 */
923#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
924
925/**
926 * Rx write pointer (index, really!).
927 * Bit fields:
928 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
929 * NOTE: For 256-entry circular buffer, use only bits [7:0].
930 */
931#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
932#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
933
934
935/**
936 * Rx Config/Status Registers (RCSR)
937 * Rx Config Reg for channel 0 (only channel used)
938 *
939 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
940 * normal operation (see bit fields).
941 *
942 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
943 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
944 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
945 *
946 * Bit fields:
947 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
948 * '10' operate normally
949 * 29-24: reserved
950 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
951 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
952 * 19-18: reserved
953 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
954 * '10' 12K, '11' 16K.
955 * 15-14: reserved
956 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
957 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
958 * typical value 0x10 (about 1/2 msec)
959 * 3- 0: reserved
960 */
961#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
962#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
963#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
964
965#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
966
967#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */
968#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */
969#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */
970#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */
971#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */
972#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
973
974#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
975#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
976#define RX_RB_TIMEOUT (0x10)
977
978#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
979#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
980#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
981
982#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
983#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
984#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
985#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
986
987#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
988#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
989
990
991/**
992 * Rx Shared Status Registers (RSSR)
993 *
994 * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG),
995 * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
996 *
997 * Bit fields:
998 * 24: 1 = Channel 0 is idle
999 *
1000 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain
1001 * default values that should not be altered by the driver.
1002 */
1003#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
1004#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1005
1006#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
1007#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
1008#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)
1009
1010#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1011
1012
1013/**
1014 * Transmit DMA Channel Control/Status Registers (TCSR)
1015 *
1016 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
1017 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1018 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1019 *
1020 * To use a Tx DMA channel, driver must initialize its
1021 * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1022 *
1023 * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1024 * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1025 *
1026 * All other bits should be 0.
1027 *
1028 * Bit fields:
1029 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1030 * '10' operate normally
1031 * 29- 4: Reserved, set to "0"
1032 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1033 * 2- 0: Reserved, set to "0"
1034 */
1035#define IWL_FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
1036#define IWL_FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
1037
1038/* Find Control/Status reg for given Tx DMA/FIFO channel */
1039#define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1040 (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
1041
1042#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
1043#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
1044
1045#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1046#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1047#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1048
1049/**
1050 * Tx Shared Status Registers (TSSR)
1051 *
1052 * After stopping Tx DMA channel (writing 0 to
1053 * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1054 * IWL_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1055 * (channel's buffers empty | no pending requests).
1056 *
1057 * Bit fields:
1058 * 31-24: 1 = Channel buffers empty (channel 7:0)
1059 * 23-16: 1 = No pending requests (channel 7:0)
1060 */
1061#define IWL_FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
1062#define IWL_FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
1063
1064#define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)
1065
1066#define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
1067 ((1 << (_chnl)) << 24)
1068#define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
1069 ((1 << (_chnl)) << 16)
1070
1071#define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
1072 (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
1073 IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
1074
1075static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags) 791static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags)
1076{ 792{
1077 return le32_to_cpu(rate_n_flags) & 0xFF; 793 return le32_to_cpu(rate_n_flags) & 0xFF;
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 93f4cdbae0ff..99c08ea6ddf9 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -435,7 +435,7 @@ static int iwl4965_kw_init(struct iwl_priv *priv)
435 if (rc) 435 if (rc)
436 goto out; 436 goto out;
437 437
438 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG, 438 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
439 priv->kw.dma_addr >> 4); 439 priv->kw.dma_addr >> 4);
440 iwl_release_nic_access(priv); 440 iwl_release_nic_access(priv);
441out: 441out:
@@ -726,9 +726,9 @@ void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
726 } 726 }
727 727
728 iwl_write_direct32(priv, 728 iwl_write_direct32(priv,
729 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0); 729 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
730 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG, 730 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
731 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE 731 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
732 (txq_id), 200); 732 (txq_id), 200);
733 iwl_release_nic_access(priv); 733 iwl_release_nic_access(priv);
734 spin_unlock_irqrestore(&priv->lock, flags); 734 spin_unlock_irqrestore(&priv->lock, flags);
@@ -2256,9 +2256,9 @@ int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq
2256 2256
2257 /* Enable DMA channel, using same id as for TFD queue */ 2257 /* Enable DMA channel, using same id as for TFD queue */
2258 iwl_write_direct32( 2258 iwl_write_direct32(
2259 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 2259 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2260 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 2260 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2261 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); 2261 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2262 iwl_release_nic_access(priv); 2262 iwl_release_nic_access(priv);
2263 spin_unlock_irqrestore(&priv->lock, flags); 2263 spin_unlock_irqrestore(&priv->lock, flags);
2264 2264
diff --git a/drivers/net/wireless/iwlwifi/iwl-fh.h b/drivers/net/wireless/iwlwifi/iwl-fh.h
new file mode 100644
index 000000000000..944642450d3d
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-fh.h
@@ -0,0 +1,391 @@
1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63
64/****************************/
65/* Flow Handler Definitions */
66/****************************/
67
68/**
69 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
70 * Addresses are offsets from device's PCI hardware base address.
71 */
72#define FH_MEM_LOWER_BOUND (0x1000)
73#define FH_MEM_UPPER_BOUND (0x1EF0)
74
75/**
76 * Keep-Warm (KW) buffer base address.
77 *
78 * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the
79 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
80 * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host
81 * from going into a power-savings mode that would cause higher DRAM latency,
82 * and possible data over/under-runs, before all Tx/Rx is complete.
83 *
84 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
85 * of the buffer, which must be 4K aligned. Once this is set up, the 4965
86 * automatically invokes keep-warm accesses when normal accesses might not
87 * be sufficient to maintain fast DRAM response.
88 *
89 * Bit fields:
90 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
91 */
92#define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
93
94
95/**
96 * TFD Circular Buffers Base (CBBC) addresses
97 *
98 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
99 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
100 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
101 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
102 * aligned (address bits 0-7 must be 0).
103 *
104 * Bit fields in each pointer register:
105 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
106 */
107#define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
108#define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
109
110/* Find TFD CB base pointer for given queue (range 0-15). */
111#define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
112
113
114/**
115 * Rx SRAM Control and Status Registers (RSCSR)
116 *
117 * These registers provide handshake between driver and 4965 for the Rx queue
118 * (this queue handles *all* command responses, notifications, Rx data, etc.
119 * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx
120 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
121 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
122 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
123 * mapping between RBDs and RBs.
124 *
125 * Driver must allocate host DRAM memory for the following, and set the
126 * physical address of each into 4965 registers:
127 *
128 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
129 * entries (although any power of 2, up to 4096, is selectable by driver).
130 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
131 * (typically 4K, although 8K or 16K are also selectable by driver).
132 * Driver sets up RB size and number of RBDs in the CB via Rx config
133 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
134 *
135 * Bit fields within one RBD:
136 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
137 *
138 * Driver sets physical address [35:8] of base of RBD circular buffer
139 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
140 *
141 * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers
142 * (RBs) have been filled, via a "write pointer", actually the index of
143 * the RB's corresponding RBD within the circular buffer. Driver sets
144 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
145 *
146 * Bit fields in lower dword of Rx status buffer (upper dword not used
147 * by driver; see struct iwl4965_shared, val0):
148 * 31-12: Not used by driver
149 * 11- 0: Index of last filled Rx buffer descriptor
150 * (4965 writes, driver reads this value)
151 *
152 * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must
153 * enter pointers to these RBs into contiguous RBD circular buffer entries,
154 * and update the 4965's "write" index register,
155 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
156 *
157 * This "write" index corresponds to the *next* RBD that the driver will make
158 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
159 * the circular buffer. This value should initially be 0 (before preparing any
160 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
161 * wrap back to 0 at the end of the circular buffer (but don't wrap before
162 * "read" index has advanced past 1! See below).
163 * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
164 *
165 * As the 4965 fills RBs (referenced from contiguous RBDs within the circular
166 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
167 * to tell the driver the index of the latest filled RBD. The driver must
168 * read this "read" index from DRAM after receiving an Rx interrupt from 4965.
169 *
170 * The driver must also internally keep track of a third index, which is the
171 * next RBD to process. When receiving an Rx interrupt, driver should process
172 * all filled but unprocessed RBs up to, but not including, the RB
173 * corresponding to the "read" index. For example, if "read" index becomes "1",
174 * driver may process the RB pointed to by RBD 0. Depending on volume of
175 * traffic, there may be many RBs to process.
176 *
177 * If read index == write index, 4965 thinks there is no room to put new data.
178 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
179 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
180 * and "read" indexes; that is, make sure that there are no more than 254
181 * buffers waiting to be filled.
182 */
183#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
184#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
185#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
186
187/**
188 * Physical base address of 8-byte Rx Status buffer.
189 * Bit fields:
190 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
191 */
192#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
193
194/**
195 * Physical base address of Rx Buffer Descriptor Circular Buffer.
196 * Bit fields:
197 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
198 */
199#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
200
201/**
202 * Rx write pointer (index, really!).
203 * Bit fields:
204 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
205 * NOTE: For 256-entry circular buffer, use only bits [7:0].
206 */
207#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
208#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
209
210
211/**
212 * Rx Config/Status Registers (RCSR)
213 * Rx Config Reg for channel 0 (only channel used)
214 *
215 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
216 * normal operation (see bit fields).
217 *
218 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
219 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
220 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
221 *
222 * Bit fields:
223 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
224 * '10' operate normally
225 * 29-24: reserved
226 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
227 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
228 * 19-18: reserved
229 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
230 * '10' 12K, '11' 16K.
231 * 15-14: reserved
232 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
233 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
234 * typical value 0x10 (about 1/2 msec)
235 * 3- 0: reserved
236 */
237#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
238#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
239#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
240
241#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
242
243#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
244#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
245#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
246#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
247#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
248#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
249
250#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
251#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4)
252#define RX_RB_TIMEOUT (0x10)
253
254#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
255#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
256#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
257
258#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
259#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
260#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
261#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
262
263#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
264#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
265
266
267/**
268 * Rx Shared Status Registers (RSSR)
269 *
270 * After stopping Rx DMA channel (writing 0 to
271 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
272 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
273 *
274 * Bit fields:
275 * 24: 1 = Channel 0 is idle
276 *
277 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
278 * contain default values that should not be altered by the driver.
279 */
280#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
281#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
282
283#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
284#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
285#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
286 (FH_MEM_RSSR_LOWER_BOUND + 0x008)
287
288#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
289
290
291/**
292 * Transmit DMA Channel Control/Status Registers (TCSR)
293 *
294 * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels
295 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
296 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
297 *
298 * To use a Tx DMA channel, driver must initialize its
299 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
300 *
301 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
302 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
303 *
304 * All other bits should be 0.
305 *
306 * Bit fields:
307 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
308 * '10' operate normally
309 * 29- 4: Reserved, set to "0"
310 * 3: Enable internal DMA requests (1, normal operation), disable (0)
311 * 2- 0: Reserved, set to "0"
312 */
313#define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
314#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
315
316/* Find Control/Status reg for given Tx DMA/FIFO channel */
317#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
318 (FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
319
320#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
321#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
322
323#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
324#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
325#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
326
327#define FH_TCSR_CHNL_NUM (7)
328
329#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
330#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
331#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
332
333#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
334#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
335#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
336
337#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
338#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
339#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
340 (FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
341#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
342 (FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x4)
343#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
344 (FH_TCSR_LOWER_BOUND + 0x20 * _chnl + 0x8)
345
346/**
347 * Tx Shared Status Registers (TSSR)
348 *
349 * After stopping Tx DMA channel (writing 0 to
350 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
351 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
352 * (channel's buffers empty | no pending requests).
353 *
354 * Bit fields:
355 * 31-24: 1 = Channel buffers empty (channel 7:0)
356 * 23-16: 1 = No pending requests (channel 7:0)
357 */
358#define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
359#define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
360
361#define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010)
362
363#define FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) ((1 << (_chnl)) << 24)
364#define FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) ((1 << (_chnl)) << 16)
365
366#define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
367 (FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
368 FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
369
370
371
372#define FH_REGS_LOWER_BOUND (0x1000)
373#define FH_REGS_UPPER_BOUND (0x2000)
374
375/* Tx service channels */
376#define FH_SRVC_CHNL (9)
377#define FH_SRVC_LOWER_BOUND (FH_REGS_LOWER_BOUND + 0x9C8)
378#define FH_SRVC_UPPER_BOUND (FH_REGS_LOWER_BOUND + 0x9D0)
379#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
380 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
381
382/* TFDB Area - TFDs buffer table */
383#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
384#define FH_TFDIB_LOWER_BOUND (FH_REGS_LOWER_BOUND + 0x900)
385#define FH_TFDIB_UPPER_BOUND (FH_REGS_LOWER_BOUND + 0x958)
386#define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
387#define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
388
389/* TCSR: tx_config register values */
390#define FH_RSCSR_FRAME_SIZE_MSK (0x00003FFF) /* bits 0-13 */
391
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