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path: root/drivers/net/wireless/iwlwifi/pcie/trans.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/pcie/trans.c')
-rw-r--r--drivers/net/wireless/iwlwifi/pcie/trans.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 5d79a1f44b8e..523fe0c88dcb 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -614,7 +614,7 @@ static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
614{ 614{
615 u8 *v_addr; 615 u8 *v_addr;
616 dma_addr_t p_addr; 616 dma_addr_t p_addr;
617 u32 offset, chunk_sz = section->len; 617 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
618 int ret = 0; 618 int ret = 0;
619 619
620 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 620 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
@@ -1012,16 +1012,21 @@ static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1012 /* Stop the device, and put it in low power state */ 1012 /* Stop the device, and put it in low power state */
1013 iwl_pcie_apm_stop(trans); 1013 iwl_pcie_apm_stop(trans);
1014 1014
1015 /* Upon stop, the APM issues an interrupt if HW RF kill is set. 1015 /* stop and reset the on-board processor */
1016 * Clean again the interrupt here 1016 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1017 udelay(20);
1018
1019 /*
1020 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1021 * This is a bug in certain verions of the hardware.
1022 * Certain devices also keep sending HW RF kill interrupt all
1023 * the time, unless the interrupt is ACKed even if the interrupt
1024 * should be masked. Re-ACK all the interrupts here.
1017 */ 1025 */
1018 spin_lock(&trans_pcie->irq_lock); 1026 spin_lock(&trans_pcie->irq_lock);
1019 iwl_disable_interrupts(trans); 1027 iwl_disable_interrupts(trans);
1020 spin_unlock(&trans_pcie->irq_lock); 1028 spin_unlock(&trans_pcie->irq_lock);
1021 1029
1022 /* stop and reset the on-board processor */
1023 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1024 udelay(20);
1025 1030
1026 /* clear all status bits */ 1031 /* clear all status bits */
1027 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1032 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);