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path: root/drivers/net/wireless/iwlwifi/iwl-tx.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-tx.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-tx.c99
1 files changed, 56 insertions, 43 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
index 1f117a49c569..71d5b8a1a73e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -799,6 +799,22 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
799 /* Copy MAC header from skb into command buffer */ 799 /* Copy MAC header from skb into command buffer */
800 memcpy(tx_cmd->hdr, hdr, hdr_len); 800 memcpy(tx_cmd->hdr, hdr, hdr_len);
801 801
802
803 /* Total # bytes to be transmitted */
804 len = (u16)skb->len;
805 tx_cmd->len = cpu_to_le16(len);
806
807 if (info->control.hw_key)
808 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
809
810 /* TODO need this for burst mode later on */
811 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
812
813 /* set is_hcca to 0; it probably will never be implemented */
814 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
815
816 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
817
802 /* 818 /*
803 * Use the first empty entry in this queue's command buffer array 819 * Use the first empty entry in this queue's command buffer array
804 * to contain the Tx command and MAC header concatenated together 820 * to contain the Tx command and MAC header concatenated together
@@ -819,21 +835,30 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
819 else 835 else
820 len_org = 0; 836 len_org = 0;
821 837
838 /* Tell NIC about any 2-byte padding after MAC header */
839 if (len_org)
840 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
841
822 /* Physical address of this Tx command's header (not MAC header!), 842 /* Physical address of this Tx command's header (not MAC header!),
823 * within command buffer array. */ 843 * within command buffer array. */
824 txcmd_phys = pci_map_single(priv->pci_dev, 844 txcmd_phys = pci_map_single(priv->pci_dev,
825 out_cmd, sizeof(struct iwl_cmd), 845 &out_cmd->hdr, len,
826 PCI_DMA_BIDIRECTIONAL); 846 PCI_DMA_BIDIRECTIONAL);
827 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys); 847 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
828 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd)); 848 pci_unmap_len_set(&out_cmd->meta, len, len);
829 /* Add buffer containing Tx command and MAC(!) header to TFD's 849 /* Add buffer containing Tx command and MAC(!) header to TFD's
830 * first entry */ 850 * first entry */
831 txcmd_phys += offsetof(struct iwl_cmd, hdr);
832 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq, 851 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
833 txcmd_phys, len, 1, 0); 852 txcmd_phys, len, 1, 0);
834 853
835 if (info->control.hw_key) 854 if (!ieee80211_has_morefrags(hdr->frame_control)) {
836 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id); 855 txq->need_update = 1;
856 if (qc)
857 priv->stations[sta_id].tid[tid].seq_number = seq_number;
858 } else {
859 wait_write_ptr = 1;
860 txq->need_update = 0;
861 }
837 862
838 /* Set up TFD's 2nd entry to point directly to remainder of skb, 863 /* Set up TFD's 2nd entry to point directly to remainder of skb,
839 * if any (802.11 null frames have no payload). */ 864 * if any (802.11 null frames have no payload). */
@@ -846,41 +871,29 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
846 0, 0); 871 0, 0);
847 } 872 }
848 873
849 /* Tell NIC about any 2-byte padding after MAC header */
850 if (len_org)
851 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
852
853 /* Total # bytes to be transmitted */
854 len = (u16)skb->len;
855 tx_cmd->len = cpu_to_le16(len);
856 /* TODO need this for burst mode later on */
857 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
858
859 /* set is_hcca to 0; it probably will never be implemented */
860 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
861
862 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
863
864 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) + 874 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
865 offsetof(struct iwl_tx_cmd, scratch); 875 offsetof(struct iwl_tx_cmd, scratch);
876
877 len = sizeof(struct iwl_tx_cmd) +
878 sizeof(struct iwl_cmd_header) + hdr_len;
879 /* take back ownership of DMA buffer to enable update */
880 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
881 len, PCI_DMA_BIDIRECTIONAL);
866 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 882 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
867 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 883 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
868 884
869 if (!ieee80211_has_morefrags(hdr->frame_control)) { 885 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
870 txq->need_update = 1; 886 le16_to_cpu(out_cmd->hdr.sequence));
871 if (qc) 887 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
872 priv->stations[sta_id].tid[tid].seq_number = seq_number;
873 } else {
874 wait_write_ptr = 1;
875 txq->need_update = 0;
876 }
877
878 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd)); 888 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
879
880 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len); 889 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
881 890
882 /* Set up entry for this TFD in Tx byte-count array */ 891 /* Set up entry for this TFD in Tx byte-count array */
883 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len); 892 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
893 le16_to_cpu(tx_cmd->len));
894
895 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
896 len, PCI_DMA_BIDIRECTIONAL);
884 897
885 /* Tell device the write index *just past* this latest filled TFD */ 898 /* Tell device the write index *just past* this latest filled TFD */
886 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); 899 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
@@ -968,18 +981,9 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
968 INDEX_TO_SEQ(q->write_ptr)); 981 INDEX_TO_SEQ(q->write_ptr));
969 if (out_cmd->meta.flags & CMD_SIZE_HUGE) 982 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
970 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; 983 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
971 len = (idx == TFD_CMD_SLOTS) ? 984 len = sizeof(struct iwl_cmd) - sizeof(struct iwl_cmd_meta);
972 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd); 985 len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0;
973
974 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
975 len, PCI_DMA_BIDIRECTIONAL);
976 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
977 pci_unmap_len_set(&out_cmd->meta, len, len);
978 phys_addr += offsetof(struct iwl_cmd, hdr);
979 986
980 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
981 phys_addr, fix_size, 1,
982 U32_PAD(cmd->len));
983 987
984#ifdef CONFIG_IWLWIFI_DEBUG 988#ifdef CONFIG_IWLWIFI_DEBUG
985 switch (out_cmd->hdr.cmd) { 989 switch (out_cmd->hdr.cmd) {
@@ -1007,6 +1011,15 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1007 /* Set up entry in queue's byte count circular buffer */ 1011 /* Set up entry in queue's byte count circular buffer */
1008 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0); 1012 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1009 1013
1014 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1015 fix_size, PCI_DMA_BIDIRECTIONAL);
1016 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
1017 pci_unmap_len_set(&out_cmd->meta, len, fix_size);
1018
1019 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1020 phys_addr, fix_size, 1,
1021 U32_PAD(cmd->len));
1022
1010 /* Increment and update queue's write index */ 1023 /* Increment and update queue's write index */
1011 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); 1024 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1012 ret = iwl_txq_update_write_ptr(priv, txq); 1025 ret = iwl_txq_update_write_ptr(priv, txq);