diff options
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-prph.h')
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-prph.h | 74 |
1 files changed, 39 insertions, 35 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h index ecf651ae2593..c9cf8eef1a90 100644 --- a/drivers/net/wireless/iwlwifi/iwl-prph.h +++ b/drivers/net/wireless/iwlwifi/iwl-prph.h | |||
| @@ -243,44 +243,48 @@ | |||
| 243 | * 4965 Tx Scheduler registers. | 243 | * 4965 Tx Scheduler registers. |
| 244 | * Details are documented in iwl-4965-hw.h | 244 | * Details are documented in iwl-4965-hw.h |
| 245 | */ | 245 | */ |
| 246 | #define KDR_SCD_BASE (PRPH_BASE + 0xa02c00) | 246 | #define IWL49_SCD_BASE (PRPH_BASE + 0xa02c00) |
| 247 | 247 | ||
| 248 | #define KDR_SCD_SRAM_BASE_ADDR (KDR_SCD_BASE + 0x0) | 248 | #define IWL49_SCD_SRAM_BASE_ADDR (IWL49_SCD_BASE + 0x0) |
| 249 | #define KDR_SCD_EMPTY_BITS (KDR_SCD_BASE + 0x4) | 249 | #define IWL49_SCD_EMPTY_BITS (IWL49_SCD_BASE + 0x4) |
| 250 | #define KDR_SCD_DRAM_BASE_ADDR (KDR_SCD_BASE + 0x10) | 250 | #define IWL49_SCD_DRAM_BASE_ADDR (IWL49_SCD_BASE + 0x10) |
| 251 | #define KDR_SCD_AIT (KDR_SCD_BASE + 0x18) | 251 | #define IWL49_SCD_AIT (IWL49_SCD_BASE + 0x18) |
| 252 | #define KDR_SCD_TXFACT (KDR_SCD_BASE + 0x1c) | 252 | #define IWL49_SCD_TXFACT (IWL49_SCD_BASE + 0x1c) |
| 253 | #define KDR_SCD_QUEUE_WRPTR(x) (KDR_SCD_BASE + 0x24 + (x) * 4) | 253 | #define IWL49_SCD_QUEUE_WRPTR(x) (IWL49_SCD_BASE + 0x24 + (x) * 4) |
| 254 | #define KDR_SCD_QUEUE_RDPTR(x) (KDR_SCD_BASE + 0x64 + (x) * 4) | 254 | #define IWL49_SCD_QUEUE_RDPTR(x) (IWL49_SCD_BASE + 0x64 + (x) * 4) |
| 255 | #define KDR_SCD_SETQUEUENUM (KDR_SCD_BASE + 0xa4) | 255 | #define IWL49_SCD_SETQUEUENUM (IWL49_SCD_BASE + 0xa4) |
| 256 | #define KDR_SCD_SET_TXSTAT_TXED (KDR_SCD_BASE + 0xa8) | 256 | #define IWL49_SCD_SET_TXSTAT_TXED (IWL49_SCD_BASE + 0xa8) |
| 257 | #define KDR_SCD_SET_TXSTAT_DONE (KDR_SCD_BASE + 0xac) | 257 | #define IWL49_SCD_SET_TXSTAT_DONE (IWL49_SCD_BASE + 0xac) |
| 258 | #define KDR_SCD_SET_TXSTAT_NOT_SCHD (KDR_SCD_BASE + 0xb0) | 258 | #define IWL49_SCD_SET_TXSTAT_NOT_SCHD (IWL49_SCD_BASE + 0xb0) |
| 259 | #define KDR_SCD_DECREASE_CREDIT (KDR_SCD_BASE + 0xb4) | 259 | #define IWL49_SCD_DECREASE_CREDIT (IWL49_SCD_BASE + 0xb4) |
| 260 | #define KDR_SCD_DECREASE_SCREDIT (KDR_SCD_BASE + 0xb8) | 260 | #define IWL49_SCD_DECREASE_SCREDIT (IWL49_SCD_BASE + 0xb8) |
| 261 | #define KDR_SCD_LOAD_CREDIT (KDR_SCD_BASE + 0xbc) | 261 | #define IWL49_SCD_LOAD_CREDIT (IWL49_SCD_BASE + 0xbc) |
| 262 | #define KDR_SCD_LOAD_SCREDIT (KDR_SCD_BASE + 0xc0) | 262 | #define IWL49_SCD_LOAD_SCREDIT (IWL49_SCD_BASE + 0xc0) |
| 263 | #define KDR_SCD_BAR (KDR_SCD_BASE + 0xc4) | 263 | #define IWL49_SCD_BAR (IWL49_SCD_BASE + 0xc4) |
| 264 | #define KDR_SCD_BAR_DW0 (KDR_SCD_BASE + 0xc8) | 264 | #define IWL49_SCD_BAR_DW0 (IWL49_SCD_BASE + 0xc8) |
| 265 | #define KDR_SCD_BAR_DW1 (KDR_SCD_BASE + 0xcc) | 265 | #define IWL49_SCD_BAR_DW1 (IWL49_SCD_BASE + 0xcc) |
| 266 | #define KDR_SCD_QUEUECHAIN_SEL (KDR_SCD_BASE + 0xd0) | 266 | #define IWL49_SCD_QUEUECHAIN_SEL (IWL49_SCD_BASE + 0xd0) |
| 267 | #define KDR_SCD_QUERY_REQ (KDR_SCD_BASE + 0xd8) | 267 | #define IWL49_SCD_QUERY_REQ (IWL49_SCD_BASE + 0xd8) |
| 268 | #define KDR_SCD_QUERY_RES (KDR_SCD_BASE + 0xdc) | 268 | #define IWL49_SCD_QUERY_RES (IWL49_SCD_BASE + 0xdc) |
| 269 | #define KDR_SCD_PENDING_FRAMES (KDR_SCD_BASE + 0xe0) | 269 | #define IWL49_SCD_PENDING_FRAMES (IWL49_SCD_BASE + 0xe0) |
| 270 | #define KDR_SCD_INTERRUPT_MASK (KDR_SCD_BASE + 0xe4) | 270 | #define IWL49_SCD_INTERRUPT_MASK (IWL49_SCD_BASE + 0xe4) |
| 271 | #define KDR_SCD_INTERRUPT_THRESHOLD (KDR_SCD_BASE + 0xe8) | 271 | #define IWL49_SCD_INTERRUPT_THRESHOLD (IWL49_SCD_BASE + 0xe8) |
| 272 | #define KDR_SCD_QUERY_MIN_FRAME_SIZE (KDR_SCD_BASE + 0x100) | 272 | #define IWL49_SCD_QUERY_MIN_FRAME_SIZE (IWL49_SCD_BASE + 0x100) |
| 273 | #define KDR_SCD_QUEUE_STATUS_BITS(x) (KDR_SCD_BASE + 0x104 + (x) * 4) | 273 | #define IWL49_SCD_QUEUE_STATUS_BITS(x) (IWL49_SCD_BASE + 0x104 + (x) * 4) |
| 274 | 274 | ||
| 275 | /* SP SCD */ | 275 | /* SP SCD */ |
| 276 | #define SHL_SCD_BASE (PRPH_BASE + 0xa02c00) | 276 | #define IWL50_SCD_BASE (PRPH_BASE + 0xa02c00) |
| 277 | 277 | ||
| 278 | #define SHL_SCD_AIT (SHL_SCD_BASE + 0x0c) | 278 | #define IWL50_SCD_SRAM_BASE_ADDR (IWL50_SCD_BASE + 0x0) |
| 279 | #define SHL_SCD_TXFACT (SHL_SCD_BASE + 0x10) | 279 | #define IWL50_SCD_DRAM_BASE_ADDR (IWL50_SCD_BASE + 0x8) |
| 280 | #define SHL_SCD_QUEUE_WRPTR(x) (SHL_SCD_BASE + 0x18 + (x) * 4) | 280 | #define IWL50_SCD_AIT (IWL50_SCD_BASE + 0x0c) |
| 281 | #define SHL_SCD_QUEUE_RDPTR(x) (SHL_SCD_BASE + 0x68 + (x) * 4) | 281 | #define IWL50_SCD_TXFACT (IWL50_SCD_BASE + 0x10) |
| 282 | #define SHL_SCD_QUEUECHAIN_SEL (SHL_SCD_BASE + 0xe8) | 282 | #define IWL50_SCD_ACTIVE (IWL50_SCD_BASE + 0x14) |
| 283 | #define SHL_SCD_AGGR_SEL (SHL_SCD_BASE + 0x248) | 283 | #define IWL50_SCD_QUEUE_WRPTR(x) (IWL50_SCD_BASE + 0x18 + (x) * 4) |
| 284 | #define SHL_SCD_INTERRUPT_MASK (SHL_SCD_BASE + 0x108) | 284 | #define IWL50_SCD_QUEUE_RDPTR(x) (IWL50_SCD_BASE + 0x68 + (x) * 4) |
| 285 | #define IWL50_SCD_QUEUECHAIN_SEL (IWL50_SCD_BASE + 0xe8) | ||
| 286 | #define IWL50_SCD_AGGR_SEL (IWL50_SCD_BASE + 0x248) | ||
| 287 | #define IWL50_SCD_INTERRUPT_MASK (IWL50_SCD_BASE + 0x108) | ||
| 288 | #define IWL50_SCD_QUEUE_STATUS_BITS(x) (IWL50_SCD_BASE + 0x10c + (x) * 4) | ||
| 285 | 289 | ||
| 286 | #endif /* __iwl_prph_h__ */ | 290 | #endif /* __iwl_prph_h__ */ |