diff options
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index 545ed692d889..52629fbd835a 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h | |||
@@ -104,6 +104,7 @@ | |||
104 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step | 104 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step |
105 | */ | 105 | */ |
106 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) | 106 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
107 | #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) | ||
107 | 108 | ||
108 | /* Bits for CSR_HW_IF_CONFIG_REG */ | 109 | /* Bits for CSR_HW_IF_CONFIG_REG */ |
109 | #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) | 110 | #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) |
@@ -118,7 +119,12 @@ | |||
118 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) | 119 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) |
119 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) | 120 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) |
120 | 121 | ||
121 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | 122 | #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
123 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | ||
124 | #define CSR_HW_IF_CONFIG_REG_BIT_PCI_OWN_SEM (0x00400000) | ||
125 | #define CSR_HW_IF_CONFIG_REG_BIT_ME_OWN (0x02000000) | ||
126 | #define CSR_HW_IF_CONFIG_REG_BIT_WAKE_ME (0x08000000) | ||
127 | |||
122 | 128 | ||
123 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), | 129 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), |
124 | * acknowledged (reset) by host writing "1" to flagged bits. */ | 130 | * acknowledged (reset) by host writing "1" to flagged bits. */ |
@@ -236,6 +242,8 @@ | |||
236 | #define CSR39_ANA_PLL_CFG_VAL (0x01000000) | 242 | #define CSR39_ANA_PLL_CFG_VAL (0x01000000) |
237 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) | 243 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) |
238 | 244 | ||
245 | /* HPET MEM debug */ | ||
246 | #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) | ||
239 | /*=== HBUS (Host-side Bus) ===*/ | 247 | /*=== HBUS (Host-side Bus) ===*/ |
240 | #define HBUS_BASE (0x400) | 248 | #define HBUS_BASE (0x400) |
241 | /* | 249 | /* |