diff options
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index f03dae1b2f36..06437d13e73e 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h | |||
@@ -91,7 +91,8 @@ | |||
91 | #define CSR_EEPROM_GP (CSR_BASE+0x030) | 91 | #define CSR_EEPROM_GP (CSR_BASE+0x030) |
92 | #define CSR_OTP_GP_REG (CSR_BASE+0x034) | 92 | #define CSR_OTP_GP_REG (CSR_BASE+0x034) |
93 | #define CSR_GIO_REG (CSR_BASE+0x03C) | 93 | #define CSR_GIO_REG (CSR_BASE+0x03C) |
94 | #define CSR_GP_UCODE (CSR_BASE+0x044) | 94 | #define CSR_GP_UCODE_REG (CSR_BASE+0x048) |
95 | #define CSR_GP_DRIVER_REG (CSR_BASE+0x050) | ||
95 | #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) | 96 | #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) |
96 | #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) | 97 | #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) |
97 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) | 98 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) |
@@ -245,6 +246,13 @@ | |||
245 | #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) | 246 | #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) |
246 | #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) | 247 | #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) |
247 | 248 | ||
249 | /* GP Driver */ | ||
250 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) | ||
251 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) | ||
252 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) | ||
253 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) | ||
254 | |||
255 | |||
248 | /* GI Chicken Bits */ | 256 | /* GI Chicken Bits */ |
249 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) | 257 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
250 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) | 258 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) |