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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-commands.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-commands.h34
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h
index a304f771bcc3..b28cb4ffedc7 100644
--- a/drivers/net/wireless/iwlwifi/iwl-commands.h
+++ b/drivers/net/wireless/iwlwifi/iwl-commands.h
@@ -97,6 +97,7 @@ enum {
97 REPLY_ADD_STA = 0x18, 97 REPLY_ADD_STA = 0x18,
98 REPLY_REMOVE_STA = 0x19, 98 REPLY_REMOVE_STA = 0x19,
99 REPLY_REMOVE_ALL_STA = 0x1a, /* not used */ 99 REPLY_REMOVE_ALL_STA = 0x1a, /* not used */
100 REPLY_TXFIFO_FLUSH = 0x1e,
100 101
101 /* Security */ 102 /* Security */
102 REPLY_WEPKEY = 0x20, 103 REPLY_WEPKEY = 0x20,
@@ -1209,6 +1210,39 @@ struct iwl_rem_sta_cmd {
1209 u8 reserved2[2]; 1210 u8 reserved2[2];
1210} __attribute__ ((packed)); 1211} __attribute__ ((packed));
1211 1212
1213#define IWL_TX_FIFO_BK_MSK cpu_to_le32(BIT(0))
1214#define IWL_TX_FIFO_BE_MSK cpu_to_le32(BIT(1))
1215#define IWL_TX_FIFO_VI_MSK cpu_to_le32(BIT(2))
1216#define IWL_TX_FIFO_VO_MSK cpu_to_le32(BIT(3))
1217#define IWL_AGG_TX_QUEUE_MSK cpu_to_le32(0xffc00)
1218
1219/*
1220 * REPLY_TXFIFO_FLUSH = 0x1e(command and response)
1221 *
1222 * When using full FIFO flush this command checks the scheduler HW block WR/RD
1223 * pointers to check if all the frames were transferred by DMA into the
1224 * relevant TX FIFO queue. Only when the DMA is finished and the queue is
1225 * empty the command can finish.
1226 * This command is used to flush the TXFIFO from transmit commands, it may
1227 * operate on single or multiple queues, the command queue can't be flushed by
1228 * this command. The command response is returned when all the queue flush
1229 * operations are done. Each TX command flushed return response with the FLUSH
1230 * status set in the TX response status. When FIFO flush operation is used,
1231 * the flush operation ends when both the scheduler DMA done and TXFIFO empty
1232 * are set.
1233 *
1234 * @fifo_control: bit mask for which queues to flush
1235 * @flush_control: flush controls
1236 * 0: Dump single MSDU
1237 * 1: Dump multiple MSDU according to PS, INVALID STA, TTL, TID disable.
1238 * 2: Dump all FIFO
1239 */
1240struct iwl_txfifo_flush_cmd {
1241 __le32 fifo_control;
1242 __le16 flush_control;
1243 __le16 reserved;
1244} __attribute__ ((packed));
1245
1212/* 1246/*
1213 * REPLY_WEP_KEY = 0x20 1247 * REPLY_WEP_KEY = 0x20
1214 */ 1248 */