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path: root/drivers/net/wireless/iwlwifi/iwl-agn.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-agn.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.c193
1 files changed, 2 insertions, 191 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index 8fdd1746c102..bd980a2da413 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -845,191 +845,6 @@ static inline void iwl_synchronize_irq(struct iwl_priv *priv)
845 tasklet_kill(&priv->irq_tasklet); 845 tasklet_kill(&priv->irq_tasklet);
846} 846}
847 847
848static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
849{
850 u32 inta, handled = 0;
851 u32 inta_fh;
852 unsigned long flags;
853 u32 i;
854#ifdef CONFIG_IWLWIFI_DEBUG
855 u32 inta_mask;
856#endif
857
858 spin_lock_irqsave(&priv->lock, flags);
859
860 /* Ack/clear/reset pending uCode interrupts.
861 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
862 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
863 inta = iwl_read32(priv, CSR_INT);
864 iwl_write32(priv, CSR_INT, inta);
865
866 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
867 * Any new interrupts that happen after this, either while we're
868 * in this tasklet, or later, will show up in next ISR/tasklet. */
869 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
870 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
871
872#ifdef CONFIG_IWLWIFI_DEBUG
873 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
874 /* just for debug */
875 inta_mask = iwl_read32(priv, CSR_INT_MASK);
876 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
877 inta, inta_mask, inta_fh);
878 }
879#endif
880
881 spin_unlock_irqrestore(&priv->lock, flags);
882
883 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
884 * atomic, make sure that inta covers all the interrupts that
885 * we've discovered, even if FH interrupt came in just after
886 * reading CSR_INT. */
887 if (inta_fh & CSR49_FH_INT_RX_MASK)
888 inta |= CSR_INT_BIT_FH_RX;
889 if (inta_fh & CSR49_FH_INT_TX_MASK)
890 inta |= CSR_INT_BIT_FH_TX;
891
892 /* Now service all interrupt bits discovered above. */
893 if (inta & CSR_INT_BIT_HW_ERR) {
894 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
895
896 /* Tell the device to stop sending interrupts */
897 iwl_disable_interrupts(priv);
898
899 priv->isr_stats.hw++;
900 iwl_irq_handle_error(priv);
901
902 handled |= CSR_INT_BIT_HW_ERR;
903
904 return;
905 }
906
907#ifdef CONFIG_IWLWIFI_DEBUG
908 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
909 /* NIC fires this, but we don't use it, redundant with WAKEUP */
910 if (inta & CSR_INT_BIT_SCD) {
911 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
912 "the frame/frames.\n");
913 priv->isr_stats.sch++;
914 }
915
916 /* Alive notification via Rx interrupt will do the real work */
917 if (inta & CSR_INT_BIT_ALIVE) {
918 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
919 priv->isr_stats.alive++;
920 }
921 }
922#endif
923 /* Safely ignore these bits for debug checks below */
924 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
925
926 /* HW RF KILL switch toggled */
927 if (inta & CSR_INT_BIT_RF_KILL) {
928 int hw_rf_kill = 0;
929 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
930 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
931 hw_rf_kill = 1;
932
933 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
934 hw_rf_kill ? "disable radio" : "enable radio");
935
936 priv->isr_stats.rfkill++;
937
938 /* driver only loads ucode once setting the interface up.
939 * the driver allows loading the ucode even if the radio
940 * is killed. Hence update the killswitch state here. The
941 * rfkill handler will care about restarting if needed.
942 */
943 if (!test_bit(STATUS_ALIVE, &priv->status)) {
944 if (hw_rf_kill)
945 set_bit(STATUS_RF_KILL_HW, &priv->status);
946 else
947 clear_bit(STATUS_RF_KILL_HW, &priv->status);
948 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
949 }
950
951 handled |= CSR_INT_BIT_RF_KILL;
952 }
953
954 /* Chip got too hot and stopped itself */
955 if (inta & CSR_INT_BIT_CT_KILL) {
956 IWL_ERR(priv, "Microcode CT kill error detected.\n");
957 priv->isr_stats.ctkill++;
958 handled |= CSR_INT_BIT_CT_KILL;
959 }
960
961 /* Error detected by uCode */
962 if (inta & CSR_INT_BIT_SW_ERR) {
963 IWL_ERR(priv, "Microcode SW error detected. "
964 " Restarting 0x%X.\n", inta);
965 priv->isr_stats.sw++;
966 iwl_irq_handle_error(priv);
967 handled |= CSR_INT_BIT_SW_ERR;
968 }
969
970 /*
971 * uCode wakes up after power-down sleep.
972 * Tell device about any new tx or host commands enqueued,
973 * and about any Rx buffers made available while asleep.
974 */
975 if (inta & CSR_INT_BIT_WAKEUP) {
976 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
977 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
978 for (i = 0; i < priv->hw_params.max_txq_num; i++)
979 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
980 priv->isr_stats.wakeup++;
981 handled |= CSR_INT_BIT_WAKEUP;
982 }
983
984 /* All uCode command responses, including Tx command responses,
985 * Rx "responses" (frame-received notification), and other
986 * notifications from uCode come through here*/
987 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
988 iwl_rx_handle(priv);
989 priv->isr_stats.rx++;
990 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
991 }
992
993 /* This "Tx" DMA channel is used only for loading uCode */
994 if (inta & CSR_INT_BIT_FH_TX) {
995 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
996 priv->isr_stats.tx++;
997 handled |= CSR_INT_BIT_FH_TX;
998 /* Wake up uCode load routine, now that load is complete */
999 priv->ucode_write_complete = 1;
1000 wake_up_interruptible(&priv->wait_command_queue);
1001 }
1002
1003 if (inta & ~handled) {
1004 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1005 priv->isr_stats.unhandled++;
1006 }
1007
1008 if (inta & ~(priv->inta_mask)) {
1009 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1010 inta & ~priv->inta_mask);
1011 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1012 }
1013
1014 /* Re-enable all interrupts */
1015 /* only Re-enable if disabled by irq */
1016 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1017 iwl_enable_interrupts(priv);
1018 /* Re-enable RF_KILL if it occurred */
1019 else if (handled & CSR_INT_BIT_RF_KILL)
1020 iwl_enable_rfkill_int(priv);
1021
1022#ifdef CONFIG_IWLWIFI_DEBUG
1023 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1024 inta = iwl_read32(priv, CSR_INT);
1025 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1026 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1027 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1028 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1029 }
1030#endif
1031}
1032
1033/* tasklet for iwlagn interrupt */ 848/* tasklet for iwlagn interrupt */
1034static void iwl_irq_tasklet(struct iwl_priv *priv) 849static void iwl_irq_tasklet(struct iwl_priv *priv)
1035{ 850{
@@ -3751,12 +3566,8 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv)
3751 priv->watchdog.data = (unsigned long)priv; 3566 priv->watchdog.data = (unsigned long)priv;
3752 priv->watchdog.function = iwl_bg_watchdog; 3567 priv->watchdog.function = iwl_bg_watchdog;
3753 3568
3754 if (!priv->cfg->base_params->use_isr_legacy) 3569 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3755 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) 3570 iwl_irq_tasklet, (unsigned long)priv);
3756 iwl_irq_tasklet, (unsigned long)priv);
3757 else
3758 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3759 iwl_irq_tasklet_legacy, (unsigned long)priv);
3760} 3571}
3761 3572
3762static void iwl_cancel_deferred_work(struct iwl_priv *priv) 3573static void iwl_cancel_deferred_work(struct iwl_priv *priv)
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 19:16:41 -0500