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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-agn-ict.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn-ict.c306
1 files changed, 0 insertions, 306 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-ict.c b/drivers/net/wireless/iwlwifi/iwl-agn-ict.c
deleted file mode 100644
index f1b40ec1c873..000000000000
--- a/drivers/net/wireless/iwlwifi/iwl-agn-ict.c
+++ /dev/null
@@ -1,306 +0,0 @@
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/gfp.h>
34#include <net/mac80211.h>
35
36#include "iwl-dev.h"
37#include "iwl-core.h"
38#include "iwl-agn.h"
39#include "iwl-helpers.h"
40
41#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
42
43/* Free dram table */
44void iwl_free_isr_ict(struct iwl_priv *priv)
45{
46 if (priv->_agn.ict_tbl_vir) {
47 dma_free_coherent(priv->bus.dev,
48 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
49 priv->_agn.ict_tbl_vir,
50 priv->_agn.ict_tbl_dma);
51 priv->_agn.ict_tbl_vir = NULL;
52 }
53}
54
55
56/* allocate dram shared table it is a PAGE_SIZE aligned
57 * also reset all data related to ICT table interrupt.
58 */
59int iwl_alloc_isr_ict(struct iwl_priv *priv)
60{
61
62 /* allocate shrared data table */
63 priv->_agn.ict_tbl_vir =
64 dma_alloc_coherent(priv->bus.dev,
65 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
66 &priv->_agn.ict_tbl_dma, GFP_KERNEL);
67 if (!priv->_agn.ict_tbl_vir)
68 return -ENOMEM;
69
70 /* align table to PAGE_SIZE boundary */
71 priv->_agn.aligned_ict_tbl_dma = ALIGN(priv->_agn.ict_tbl_dma, PAGE_SIZE);
72
73 IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
74 (unsigned long long)priv->_agn.ict_tbl_dma,
75 (unsigned long long)priv->_agn.aligned_ict_tbl_dma,
76 (int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
77
78 priv->_agn.ict_tbl = priv->_agn.ict_tbl_vir +
79 (priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma);
80
81 IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
82 priv->_agn.ict_tbl, priv->_agn.ict_tbl_vir,
83 (int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
84
85 /* reset table and index to all 0 */
86 memset(priv->_agn.ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
87 priv->_agn.ict_index = 0;
88
89 /* add periodic RX interrupt */
90 priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
91 return 0;
92}
93
94/* Device is going up inform it about using ICT interrupt table,
95 * also we need to tell the driver to start using ICT interrupt.
96 */
97int iwl_reset_ict(struct iwl_priv *priv)
98{
99 u32 val;
100 unsigned long flags;
101
102 if (!priv->_agn.ict_tbl_vir)
103 return 0;
104
105 spin_lock_irqsave(&priv->lock, flags);
106 iwl_disable_interrupts(priv);
107
108 memset(&priv->_agn.ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
109
110 val = priv->_agn.aligned_ict_tbl_dma >> PAGE_SHIFT;
111
112 val |= CSR_DRAM_INT_TBL_ENABLE;
113 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
114
115 IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
116 "aligned dma address %Lx\n",
117 val, (unsigned long long)priv->_agn.aligned_ict_tbl_dma);
118
119 iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
120 priv->_agn.use_ict = true;
121 priv->_agn.ict_index = 0;
122 iwl_write32(priv, CSR_INT, priv->inta_mask);
123 iwl_enable_interrupts(priv);
124 spin_unlock_irqrestore(&priv->lock, flags);
125
126 return 0;
127}
128
129/* Device is going down disable ict interrupt usage */
130void iwl_disable_ict(struct iwl_priv *priv)
131{
132 unsigned long flags;
133
134 spin_lock_irqsave(&priv->lock, flags);
135 priv->_agn.use_ict = false;
136 spin_unlock_irqrestore(&priv->lock, flags);
137}
138
139static irqreturn_t iwl_isr(int irq, void *data)
140{
141 struct iwl_priv *priv = data;
142 u32 inta, inta_mask;
143 unsigned long flags;
144#ifdef CONFIG_IWLWIFI_DEBUG
145 u32 inta_fh;
146#endif
147 if (!priv)
148 return IRQ_NONE;
149
150 spin_lock_irqsave(&priv->lock, flags);
151
152 /* Disable (but don't clear!) interrupts here to avoid
153 * back-to-back ISRs and sporadic interrupts from our NIC.
154 * If we have something to service, the tasklet will re-enable ints.
155 * If we *don't* have something, we'll re-enable before leaving here. */
156 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
157 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
158
159 /* Discover which interrupts are active/pending */
160 inta = iwl_read32(priv, CSR_INT);
161
162 /* Ignore interrupt if there's nothing in NIC to service.
163 * This may be due to IRQ shared with another device,
164 * or due to sporadic interrupts thrown from our NIC. */
165 if (!inta) {
166 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
167 goto none;
168 }
169
170 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
171 /* Hardware disappeared. It might have already raised
172 * an interrupt */
173 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
174 goto unplugged;
175 }
176
177#ifdef CONFIG_IWLWIFI_DEBUG
178 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
179 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
180 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
181 "fh 0x%08x\n", inta, inta_mask, inta_fh);
182 }
183#endif
184
185 priv->_agn.inta |= inta;
186 /* iwl_irq_tasklet() will service interrupts and re-enable them */
187 if (likely(inta))
188 tasklet_schedule(&priv->irq_tasklet);
189 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
190 iwl_enable_interrupts(priv);
191
192 unplugged:
193 spin_unlock_irqrestore(&priv->lock, flags);
194 return IRQ_HANDLED;
195
196 none:
197 /* re-enable interrupts here since we don't have anything to service. */
198 /* only Re-enable if disabled by irq and no schedules tasklet. */
199 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
200 iwl_enable_interrupts(priv);
201
202 spin_unlock_irqrestore(&priv->lock, flags);
203 return IRQ_NONE;
204}
205
206/* interrupt handler using ict table, with this interrupt driver will
207 * stop using INTA register to get device's interrupt, reading this register
208 * is expensive, device will write interrupts in ICT dram table, increment
209 * index then will fire interrupt to driver, driver will OR all ICT table
210 * entries from current index up to table entry with 0 value. the result is
211 * the interrupt we need to service, driver will set the entries back to 0 and
212 * set index.
213 */
214irqreturn_t iwl_isr_ict(int irq, void *data)
215{
216 struct iwl_priv *priv = data;
217 u32 inta, inta_mask;
218 u32 val = 0;
219 unsigned long flags;
220
221 if (!priv)
222 return IRQ_NONE;
223
224 /* dram interrupt table not set yet,
225 * use legacy interrupt.
226 */
227 if (!priv->_agn.use_ict)
228 return iwl_isr(irq, data);
229
230 spin_lock_irqsave(&priv->lock, flags);
231
232 /* Disable (but don't clear!) interrupts here to avoid
233 * back-to-back ISRs and sporadic interrupts from our NIC.
234 * If we have something to service, the tasklet will re-enable ints.
235 * If we *don't* have something, we'll re-enable before leaving here.
236 */
237 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
238 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
239
240
241 /* Ignore interrupt if there's nothing in NIC to service.
242 * This may be due to IRQ shared with another device,
243 * or due to sporadic interrupts thrown from our NIC. */
244 if (!priv->_agn.ict_tbl[priv->_agn.ict_index]) {
245 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
246 goto none;
247 }
248
249 /* read all entries that not 0 start with ict_index */
250 while (priv->_agn.ict_tbl[priv->_agn.ict_index]) {
251
252 val |= le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]);
253 IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
254 priv->_agn.ict_index,
255 le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]));
256 priv->_agn.ict_tbl[priv->_agn.ict_index] = 0;
257 priv->_agn.ict_index = iwl_queue_inc_wrap(priv->_agn.ict_index,
258 ICT_COUNT);
259
260 }
261
262 /* We should not get this value, just ignore it. */
263 if (val == 0xffffffff)
264 val = 0;
265
266 /*
267 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
268 * (bit 15 before shifting it to 31) to clear when using interrupt
269 * coalescing. fortunately, bits 18 and 19 stay set when this happens
270 * so we use them to decide on the real state of the Rx bit.
271 * In order words, bit 15 is set if bit 18 or bit 19 are set.
272 */
273 if (val & 0xC0000)
274 val |= 0x8000;
275
276 inta = (0xff & val) | ((0xff00 & val) << 16);
277 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
278 inta, inta_mask, val);
279
280 inta &= priv->inta_mask;
281 priv->_agn.inta |= inta;
282
283 /* iwl_irq_tasklet() will service interrupts and re-enable them */
284 if (likely(inta))
285 tasklet_schedule(&priv->irq_tasklet);
286 else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) {
287 /* Allow interrupt if was disabled by this handler and
288 * no tasklet was schedules, We should not enable interrupt,
289 * tasklet will enable it.
290 */
291 iwl_enable_interrupts(priv);
292 }
293
294 spin_unlock_irqrestore(&priv->lock, flags);
295 return IRQ_HANDLED;
296
297 none:
298 /* re-enable interrupts here since we don't have anything to service.
299 * only Re-enable if disabled by irq.
300 */
301 if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
302 iwl_enable_interrupts(priv);
303
304 spin_unlock_irqrestore(&priv->lock, flags);
305 return IRQ_NONE;
306}
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