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path: root/drivers/net/wireless/iwlwifi/iwl-4965.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c80
1 files changed, 40 insertions, 40 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 5914657f1ca3..8e9810b72ace 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -139,20 +139,20 @@ int iwl_hw_rxq_stop(struct iwl_priv *priv)
139 unsigned long flags; 139 unsigned long flags;
140 140
141 spin_lock_irqsave(&priv->lock, flags); 141 spin_lock_irqsave(&priv->lock, flags);
142 rc = iwl_grab_restricted_access(priv); 142 rc = iwl_grab_nic_access(priv);
143 if (rc) { 143 if (rc) {
144 spin_unlock_irqrestore(&priv->lock, flags); 144 spin_unlock_irqrestore(&priv->lock, flags);
145 return rc; 145 return rc;
146 } 146 }
147 147
148 /* stop HW */ 148 /* stop HW */
149 iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 149 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
150 rc = iwl_poll_restricted_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, 150 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
151 (1 << 24), 1000); 151 (1 << 24), 1000);
152 if (rc < 0) 152 if (rc < 0)
153 IWL_ERROR("Can't stop Rx DMA.\n"); 153 IWL_ERROR("Can't stop Rx DMA.\n");
154 154
155 iwl_release_restricted_access(priv); 155 iwl_release_nic_access(priv);
156 spin_unlock_irqrestore(&priv->lock, flags); 156 spin_unlock_irqrestore(&priv->lock, flags);
157 157
158 return 0; 158 return 0;
@@ -196,7 +196,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
196 unsigned long flags; 196 unsigned long flags;
197 197
198 spin_lock_irqsave(&priv->lock, flags); 198 spin_lock_irqsave(&priv->lock, flags);
199 ret = iwl_grab_restricted_access(priv); 199 ret = iwl_grab_nic_access(priv);
200 if (ret) { 200 if (ret) {
201 spin_unlock_irqrestore(&priv->lock, flags); 201 spin_unlock_irqrestore(&priv->lock, flags);
202 return ret; 202 return ret;
@@ -217,7 +217,7 @@ static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
217 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 217 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
218 ~APMG_PS_CTRL_MSK_PWR_SRC); 218 ~APMG_PS_CTRL_MSK_PWR_SRC);
219 219
220 iwl_release_restricted_access(priv); 220 iwl_release_nic_access(priv);
221 spin_unlock_irqrestore(&priv->lock, flags); 221 spin_unlock_irqrestore(&priv->lock, flags);
222 222
223 return ret; 223 return ret;
@@ -229,24 +229,24 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
229 unsigned long flags; 229 unsigned long flags;
230 230
231 spin_lock_irqsave(&priv->lock, flags); 231 spin_lock_irqsave(&priv->lock, flags);
232 rc = iwl_grab_restricted_access(priv); 232 rc = iwl_grab_nic_access(priv);
233 if (rc) { 233 if (rc) {
234 spin_unlock_irqrestore(&priv->lock, flags); 234 spin_unlock_irqrestore(&priv->lock, flags);
235 return rc; 235 return rc;
236 } 236 }
237 237
238 /* stop HW */ 238 /* stop HW */
239 iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 239 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
240 240
241 iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 241 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
242 iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 242 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
243 rxq->dma_addr >> 8); 243 rxq->dma_addr >> 8);
244 244
245 iwl_write_restricted(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, 245 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
246 (priv->hw_setting.shared_phys + 246 (priv->hw_setting.shared_phys +
247 offsetof(struct iwl_shared, val0)) >> 4); 247 offsetof(struct iwl_shared, val0)) >> 4);
248 248
249 iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 249 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
250 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 250 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
251 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 251 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
252 IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K | 252 IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
@@ -258,7 +258,7 @@ static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
258 * iwl_write32(priv,CSR_INT_COAL_REG,0); 258 * iwl_write32(priv,CSR_INT_COAL_REG,0);
259 */ 259 */
260 260
261 iwl_release_restricted_access(priv); 261 iwl_release_nic_access(priv);
262 spin_unlock_irqrestore(&priv->lock, flags); 262 spin_unlock_irqrestore(&priv->lock, flags);
263 263
264 return 0; 264 return 0;
@@ -270,13 +270,13 @@ static int iwl4965_kw_init(struct iwl_priv *priv)
270 int rc; 270 int rc;
271 271
272 spin_lock_irqsave(&priv->lock, flags); 272 spin_lock_irqsave(&priv->lock, flags);
273 rc = iwl_grab_restricted_access(priv); 273 rc = iwl_grab_nic_access(priv);
274 if (rc) 274 if (rc)
275 goto out; 275 goto out;
276 276
277 iwl_write_restricted(priv, IWL_FH_KW_MEM_ADDR_REG, 277 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
278 priv->kw.dma_addr >> 4); 278 priv->kw.dma_addr >> 4);
279 iwl_release_restricted_access(priv); 279 iwl_release_nic_access(priv);
280out: 280out:
281 spin_unlock_irqrestore(&priv->lock, flags); 281 spin_unlock_irqrestore(&priv->lock, flags);
282 return rc; 282 return rc;
@@ -375,7 +375,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
375 375
376 spin_lock_irqsave(&priv->lock, flags); 376 spin_lock_irqsave(&priv->lock, flags);
377 377
378 rc = iwl_grab_restricted_access(priv); 378 rc = iwl_grab_nic_access(priv);
379 if (unlikely(rc)) { 379 if (unlikely(rc)) {
380 IWL_ERROR("TX reset failed"); 380 IWL_ERROR("TX reset failed");
381 spin_unlock_irqrestore(&priv->lock, flags); 381 spin_unlock_irqrestore(&priv->lock, flags);
@@ -383,7 +383,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
383 } 383 }
384 384
385 iwl_write_prph(priv, SCD_TXFACT, 0); 385 iwl_write_prph(priv, SCD_TXFACT, 0);
386 iwl_release_restricted_access(priv); 386 iwl_release_nic_access(priv);
387 spin_unlock_irqrestore(&priv->lock, flags); 387 spin_unlock_irqrestore(&priv->lock, flags);
388 388
389 rc = iwl4965_kw_init(priv); 389 rc = iwl4965_kw_init(priv);
@@ -441,7 +441,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
441 return rc; 441 return rc;
442 } 442 }
443 443
444 rc = iwl_grab_restricted_access(priv); 444 rc = iwl_grab_nic_access(priv);
445 if (rc) { 445 if (rc) {
446 spin_unlock_irqrestore(&priv->lock, flags); 446 spin_unlock_irqrestore(&priv->lock, flags);
447 return rc; 447 return rc;
@@ -459,7 +459,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
459 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 459 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
460 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 460 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
461 461
462 iwl_release_restricted_access(priv); 462 iwl_release_nic_access(priv);
463 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32); 463 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
464 spin_unlock_irqrestore(&priv->lock, flags); 464 spin_unlock_irqrestore(&priv->lock, flags);
465 465
@@ -505,7 +505,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
505 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | 505 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
506 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); 506 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
507 507
508 rc = iwl_grab_restricted_access(priv); 508 rc = iwl_grab_nic_access(priv);
509 if (rc < 0) { 509 if (rc < 0) {
510 spin_unlock_irqrestore(&priv->lock, flags); 510 spin_unlock_irqrestore(&priv->lock, flags);
511 IWL_DEBUG_INFO("Failed to init the card\n"); 511 IWL_DEBUG_INFO("Failed to init the card\n");
@@ -519,7 +519,7 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
519 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, 519 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
520 APMG_PS_CTRL_VAL_RESET_REQ); 520 APMG_PS_CTRL_VAL_RESET_REQ);
521 521
522 iwl_release_restricted_access(priv); 522 iwl_release_nic_access(priv);
523 spin_unlock_irqrestore(&priv->lock, flags); 523 spin_unlock_irqrestore(&priv->lock, flags);
524 524
525 iwl_hw_card_show_info(priv); 525 iwl_hw_card_show_info(priv);
@@ -603,18 +603,18 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
603 /* reset TFD queues */ 603 /* reset TFD queues */
604 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) { 604 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
605 spin_lock_irqsave(&priv->lock, flags); 605 spin_lock_irqsave(&priv->lock, flags);
606 if (iwl_grab_restricted_access(priv)) { 606 if (iwl_grab_nic_access(priv)) {
607 spin_unlock_irqrestore(&priv->lock, flags); 607 spin_unlock_irqrestore(&priv->lock, flags);
608 continue; 608 continue;
609 } 609 }
610 610
611 iwl_write_restricted(priv, 611 iwl_write_direct32(priv,
612 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 612 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
613 0x0); 613 0x0);
614 iwl_poll_restricted_bit(priv, IWL_FH_TSSR_TX_STATUS_REG, 614 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
615 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE 615 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
616 (txq_id), 200); 616 (txq_id), 200);
617 iwl_release_restricted_access(priv); 617 iwl_release_nic_access(priv);
618 spin_unlock_irqrestore(&priv->lock, flags); 618 spin_unlock_irqrestore(&priv->lock, flags);
619 } 619 }
620 620
@@ -641,7 +641,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
641 641
642 udelay(10); 642 udelay(10);
643 643
644 rc = iwl_grab_restricted_access(priv); 644 rc = iwl_grab_nic_access(priv);
645 if (!rc) { 645 if (!rc) {
646 iwl_write_prph(priv, APMG_CLK_EN_REG, 646 iwl_write_prph(priv, APMG_CLK_EN_REG,
647 APMG_CLK_VAL_DMA_CLK_RQT | 647 APMG_CLK_VAL_DMA_CLK_RQT |
@@ -652,7 +652,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
652 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, 652 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
653 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 653 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
654 654
655 iwl_release_restricted_access(priv); 655 iwl_release_nic_access(priv);
656 } 656 }
657 657
658 clear_bit(STATUS_HCMD_ACTIVE, &priv->status); 658 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
@@ -1581,7 +1581,7 @@ static void iwl4965_bg_txpower_work(struct work_struct *work)
1581 */ 1581 */
1582static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index) 1582static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1583{ 1583{
1584 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 1584 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
1585 (index & 0xff) | (txq_id << 8)); 1585 (index & 0xff) | (txq_id << 8));
1586 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index); 1586 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
1587} 1587}
@@ -1648,7 +1648,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1648 priv->chain_noise_data.delta_gain_code[i] = 1648 priv->chain_noise_data.delta_gain_code[i] =
1649 CHAIN_NOISE_DELTA_GAIN_INIT_VAL; 1649 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1650#endif /* CONFIG_IWLWIFI_SENSITIVITY*/ 1650#endif /* CONFIG_IWLWIFI_SENSITIVITY*/
1651 rc = iwl_grab_restricted_access(priv); 1651 rc = iwl_grab_nic_access(priv);
1652 if (rc) { 1652 if (rc) {
1653 spin_unlock_irqrestore(&priv->lock, flags); 1653 spin_unlock_irqrestore(&priv->lock, flags);
1654 return rc; 1654 return rc;
@@ -1671,7 +1671,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1671 /* initiate the queues */ 1671 /* initiate the queues */
1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) { 1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
1673 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0); 1673 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
1674 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 1674 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1675 iwl_write_targ_mem(priv, priv->scd_base_addr + 1675 iwl_write_targ_mem(priv, priv->scd_base_addr +
1676 SCD_CONTEXT_QUEUE_OFFSET(i), 1676 SCD_CONTEXT_QUEUE_OFFSET(i),
1677 (SCD_WIN_SIZE << 1677 (SCD_WIN_SIZE <<
@@ -1699,7 +1699,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1699 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); 1699 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1700 } 1700 }
1701 1701
1702 iwl_release_restricted_access(priv); 1702 iwl_release_nic_access(priv);
1703 spin_unlock_irqrestore(&priv->lock, flags); 1703 spin_unlock_irqrestore(&priv->lock, flags);
1704 1704
1705 return 0; 1705 return 0;
@@ -2688,19 +2688,19 @@ int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2688 int txq_id = txq->q.id; 2688 int txq_id = txq->q.id;
2689 2689
2690 spin_lock_irqsave(&priv->lock, flags); 2690 spin_lock_irqsave(&priv->lock, flags);
2691 rc = iwl_grab_restricted_access(priv); 2691 rc = iwl_grab_nic_access(priv);
2692 if (rc) { 2692 if (rc) {
2693 spin_unlock_irqrestore(&priv->lock, flags); 2693 spin_unlock_irqrestore(&priv->lock, flags);
2694 return rc; 2694 return rc;
2695 } 2695 }
2696 2696
2697 iwl_write_restricted(priv, FH_MEM_CBBC_QUEUE(txq_id), 2697 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2698 txq->q.dma_addr >> 8); 2698 txq->q.dma_addr >> 8);
2699 iwl_write_restricted( 2699 iwl_write_direct32(
2700 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 2700 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2701 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 2701 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2702 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); 2702 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2703 iwl_release_restricted_access(priv); 2703 iwl_release_nic_access(priv);
2704 spin_unlock_irqrestore(&priv->lock, flags); 2704 spin_unlock_irqrestore(&priv->lock, flags);
2705 2705
2706 return 0; 2706 return 0;
@@ -4188,7 +4188,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4188 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid); 4188 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
4189 4189
4190 spin_lock_irqsave(&priv->lock, flags); 4190 spin_lock_irqsave(&priv->lock, flags);
4191 rc = iwl_grab_restricted_access(priv); 4191 rc = iwl_grab_nic_access(priv);
4192 if (rc) { 4192 if (rc) {
4193 spin_unlock_irqrestore(&priv->lock, flags); 4193 spin_unlock_irqrestore(&priv->lock, flags);
4194 return rc; 4194 return rc;
@@ -4221,7 +4221,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4221 4221
4222 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 4222 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4223 4223
4224 iwl_release_restricted_access(priv); 4224 iwl_release_nic_access(priv);
4225 spin_unlock_irqrestore(&priv->lock, flags); 4225 spin_unlock_irqrestore(&priv->lock, flags);
4226 4226
4227 return 0; 4227 return 0;
@@ -4243,7 +4243,7 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4243 } 4243 }
4244 4244
4245 spin_lock_irqsave(&priv->lock, flags); 4245 spin_lock_irqsave(&priv->lock, flags);
4246 rc = iwl_grab_restricted_access(priv); 4246 rc = iwl_grab_nic_access(priv);
4247 if (rc) { 4247 if (rc) {
4248 spin_unlock_irqrestore(&priv->lock, flags); 4248 spin_unlock_irqrestore(&priv->lock, flags);
4249 return rc; 4249 return rc;
@@ -4262,7 +4262,7 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4262 iwl4965_txq_ctx_deactivate(priv, txq_id); 4262 iwl4965_txq_ctx_deactivate(priv, txq_id);
4263 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 4263 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4264 4264
4265 iwl_release_restricted_access(priv); 4265 iwl_release_nic_access(priv);
4266 spin_unlock_irqrestore(&priv->lock, flags); 4266 spin_unlock_irqrestore(&priv->lock, flags);
4267 4267
4268 return 0; 4268 return 0;