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path: root/drivers/net/wireless/iwlwifi/iwl-4965.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index 1e56dfa0cfbc..5914657f1ca3 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -1657,11 +1657,11 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1657 priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR); 1657 priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
1658 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET; 1658 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1659 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4) 1659 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1660 iwl_write_restricted_mem(priv, a, 0); 1660 iwl_write_targ_mem(priv, a, 0);
1661 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4) 1661 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
1662 iwl_write_restricted_mem(priv, a, 0); 1662 iwl_write_targ_mem(priv, a, 0);
1663 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4) 1663 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
1664 iwl_write_restricted_mem(priv, a, 0); 1664 iwl_write_targ_mem(priv, a, 0);
1665 1665
1666 iwl_write_prph(priv, SCD_DRAM_BASE_ADDR, 1666 iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
1667 (priv->hw_setting.shared_phys + 1667 (priv->hw_setting.shared_phys +
@@ -1672,12 +1672,12 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) { 1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
1673 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0); 1673 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
1674 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 1674 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1675 iwl_write_restricted_mem(priv, priv->scd_base_addr + 1675 iwl_write_targ_mem(priv, priv->scd_base_addr +
1676 SCD_CONTEXT_QUEUE_OFFSET(i), 1676 SCD_CONTEXT_QUEUE_OFFSET(i),
1677 (SCD_WIN_SIZE << 1677 (SCD_WIN_SIZE <<
1678 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 1678 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1679 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 1679 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1680 iwl_write_restricted_mem(priv, priv->scd_base_addr + 1680 iwl_write_targ_mem(priv, priv->scd_base_addr +
1681 SCD_CONTEXT_QUEUE_OFFSET(i) + 1681 SCD_CONTEXT_QUEUE_OFFSET(i) +
1682 sizeof(u32), 1682 sizeof(u32),
1683 (SCD_FRAME_LIMIT << 1683 (SCD_FRAME_LIMIT <<
@@ -4156,14 +4156,14 @@ static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
4156 tbl_dw_addr = priv->scd_base_addr + 4156 tbl_dw_addr = priv->scd_base_addr +
4157 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 4157 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4158 4158
4159 tbl_dw = iwl_read_restricted_mem(priv, tbl_dw_addr); 4159 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
4160 4160
4161 if (txq_id & 0x1) 4161 if (txq_id & 0x1)
4162 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 4162 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
4163 else 4163 else
4164 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 4164 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
4165 4165
4166 iwl_write_restricted_mem(priv, tbl_dw_addr, tbl_dw); 4166 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
4167 4167
4168 return 0; 4168 return 0;
4169} 4169}
@@ -4207,12 +4207,12 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4207 /* supposes that ssn_idx is valid (!= 0xFFF) */ 4207 /* supposes that ssn_idx is valid (!= 0xFFF) */
4208 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); 4208 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4209 4209
4210 iwl_write_restricted_mem(priv, 4210 iwl_write_targ_mem(priv,
4211 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id), 4211 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4212 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 4212 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4213 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 4213 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4214 4214
4215 iwl_write_restricted_mem(priv, priv->scd_base_addr + 4215 iwl_write_targ_mem(priv, priv->scd_base_addr +
4216 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 4216 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4217 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) 4217 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4218 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 4218 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);