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path: root/drivers/net/wireless/iwlwifi/iwl-3945.c
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Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-3945.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c1038
1 files changed, 644 insertions, 394 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 45cfa1cf194a..12f93b6207d6 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -1,6 +1,6 @@
1/****************************************************************************** 1/******************************************************************************
2 * 2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as 6 * under the terms of version 2 of the GNU General Public License as
@@ -38,10 +38,15 @@
38#include <asm/unaligned.h> 38#include <asm/unaligned.h>
39#include <net/mac80211.h> 39#include <net/mac80211.h>
40 40
41#include "iwl-3945-core.h" 41#include "iwl-fh.h"
42#include "iwl-3945-fh.h"
43#include "iwl-commands.h"
44#include "iwl-sta.h"
42#include "iwl-3945.h" 45#include "iwl-3945.h"
46#include "iwl-eeprom.h"
43#include "iwl-helpers.h" 47#include "iwl-helpers.h"
44#include "iwl-3945-rs.h" 48#include "iwl-core.h"
49#include "iwl-agn-rs.h"
45 50
46#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \ 51#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ 52 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
@@ -63,7 +68,7 @@
63 * maps to IWL_RATE_INVALID 68 * maps to IWL_RATE_INVALID
64 * 69 *
65 */ 70 */
66const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = { 71const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */ 72 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */ 73 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */ 74 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
@@ -91,7 +96,7 @@ const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
91 * Use for only special debugging. This function is just a placeholder as-is, 96 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ... 97 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */ 98 * ... and set IWL_EVT_DISABLE to 1. */
94void iwl3945_disable_events(struct iwl3945_priv *priv) 99void iwl3945_disable_events(struct iwl_priv *priv)
95{ 100{
96 int ret; 101 int ret;
97 int i; 102 int i;
@@ -150,30 +155,30 @@ void iwl3945_disable_events(struct iwl3945_priv *priv)
150 155
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr); 156 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
152 if (!iwl3945_hw_valid_rtc_data_addr(base)) { 157 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base); 158 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
154 return; 159 return;
155 } 160 }
156 161
157 ret = iwl3945_grab_nic_access(priv); 162 ret = iwl_grab_nic_access(priv);
158 if (ret) { 163 if (ret) {
159 IWL_WARNING("Can not read from adapter at this time.\n"); 164 IWL_WARN(priv, "Can not read from adapter at this time.\n");
160 return; 165 return;
161 } 166 }
162 167
163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32))); 168 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32))); 169 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv); 170 iwl_release_nic_access(priv);
166 171
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { 172 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n", 173 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
169 disable_ptr); 174 disable_ptr);
170 ret = iwl3945_grab_nic_access(priv); 175 ret = iwl_grab_nic_access(priv);
171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) 176 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
172 iwl3945_write_targ_mem(priv, 177 iwl_write_targ_mem(priv,
173 disable_ptr + (i * sizeof(u32)), 178 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]); 179 evt_disable[i]);
175 180
176 iwl3945_release_nic_access(priv); 181 iwl_release_nic_access(priv);
177 } else { 182 } else {
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n"); 183 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n"); 184 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
@@ -193,40 +198,7 @@ static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
193 return -1; 198 return -1;
194} 199}
195 200
196/** 201#ifdef CONFIG_IWLWIFI_DEBUG
197 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
198 * @priv: eeprom and antenna fields are used to determine antenna flags
199 *
200 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
201 * priv->antenna specifies the antenna diversity mode:
202 *
203 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
204 * IWL_ANTENNA_MAIN - Force MAIN antenna
205 * IWL_ANTENNA_AUX - Force AUX antenna
206 */
207__le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
208{
209 switch (priv->antenna) {
210 case IWL_ANTENNA_DIVERSITY:
211 return 0;
212
213 case IWL_ANTENNA_MAIN:
214 if (priv->eeprom.antenna_switch_type)
215 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
216 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
217
218 case IWL_ANTENNA_AUX:
219 if (priv->eeprom.antenna_switch_type)
220 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
221 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
222 }
223
224 /* bad antenna selector value */
225 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
226 return 0; /* "diversity" is default if error */
227}
228
229#ifdef CONFIG_IWL3945_DEBUG
230#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x 202#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
231 203
232static const char *iwl3945_get_tx_fail_reason(u32 status) 204static const char *iwl3945_get_tx_fail_reason(u32 status)
@@ -266,7 +238,7 @@ static inline const char *iwl3945_get_tx_fail_reason(u32 status)
266 * for A and B mode we need to overright prev 238 * for A and B mode we need to overright prev
267 * value 239 * value
268 */ 240 */
269int iwl3945_rs_next_rate(struct iwl3945_priv *priv, int rate) 241int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
270{ 242{
271 int next_rate = iwl3945_get_prev_ieee_rate(rate); 243 int next_rate = iwl3945_get_prev_ieee_rate(rate);
272 244
@@ -300,12 +272,12 @@ int iwl3945_rs_next_rate(struct iwl3945_priv *priv, int rate)
300 * need to be reclaimed. As result, some free space forms. If there is 272 * need to be reclaimed. As result, some free space forms. If there is
301 * enough free space (> low mark), wake the stack that feeds us. 273 * enough free space (> low mark), wake the stack that feeds us.
302 */ 274 */
303static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv, 275static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
304 int txq_id, int index) 276 int txq_id, int index)
305{ 277{
306 struct iwl3945_tx_queue *txq = &priv->txq[txq_id]; 278 struct iwl_tx_queue *txq = &priv->txq[txq_id];
307 struct iwl3945_queue *q = &txq->q; 279 struct iwl_queue *q = &txq->q;
308 struct iwl3945_tx_info *tx_info; 280 struct iwl_tx_info *tx_info;
309 281
310 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM); 282 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
311 283
@@ -315,10 +287,10 @@ static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
315 tx_info = &txq->txb[txq->q.read_ptr]; 287 tx_info = &txq->txb[txq->q.read_ptr];
316 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]); 288 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
317 tx_info->skb[0] = NULL; 289 tx_info->skb[0] = NULL;
318 iwl3945_hw_txq_free_tfd(priv, txq); 290 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
319 } 291 }
320 292
321 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) && 293 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
322 (txq_id != IWL_CMD_QUEUE_NUM) && 294 (txq_id != IWL_CMD_QUEUE_NUM) &&
323 priv->mac80211_registered) 295 priv->mac80211_registered)
324 ieee80211_wake_queue(priv->hw, txq_id); 296 ieee80211_wake_queue(priv->hw, txq_id);
@@ -327,22 +299,22 @@ static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
327/** 299/**
328 * iwl3945_rx_reply_tx - Handle Tx response 300 * iwl3945_rx_reply_tx - Handle Tx response
329 */ 301 */
330static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv, 302static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
331 struct iwl3945_rx_mem_buffer *rxb) 303 struct iwl_rx_mem_buffer *rxb)
332{ 304{
333 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; 305 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
334 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 306 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
335 int txq_id = SEQ_TO_QUEUE(sequence); 307 int txq_id = SEQ_TO_QUEUE(sequence);
336 int index = SEQ_TO_INDEX(sequence); 308 int index = SEQ_TO_INDEX(sequence);
337 struct iwl3945_tx_queue *txq = &priv->txq[txq_id]; 309 struct iwl_tx_queue *txq = &priv->txq[txq_id];
338 struct ieee80211_tx_info *info; 310 struct ieee80211_tx_info *info;
339 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 311 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
340 u32 status = le32_to_cpu(tx_resp->status); 312 u32 status = le32_to_cpu(tx_resp->status);
341 int rate_idx; 313 int rate_idx;
342 int fail; 314 int fail;
343 315
344 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) { 316 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
345 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " 317 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
346 "is out of range [0-%d] %d %d\n", txq_id, 318 "is out of range [0-%d] %d %d\n", txq_id,
347 index, txq->q.n_bd, txq->q.write_ptr, 319 index, txq->q.n_bd, txq->q.write_ptr,
348 txq->q.read_ptr); 320 txq->q.read_ptr);
@@ -374,7 +346,7 @@ static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
374 iwl3945_tx_queue_reclaim(priv, txq_id, index); 346 iwl3945_tx_queue_reclaim(priv, txq_id, index);
375 347
376 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 348 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
377 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); 349 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
378} 350}
379 351
380 352
@@ -387,14 +359,14 @@ static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
387 * 359 *
388 *****************************************************************************/ 360 *****************************************************************************/
389 361
390void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb) 362void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
391{ 363{
392 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; 364 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
393 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n", 365 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
394 (int)sizeof(struct iwl3945_notif_statistics), 366 (int)sizeof(struct iwl3945_notif_statistics),
395 le32_to_cpu(pkt->len)); 367 le32_to_cpu(pkt->len));
396 368
397 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics)); 369 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
398 370
399 iwl3945_led_background(priv); 371 iwl3945_led_background(priv);
400 372
@@ -406,7 +378,7 @@ void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_b
406 * Misc. internal state and helper functions 378 * Misc. internal state and helper functions
407 * 379 *
408 ******************************************************************************/ 380 ******************************************************************************/
409#ifdef CONFIG_IWL3945_DEBUG 381#ifdef CONFIG_IWLWIFI_DEBUG
410 382
411/** 383/**
412 * iwl3945_report_frame - dump frame to syslog during debug sessions 384 * iwl3945_report_frame - dump frame to syslog during debug sessions
@@ -415,8 +387,8 @@ void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_b
415 * including selective frame dumps. 387 * including selective frame dumps.
416 * group100 parameter selects whether to show 1 out of 100 good frames. 388 * group100 parameter selects whether to show 1 out of 100 good frames.
417 */ 389 */
418static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv, 390static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
419 struct iwl3945_rx_packet *pkt, 391 struct iwl_rx_packet *pkt,
420 struct ieee80211_hdr *header, int group100) 392 struct ieee80211_hdr *header, int group100)
421{ 393{
422 u32 to_us; 394 u32 to_us;
@@ -540,18 +512,27 @@ static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
540 } 512 }
541 } 513 }
542 if (print_dump) 514 if (print_dump)
543 iwl3945_print_hex_dump(IWL_DL_RX, data, length); 515 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
516}
517
518static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
519 struct iwl_rx_packet *pkt,
520 struct ieee80211_hdr *header, int group100)
521{
522 if (priv->debug_level & IWL_DL_RX)
523 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
544} 524}
525
545#else 526#else
546static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv, 527static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
547 struct iwl3945_rx_packet *pkt, 528 struct iwl_rx_packet *pkt,
548 struct ieee80211_hdr *header, int group100) 529 struct ieee80211_hdr *header, int group100)
549{ 530{
550} 531}
551#endif 532#endif
552 533
553/* This is necessary only for a number of statistics, see the caller. */ 534/* This is necessary only for a number of statistics, see the caller. */
554static int iwl3945_is_network_packet(struct iwl3945_priv *priv, 535static int iwl3945_is_network_packet(struct iwl_priv *priv,
555 struct ieee80211_hdr *header) 536 struct ieee80211_hdr *header)
556{ 537{
557 /* Filter incoming packets to determine if they are targeted toward 538 /* Filter incoming packets to determine if they are targeted toward
@@ -568,11 +549,11 @@ static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
568 } 549 }
569} 550}
570 551
571static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv, 552static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
572 struct iwl3945_rx_mem_buffer *rxb, 553 struct iwl_rx_mem_buffer *rxb,
573 struct ieee80211_rx_status *stats) 554 struct ieee80211_rx_status *stats)
574{ 555{
575 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data; 556 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
576#ifdef CONFIG_IWL3945_LEDS 557#ifdef CONFIG_IWL3945_LEDS
577 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt); 558 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
578#endif 559#endif
@@ -581,7 +562,7 @@ static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
581 short len = le16_to_cpu(rx_hdr->len); 562 short len = le16_to_cpu(rx_hdr->len);
582 563
583 /* We received data from the HW, so stop the watchdog */ 564 /* We received data from the HW, so stop the watchdog */
584 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) { 565 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
585 IWL_DEBUG_DROP("Corruption detected!\n"); 566 IWL_DEBUG_DROP("Corruption detected!\n");
586 return; 567 return;
587 } 568 }
@@ -597,7 +578,7 @@ static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
597 /* Set the size of the skb to the size of the frame */ 578 /* Set the size of the skb to the size of the frame */
598 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len)); 579 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
599 580
600 if (iwl3945_param_hwcrypto) 581 if (!iwl3945_mod_params.sw_crypto)
601 iwl3945_set_decrypted_flag(priv, rxb->skb, 582 iwl3945_set_decrypted_flag(priv, rxb->skb,
602 le32_to_cpu(rx_end->status), stats); 583 le32_to_cpu(rx_end->status), stats);
603 584
@@ -611,12 +592,12 @@ static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
611 592
612#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) 593#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
613 594
614static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv, 595static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
615 struct iwl3945_rx_mem_buffer *rxb) 596 struct iwl_rx_mem_buffer *rxb)
616{ 597{
617 struct ieee80211_hdr *header; 598 struct ieee80211_hdr *header;
618 struct ieee80211_rx_status rx_status; 599 struct ieee80211_rx_status rx_status;
619 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data; 600 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
620 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt); 601 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
621 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); 602 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
622 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); 603 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
@@ -659,7 +640,7 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
659 640
660 641
661 /* Convert 3945's rssi indicator to dBm */ 642 /* Convert 3945's rssi indicator to dBm */
662 rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET; 643 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
663 644
664 /* Set default noise value to -127 */ 645 /* Set default noise value to -127 */
665 if (priv->last_rx_noise == 0) 646 if (priv->last_rx_noise == 0)
@@ -705,11 +686,8 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
705 rx_status.signal, rx_status.signal, 686 rx_status.signal, rx_status.signal,
706 rx_status.noise, rx_status.rate_idx); 687 rx_status.noise, rx_status.rate_idx);
707 688
708#ifdef CONFIG_IWL3945_DEBUG 689 /* Set "1" to report good data frames in groups of 100 */
709 if (iwl3945_debug_level & (IWL_DL_RX)) 690 iwl3945_dbg_report_frame(priv, pkt, header, 1);
710 /* Set "1" to report good data frames in groups of 100 */
711 iwl3945_dbg_report_frame(priv, pkt, header, 1);
712#endif
713 691
714 if (network_packet) { 692 if (network_packet) {
715 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp); 693 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
@@ -721,24 +699,31 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
721 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status); 699 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
722} 700}
723 701
724int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr, 702int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
725 dma_addr_t addr, u16 len) 703 struct iwl_tx_queue *txq,
704 dma_addr_t addr, u16 len, u8 reset, u8 pad)
726{ 705{
727 int count; 706 int count;
728 u32 pad; 707 struct iwl_queue *q;
729 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr; 708 struct iwl3945_tfd *tfd, *tfd_tmp;
709
710 q = &txq->q;
711 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
712 tfd = &tfd_tmp[q->write_ptr];
713
714 if (reset)
715 memset(tfd, 0, sizeof(*tfd));
730 716
731 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); 717 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
732 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
733 718
734 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) { 719 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
735 IWL_ERROR("Error can not send more than %d chunks\n", 720 IWL_ERR(priv, "Error can not send more than %d chunks\n",
736 NUM_TFD_CHUNKS); 721 NUM_TFD_CHUNKS);
737 return -EINVAL; 722 return -EINVAL;
738 } 723 }
739 724
740 tfd->pa[count].addr = cpu_to_le32(addr); 725 tfd->tbs[count].addr = cpu_to_le32(addr);
741 tfd->pa[count].len = cpu_to_le32(len); 726 tfd->tbs[count].len = cpu_to_le32(len);
742 727
743 count++; 728 count++;
744 729
@@ -753,10 +738,10 @@ int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
753 * 738 *
754 * Does NOT advance any indexes 739 * Does NOT advance any indexes
755 */ 740 */
756int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq) 741void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
757{ 742{
758 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0]; 743 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
759 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; 744 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
760 struct pci_dev *dev = priv->pci_dev; 745 struct pci_dev *dev = priv->pci_dev;
761 int i; 746 int i;
762 int counter; 747 int counter;
@@ -764,21 +749,21 @@ int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *
764 /* classify bd */ 749 /* classify bd */
765 if (txq->q.id == IWL_CMD_QUEUE_NUM) 750 if (txq->q.id == IWL_CMD_QUEUE_NUM)
766 /* nothing to cleanup after for host commands */ 751 /* nothing to cleanup after for host commands */
767 return 0; 752 return;
768 753
769 /* sanity check */ 754 /* sanity check */
770 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags)); 755 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
771 if (counter > NUM_TFD_CHUNKS) { 756 if (counter > NUM_TFD_CHUNKS) {
772 IWL_ERROR("Too many chunks: %i\n", counter); 757 IWL_ERR(priv, "Too many chunks: %i\n", counter);
773 /* @todo issue fatal error, it is quite serious situation */ 758 /* @todo issue fatal error, it is quite serious situation */
774 return 0; 759 return;
775 } 760 }
776 761
777 /* unmap chunks if any */ 762 /* unmap chunks if any */
778 763
779 for (i = 1; i < counter; i++) { 764 for (i = 1; i < counter; i++) {
780 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr), 765 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
781 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE); 766 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
782 if (txq->txb[txq->q.read_ptr].skb[0]) { 767 if (txq->txb[txq->q.read_ptr].skb[0]) {
783 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0]; 768 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
784 if (txq->txb[txq->q.read_ptr].skb[0]) { 769 if (txq->txb[txq->q.read_ptr].skb[0]) {
@@ -788,10 +773,10 @@ int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *
788 } 773 }
789 } 774 }
790 } 775 }
791 return 0; 776 return ;
792} 777}
793 778
794u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr) 779u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
795{ 780{
796 int i, start = IWL_AP_ID; 781 int i, start = IWL_AP_ID;
797 int ret = IWL_INVALID_STATION; 782 int ret = IWL_INVALID_STATION;
@@ -802,13 +787,13 @@ u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
802 start = IWL_STA_ID; 787 start = IWL_STA_ID;
803 788
804 if (is_broadcast_ether_addr(addr)) 789 if (is_broadcast_ether_addr(addr))
805 return priv->hw_setting.bcast_sta_id; 790 return priv->hw_params.bcast_sta_id;
806 791
807 spin_lock_irqsave(&priv->sta_lock, flags); 792 spin_lock_irqsave(&priv->sta_lock, flags);
808 for (i = start; i < priv->hw_setting.max_stations; i++) 793 for (i = start; i < priv->hw_params.max_stations; i++)
809 if ((priv->stations[i].used) && 794 if ((priv->stations_39[i].used) &&
810 (!compare_ether_addr 795 (!compare_ether_addr
811 (priv->stations[i].sta.sta.addr, addr))) { 796 (priv->stations_39[i].sta.sta.addr, addr))) {
812 ret = i; 797 ret = i;
813 goto out; 798 goto out;
814 } 799 }
@@ -824,12 +809,10 @@ u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
824 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD: 809 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
825 * 810 *
826*/ 811*/
827void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv, 812void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
828 struct iwl3945_cmd *cmd,
829 struct ieee80211_tx_info *info, 813 struct ieee80211_tx_info *info,
830 struct ieee80211_hdr *hdr, int sta_id, int tx_id) 814 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
831{ 815{
832 unsigned long flags;
833 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value; 816 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
834 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1); 817 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
835 u16 rate_mask; 818 u16 rate_mask;
@@ -838,25 +821,15 @@ void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
838 u8 data_retry_limit; 821 u8 data_retry_limit;
839 __le32 tx_flags; 822 __le32 tx_flags;
840 __le16 fc = hdr->frame_control; 823 __le16 fc = hdr->frame_control;
824 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
841 825
842 rate = iwl3945_rates[rate_index].plcp; 826 rate = iwl3945_rates[rate_index].plcp;
843 tx_flags = cmd->cmd.tx.tx_flags; 827 tx_flags = tx->tx_flags;
844 828
845 /* We need to figure out how to get the sta->supp_rates while 829 /* We need to figure out how to get the sta->supp_rates while
846 * in this running context */ 830 * in this running context */
847 rate_mask = IWL_RATES_MASK; 831 rate_mask = IWL_RATES_MASK;
848 832
849 spin_lock_irqsave(&priv->sta_lock, flags);
850
851 priv->stations[sta_id].current_rate.rate_n_flags = rate;
852
853 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
854 (sta_id != priv->hw_setting.bcast_sta_id) &&
855 (sta_id != IWL_MULTICAST_ID))
856 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
857
858 spin_unlock_irqrestore(&priv->sta_lock, flags);
859
860 if (tx_id >= IWL_CMD_QUEUE_NUM) 833 if (tx_id >= IWL_CMD_QUEUE_NUM)
861 rts_retry_limit = 3; 834 rts_retry_limit = 3;
862 else 835 else
@@ -888,25 +861,25 @@ void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
888 } 861 }
889 } 862 }
890 863
891 cmd->cmd.tx.rts_retry_limit = rts_retry_limit; 864 tx->rts_retry_limit = rts_retry_limit;
892 cmd->cmd.tx.data_retry_limit = data_retry_limit; 865 tx->data_retry_limit = data_retry_limit;
893 cmd->cmd.tx.rate = rate; 866 tx->rate = rate;
894 cmd->cmd.tx.tx_flags = tx_flags; 867 tx->tx_flags = tx_flags;
895 868
896 /* OFDM */ 869 /* OFDM */
897 cmd->cmd.tx.supp_rates[0] = 870 tx->supp_rates[0] =
898 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF; 871 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
899 872
900 /* CCK */ 873 /* CCK */
901 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF); 874 tx->supp_rates[1] = (rate_mask & 0xF);
902 875
903 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X " 876 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
904 "cck/ofdm mask: 0x%x/0x%x\n", sta_id, 877 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
905 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags), 878 tx->rate, le32_to_cpu(tx->tx_flags),
906 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]); 879 tx->supp_rates[1], tx->supp_rates[0]);
907} 880}
908 881
909u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags) 882u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
910{ 883{
911 unsigned long flags_spin; 884 unsigned long flags_spin;
912 struct iwl3945_station_entry *station; 885 struct iwl3945_station_entry *station;
@@ -915,56 +888,56 @@ u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags
915 return IWL_INVALID_STATION; 888 return IWL_INVALID_STATION;
916 889
917 spin_lock_irqsave(&priv->sta_lock, flags_spin); 890 spin_lock_irqsave(&priv->sta_lock, flags_spin);
918 station = &priv->stations[sta_id]; 891 station = &priv->stations_39[sta_id];
919 892
920 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK; 893 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
921 station->sta.rate_n_flags = cpu_to_le16(tx_rate); 894 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
922 station->current_rate.rate_n_flags = tx_rate;
923 station->sta.mode = STA_CONTROL_MODIFY_MSK; 895 station->sta.mode = STA_CONTROL_MODIFY_MSK;
924 896
925 spin_unlock_irqrestore(&priv->sta_lock, flags_spin); 897 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
926 898
927 iwl3945_send_add_station(priv, &station->sta, flags); 899 iwl_send_add_sta(priv,
900 (struct iwl_addsta_cmd *)&station->sta, flags);
928 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n", 901 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
929 sta_id, tx_rate); 902 sta_id, tx_rate);
930 return sta_id; 903 return sta_id;
931} 904}
932 905
933static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max) 906static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
934{ 907{
935 int rc; 908 int rc;
936 unsigned long flags; 909 unsigned long flags;
937 910
938 spin_lock_irqsave(&priv->lock, flags); 911 spin_lock_irqsave(&priv->lock, flags);
939 rc = iwl3945_grab_nic_access(priv); 912 rc = iwl_grab_nic_access(priv);
940 if (rc) { 913 if (rc) {
941 spin_unlock_irqrestore(&priv->lock, flags); 914 spin_unlock_irqrestore(&priv->lock, flags);
942 return rc; 915 return rc;
943 } 916 }
944 917
945 if (!pwr_max) { 918 if (src == IWL_PWR_SRC_VAUX) {
946 u32 val; 919 u32 val;
947 920
948 rc = pci_read_config_dword(priv->pci_dev, 921 rc = pci_read_config_dword(priv->pci_dev,
949 PCI_POWER_SOURCE, &val); 922 PCI_POWER_SOURCE, &val);
950 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) { 923 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
951 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 924 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
952 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 925 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
953 ~APMG_PS_CTRL_MSK_PWR_SRC); 926 ~APMG_PS_CTRL_MSK_PWR_SRC);
954 iwl3945_release_nic_access(priv); 927 iwl_release_nic_access(priv);
955 928
956 iwl3945_poll_bit(priv, CSR_GPIO_IN, 929 iwl_poll_bit(priv, CSR_GPIO_IN,
957 CSR_GPIO_IN_VAL_VAUX_PWR_SRC, 930 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
958 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 931 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
959 } else 932 } else
960 iwl3945_release_nic_access(priv); 933 iwl_release_nic_access(priv);
961 } else { 934 } else {
962 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 935 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
963 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 936 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
964 ~APMG_PS_CTRL_MSK_PWR_SRC); 937 ~APMG_PS_CTRL_MSK_PWR_SRC);
965 938
966 iwl3945_release_nic_access(priv); 939 iwl_release_nic_access(priv);
967 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, 940 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
968 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ 941 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
969 } 942 }
970 spin_unlock_irqrestore(&priv->lock, flags); 943 spin_unlock_irqrestore(&priv->lock, flags);
@@ -972,81 +945,79 @@ static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
972 return rc; 945 return rc;
973} 946}
974 947
975static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq) 948static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
976{ 949{
977 int rc; 950 int rc;
978 unsigned long flags; 951 unsigned long flags;
979 952
980 spin_lock_irqsave(&priv->lock, flags); 953 spin_lock_irqsave(&priv->lock, flags);
981 rc = iwl3945_grab_nic_access(priv); 954 rc = iwl_grab_nic_access(priv);
982 if (rc) { 955 if (rc) {
983 spin_unlock_irqrestore(&priv->lock, flags); 956 spin_unlock_irqrestore(&priv->lock, flags);
984 return rc; 957 return rc;
985 } 958 }
986 959
987 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr); 960 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
988 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0), 961 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
989 priv->hw_setting.shared_phys + 962 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
990 offsetof(struct iwl3945_shared, rx_read_ptr[0])); 963 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
991 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0); 964 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
992 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 965 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
993 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | 966 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
994 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | 967 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
995 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | 968 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
996 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | 969 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
997 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) | 970 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
998 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | 971 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
999 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
1000 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
1001 972
1002 /* fake read to flush all prev I/O */ 973 /* fake read to flush all prev I/O */
1003 iwl3945_read_direct32(priv, FH_RSSR_CTRL); 974 iwl_read_direct32(priv, FH39_RSSR_CTRL);
1004 975
1005 iwl3945_release_nic_access(priv); 976 iwl_release_nic_access(priv);
1006 spin_unlock_irqrestore(&priv->lock, flags); 977 spin_unlock_irqrestore(&priv->lock, flags);
1007 978
1008 return 0; 979 return 0;
1009} 980}
1010 981
1011static int iwl3945_tx_reset(struct iwl3945_priv *priv) 982static int iwl3945_tx_reset(struct iwl_priv *priv)
1012{ 983{
1013 int rc; 984 int rc;
1014 unsigned long flags; 985 unsigned long flags;
1015 986
1016 spin_lock_irqsave(&priv->lock, flags); 987 spin_lock_irqsave(&priv->lock, flags);
1017 rc = iwl3945_grab_nic_access(priv); 988 rc = iwl_grab_nic_access(priv);
1018 if (rc) { 989 if (rc) {
1019 spin_unlock_irqrestore(&priv->lock, flags); 990 spin_unlock_irqrestore(&priv->lock, flags);
1020 return rc; 991 return rc;
1021 } 992 }
1022 993
1023 /* bypass mode */ 994 /* bypass mode */
1024 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2); 995 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
1025 996
1026 /* RA 0 is active */ 997 /* RA 0 is active */
1027 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01); 998 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
1028 999
1029 /* all 6 fifo are active */ 1000 /* all 6 fifo are active */
1030 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f); 1001 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1031 1002
1032 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000); 1003 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1033 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002); 1004 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1034 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); 1005 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1035 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); 1006 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1036 1007
1037 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE, 1008 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1038 priv->hw_setting.shared_phys); 1009 priv->shared_phys);
1039 1010
1040 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG, 1011 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1041 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | 1012 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1042 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | 1013 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1043 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | 1014 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1044 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON | 1015 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1045 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON | 1016 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1046 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | 1017 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1047 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); 1018 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1048 1019
1049 iwl3945_release_nic_access(priv); 1020 iwl_release_nic_access(priv);
1050 spin_unlock_irqrestore(&priv->lock, flags); 1021 spin_unlock_irqrestore(&priv->lock, flags);
1051 1022
1052 return 0; 1023 return 0;
@@ -1057,7 +1028,7 @@ static int iwl3945_tx_reset(struct iwl3945_priv *priv)
1057 * 1028 *
1058 * Destroys all DMA structures and initialize them again 1029 * Destroys all DMA structures and initialize them again
1059 */ 1030 */
1060static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv) 1031static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1061{ 1032{
1062 int rc; 1033 int rc;
1063 int txq_id, slots_num; 1034 int txq_id, slots_num;
@@ -1073,10 +1044,10 @@ static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
1073 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) { 1044 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1074 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? 1045 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1075 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 1046 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1076 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num, 1047 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1077 txq_id); 1048 txq_id);
1078 if (rc) { 1049 if (rc) {
1079 IWL_ERROR("Tx %d queue init failed\n", txq_id); 1050 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1080 goto error; 1051 goto error;
1081 } 1052 }
1082 } 1053 }
@@ -1088,111 +1059,140 @@ static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
1088 return rc; 1059 return rc;
1089} 1060}
1090 1061
1091int iwl3945_hw_nic_init(struct iwl3945_priv *priv) 1062static int iwl3945_apm_init(struct iwl_priv *priv)
1092{ 1063{
1093 u8 rev_id; 1064 int ret = 0;
1094 int rc;
1095 unsigned long flags;
1096 struct iwl3945_rx_queue *rxq = &priv->rxq;
1097 1065
1098 iwl3945_power_init_handle(priv); 1066 iwl3945_power_init_handle(priv);
1099 1067
1100 spin_lock_irqsave(&priv->lock, flags); 1068 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1101 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL); 1069 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1102 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, 1070
1103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 1071 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1104 1072 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1105 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1073 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1106 rc = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL, 1074
1107 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 1075 /* set "initialization complete" bit to move adapter
1108 if (rc < 0) { 1076 * D0U* --> D0A* state */
1109 spin_unlock_irqrestore(&priv->lock, flags); 1077 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1078
1079 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1080 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1081 if (ret < 0) {
1110 IWL_DEBUG_INFO("Failed to init the card\n"); 1082 IWL_DEBUG_INFO("Failed to init the card\n");
1111 return rc; 1083 goto out;
1112 } 1084 }
1113 1085
1114 rc = iwl3945_grab_nic_access(priv); 1086 ret = iwl_grab_nic_access(priv);
1115 if (rc) { 1087 if (ret)
1116 spin_unlock_irqrestore(&priv->lock, flags); 1088 goto out;
1117 return rc; 1089
1118 } 1090 /* enable DMA */
1119 iwl3945_write_prph(priv, APMG_CLK_EN_REG, 1091 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1120 APMG_CLK_VAL_DMA_CLK_RQT | 1092 APMG_CLK_VAL_BSM_CLK_RQT);
1121 APMG_CLK_VAL_BSM_CLK_RQT); 1093
1122 udelay(20); 1094 udelay(20);
1123 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1124 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1125 iwl3945_release_nic_access(priv);
1126 spin_unlock_irqrestore(&priv->lock, flags);
1127 1095
1128 /* Determine HW type */ 1096 /* disable L1-Active */
1129 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id); 1097 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1130 if (rc) 1098 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1131 return rc; 1099
1132 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id); 1100 iwl_release_nic_access(priv);
1101out:
1102 return ret;
1103}
1104
1105static void iwl3945_nic_config(struct iwl_priv *priv)
1106{
1107 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1108 unsigned long flags;
1109 u8 rev_id = 0;
1133 1110
1134 iwl3945_nic_set_pwr_src(priv, 1);
1135 spin_lock_irqsave(&priv->lock, flags); 1111 spin_lock_irqsave(&priv->lock, flags);
1136 1112
1137 if (rev_id & PCI_CFG_REV_ID_BIT_RTP) 1113 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1138 IWL_DEBUG_INFO("RTP type \n"); 1114 IWL_DEBUG_INFO("RTP type \n");
1139 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { 1115 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1140 IWL_DEBUG_INFO("3945 RADIO-MB type\n"); 1116 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1141 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1117 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1142 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB); 1118 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1143 } else { 1119 } else {
1144 IWL_DEBUG_INFO("3945 RADIO-MM type\n"); 1120 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1145 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1121 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1146 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM); 1122 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1147 } 1123 }
1148 1124
1149 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) { 1125 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1150 IWL_DEBUG_INFO("SKU OP mode is mrc\n"); 1126 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1151 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1127 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1152 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC); 1128 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1153 } else 1129 } else
1154 IWL_DEBUG_INFO("SKU OP mode is basic\n"); 1130 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1155 1131
1156 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) { 1132 if ((eeprom->board_revision & 0xF0) == 0xD0) {
1157 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", 1133 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1158 priv->eeprom.board_revision); 1134 eeprom->board_revision);
1159 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1135 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1160 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 1136 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1161 } else { 1137 } else {
1162 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", 1138 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1163 priv->eeprom.board_revision); 1139 eeprom->board_revision);
1164 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG, 1140 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1165 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 1141 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1166 } 1142 }
1167 1143
1168 if (priv->eeprom.almgor_m_version <= 1) { 1144 if (eeprom->almgor_m_version <= 1) {
1169 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1145 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1170 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); 1146 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1171 IWL_DEBUG_INFO("Card M type A version is 0x%X\n", 1147 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1172 priv->eeprom.almgor_m_version); 1148 eeprom->almgor_m_version);
1173 } else { 1149 } else {
1174 IWL_DEBUG_INFO("Card M type B version is 0x%X\n", 1150 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1175 priv->eeprom.almgor_m_version); 1151 eeprom->almgor_m_version);
1176 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG, 1152 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1177 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); 1153 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1178 } 1154 }
1179 spin_unlock_irqrestore(&priv->lock, flags); 1155 spin_unlock_irqrestore(&priv->lock, flags);
1180 1156
1181 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE) 1157 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1182 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n"); 1158 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1183 1159
1184 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE) 1160 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1185 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n"); 1161 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1162}
1163
1164int iwl3945_hw_nic_init(struct iwl_priv *priv)
1165{
1166 u8 rev_id;
1167 int rc;
1168 unsigned long flags;
1169 struct iwl_rx_queue *rxq = &priv->rxq;
1170
1171 spin_lock_irqsave(&priv->lock, flags);
1172 priv->cfg->ops->lib->apm_ops.init(priv);
1173 spin_unlock_irqrestore(&priv->lock, flags);
1174
1175 /* Determine HW type */
1176 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1177 if (rc)
1178 return rc;
1179 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1180
1181 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1182 if(rc)
1183 return rc;
1184
1185 priv->cfg->ops->lib->apm_ops.config(priv);
1186 1186
1187 /* Allocate the RX queue, or reset if it is already allocated */ 1187 /* Allocate the RX queue, or reset if it is already allocated */
1188 if (!rxq->bd) { 1188 if (!rxq->bd) {
1189 rc = iwl3945_rx_queue_alloc(priv); 1189 rc = iwl_rx_queue_alloc(priv);
1190 if (rc) { 1190 if (rc) {
1191 IWL_ERROR("Unable to initialize Rx queue\n"); 1191 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1192 return -ENOMEM; 1192 return -ENOMEM;
1193 } 1193 }
1194 } else 1194 } else
1195 iwl3945_rx_queue_reset(priv, rxq); 1195 iwl_rx_queue_reset(priv, rxq);
1196 1196
1197 iwl3945_rx_replenish(priv); 1197 iwl3945_rx_replenish(priv);
1198 1198
@@ -1202,16 +1202,16 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1202 1202
1203 /* Look at using this instead: 1203 /* Look at using this instead:
1204 rxq->need_update = 1; 1204 rxq->need_update = 1;
1205 iwl3945_rx_queue_update_write_ptr(priv, rxq); 1205 iwl_rx_queue_update_write_ptr(priv, rxq);
1206 */ 1206 */
1207 1207
1208 rc = iwl3945_grab_nic_access(priv); 1208 rc = iwl_grab_nic_access(priv);
1209 if (rc) { 1209 if (rc) {
1210 spin_unlock_irqrestore(&priv->lock, flags); 1210 spin_unlock_irqrestore(&priv->lock, flags);
1211 return rc; 1211 return rc;
1212 } 1212 }
1213 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7); 1213 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1214 iwl3945_release_nic_access(priv); 1214 iwl_release_nic_access(priv);
1215 1215
1216 spin_unlock_irqrestore(&priv->lock, flags); 1216 spin_unlock_irqrestore(&priv->lock, flags);
1217 1217
@@ -1229,116 +1229,121 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1229 * 1229 *
1230 * Destroy all TX DMA queues and structures 1230 * Destroy all TX DMA queues and structures
1231 */ 1231 */
1232void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv) 1232void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1233{ 1233{
1234 int txq_id; 1234 int txq_id;
1235 1235
1236 /* Tx queues */ 1236 /* Tx queues */
1237 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) 1237 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1238 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]); 1238 iwl_tx_queue_free(priv, txq_id);
1239} 1239}
1240 1240
1241void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv) 1241void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1242{ 1242{
1243 int queue; 1243 int txq_id;
1244 unsigned long flags; 1244 unsigned long flags;
1245 1245
1246 spin_lock_irqsave(&priv->lock, flags); 1246 spin_lock_irqsave(&priv->lock, flags);
1247 if (iwl3945_grab_nic_access(priv)) { 1247 if (iwl_grab_nic_access(priv)) {
1248 spin_unlock_irqrestore(&priv->lock, flags); 1248 spin_unlock_irqrestore(&priv->lock, flags);
1249 iwl3945_hw_txq_ctx_free(priv); 1249 iwl3945_hw_txq_ctx_free(priv);
1250 return; 1250 return;
1251 } 1251 }
1252 1252
1253 /* stop SCD */ 1253 /* stop SCD */
1254 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0); 1254 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1255 1255
1256 /* reset TFD queues */ 1256 /* reset TFD queues */
1257 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) { 1257 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1258 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0); 1258 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1259 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS, 1259 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1260 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue), 1260 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1261 1000); 1261 1000);
1262 } 1262 }
1263 1263
1264 iwl3945_release_nic_access(priv); 1264 iwl_release_nic_access(priv);
1265 spin_unlock_irqrestore(&priv->lock, flags); 1265 spin_unlock_irqrestore(&priv->lock, flags);
1266 1266
1267 iwl3945_hw_txq_ctx_free(priv); 1267 iwl3945_hw_txq_ctx_free(priv);
1268} 1268}
1269 1269
1270int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv) 1270static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1271{ 1271{
1272 int rc = 0; 1272 int ret = 0;
1273 u32 reg_val;
1274 unsigned long flags; 1273 unsigned long flags;
1275 1274
1276 spin_lock_irqsave(&priv->lock, flags); 1275 spin_lock_irqsave(&priv->lock, flags);
1277 1276
1278 /* set stop master bit */ 1277 /* set stop master bit */
1279 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 1278 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1280 1279
1281 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL); 1280 iwl_poll_direct_bit(priv, CSR_RESET,
1281 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1282 1282
1283 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE == 1283 if (ret < 0)
1284 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE)) 1284 goto out;
1285 IWL_DEBUG_INFO("Card in power save, master is already "
1286 "stopped\n");
1287 else {
1288 rc = iwl3945_poll_direct_bit(priv, CSR_RESET,
1289 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1290 if (rc < 0) {
1291 spin_unlock_irqrestore(&priv->lock, flags);
1292 return rc;
1293 }
1294 }
1295 1285
1286out:
1296 spin_unlock_irqrestore(&priv->lock, flags); 1287 spin_unlock_irqrestore(&priv->lock, flags);
1297 IWL_DEBUG_INFO("stop master\n"); 1288 IWL_DEBUG_INFO("stop master\n");
1298 1289
1299 return rc; 1290 return ret;
1291}
1292
1293static void iwl3945_apm_stop(struct iwl_priv *priv)
1294{
1295 unsigned long flags;
1296
1297 iwl3945_apm_stop_master(priv);
1298
1299 spin_lock_irqsave(&priv->lock, flags);
1300
1301 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1302
1303 udelay(10);
1304 /* clear "init complete" move adapter D0A* --> D0U state */
1305 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1306 spin_unlock_irqrestore(&priv->lock, flags);
1300} 1307}
1301 1308
1302int iwl3945_hw_nic_reset(struct iwl3945_priv *priv) 1309static int iwl3945_apm_reset(struct iwl_priv *priv)
1303{ 1310{
1304 int rc; 1311 int rc;
1305 unsigned long flags; 1312 unsigned long flags;
1306 1313
1307 iwl3945_hw_nic_stop_master(priv); 1314 iwl3945_apm_stop_master(priv);
1308 1315
1309 spin_lock_irqsave(&priv->lock, flags); 1316 spin_lock_irqsave(&priv->lock, flags);
1310 1317
1311 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1318 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1319 udelay(10);
1312 1320
1313 iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL, 1321 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1322
1323 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1314 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 1324 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1315 1325
1316 rc = iwl3945_grab_nic_access(priv); 1326 rc = iwl_grab_nic_access(priv);
1317 if (!rc) { 1327 if (!rc) {
1318 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG, 1328 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1319 APMG_CLK_VAL_BSM_CLK_RQT); 1329 APMG_CLK_VAL_BSM_CLK_RQT);
1320 1330
1321 udelay(10); 1331 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1322 1332 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1323 iwl3945_set_bit(priv, CSR_GP_CNTRL,
1324 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1325
1326 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1327 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
1328 0xFFFFFFFF); 1333 0xFFFFFFFF);
1329 1334
1330 /* enable DMA */ 1335 /* enable DMA */
1331 iwl3945_write_prph(priv, APMG_CLK_EN_REG, 1336 iwl_write_prph(priv, APMG_CLK_EN_REG,
1332 APMG_CLK_VAL_DMA_CLK_RQT | 1337 APMG_CLK_VAL_DMA_CLK_RQT |
1333 APMG_CLK_VAL_BSM_CLK_RQT); 1338 APMG_CLK_VAL_BSM_CLK_RQT);
1334 udelay(10); 1339 udelay(10);
1335 1340
1336 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG, 1341 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1337 APMG_PS_CTRL_VAL_RESET_REQ); 1342 APMG_PS_CTRL_VAL_RESET_REQ);
1338 udelay(5); 1343 udelay(5);
1339 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG, 1344 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1340 APMG_PS_CTRL_VAL_RESET_REQ); 1345 APMG_PS_CTRL_VAL_RESET_REQ);
1341 iwl3945_release_nic_access(priv); 1346 iwl_release_nic_access(priv);
1342 } 1347 }
1343 1348
1344 /* Clear the 'host command active' bit... */ 1349 /* Clear the 'host command active' bit... */
@@ -1367,17 +1372,18 @@ static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1367 return ((temperature < -260) || (temperature > 25)) ? 1 : 0; 1372 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1368} 1373}
1369 1374
1370int iwl3945_hw_get_temperature(struct iwl3945_priv *priv) 1375int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1371{ 1376{
1372 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2); 1377 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1373} 1378}
1374 1379
1375/** 1380/**
1376 * iwl3945_hw_reg_txpower_get_temperature 1381 * iwl3945_hw_reg_txpower_get_temperature
1377 * get the current temperature by reading from NIC 1382 * get the current temperature by reading from NIC
1378*/ 1383*/
1379static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv) 1384static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1380{ 1385{
1386 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1381 int temperature; 1387 int temperature;
1382 1388
1383 temperature = iwl3945_hw_get_temperature(priv); 1389 temperature = iwl3945_hw_get_temperature(priv);
@@ -1388,12 +1394,12 @@ static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
1388 1394
1389 /* handle insane temp reading */ 1395 /* handle insane temp reading */
1390 if (iwl3945_hw_reg_temp_out_of_range(temperature)) { 1396 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1391 IWL_ERROR("Error bad temperature value %d\n", temperature); 1397 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1392 1398
1393 /* if really really hot(?), 1399 /* if really really hot(?),
1394 * substitute the 3rd band/group's temp measured at factory */ 1400 * substitute the 3rd band/group's temp measured at factory */
1395 if (priv->last_temperature > 100) 1401 if (priv->last_temperature > 100)
1396 temperature = priv->eeprom.groups[2].temperature; 1402 temperature = eeprom->groups[2].temperature;
1397 else /* else use most recent "sane" value from driver */ 1403 else /* else use most recent "sane" value from driver */
1398 temperature = priv->last_temperature; 1404 temperature = priv->last_temperature;
1399 } 1405 }
@@ -1412,7 +1418,7 @@ static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
1412 * records new temperature in tx_mgr->temperature. 1418 * records new temperature in tx_mgr->temperature.
1413 * replaces tx_mgr->last_temperature *only* if calib needed 1419 * replaces tx_mgr->last_temperature *only* if calib needed
1414 * (assumes caller will actually do the calibration!). */ 1420 * (assumes caller will actually do the calibration!). */
1415static int is_temp_calib_needed(struct iwl3945_priv *priv) 1421static int is_temp_calib_needed(struct iwl_priv *priv)
1416{ 1422{
1417 int temp_diff; 1423 int temp_diff;
1418 1424
@@ -1627,9 +1633,9 @@ static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1627 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK) 1633 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1628 * or 6 Mbit (OFDM) rates. 1634 * or 6 Mbit (OFDM) rates.
1629 */ 1635 */
1630static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index, 1636static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1631 s32 rate_index, const s8 *clip_pwrs, 1637 s32 rate_index, const s8 *clip_pwrs,
1632 struct iwl3945_channel_info *ch_info, 1638 struct iwl_channel_info *ch_info,
1633 int band_index) 1639 int band_index)
1634{ 1640{
1635 struct iwl3945_scan_power_info *scan_power_info; 1641 struct iwl3945_scan_power_info *scan_power_info;
@@ -1646,7 +1652,7 @@ static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tb
1646 /* further limit to user's max power preference. 1652 /* further limit to user's max power preference.
1647 * FIXME: Other spectrum management power limitations do not 1653 * FIXME: Other spectrum management power limitations do not
1648 * seem to apply?? */ 1654 * seem to apply?? */
1649 power = min(power, priv->user_txpower_limit); 1655 power = min(power, priv->tx_power_user_lmt);
1650 scan_power_info->requested_power = power; 1656 scan_power_info->requested_power = power;
1651 1657
1652 /* find difference between new scan *power* and current "normal" 1658 /* find difference between new scan *power* and current "normal"
@@ -1678,27 +1684,27 @@ static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tb
1678} 1684}
1679 1685
1680/** 1686/**
1681 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings 1687 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1682 * 1688 *
1683 * Configures power settings for all rates for the current channel, 1689 * Configures power settings for all rates for the current channel,
1684 * using values from channel info struct, and send to NIC 1690 * using values from channel info struct, and send to NIC
1685 */ 1691 */
1686int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv) 1692int iwl3945_send_tx_power(struct iwl_priv *priv)
1687{ 1693{
1688 int rate_idx, i; 1694 int rate_idx, i;
1689 const struct iwl3945_channel_info *ch_info = NULL; 1695 const struct iwl_channel_info *ch_info = NULL;
1690 struct iwl3945_txpowertable_cmd txpower = { 1696 struct iwl3945_txpowertable_cmd txpower = {
1691 .channel = priv->active_rxon.channel, 1697 .channel = priv->active39_rxon.channel,
1692 }; 1698 };
1693 1699
1694 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1; 1700 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1695 ch_info = iwl3945_get_channel_info(priv, 1701 ch_info = iwl_get_channel_info(priv,
1696 priv->band, 1702 priv->band,
1697 le16_to_cpu(priv->active_rxon.channel)); 1703 le16_to_cpu(priv->active39_rxon.channel));
1698 if (!ch_info) { 1704 if (!ch_info) {
1699 IWL_ERROR 1705 IWL_ERR(priv,
1700 ("Failed to get channel info for channel %d [%d]\n", 1706 "Failed to get channel info for channel %d [%d]\n",
1701 le16_to_cpu(priv->active_rxon.channel), priv->band); 1707 le16_to_cpu(priv->active39_rxon.channel), priv->band);
1702 return -EINVAL; 1708 return -EINVAL;
1703 } 1709 }
1704 1710
@@ -1711,7 +1717,7 @@ int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
1711 /* fill cmd with power settings for all rates for current channel */ 1717 /* fill cmd with power settings for all rates for current channel */
1712 /* Fill OFDM rate */ 1718 /* Fill OFDM rate */
1713 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0; 1719 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1714 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) { 1720 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1715 1721
1716 txpower.power[i].tpc = ch_info->power_info[i].tpc; 1722 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1717 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp; 1723 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
@@ -1737,8 +1743,9 @@ int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
1737 txpower.power[i].rate); 1743 txpower.power[i].rate);
1738 } 1744 }
1739 1745
1740 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, 1746 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1741 sizeof(struct iwl3945_txpowertable_cmd), &txpower); 1747 sizeof(struct iwl3945_txpowertable_cmd),
1748 &txpower);
1742 1749
1743} 1750}
1744 1751
@@ -1758,8 +1765,8 @@ int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
1758 * properly fill out the scan powers, and actual h/w gain settings, 1765 * properly fill out the scan powers, and actual h/w gain settings,
1759 * and send changes to NIC 1766 * and send changes to NIC
1760 */ 1767 */
1761static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv, 1768static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1762 struct iwl3945_channel_info *ch_info) 1769 struct iwl_channel_info *ch_info)
1763{ 1770{
1764 struct iwl3945_channel_power_info *power_info; 1771 struct iwl3945_channel_power_info *power_info;
1765 int power_changed = 0; 1772 int power_changed = 0;
@@ -1768,7 +1775,7 @@ static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1768 int power; 1775 int power;
1769 1776
1770 /* Get this chnlgrp's rate-to-max/clip-powers table */ 1777 /* Get this chnlgrp's rate-to-max/clip-powers table */
1771 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers; 1778 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1772 1779
1773 /* Get this channel's rate-to-current-power settings table */ 1780 /* Get this channel's rate-to-current-power settings table */
1774 power_info = ch_info->power_info; 1781 power_info = ch_info->power_info;
@@ -1821,7 +1828,7 @@ static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1821 * based strictly on regulatory (eeprom and spectrum mgt) limitations 1828 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1822 * (no consideration for h/w clipping limitations). 1829 * (no consideration for h/w clipping limitations).
1823 */ 1830 */
1824static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info) 1831static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1825{ 1832{
1826 s8 max_power; 1833 s8 max_power;
1827 1834
@@ -1849,9 +1856,10 @@ static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_i
1849 * 1856 *
1850 * If RxOn is "associated", this sends the new Txpower to NIC! 1857 * If RxOn is "associated", this sends the new Txpower to NIC!
1851 */ 1858 */
1852static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv) 1859static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1853{ 1860{
1854 struct iwl3945_channel_info *ch_info = NULL; 1861 struct iwl_channel_info *ch_info = NULL;
1862 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1855 int delta_index; 1863 int delta_index;
1856 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */ 1864 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1857 u8 a_band; 1865 u8 a_band;
@@ -1867,7 +1875,7 @@ static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
1867 a_band = is_channel_a_band(ch_info); 1875 a_band = is_channel_a_band(ch_info);
1868 1876
1869 /* Get this chnlgrp's factory calibration temperature */ 1877 /* Get this chnlgrp's factory calibration temperature */
1870 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index]. 1878 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1871 temperature; 1879 temperature;
1872 1880
1873 /* get power index adjustment based on current and factory 1881 /* get power index adjustment based on current and factory
@@ -1893,7 +1901,7 @@ static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
1893 } 1901 }
1894 1902
1895 /* Get this chnlgrp's rate-to-max/clip-powers table */ 1903 /* Get this chnlgrp's rate-to-max/clip-powers table */
1896 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers; 1904 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1897 1905
1898 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ 1906 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1899 for (scan_tbl_index = 0; 1907 for (scan_tbl_index = 0;
@@ -1907,24 +1915,24 @@ static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
1907 } 1915 }
1908 1916
1909 /* send Txpower command for current channel to ucode */ 1917 /* send Txpower command for current channel to ucode */
1910 return iwl3945_hw_reg_send_txpower(priv); 1918 return priv->cfg->ops->lib->send_tx_power(priv);
1911} 1919}
1912 1920
1913int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power) 1921int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1914{ 1922{
1915 struct iwl3945_channel_info *ch_info; 1923 struct iwl_channel_info *ch_info;
1916 s8 max_power; 1924 s8 max_power;
1917 u8 a_band; 1925 u8 a_band;
1918 u8 i; 1926 u8 i;
1919 1927
1920 if (priv->user_txpower_limit == power) { 1928 if (priv->tx_power_user_lmt == power) {
1921 IWL_DEBUG_POWER("Requested Tx power same as current " 1929 IWL_DEBUG_POWER("Requested Tx power same as current "
1922 "limit: %ddBm.\n", power); 1930 "limit: %ddBm.\n", power);
1923 return 0; 1931 return 0;
1924 } 1932 }
1925 1933
1926 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power); 1934 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1927 priv->user_txpower_limit = power; 1935 priv->tx_power_user_lmt = power;
1928 1936
1929 /* set up new Tx powers for each and every channel, 2.4 and 5.x */ 1937 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1930 1938
@@ -1953,7 +1961,7 @@ int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
1953} 1961}
1954 1962
1955/* will add 3945 channel switch cmd handling later */ 1963/* will add 3945 channel switch cmd handling later */
1956int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel) 1964int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1957{ 1965{
1958 return 0; 1966 return 0;
1959} 1967}
@@ -1968,7 +1976,7 @@ int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
1968 * -- send new set of gain settings to NIC 1976 * -- send new set of gain settings to NIC
1969 * NOTE: This should continue working, even when we're not associated, 1977 * NOTE: This should continue working, even when we're not associated,
1970 * so we can keep our internal table of scan powers current. */ 1978 * so we can keep our internal table of scan powers current. */
1971void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv) 1979void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1972{ 1980{
1973 /* This will kick in the "brute force" 1981 /* This will kick in the "brute force"
1974 * iwl3945_hw_reg_comp_txpower_temp() below */ 1982 * iwl3945_hw_reg_comp_txpower_temp() below */
@@ -1987,7 +1995,7 @@ void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
1987 1995
1988static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) 1996static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1989{ 1997{
1990 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, 1998 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1991 thermal_periodic.work); 1999 thermal_periodic.work);
1992 2000
1993 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 2001 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
@@ -2009,10 +2017,11 @@ static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2009 * on A-band, EEPROM's "group frequency" entries represent the top 2017 * on A-band, EEPROM's "group frequency" entries represent the top
2010 * channel in each group 1-4. Group 5 All B/G channels are in group 0. 2018 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2011 */ 2019 */
2012static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv, 2020static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2013 const struct iwl3945_channel_info *ch_info) 2021 const struct iwl_channel_info *ch_info)
2014{ 2022{
2015 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0]; 2023 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2024 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2016 u8 group; 2025 u8 group;
2017 u16 group_index = 0; /* based on factory calib frequencies */ 2026 u16 group_index = 0; /* based on factory calib frequencies */
2018 u8 grp_channel; 2027 u8 grp_channel;
@@ -2043,11 +2052,12 @@ static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
2043 * Interpolate to get nominal (i.e. at factory calibration temperature) index 2052 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2044 * into radio/DSP gain settings table for requested power. 2053 * into radio/DSP gain settings table for requested power.
2045 */ 2054 */
2046static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv, 2055static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2047 s8 requested_power, 2056 s8 requested_power,
2048 s32 setting_index, s32 *new_index) 2057 s32 setting_index, s32 *new_index)
2049{ 2058{
2050 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL; 2059 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2060 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2051 s32 index0, index1; 2061 s32 index0, index1;
2052 s32 power = 2 * requested_power; 2062 s32 power = 2 * requested_power;
2053 s32 i; 2063 s32 i;
@@ -2056,7 +2066,7 @@ static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
2056 s32 res; 2066 s32 res;
2057 s32 denominator; 2067 s32 denominator;
2058 2068
2059 chnl_grp = &priv->eeprom.groups[setting_index]; 2069 chnl_grp = &eeprom->groups[setting_index];
2060 samples = chnl_grp->samples; 2070 samples = chnl_grp->samples;
2061 for (i = 0; i < 5; i++) { 2071 for (i = 0; i < 5; i++) {
2062 if (power == samples[i].power) { 2072 if (power == samples[i].power) {
@@ -2091,10 +2101,11 @@ static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
2091 return 0; 2101 return 0;
2092} 2102}
2093 2103
2094static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv) 2104static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2095{ 2105{
2096 u32 i; 2106 u32 i;
2097 s32 rate_index; 2107 s32 rate_index;
2108 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2098 const struct iwl3945_eeprom_txpower_group *group; 2109 const struct iwl3945_eeprom_txpower_group *group;
2099 2110
2100 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n"); 2111 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
@@ -2102,11 +2113,11 @@ static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
2102 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) { 2113 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2103 s8 *clip_pwrs; /* table of power levels for each rate */ 2114 s8 *clip_pwrs; /* table of power levels for each rate */
2104 s8 satur_pwr; /* saturation power for each chnl group */ 2115 s8 satur_pwr; /* saturation power for each chnl group */
2105 group = &priv->eeprom.groups[i]; 2116 group = &eeprom->groups[i];
2106 2117
2107 /* sanity check on factory saturation power value */ 2118 /* sanity check on factory saturation power value */
2108 if (group->saturation_power < 40) { 2119 if (group->saturation_power < 40) {
2109 IWL_WARNING("Error: saturation power is %d, " 2120 IWL_WARN(priv, "Error: saturation power is %d, "
2110 "less than minimum expected 40\n", 2121 "less than minimum expected 40\n",
2111 group->saturation_power); 2122 group->saturation_power);
2112 return; 2123 return;
@@ -2121,7 +2132,7 @@ static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
2121 * power peaks, without too much distortion (clipping). 2132 * power peaks, without too much distortion (clipping).
2122 */ 2133 */
2123 /* we'll fill in this array with h/w max power levels */ 2134 /* we'll fill in this array with h/w max power levels */
2124 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers; 2135 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2125 2136
2126 /* divide factory saturation power by 2 to find -3dB level */ 2137 /* divide factory saturation power by 2 to find -3dB level */
2127 satur_pwr = (s8) (group->saturation_power >> 1); 2138 satur_pwr = (s8) (group->saturation_power >> 1);
@@ -2171,10 +2182,11 @@ static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
2171 * 2182 *
2172 * This does *not* write values to NIC, just sets up our internal table. 2183 * This does *not* write values to NIC, just sets up our internal table.
2173 */ 2184 */
2174int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv) 2185int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2175{ 2186{
2176 struct iwl3945_channel_info *ch_info = NULL; 2187 struct iwl_channel_info *ch_info = NULL;
2177 struct iwl3945_channel_power_info *pwr_info; 2188 struct iwl3945_channel_power_info *pwr_info;
2189 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2178 int delta_index; 2190 int delta_index;
2179 u8 rate_index; 2191 u8 rate_index;
2180 u8 scan_tbl_index; 2192 u8 scan_tbl_index;
@@ -2204,12 +2216,12 @@ int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
2204 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info); 2216 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2205 2217
2206 /* Get this chnlgrp's rate->max/clip-powers table */ 2218 /* Get this chnlgrp's rate->max/clip-powers table */
2207 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers; 2219 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2208 2220
2209 /* calculate power index *adjustment* value according to 2221 /* calculate power index *adjustment* value according to
2210 * diff between current temperature and factory temperature */ 2222 * diff between current temperature and factory temperature */
2211 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature, 2223 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2212 priv->eeprom.groups[ch_info->group_index]. 2224 eeprom->groups[ch_info->group_index].
2213 temperature); 2225 temperature);
2214 2226
2215 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n", 2227 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
@@ -2235,7 +2247,7 @@ int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
2235 ch_info->group_index, 2247 ch_info->group_index,
2236 &power_idx); 2248 &power_idx);
2237 if (rc) { 2249 if (rc) {
2238 IWL_ERROR("Invalid power index\n"); 2250 IWL_ERR(priv, "Invalid power index\n");
2239 return rc; 2251 return rc;
2240 } 2252 }
2241 pwr_info->base_power_index = (u8) power_idx; 2253 pwr_info->base_power_index = (u8) power_idx;
@@ -2295,75 +2307,88 @@ int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
2295 return 0; 2307 return 0;
2296} 2308}
2297 2309
2298int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv) 2310int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2299{ 2311{
2300 int rc; 2312 int rc;
2301 unsigned long flags; 2313 unsigned long flags;
2302 2314
2303 spin_lock_irqsave(&priv->lock, flags); 2315 spin_lock_irqsave(&priv->lock, flags);
2304 rc = iwl3945_grab_nic_access(priv); 2316 rc = iwl_grab_nic_access(priv);
2305 if (rc) { 2317 if (rc) {
2306 spin_unlock_irqrestore(&priv->lock, flags); 2318 spin_unlock_irqrestore(&priv->lock, flags);
2307 return rc; 2319 return rc;
2308 } 2320 }
2309 2321
2310 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0); 2322 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2311 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, 2323 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2312 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 2324 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2313 if (rc < 0) 2325 if (rc < 0)
2314 IWL_ERROR("Can't stop Rx DMA.\n"); 2326 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2315 2327
2316 iwl3945_release_nic_access(priv); 2328 iwl_release_nic_access(priv);
2317 spin_unlock_irqrestore(&priv->lock, flags); 2329 spin_unlock_irqrestore(&priv->lock, flags);
2318 2330
2319 return 0; 2331 return 0;
2320} 2332}
2321 2333
2322int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq) 2334int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2323{ 2335{
2324 int rc; 2336 int rc;
2325 unsigned long flags; 2337 unsigned long flags;
2326 int txq_id = txq->q.id; 2338 int txq_id = txq->q.id;
2327 2339
2328 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt; 2340 struct iwl3945_shared *shared_data = priv->shared_virt;
2329 2341
2330 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); 2342 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2331 2343
2332 spin_lock_irqsave(&priv->lock, flags); 2344 spin_lock_irqsave(&priv->lock, flags);
2333 rc = iwl3945_grab_nic_access(priv); 2345 rc = iwl_grab_nic_access(priv);
2334 if (rc) { 2346 if (rc) {
2335 spin_unlock_irqrestore(&priv->lock, flags); 2347 spin_unlock_irqrestore(&priv->lock, flags);
2336 return rc; 2348 return rc;
2337 } 2349 }
2338 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0); 2350 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2339 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0); 2351 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2340 2352
2341 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id), 2353 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2342 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | 2354 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2343 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | 2355 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2344 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | 2356 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2345 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | 2357 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2346 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); 2358 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2347 iwl3945_release_nic_access(priv); 2359 iwl_release_nic_access(priv);
2348 2360
2349 /* fake read to flush all prev. writes */ 2361 /* fake read to flush all prev. writes */
2350 iwl3945_read32(priv, FH_TSSR_CBB_BASE); 2362 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2351 spin_unlock_irqrestore(&priv->lock, flags); 2363 spin_unlock_irqrestore(&priv->lock, flags);
2352 2364
2353 return 0; 2365 return 0;
2354} 2366}
2355 2367
2356int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv) 2368/*
2369 * HCMD utils
2370 */
2371static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2357{ 2372{
2358 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt; 2373 switch (cmd_id) {
2374 case REPLY_RXON:
2375 return (u16) sizeof(struct iwl3945_rxon_cmd);
2376 default:
2377 return len;
2378 }
2379}
2359 2380
2360 return le32_to_cpu(shared_data->rx_read_ptr[0]); 2381static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2382{
2383 u16 size = (u16)sizeof(struct iwl3945_addsta_cmd);
2384 memcpy(data, cmd, size);
2385 return size;
2361} 2386}
2362 2387
2363/** 2388/**
2364 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table 2389 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2365 */ 2390 */
2366int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv) 2391int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2367{ 2392{
2368 int rc, i, index, prev_index; 2393 int rc, i, index, prev_index;
2369 struct iwl3945_rate_scaling_cmd rate_cmd = { 2394 struct iwl3945_rate_scaling_cmd rate_cmd = {
@@ -2428,47 +2453,48 @@ int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
2428 2453
2429 /* Update the rate scaling for control frame Tx */ 2454 /* Update the rate scaling for control frame Tx */
2430 rate_cmd.table_id = 0; 2455 rate_cmd.table_id = 0;
2431 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), 2456 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2432 &rate_cmd); 2457 &rate_cmd);
2433 if (rc) 2458 if (rc)
2434 return rc; 2459 return rc;
2435 2460
2436 /* Update the rate scaling for data frame Tx */ 2461 /* Update the rate scaling for data frame Tx */
2437 rate_cmd.table_id = 1; 2462 rate_cmd.table_id = 1;
2438 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), 2463 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2439 &rate_cmd); 2464 &rate_cmd);
2440} 2465}
2441 2466
2442/* Called when initializing driver */ 2467/* Called when initializing driver */
2443int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv) 2468int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2444{ 2469{
2445 memset((void *)&priv->hw_setting, 0, 2470 memset((void *)&priv->hw_params, 0,
2446 sizeof(struct iwl3945_driver_hw_info)); 2471 sizeof(struct iwl_hw_params));
2447 2472
2448 priv->hw_setting.shared_virt = 2473 priv->shared_virt =
2449 pci_alloc_consistent(priv->pci_dev, 2474 pci_alloc_consistent(priv->pci_dev,
2450 sizeof(struct iwl3945_shared), 2475 sizeof(struct iwl3945_shared),
2451 &priv->hw_setting.shared_phys); 2476 &priv->shared_phys);
2452 2477
2453 if (!priv->hw_setting.shared_virt) { 2478 if (!priv->shared_virt) {
2454 IWL_ERROR("failed to allocate pci memory\n"); 2479 IWL_ERR(priv, "failed to allocate pci memory\n");
2455 mutex_unlock(&priv->mutex); 2480 mutex_unlock(&priv->mutex);
2456 return -ENOMEM; 2481 return -ENOMEM;
2457 } 2482 }
2458 2483
2459 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE; 2484 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2460 priv->hw_setting.max_pkt_size = 2342; 2485 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2461 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd); 2486 priv->hw_params.max_pkt_size = 2342;
2462 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE; 2487 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2463 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG; 2488 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2464 priv->hw_setting.max_stations = IWL3945_STATION_COUNT; 2489 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2465 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID; 2490 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2491
2492 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2466 2493
2467 priv->hw_setting.tx_ant_num = 2;
2468 return 0; 2494 return 0;
2469} 2495}
2470 2496
2471unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv, 2497unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2472 struct iwl3945_frame *frame, u8 rate) 2498 struct iwl3945_frame *frame, u8 rate)
2473{ 2499{
2474 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd; 2500 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
@@ -2477,7 +2503,7 @@ unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2477 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u; 2503 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2478 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); 2504 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2479 2505
2480 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id; 2506 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2481 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 2507 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2482 2508
2483 frame_size = iwl3945_fill_beacon_frame(priv, 2509 frame_size = iwl3945_fill_beacon_frame(priv,
@@ -2501,37 +2527,261 @@ unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2501 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size; 2527 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2502} 2528}
2503 2529
2504void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv) 2530void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2505{ 2531{
2506 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx; 2532 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2507 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx; 2533 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2508} 2534}
2509 2535
2510void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv) 2536void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2511{ 2537{
2512 INIT_DELAYED_WORK(&priv->thermal_periodic, 2538 INIT_DELAYED_WORK(&priv->thermal_periodic,
2513 iwl3945_bg_reg_txpower_periodic); 2539 iwl3945_bg_reg_txpower_periodic);
2514} 2540}
2515 2541
2516void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv) 2542void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2517{ 2543{
2518 cancel_delayed_work(&priv->thermal_periodic); 2544 cancel_delayed_work(&priv->thermal_periodic);
2519} 2545}
2520 2546
2521static struct iwl_3945_cfg iwl3945_bg_cfg = { 2547/* check contents of special bootstrap uCode SRAM */
2548static int iwl3945_verify_bsm(struct iwl_priv *priv)
2549 {
2550 __le32 *image = priv->ucode_boot.v_addr;
2551 u32 len = priv->ucode_boot.len;
2552 u32 reg;
2553 u32 val;
2554
2555 IWL_DEBUG_INFO("Begin verify bsm\n");
2556
2557 /* verify BSM SRAM contents */
2558 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2559 for (reg = BSM_SRAM_LOWER_BOUND;
2560 reg < BSM_SRAM_LOWER_BOUND + len;
2561 reg += sizeof(u32), image++) {
2562 val = iwl_read_prph(priv, reg);
2563 if (val != le32_to_cpu(*image)) {
2564 IWL_ERR(priv, "BSM uCode verification failed at "
2565 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2566 BSM_SRAM_LOWER_BOUND,
2567 reg - BSM_SRAM_LOWER_BOUND, len,
2568 val, le32_to_cpu(*image));
2569 return -EIO;
2570 }
2571 }
2572
2573 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2574
2575 return 0;
2576}
2577
2578
2579/******************************************************************************
2580 *
2581 * EEPROM related functions
2582 *
2583 ******************************************************************************/
2584
2585/*
2586 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2587 * embedded controller) as EEPROM reader; each read is a series of pulses
2588 * to/from the EEPROM chip, not a single event, so even reads could conflict
2589 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2590 * simply claims ownership, which should be safe when this function is called
2591 * (i.e. before loading uCode!).
2592 */
2593static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2594{
2595 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2596 return 0;
2597}
2598
2599
2600static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2601{
2602 return;
2603}
2604
2605 /**
2606 * iwl3945_load_bsm - Load bootstrap instructions
2607 *
2608 * BSM operation:
2609 *
2610 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2611 * in special SRAM that does not power down during RFKILL. When powering back
2612 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2613 * the bootstrap program into the on-board processor, and starts it.
2614 *
2615 * The bootstrap program loads (via DMA) instructions and data for a new
2616 * program from host DRAM locations indicated by the host driver in the
2617 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2618 * automatically.
2619 *
2620 * When initializing the NIC, the host driver points the BSM to the
2621 * "initialize" uCode image. This uCode sets up some internal data, then
2622 * notifies host via "initialize alive" that it is complete.
2623 *
2624 * The host then replaces the BSM_DRAM_* pointer values to point to the
2625 * normal runtime uCode instructions and a backup uCode data cache buffer
2626 * (filled initially with starting data values for the on-board processor),
2627 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2628 * which begins normal operation.
2629 *
2630 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2631 * the backup data cache in DRAM before SRAM is powered down.
2632 *
2633 * When powering back up, the BSM loads the bootstrap program. This reloads
2634 * the runtime uCode instructions and the backup data cache into SRAM,
2635 * and re-launches the runtime uCode from where it left off.
2636 */
2637static int iwl3945_load_bsm(struct iwl_priv *priv)
2638{
2639 __le32 *image = priv->ucode_boot.v_addr;
2640 u32 len = priv->ucode_boot.len;
2641 dma_addr_t pinst;
2642 dma_addr_t pdata;
2643 u32 inst_len;
2644 u32 data_len;
2645 int rc;
2646 int i;
2647 u32 done;
2648 u32 reg_offset;
2649
2650 IWL_DEBUG_INFO("Begin load bsm\n");
2651
2652 /* make sure bootstrap program is no larger than BSM's SRAM size */
2653 if (len > IWL39_MAX_BSM_SIZE)
2654 return -EINVAL;
2655
2656 /* Tell bootstrap uCode where to find the "Initialize" uCode
2657 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2658 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2659 * after the "initialize" uCode has run, to point to
2660 * runtime/protocol instructions and backup data cache. */
2661 pinst = priv->ucode_init.p_addr;
2662 pdata = priv->ucode_init_data.p_addr;
2663 inst_len = priv->ucode_init.len;
2664 data_len = priv->ucode_init_data.len;
2665
2666 rc = iwl_grab_nic_access(priv);
2667 if (rc)
2668 return rc;
2669
2670 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2671 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2672 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2673 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2674
2675 /* Fill BSM memory with bootstrap instructions */
2676 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2677 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2678 reg_offset += sizeof(u32), image++)
2679 _iwl_write_prph(priv, reg_offset,
2680 le32_to_cpu(*image));
2681
2682 rc = iwl3945_verify_bsm(priv);
2683 if (rc) {
2684 iwl_release_nic_access(priv);
2685 return rc;
2686 }
2687
2688 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2689 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2690 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2691 IWL39_RTC_INST_LOWER_BOUND);
2692 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2693
2694 /* Load bootstrap code into instruction SRAM now,
2695 * to prepare to load "initialize" uCode */
2696 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2697 BSM_WR_CTRL_REG_BIT_START);
2698
2699 /* Wait for load of bootstrap uCode to finish */
2700 for (i = 0; i < 100; i++) {
2701 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2702 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2703 break;
2704 udelay(10);
2705 }
2706 if (i < 100)
2707 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2708 else {
2709 IWL_ERR(priv, "BSM write did not complete!\n");
2710 return -EIO;
2711 }
2712
2713 /* Enable future boot loads whenever power management unit triggers it
2714 * (e.g. when powering back up after power-save shutdown) */
2715 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2716 BSM_WR_CTRL_REG_BIT_START_EN);
2717
2718 iwl_release_nic_access(priv);
2719
2720 return 0;
2721}
2722
2723static struct iwl_lib_ops iwl3945_lib = {
2724 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2725 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2726 .txq_init = iwl3945_hw_tx_queue_init,
2727 .load_ucode = iwl3945_load_bsm,
2728 .apm_ops = {
2729 .init = iwl3945_apm_init,
2730 .reset = iwl3945_apm_reset,
2731 .stop = iwl3945_apm_stop,
2732 .config = iwl3945_nic_config,
2733 .set_pwr_src = iwl3945_set_pwr_src,
2734 },
2735 .eeprom_ops = {
2736 .regulatory_bands = {
2737 EEPROM_REGULATORY_BAND_1_CHANNELS,
2738 EEPROM_REGULATORY_BAND_2_CHANNELS,
2739 EEPROM_REGULATORY_BAND_3_CHANNELS,
2740 EEPROM_REGULATORY_BAND_4_CHANNELS,
2741 EEPROM_REGULATORY_BAND_5_CHANNELS,
2742 IWL3945_EEPROM_IMG_SIZE,
2743 IWL3945_EEPROM_IMG_SIZE,
2744 },
2745 .verify_signature = iwlcore_eeprom_verify_signature,
2746 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2747 .release_semaphore = iwl3945_eeprom_release_semaphore,
2748 .query_addr = iwlcore_eeprom_query_addr,
2749 },
2750 .send_tx_power = iwl3945_send_tx_power,
2751};
2752
2753static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2754 .get_hcmd_size = iwl3945_get_hcmd_size,
2755 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2756};
2757
2758static struct iwl_ops iwl3945_ops = {
2759 .lib = &iwl3945_lib,
2760 .utils = &iwl3945_hcmd_utils,
2761};
2762
2763static struct iwl_cfg iwl3945_bg_cfg = {
2522 .name = "3945BG", 2764 .name = "3945BG",
2523 .fw_name_pre = IWL3945_FW_PRE, 2765 .fw_name_pre = IWL3945_FW_PRE,
2524 .ucode_api_max = IWL3945_UCODE_API_MAX, 2766 .ucode_api_max = IWL3945_UCODE_API_MAX,
2525 .ucode_api_min = IWL3945_UCODE_API_MIN, 2767 .ucode_api_min = IWL3945_UCODE_API_MIN,
2526 .sku = IWL_SKU_G, 2768 .sku = IWL_SKU_G,
2769 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2770 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2771 .ops = &iwl3945_ops,
2772 .mod_params = &iwl3945_mod_params
2527}; 2773};
2528 2774
2529static struct iwl_3945_cfg iwl3945_abg_cfg = { 2775static struct iwl_cfg iwl3945_abg_cfg = {
2530 .name = "3945ABG", 2776 .name = "3945ABG",
2531 .fw_name_pre = IWL3945_FW_PRE, 2777 .fw_name_pre = IWL3945_FW_PRE,
2532 .ucode_api_max = IWL3945_UCODE_API_MAX, 2778 .ucode_api_max = IWL3945_UCODE_API_MAX,
2533 .ucode_api_min = IWL3945_UCODE_API_MIN, 2779 .ucode_api_min = IWL3945_UCODE_API_MIN,
2534 .sku = IWL_SKU_A|IWL_SKU_G, 2780 .sku = IWL_SKU_A|IWL_SKU_G,
2781 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2782 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2783 .ops = &iwl3945_ops,
2784 .mod_params = &iwl3945_mod_params
2535}; 2785};
2536 2786
2537struct pci_device_id iwl3945_hw_card_ids[] = { 2787struct pci_device_id iwl3945_hw_card_ids[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 08:46:52 -0500