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Diffstat (limited to 'drivers/net/wireless/iwlegacy/4965-mac.c')
-rw-r--r--drivers/net/wireless/iwlegacy/4965-mac.c1477
1 files changed, 1477 insertions, 0 deletions
diff --git a/drivers/net/wireless/iwlegacy/4965-mac.c b/drivers/net/wireless/iwlegacy/4965-mac.c
index 142d39f94498..b6f96b4b1f5c 100644
--- a/drivers/net/wireless/iwlegacy/4965-mac.c
+++ b/drivers/net/wireless/iwlegacy/4965-mac.c
@@ -86,6 +86,1483 @@ MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
86MODULE_LICENSE("GPL"); 86MODULE_LICENSE("GPL");
87MODULE_ALIAS("iwl4965"); 87MODULE_ALIAS("iwl4965");
88 88
89void il4965_rx_missed_beacon_notif(struct il_priv *il,
90 struct il_rx_buf *rxb)
91
92{
93 struct il_rx_pkt *pkt = rxb_addr(rxb);
94 struct il_missed_beacon_notif *missed_beacon;
95
96 missed_beacon = &pkt->u.missed_beacon;
97 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) >
98 il->missed_beacon_threshold) {
99 D_CALIB(
100 "missed bcn cnsq %d totl %d rcd %d expctd %d\n",
101 le32_to_cpu(missed_beacon->consecutive_missed_beacons),
102 le32_to_cpu(missed_beacon->total_missed_becons),
103 le32_to_cpu(missed_beacon->num_recvd_beacons),
104 le32_to_cpu(missed_beacon->num_expected_beacons));
105 if (!test_bit(STATUS_SCANNING, &il->status))
106 il4965_init_sensitivity(il);
107 }
108}
109
110/* Calculate noise level, based on measurements during network silence just
111 * before arriving beacon. This measurement can be done only if we know
112 * exactly when to expect beacons, therefore only when we're associated. */
113static void il4965_rx_calc_noise(struct il_priv *il)
114{
115 struct stats_rx_non_phy *rx_info;
116 int num_active_rx = 0;
117 int total_silence = 0;
118 int bcn_silence_a, bcn_silence_b, bcn_silence_c;
119 int last_rx_noise;
120
121 rx_info = &(il->_4965.stats.rx.general);
122 bcn_silence_a =
123 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
124 bcn_silence_b =
125 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
126 bcn_silence_c =
127 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
128
129 if (bcn_silence_a) {
130 total_silence += bcn_silence_a;
131 num_active_rx++;
132 }
133 if (bcn_silence_b) {
134 total_silence += bcn_silence_b;
135 num_active_rx++;
136 }
137 if (bcn_silence_c) {
138 total_silence += bcn_silence_c;
139 num_active_rx++;
140 }
141
142 /* Average among active antennas */
143 if (num_active_rx)
144 last_rx_noise = (total_silence / num_active_rx) - 107;
145 else
146 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE;
147
148 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
149 bcn_silence_a, bcn_silence_b, bcn_silence_c,
150 last_rx_noise);
151}
152
153#ifdef CONFIG_IWLEGACY_DEBUGFS
154/*
155 * based on the assumption of all stats counter are in DWORD
156 * FIXME: This function is for debugging, do not deal with
157 * the case of counters roll-over.
158 */
159static void il4965_accumulative_stats(struct il_priv *il,
160 __le32 *stats)
161{
162 int i, size;
163 __le32 *prev_stats;
164 u32 *accum_stats;
165 u32 *delta, *max_delta;
166 struct stats_general_common *general, *accum_general;
167 struct stats_tx *tx, *accum_tx;
168
169 prev_stats = (__le32 *)&il->_4965.stats;
170 accum_stats = (u32 *)&il->_4965.accum_stats;
171 size = sizeof(struct il_notif_stats);
172 general = &il->_4965.stats.general.common;
173 accum_general = &il->_4965.accum_stats.general.common;
174 tx = &il->_4965.stats.tx;
175 accum_tx = &il->_4965.accum_stats.tx;
176 delta = (u32 *)&il->_4965.delta_stats;
177 max_delta = (u32 *)&il->_4965.max_delta;
178
179 for (i = sizeof(__le32); i < size;
180 i += sizeof(__le32), stats++, prev_stats++, delta++,
181 max_delta++, accum_stats++) {
182 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
183 *delta = (le32_to_cpu(*stats) -
184 le32_to_cpu(*prev_stats));
185 *accum_stats += *delta;
186 if (*delta > *max_delta)
187 *max_delta = *delta;
188 }
189 }
190
191 /* reset accumulative stats for "no-counter" type stats */
192 accum_general->temperature = general->temperature;
193 accum_general->ttl_timestamp = general->ttl_timestamp;
194}
195#endif
196
197#define REG_RECALIB_PERIOD (60)
198
199void il4965_rx_stats(struct il_priv *il,
200 struct il_rx_buf *rxb)
201{
202 int change;
203 struct il_rx_pkt *pkt = rxb_addr(rxb);
204
205 D_RX(
206 "Statistics notification received (%d vs %d).\n",
207 (int)sizeof(struct il_notif_stats),
208 le32_to_cpu(pkt->len_n_flags) &
209 FH_RSCSR_FRAME_SIZE_MSK);
210
211 change = ((il->_4965.stats.general.common.temperature !=
212 pkt->u.stats.general.common.temperature) ||
213 ((il->_4965.stats.flag &
214 STATISTICS_REPLY_FLG_HT40_MODE_MSK) !=
215 (pkt->u.stats.flag &
216 STATISTICS_REPLY_FLG_HT40_MODE_MSK)));
217#ifdef CONFIG_IWLEGACY_DEBUGFS
218 il4965_accumulative_stats(il, (__le32 *)&pkt->u.stats);
219#endif
220
221 /* TODO: reading some of stats is unneeded */
222 memcpy(&il->_4965.stats, &pkt->u.stats,
223 sizeof(il->_4965.stats));
224
225 set_bit(STATUS_STATISTICS, &il->status);
226
227 /* Reschedule the stats timer to occur in
228 * REG_RECALIB_PERIOD seconds to ensure we get a
229 * thermal update even if the uCode doesn't give
230 * us one */
231 mod_timer(&il->stats_periodic, jiffies +
232 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
233
234 if (unlikely(!test_bit(STATUS_SCANNING, &il->status)) &&
235 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
236 il4965_rx_calc_noise(il);
237 queue_work(il->workqueue, &il->run_time_calib_work);
238 }
239 if (il->cfg->ops->lib->temp_ops.temperature && change)
240 il->cfg->ops->lib->temp_ops.temperature(il);
241}
242
243void il4965_reply_stats(struct il_priv *il,
244 struct il_rx_buf *rxb)
245{
246 struct il_rx_pkt *pkt = rxb_addr(rxb);
247
248 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATISTICS_CLEAR_MSK) {
249#ifdef CONFIG_IWLEGACY_DEBUGFS
250 memset(&il->_4965.accum_stats, 0,
251 sizeof(struct il_notif_stats));
252 memset(&il->_4965.delta_stats, 0,
253 sizeof(struct il_notif_stats));
254 memset(&il->_4965.max_delta, 0,
255 sizeof(struct il_notif_stats));
256#endif
257 D_RX("Statistics have been cleared\n");
258 }
259 il4965_rx_stats(il, rxb);
260}
261
262static const u8 tid_to_ac[] = {
263 IEEE80211_AC_BE,
264 IEEE80211_AC_BK,
265 IEEE80211_AC_BK,
266 IEEE80211_AC_BE,
267 IEEE80211_AC_VI,
268 IEEE80211_AC_VI,
269 IEEE80211_AC_VO,
270 IEEE80211_AC_VO
271};
272
273static inline int il4965_get_ac_from_tid(u16 tid)
274{
275 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
276 return tid_to_ac[tid];
277
278 /* no support for TIDs 8-15 yet */
279 return -EINVAL;
280}
281
282static inline int
283il4965_get_fifo_from_tid(struct il_rxon_context *ctx, u16 tid)
284{
285 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
286 return ctx->ac_to_fifo[tid_to_ac[tid]];
287
288 /* no support for TIDs 8-15 yet */
289 return -EINVAL;
290}
291
292/*
293 * handle build REPLY_TX command notification.
294 */
295static void il4965_tx_cmd_build_basic(struct il_priv *il,
296 struct sk_buff *skb,
297 struct il_tx_cmd *tx_cmd,
298 struct ieee80211_tx_info *info,
299 struct ieee80211_hdr *hdr,
300 u8 std_id)
301{
302 __le16 fc = hdr->frame_control;
303 __le32 tx_flags = tx_cmd->tx_flags;
304
305 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
306 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
307 tx_flags |= TX_CMD_FLG_ACK_MSK;
308 if (ieee80211_is_mgmt(fc))
309 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
310 if (ieee80211_is_probe_resp(fc) &&
311 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
312 tx_flags |= TX_CMD_FLG_TSF_MSK;
313 } else {
314 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
315 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
316 }
317
318 if (ieee80211_is_back_req(fc))
319 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
320
321 tx_cmd->sta_id = std_id;
322 if (ieee80211_has_morefrags(fc))
323 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
324
325 if (ieee80211_is_data_qos(fc)) {
326 u8 *qc = ieee80211_get_qos_ctl(hdr);
327 tx_cmd->tid_tspec = qc[0] & 0xf;
328 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
329 } else {
330 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
331 }
332
333 il_tx_cmd_protection(il, info, fc, &tx_flags);
334
335 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
336 if (ieee80211_is_mgmt(fc)) {
337 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
338 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
339 else
340 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
341 } else {
342 tx_cmd->timeout.pm_frame_timeout = 0;
343 }
344
345 tx_cmd->driver_txop = 0;
346 tx_cmd->tx_flags = tx_flags;
347 tx_cmd->next_frame_len = 0;
348}
349
350#define RTS_DFAULT_RETRY_LIMIT 60
351
352static void il4965_tx_cmd_build_rate(struct il_priv *il,
353 struct il_tx_cmd *tx_cmd,
354 struct ieee80211_tx_info *info,
355 __le16 fc)
356{
357 u32 rate_flags;
358 int rate_idx;
359 u8 rts_retry_limit;
360 u8 data_retry_limit;
361 u8 rate_plcp;
362
363 /* Set retry limit on DATA packets and Probe Responses*/
364 if (ieee80211_is_probe_resp(fc))
365 data_retry_limit = 3;
366 else
367 data_retry_limit = IL4965_DEFAULT_TX_RETRY;
368 tx_cmd->data_retry_limit = data_retry_limit;
369
370 /* Set retry limit on RTS packets */
371 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
372 if (data_retry_limit < rts_retry_limit)
373 rts_retry_limit = data_retry_limit;
374 tx_cmd->rts_retry_limit = rts_retry_limit;
375
376 /* DATA packets will use the uCode station table for rate/antenna
377 * selection */
378 if (ieee80211_is_data(fc)) {
379 tx_cmd->initial_rate_idx = 0;
380 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
381 return;
382 }
383
384 /**
385 * If the current TX rate stored in mac80211 has the MCS bit set, it's
386 * not really a TX rate. Thus, we use the lowest supported rate for
387 * this band. Also use the lowest supported rate if the stored rate
388 * idx is invalid.
389 */
390 rate_idx = info->control.rates[0].idx;
391 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) ||
392 rate_idx < 0 || rate_idx > RATE_COUNT_LEGACY)
393 rate_idx = rate_lowest_index(&il->bands[info->band],
394 info->control.sta);
395 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
396 if (info->band == IEEE80211_BAND_5GHZ)
397 rate_idx += IL_FIRST_OFDM_RATE;
398 /* Get PLCP rate for tx_cmd->rate_n_flags */
399 rate_plcp = il_rates[rate_idx].plcp;
400 /* Zero out flags for this packet */
401 rate_flags = 0;
402
403 /* Set CCK flag as needed */
404 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE)
405 rate_flags |= RATE_MCS_CCK_MSK;
406
407 /* Set up antennas */
408 il->mgmt_tx_ant = il4965_toggle_tx_ant(il, il->mgmt_tx_ant,
409 il->hw_params.valid_tx_ant);
410
411 rate_flags |= il4965_ant_idx_to_flags(il->mgmt_tx_ant);
412
413 /* Set the rate in the TX cmd */
414 tx_cmd->rate_n_flags = il4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
415}
416
417static void il4965_tx_cmd_build_hwcrypto(struct il_priv *il,
418 struct ieee80211_tx_info *info,
419 struct il_tx_cmd *tx_cmd,
420 struct sk_buff *skb_frag,
421 int sta_id)
422{
423 struct ieee80211_key_conf *keyconf = info->control.hw_key;
424
425 switch (keyconf->cipher) {
426 case WLAN_CIPHER_SUITE_CCMP:
427 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
428 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
429 if (info->flags & IEEE80211_TX_CTL_AMPDU)
430 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
431 D_TX("tx_cmd with AES hwcrypto\n");
432 break;
433
434 case WLAN_CIPHER_SUITE_TKIP:
435 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
436 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key);
437 D_TX("tx_cmd with tkip hwcrypto\n");
438 break;
439
440 case WLAN_CIPHER_SUITE_WEP104:
441 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
442 /* fall through */
443 case WLAN_CIPHER_SUITE_WEP40:
444 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
445 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
446
447 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
448
449 D_TX("Configuring packet for WEP encryption "
450 "with key %d\n", keyconf->keyidx);
451 break;
452
453 default:
454 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher);
455 break;
456 }
457}
458
459/*
460 * start REPLY_TX command process
461 */
462int il4965_tx_skb(struct il_priv *il, struct sk_buff *skb)
463{
464 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
465 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
466 struct ieee80211_sta *sta = info->control.sta;
467 struct il_station_priv *sta_priv = NULL;
468 struct il_tx_queue *txq;
469 struct il_queue *q;
470 struct il_device_cmd *out_cmd;
471 struct il_cmd_meta *out_meta;
472 struct il_tx_cmd *tx_cmd;
473 struct il_rxon_context *ctx = &il->ctx;
474 int txq_id;
475 dma_addr_t phys_addr;
476 dma_addr_t txcmd_phys;
477 dma_addr_t scratch_phys;
478 u16 len, firstlen, secondlen;
479 u16 seq_number = 0;
480 __le16 fc;
481 u8 hdr_len;
482 u8 sta_id;
483 u8 wait_write_ptr = 0;
484 u8 tid = 0;
485 u8 *qc = NULL;
486 unsigned long flags;
487 bool is_agg = false;
488
489 if (info->control.vif)
490 ctx = il_rxon_ctx_from_vif(info->control.vif);
491
492 spin_lock_irqsave(&il->lock, flags);
493 if (il_is_rfkill(il)) {
494 D_DROP("Dropping - RF KILL\n");
495 goto drop_unlock;
496 }
497
498 fc = hdr->frame_control;
499
500#ifdef CONFIG_IWLEGACY_DEBUG
501 if (ieee80211_is_auth(fc))
502 D_TX("Sending AUTH frame\n");
503 else if (ieee80211_is_assoc_req(fc))
504 D_TX("Sending ASSOC frame\n");
505 else if (ieee80211_is_reassoc_req(fc))
506 D_TX("Sending REASSOC frame\n");
507#endif
508
509 hdr_len = ieee80211_hdrlen(fc);
510
511 /* For management frames use broadcast id to do not break aggregation */
512 if (!ieee80211_is_data(fc))
513 sta_id = ctx->bcast_sta_id;
514 else {
515 /* Find idx into station table for destination station */
516 sta_id = il_sta_id_or_broadcast(il, ctx, info->control.sta);
517
518 if (sta_id == IL_INVALID_STATION) {
519 D_DROP("Dropping - INVALID STATION: %pM\n",
520 hdr->addr1);
521 goto drop_unlock;
522 }
523 }
524
525 D_TX("station Id %d\n", sta_id);
526
527 if (sta)
528 sta_priv = (void *)sta->drv_priv;
529
530 if (sta_priv && sta_priv->asleep &&
531 (info->flags & IEEE80211_TX_CTL_POLL_RESPONSE)) {
532 /*
533 * This sends an asynchronous command to the device,
534 * but we can rely on it being processed before the
535 * next frame is processed -- and the next frame to
536 * this station is the one that will consume this
537 * counter.
538 * For now set the counter to just 1 since we do not
539 * support uAPSD yet.
540 */
541 il4965_sta_modify_sleep_tx_count(il, sta_id, 1);
542 }
543
544 /*
545 * Send this frame after DTIM -- there's a special queue
546 * reserved for this for contexts that support AP mode.
547 */
548 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
549 txq_id = ctx->mcast_queue;
550 /*
551 * The microcode will clear the more data
552 * bit in the last frame it transmits.
553 */
554 hdr->frame_control |=
555 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
556 } else
557 txq_id = ctx->ac_to_queue[skb_get_queue_mapping(skb)];
558
559 /* irqs already disabled/saved above when locking il->lock */
560 spin_lock(&il->sta_lock);
561
562 if (ieee80211_is_data_qos(fc)) {
563 qc = ieee80211_get_qos_ctl(hdr);
564 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
565 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) {
566 spin_unlock(&il->sta_lock);
567 goto drop_unlock;
568 }
569 seq_number = il->stations[sta_id].tid[tid].seq_number;
570 seq_number &= IEEE80211_SCTL_SEQ;
571 hdr->seq_ctrl = hdr->seq_ctrl &
572 cpu_to_le16(IEEE80211_SCTL_FRAG);
573 hdr->seq_ctrl |= cpu_to_le16(seq_number);
574 seq_number += 0x10;
575 /* aggregation is on for this <sta,tid> */
576 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
577 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) {
578 txq_id = il->stations[sta_id].tid[tid].agg.txq_id;
579 is_agg = true;
580 }
581 }
582
583 txq = &il->txq[txq_id];
584 q = &txq->q;
585
586 if (unlikely(il_queue_space(q) < q->high_mark)) {
587 spin_unlock(&il->sta_lock);
588 goto drop_unlock;
589 }
590
591 if (ieee80211_is_data_qos(fc)) {
592 il->stations[sta_id].tid[tid].tfds_in_queue++;
593 if (!ieee80211_has_morefrags(fc))
594 il->stations[sta_id].tid[tid].seq_number = seq_number;
595 }
596
597 spin_unlock(&il->sta_lock);
598
599 /* Set up driver data for this TFD */
600 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct il_tx_info));
601 txq->txb[q->write_ptr].skb = skb;
602 txq->txb[q->write_ptr].ctx = ctx;
603
604 /* Set up first empty entry in queue's array of Tx/cmd buffers */
605 out_cmd = txq->cmd[q->write_ptr];
606 out_meta = &txq->meta[q->write_ptr];
607 tx_cmd = &out_cmd->cmd.tx;
608 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
609 memset(tx_cmd, 0, sizeof(struct il_tx_cmd));
610
611 /*
612 * Set up the Tx-command (not MAC!) header.
613 * Store the chosen Tx queue and TFD idx within the sequence field;
614 * after Tx, uCode's Tx response will return this value so driver can
615 * locate the frame within the tx queue and do post-tx processing.
616 */
617 out_cmd->hdr.cmd = REPLY_TX;
618 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
619 IDX_TO_SEQ(q->write_ptr)));
620
621 /* Copy MAC header from skb into command buffer */
622 memcpy(tx_cmd->hdr, hdr, hdr_len);
623
624
625 /* Total # bytes to be transmitted */
626 len = (u16)skb->len;
627 tx_cmd->len = cpu_to_le16(len);
628
629 if (info->control.hw_key)
630 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id);
631
632 /* TODO need this for burst mode later on */
633 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id);
634 il_dbg_log_tx_data_frame(il, len, hdr);
635
636 il4965_tx_cmd_build_rate(il, tx_cmd, info, fc);
637
638 il_update_stats(il, true, fc, len);
639 /*
640 * Use the first empty entry in this queue's command buffer array
641 * to contain the Tx command and MAC header concatenated together
642 * (payload data will be in another buffer).
643 * Size of this varies, due to varying MAC header length.
644 * If end is not dword aligned, we'll have 2 extra bytes at the end
645 * of the MAC header (device reads on dword boundaries).
646 * We'll tell device about this padding later.
647 */
648 len = sizeof(struct il_tx_cmd) +
649 sizeof(struct il_cmd_header) + hdr_len;
650 firstlen = (len + 3) & ~3;
651
652 /* Tell NIC about any 2-byte padding after MAC header */
653 if (firstlen != len)
654 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
655
656 /* Physical address of this Tx command's header (not MAC header!),
657 * within command buffer array. */
658 txcmd_phys = pci_map_single(il->pci_dev,
659 &out_cmd->hdr, firstlen,
660 PCI_DMA_BIDIRECTIONAL);
661 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
662 dma_unmap_len_set(out_meta, len, firstlen);
663 /* Add buffer containing Tx command and MAC(!) header to TFD's
664 * first entry */
665 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
666 txcmd_phys, firstlen, 1, 0);
667
668 if (!ieee80211_has_morefrags(hdr->frame_control)) {
669 txq->need_update = 1;
670 } else {
671 wait_write_ptr = 1;
672 txq->need_update = 0;
673 }
674
675 /* Set up TFD's 2nd entry to point directly to remainder of skb,
676 * if any (802.11 null frames have no payload). */
677 secondlen = skb->len - hdr_len;
678 if (secondlen > 0) {
679 phys_addr = pci_map_single(il->pci_dev, skb->data + hdr_len,
680 secondlen, PCI_DMA_TODEVICE);
681 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq,
682 phys_addr, secondlen,
683 0, 0);
684 }
685
686 scratch_phys = txcmd_phys + sizeof(struct il_cmd_header) +
687 offsetof(struct il_tx_cmd, scratch);
688
689 /* take back ownership of DMA buffer to enable update */
690 pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys,
691 firstlen, PCI_DMA_BIDIRECTIONAL);
692 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
693 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys);
694
695 D_TX("sequence nr = 0X%x\n",
696 le16_to_cpu(out_cmd->hdr.sequence));
697 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
698 il_print_hex_dump(il, IL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
699 il_print_hex_dump(il, IL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
700
701 /* Set up entry for this TFD in Tx byte-count array */
702 if (info->flags & IEEE80211_TX_CTL_AMPDU)
703 il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq,
704 le16_to_cpu(tx_cmd->len));
705
706 pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys,
707 firstlen, PCI_DMA_BIDIRECTIONAL);
708
709 /* Tell device the write idx *just past* this latest filled TFD */
710 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
711 il_txq_update_write_ptr(il, txq);
712 spin_unlock_irqrestore(&il->lock, flags);
713
714 /*
715 * At this point the frame is "transmitted" successfully
716 * and we will get a TX status notification eventually,
717 * regardless of the value of ret. "ret" only indicates
718 * whether or not we should update the write pointer.
719 */
720
721 /*
722 * Avoid atomic ops if it isn't an associated client.
723 * Also, if this is a packet for aggregation, don't
724 * increase the counter because the ucode will stop
725 * aggregation queues when their respective station
726 * goes to sleep.
727 */
728 if (sta_priv && sta_priv->client && !is_agg)
729 atomic_inc(&sta_priv->pending_frames);
730
731 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) {
732 if (wait_write_ptr) {
733 spin_lock_irqsave(&il->lock, flags);
734 txq->need_update = 1;
735 il_txq_update_write_ptr(il, txq);
736 spin_unlock_irqrestore(&il->lock, flags);
737 } else {
738 il_stop_queue(il, txq);
739 }
740 }
741
742 return 0;
743
744drop_unlock:
745 spin_unlock_irqrestore(&il->lock, flags);
746 return -1;
747}
748
749static inline int il4965_alloc_dma_ptr(struct il_priv *il,
750 struct il_dma_ptr *ptr, size_t size)
751{
752 ptr->addr = dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma,
753 GFP_KERNEL);
754 if (!ptr->addr)
755 return -ENOMEM;
756 ptr->size = size;
757 return 0;
758}
759
760static inline void il4965_free_dma_ptr(struct il_priv *il,
761 struct il_dma_ptr *ptr)
762{
763 if (unlikely(!ptr->addr))
764 return;
765
766 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
767 memset(ptr, 0, sizeof(*ptr));
768}
769
770/**
771 * il4965_hw_txq_ctx_free - Free TXQ Context
772 *
773 * Destroy all TX DMA queues and structures
774 */
775void il4965_hw_txq_ctx_free(struct il_priv *il)
776{
777 int txq_id;
778
779 /* Tx queues */
780 if (il->txq) {
781 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
782 if (txq_id == il->cmd_queue)
783 il_cmd_queue_free(il);
784 else
785 il_tx_queue_free(il, txq_id);
786 }
787 il4965_free_dma_ptr(il, &il->kw);
788
789 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
790
791 /* free tx queue structure */
792 il_txq_mem(il);
793}
794
795/**
796 * il4965_txq_ctx_alloc - allocate TX queue context
797 * Allocate all Tx DMA structures and initialize them
798 *
799 * @param il
800 * @return error code
801 */
802int il4965_txq_ctx_alloc(struct il_priv *il)
803{
804 int ret;
805 int txq_id, slots_num;
806 unsigned long flags;
807
808 /* Free all tx/cmd queues and keep-warm buffer */
809 il4965_hw_txq_ctx_free(il);
810
811 ret = il4965_alloc_dma_ptr(il, &il->scd_bc_tbls,
812 il->hw_params.scd_bc_tbls_size);
813 if (ret) {
814 IL_ERR("Scheduler BC Table allocation failed\n");
815 goto error_bc_tbls;
816 }
817 /* Alloc keep-warm buffer */
818 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE);
819 if (ret) {
820 IL_ERR("Keep Warm allocation failed\n");
821 goto error_kw;
822 }
823
824 /* allocate tx queue structure */
825 ret = il_alloc_txq_mem(il);
826 if (ret)
827 goto error;
828
829 spin_lock_irqsave(&il->lock, flags);
830
831 /* Turn off all Tx DMA fifos */
832 il4965_txq_set_sched(il, 0);
833
834 /* Tell NIC where to find the "keep warm" buffer */
835 il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);
836
837 spin_unlock_irqrestore(&il->lock, flags);
838
839 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
840 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
841 slots_num = (txq_id == il->cmd_queue) ?
842 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
843 ret = il_tx_queue_init(il,
844 &il->txq[txq_id], slots_num,
845 txq_id);
846 if (ret) {
847 IL_ERR("Tx %d queue init failed\n", txq_id);
848 goto error;
849 }
850 }
851
852 return ret;
853
854 error:
855 il4965_hw_txq_ctx_free(il);
856 il4965_free_dma_ptr(il, &il->kw);
857 error_kw:
858 il4965_free_dma_ptr(il, &il->scd_bc_tbls);
859 error_bc_tbls:
860 return ret;
861}
862
863void il4965_txq_ctx_reset(struct il_priv *il)
864{
865 int txq_id, slots_num;
866 unsigned long flags;
867
868 spin_lock_irqsave(&il->lock, flags);
869
870 /* Turn off all Tx DMA fifos */
871 il4965_txq_set_sched(il, 0);
872
873 /* Tell NIC where to find the "keep warm" buffer */
874 il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4);
875
876 spin_unlock_irqrestore(&il->lock, flags);
877
878 /* Alloc and init all Tx queues, including the command queue (#4) */
879 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) {
880 slots_num = txq_id == il->cmd_queue ?
881 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
882 il_tx_queue_reset(il, &il->txq[txq_id],
883 slots_num, txq_id);
884 }
885}
886
887/**
888 * il4965_txq_ctx_stop - Stop all Tx DMA channels
889 */
890void il4965_txq_ctx_stop(struct il_priv *il)
891{
892 int ch, txq_id;
893 unsigned long flags;
894
895 /* Turn off all Tx DMA fifos */
896 spin_lock_irqsave(&il->lock, flags);
897
898 il4965_txq_set_sched(il, 0);
899
900 /* Stop each Tx DMA channel, and wait for it to be idle */
901 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) {
902 il_wr(il,
903 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
904 if (il_poll_bit(il, FH_TSSR_TX_STATUS_REG,
905 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
906 1000))
907 IL_ERR("Failing on timeout while stopping"
908 " DMA channel %d [0x%08x]", ch,
909 il_rd(il,
910 FH_TSSR_TX_STATUS_REG));
911 }
912 spin_unlock_irqrestore(&il->lock, flags);
913
914 if (!il->txq)
915 return;
916
917 /* Unmap DMA from host system and free skb's */
918 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
919 if (txq_id == il->cmd_queue)
920 il_cmd_queue_unmap(il);
921 else
922 il_tx_queue_unmap(il, txq_id);
923}
924
925/*
926 * Find first available (lowest unused) Tx Queue, mark it "active".
927 * Called only when finding queue for aggregation.
928 * Should never return anything < 7, because they should already
929 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
930 */
931static int il4965_txq_ctx_activate_free(struct il_priv *il)
932{
933 int txq_id;
934
935 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++)
936 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk))
937 return txq_id;
938 return -1;
939}
940
941/**
942 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
943 */
944static void il4965_tx_queue_stop_scheduler(struct il_priv *il,
945 u16 txq_id)
946{
947 /* Simply stop the queue, but don't change any configuration;
948 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
949 il_wr_prph(il,
950 IL49_SCD_QUEUE_STATUS_BITS(txq_id),
951 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
952 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
953}
954
955/**
956 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
957 */
958static int il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid,
959 u16 txq_id)
960{
961 u32 tbl_dw_addr;
962 u32 tbl_dw;
963 u16 scd_q2ratid;
964
965 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
966
967 tbl_dw_addr = il->scd_base_addr +
968 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
969
970 tbl_dw = il_read_targ_mem(il, tbl_dw_addr);
971
972 if (txq_id & 0x1)
973 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
974 else
975 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
976
977 il_write_targ_mem(il, tbl_dw_addr, tbl_dw);
978
979 return 0;
980}
981
982/**
983 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
984 *
985 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE,
986 * i.e. it must be one of the higher queues used for aggregation
987 */
988static int il4965_txq_agg_enable(struct il_priv *il, int txq_id,
989 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
990{
991 unsigned long flags;
992 u16 ra_tid;
993 int ret;
994
995 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
996 (IL49_FIRST_AMPDU_QUEUE +
997 il->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
998 IL_WARN(
999 "queue number out of range: %d, must be %d to %d\n",
1000 txq_id, IL49_FIRST_AMPDU_QUEUE,
1001 IL49_FIRST_AMPDU_QUEUE +
1002 il->cfg->base_params->num_of_ampdu_queues - 1);
1003 return -EINVAL;
1004 }
1005
1006 ra_tid = BUILD_RAxTID(sta_id, tid);
1007
1008 /* Modify device's station table to Tx this TID */
1009 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid);
1010 if (ret)
1011 return ret;
1012
1013 spin_lock_irqsave(&il->lock, flags);
1014
1015 /* Stop this Tx queue before configuring it */
1016 il4965_tx_queue_stop_scheduler(il, txq_id);
1017
1018 /* Map receiver-address / traffic-ID to this queue */
1019 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id);
1020
1021 /* Set this queue as a chain-building queue */
1022 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1023
1024 /* Place first TFD at idx corresponding to start sequence number.
1025 * Assumes that ssn_idx is valid (!= 0xFFF) */
1026 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1027 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1028 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
1029
1030 /* Set up Tx win size and frame limit for this queue */
1031 il_write_targ_mem(il,
1032 il->scd_base_addr + IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1033 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1034 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1035
1036 il_write_targ_mem(il, il->scd_base_addr +
1037 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1038 (SCD_FRAME_LIMIT << IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1039 & IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1040
1041 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1042
1043 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1044 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1);
1045
1046 spin_unlock_irqrestore(&il->lock, flags);
1047
1048 return 0;
1049}
1050
1051
1052int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
1053 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
1054{
1055 int sta_id;
1056 int tx_fifo;
1057 int txq_id;
1058 int ret;
1059 unsigned long flags;
1060 struct il_tid_data *tid_data;
1061
1062 tx_fifo = il4965_get_fifo_from_tid(il_rxon_ctx_from_vif(vif), tid);
1063 if (unlikely(tx_fifo < 0))
1064 return tx_fifo;
1065
1066 IL_WARN("%s on ra = %pM tid = %d\n",
1067 __func__, sta->addr, tid);
1068
1069 sta_id = il_sta_id(sta);
1070 if (sta_id == IL_INVALID_STATION) {
1071 IL_ERR("Start AGG on invalid station\n");
1072 return -ENXIO;
1073 }
1074 if (unlikely(tid >= MAX_TID_COUNT))
1075 return -EINVAL;
1076
1077 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) {
1078 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n");
1079 return -ENXIO;
1080 }
1081
1082 txq_id = il4965_txq_ctx_activate_free(il);
1083 if (txq_id == -1) {
1084 IL_ERR("No free aggregation queue available\n");
1085 return -ENXIO;
1086 }
1087
1088 spin_lock_irqsave(&il->sta_lock, flags);
1089 tid_data = &il->stations[sta_id].tid[tid];
1090 *ssn = SEQ_TO_SN(tid_data->seq_number);
1091 tid_data->agg.txq_id = txq_id;
1092 il_set_swq_id(&il->txq[txq_id],
1093 il4965_get_ac_from_tid(tid), txq_id);
1094 spin_unlock_irqrestore(&il->sta_lock, flags);
1095
1096 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo,
1097 sta_id, tid, *ssn);
1098 if (ret)
1099 return ret;
1100
1101 spin_lock_irqsave(&il->sta_lock, flags);
1102 tid_data = &il->stations[sta_id].tid[tid];
1103 if (tid_data->tfds_in_queue == 0) {
1104 D_HT("HW queue is empty\n");
1105 tid_data->agg.state = IL_AGG_ON;
1106 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1107 } else {
1108 D_HT(
1109 "HW queue is NOT empty: %d packets in HW queue\n",
1110 tid_data->tfds_in_queue);
1111 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA;
1112 }
1113 spin_unlock_irqrestore(&il->sta_lock, flags);
1114 return ret;
1115}
1116
1117/**
1118 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE
1119 * il->lock must be held by the caller
1120 */
1121static int il4965_txq_agg_disable(struct il_priv *il, u16 txq_id,
1122 u16 ssn_idx, u8 tx_fifo)
1123{
1124 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) ||
1125 (IL49_FIRST_AMPDU_QUEUE +
1126 il->cfg->base_params->num_of_ampdu_queues <= txq_id)) {
1127 IL_WARN(
1128 "queue number out of range: %d, must be %d to %d\n",
1129 txq_id, IL49_FIRST_AMPDU_QUEUE,
1130 IL49_FIRST_AMPDU_QUEUE +
1131 il->cfg->base_params->num_of_ampdu_queues - 1);
1132 return -EINVAL;
1133 }
1134
1135 il4965_tx_queue_stop_scheduler(il, txq_id);
1136
1137 il_clear_bits_prph(il,
1138 IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1139
1140 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1141 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1142 /* supposes that ssn_idx is valid (!= 0xFFF) */
1143 il4965_set_wr_ptrs(il, txq_id, ssn_idx);
1144
1145 il_clear_bits_prph(il,
1146 IL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1147 il_txq_ctx_deactivate(il, txq_id);
1148 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0);
1149
1150 return 0;
1151}
1152
1153int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
1154 struct ieee80211_sta *sta, u16 tid)
1155{
1156 int tx_fifo_id, txq_id, sta_id, ssn;
1157 struct il_tid_data *tid_data;
1158 int write_ptr, read_ptr;
1159 unsigned long flags;
1160
1161 tx_fifo_id = il4965_get_fifo_from_tid(il_rxon_ctx_from_vif(vif), tid);
1162 if (unlikely(tx_fifo_id < 0))
1163 return tx_fifo_id;
1164
1165 sta_id = il_sta_id(sta);
1166
1167 if (sta_id == IL_INVALID_STATION) {
1168 IL_ERR("Invalid station for AGG tid %d\n", tid);
1169 return -ENXIO;
1170 }
1171
1172 spin_lock_irqsave(&il->sta_lock, flags);
1173
1174 tid_data = &il->stations[sta_id].tid[tid];
1175 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1176 txq_id = tid_data->agg.txq_id;
1177
1178 switch (il->stations[sta_id].tid[tid].agg.state) {
1179 case IL_EMPTYING_HW_QUEUE_ADDBA:
1180 /*
1181 * This can happen if the peer stops aggregation
1182 * again before we've had a chance to drain the
1183 * queue we selected previously, i.e. before the
1184 * session was really started completely.
1185 */
1186 D_HT("AGG stop before setup done\n");
1187 goto turn_off;
1188 case IL_AGG_ON:
1189 break;
1190 default:
1191 IL_WARN("Stopping AGG while state not ON or starting\n");
1192 }
1193
1194 write_ptr = il->txq[txq_id].q.write_ptr;
1195 read_ptr = il->txq[txq_id].q.read_ptr;
1196
1197 /* The queue is not empty */
1198 if (write_ptr != read_ptr) {
1199 D_HT("Stopping a non empty AGG HW QUEUE\n");
1200 il->stations[sta_id].tid[tid].agg.state =
1201 IL_EMPTYING_HW_QUEUE_DELBA;
1202 spin_unlock_irqrestore(&il->sta_lock, flags);
1203 return 0;
1204 }
1205
1206 D_HT("HW queue is empty\n");
1207 turn_off:
1208 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF;
1209
1210 /* do not restore/save irqs */
1211 spin_unlock(&il->sta_lock);
1212 spin_lock(&il->lock);
1213
1214 /*
1215 * the only reason this call can fail is queue number out of range,
1216 * which can happen if uCode is reloaded and all the station
1217 * information are lost. if it is outside the range, there is no need
1218 * to deactivate the uCode queue, just return "success" to allow
1219 * mac80211 to clean up it own data.
1220 */
1221 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id);
1222 spin_unlock_irqrestore(&il->lock, flags);
1223
1224 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1225
1226 return 0;
1227}
1228
1229int il4965_txq_check_empty(struct il_priv *il,
1230 int sta_id, u8 tid, int txq_id)
1231{
1232 struct il_queue *q = &il->txq[txq_id].q;
1233 u8 *addr = il->stations[sta_id].sta.sta.addr;
1234 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid];
1235 struct il_rxon_context *ctx;
1236
1237 ctx = &il->ctx;
1238
1239 lockdep_assert_held(&il->sta_lock);
1240
1241 switch (il->stations[sta_id].tid[tid].agg.state) {
1242 case IL_EMPTYING_HW_QUEUE_DELBA:
1243 /* We are reclaiming the last packet of the */
1244 /* aggregated HW queue */
1245 if (txq_id == tid_data->agg.txq_id &&
1246 q->read_ptr == q->write_ptr) {
1247 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1248 int tx_fifo = il4965_get_fifo_from_tid(ctx, tid);
1249 D_HT(
1250 "HW queue empty: continue DELBA flow\n");
1251 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo);
1252 tid_data->agg.state = IL_AGG_OFF;
1253 ieee80211_stop_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1254 }
1255 break;
1256 case IL_EMPTYING_HW_QUEUE_ADDBA:
1257 /* We are reclaiming the last packet of the queue */
1258 if (tid_data->tfds_in_queue == 0) {
1259 D_HT(
1260 "HW queue empty: continue ADDBA flow\n");
1261 tid_data->agg.state = IL_AGG_ON;
1262 ieee80211_start_tx_ba_cb_irqsafe(ctx->vif, addr, tid);
1263 }
1264 break;
1265 }
1266
1267 return 0;
1268}
1269
1270static void il4965_non_agg_tx_status(struct il_priv *il,
1271 struct il_rxon_context *ctx,
1272 const u8 *addr1)
1273{
1274 struct ieee80211_sta *sta;
1275 struct il_station_priv *sta_priv;
1276
1277 rcu_read_lock();
1278 sta = ieee80211_find_sta(ctx->vif, addr1);
1279 if (sta) {
1280 sta_priv = (void *)sta->drv_priv;
1281 /* avoid atomic ops if this isn't a client */
1282 if (sta_priv->client &&
1283 atomic_dec_return(&sta_priv->pending_frames) == 0)
1284 ieee80211_sta_block_awake(il->hw, sta, false);
1285 }
1286 rcu_read_unlock();
1287}
1288
1289static void
1290il4965_tx_status(struct il_priv *il, struct il_tx_info *tx_info,
1291 bool is_agg)
1292{
1293 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
1294
1295 if (!is_agg)
1296 il4965_non_agg_tx_status(il, tx_info->ctx, hdr->addr1);
1297
1298 ieee80211_tx_status_irqsafe(il->hw, tx_info->skb);
1299}
1300
1301int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx)
1302{
1303 struct il_tx_queue *txq = &il->txq[txq_id];
1304 struct il_queue *q = &txq->q;
1305 struct il_tx_info *tx_info;
1306 int nfreed = 0;
1307 struct ieee80211_hdr *hdr;
1308
1309 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
1310 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
1311 "is out of range [0-%d] %d %d.\n", txq_id,
1312 idx, q->n_bd, q->write_ptr, q->read_ptr);
1313 return 0;
1314 }
1315
1316 for (idx = il_queue_inc_wrap(idx, q->n_bd);
1317 q->read_ptr != idx;
1318 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1319
1320 tx_info = &txq->txb[txq->q.read_ptr];
1321
1322 if (WARN_ON_ONCE(tx_info->skb == NULL))
1323 continue;
1324
1325 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1326 if (ieee80211_is_data_qos(hdr->frame_control))
1327 nfreed++;
1328
1329 il4965_tx_status(il, tx_info,
1330 txq_id >= IL4965_FIRST_AMPDU_QUEUE);
1331 tx_info->skb = NULL;
1332
1333 il->cfg->ops->lib->txq_free_tfd(il, txq);
1334 }
1335 return nfreed;
1336}
1337
1338/**
1339 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack
1340 *
1341 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1342 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1343 */
1344static int il4965_tx_status_reply_compressed_ba(struct il_priv *il,
1345 struct il_ht_agg *agg,
1346 struct il_compressed_ba_resp *ba_resp)
1347
1348{
1349 int i, sh, ack;
1350 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1351 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1352 int successes = 0;
1353 struct ieee80211_tx_info *info;
1354 u64 bitmap, sent_bitmap;
1355
1356 if (unlikely(!agg->wait_for_ba)) {
1357 if (unlikely(ba_resp->bitmap))
1358 IL_ERR("Received BA when not expected\n");
1359 return -EINVAL;
1360 }
1361
1362 /* Mark that the expected block-ack response arrived */
1363 agg->wait_for_ba = 0;
1364 D_TX_REPLY("BA %d %d\n", agg->start_idx,
1365 ba_resp->seq_ctl);
1366
1367 /* Calculate shift to align block-ack bits with our Tx win bits */
1368 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4);
1369 if (sh < 0) /* tbw something is wrong with indices */
1370 sh += 0x100;
1371
1372 if (agg->frame_count > (64 - sh)) {
1373 D_TX_REPLY("more frames than bitmap size");
1374 return -1;
1375 }
1376
1377 /* don't use 64-bit values for now */
1378 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1379
1380 /* check for success or failure according to the
1381 * transmitted bitmap and block-ack bitmap */
1382 sent_bitmap = bitmap & agg->bitmap;
1383
1384 /* For each frame attempted in aggregation,
1385 * update driver's record of tx frame's status. */
1386 i = 0;
1387 while (sent_bitmap) {
1388 ack = sent_bitmap & 1ULL;
1389 successes += ack;
1390 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1391 ack ? "ACK" : "NACK", i,
1392 (agg->start_idx + i) & 0xff,
1393 agg->start_idx + i);
1394 sent_bitmap >>= 1;
1395 ++i;
1396 }
1397
1398 D_TX_REPLY("Bitmap %llx\n",
1399 (unsigned long long)bitmap);
1400
1401 info = IEEE80211_SKB_CB(il->txq[scd_flow].txb[agg->start_idx].skb);
1402 memset(&info->status, 0, sizeof(info->status));
1403 info->flags |= IEEE80211_TX_STAT_ACK;
1404 info->flags |= IEEE80211_TX_STAT_AMPDU;
1405 info->status.ampdu_ack_len = successes;
1406 info->status.ampdu_len = agg->frame_count;
1407 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info);
1408
1409 return 0;
1410}
1411
1412/**
1413 * translate ucode response to mac80211 tx status control values
1414 */
1415void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
1416 struct ieee80211_tx_info *info)
1417{
1418 struct ieee80211_tx_rate *r = &info->control.rates[0];
1419
1420 info->antenna_sel_tx =
1421 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
1422 if (rate_n_flags & RATE_MCS_HT_MSK)
1423 r->flags |= IEEE80211_TX_RC_MCS;
1424 if (rate_n_flags & RATE_MCS_GF_MSK)
1425 r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
1426 if (rate_n_flags & RATE_MCS_HT40_MSK)
1427 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
1428 if (rate_n_flags & RATE_MCS_DUP_MSK)
1429 r->flags |= IEEE80211_TX_RC_DUP_DATA;
1430 if (rate_n_flags & RATE_MCS_SGI_MSK)
1431 r->flags |= IEEE80211_TX_RC_SHORT_GI;
1432 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band);
1433}
1434
1435/**
1436 * il4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1437 *
1438 * Handles block-acknowledge notification from device, which reports success
1439 * of frames sent via aggregation.
1440 */
1441void il4965_rx_reply_compressed_ba(struct il_priv *il,
1442 struct il_rx_buf *rxb)
1443{
1444 struct il_rx_pkt *pkt = rxb_addr(rxb);
1445 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1446 struct il_tx_queue *txq = NULL;
1447 struct il_ht_agg *agg;
1448 int idx;
1449 int sta_id;
1450 int tid;
1451 unsigned long flags;
1452
1453 /* "flow" corresponds to Tx queue */
1454 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1455
1456 /* "ssn" is start of block-ack Tx win, corresponds to idx
1457 * (in Tx queue's circular buffer) of first TFD/frame in win */
1458 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1459
1460 if (scd_flow >= il->hw_params.max_txq_num) {
1461 IL_ERR(
1462 "BUG_ON scd_flow is bigger than number of queues\n");
1463 return;
1464 }
1465
1466 txq = &il->txq[scd_flow];
1467 sta_id = ba_resp->sta_id;
1468 tid = ba_resp->tid;
1469 agg = &il->stations[sta_id].tid[tid].agg;
1470 if (unlikely(agg->txq_id != scd_flow)) {
1471 /*
1472 * FIXME: this is a uCode bug which need to be addressed,
1473 * log the information and return for now!
1474 * since it is possible happen very often and in order
1475 * not to fill the syslog, don't enable the logging by default
1476 */
1477 D_TX_REPLY(
1478 "BA scd_flow %d does not match txq_id %d\n",
1479 scd_flow, agg->txq_id);
1480 return;
1481 }
1482
1483 /* Find idx just before block-ack win */
1484 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1485
1486 spin_lock_irqsave(&il->sta_lock, flags);
1487
1488 D_TX_REPLY("REPLY_COMPRESSED_BA [%d] Received from %pM, "
1489 "sta_id = %d\n",
1490 agg->wait_for_ba,
1491 (u8 *) &ba_resp->sta_addr_lo32,
1492 ba_resp->sta_id);
1493 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx,"
1494 "scd_flow = "
1495 "%d, scd_ssn = %d\n",
1496 ba_resp->tid,
1497 ba_resp->seq_ctl,
1498 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1499 ba_resp->scd_flow,
1500 ba_resp->scd_ssn);
1501 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n",
1502 agg->start_idx,
1503 (unsigned long long)agg->bitmap);
1504
1505 /* Update driver's record of ACK vs. not for each frame in win */
1506 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp);
1507
1508 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1509 * block-ack win (we assume that they've been successfully
1510 * transmitted ... if not, it's too late anyway). */
1511 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1512 /* calculate mac80211 ampdu sw queue to wake */
1513 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx);
1514 il4965_free_tfds_in_queue(il, sta_id, tid, freed);
1515
1516 if (il_queue_space(&txq->q) > txq->q.low_mark &&
1517 il->mac80211_registered &&
1518 agg->state != IL_EMPTYING_HW_QUEUE_DELBA)
1519 il_wake_queue(il, txq);
1520
1521 il4965_txq_check_empty(il, sta_id, tid, scd_flow);
1522 }
1523
1524 spin_unlock_irqrestore(&il->sta_lock, flags);
1525}
1526
1527#ifdef CONFIG_IWLEGACY_DEBUG
1528const char *il4965_get_tx_fail_reason(u32 status)
1529{
1530#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x
1531#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x
1532
1533 switch (status & TX_STATUS_MSK) {
1534 case TX_STATUS_SUCCESS:
1535 return "SUCCESS";
1536 TX_STATUS_POSTPONE(DELAY);
1537 TX_STATUS_POSTPONE(FEW_BYTES);
1538 TX_STATUS_POSTPONE(QUIET_PERIOD);
1539 TX_STATUS_POSTPONE(CALC_TTAK);
1540 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY);
1541 TX_STATUS_FAIL(SHORT_LIMIT);
1542 TX_STATUS_FAIL(LONG_LIMIT);
1543 TX_STATUS_FAIL(FIFO_UNDERRUN);
1544 TX_STATUS_FAIL(DRAIN_FLOW);
1545 TX_STATUS_FAIL(RFKILL_FLUSH);
1546 TX_STATUS_FAIL(LIFE_EXPIRE);
1547 TX_STATUS_FAIL(DEST_PS);
1548 TX_STATUS_FAIL(HOST_ABORTED);
1549 TX_STATUS_FAIL(BT_RETRY);
1550 TX_STATUS_FAIL(STA_INVALID);
1551 TX_STATUS_FAIL(FRAG_DROPPED);
1552 TX_STATUS_FAIL(TID_DISABLE);
1553 TX_STATUS_FAIL(FIFO_FLUSHED);
1554 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL);
1555 TX_STATUS_FAIL(PASSIVE_NO_RX);
1556 TX_STATUS_FAIL(NO_BEACON_ON_RADAR);
1557 }
1558
1559 return "UNKNOWN";
1560
1561#undef TX_STATUS_FAIL
1562#undef TX_STATUS_POSTPONE
1563}
1564#endif /* CONFIG_IWLEGACY_DEBUG */
1565
89static struct il_link_quality_cmd * 1566static struct il_link_quality_cmd *
90il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id) 1567il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id)
91{ 1568{
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-12 07:49:52 -0500