diff options
Diffstat (limited to 'drivers/net/wireless/hostap/hostap_wlan.h')
-rw-r--r-- | drivers/net/wireless/hostap/hostap_wlan.h | 1033 |
1 files changed, 1033 insertions, 0 deletions
diff --git a/drivers/net/wireless/hostap/hostap_wlan.h b/drivers/net/wireless/hostap/hostap_wlan.h new file mode 100644 index 000000000000..cc061e1560d3 --- /dev/null +++ b/drivers/net/wireless/hostap/hostap_wlan.h | |||
@@ -0,0 +1,1033 @@ | |||
1 | #ifndef HOSTAP_WLAN_H | ||
2 | #define HOSTAP_WLAN_H | ||
3 | |||
4 | #include "hostap_config.h" | ||
5 | #include "hostap_common.h" | ||
6 | |||
7 | #define MAX_PARM_DEVICES 8 | ||
8 | #define PARM_MIN_MAX "1-" __MODULE_STRING(MAX_PARM_DEVICES) | ||
9 | #define DEF_INTS -1, -1, -1, -1, -1, -1, -1 | ||
10 | #define GET_INT_PARM(var,idx) var[var[idx] < 0 ? 0 : idx] | ||
11 | |||
12 | |||
13 | /* Specific skb->protocol value that indicates that the packet already contains | ||
14 | * txdesc header. | ||
15 | * FIX: This might need own value that would be allocated especially for Prism2 | ||
16 | * txdesc; ETH_P_CONTROL is commented as "Card specific control frames". | ||
17 | * However, these skb's should have only minimal path in the kernel side since | ||
18 | * prism2_send_mgmt() sends these with dev_queue_xmit() to prism2_tx(). */ | ||
19 | #define ETH_P_HOSTAP ETH_P_CONTROL | ||
20 | |||
21 | /* ARPHRD_IEEE80211_PRISM uses a bloated version of Prism2 RX frame header | ||
22 | * (from linux-wlan-ng) */ | ||
23 | struct linux_wlan_ng_val { | ||
24 | u32 did; | ||
25 | u16 status, len; | ||
26 | u32 data; | ||
27 | } __attribute__ ((packed)); | ||
28 | |||
29 | struct linux_wlan_ng_prism_hdr { | ||
30 | u32 msgcode, msglen; | ||
31 | char devname[16]; | ||
32 | struct linux_wlan_ng_val hosttime, mactime, channel, rssi, sq, signal, | ||
33 | noise, rate, istx, frmlen; | ||
34 | } __attribute__ ((packed)); | ||
35 | |||
36 | struct linux_wlan_ng_cap_hdr { | ||
37 | u32 version; | ||
38 | u32 length; | ||
39 | u64 mactime; | ||
40 | u64 hosttime; | ||
41 | u32 phytype; | ||
42 | u32 channel; | ||
43 | u32 datarate; | ||
44 | u32 antenna; | ||
45 | u32 priority; | ||
46 | u32 ssi_type; | ||
47 | s32 ssi_signal; | ||
48 | s32 ssi_noise; | ||
49 | u32 preamble; | ||
50 | u32 encoding; | ||
51 | } __attribute__ ((packed)); | ||
52 | |||
53 | #define LWNG_CAP_DID_BASE (4 | (1 << 6)) /* section 4, group 1 */ | ||
54 | #define LWNG_CAPHDR_VERSION 0x80211001 | ||
55 | |||
56 | struct hfa384x_rx_frame { | ||
57 | /* HFA384X RX frame descriptor */ | ||
58 | u16 status; /* HFA384X_RX_STATUS_ flags */ | ||
59 | u32 time; /* timestamp, 1 microsecond resolution */ | ||
60 | u8 silence; /* 27 .. 154; seems to be 0 */ | ||
61 | u8 signal; /* 27 .. 154 */ | ||
62 | u8 rate; /* 10, 20, 55, or 110 */ | ||
63 | u8 rxflow; | ||
64 | u32 reserved; | ||
65 | |||
66 | /* 802.11 */ | ||
67 | u16 frame_control; | ||
68 | u16 duration_id; | ||
69 | u8 addr1[6]; | ||
70 | u8 addr2[6]; | ||
71 | u8 addr3[6]; | ||
72 | u16 seq_ctrl; | ||
73 | u8 addr4[6]; | ||
74 | u16 data_len; | ||
75 | |||
76 | /* 802.3 */ | ||
77 | u8 dst_addr[6]; | ||
78 | u8 src_addr[6]; | ||
79 | u16 len; | ||
80 | |||
81 | /* followed by frame data; max 2304 bytes */ | ||
82 | } __attribute__ ((packed)); | ||
83 | |||
84 | |||
85 | struct hfa384x_tx_frame { | ||
86 | /* HFA384X TX frame descriptor */ | ||
87 | u16 status; /* HFA384X_TX_STATUS_ flags */ | ||
88 | u16 reserved1; | ||
89 | u16 reserved2; | ||
90 | u32 sw_support; | ||
91 | u8 retry_count; /* not yet implemented */ | ||
92 | u8 tx_rate; /* Host AP only; 0 = firmware, or 10, 20, 55, 110 */ | ||
93 | u16 tx_control; /* HFA384X_TX_CTRL_ flags */ | ||
94 | |||
95 | /* 802.11 */ | ||
96 | u16 frame_control; /* parts not used */ | ||
97 | u16 duration_id; | ||
98 | u8 addr1[6]; | ||
99 | u8 addr2[6]; /* filled by firmware */ | ||
100 | u8 addr3[6]; | ||
101 | u16 seq_ctrl; /* filled by firmware */ | ||
102 | u8 addr4[6]; | ||
103 | u16 data_len; | ||
104 | |||
105 | /* 802.3 */ | ||
106 | u8 dst_addr[6]; | ||
107 | u8 src_addr[6]; | ||
108 | u16 len; | ||
109 | |||
110 | /* followed by frame data; max 2304 bytes */ | ||
111 | } __attribute__ ((packed)); | ||
112 | |||
113 | |||
114 | struct hfa384x_rid_hdr | ||
115 | { | ||
116 | u16 len; | ||
117 | u16 rid; | ||
118 | } __attribute__ ((packed)); | ||
119 | |||
120 | |||
121 | /* Macro for converting signal levels (range 27 .. 154) to wireless ext | ||
122 | * dBm value with some accuracy */ | ||
123 | #define HFA384X_LEVEL_TO_dBm(v) 0x100 + (v) * 100 / 255 - 100 | ||
124 | |||
125 | #define HFA384X_LEVEL_TO_dBm_sign(v) (v) * 100 / 255 - 100 | ||
126 | |||
127 | struct hfa384x_scan_request { | ||
128 | u16 channel_list; | ||
129 | u16 txrate; /* HFA384X_RATES_* */ | ||
130 | } __attribute__ ((packed)); | ||
131 | |||
132 | struct hfa384x_hostscan_request { | ||
133 | u16 channel_list; | ||
134 | u16 txrate; | ||
135 | u16 target_ssid_len; | ||
136 | u8 target_ssid[32]; | ||
137 | } __attribute__ ((packed)); | ||
138 | |||
139 | struct hfa384x_join_request { | ||
140 | u8 bssid[6]; | ||
141 | u16 channel; | ||
142 | } __attribute__ ((packed)); | ||
143 | |||
144 | struct hfa384x_info_frame { | ||
145 | u16 len; | ||
146 | u16 type; | ||
147 | } __attribute__ ((packed)); | ||
148 | |||
149 | struct hfa384x_comm_tallies { | ||
150 | u16 tx_unicast_frames; | ||
151 | u16 tx_multicast_frames; | ||
152 | u16 tx_fragments; | ||
153 | u16 tx_unicast_octets; | ||
154 | u16 tx_multicast_octets; | ||
155 | u16 tx_deferred_transmissions; | ||
156 | u16 tx_single_retry_frames; | ||
157 | u16 tx_multiple_retry_frames; | ||
158 | u16 tx_retry_limit_exceeded; | ||
159 | u16 tx_discards; | ||
160 | u16 rx_unicast_frames; | ||
161 | u16 rx_multicast_frames; | ||
162 | u16 rx_fragments; | ||
163 | u16 rx_unicast_octets; | ||
164 | u16 rx_multicast_octets; | ||
165 | u16 rx_fcs_errors; | ||
166 | u16 rx_discards_no_buffer; | ||
167 | u16 tx_discards_wrong_sa; | ||
168 | u16 rx_discards_wep_undecryptable; | ||
169 | u16 rx_message_in_msg_fragments; | ||
170 | u16 rx_message_in_bad_msg_fragments; | ||
171 | } __attribute__ ((packed)); | ||
172 | |||
173 | struct hfa384x_comm_tallies32 { | ||
174 | u32 tx_unicast_frames; | ||
175 | u32 tx_multicast_frames; | ||
176 | u32 tx_fragments; | ||
177 | u32 tx_unicast_octets; | ||
178 | u32 tx_multicast_octets; | ||
179 | u32 tx_deferred_transmissions; | ||
180 | u32 tx_single_retry_frames; | ||
181 | u32 tx_multiple_retry_frames; | ||
182 | u32 tx_retry_limit_exceeded; | ||
183 | u32 tx_discards; | ||
184 | u32 rx_unicast_frames; | ||
185 | u32 rx_multicast_frames; | ||
186 | u32 rx_fragments; | ||
187 | u32 rx_unicast_octets; | ||
188 | u32 rx_multicast_octets; | ||
189 | u32 rx_fcs_errors; | ||
190 | u32 rx_discards_no_buffer; | ||
191 | u32 tx_discards_wrong_sa; | ||
192 | u32 rx_discards_wep_undecryptable; | ||
193 | u32 rx_message_in_msg_fragments; | ||
194 | u32 rx_message_in_bad_msg_fragments; | ||
195 | } __attribute__ ((packed)); | ||
196 | |||
197 | struct hfa384x_scan_result_hdr { | ||
198 | u16 reserved; | ||
199 | u16 scan_reason; | ||
200 | #define HFA384X_SCAN_IN_PROGRESS 0 /* no results available yet */ | ||
201 | #define HFA384X_SCAN_HOST_INITIATED 1 | ||
202 | #define HFA384X_SCAN_FIRMWARE_INITIATED 2 | ||
203 | #define HFA384X_SCAN_INQUIRY_FROM_HOST 3 | ||
204 | } __attribute__ ((packed)); | ||
205 | |||
206 | #define HFA384X_SCAN_MAX_RESULTS 32 | ||
207 | |||
208 | struct hfa384x_scan_result { | ||
209 | u16 chid; | ||
210 | u16 anl; | ||
211 | u16 sl; | ||
212 | u8 bssid[6]; | ||
213 | u16 beacon_interval; | ||
214 | u16 capability; | ||
215 | u16 ssid_len; | ||
216 | u8 ssid[32]; | ||
217 | u8 sup_rates[10]; | ||
218 | u16 rate; | ||
219 | } __attribute__ ((packed)); | ||
220 | |||
221 | struct hfa384x_hostscan_result { | ||
222 | u16 chid; | ||
223 | u16 anl; | ||
224 | u16 sl; | ||
225 | u8 bssid[6]; | ||
226 | u16 beacon_interval; | ||
227 | u16 capability; | ||
228 | u16 ssid_len; | ||
229 | u8 ssid[32]; | ||
230 | u8 sup_rates[10]; | ||
231 | u16 rate; | ||
232 | u16 atim; | ||
233 | } __attribute__ ((packed)); | ||
234 | |||
235 | struct comm_tallies_sums { | ||
236 | unsigned int tx_unicast_frames; | ||
237 | unsigned int tx_multicast_frames; | ||
238 | unsigned int tx_fragments; | ||
239 | unsigned int tx_unicast_octets; | ||
240 | unsigned int tx_multicast_octets; | ||
241 | unsigned int tx_deferred_transmissions; | ||
242 | unsigned int tx_single_retry_frames; | ||
243 | unsigned int tx_multiple_retry_frames; | ||
244 | unsigned int tx_retry_limit_exceeded; | ||
245 | unsigned int tx_discards; | ||
246 | unsigned int rx_unicast_frames; | ||
247 | unsigned int rx_multicast_frames; | ||
248 | unsigned int rx_fragments; | ||
249 | unsigned int rx_unicast_octets; | ||
250 | unsigned int rx_multicast_octets; | ||
251 | unsigned int rx_fcs_errors; | ||
252 | unsigned int rx_discards_no_buffer; | ||
253 | unsigned int tx_discards_wrong_sa; | ||
254 | unsigned int rx_discards_wep_undecryptable; | ||
255 | unsigned int rx_message_in_msg_fragments; | ||
256 | unsigned int rx_message_in_bad_msg_fragments; | ||
257 | }; | ||
258 | |||
259 | |||
260 | struct hfa384x_regs { | ||
261 | u16 cmd; | ||
262 | u16 evstat; | ||
263 | u16 offset0; | ||
264 | u16 offset1; | ||
265 | u16 swsupport0; | ||
266 | }; | ||
267 | |||
268 | |||
269 | #if defined(PRISM2_PCCARD) || defined(PRISM2_PLX) | ||
270 | /* I/O ports for HFA384X Controller access */ | ||
271 | #define HFA384X_CMD_OFF 0x00 | ||
272 | #define HFA384X_PARAM0_OFF 0x02 | ||
273 | #define HFA384X_PARAM1_OFF 0x04 | ||
274 | #define HFA384X_PARAM2_OFF 0x06 | ||
275 | #define HFA384X_STATUS_OFF 0x08 | ||
276 | #define HFA384X_RESP0_OFF 0x0A | ||
277 | #define HFA384X_RESP1_OFF 0x0C | ||
278 | #define HFA384X_RESP2_OFF 0x0E | ||
279 | #define HFA384X_INFOFID_OFF 0x10 | ||
280 | #define HFA384X_CONTROL_OFF 0x14 | ||
281 | #define HFA384X_SELECT0_OFF 0x18 | ||
282 | #define HFA384X_SELECT1_OFF 0x1A | ||
283 | #define HFA384X_OFFSET0_OFF 0x1C | ||
284 | #define HFA384X_OFFSET1_OFF 0x1E | ||
285 | #define HFA384X_RXFID_OFF 0x20 | ||
286 | #define HFA384X_ALLOCFID_OFF 0x22 | ||
287 | #define HFA384X_TXCOMPLFID_OFF 0x24 | ||
288 | #define HFA384X_SWSUPPORT0_OFF 0x28 | ||
289 | #define HFA384X_SWSUPPORT1_OFF 0x2A | ||
290 | #define HFA384X_SWSUPPORT2_OFF 0x2C | ||
291 | #define HFA384X_EVSTAT_OFF 0x30 | ||
292 | #define HFA384X_INTEN_OFF 0x32 | ||
293 | #define HFA384X_EVACK_OFF 0x34 | ||
294 | #define HFA384X_DATA0_OFF 0x36 | ||
295 | #define HFA384X_DATA1_OFF 0x38 | ||
296 | #define HFA384X_AUXPAGE_OFF 0x3A | ||
297 | #define HFA384X_AUXOFFSET_OFF 0x3C | ||
298 | #define HFA384X_AUXDATA_OFF 0x3E | ||
299 | #endif /* PRISM2_PCCARD || PRISM2_PLX */ | ||
300 | |||
301 | #ifdef PRISM2_PCI | ||
302 | /* Memory addresses for ISL3874 controller access */ | ||
303 | #define HFA384X_CMD_OFF 0x00 | ||
304 | #define HFA384X_PARAM0_OFF 0x04 | ||
305 | #define HFA384X_PARAM1_OFF 0x08 | ||
306 | #define HFA384X_PARAM2_OFF 0x0C | ||
307 | #define HFA384X_STATUS_OFF 0x10 | ||
308 | #define HFA384X_RESP0_OFF 0x14 | ||
309 | #define HFA384X_RESP1_OFF 0x18 | ||
310 | #define HFA384X_RESP2_OFF 0x1C | ||
311 | #define HFA384X_INFOFID_OFF 0x20 | ||
312 | #define HFA384X_CONTROL_OFF 0x28 | ||
313 | #define HFA384X_SELECT0_OFF 0x30 | ||
314 | #define HFA384X_SELECT1_OFF 0x34 | ||
315 | #define HFA384X_OFFSET0_OFF 0x38 | ||
316 | #define HFA384X_OFFSET1_OFF 0x3C | ||
317 | #define HFA384X_RXFID_OFF 0x40 | ||
318 | #define HFA384X_ALLOCFID_OFF 0x44 | ||
319 | #define HFA384X_TXCOMPLFID_OFF 0x48 | ||
320 | #define HFA384X_PCICOR_OFF 0x4C | ||
321 | #define HFA384X_SWSUPPORT0_OFF 0x50 | ||
322 | #define HFA384X_SWSUPPORT1_OFF 0x54 | ||
323 | #define HFA384X_SWSUPPORT2_OFF 0x58 | ||
324 | #define HFA384X_PCIHCR_OFF 0x5C | ||
325 | #define HFA384X_EVSTAT_OFF 0x60 | ||
326 | #define HFA384X_INTEN_OFF 0x64 | ||
327 | #define HFA384X_EVACK_OFF 0x68 | ||
328 | #define HFA384X_DATA0_OFF 0x6C | ||
329 | #define HFA384X_DATA1_OFF 0x70 | ||
330 | #define HFA384X_AUXPAGE_OFF 0x74 | ||
331 | #define HFA384X_AUXOFFSET_OFF 0x78 | ||
332 | #define HFA384X_AUXDATA_OFF 0x7C | ||
333 | #define HFA384X_PCI_M0_ADDRH_OFF 0x80 | ||
334 | #define HFA384X_PCI_M0_ADDRL_OFF 0x84 | ||
335 | #define HFA384X_PCI_M0_LEN_OFF 0x88 | ||
336 | #define HFA384X_PCI_M0_CTL_OFF 0x8C | ||
337 | #define HFA384X_PCI_STATUS_OFF 0x98 | ||
338 | #define HFA384X_PCI_M1_ADDRH_OFF 0xA0 | ||
339 | #define HFA384X_PCI_M1_ADDRL_OFF 0xA4 | ||
340 | #define HFA384X_PCI_M1_LEN_OFF 0xA8 | ||
341 | #define HFA384X_PCI_M1_CTL_OFF 0xAC | ||
342 | |||
343 | /* PCI bus master control bits (these are undocumented; based on guessing and | ||
344 | * experimenting..) */ | ||
345 | #define HFA384X_PCI_CTL_FROM_BAP (BIT(5) | BIT(1) | BIT(0)) | ||
346 | #define HFA384X_PCI_CTL_TO_BAP (BIT(5) | BIT(0)) | ||
347 | |||
348 | #endif /* PRISM2_PCI */ | ||
349 | |||
350 | |||
351 | /* Command codes for CMD reg. */ | ||
352 | #define HFA384X_CMDCODE_INIT 0x00 | ||
353 | #define HFA384X_CMDCODE_ENABLE 0x01 | ||
354 | #define HFA384X_CMDCODE_DISABLE 0x02 | ||
355 | #define HFA384X_CMDCODE_ALLOC 0x0A | ||
356 | #define HFA384X_CMDCODE_TRANSMIT 0x0B | ||
357 | #define HFA384X_CMDCODE_INQUIRE 0x11 | ||
358 | #define HFA384X_CMDCODE_ACCESS 0x21 | ||
359 | #define HFA384X_CMDCODE_ACCESS_WRITE (0x21 | BIT(8)) | ||
360 | #define HFA384X_CMDCODE_DOWNLOAD 0x22 | ||
361 | #define HFA384X_CMDCODE_READMIF 0x30 | ||
362 | #define HFA384X_CMDCODE_WRITEMIF 0x31 | ||
363 | #define HFA384X_CMDCODE_TEST 0x38 | ||
364 | |||
365 | #define HFA384X_CMDCODE_MASK 0x3F | ||
366 | |||
367 | /* Test mode operations */ | ||
368 | #define HFA384X_TEST_CHANGE_CHANNEL 0x08 | ||
369 | #define HFA384X_TEST_MONITOR 0x0B | ||
370 | #define HFA384X_TEST_STOP 0x0F | ||
371 | #define HFA384X_TEST_CFG_BITS 0x15 | ||
372 | #define HFA384X_TEST_CFG_BIT_ALC BIT(3) | ||
373 | |||
374 | #define HFA384X_CMD_BUSY BIT(15) | ||
375 | |||
376 | #define HFA384X_CMD_TX_RECLAIM BIT(8) | ||
377 | |||
378 | #define HFA384X_OFFSET_ERR BIT(14) | ||
379 | #define HFA384X_OFFSET_BUSY BIT(15) | ||
380 | |||
381 | |||
382 | /* ProgMode for download command */ | ||
383 | #define HFA384X_PROGMODE_DISABLE 0 | ||
384 | #define HFA384X_PROGMODE_ENABLE_VOLATILE 1 | ||
385 | #define HFA384X_PROGMODE_ENABLE_NON_VOLATILE 2 | ||
386 | #define HFA384X_PROGMODE_PROGRAM_NON_VOLATILE 3 | ||
387 | |||
388 | #define HFA384X_AUX_MAGIC0 0xfe01 | ||
389 | #define HFA384X_AUX_MAGIC1 0xdc23 | ||
390 | #define HFA384X_AUX_MAGIC2 0xba45 | ||
391 | |||
392 | #define HFA384X_AUX_PORT_DISABLED 0 | ||
393 | #define HFA384X_AUX_PORT_DISABLE BIT(14) | ||
394 | #define HFA384X_AUX_PORT_ENABLE BIT(15) | ||
395 | #define HFA384X_AUX_PORT_ENABLED (BIT(14) | BIT(15)) | ||
396 | #define HFA384X_AUX_PORT_MASK (BIT(14) | BIT(15)) | ||
397 | |||
398 | #define PRISM2_PDA_SIZE 1024 | ||
399 | |||
400 | |||
401 | /* Events; EvStat, Interrupt mask (IntEn), and acknowledge bits (EvAck) */ | ||
402 | #define HFA384X_EV_TICK BIT(15) | ||
403 | #define HFA384X_EV_WTERR BIT(14) | ||
404 | #define HFA384X_EV_INFDROP BIT(13) | ||
405 | #ifdef PRISM2_PCI | ||
406 | #define HFA384X_EV_PCI_M1 BIT(9) | ||
407 | #define HFA384X_EV_PCI_M0 BIT(8) | ||
408 | #endif /* PRISM2_PCI */ | ||
409 | #define HFA384X_EV_INFO BIT(7) | ||
410 | #define HFA384X_EV_DTIM BIT(5) | ||
411 | #define HFA384X_EV_CMD BIT(4) | ||
412 | #define HFA384X_EV_ALLOC BIT(3) | ||
413 | #define HFA384X_EV_TXEXC BIT(2) | ||
414 | #define HFA384X_EV_TX BIT(1) | ||
415 | #define HFA384X_EV_RX BIT(0) | ||
416 | |||
417 | |||
418 | /* HFA384X Information frames */ | ||
419 | #define HFA384X_INFO_HANDOVERADDR 0xF000 /* AP f/w ? */ | ||
420 | #define HFA384X_INFO_HANDOVERDEAUTHADDR 0xF001 /* AP f/w 1.3.7 */ | ||
421 | #define HFA384X_INFO_COMMTALLIES 0xF100 | ||
422 | #define HFA384X_INFO_SCANRESULTS 0xF101 | ||
423 | #define HFA384X_INFO_CHANNELINFORESULTS 0xF102 /* AP f/w only */ | ||
424 | #define HFA384X_INFO_HOSTSCANRESULTS 0xF103 | ||
425 | #define HFA384X_INFO_LINKSTATUS 0xF200 | ||
426 | #define HFA384X_INFO_ASSOCSTATUS 0xF201 /* ? */ | ||
427 | #define HFA384X_INFO_AUTHREQ 0xF202 /* ? */ | ||
428 | #define HFA384X_INFO_PSUSERCNT 0xF203 /* ? */ | ||
429 | #define HFA384X_INFO_KEYIDCHANGED 0xF204 /* ? */ | ||
430 | |||
431 | enum { HFA384X_LINKSTATUS_CONNECTED = 1, | ||
432 | HFA384X_LINKSTATUS_DISCONNECTED = 2, | ||
433 | HFA384X_LINKSTATUS_AP_CHANGE = 3, | ||
434 | HFA384X_LINKSTATUS_AP_OUT_OF_RANGE = 4, | ||
435 | HFA384X_LINKSTATUS_AP_IN_RANGE = 5, | ||
436 | HFA384X_LINKSTATUS_ASSOC_FAILED = 6 }; | ||
437 | |||
438 | enum { HFA384X_PORTTYPE_BSS = 1, HFA384X_PORTTYPE_WDS = 2, | ||
439 | HFA384X_PORTTYPE_PSEUDO_IBSS = 3, HFA384X_PORTTYPE_IBSS = 0, | ||
440 | HFA384X_PORTTYPE_HOSTAP = 6 }; | ||
441 | |||
442 | #define HFA384X_RATES_1MBPS BIT(0) | ||
443 | #define HFA384X_RATES_2MBPS BIT(1) | ||
444 | #define HFA384X_RATES_5MBPS BIT(2) | ||
445 | #define HFA384X_RATES_11MBPS BIT(3) | ||
446 | |||
447 | #define HFA384X_ROAMING_FIRMWARE 1 | ||
448 | #define HFA384X_ROAMING_HOST 2 | ||
449 | #define HFA384X_ROAMING_DISABLED 3 | ||
450 | |||
451 | #define HFA384X_WEPFLAGS_PRIVACYINVOKED BIT(0) | ||
452 | #define HFA384X_WEPFLAGS_EXCLUDEUNENCRYPTED BIT(1) | ||
453 | #define HFA384X_WEPFLAGS_HOSTENCRYPT BIT(4) | ||
454 | #define HFA384X_WEPFLAGS_HOSTDECRYPT BIT(7) | ||
455 | |||
456 | #define HFA384X_RX_STATUS_MSGTYPE (BIT(15) | BIT(14) | BIT(13)) | ||
457 | #define HFA384X_RX_STATUS_PCF BIT(12) | ||
458 | #define HFA384X_RX_STATUS_MACPORT (BIT(10) | BIT(9) | BIT(8)) | ||
459 | #define HFA384X_RX_STATUS_UNDECR BIT(1) | ||
460 | #define HFA384X_RX_STATUS_FCSERR BIT(0) | ||
461 | |||
462 | #define HFA384X_RX_STATUS_GET_MSGTYPE(s) \ | ||
463 | (((s) & HFA384X_RX_STATUS_MSGTYPE) >> 13) | ||
464 | #define HFA384X_RX_STATUS_GET_MACPORT(s) \ | ||
465 | (((s) & HFA384X_RX_STATUS_MACPORT) >> 8) | ||
466 | |||
467 | enum { HFA384X_RX_MSGTYPE_NORMAL = 0, HFA384X_RX_MSGTYPE_RFC1042 = 1, | ||
468 | HFA384X_RX_MSGTYPE_BRIDGETUNNEL = 2, HFA384X_RX_MSGTYPE_MGMT = 4 }; | ||
469 | |||
470 | |||
471 | #define HFA384X_TX_CTRL_ALT_RTRY BIT(5) | ||
472 | #define HFA384X_TX_CTRL_802_11 BIT(3) | ||
473 | #define HFA384X_TX_CTRL_802_3 0 | ||
474 | #define HFA384X_TX_CTRL_TX_EX BIT(2) | ||
475 | #define HFA384X_TX_CTRL_TX_OK BIT(1) | ||
476 | |||
477 | #define HFA384X_TX_STATUS_RETRYERR BIT(0) | ||
478 | #define HFA384X_TX_STATUS_AGEDERR BIT(1) | ||
479 | #define HFA384X_TX_STATUS_DISCON BIT(2) | ||
480 | #define HFA384X_TX_STATUS_FORMERR BIT(3) | ||
481 | |||
482 | /* HFA3861/3863 (BBP) Control Registers */ | ||
483 | #define HFA386X_CR_TX_CONFIGURE 0x12 /* CR9 */ | ||
484 | #define HFA386X_CR_RX_CONFIGURE 0x14 /* CR10 */ | ||
485 | #define HFA386X_CR_A_D_TEST_MODES2 0x1A /* CR13 */ | ||
486 | #define HFA386X_CR_MANUAL_TX_POWER 0x3E /* CR31 */ | ||
487 | #define HFA386X_CR_MEASURED_TX_POWER 0x74 /* CR58 */ | ||
488 | |||
489 | |||
490 | #ifdef __KERNEL__ | ||
491 | |||
492 | #define PRISM2_TXFID_COUNT 8 | ||
493 | #define PRISM2_DATA_MAXLEN 2304 | ||
494 | #define PRISM2_TXFID_LEN (PRISM2_DATA_MAXLEN + sizeof(struct hfa384x_tx_frame)) | ||
495 | #define PRISM2_TXFID_EMPTY 0xffff | ||
496 | #define PRISM2_TXFID_RESERVED 0xfffe | ||
497 | #define PRISM2_DUMMY_FID 0xffff | ||
498 | #define MAX_SSID_LEN 32 | ||
499 | #define MAX_NAME_LEN 32 /* this is assumed to be equal to MAX_SSID_LEN */ | ||
500 | |||
501 | #define PRISM2_DUMP_RX_HDR BIT(0) | ||
502 | #define PRISM2_DUMP_TX_HDR BIT(1) | ||
503 | #define PRISM2_DUMP_TXEXC_HDR BIT(2) | ||
504 | |||
505 | struct hostap_tx_callback_info { | ||
506 | u16 idx; | ||
507 | void (*func)(struct sk_buff *, int ok, void *); | ||
508 | void *data; | ||
509 | struct hostap_tx_callback_info *next; | ||
510 | }; | ||
511 | |||
512 | |||
513 | /* IEEE 802.11 requires that STA supports concurrent reception of at least | ||
514 | * three fragmented frames. This define can be increased to support more | ||
515 | * concurrent frames, but it should be noted that each entry can consume about | ||
516 | * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ | ||
517 | #define PRISM2_FRAG_CACHE_LEN 4 | ||
518 | |||
519 | struct prism2_frag_entry { | ||
520 | unsigned long first_frag_time; | ||
521 | unsigned int seq; | ||
522 | unsigned int last_frag; | ||
523 | struct sk_buff *skb; | ||
524 | u8 src_addr[ETH_ALEN]; | ||
525 | u8 dst_addr[ETH_ALEN]; | ||
526 | }; | ||
527 | |||
528 | |||
529 | struct hostap_cmd_queue { | ||
530 | struct list_head list; | ||
531 | wait_queue_head_t compl; | ||
532 | volatile enum { CMD_SLEEP, CMD_CALLBACK, CMD_COMPLETED } type; | ||
533 | void (*callback)(struct net_device *dev, long context, u16 resp0, | ||
534 | u16 res); | ||
535 | long context; | ||
536 | u16 cmd, param0, param1; | ||
537 | u16 resp0, res; | ||
538 | volatile int issued, issuing; | ||
539 | |||
540 | atomic_t usecnt; | ||
541 | int del_req; | ||
542 | }; | ||
543 | |||
544 | /* options for hw_shutdown */ | ||
545 | #define HOSTAP_HW_NO_DISABLE BIT(0) | ||
546 | #define HOSTAP_HW_ENABLE_CMDCOMPL BIT(1) | ||
547 | |||
548 | typedef struct local_info local_info_t; | ||
549 | |||
550 | struct prism2_helper_functions { | ||
551 | /* these functions are defined in hardware model specific files | ||
552 | * (hostap_{cs,plx,pci}.c */ | ||
553 | int (*card_present)(local_info_t *local); | ||
554 | void (*cor_sreset)(local_info_t *local); | ||
555 | int (*dev_open)(local_info_t *local); | ||
556 | int (*dev_close)(local_info_t *local); | ||
557 | void (*genesis_reset)(local_info_t *local, int hcr); | ||
558 | |||
559 | /* the following functions are from hostap_hw.c, but they may have some | ||
560 | * hardware model specific code */ | ||
561 | |||
562 | /* FIX: low-level commands like cmd might disappear at some point to | ||
563 | * make it easier to change them if needed (e.g., cmd would be replaced | ||
564 | * with write_mif/read_mif/testcmd/inquire); at least get_rid and | ||
565 | * set_rid might move to hostap_{cs,plx,pci}.c */ | ||
566 | int (*cmd)(struct net_device *dev, u16 cmd, u16 param0, u16 *param1, | ||
567 | u16 *resp0); | ||
568 | void (*read_regs)(struct net_device *dev, struct hfa384x_regs *regs); | ||
569 | int (*get_rid)(struct net_device *dev, u16 rid, void *buf, int len, | ||
570 | int exact_len); | ||
571 | int (*set_rid)(struct net_device *dev, u16 rid, void *buf, int len); | ||
572 | int (*hw_enable)(struct net_device *dev, int initial); | ||
573 | int (*hw_config)(struct net_device *dev, int initial); | ||
574 | void (*hw_reset)(struct net_device *dev); | ||
575 | void (*hw_shutdown)(struct net_device *dev, int no_disable); | ||
576 | int (*reset_port)(struct net_device *dev); | ||
577 | void (*schedule_reset)(local_info_t *local); | ||
578 | int (*download)(local_info_t *local, | ||
579 | struct prism2_download_param *param); | ||
580 | int (*tx)(struct sk_buff *skb, struct net_device *dev); | ||
581 | int (*set_tim)(struct net_device *dev, int aid, int set); | ||
582 | int (*read_aux)(struct net_device *dev, unsigned addr, int len, | ||
583 | u8 *buf); | ||
584 | |||
585 | int need_tx_headroom; /* number of bytes of headroom needed before | ||
586 | * IEEE 802.11 header */ | ||
587 | enum { HOSTAP_HW_PCCARD, HOSTAP_HW_PLX, HOSTAP_HW_PCI } hw_type; | ||
588 | }; | ||
589 | |||
590 | |||
591 | struct prism2_download_data { | ||
592 | u32 dl_cmd; | ||
593 | u32 start_addr; | ||
594 | u32 num_areas; | ||
595 | struct prism2_download_data_area { | ||
596 | u32 addr; /* wlan card address */ | ||
597 | u32 len; | ||
598 | u8 *data; /* allocated data */ | ||
599 | } data[0]; | ||
600 | }; | ||
601 | |||
602 | |||
603 | #define HOSTAP_MAX_BSS_COUNT 64 | ||
604 | #define MAX_WPA_IE_LEN 64 | ||
605 | |||
606 | struct hostap_bss_info { | ||
607 | struct list_head list; | ||
608 | unsigned long last_update; | ||
609 | unsigned int count; | ||
610 | u8 bssid[ETH_ALEN]; | ||
611 | u16 capab_info; | ||
612 | u8 ssid[32]; | ||
613 | size_t ssid_len; | ||
614 | u8 wpa_ie[MAX_WPA_IE_LEN]; | ||
615 | size_t wpa_ie_len; | ||
616 | u8 rsn_ie[MAX_WPA_IE_LEN]; | ||
617 | size_t rsn_ie_len; | ||
618 | int chan; | ||
619 | int included; | ||
620 | }; | ||
621 | |||
622 | |||
623 | /* Per radio private Host AP data - shared by all net devices interfaces used | ||
624 | * by each radio (wlan#, wlan#ap, wlan#sta, WDS). | ||
625 | * ((struct hostap_interface *) netdev_priv(dev))->local points to this | ||
626 | * structure. */ | ||
627 | struct local_info { | ||
628 | struct module *hw_module; | ||
629 | int card_idx; | ||
630 | int dev_enabled; | ||
631 | int master_dev_auto_open; /* was master device opened automatically */ | ||
632 | int num_dev_open; /* number of open devices */ | ||
633 | struct net_device *dev; /* master radio device */ | ||
634 | struct net_device *ddev; /* main data device */ | ||
635 | struct list_head hostap_interfaces; /* Host AP interface list (contains | ||
636 | * struct hostap_interface entries) | ||
637 | */ | ||
638 | rwlock_t iface_lock; /* hostap_interfaces read lock; use write lock | ||
639 | * when removing entries from the list. | ||
640 | * TX and RX paths can use read lock. */ | ||
641 | spinlock_t cmdlock, baplock, lock; | ||
642 | struct semaphore rid_bap_sem; | ||
643 | u16 infofid; /* MAC buffer id for info frame */ | ||
644 | /* txfid, intransmitfid, next_txtid, and next_alloc are protected by | ||
645 | * txfidlock */ | ||
646 | spinlock_t txfidlock; | ||
647 | int txfid_len; /* length of allocated TX buffers */ | ||
648 | u16 txfid[PRISM2_TXFID_COUNT]; /* buffer IDs for TX frames */ | ||
649 | /* buffer IDs for intransmit frames or PRISM2_TXFID_EMPTY if | ||
650 | * corresponding txfid is free for next TX frame */ | ||
651 | u16 intransmitfid[PRISM2_TXFID_COUNT]; | ||
652 | int next_txfid; /* index to the next txfid to be checked for | ||
653 | * availability */ | ||
654 | int next_alloc; /* index to the next intransmitfid to be checked for | ||
655 | * allocation events */ | ||
656 | |||
657 | /* bitfield for atomic bitops */ | ||
658 | #define HOSTAP_BITS_TRANSMIT 0 | ||
659 | #define HOSTAP_BITS_BAP_TASKLET 1 | ||
660 | #define HOSTAP_BITS_BAP_TASKLET2 2 | ||
661 | long bits; | ||
662 | |||
663 | struct ap_data *ap; | ||
664 | |||
665 | char essid[MAX_SSID_LEN + 1]; | ||
666 | char name[MAX_NAME_LEN + 1]; | ||
667 | int name_set; | ||
668 | u16 channel_mask; /* mask of allowed channels */ | ||
669 | u16 scan_channel_mask; /* mask of channels to be scanned */ | ||
670 | struct comm_tallies_sums comm_tallies; | ||
671 | struct net_device_stats stats; | ||
672 | struct proc_dir_entry *proc; | ||
673 | int iw_mode; /* operating mode (IW_MODE_*) */ | ||
674 | int pseudo_adhoc; /* 0: IW_MODE_ADHOC is real 802.11 compliant IBSS | ||
675 | * 1: IW_MODE_ADHOC is "pseudo IBSS" */ | ||
676 | char bssid[ETH_ALEN]; | ||
677 | int channel; | ||
678 | int beacon_int; | ||
679 | int dtim_period; | ||
680 | int mtu; | ||
681 | int frame_dump; /* dump RX/TX frame headers, PRISM2_DUMP_ flags */ | ||
682 | int fw_tx_rate_control; | ||
683 | u16 tx_rate_control; | ||
684 | u16 basic_rates; | ||
685 | int hw_resetting; | ||
686 | int hw_ready; | ||
687 | int hw_reset_tries; /* how many times reset has been tried */ | ||
688 | int hw_downloading; | ||
689 | int shutdown; | ||
690 | int pri_only; | ||
691 | int no_pri; /* no PRI f/w present */ | ||
692 | int sram_type; /* 8 = x8 SRAM, 16 = x16 SRAM, -1 = unknown */ | ||
693 | |||
694 | enum { | ||
695 | PRISM2_TXPOWER_AUTO = 0, PRISM2_TXPOWER_OFF, | ||
696 | PRISM2_TXPOWER_FIXED, PRISM2_TXPOWER_UNKNOWN | ||
697 | } txpower_type; | ||
698 | int txpower; /* if txpower_type == PRISM2_TXPOWER_FIXED */ | ||
699 | |||
700 | /* command queue for hfa384x_cmd(); protected with cmdlock */ | ||
701 | struct list_head cmd_queue; | ||
702 | /* max_len for cmd_queue; in addition, cmd_callback can use two | ||
703 | * additional entries to prevent sleeping commands from stopping | ||
704 | * transmits */ | ||
705 | #define HOSTAP_CMD_QUEUE_MAX_LEN 16 | ||
706 | int cmd_queue_len; /* number of entries in cmd_queue */ | ||
707 | |||
708 | /* if card timeout is detected in interrupt context, reset_queue is | ||
709 | * used to schedule card reseting to be done in user context */ | ||
710 | struct work_struct reset_queue; | ||
711 | |||
712 | /* For scheduling a change of the promiscuous mode RID */ | ||
713 | int is_promisc; | ||
714 | struct work_struct set_multicast_list_queue; | ||
715 | |||
716 | struct work_struct set_tim_queue; | ||
717 | struct list_head set_tim_list; | ||
718 | spinlock_t set_tim_lock; | ||
719 | |||
720 | int wds_max_connections; | ||
721 | int wds_connections; | ||
722 | #define HOSTAP_WDS_BROADCAST_RA BIT(0) | ||
723 | #define HOSTAP_WDS_AP_CLIENT BIT(1) | ||
724 | #define HOSTAP_WDS_STANDARD_FRAME BIT(2) | ||
725 | u32 wds_type; | ||
726 | u16 tx_control; /* flags to be used in TX description */ | ||
727 | int manual_retry_count; /* -1 = use f/w default; otherwise retry count | ||
728 | * to be used with all frames */ | ||
729 | |||
730 | struct iw_statistics wstats; | ||
731 | unsigned long scan_timestamp; /* Time started to scan */ | ||
732 | enum { | ||
733 | PRISM2_MONITOR_80211 = 0, PRISM2_MONITOR_PRISM = 1, | ||
734 | PRISM2_MONITOR_CAPHDR = 2 | ||
735 | } monitor_type; | ||
736 | int (*saved_eth_header_parse)(struct sk_buff *skb, | ||
737 | unsigned char *haddr); | ||
738 | int monitor_allow_fcserr; | ||
739 | |||
740 | int hostapd; /* whether user space daemon, hostapd, is used for AP | ||
741 | * management */ | ||
742 | int hostapd_sta; /* whether hostapd is used with an extra STA interface | ||
743 | */ | ||
744 | struct net_device *apdev; | ||
745 | struct net_device_stats apdevstats; | ||
746 | |||
747 | char assoc_ap_addr[ETH_ALEN]; | ||
748 | struct net_device *stadev; | ||
749 | struct net_device_stats stadevstats; | ||
750 | |||
751 | #define WEP_KEYS 4 | ||
752 | #define WEP_KEY_LEN 13 | ||
753 | struct ieee80211_crypt_data *crypt[WEP_KEYS]; | ||
754 | int tx_keyidx; /* default TX key index (crypt[tx_keyidx]) */ | ||
755 | struct timer_list crypt_deinit_timer; | ||
756 | struct list_head crypt_deinit_list; | ||
757 | |||
758 | int open_wep; /* allow unencrypted frames */ | ||
759 | int host_encrypt; | ||
760 | int host_decrypt; | ||
761 | int privacy_invoked; /* force privacy invoked flag even if no keys are | ||
762 | * configured */ | ||
763 | int fw_encrypt_ok; /* whether firmware-based WEP encrypt is working | ||
764 | * in Host AP mode (STA f/w 1.4.9 or newer) */ | ||
765 | int bcrx_sta_key; /* use individual keys to override default keys even | ||
766 | * with RX of broad/multicast frames */ | ||
767 | |||
768 | struct prism2_frag_entry frag_cache[PRISM2_FRAG_CACHE_LEN]; | ||
769 | unsigned int frag_next_idx; | ||
770 | |||
771 | int ieee_802_1x; /* is IEEE 802.1X used */ | ||
772 | |||
773 | int antsel_tx, antsel_rx; | ||
774 | int rts_threshold; /* dot11RTSThreshold */ | ||
775 | int fragm_threshold; /* dot11FragmentationThreshold */ | ||
776 | int auth_algs; /* PRISM2_AUTH_ flags */ | ||
777 | |||
778 | int enh_sec; /* cnfEnhSecurity options (broadcast SSID hide/ignore) */ | ||
779 | int tallies32; /* 32-bit tallies in use */ | ||
780 | |||
781 | struct prism2_helper_functions *func; | ||
782 | |||
783 | u8 *pda; | ||
784 | int fw_ap; | ||
785 | #define PRISM2_FW_VER(major, minor, variant) \ | ||
786 | (((major) << 16) | ((minor) << 8) | variant) | ||
787 | u32 sta_fw_ver; | ||
788 | |||
789 | /* Tasklets for handling hardware IRQ related operations outside hw IRQ | ||
790 | * handler */ | ||
791 | struct tasklet_struct bap_tasklet; | ||
792 | |||
793 | struct tasklet_struct info_tasklet; | ||
794 | struct sk_buff_head info_list; /* info frames as skb's for | ||
795 | * info_tasklet */ | ||
796 | |||
797 | struct hostap_tx_callback_info *tx_callback; /* registered TX callbacks | ||
798 | */ | ||
799 | |||
800 | struct tasklet_struct rx_tasklet; | ||
801 | struct sk_buff_head rx_list; | ||
802 | |||
803 | struct tasklet_struct sta_tx_exc_tasklet; | ||
804 | struct sk_buff_head sta_tx_exc_list; | ||
805 | |||
806 | int host_roaming; | ||
807 | unsigned long last_join_time; /* time of last JoinRequest */ | ||
808 | struct hfa384x_hostscan_result *last_scan_results; | ||
809 | int last_scan_results_count; | ||
810 | enum { PRISM2_SCAN, PRISM2_HOSTSCAN } last_scan_type; | ||
811 | struct work_struct info_queue; | ||
812 | long pending_info; /* bit field of pending info_queue items */ | ||
813 | #define PRISM2_INFO_PENDING_LINKSTATUS 0 | ||
814 | #define PRISM2_INFO_PENDING_SCANRESULTS 1 | ||
815 | int prev_link_status; /* previous received LinkStatus info */ | ||
816 | int prev_linkstatus_connected; | ||
817 | u8 preferred_ap[6]; /* use this AP if possible */ | ||
818 | |||
819 | #ifdef PRISM2_CALLBACK | ||
820 | void *callback_data; /* Can be used in callbacks; e.g., allocate | ||
821 | * on enable event and free on disable event. | ||
822 | * Host AP driver code does not touch this. */ | ||
823 | #endif /* PRISM2_CALLBACK */ | ||
824 | |||
825 | wait_queue_head_t hostscan_wq; | ||
826 | |||
827 | /* Passive scan in Host AP mode */ | ||
828 | struct timer_list passive_scan_timer; | ||
829 | int passive_scan_interval; /* in seconds, 0 = disabled */ | ||
830 | int passive_scan_channel; | ||
831 | enum { PASSIVE_SCAN_WAIT, PASSIVE_SCAN_LISTEN } passive_scan_state; | ||
832 | |||
833 | struct timer_list tick_timer; | ||
834 | unsigned long last_tick_timer; | ||
835 | unsigned int sw_tick_stuck; | ||
836 | |||
837 | /* commsQuality / dBmCommsQuality data from periodic polling; only | ||
838 | * valid for Managed and Ad-hoc modes */ | ||
839 | unsigned long last_comms_qual_update; | ||
840 | int comms_qual; /* in some odd unit.. */ | ||
841 | int avg_signal; /* in dB (note: negative) */ | ||
842 | int avg_noise; /* in dB (note: negative) */ | ||
843 | struct work_struct comms_qual_update; | ||
844 | |||
845 | /* RSSI to dBm adjustment (for RX descriptor fields) */ | ||
846 | int rssi_to_dBm; /* substract from RSSI to get approximate dBm value */ | ||
847 | |||
848 | /* BSS list / protected by local->lock */ | ||
849 | struct list_head bss_list; | ||
850 | int num_bss_info; | ||
851 | int wpa; /* WPA support enabled */ | ||
852 | int tkip_countermeasures; | ||
853 | int drop_unencrypted; | ||
854 | /* Generic IEEE 802.11 info element to be added to | ||
855 | * ProbeResp/Beacon/(Re)AssocReq */ | ||
856 | u8 *generic_elem; | ||
857 | size_t generic_elem_len; | ||
858 | |||
859 | #ifdef PRISM2_DOWNLOAD_SUPPORT | ||
860 | /* Persistent volatile download data */ | ||
861 | struct prism2_download_data *dl_pri; | ||
862 | struct prism2_download_data *dl_sec; | ||
863 | #endif /* PRISM2_DOWNLOAD_SUPPORT */ | ||
864 | |||
865 | #ifdef PRISM2_IO_DEBUG | ||
866 | #define PRISM2_IO_DEBUG_SIZE 10000 | ||
867 | u32 io_debug[PRISM2_IO_DEBUG_SIZE]; | ||
868 | int io_debug_head; | ||
869 | int io_debug_enabled; | ||
870 | #endif /* PRISM2_IO_DEBUG */ | ||
871 | |||
872 | /* Pointer to hardware model specific (cs,pci,plx) private data. */ | ||
873 | void *hw_priv; | ||
874 | }; | ||
875 | |||
876 | |||
877 | /* Per interface private Host AP data | ||
878 | * Allocated for each net device that Host AP uses (wlan#, wlan#ap, wlan#sta, | ||
879 | * WDS) and netdev_priv(dev) points to this structure. */ | ||
880 | struct hostap_interface { | ||
881 | struct list_head list; /* list entry in Host AP interface list */ | ||
882 | struct net_device *dev; /* pointer to this device */ | ||
883 | struct local_info *local; /* pointer to shared private data */ | ||
884 | struct net_device_stats stats; | ||
885 | struct iw_spy_data spy_data; /* iwspy support */ | ||
886 | struct iw_public_data wireless_data; | ||
887 | |||
888 | enum { | ||
889 | HOSTAP_INTERFACE_MASTER, | ||
890 | HOSTAP_INTERFACE_MAIN, | ||
891 | HOSTAP_INTERFACE_AP, | ||
892 | HOSTAP_INTERFACE_STA, | ||
893 | HOSTAP_INTERFACE_WDS, | ||
894 | } type; | ||
895 | |||
896 | union { | ||
897 | struct hostap_interface_wds { | ||
898 | u8 remote_addr[ETH_ALEN]; | ||
899 | } wds; | ||
900 | } u; | ||
901 | }; | ||
902 | |||
903 | |||
904 | #define HOSTAP_SKB_TX_DATA_MAGIC 0xf08a36a2 | ||
905 | |||
906 | /* | ||
907 | * TX meta data - stored in skb->cb buffer, so this must not be increased over | ||
908 | * the 40-byte limit | ||
909 | */ | ||
910 | struct hostap_skb_tx_data { | ||
911 | u32 magic; /* HOSTAP_SKB_TX_DATA_MAGIC */ | ||
912 | u8 rate; /* transmit rate */ | ||
913 | #define HOSTAP_TX_FLAGS_WDS BIT(0) | ||
914 | #define HOSTAP_TX_FLAGS_BUFFERED_FRAME BIT(1) | ||
915 | #define HOSTAP_TX_FLAGS_ADD_MOREDATA BIT(2) | ||
916 | u8 flags; /* HOSTAP_TX_FLAGS_* */ | ||
917 | u16 tx_cb_idx; | ||
918 | struct hostap_interface *iface; | ||
919 | unsigned long jiffies; /* queueing timestamp */ | ||
920 | unsigned short ethertype; | ||
921 | }; | ||
922 | |||
923 | |||
924 | #ifndef PRISM2_NO_DEBUG | ||
925 | |||
926 | #define DEBUG_FID BIT(0) | ||
927 | #define DEBUG_PS BIT(1) | ||
928 | #define DEBUG_FLOW BIT(2) | ||
929 | #define DEBUG_AP BIT(3) | ||
930 | #define DEBUG_HW BIT(4) | ||
931 | #define DEBUG_EXTRA BIT(5) | ||
932 | #define DEBUG_EXTRA2 BIT(6) | ||
933 | #define DEBUG_PS2 BIT(7) | ||
934 | #define DEBUG_MASK (DEBUG_PS | DEBUG_AP | DEBUG_HW | DEBUG_EXTRA) | ||
935 | #define PDEBUG(n, args...) \ | ||
936 | do { if ((n) & DEBUG_MASK) printk(KERN_DEBUG args); } while (0) | ||
937 | #define PDEBUG2(n, args...) \ | ||
938 | do { if ((n) & DEBUG_MASK) printk(args); } while (0) | ||
939 | |||
940 | #else /* PRISM2_NO_DEBUG */ | ||
941 | |||
942 | #define PDEBUG(n, args...) | ||
943 | #define PDEBUG2(n, args...) | ||
944 | |||
945 | #endif /* PRISM2_NO_DEBUG */ | ||
946 | |||
947 | enum { BAP0 = 0, BAP1 = 1 }; | ||
948 | |||
949 | #define PRISM2_IO_DEBUG_CMD_INB 0 | ||
950 | #define PRISM2_IO_DEBUG_CMD_INW 1 | ||
951 | #define PRISM2_IO_DEBUG_CMD_INSW 2 | ||
952 | #define PRISM2_IO_DEBUG_CMD_OUTB 3 | ||
953 | #define PRISM2_IO_DEBUG_CMD_OUTW 4 | ||
954 | #define PRISM2_IO_DEBUG_CMD_OUTSW 5 | ||
955 | #define PRISM2_IO_DEBUG_CMD_ERROR 6 | ||
956 | #define PRISM2_IO_DEBUG_CMD_INTERRUPT 7 | ||
957 | |||
958 | #ifdef PRISM2_IO_DEBUG | ||
959 | |||
960 | #define PRISM2_IO_DEBUG_ENTRY(cmd, reg, value) \ | ||
961 | (((cmd) << 24) | ((reg) << 16) | value) | ||
962 | |||
963 | static inline void prism2_io_debug_add(struct net_device *dev, int cmd, | ||
964 | int reg, int value) | ||
965 | { | ||
966 | struct hostap_interface *iface = netdev_priv(dev); | ||
967 | local_info_t *local = iface->local; | ||
968 | |||
969 | if (!local->io_debug_enabled) | ||
970 | return; | ||
971 | |||
972 | local->io_debug[local->io_debug_head] = jiffies & 0xffffffff; | ||
973 | if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE) | ||
974 | local->io_debug_head = 0; | ||
975 | local->io_debug[local->io_debug_head] = | ||
976 | PRISM2_IO_DEBUG_ENTRY(cmd, reg, value); | ||
977 | if (++local->io_debug_head >= PRISM2_IO_DEBUG_SIZE) | ||
978 | local->io_debug_head = 0; | ||
979 | } | ||
980 | |||
981 | |||
982 | static inline void prism2_io_debug_error(struct net_device *dev, int err) | ||
983 | { | ||
984 | struct hostap_interface *iface = netdev_priv(dev); | ||
985 | local_info_t *local = iface->local; | ||
986 | unsigned long flags; | ||
987 | |||
988 | if (!local->io_debug_enabled) | ||
989 | return; | ||
990 | |||
991 | spin_lock_irqsave(&local->lock, flags); | ||
992 | prism2_io_debug_add(dev, PRISM2_IO_DEBUG_CMD_ERROR, 0, err); | ||
993 | if (local->io_debug_enabled == 1) { | ||
994 | local->io_debug_enabled = 0; | ||
995 | printk(KERN_DEBUG "%s: I/O debug stopped\n", dev->name); | ||
996 | } | ||
997 | spin_unlock_irqrestore(&local->lock, flags); | ||
998 | } | ||
999 | |||
1000 | #else /* PRISM2_IO_DEBUG */ | ||
1001 | |||
1002 | static inline void prism2_io_debug_add(struct net_device *dev, int cmd, | ||
1003 | int reg, int value) | ||
1004 | { | ||
1005 | } | ||
1006 | |||
1007 | static inline void prism2_io_debug_error(struct net_device *dev, int err) | ||
1008 | { | ||
1009 | } | ||
1010 | |||
1011 | #endif /* PRISM2_IO_DEBUG */ | ||
1012 | |||
1013 | |||
1014 | #ifdef PRISM2_CALLBACK | ||
1015 | enum { | ||
1016 | /* Called when card is enabled */ | ||
1017 | PRISM2_CALLBACK_ENABLE, | ||
1018 | |||
1019 | /* Called when card is disabled */ | ||
1020 | PRISM2_CALLBACK_DISABLE, | ||
1021 | |||
1022 | /* Called when RX/TX starts/ends */ | ||
1023 | PRISM2_CALLBACK_RX_START, PRISM2_CALLBACK_RX_END, | ||
1024 | PRISM2_CALLBACK_TX_START, PRISM2_CALLBACK_TX_END | ||
1025 | }; | ||
1026 | void prism2_callback(local_info_t *local, int event); | ||
1027 | #else /* PRISM2_CALLBACK */ | ||
1028 | #define prism2_callback(d, e) do { } while (0) | ||
1029 | #endif /* PRISM2_CALLBACK */ | ||
1030 | |||
1031 | #endif /* __KERNEL__ */ | ||
1032 | |||
1033 | #endif /* HOSTAP_WLAN_H */ | ||