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-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/Makefile3
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/aiutils.c479
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/aiutils.h24
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/antsel.c16
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/channel.c7
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c11
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/main.c142
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/nicpci.c826
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/nicpci.h77
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/otp.c410
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/otp.h36
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c67
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c333
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c9
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h3
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/pub.h228
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/srom.c980
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/srom.h29
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/stf.c6
19 files changed, 252 insertions, 3434 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/Makefile b/drivers/net/wireless/brcm80211/brcmsmac/Makefile
index c2eb2d0af386..e227c4c68ef9 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/Makefile
+++ b/drivers/net/wireless/brcm80211/brcmsmac/Makefile
@@ -39,10 +39,7 @@ BRCMSMAC_OFILES := \
39 phy/phytbl_lcn.o \ 39 phy/phytbl_lcn.o \
40 phy/phytbl_n.o \ 40 phy/phytbl_n.o \
41 phy/phy_qmath.o \ 41 phy/phy_qmath.o \
42 otp.o \
43 srom.o \
44 dma.o \ 42 dma.o \
45 nicpci.o \
46 brcms_trace_events.o 43 brcms_trace_events.o
47 44
48MODULEPFX := brcmsmac 45MODULEPFX := brcmsmac
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
index c93ea35bceec..6d8b7213643a 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
@@ -19,7 +19,6 @@
19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 20
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/pci.h>
23 22
24#include <defs.h> 23#include <defs.h>
25#include <chipcommon.h> 24#include <chipcommon.h>
@@ -29,8 +28,6 @@
29#include "types.h" 28#include "types.h"
30#include "pub.h" 29#include "pub.h"
31#include "pmu.h" 30#include "pmu.h"
32#include "srom.h"
33#include "nicpci.h"
34#include "aiutils.h" 31#include "aiutils.h"
35 32
36/* slow_clk_ctl */ 33/* slow_clk_ctl */
@@ -321,7 +318,6 @@
321#define IS_SIM(chippkg) \ 318#define IS_SIM(chippkg) \
322 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 319 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
323 320
324#define PCI(sih) (ai_get_buscoretype(sih) == PCI_CORE_ID)
325#define PCIE(sih) (ai_get_buscoretype(sih) == PCIE_CORE_ID) 321#define PCIE(sih) (ai_get_buscoretype(sih) == PCIE_CORE_ID)
326 322
327#define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID)) 323#define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
@@ -454,36 +450,9 @@ struct aidmp {
454 u32 componentid3; /* 0xffc */ 450 u32 componentid3; /* 0xffc */
455}; 451};
456 452
457/* return true if PCIE capability exists in the pci config space */
458static bool ai_ispcie(struct si_info *sii)
459{
460 u8 cap_ptr;
461
462 cap_ptr =
463 pcicore_find_pci_capability(sii->pcibus, PCI_CAP_ID_EXP, NULL,
464 NULL);
465 if (!cap_ptr)
466 return false;
467
468 return true;
469}
470
471static bool ai_buscore_prep(struct si_info *sii)
472{
473 /* kludge to enable the clock on the 4306 which lacks a slowclock */
474 if (!ai_ispcie(sii))
475 ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
476 return true;
477}
478
479static bool 453static bool
480ai_buscore_setup(struct si_info *sii, struct bcma_device *cc) 454ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
481{ 455{
482 struct bcma_device *pci = NULL;
483 struct bcma_device *pcie = NULL;
484 struct bcma_device *core;
485
486
487 /* no cores found, bail out */ 456 /* no cores found, bail out */
488 if (cc->bus->nr_cores == 0) 457 if (cc->bus->nr_cores == 0)
489 return false; 458 return false;
@@ -492,8 +461,7 @@ ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
492 sii->pub.ccrev = cc->id.rev; 461 sii->pub.ccrev = cc->id.rev;
493 462
494 /* get chipcommon chipstatus */ 463 /* get chipcommon chipstatus */
495 if (ai_get_ccrev(&sii->pub) >= 11) 464 sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
496 sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
497 465
498 /* get chipcommon capabilites */ 466 /* get chipcommon capabilites */
499 sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities)); 467 sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities));
@@ -506,64 +474,18 @@ ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
506 } 474 }
507 475
508 /* figure out buscore */ 476 /* figure out buscore */
509 list_for_each_entry(core, &cc->bus->cores, list) { 477 sii->buscore = ai_findcore(&sii->pub, PCIE_CORE_ID, 0);
510 uint cid, crev;
511
512 cid = core->id.id;
513 crev = core->id.rev;
514
515 if (cid == PCI_CORE_ID) {
516 pci = core;
517 } else if (cid == PCIE_CORE_ID) {
518 pcie = core;
519 }
520 }
521
522 if (pci && pcie) {
523 if (ai_ispcie(sii))
524 pci = NULL;
525 else
526 pcie = NULL;
527 }
528 if (pci) {
529 sii->buscore = pci;
530 } else if (pcie) {
531 sii->buscore = pcie;
532 }
533
534 /* fixup necessary chip/core configurations */
535 if (!sii->pch) {
536 sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
537 if (sii->pch == NULL)
538 return false;
539 }
540 if (ai_pci_fixcfg(&sii->pub))
541 return false;
542 478
543 return true; 479 return true;
544} 480}
545 481
546/*
547 * get boardtype and boardrev
548 */
549static __used void ai_nvram_process(struct si_info *sii)
550{
551 uint w = 0;
552
553 /* do a pci config read to get subsystem id and subvendor id */
554 pci_read_config_dword(sii->pcibus, PCI_SUBSYSTEM_VENDOR_ID, &w);
555
556 sii->pub.boardvendor = w & 0xffff;
557 sii->pub.boardtype = (w >> 16) & 0xffff;
558}
559
560static struct si_info *ai_doattach(struct si_info *sii, 482static struct si_info *ai_doattach(struct si_info *sii,
561 struct bcma_bus *pbus) 483 struct bcma_bus *pbus)
562{ 484{
563 struct si_pub *sih = &sii->pub; 485 struct si_pub *sih = &sii->pub;
564 u32 w, savewin; 486 u32 w, savewin;
565 struct bcma_device *cc; 487 struct bcma_device *cc;
566 uint socitype; 488 struct ssb_sprom *sprom = &pbus->sprom;
567 489
568 savewin = 0; 490 savewin = 0;
569 491
@@ -573,38 +495,15 @@ static struct si_info *ai_doattach(struct si_info *sii,
573 /* switch to Chipcommon core */ 495 /* switch to Chipcommon core */
574 cc = pbus->drv_cc.core; 496 cc = pbus->drv_cc.core;
575 497
576 /* bus/core/clk setup for register access */ 498 sih->chip = pbus->chipinfo.id;
577 if (!ai_buscore_prep(sii)) 499 sih->chiprev = pbus->chipinfo.rev;
578 return NULL; 500 sih->chippkg = pbus->chipinfo.pkg;
501 sih->boardvendor = pbus->boardinfo.vendor;
502 sih->boardtype = pbus->boardinfo.type;
579 503
580 /*
581 * ChipID recognition.
582 * We assume we can read chipid at offset 0 from the regs arg.
583 * If we add other chiptypes (or if we need to support old sdio
584 * hosts w/o chipcommon), some way of recognizing them needs to
585 * be added here.
586 */
587 w = bcma_read32(cc, CHIPCREGOFFS(chipid));
588 socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
589 /* Might as wll fill in chip id rev & pkg */
590 sih->chip = w & CID_ID_MASK;
591 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
592 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
593
594 /* scan for cores */
595 if (socitype != SOCI_AI)
596 return NULL;
597
598 SI_MSG("Found chip type AI (0x%08x)\n", w);
599 if (!ai_buscore_setup(sii, cc)) 504 if (!ai_buscore_setup(sii, cc))
600 goto exit; 505 goto exit;
601 506
602 /* Init nvram from sprom/otp if they exist */
603 if (srom_var_init(&sii->pub))
604 goto exit;
605
606 ai_nvram_process(sii);
607
608 /* === NVRAM, clock is ready === */ 507 /* === NVRAM, clock is ready === */
609 bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0); 508 bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0);
610 bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0); 509 bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0);
@@ -617,15 +516,13 @@ static struct si_info *ai_doattach(struct si_info *sii,
617 } 516 }
618 517
619 /* setup the GPIO based LED powersave register */ 518 /* setup the GPIO based LED powersave register */
620 w = getintvar(sih, BRCMS_SROM_LEDDC); 519 w = (sprom->leddc_on_time << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
520 (sprom->leddc_off_time << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT);
621 if (w == 0) 521 if (w == 0)
622 w = DEFAULT_GPIOTIMERVAL; 522 w = DEFAULT_GPIOTIMERVAL;
623 ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval), 523 ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
624 ~0, w); 524 ~0, w);
625 525
626 if (PCIE(sih))
627 pcicore_attach(sii->pch, SI_DOATTACH);
628
629 if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) { 526 if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
630 /* 527 /*
631 * enable 12 mA drive strenth for 43224 and 528 * enable 12 mA drive strenth for 43224 and
@@ -659,9 +556,6 @@ static struct si_info *ai_doattach(struct si_info *sii,
659 return sii; 556 return sii;
660 557
661 exit: 558 exit:
662 if (sii->pch)
663 pcicore_deinit(sii->pch);
664 sii->pch = NULL;
665 559
666 return NULL; 560 return NULL;
667} 561}
@@ -700,11 +594,6 @@ void ai_detach(struct si_pub *sih)
700 if (sii == NULL) 594 if (sii == NULL)
701 return; 595 return;
702 596
703 if (sii->pch)
704 pcicore_deinit(sii->pch);
705 sii->pch = NULL;
706
707 srom_free_vars(sih);
708 kfree(sii); 597 kfree(sii);
709} 598}
710 599
@@ -755,21 +644,7 @@ uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val)
755/* return the slow clock source - LPO, XTAL, or PCI */ 644/* return the slow clock source - LPO, XTAL, or PCI */
756static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc) 645static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
757{ 646{
758 struct si_info *sii; 647 return SCC_SS_XTAL;
759 u32 val;
760
761 sii = (struct si_info *)sih;
762 if (ai_get_ccrev(&sii->pub) < 6) {
763 pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT,
764 &val);
765 if (val & PCI_CFG_GPIO_SCS)
766 return SCC_SS_PCI;
767 return SCC_SS_XTAL;
768 } else if (ai_get_ccrev(&sii->pub) < 10) {
769 return bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
770 SCC_SS_MASK;
771 } else /* Insta-clock */
772 return SCC_SS_XTAL;
773} 648}
774 649
775/* 650/*
@@ -779,36 +654,12 @@ static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
779static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq, 654static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq,
780 struct bcma_device *cc) 655 struct bcma_device *cc)
781{ 656{
782 u32 slowclk;
783 uint div; 657 uint div;
784 658
785 slowclk = ai_slowclk_src(sih, cc); 659 /* Chipc rev 10 is InstaClock */
786 if (ai_get_ccrev(sih) < 6) { 660 div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
787 if (slowclk == SCC_SS_PCI) 661 div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
788 return max_freq ? (PCIMAXFREQ / 64) 662 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
789 : (PCIMINFREQ / 64);
790 else
791 return max_freq ? (XTALMAXFREQ / 32)
792 : (XTALMINFREQ / 32);
793 } else if (ai_get_ccrev(sih) < 10) {
794 div = 4 *
795 (((bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
796 SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
797 if (slowclk == SCC_SS_LPO)
798 return max_freq ? LPOMAXFREQ : LPOMINFREQ;
799 else if (slowclk == SCC_SS_XTAL)
800 return max_freq ? (XTALMAXFREQ / div)
801 : (XTALMINFREQ / div);
802 else if (slowclk == SCC_SS_PCI)
803 return max_freq ? (PCIMAXFREQ / div)
804 : (PCIMINFREQ / div);
805 } else {
806 /* Chipc rev 10 is InstaClock */
807 div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
808 div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
809 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
810 }
811 return 0;
812} 663}
813 664
814static void 665static void
@@ -831,8 +682,7 @@ ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc)
831 682
832 /* Starting with 4318 it is ILP that is used for the delays */ 683 /* Starting with 4318 it is ILP that is used for the delays */
833 slowmaxfreq = 684 slowmaxfreq =
834 ai_slowclk_freq(sih, 685 ai_slowclk_freq(sih, false, cc);
835 (ai_get_ccrev(sih) >= 10) ? false : true, cc);
836 686
837 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; 687 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
838 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; 688 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
@@ -854,9 +704,8 @@ void ai_clkctl_init(struct si_pub *sih)
854 return; 704 return;
855 705
856 /* set all Instaclk chip ILP to 1 MHz */ 706 /* set all Instaclk chip ILP to 1 MHz */
857 if (ai_get_ccrev(sih) >= 10) 707 bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
858 bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK, 708 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
859 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
860 709
861 ai_clkctl_setdelay(sih, cc); 710 ai_clkctl_setdelay(sih, cc);
862} 711}
@@ -891,140 +740,6 @@ u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
891 return fpdelay; 740 return fpdelay;
892} 741}
893 742
894/* turn primary xtal and/or pll off/on */
895int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
896{
897 struct si_info *sii;
898 u32 in, out, outen;
899
900 sii = (struct si_info *)sih;
901
902 /* pcie core doesn't have any mapping to control the xtal pu */
903 if (PCIE(sih))
904 return -1;
905
906 pci_read_config_dword(sii->pcibus, PCI_GPIO_IN, &in);
907 pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT, &out);
908 pci_read_config_dword(sii->pcibus, PCI_GPIO_OUTEN, &outen);
909
910 /*
911 * Avoid glitching the clock if GPRS is already using it.
912 * We can't actually read the state of the PLLPD so we infer it
913 * by the value of XTAL_PU which *is* readable via gpioin.
914 */
915 if (on && (in & PCI_CFG_GPIO_XTAL))
916 return 0;
917
918 if (what & XTAL)
919 outen |= PCI_CFG_GPIO_XTAL;
920 if (what & PLL)
921 outen |= PCI_CFG_GPIO_PLL;
922
923 if (on) {
924 /* turn primary xtal on */
925 if (what & XTAL) {
926 out |= PCI_CFG_GPIO_XTAL;
927 if (what & PLL)
928 out |= PCI_CFG_GPIO_PLL;
929 pci_write_config_dword(sii->pcibus,
930 PCI_GPIO_OUT, out);
931 pci_write_config_dword(sii->pcibus,
932 PCI_GPIO_OUTEN, outen);
933 udelay(XTAL_ON_DELAY);
934 }
935
936 /* turn pll on */
937 if (what & PLL) {
938 out &= ~PCI_CFG_GPIO_PLL;
939 pci_write_config_dword(sii->pcibus,
940 PCI_GPIO_OUT, out);
941 mdelay(2);
942 }
943 } else {
944 if (what & XTAL)
945 out &= ~PCI_CFG_GPIO_XTAL;
946 if (what & PLL)
947 out |= PCI_CFG_GPIO_PLL;
948 pci_write_config_dword(sii->pcibus,
949 PCI_GPIO_OUT, out);
950 pci_write_config_dword(sii->pcibus,
951 PCI_GPIO_OUTEN, outen);
952 }
953
954 return 0;
955}
956
957/* clk control mechanism through chipcommon, no policy checking */
958static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
959{
960 struct bcma_device *cc;
961 u32 scc;
962
963 /* chipcommon cores prior to rev6 don't support dynamic clock control */
964 if (ai_get_ccrev(&sii->pub) < 6)
965 return false;
966
967 cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
968
969 if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) &&
970 (ai_get_ccrev(&sii->pub) < 20))
971 return mode == CLK_FAST;
972
973 switch (mode) {
974 case CLK_FAST: /* FORCEHT, fast (pll) clock */
975 if (ai_get_ccrev(&sii->pub) < 10) {
976 /*
977 * don't forget to force xtal back
978 * on before we clear SCC_DYN_XTAL..
979 */
980 ai_clkctl_xtal(&sii->pub, XTAL, ON);
981 bcma_maskset32(cc, CHIPCREGOFFS(slow_clk_ctl),
982 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
983 } else if (ai_get_ccrev(&sii->pub) < 20) {
984 bcma_set32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_HR);
985 } else {
986 bcma_set32(cc, CHIPCREGOFFS(clk_ctl_st), CCS_FORCEHT);
987 }
988
989 /* wait for the PLL */
990 if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
991 u32 htavail = CCS_HTAVAIL;
992 SPINWAIT(((bcma_read32(cc, CHIPCREGOFFS(clk_ctl_st)) &
993 htavail) == 0), PMU_MAX_TRANSITION_DLY);
994 } else {
995 udelay(PLL_DELAY);
996 }
997 break;
998
999 case CLK_DYNAMIC: /* enable dynamic clock control */
1000 if (ai_get_ccrev(&sii->pub) < 10) {
1001 scc = bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl));
1002 scc &= ~(SCC_FS | SCC_IP | SCC_XC);
1003 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
1004 scc |= SCC_XC;
1005 bcma_write32(cc, CHIPCREGOFFS(slow_clk_ctl), scc);
1006
1007 /*
1008 * for dynamic control, we have to
1009 * release our xtal_pu "force on"
1010 */
1011 if (scc & SCC_XC)
1012 ai_clkctl_xtal(&sii->pub, XTAL, OFF);
1013 } else if (ai_get_ccrev(&sii->pub) < 20) {
1014 /* Instaclock */
1015 bcma_mask32(cc, CHIPCREGOFFS(system_clk_ctl), ~SYCC_HR);
1016 } else {
1017 bcma_mask32(cc, CHIPCREGOFFS(clk_ctl_st), ~CCS_FORCEHT);
1018 }
1019 break;
1020
1021 default:
1022 break;
1023 }
1024
1025 return mode == CLK_FAST;
1026}
1027
1028/* 743/*
1029 * clock control policy function throught chipcommon 744 * clock control policy function throught chipcommon
1030 * 745 *
@@ -1033,133 +748,53 @@ static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
1033 * this is a wrapper over the next internal function 748 * this is a wrapper over the next internal function
1034 * to allow flexible policy settings for outside caller 749 * to allow flexible policy settings for outside caller
1035 */ 750 */
1036bool ai_clkctl_cc(struct si_pub *sih, uint mode) 751bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode)
1037{ 752{
1038 struct si_info *sii; 753 struct si_info *sii;
754 struct bcma_device *cc;
1039 755
1040 sii = (struct si_info *)sih; 756 sii = (struct si_info *)sih;
1041 757
1042 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1043 if (ai_get_ccrev(sih) < 6)
1044 return false;
1045
1046 if (PCI_FORCEHT(sih)) 758 if (PCI_FORCEHT(sih))
1047 return mode == CLK_FAST; 759 return mode == BCMA_CLKMODE_FAST;
1048 760
1049 return _ai_clkctl_cc(sii, mode); 761 cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
762 bcma_core_set_clockmode(cc, mode);
763 return mode == BCMA_CLKMODE_FAST;
1050} 764}
1051 765
1052void ai_pci_up(struct si_pub *sih) 766void ai_pci_up(struct si_pub *sih)
1053{ 767{
1054 struct si_info *sii; 768 struct si_info *sii;
769 struct bcma_device *cc;
1055 770
1056 sii = (struct si_info *)sih; 771 sii = (struct si_info *)sih;
1057 772
1058 if (PCI_FORCEHT(sih)) 773 if (PCI_FORCEHT(sih)) {
1059 _ai_clkctl_cc(sii, CLK_FAST); 774 cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
775 bcma_core_set_clockmode(cc, BCMA_CLKMODE_FAST);
776 }
1060 777
1061 if (PCIE(sih)) 778 if (PCIE(sih))
1062 pcicore_up(sii->pch, SI_PCIUP); 779 bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
1063
1064}
1065
1066/* Unconfigure and/or apply various WARs when system is going to sleep mode */
1067void ai_pci_sleep(struct si_pub *sih)
1068{
1069 struct si_info *sii;
1070
1071 sii = (struct si_info *)sih;
1072
1073 pcicore_sleep(sii->pch);
1074} 780}
1075 781
1076/* Unconfigure and/or apply various WARs when going down */ 782/* Unconfigure and/or apply various WARs when going down */
1077void ai_pci_down(struct si_pub *sih) 783void ai_pci_down(struct si_pub *sih)
1078{ 784{
1079 struct si_info *sii; 785 struct si_info *sii;
786 struct bcma_device *cc;
1080 787
1081 sii = (struct si_info *)sih; 788 sii = (struct si_info *)sih;
1082 789
1083 /* release FORCEHT since chip is going to "down" state */ 790 /* release FORCEHT since chip is going to "down" state */
1084 if (PCI_FORCEHT(sih)) 791 if (PCI_FORCEHT(sih)) {
1085 _ai_clkctl_cc(sii, CLK_DYNAMIC); 792 cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
1086 793 bcma_core_set_clockmode(cc, BCMA_CLKMODE_DYNAMIC);
1087 pcicore_down(sii->pch, SI_PCIDOWN);
1088}
1089
1090/*
1091 * Configure the pci core for pci client (NIC) action
1092 * coremask is the bitvec of cores by index to be enabled.
1093 */
1094void ai_pci_setup(struct si_pub *sih, uint coremask)
1095{
1096 struct si_info *sii;
1097 u32 w;
1098
1099 sii = (struct si_info *)sih;
1100
1101 /*
1102 * Enable sb->pci interrupts. Assume
1103 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1104 */
1105 if (PCIE(sih) || (PCI(sih) && (ai_get_buscorerev(sih) >= 6))) {
1106 /* pci config write to set this core bit in PCIIntMask */
1107 pci_read_config_dword(sii->pcibus, PCI_INT_MASK, &w);
1108 w |= (coremask << PCI_SBIM_SHIFT);
1109 pci_write_config_dword(sii->pcibus, PCI_INT_MASK, w);
1110 }
1111
1112 if (PCI(sih)) {
1113 pcicore_pci_setup(sii->pch);
1114 } 794 }
1115}
1116 795
1117/* 796 if (PCIE(sih))
1118 * Fixup SROMless PCI device's configuration. 797 bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
1119 * The current core may be changed upon return.
1120 */
1121int ai_pci_fixcfg(struct si_pub *sih)
1122{
1123 struct si_info *sii = (struct si_info *)sih;
1124
1125 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
1126 /* check 'pi' is correct and fix it if not */
1127 pcicore_fixcfg(sii->pch);
1128 pcicore_hwup(sii->pch);
1129 return 0;
1130}
1131
1132/* mask&set gpiocontrol bits */
1133u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
1134{
1135 uint regoff;
1136
1137 regoff = offsetof(struct chipcregs, gpiocontrol);
1138 return ai_cc_reg(sih, regoff, mask, val);
1139}
1140
1141void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
1142{
1143 struct bcma_device *cc;
1144 u32 val;
1145
1146 cc = ai_findcore(sih, CC_CORE_ID, 0);
1147
1148 if (on) {
1149 if (ai_get_chippkg(sih) == 9 || ai_get_chippkg(sih) == 0xb)
1150 /* Ext PA Controls for 4331 12x9 Package */
1151 bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
1152 CCTRL4331_EXTPA_EN |
1153 CCTRL4331_EXTPA_ON_GPIO2_5);
1154 else
1155 /* Ext PA Controls for 4331 12x12 Package */
1156 bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
1157 CCTRL4331_EXTPA_EN);
1158 } else {
1159 val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
1160 bcma_mask32(cc, CHIPCREGOFFS(chipcontrol),
1161 ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5));
1162 }
1163} 798}
1164 799
1165/* Enable BT-COEX & Ex-PA for 4313 */ 800/* Enable BT-COEX & Ex-PA for 4313 */
@@ -1181,6 +816,9 @@ bool ai_deviceremoved(struct si_pub *sih)
1181 816
1182 sii = (struct si_info *)sih; 817 sii = (struct si_info *)sih;
1183 818
819 if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI)
820 return false;
821
1184 pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w); 822 pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w);
1185 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM) 823 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
1186 return true; 824 return true;
@@ -1188,45 +826,6 @@ bool ai_deviceremoved(struct si_pub *sih)
1188 return false; 826 return false;
1189} 827}
1190 828
1191bool ai_is_sprom_available(struct si_pub *sih)
1192{
1193 struct si_info *sii = (struct si_info *)sih;
1194
1195 if (ai_get_ccrev(sih) >= 31) {
1196 struct bcma_device *cc;
1197 u32 sromctrl;
1198
1199 if ((ai_get_cccaps(sih) & CC_CAP_SROM) == 0)
1200 return false;
1201
1202 cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
1203 sromctrl = bcma_read32(cc, CHIPCREGOFFS(sromcontrol));
1204 return sromctrl & SRC_PRESENT;
1205 }
1206
1207 switch (ai_get_chip_id(sih)) {
1208 case BCM4313_CHIP_ID:
1209 return (sii->chipst & CST4313_SPROM_PRESENT) != 0;
1210 default:
1211 return true;
1212 }
1213}
1214
1215bool ai_is_otp_disabled(struct si_pub *sih)
1216{
1217 struct si_info *sii = (struct si_info *)sih;
1218
1219 switch (ai_get_chip_id(sih)) {
1220 case BCM4313_CHIP_ID:
1221 return (sii->chipst & CST4313_OTP_PRESENT) == 0;
1222 /* These chips always have their OTP on */
1223 case BCM43224_CHIP_ID:
1224 case BCM43225_CHIP_ID:
1225 default:
1226 return false;
1227 }
1228}
1229
1230uint ai_get_buscoretype(struct si_pub *sih) 829uint ai_get_buscoretype(struct si_pub *sih)
1231{ 830{
1232 struct si_info *sii = (struct si_info *)sih; 831 struct si_info *sii = (struct si_info *)sih;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
index f84c6f781692..d9f04a683bdb 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
@@ -113,10 +113,6 @@
113#define XTAL 0x1 /* primary crystal oscillator (2050) */ 113#define XTAL 0x1 /* primary crystal oscillator (2050) */
114#define PLL 0x2 /* main chip pll */ 114#define PLL 0x2 /* main chip pll */
115 115
116/* clkctl clk mode */
117#define CLK_FAST 0 /* force fast (pll) clock */
118#define CLK_DYNAMIC 2 /* enable dynamic clock control */
119
120/* GPIO usage priorities */ 116/* GPIO usage priorities */
121#define GPIO_DRV_PRIORITY 0 /* Driver */ 117#define GPIO_DRV_PRIORITY 0 /* Driver */
122#define GPIO_APP_PRIORITY 1 /* Application */ 118#define GPIO_APP_PRIORITY 1 /* Application */
@@ -172,9 +168,7 @@ struct si_info {
172 struct si_pub pub; /* back plane public state (must be first) */ 168 struct si_pub pub; /* back plane public state (must be first) */
173 struct bcma_bus *icbus; /* handle to soc interconnect bus */ 169 struct bcma_bus *icbus; /* handle to soc interconnect bus */
174 struct pci_dev *pcibus; /* handle to pci bus */ 170 struct pci_dev *pcibus; /* handle to pci bus */
175 struct pcicore_info *pch; /* PCI/E core handle */
176 struct bcma_device *buscore; 171 struct bcma_device *buscore;
177 struct list_head var_list; /* list of srom variables */
178 172
179 u32 chipst; /* chip status */ 173 u32 chipst; /* chip status */
180}; 174};
@@ -197,38 +191,20 @@ extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
197extern struct si_pub *ai_attach(struct bcma_bus *pbus); 191extern struct si_pub *ai_attach(struct bcma_bus *pbus);
198extern void ai_detach(struct si_pub *sih); 192extern void ai_detach(struct si_pub *sih);
199extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val); 193extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
200extern void ai_pci_setup(struct si_pub *sih, uint coremask);
201extern void ai_clkctl_init(struct si_pub *sih); 194extern void ai_clkctl_init(struct si_pub *sih);
202extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih); 195extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
203extern bool ai_clkctl_cc(struct si_pub *sih, uint mode); 196extern bool ai_clkctl_cc(struct si_pub *sih, uint mode);
204extern int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on);
205extern bool ai_deviceremoved(struct si_pub *sih); 197extern bool ai_deviceremoved(struct si_pub *sih);
206extern u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val,
207 u8 priority);
208
209/* OTP status */
210extern bool ai_is_otp_disabled(struct si_pub *sih);
211
212/* SPROM availability */
213extern bool ai_is_sprom_available(struct si_pub *sih);
214 198
215extern void ai_pci_sleep(struct si_pub *sih);
216extern void ai_pci_down(struct si_pub *sih); 199extern void ai_pci_down(struct si_pub *sih);
217extern void ai_pci_up(struct si_pub *sih); 200extern void ai_pci_up(struct si_pub *sih);
218extern int ai_pci_fixcfg(struct si_pub *sih);
219 201
220extern void ai_chipcontrl_epa4331(struct si_pub *sih, bool on);
221/* Enable Ex-PA for 4313 */ 202/* Enable Ex-PA for 4313 */
222extern void ai_epa_4313war(struct si_pub *sih); 203extern void ai_epa_4313war(struct si_pub *sih);
223 204
224extern uint ai_get_buscoretype(struct si_pub *sih); 205extern uint ai_get_buscoretype(struct si_pub *sih);
225extern uint ai_get_buscorerev(struct si_pub *sih); 206extern uint ai_get_buscorerev(struct si_pub *sih);
226 207
227static inline int ai_get_ccrev(struct si_pub *sih)
228{
229 return sih->ccrev;
230}
231
232static inline u32 ai_get_cccaps(struct si_pub *sih) 208static inline u32 ai_get_cccaps(struct si_pub *sih)
233{ 209{
234 return sih->cccaps; 210 return sih->cccaps;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/antsel.c b/drivers/net/wireless/brcm80211/brcmsmac/antsel.c
index a47ce25cb9a2..55e12c327911 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/antsel.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/antsel.c
@@ -108,7 +108,7 @@ brcms_c_antsel_init_cfg(struct antsel_info *asi, struct brcms_antselcfg *antsel,
108struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc) 108struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc)
109{ 109{
110 struct antsel_info *asi; 110 struct antsel_info *asi;
111 struct si_pub *sih = wlc->hw->sih; 111 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
112 112
113 asi = kzalloc(sizeof(struct antsel_info), GFP_ATOMIC); 113 asi = kzalloc(sizeof(struct antsel_info), GFP_ATOMIC);
114 if (!asi) 114 if (!asi)
@@ -118,7 +118,7 @@ struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc)
118 asi->pub = wlc->pub; 118 asi->pub = wlc->pub;
119 asi->antsel_type = ANTSEL_NA; 119 asi->antsel_type = ANTSEL_NA;
120 asi->antsel_avail = false; 120 asi->antsel_avail = false;
121 asi->antsel_antswitch = (u8) getintvar(sih, BRCMS_SROM_ANTSWITCH); 121 asi->antsel_antswitch = sprom->antswitch;
122 122
123 if ((asi->pub->sromrev >= 4) && (asi->antsel_antswitch != 0)) { 123 if ((asi->pub->sromrev >= 4) && (asi->antsel_antswitch != 0)) {
124 switch (asi->antsel_antswitch) { 124 switch (asi->antsel_antswitch) {
@@ -128,12 +128,12 @@ struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc)
128 /* 4321/2 board with 2x3 switch logic */ 128 /* 4321/2 board with 2x3 switch logic */
129 asi->antsel_type = ANTSEL_2x3; 129 asi->antsel_type = ANTSEL_2x3;
130 /* Antenna selection availability */ 130 /* Antenna selection availability */
131 if (((u16) getintvar(sih, BRCMS_SROM_AA2G) == 7) || 131 if ((sprom->ant_available_bg == 7) ||
132 ((u16) getintvar(sih, BRCMS_SROM_AA5G) == 7)) { 132 (sprom->ant_available_a == 7)) {
133 asi->antsel_avail = true; 133 asi->antsel_avail = true;
134 } else if ( 134 } else if (
135 (u16) getintvar(sih, BRCMS_SROM_AA2G) == 3 || 135 sprom->ant_available_bg == 3 ||
136 (u16) getintvar(sih, BRCMS_SROM_AA5G) == 3) { 136 sprom->ant_available_a == 3) {
137 asi->antsel_avail = false; 137 asi->antsel_avail = false;
138 } else { 138 } else {
139 asi->antsel_avail = false; 139 asi->antsel_avail = false;
@@ -146,8 +146,8 @@ struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc)
146 break; 146 break;
147 } 147 }
148 } else if ((asi->pub->sromrev == 4) && 148 } else if ((asi->pub->sromrev == 4) &&
149 ((u16) getintvar(sih, BRCMS_SROM_AA2G) == 7) && 149 (sprom->ant_available_bg == 7) &&
150 ((u16) getintvar(sih, BRCMS_SROM_AA5G) == 0)) { 150 (sprom->ant_available_a == 0)) {
151 /* hack to match old 4321CB2 cards with 2of3 antenna switch */ 151 /* hack to match old 4321CB2 cards with 2of3 antenna switch */
152 asi->antsel_type = ANTSEL_2x3; 152 asi->antsel_type = ANTSEL_2x3;
153 asi->antsel_avail = true; 153 asi->antsel_avail = true;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/channel.c b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
index 0efe88e25a9a..eb77ac3cfb6b 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/channel.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/channel.c
@@ -1110,7 +1110,7 @@ struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc)
1110 char country_abbrev[BRCM_CNTRY_BUF_SZ]; 1110 char country_abbrev[BRCM_CNTRY_BUF_SZ];
1111 const struct country_info *country; 1111 const struct country_info *country;
1112 struct brcms_pub *pub = wlc->pub; 1112 struct brcms_pub *pub = wlc->pub;
1113 char *ccode; 1113 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
1114 1114
1115 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit); 1115 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
1116 1116
@@ -1122,9 +1122,8 @@ struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc)
1122 wlc->cmi = wlc_cm; 1122 wlc->cmi = wlc_cm;
1123 1123
1124 /* store the country code for passing up as a regulatory hint */ 1124 /* store the country code for passing up as a regulatory hint */
1125 ccode = getvar(wlc->hw->sih, BRCMS_SROM_CCODE); 1125 if (sprom->alpha2 && brcms_c_country_valid(sprom->alpha2))
1126 if (ccode && brcms_c_country_valid(ccode)) 1126 strncpy(wlc->pub->srom_ccode, sprom->alpha2, sizeof(sprom->alpha2));
1127 strncpy(wlc->pub->srom_ccode, ccode, BRCM_CNTRY_BUF_SZ - 1);
1128 1127
1129 /* 1128 /*
1130 * internal country information which must match 1129 * internal country information which must match
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
index aa15558f75c8..50f92a0b7c41 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
@@ -25,7 +25,6 @@
25#include <linux/bcma/bcma.h> 25#include <linux/bcma/bcma.h>
26#include <net/mac80211.h> 26#include <net/mac80211.h>
27#include <defs.h> 27#include <defs.h>
28#include "nicpci.h"
29#include "phy/phy_int.h" 28#include "phy/phy_int.h"
30#include "d11.h" 29#include "d11.h"
31#include "channel.h" 30#include "channel.h"
@@ -770,7 +769,7 @@ void brcms_dpc(unsigned long data)
770 * Precondition: Since this function is called in brcms_pci_probe() context, 769 * Precondition: Since this function is called in brcms_pci_probe() context,
771 * no locking is required. 770 * no locking is required.
772 */ 771 */
773static int brcms_request_fw(struct brcms_info *wl, struct pci_dev *pdev) 772static int brcms_request_fw(struct brcms_info *wl, struct bcma_device *pdev)
774{ 773{
775 int status; 774 int status;
776 struct device *device = &pdev->dev; 775 struct device *device = &pdev->dev;
@@ -1022,7 +1021,7 @@ static struct brcms_info *brcms_attach(struct bcma_device *pdev)
1022 spin_lock_init(&wl->isr_lock); 1021 spin_lock_init(&wl->isr_lock);
1023 1022
1024 /* prepare ucode */ 1023 /* prepare ucode */
1025 if (brcms_request_fw(wl, pdev->bus->host_pci) < 0) { 1024 if (brcms_request_fw(wl, pdev) < 0) {
1026 wiphy_err(wl->wiphy, "%s: Failed to find firmware usually in " 1025 wiphy_err(wl->wiphy, "%s: Failed to find firmware usually in "
1027 "%s\n", KBUILD_MODNAME, "/lib/firmware/brcm"); 1026 "%s\n", KBUILD_MODNAME, "/lib/firmware/brcm");
1028 brcms_release_fw(wl); 1027 brcms_release_fw(wl);
@@ -1043,12 +1042,12 @@ static struct brcms_info *brcms_attach(struct bcma_device *pdev)
1043 wl->pub->ieee_hw = hw; 1042 wl->pub->ieee_hw = hw;
1044 1043
1045 /* register our interrupt handler */ 1044 /* register our interrupt handler */
1046 if (request_irq(pdev->bus->host_pci->irq, brcms_isr, 1045 if (request_irq(pdev->irq, brcms_isr,
1047 IRQF_SHARED, KBUILD_MODNAME, wl)) { 1046 IRQF_SHARED, KBUILD_MODNAME, wl)) {
1048 wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit); 1047 wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit);
1049 goto fail; 1048 goto fail;
1050 } 1049 }
1051 wl->irq = pdev->bus->host_pci->irq; 1050 wl->irq = pdev->irq;
1052 1051
1053 /* register module */ 1052 /* register module */
1054 brcms_c_module_register(wl->pub, "linux", wl, NULL); 1053 brcms_c_module_register(wl->pub, "linux", wl, NULL);
@@ -1098,7 +1097,7 @@ static int __devinit brcms_bcma_probe(struct bcma_device *pdev)
1098 1097
1099 dev_info(&pdev->dev, "mfg %x core %x rev %d class %d irq %d\n", 1098 dev_info(&pdev->dev, "mfg %x core %x rev %d class %d irq %d\n",
1100 pdev->id.manuf, pdev->id.id, pdev->id.rev, pdev->id.class, 1099 pdev->id.manuf, pdev->id.id, pdev->id.rev, pdev->id.class,
1101 pdev->bus->host_pci->irq); 1100 pdev->irq);
1102 1101
1103 if ((pdev->id.manuf != BCMA_MANUF_BCM) || 1102 if ((pdev->id.manuf != BCMA_MANUF_BCM) ||
1104 (pdev->id.id != BCMA_CORE_80211)) 1103 (pdev->id.id != BCMA_CORE_80211))
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/main.c b/drivers/net/wireless/brcm80211/brcmsmac/main.c
index b4d92792c502..19db4052c44c 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
@@ -1219,7 +1219,7 @@ static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1219} 1219}
1220 1220
1221/* control chip clock to save power, enable dynamic clock or force fast clock */ 1221/* control chip clock to save power, enable dynamic clock or force fast clock */
1222static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode) 1222static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1223{ 1223{
1224 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) { 1224 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1225 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock 1225 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
@@ -1229,7 +1229,7 @@ static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
1229 */ 1229 */
1230 1230
1231 if (wlc_hw->clk) { 1231 if (wlc_hw->clk) {
1232 if (mode == CLK_FAST) { 1232 if (mode == BCMA_CLKMODE_FAST) {
1233 bcma_set32(wlc_hw->d11core, 1233 bcma_set32(wlc_hw->d11core,
1234 D11REGOFFS(clk_ctl_st), 1234 D11REGOFFS(clk_ctl_st),
1235 CCS_FORCEHT); 1235 CCS_FORCEHT);
@@ -1260,7 +1260,7 @@ static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
1260 ~CCS_FORCEHT); 1260 ~CCS_FORCEHT);
1261 } 1261 }
1262 } 1262 }
1263 wlc_hw->forcefastclk = (mode == CLK_FAST); 1263 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1264 } else { 1264 } else {
1265 1265
1266 /* old chips w/o PMU, force HT through cc, 1266 /* old chips w/o PMU, force HT through cc,
@@ -1567,7 +1567,7 @@ void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1567 /* request FAST clock if not on */ 1567 /* request FAST clock if not on */
1568 fastclk = wlc_hw->forcefastclk; 1568 fastclk = wlc_hw->forcefastclk;
1569 if (!fastclk) 1569 if (!fastclk)
1570 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 1570 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1571 1571
1572 wlc_phy_bw_state_set(wlc_hw->band->pi, bw); 1572 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1573 1573
@@ -1576,7 +1576,7 @@ void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1576 1576
1577 /* restore the clk */ 1577 /* restore the clk */
1578 if (!fastclk) 1578 if (!fastclk)
1579 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 1579 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1580} 1580}
1581 1581
1582static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw) 1582static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
@@ -1882,27 +1882,20 @@ static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1882 return true; 1882 return true;
1883} 1883}
1884 1884
1885static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw) 1885static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1886{ 1886{
1887 enum brcms_srom_id var_id = BRCMS_SROM_MACADDR; 1887 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1888 char *macaddr;
1889 1888
1890 /* If macaddr exists, use it (Sromrev4, CIS, ...). */ 1889 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1891 macaddr = getvar(wlc_hw->sih, var_id); 1890 if (!is_zero_ether_addr(sprom->il0mac)) {
1892 if (macaddr != NULL) 1891 memcpy(etheraddr, sprom->il0mac, 6);
1893 return macaddr; 1892 return;
1893 }
1894 1894
1895 if (wlc_hw->_nbands > 1) 1895 if (wlc_hw->_nbands > 1)
1896 var_id = BRCMS_SROM_ET1MACADDR; 1896 memcpy(etheraddr, sprom->et1mac, 6);
1897 else 1897 else
1898 var_id = BRCMS_SROM_IL0MACADDR; 1898 memcpy(etheraddr, sprom->il0mac, 6);
1899
1900 macaddr = getvar(wlc_hw->sih, var_id);
1901 if (macaddr == NULL)
1902 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
1903 "getvar(%d) not found\n", wlc_hw->unit, var_id);
1904
1905 return macaddr;
1906} 1899}
1907 1900
1908/* power both the pll and external oscillator on/off */ 1901/* power both the pll and external oscillator on/off */
@@ -1917,9 +1910,6 @@ static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1917 if (!want && wlc_hw->pllreq) 1910 if (!want && wlc_hw->pllreq)
1918 return; 1911 return;
1919 1912
1920 if (wlc_hw->sih)
1921 ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
1922
1923 wlc_hw->sbclk = want; 1913 wlc_hw->sbclk = want;
1924 if (!wlc_hw->sbclk) { 1914 if (!wlc_hw->sbclk) {
1925 wlc_hw->clk = false; 1915 wlc_hw->clk = false;
@@ -2004,7 +1994,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2004 /* request FAST clock if not on */ 1994 /* request FAST clock if not on */
2005 fastclk = wlc_hw->forcefastclk; 1995 fastclk = wlc_hw->forcefastclk;
2006 if (!fastclk) 1996 if (!fastclk)
2007 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 1997 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2008 1998
2009 /* reset the dma engines except first time thru */ 1999 /* reset the dma engines except first time thru */
2010 if (bcma_core_is_enabled(wlc_hw->d11core)) { 2000 if (bcma_core_is_enabled(wlc_hw->d11core)) {
@@ -2053,7 +2043,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2053 brcms_c_mctrl_reset(wlc_hw); 2043 brcms_c_mctrl_reset(wlc_hw);
2054 2044
2055 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) 2045 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2056 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 2046 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2057 2047
2058 brcms_b_phy_reset(wlc_hw); 2048 brcms_b_phy_reset(wlc_hw);
2059 2049
@@ -2065,7 +2055,7 @@ void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2065 2055
2066 /* restore the clk setting */ 2056 /* restore the clk setting */
2067 if (!fastclk) 2057 if (!fastclk)
2068 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 2058 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2069} 2059}
2070 2060
2071/* txfifo sizes needs to be modified(increased) since the newer cores 2061/* txfifo sizes needs to be modified(increased) since the newer cores
@@ -2218,7 +2208,7 @@ static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2218 gm |= gc |= BOARD_GPIO_PACTRL; 2208 gm |= gc |= BOARD_GPIO_PACTRL;
2219 2209
2220 /* apply to gpiocontrol register */ 2210 /* apply to gpiocontrol register */
2221 ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY); 2211 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2222} 2212}
2223 2213
2224static void brcms_ucode_write(struct brcms_hardware *wlc_hw, 2214static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
@@ -3371,7 +3361,7 @@ static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3371 /* request FAST clock if not on */ 3361 /* request FAST clock if not on */
3372 fastclk = wlc_hw->forcefastclk; 3362 fastclk = wlc_hw->forcefastclk;
3373 if (!fastclk) 3363 if (!fastclk)
3374 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 3364 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3375 3365
3376 /* disable interrupts */ 3366 /* disable interrupts */
3377 macintmask = brcms_intrsoff(wlc->wl); 3367 macintmask = brcms_intrsoff(wlc->wl);
@@ -3405,7 +3395,7 @@ static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3405 3395
3406 /* restore the clk */ 3396 /* restore the clk */
3407 if (!fastclk) 3397 if (!fastclk)
3408 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 3398 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3409} 3399}
3410 3400
3411static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc, 3401static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
@@ -4436,17 +4426,22 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4436 uint unit, bool piomode) 4426 uint unit, bool piomode)
4437{ 4427{
4438 struct brcms_hardware *wlc_hw; 4428 struct brcms_hardware *wlc_hw;
4439 char *macaddr = NULL;
4440 uint err = 0; 4429 uint err = 0;
4441 uint j; 4430 uint j;
4442 bool wme = false; 4431 bool wme = false;
4443 struct shared_phy_params sha_params; 4432 struct shared_phy_params sha_params;
4444 struct wiphy *wiphy = wlc->wiphy; 4433 struct wiphy *wiphy = wlc->wiphy;
4445 struct pci_dev *pcidev = core->bus->host_pci; 4434 struct pci_dev *pcidev = core->bus->host_pci;
4435 struct ssb_sprom *sprom = &core->bus->sprom;
4446 4436
4447 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, 4437 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4448 pcidev->vendor, 4438 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4449 pcidev->device); 4439 pcidev->vendor,
4440 pcidev->device);
4441 else
4442 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4443 core->bus->boardinfo.vendor,
4444 core->bus->boardinfo.type);
4450 4445
4451 wme = true; 4446 wme = true;
4452 4447
@@ -4472,7 +4467,8 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4472 } 4467 }
4473 4468
4474 /* verify again the device is supported */ 4469 /* verify again the device is supported */
4475 if (!brcms_c_chipmatch(pcidev->vendor, pcidev->device)) { 4470 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI &&
4471 !brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
4476 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported " 4472 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
4477 "vendor/device (0x%x/0x%x)\n", 4473 "vendor/device (0x%x/0x%x)\n",
4478 unit, pcidev->vendor, pcidev->device); 4474 unit, pcidev->vendor, pcidev->device);
@@ -4480,8 +4476,13 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4480 goto fail; 4476 goto fail;
4481 } 4477 }
4482 4478
4483 wlc_hw->vendorid = pcidev->vendor; 4479 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4484 wlc_hw->deviceid = pcidev->device; 4480 wlc_hw->vendorid = pcidev->vendor;
4481 wlc_hw->deviceid = pcidev->device;
4482 } else {
4483 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4484 wlc_hw->deviceid = core->bus->boardinfo.type;
4485 }
4485 4486
4486 wlc_hw->d11core = core; 4487 wlc_hw->d11core = core;
4487 wlc_hw->corerev = core->id.rev; 4488 wlc_hw->corerev = core->id.rev;
@@ -4501,7 +4502,7 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4501 * is still false; But it will be called again inside wlc_corereset, 4502 * is still false; But it will be called again inside wlc_corereset,
4502 * after d11 is out of reset. 4503 * after d11 is out of reset.
4503 */ 4504 */
4504 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 4505 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4505 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS); 4506 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4506 4507
4507 if (!brcms_b_validate_chip_access(wlc_hw)) { 4508 if (!brcms_b_validate_chip_access(wlc_hw)) {
@@ -4512,7 +4513,7 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4512 } 4513 }
4513 4514
4514 /* get the board rev, used just below */ 4515 /* get the board rev, used just below */
4515 j = getintvar(wlc_hw->sih, BRCMS_SROM_BOARDREV); 4516 j = sprom->board_rev;
4516 /* promote srom boardrev of 0xFF to 1 */ 4517 /* promote srom boardrev of 0xFF to 1 */
4517 if (j == BOARDREV_PROMOTABLE) 4518 if (j == BOARDREV_PROMOTABLE)
4518 j = BOARDREV_PROMOTED; 4519 j = BOARDREV_PROMOTED;
@@ -4525,11 +4526,9 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4525 err = 15; 4526 err = 15;
4526 goto fail; 4527 goto fail;
4527 } 4528 }
4528 wlc_hw->sromrev = (u8) getintvar(wlc_hw->sih, BRCMS_SROM_REV); 4529 wlc_hw->sromrev = sprom->revision;
4529 wlc_hw->boardflags = (u32) getintvar(wlc_hw->sih, 4530 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4530 BRCMS_SROM_BOARDFLAGS); 4531 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4531 wlc_hw->boardflags2 = (u32) getintvar(wlc_hw->sih,
4532 BRCMS_SROM_BOARDFLAGS2);
4533 4532
4534 if (wlc_hw->boardflags & BFL_NOPLLDOWN) 4533 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4535 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED); 4534 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
@@ -4702,25 +4701,18 @@ static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4702 */ 4701 */
4703 4702
4704 /* init etheraddr state variables */ 4703 /* init etheraddr state variables */
4705 macaddr = brcms_c_get_macaddr(wlc_hw); 4704 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4706 if (macaddr == NULL) { 4705
4707 wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n", 4706 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4708 unit);
4709 err = 21;
4710 goto fail;
4711 }
4712 if (!mac_pton(macaddr, wlc_hw->etheraddr) ||
4713 is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4714 is_zero_ether_addr(wlc_hw->etheraddr)) { 4707 is_zero_ether_addr(wlc_hw->etheraddr)) {
4715 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n", 4708 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4716 unit, macaddr); 4709 unit);
4717 err = 22; 4710 err = 22;
4718 goto fail; 4711 goto fail;
4719 } 4712 }
4720 4713
4721 BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n", 4714 BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x\n",
4722 wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih), 4715 wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih));
4723 macaddr);
4724 4716
4725 return err; 4717 return err;
4726 4718
@@ -4770,16 +4762,16 @@ static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4770 int aa; 4762 int aa;
4771 uint unit; 4763 uint unit;
4772 int bandtype; 4764 int bandtype;
4773 struct si_pub *sih = wlc->hw->sih; 4765 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4774 4766
4775 unit = wlc->pub->unit; 4767 unit = wlc->pub->unit;
4776 bandtype = wlc->band->bandtype; 4768 bandtype = wlc->band->bandtype;
4777 4769
4778 /* get antennas available */ 4770 /* get antennas available */
4779 if (bandtype == BRCM_BAND_5G) 4771 if (bandtype == BRCM_BAND_5G)
4780 aa = (s8) getintvar(sih, BRCMS_SROM_AA5G); 4772 aa = sprom->ant_available_a;
4781 else 4773 else
4782 aa = (s8) getintvar(sih, BRCMS_SROM_AA2G); 4774 aa = sprom->ant_available_bg;
4783 4775
4784 if ((aa < 1) || (aa > 15)) { 4776 if ((aa < 1) || (aa > 15)) {
4785 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in" 4777 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
@@ -4799,9 +4791,9 @@ static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4799 4791
4800 /* Compute Antenna Gain */ 4792 /* Compute Antenna Gain */
4801 if (bandtype == BRCM_BAND_5G) 4793 if (bandtype == BRCM_BAND_5G)
4802 wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG1); 4794 wlc->band->antgain = sprom->antenna_gain.a1;
4803 else 4795 else
4804 wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG0); 4796 wlc->band->antgain = sprom->antenna_gain.a0;
4805 4797
4806 brcms_c_attach_antgain_init(wlc); 4798 brcms_c_attach_antgain_init(wlc);
4807 4799
@@ -4952,15 +4944,6 @@ static int brcms_b_detach(struct brcms_c_info *wlc)
4952 4944
4953 callbacks = 0; 4945 callbacks = 0;
4954 4946
4955 if (wlc_hw->sih) {
4956 /*
4957 * detach interrupt sync mechanism since interrupt is disabled
4958 * and per-port interrupt object may has been freed. this must
4959 * be done before sb core switch
4960 */
4961 ai_pci_sleep(wlc_hw->sih);
4962 }
4963
4964 brcms_b_detach_dmapio(wlc_hw); 4947 brcms_b_detach_dmapio(wlc_hw);
4965 4948
4966 band = wlc_hw->band; 4949 band = wlc_hw->band;
@@ -5047,9 +5030,7 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5047 */ 5030 */
5048 brcms_b_xtal(wlc_hw, ON); 5031 brcms_b_xtal(wlc_hw, ON);
5049 ai_clkctl_init(wlc_hw->sih); 5032 ai_clkctl_init(wlc_hw->sih);
5050 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5033 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5051
5052 ai_pci_fixcfg(wlc_hw->sih);
5053 5034
5054 /* 5035 /*
5055 * TODO: test suspend/resume 5036 * TODO: test suspend/resume
@@ -5078,8 +5059,6 @@ static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
5078 5059
5079static int brcms_b_up_prep(struct brcms_hardware *wlc_hw) 5060static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5080{ 5061{
5081 uint coremask;
5082
5083 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit); 5062 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5084 5063
5085 /* 5064 /*
@@ -5088,15 +5067,14 @@ static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5088 */ 5067 */
5089 brcms_b_xtal(wlc_hw, ON); 5068 brcms_b_xtal(wlc_hw, ON);
5090 ai_clkctl_init(wlc_hw->sih); 5069 ai_clkctl_init(wlc_hw->sih);
5091 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5070 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5092 5071
5093 /* 5072 /*
5094 * Configure pci/pcmcia here instead of in brcms_c_attach() 5073 * Configure pci/pcmcia here instead of in brcms_c_attach()
5095 * to allow mfg hotswap: down, hotswap (chip power cycle), up. 5074 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
5096 */ 5075 */
5097 coremask = (1 << wlc_hw->wlc->core->coreidx); 5076 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci, wlc_hw->d11core,
5098 5077 true);
5099 ai_pci_setup(wlc_hw->sih, coremask);
5100 5078
5101 /* 5079 /*
5102 * Need to read the hwradio status here to cover the case where the 5080 * Need to read the hwradio status here to cover the case where the
@@ -5126,7 +5104,7 @@ static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5126 wlc_phy_hw_state_upd(wlc_hw->band->pi, true); 5104 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5127 5105
5128 /* FULLY enable dynamic power control and d11 core interrupt */ 5106 /* FULLY enable dynamic power control and d11 core interrupt */
5129 brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC); 5107 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5130 brcms_intrson(wlc_hw->wlc->wl); 5108 brcms_intrson(wlc_hw->wlc->wl);
5131 return 0; 5109 return 0;
5132} 5110}
@@ -5267,7 +5245,7 @@ static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5267 brcms_intrsoff(wlc_hw->wlc->wl); 5245 brcms_intrsoff(wlc_hw->wlc->wl);
5268 5246
5269 /* ensure we're running on the pll clock again */ 5247 /* ensure we're running on the pll clock again */
5270 brcms_b_clkctl_clk(wlc_hw, CLK_FAST); 5248 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5271 } 5249 }
5272 /* down phy at the last of this stage */ 5250 /* down phy at the last of this stage */
5273 callbacks += wlc_phy_down(wlc_hw->band->pi); 5251 callbacks += wlc_phy_down(wlc_hw->band->pi);
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c b/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
deleted file mode 100644
index 7fad6dc19258..000000000000
--- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.c
+++ /dev/null
@@ -1,826 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/pci.h>
20
21#include <defs.h>
22#include <soc.h>
23#include <chipcommon.h>
24#include "aiutils.h"
25#include "pub.h"
26#include "nicpci.h"
27
28/* SPROM offsets */
29#define SRSH_ASPM_OFFSET 4 /* word 4 */
30#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
31#define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */
32#define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */
33
34#define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */
35#define SRSH_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
36#define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
37#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
38#define SRSH_BD_OFFSET 6 /* word 6 */
39
40/* chipcontrol */
41#define CHIPCTRL_4321_PLL_DOWN 0x800000/* serdes PLL down override */
42
43/* MDIO control */
44#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
45#define MDIOCTL_DIVISOR_VAL 0x2
46#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
47#define MDIOCTL_ACCESS_DONE 0x100 /* Transaction complete */
48
49/* MDIO Data */
50#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
51#define MDIODATA_TA 0x00020000 /* Turnaround */
52
53#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
54#define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
55#define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
56#define MDIODATA_DEVADDR_MASK 0x0f800000
57 /* Physmedia devaddr Mask */
58
59/* MDIO Data for older revisions < 10 */
60#define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift */
61#define MDIODATA_REGADDR_MASK_OLD 0x003c0000
62 /* Regaddr Mask */
63#define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift */
64#define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000
65 /* Physmedia devaddr Mask */
66
67/* Transactions flags */
68#define MDIODATA_WRITE 0x10000000
69#define MDIODATA_READ 0x20000000
70#define MDIODATA_START 0x40000000
71
72#define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
73#define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
74
75/* serdes regs (rev < 10) */
76#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
77#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
78#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
79
80/* SERDES RX registers */
81#define SERDES_RX_CTRL 1 /* Rx cntrl */
82#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
83#define SERDES_RX_CDR 6 /* CDR */
84#define SERDES_RX_CDRBW 7 /* CDR BW */
85/* SERDES RX control register */
86#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
87#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
88
89/* SERDES PLL registers */
90#define SERDES_PLL_CTRL 1 /* PLL control reg */
91#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
92
93/* Linkcontrol reg offset in PCIE Cap */
94#define PCIE_CAP_LINKCTRL_OFFSET 16 /* offset in pcie cap */
95#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
96#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
97#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
98
99#define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */
100#define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */
101#define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */
102#define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */
103
104/* Power management threshold */
105#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
106#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
107#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
108#define PCIE_ASPMTIMER_EXTEND 0x01000000
109 /* > rev7:
110 * enable extend ASPM timer
111 */
112
113/* different register spaces to access thru pcie indirect access */
114#define PCIE_CONFIGREGS 1 /* Access to config space */
115#define PCIE_PCIEREGS 2 /* Access to pcie registers */
116
117/* PCIE protocol PHY diagnostic registers */
118#define PCIE_PLP_STATUSREG 0x204 /* Status */
119
120/* Status reg PCIE_PLP_STATUSREG */
121#define PCIE_PLP_POLARITYINV_STAT 0x10
122
123/* PCIE protocol DLLP diagnostic registers */
124#define PCIE_DLLP_LCREG 0x100 /* Link Control */
125#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
126
127/* PCIE protocol TLP diagnostic registers */
128#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
129
130/* Sonics to PCI translation types */
131#define SBTOPCI_PREF 0x4 /* prefetch enable */
132#define SBTOPCI_BURST 0x8 /* burst enable */
133#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
134
135#define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */
136
137/* PCI core index in SROM shadow area */
138#define SRSH_PI_OFFSET 0 /* first word */
139#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
140#define SRSH_PI_SHIFT 12 /* bit 15:12 */
141
142#define PCIREGOFFS(field) offsetof(struct sbpciregs, field)
143#define PCIEREGOFFS(field) offsetof(struct sbpcieregs, field)
144
145/* Sonics side: PCI core and host control registers */
146struct sbpciregs {
147 u32 control; /* PCI control */
148 u32 PAD[3];
149 u32 arbcontrol; /* PCI arbiter control */
150 u32 clkrun; /* Clkrun Control (>=rev11) */
151 u32 PAD[2];
152 u32 intstatus; /* Interrupt status */
153 u32 intmask; /* Interrupt mask */
154 u32 sbtopcimailbox; /* Sonics to PCI mailbox */
155 u32 PAD[9];
156 u32 bcastaddr; /* Sonics broadcast address */
157 u32 bcastdata; /* Sonics broadcast data */
158 u32 PAD[2];
159 u32 gpioin; /* ro: gpio input (>=rev2) */
160 u32 gpioout; /* rw: gpio output (>=rev2) */
161 u32 gpioouten; /* rw: gpio output enable (>= rev2) */
162 u32 gpiocontrol; /* rw: gpio control (>= rev2) */
163 u32 PAD[36];
164 u32 sbtopci0; /* Sonics to PCI translation 0 */
165 u32 sbtopci1; /* Sonics to PCI translation 1 */
166 u32 sbtopci2; /* Sonics to PCI translation 2 */
167 u32 PAD[189];
168 u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
169 u16 sprom[36]; /* SPROM shadow Area */
170 u32 PAD[46];
171};
172
173/* SB side: PCIE core and host control registers */
174struct sbpcieregs {
175 u32 control; /* host mode only */
176 u32 PAD[2];
177 u32 biststatus; /* bist Status: 0x00C */
178 u32 gpiosel; /* PCIE gpio sel: 0x010 */
179 u32 gpioouten; /* PCIE gpio outen: 0x14 */
180 u32 PAD[2];
181 u32 intstatus; /* Interrupt status: 0x20 */
182 u32 intmask; /* Interrupt mask: 0x24 */
183 u32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
184 u32 PAD[53];
185 u32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
186 u32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
187 u32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
188 u32 PAD[5];
189
190 /* pcie core supports in direct access to config space */
191 u32 configaddr; /* pcie config space access: Address field: 0x120 */
192 u32 configdata; /* pcie config space access: Data field: 0x124 */
193
194 /* mdio access to serdes */
195 u32 mdiocontrol; /* controls the mdio access: 0x128 */
196 u32 mdiodata; /* Data to the mdio access: 0x12c */
197
198 /* pcie protocol phy/dllp/tlp register indirect access mechanism */
199 u32 pcieindaddr; /* indirect access to
200 * the internal register: 0x130
201 */
202 u32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
203
204 u32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
205 u32 PAD[177];
206 u32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */
207 u16 sprom[64]; /* SPROM shadow Area */
208};
209
210struct pcicore_info {
211 struct bcma_device *core;
212 struct si_pub *sih; /* System interconnect handle */
213 struct pci_dev *dev;
214 u8 pciecap_lcreg_offset;/* PCIE capability LCreg offset
215 * in the config space
216 */
217 bool pcie_pr42767;
218 u8 pcie_polarity;
219 u8 pcie_war_aspm_ovr; /* Override ASPM/Clkreq settings */
220
221 u8 pmecap_offset; /* PM Capability offset in the config space */
222 bool pmecap; /* Capable of generating PME */
223};
224
225#define PCIE_ASPM(sih) \
226 ((ai_get_buscoretype(sih) == PCIE_CORE_ID) && \
227 ((ai_get_buscorerev(sih) >= 3) && \
228 (ai_get_buscorerev(sih) <= 5)))
229
230
231/* delay needed between the mdio control/ mdiodata register data access */
232static void pr28829_delay(void)
233{
234 udelay(10);
235}
236
237/* Initialize the PCI core.
238 * It's caller's responsibility to make sure that this is done only once
239 */
240struct pcicore_info *pcicore_init(struct si_pub *sih, struct bcma_device *core)
241{
242 struct pcicore_info *pi;
243
244 /* alloc struct pcicore_info */
245 pi = kzalloc(sizeof(struct pcicore_info), GFP_ATOMIC);
246 if (pi == NULL)
247 return NULL;
248
249 pi->sih = sih;
250 pi->dev = core->bus->host_pci;
251 pi->core = core;
252
253 if (core->id.id == PCIE_CORE_ID) {
254 u8 cap_ptr;
255 cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
256 NULL, NULL);
257 pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
258 }
259 return pi;
260}
261
262void pcicore_deinit(struct pcicore_info *pch)
263{
264 kfree(pch);
265}
266
267/* return cap_offset if requested capability exists in the PCI config space */
268/* Note that it's caller's responsibility to make sure it's a pci bus */
269u8
270pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
271 unsigned char *buf, u32 *buflen)
272{
273 u8 cap_id;
274 u8 cap_ptr = 0;
275 u32 bufsize;
276 u8 byte_val;
277
278 /* check for Header type 0 */
279 pci_read_config_byte(dev, PCI_HEADER_TYPE, &byte_val);
280 if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
281 goto end;
282
283 /* check if the capability pointer field exists */
284 pci_read_config_byte(dev, PCI_STATUS, &byte_val);
285 if (!(byte_val & PCI_STATUS_CAP_LIST))
286 goto end;
287
288 pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr);
289 /* check if the capability pointer is 0x00 */
290 if (cap_ptr == 0x00)
291 goto end;
292
293 /* loop thru the capability list
294 * and see if the pcie capability exists
295 */
296
297 pci_read_config_byte(dev, cap_ptr, &cap_id);
298
299 while (cap_id != req_cap_id) {
300 pci_read_config_byte(dev, cap_ptr + 1, &cap_ptr);
301 if (cap_ptr == 0x00)
302 break;
303 pci_read_config_byte(dev, cap_ptr, &cap_id);
304 }
305 if (cap_id != req_cap_id)
306 goto end;
307
308 /* found the caller requested capability */
309 if (buf != NULL && buflen != NULL) {
310 u8 cap_data;
311
312 bufsize = *buflen;
313 if (!bufsize)
314 goto end;
315 *buflen = 0;
316 /* copy the capability data excluding cap ID and next ptr */
317 cap_data = cap_ptr + 2;
318 if ((bufsize + cap_data) > PCI_SZPCR)
319 bufsize = PCI_SZPCR - cap_data;
320 *buflen = bufsize;
321 while (bufsize--) {
322 pci_read_config_byte(dev, cap_data, buf);
323 cap_data++;
324 buf++;
325 }
326 }
327end:
328 return cap_ptr;
329}
330
331/* ***** Register Access API */
332static uint
333pcie_readreg(struct bcma_device *core, uint addrtype, uint offset)
334{
335 uint retval = 0xFFFFFFFF;
336
337 switch (addrtype) {
338 case PCIE_CONFIGREGS:
339 bcma_write32(core, PCIEREGOFFS(configaddr), offset);
340 (void)bcma_read32(core, PCIEREGOFFS(configaddr));
341 retval = bcma_read32(core, PCIEREGOFFS(configdata));
342 break;
343 case PCIE_PCIEREGS:
344 bcma_write32(core, PCIEREGOFFS(pcieindaddr), offset);
345 (void)bcma_read32(core, PCIEREGOFFS(pcieindaddr));
346 retval = bcma_read32(core, PCIEREGOFFS(pcieinddata));
347 break;
348 }
349
350 return retval;
351}
352
353static uint pcie_writereg(struct bcma_device *core, uint addrtype,
354 uint offset, uint val)
355{
356 switch (addrtype) {
357 case PCIE_CONFIGREGS:
358 bcma_write32(core, PCIEREGOFFS(configaddr), offset);
359 bcma_write32(core, PCIEREGOFFS(configdata), val);
360 break;
361 case PCIE_PCIEREGS:
362 bcma_write32(core, PCIEREGOFFS(pcieindaddr), offset);
363 bcma_write32(core, PCIEREGOFFS(pcieinddata), val);
364 break;
365 default:
366 break;
367 }
368 return 0;
369}
370
371static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk)
372{
373 uint mdiodata, i = 0;
374 uint pcie_serdes_spinwait = 200;
375
376 mdiodata = (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
377 (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
378 (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) |
379 (blk << 4));
380 bcma_write32(pi->core, PCIEREGOFFS(mdiodata), mdiodata);
381
382 pr28829_delay();
383 /* retry till the transaction is complete */
384 while (i < pcie_serdes_spinwait) {
385 if (bcma_read32(pi->core, PCIEREGOFFS(mdiocontrol)) &
386 MDIOCTL_ACCESS_DONE)
387 break;
388
389 udelay(1000);
390 i++;
391 }
392
393 if (i >= pcie_serdes_spinwait)
394 return false;
395
396 return true;
397}
398
399static int
400pcie_mdioop(struct pcicore_info *pi, uint physmedia, uint regaddr, bool write,
401 uint *val)
402{
403 uint mdiodata;
404 uint i = 0;
405 uint pcie_serdes_spinwait = 10;
406
407 /* enable mdio access to SERDES */
408 bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol),
409 MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
410
411 if (ai_get_buscorerev(pi->sih) >= 10) {
412 /* new serdes is slower in rw,
413 * using two layers of reg address mapping
414 */
415 if (!pcie_mdiosetblock(pi, physmedia))
416 return 1;
417 mdiodata = ((MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
418 (regaddr << MDIODATA_REGADDR_SHF));
419 pcie_serdes_spinwait *= 20;
420 } else {
421 mdiodata = ((physmedia << MDIODATA_DEVADDR_SHF_OLD) |
422 (regaddr << MDIODATA_REGADDR_SHF_OLD));
423 }
424
425 if (!write)
426 mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
427 else
428 mdiodata |= (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA |
429 *val);
430
431 bcma_write32(pi->core, PCIEREGOFFS(mdiodata), mdiodata);
432
433 pr28829_delay();
434
435 /* retry till the transaction is complete */
436 while (i < pcie_serdes_spinwait) {
437 if (bcma_read32(pi->core, PCIEREGOFFS(mdiocontrol)) &
438 MDIOCTL_ACCESS_DONE) {
439 if (!write) {
440 pr28829_delay();
441 *val = (bcma_read32(pi->core,
442 PCIEREGOFFS(mdiodata)) &
443 MDIODATA_MASK);
444 }
445 /* Disable mdio access to SERDES */
446 bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol), 0);
447 return 0;
448 }
449 udelay(1000);
450 i++;
451 }
452
453 /* Timed out. Disable mdio access to SERDES. */
454 bcma_write32(pi->core, PCIEREGOFFS(mdiocontrol), 0);
455 return 1;
456}
457
458/* use the mdio interface to read from mdio slaves */
459static int
460pcie_mdioread(struct pcicore_info *pi, uint physmedia, uint regaddr,
461 uint *regval)
462{
463 return pcie_mdioop(pi, physmedia, regaddr, false, regval);
464}
465
466/* use the mdio interface to write to mdio slaves */
467static int
468pcie_mdiowrite(struct pcicore_info *pi, uint physmedia, uint regaddr, uint val)
469{
470 return pcie_mdioop(pi, physmedia, regaddr, true, &val);
471}
472
473/* ***** Support functions ***** */
474static u8 pcie_clkreq(struct pcicore_info *pi, u32 mask, u32 val)
475{
476 u32 reg_val;
477 u8 offset;
478
479 offset = pi->pciecap_lcreg_offset;
480 if (!offset)
481 return 0;
482
483 pci_read_config_dword(pi->dev, offset, &reg_val);
484 /* set operation */
485 if (mask) {
486 if (val)
487 reg_val |= PCIE_CLKREQ_ENAB;
488 else
489 reg_val &= ~PCIE_CLKREQ_ENAB;
490 pci_write_config_dword(pi->dev, offset, reg_val);
491 pci_read_config_dword(pi->dev, offset, &reg_val);
492 }
493 if (reg_val & PCIE_CLKREQ_ENAB)
494 return 1;
495 else
496 return 0;
497}
498
499static void pcie_extendL1timer(struct pcicore_info *pi, bool extend)
500{
501 u32 w;
502 struct si_pub *sih = pi->sih;
503
504 if (ai_get_buscoretype(sih) != PCIE_CORE_ID ||
505 ai_get_buscorerev(sih) < 7)
506 return;
507
508 w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
509 if (extend)
510 w |= PCIE_ASPMTIMER_EXTEND;
511 else
512 w &= ~PCIE_ASPMTIMER_EXTEND;
513 pcie_writereg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
514 w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
515}
516
517/* centralized clkreq control policy */
518static void pcie_clkreq_upd(struct pcicore_info *pi, uint state)
519{
520 struct si_pub *sih = pi->sih;
521
522 switch (state) {
523 case SI_DOATTACH:
524 if (PCIE_ASPM(sih))
525 pcie_clkreq(pi, 1, 0);
526 break;
527 case SI_PCIDOWN:
528 /* turn on serdes PLL down */
529 if (ai_get_buscorerev(sih) == 6) {
530 ai_cc_reg(sih,
531 offsetof(struct chipcregs, chipcontrol_addr),
532 ~0, 0);
533 ai_cc_reg(sih,
534 offsetof(struct chipcregs, chipcontrol_data),
535 ~0x40, 0);
536 } else if (pi->pcie_pr42767) {
537 pcie_clkreq(pi, 1, 1);
538 }
539 break;
540 case SI_PCIUP:
541 /* turn off serdes PLL down */
542 if (ai_get_buscorerev(sih) == 6) {
543 ai_cc_reg(sih,
544 offsetof(struct chipcregs, chipcontrol_addr),
545 ~0, 0);
546 ai_cc_reg(sih,
547 offsetof(struct chipcregs, chipcontrol_data),
548 ~0x40, 0x40);
549 } else if (PCIE_ASPM(sih)) { /* disable clkreq */
550 pcie_clkreq(pi, 1, 0);
551 }
552 break;
553 }
554}
555
556/* ***** PCI core WARs ***** */
557/* Done only once at attach time */
558static void pcie_war_polarity(struct pcicore_info *pi)
559{
560 u32 w;
561
562 if (pi->pcie_polarity != 0)
563 return;
564
565 w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_PLP_STATUSREG);
566
567 /* Detect the current polarity at attach and force that polarity and
568 * disable changing the polarity
569 */
570 if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
571 pi->pcie_polarity = SERDES_RX_CTRL_FORCE;
572 else
573 pi->pcie_polarity = (SERDES_RX_CTRL_FORCE |
574 SERDES_RX_CTRL_POLARITY);
575}
576
577/* enable ASPM and CLKREQ if srom doesn't have it */
578/* Needs to happen when update to shadow SROM is needed
579 * : Coming out of 'standby'/'hibernate'
580 * : If pcie_war_aspm_ovr state changed
581 */
582static void pcie_war_aspm_clkreq(struct pcicore_info *pi)
583{
584 struct si_pub *sih = pi->sih;
585 u16 val16;
586 u32 w;
587
588 if (!PCIE_ASPM(sih))
589 return;
590
591 /* bypass this on QT or VSIM */
592 val16 = bcma_read16(pi->core, PCIEREGOFFS(sprom[SRSH_ASPM_OFFSET]));
593
594 val16 &= ~SRSH_ASPM_ENB;
595 if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
596 val16 |= SRSH_ASPM_ENB;
597 else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB)
598 val16 |= SRSH_ASPM_L1_ENB;
599 else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
600 val16 |= SRSH_ASPM_L0s_ENB;
601
602 bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_ASPM_OFFSET]), val16);
603
604 pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
605 w &= ~PCIE_ASPM_ENAB;
606 w |= pi->pcie_war_aspm_ovr;
607 pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
608
609 val16 = bcma_read16(pi->core,
610 PCIEREGOFFS(sprom[SRSH_CLKREQ_OFFSET_REV5]));
611
612 if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
613 val16 |= SRSH_CLKREQ_ENB;
614 pi->pcie_pr42767 = true;
615 } else
616 val16 &= ~SRSH_CLKREQ_ENB;
617
618 bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_CLKREQ_OFFSET_REV5]),
619 val16);
620}
621
622/* Apply the polarity determined at the start */
623/* Needs to happen when coming out of 'standby'/'hibernate' */
624static void pcie_war_serdes(struct pcicore_info *pi)
625{
626 u32 w = 0;
627
628 if (pi->pcie_polarity != 0)
629 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
630 pi->pcie_polarity);
631
632 pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
633 if (w & PLL_CTRL_FREQDET_EN) {
634 w &= ~PLL_CTRL_FREQDET_EN;
635 pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
636 }
637}
638
639/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
640/* Needs to happen when coming out of 'standby'/'hibernate' */
641static void pcie_misc_config_fixup(struct pcicore_info *pi)
642{
643 u16 val16;
644
645 val16 = bcma_read16(pi->core,
646 PCIEREGOFFS(sprom[SRSH_PCIE_MISC_CONFIG]));
647
648 if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) {
649 val16 |= SRSH_L23READY_EXIT_NOPERST;
650 bcma_write16(pi->core,
651 PCIEREGOFFS(sprom[SRSH_PCIE_MISC_CONFIG]), val16);
652 }
653}
654
655/* quick hack for testing */
656/* Needs to happen when coming out of 'standby'/'hibernate' */
657static void pcie_war_noplldown(struct pcicore_info *pi)
658{
659 /* turn off serdes PLL down */
660 ai_cc_reg(pi->sih, offsetof(struct chipcregs, chipcontrol),
661 CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
662
663 /* clear srom shadow backdoor */
664 bcma_write16(pi->core, PCIEREGOFFS(sprom[SRSH_BD_OFFSET]), 0);
665}
666
667/* Needs to happen when coming out of 'standby'/'hibernate' */
668static void pcie_war_pci_setup(struct pcicore_info *pi)
669{
670 struct si_pub *sih = pi->sih;
671 u32 w;
672
673 if (ai_get_buscorerev(sih) == 0 || ai_get_buscorerev(sih) == 1) {
674 w = pcie_readreg(pi->core, PCIE_PCIEREGS,
675 PCIE_TLP_WORKAROUNDSREG);
676 w |= 0x8;
677 pcie_writereg(pi->core, PCIE_PCIEREGS,
678 PCIE_TLP_WORKAROUNDSREG, w);
679 }
680
681 if (ai_get_buscorerev(sih) == 1) {
682 w = pcie_readreg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
683 w |= 0x40;
684 pcie_writereg(pi->core, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
685 }
686
687 if (ai_get_buscorerev(sih) == 0) {
688 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
689 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
690 pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
691 } else if (PCIE_ASPM(sih)) {
692 /* Change the L1 threshold for better performance */
693 w = pcie_readreg(pi->core, PCIE_PCIEREGS,
694 PCIE_DLLP_PMTHRESHREG);
695 w &= ~PCIE_L1THRESHOLDTIME_MASK;
696 w |= PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT;
697 pcie_writereg(pi->core, PCIE_PCIEREGS,
698 PCIE_DLLP_PMTHRESHREG, w);
699
700 pcie_war_serdes(pi);
701
702 pcie_war_aspm_clkreq(pi);
703 } else if (ai_get_buscorerev(pi->sih) == 7)
704 pcie_war_noplldown(pi);
705
706 /* Note that the fix is actually in the SROM,
707 * that's why this is open-ended
708 */
709 if (ai_get_buscorerev(pi->sih) >= 6)
710 pcie_misc_config_fixup(pi);
711}
712
713/* ***** Functions called during driver state changes ***** */
714void pcicore_attach(struct pcicore_info *pi, int state)
715{
716 struct si_pub *sih = pi->sih;
717 u32 bfl2 = (u32)getintvar(sih, BRCMS_SROM_BOARDFLAGS2);
718
719 /* Determine if this board needs override */
720 if (PCIE_ASPM(sih)) {
721 if (bfl2 & BFL2_PCIEWAR_OVR)
722 pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
723 else
724 pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
725 }
726
727 /* These need to happen in this order only */
728 pcie_war_polarity(pi);
729
730 pcie_war_serdes(pi);
731
732 pcie_war_aspm_clkreq(pi);
733
734 pcie_clkreq_upd(pi, state);
735
736}
737
738void pcicore_hwup(struct pcicore_info *pi)
739{
740 if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
741 return;
742
743 pcie_war_pci_setup(pi);
744}
745
746void pcicore_up(struct pcicore_info *pi, int state)
747{
748 if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
749 return;
750
751 /* Restore L1 timer for better performance */
752 pcie_extendL1timer(pi, true);
753
754 pcie_clkreq_upd(pi, state);
755}
756
757/* When the device is going to enter D3 state
758 * (or the system is going to enter S3/S4 states)
759 */
760void pcicore_sleep(struct pcicore_info *pi)
761{
762 u32 w;
763
764 if (!pi || !PCIE_ASPM(pi->sih))
765 return;
766
767 pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
768 w &= ~PCIE_CAP_LCREG_ASPML1;
769 pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
770
771 pi->pcie_pr42767 = false;
772}
773
774void pcicore_down(struct pcicore_info *pi, int state)
775{
776 if (!pi || ai_get_buscoretype(pi->sih) != PCIE_CORE_ID)
777 return;
778
779 pcie_clkreq_upd(pi, state);
780
781 /* Reduce L1 timer for better power savings */
782 pcie_extendL1timer(pi, false);
783}
784
785void pcicore_fixcfg(struct pcicore_info *pi)
786{
787 struct bcma_device *core = pi->core;
788 u16 val16;
789 uint regoff;
790
791 switch (pi->core->id.id) {
792 case BCMA_CORE_PCI:
793 regoff = PCIREGOFFS(sprom[SRSH_PI_OFFSET]);
794 break;
795
796 case BCMA_CORE_PCIE:
797 regoff = PCIEREGOFFS(sprom[SRSH_PI_OFFSET]);
798 break;
799
800 default:
801 return;
802 }
803
804 val16 = bcma_read16(pi->core, regoff);
805 if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) !=
806 (u16)core->core_index) {
807 val16 = ((u16)core->core_index << SRSH_PI_SHIFT) |
808 (val16 & ~SRSH_PI_MASK);
809 bcma_write16(pi->core, regoff, val16);
810 }
811}
812
813/* precondition: current core is pci core */
814void
815pcicore_pci_setup(struct pcicore_info *pi)
816{
817 bcma_set32(pi->core, PCIREGOFFS(sbtopci2),
818 SBTOPCI_PREF | SBTOPCI_BURST);
819
820 if (pi->core->id.rev >= 11) {
821 bcma_set32(pi->core, PCIREGOFFS(sbtopci2),
822 SBTOPCI_RC_READMULTI);
823 bcma_set32(pi->core, PCIREGOFFS(clkrun), PCI_CLKRUN_DSBL);
824 (void)bcma_read32(pi->core, PCIREGOFFS(clkrun));
825 }
826}
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h b/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h
deleted file mode 100644
index 9fc3ead540a8..000000000000
--- a/drivers/net/wireless/brcm80211/brcmsmac/nicpci.h
+++ /dev/null
@@ -1,77 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_NICPCI_H_
18#define _BRCM_NICPCI_H_
19
20#include "types.h"
21
22/* PCI configuration address space size */
23#define PCI_SZPCR 256
24
25/* Brcm PCI configuration registers */
26/* backplane address space accessed by BAR0 */
27#define PCI_BAR0_WIN 0x80
28/* sprom property control */
29#define PCI_SPROM_CONTROL 0x88
30/* mask of PCI and other cores interrupts */
31#define PCI_INT_MASK 0x94
32/* backplane core interrupt mask bits offset */
33#define PCI_SBIM_SHIFT 8
34/* backplane address space accessed by second 4KB of BAR0 */
35#define PCI_BAR0_WIN2 0xac
36/* pci config space gpio input (>=rev3) */
37#define PCI_GPIO_IN 0xb0
38/* pci config space gpio output (>=rev3) */
39#define PCI_GPIO_OUT 0xb4
40/* pci config space gpio output enable (>=rev3) */
41#define PCI_GPIO_OUTEN 0xb8
42
43/* bar0 + 4K accesses external sprom */
44#define PCI_BAR0_SPROM_OFFSET (4 * 1024)
45/* bar0 + 6K accesses pci core registers */
46#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)
47/*
48 * pci core SB registers are at the end of the
49 * 8KB window, so their address is the "regular"
50 * address plus 4K
51 */
52#define PCI_BAR0_PCISBR_OFFSET (4 * 1024)
53/* bar0 window size Match with corerev 13 */
54#define PCI_BAR0_WINSZ (16 * 1024)
55/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
56/* bar0 + 8K accesses pci/pcie core registers */
57#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
58/* bar0 + 12K accesses chipc core registers */
59#define PCI_16KB0_CCREGS_OFFSET (12 * 1024)
60
61struct sbpciregs;
62struct sbpcieregs;
63
64extern struct pcicore_info *pcicore_init(struct si_pub *sih,
65 struct bcma_device *core);
66extern void pcicore_deinit(struct pcicore_info *pch);
67extern void pcicore_attach(struct pcicore_info *pch, int state);
68extern void pcicore_hwup(struct pcicore_info *pch);
69extern void pcicore_up(struct pcicore_info *pch, int state);
70extern void pcicore_sleep(struct pcicore_info *pch);
71extern void pcicore_down(struct pcicore_info *pch, int state);
72extern u8 pcicore_find_pci_capability(struct pci_dev *dev, u8 req_cap_id,
73 unsigned char *buf, u32 *buflen);
74extern void pcicore_fixcfg(struct pcicore_info *pch);
75extern void pcicore_pci_setup(struct pcicore_info *pch);
76
77#endif /* _BRCM_NICPCI_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/otp.c b/drivers/net/wireless/brcm80211/brcmsmac/otp.c
deleted file mode 100644
index f1ca12625860..000000000000
--- a/drivers/net/wireless/brcm80211/brcmsmac/otp.c
+++ /dev/null
@@ -1,410 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20
21#include <brcm_hw_ids.h>
22#include <chipcommon.h>
23#include "aiutils.h"
24#include "otp.h"
25
26#define OTPS_GUP_MASK 0x00000f00
27#define OTPS_GUP_SHIFT 8
28/* h/w subregion is programmed */
29#define OTPS_GUP_HW 0x00000100
30/* s/w subregion is programmed */
31#define OTPS_GUP_SW 0x00000200
32/* chipid/pkgopt subregion is programmed */
33#define OTPS_GUP_CI 0x00000400
34/* fuse subregion is programmed */
35#define OTPS_GUP_FUSE 0x00000800
36
37/* Fields in otpprog in rev >= 21 */
38#define OTPP_COL_MASK 0x000000ff
39#define OTPP_COL_SHIFT 0
40#define OTPP_ROW_MASK 0x0000ff00
41#define OTPP_ROW_SHIFT 8
42#define OTPP_OC_MASK 0x0f000000
43#define OTPP_OC_SHIFT 24
44#define OTPP_READERR 0x10000000
45#define OTPP_VALUE_MASK 0x20000000
46#define OTPP_VALUE_SHIFT 29
47#define OTPP_START_BUSY 0x80000000
48#define OTPP_READ 0x40000000
49
50/* Opcodes for OTPP_OC field */
51#define OTPPOC_READ 0
52#define OTPPOC_BIT_PROG 1
53#define OTPPOC_VERIFY 3
54#define OTPPOC_INIT 4
55#define OTPPOC_SET 5
56#define OTPPOC_RESET 6
57#define OTPPOC_OCST 7
58#define OTPPOC_ROW_LOCK 8
59#define OTPPOC_PRESCN_TEST 9
60
61#define OTPTYPE_IPX(ccrev) ((ccrev) == 21 || (ccrev) >= 23)
62
63#define OTPP_TRIES 10000000 /* # of tries for OTPP */
64
65#define MAXNUMRDES 9 /* Maximum OTP redundancy entries */
66
67/* Fixed size subregions sizes in words */
68#define OTPGU_CI_SZ 2
69
70struct otpinfo;
71
72/* OTP function struct */
73struct otp_fn_s {
74 int (*init)(struct si_pub *sih, struct otpinfo *oi);
75 int (*read_region)(struct otpinfo *oi, int region, u16 *data,
76 uint *wlen);
77};
78
79struct otpinfo {
80 struct bcma_device *core; /* chipc core */
81 const struct otp_fn_s *fn; /* OTP functions */
82 struct si_pub *sih; /* Saved sb handle */
83
84 /* IPX OTP section */
85 u16 wsize; /* Size of otp in words */
86 u16 rows; /* Geometry */
87 u16 cols; /* Geometry */
88 u32 status; /* Flag bits (lock/prog/rv).
89 * (Reflected only when OTP is power cycled)
90 */
91 u16 hwbase; /* hardware subregion offset */
92 u16 hwlim; /* hardware subregion boundary */
93 u16 swbase; /* software subregion offset */
94 u16 swlim; /* software subregion boundary */
95 u16 fbase; /* fuse subregion offset */
96 u16 flim; /* fuse subregion boundary */
97 int otpgu_base; /* offset to General Use Region */
98};
99
100/* OTP layout */
101/* CC revs 21, 24 and 27 OTP General Use Region word offset */
102#define REVA4_OTPGU_BASE 12
103
104/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */
105#define REVB8_OTPGU_BASE 20
106
107/* CC rev 36 OTP General Use Region word offset */
108#define REV36_OTPGU_BASE 12
109
110/* Subregion word offsets in General Use region */
111#define OTPGU_HSB_OFF 0
112#define OTPGU_SFB_OFF 1
113#define OTPGU_CI_OFF 2
114#define OTPGU_P_OFF 3
115#define OTPGU_SROM_OFF 4
116
117/* Flag bit offsets in General Use region */
118#define OTPGU_HWP_OFF 60
119#define OTPGU_SWP_OFF 61
120#define OTPGU_CIP_OFF 62
121#define OTPGU_FUSEP_OFF 63
122#define OTPGU_CIP_MSK 0x4000
123#define OTPGU_P_MSK 0xf000
124#define OTPGU_P_SHIFT (OTPGU_HWP_OFF % 16)
125
126/* OTP Size */
127#define OTP_SZ_FU_324 ((roundup(324, 8))/8) /* 324 bits */
128#define OTP_SZ_FU_288 (288/8) /* 288 bits */
129#define OTP_SZ_FU_216 (216/8) /* 216 bits */
130#define OTP_SZ_FU_72 (72/8) /* 72 bits */
131#define OTP_SZ_CHECKSUM (16/8) /* 16 bits */
132#define OTP4315_SWREG_SZ 178 /* 178 bytes */
133#define OTP_SZ_FU_144 (144/8) /* 144 bits */
134
135static u16
136ipxotp_otpr(struct otpinfo *oi, uint wn)
137{
138 return bcma_read16(oi->core,
139 CHIPCREGOFFS(sromotp[wn]));
140}
141
142/*
143 * Calculate max HW/SW region byte size by subtracting fuse region
144 * and checksum size, osizew is oi->wsize (OTP size - GU size) in words
145 */
146static int ipxotp_max_rgnsz(struct si_pub *sih, int osizew)
147{
148 int ret = 0;
149
150 switch (ai_get_chip_id(sih)) {
151 case BCM43224_CHIP_ID:
152 case BCM43225_CHIP_ID:
153 ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
154 break;
155 case BCM4313_CHIP_ID:
156 ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
157 break;
158 default:
159 break; /* Don't know about this chip */
160 }
161
162 return ret;
163}
164
165static void _ipxotp_init(struct otpinfo *oi)
166{
167 uint k;
168 u32 otpp, st;
169 int ccrev = ai_get_ccrev(oi->sih);
170
171
172 /*
173 * record word offset of General Use Region
174 * for various chipcommon revs
175 */
176 if (ccrev == 21 || ccrev == 24
177 || ccrev == 27) {
178 oi->otpgu_base = REVA4_OTPGU_BASE;
179 } else if (ccrev == 36) {
180 /*
181 * OTP size greater than equal to 2KB (128 words),
182 * otpgu_base is similar to rev23
183 */
184 if (oi->wsize >= 128)
185 oi->otpgu_base = REVB8_OTPGU_BASE;
186 else
187 oi->otpgu_base = REV36_OTPGU_BASE;
188 } else if (ccrev == 23 || ccrev >= 25) {
189 oi->otpgu_base = REVB8_OTPGU_BASE;
190 }
191
192 /* First issue an init command so the status is up to date */
193 otpp =
194 OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
195
196 bcma_write32(oi->core, CHIPCREGOFFS(otpprog), otpp);
197 st = bcma_read32(oi->core, CHIPCREGOFFS(otpprog));
198 for (k = 0; (st & OTPP_START_BUSY) && (k < OTPP_TRIES); k++)
199 st = bcma_read32(oi->core, CHIPCREGOFFS(otpprog));
200 if (k >= OTPP_TRIES)
201 return;
202
203 /* Read OTP lock bits and subregion programmed indication bits */
204 oi->status = bcma_read32(oi->core, CHIPCREGOFFS(otpstatus));
205
206 if ((ai_get_chip_id(oi->sih) == BCM43224_CHIP_ID)
207 || (ai_get_chip_id(oi->sih) == BCM43225_CHIP_ID)) {
208 u32 p_bits;
209 p_bits = (ipxotp_otpr(oi, oi->otpgu_base + OTPGU_P_OFF) &
210 OTPGU_P_MSK) >> OTPGU_P_SHIFT;
211 oi->status |= (p_bits << OTPS_GUP_SHIFT);
212 }
213
214 /*
215 * h/w region base and fuse region limit are fixed to
216 * the top and the bottom of the general use region.
217 * Everything else can be flexible.
218 */
219 oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF;
220 oi->hwlim = oi->wsize;
221 if (oi->status & OTPS_GUP_HW) {
222 oi->hwlim =
223 ipxotp_otpr(oi, oi->otpgu_base + OTPGU_HSB_OFF) / 16;
224 oi->swbase = oi->hwlim;
225 } else
226 oi->swbase = oi->hwbase;
227
228 /* subtract fuse and checksum from beginning */
229 oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2;
230
231 if (oi->status & OTPS_GUP_SW) {
232 oi->swlim =
233 ipxotp_otpr(oi, oi->otpgu_base + OTPGU_SFB_OFF) / 16;
234 oi->fbase = oi->swlim;
235 } else
236 oi->fbase = oi->swbase;
237
238 oi->flim = oi->wsize;
239}
240
241static int ipxotp_init(struct si_pub *sih, struct otpinfo *oi)
242{
243 /* Make sure we're running IPX OTP */
244 if (!OTPTYPE_IPX(ai_get_ccrev(sih)))
245 return -EBADE;
246
247 /* Make sure OTP is not disabled */
248 if (ai_is_otp_disabled(sih))
249 return -EBADE;
250
251 /* Check for otp size */
252 switch ((ai_get_cccaps(sih) & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
253 case 0:
254 /* Nothing there */
255 return -EBADE;
256 case 1: /* 32x64 */
257 oi->rows = 32;
258 oi->cols = 64;
259 oi->wsize = 128;
260 break;
261 case 2: /* 64x64 */
262 oi->rows = 64;
263 oi->cols = 64;
264 oi->wsize = 256;
265 break;
266 case 5: /* 96x64 */
267 oi->rows = 96;
268 oi->cols = 64;
269 oi->wsize = 384;
270 break;
271 case 7: /* 16x64 *//* 1024 bits */
272 oi->rows = 16;
273 oi->cols = 64;
274 oi->wsize = 64;
275 break;
276 default:
277 /* Don't know the geometry */
278 return -EBADE;
279 }
280
281 /* Retrieve OTP region info */
282 _ipxotp_init(oi);
283 return 0;
284}
285
286static int
287ipxotp_read_region(struct otpinfo *oi, int region, u16 *data, uint *wlen)
288{
289 uint base, i, sz;
290
291 /* Validate region selection */
292 switch (region) {
293 case OTP_HW_RGN:
294 sz = (uint) oi->hwlim - oi->hwbase;
295 if (!(oi->status & OTPS_GUP_HW)) {
296 *wlen = sz;
297 return -ENODATA;
298 }
299 if (*wlen < sz) {
300 *wlen = sz;
301 return -EOVERFLOW;
302 }
303 base = oi->hwbase;
304 break;
305 case OTP_SW_RGN:
306 sz = ((uint) oi->swlim - oi->swbase);
307 if (!(oi->status & OTPS_GUP_SW)) {
308 *wlen = sz;
309 return -ENODATA;
310 }
311 if (*wlen < sz) {
312 *wlen = sz;
313 return -EOVERFLOW;
314 }
315 base = oi->swbase;
316 break;
317 case OTP_CI_RGN:
318 sz = OTPGU_CI_SZ;
319 if (!(oi->status & OTPS_GUP_CI)) {
320 *wlen = sz;
321 return -ENODATA;
322 }
323 if (*wlen < sz) {
324 *wlen = sz;
325 return -EOVERFLOW;
326 }
327 base = oi->otpgu_base + OTPGU_CI_OFF;
328 break;
329 case OTP_FUSE_RGN:
330 sz = (uint) oi->flim - oi->fbase;
331 if (!(oi->status & OTPS_GUP_FUSE)) {
332 *wlen = sz;
333 return -ENODATA;
334 }
335 if (*wlen < sz) {
336 *wlen = sz;
337 return -EOVERFLOW;
338 }
339 base = oi->fbase;
340 break;
341 case OTP_ALL_RGN:
342 sz = ((uint) oi->flim - oi->hwbase);
343 if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) {
344 *wlen = sz;
345 return -ENODATA;
346 }
347 if (*wlen < sz) {
348 *wlen = sz;
349 return -EOVERFLOW;
350 }
351 base = oi->hwbase;
352 break;
353 default:
354 return -EINVAL;
355 }
356
357 /* Read the data */
358 for (i = 0; i < sz; i++)
359 data[i] = ipxotp_otpr(oi, base + i);
360
361 *wlen = sz;
362 return 0;
363}
364
365static const struct otp_fn_s ipxotp_fn = {
366 (int (*)(struct si_pub *, struct otpinfo *)) ipxotp_init,
367 (int (*)(struct otpinfo *, int, u16 *, uint *)) ipxotp_read_region,
368};
369
370static int otp_init(struct si_pub *sih, struct otpinfo *oi)
371{
372 int ret;
373
374 memset(oi, 0, sizeof(struct otpinfo));
375
376 oi->core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
377
378 if (OTPTYPE_IPX(ai_get_ccrev(sih)))
379 oi->fn = &ipxotp_fn;
380
381 if (oi->fn == NULL)
382 return -EBADE;
383
384 oi->sih = sih;
385
386 ret = (oi->fn->init)(sih, oi);
387
388 return ret;
389}
390
391int
392otp_read_region(struct si_pub *sih, int region, u16 *data, uint *wlen) {
393 struct otpinfo otpinfo;
394 struct otpinfo *oi = &otpinfo;
395 int err = 0;
396
397 if (ai_is_otp_disabled(sih)) {
398 err = -EPERM;
399 goto out;
400 }
401
402 err = otp_init(sih, oi);
403 if (err)
404 goto out;
405
406 err = ((oi)->fn->read_region)(oi, region, data, wlen);
407
408 out:
409 return err;
410}
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/otp.h b/drivers/net/wireless/brcm80211/brcmsmac/otp.h
deleted file mode 100644
index 6b6d31cf9569..000000000000
--- a/drivers/net/wireless/brcm80211/brcmsmac/otp.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_OTP_H_
18#define _BRCM_OTP_H_
19
20#include "types.h"
21
22/* OTP regions */
23#define OTP_HW_RGN 1
24#define OTP_SW_RGN 2
25#define OTP_CI_RGN 4
26#define OTP_FUSE_RGN 8
27/* From h/w region to end of OTP including checksum */
28#define OTP_ALL_RGN 0xf
29
30/* OTP Size */
31#define OTP_SZ_MAX (6144/8) /* maximum bytes in one CIS */
32
33extern int otp_read_region(struct si_pub *sih, int region, u16 *data,
34 uint *wlen);
35
36#endif /* _BRCM_OTP_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
index 0fce56235f38..abfd78822fb8 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
@@ -4817,28 +4817,23 @@ static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi)
4817 s8 txpwr = 0; 4817 s8 txpwr = 0;
4818 int i; 4818 int i;
4819 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy; 4819 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
4820 struct phy_shim_info *shim = pi->sh->physhim; 4820 struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
4821 4821
4822 if (CHSPEC_IS2G(pi->radio_chanspec)) { 4822 if (CHSPEC_IS2G(pi->radio_chanspec)) {
4823 u16 cckpo = 0; 4823 u16 cckpo = 0;
4824 u32 offset_ofdm, offset_mcs; 4824 u32 offset_ofdm, offset_mcs;
4825 4825
4826 pi_lcn->lcnphy_tr_isolation_mid = 4826 pi_lcn->lcnphy_tr_isolation_mid = sprom->fem.ghz2.tr_iso;
4827 (u8)wlapi_getintvar(shim, BRCMS_SROM_TRISO2G);
4828 4827
4829 pi_lcn->lcnphy_rx_power_offset = 4828 pi_lcn->lcnphy_rx_power_offset = sprom->rxpo2g;
4830 (u8)wlapi_getintvar(shim, BRCMS_SROM_RXPO2G);
4831 4829
4832 pi->txpa_2g[0] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B0); 4830 pi->txpa_2g[0] = sprom->pa0b0;
4833 pi->txpa_2g[1] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B1); 4831 pi->txpa_2g[1] = sprom->pa0b1;
4834 pi->txpa_2g[2] = (s16)wlapi_getintvar(shim, BRCMS_SROM_PA0B2); 4832 pi->txpa_2g[2] = sprom->pa0b2;
4835 4833
4836 pi_lcn->lcnphy_rssi_vf = 4834 pi_lcn->lcnphy_rssi_vf = sprom->rssismf2g;
4837 (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISMF2G); 4835 pi_lcn->lcnphy_rssi_vc = sprom->rssismc2g;
4838 pi_lcn->lcnphy_rssi_vc = 4836 pi_lcn->lcnphy_rssi_gs = sprom->rssisav2g;
4839 (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISMC2G);
4840 pi_lcn->lcnphy_rssi_gs =
4841 (u8)wlapi_getintvar(shim, BRCMS_SROM_RSSISAV2G);
4842 4837
4843 pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf; 4838 pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf;
4844 pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc; 4839 pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc;
@@ -4848,7 +4843,7 @@ static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi)
4848 pi_lcn->lcnphy_rssi_vc_hightemp = pi_lcn->lcnphy_rssi_vc; 4843 pi_lcn->lcnphy_rssi_vc_hightemp = pi_lcn->lcnphy_rssi_vc;
4849 pi_lcn->lcnphy_rssi_gs_hightemp = pi_lcn->lcnphy_rssi_gs; 4844 pi_lcn->lcnphy_rssi_gs_hightemp = pi_lcn->lcnphy_rssi_gs;
4850 4845
4851 txpwr = (s8)wlapi_getintvar(shim, BRCMS_SROM_MAXP2GA0); 4846 txpwr = sprom->core_pwr_info[0].maxpwr_2g;
4852 pi->tx_srom_max_2g = txpwr; 4847 pi->tx_srom_max_2g = txpwr;
4853 4848
4854 for (i = 0; i < PWRTBL_NUM_COEFF; i++) { 4849 for (i = 0; i < PWRTBL_NUM_COEFF; i++) {
@@ -4856,8 +4851,8 @@ static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi)
4856 pi->txpa_2g_high_temp[i] = pi->txpa_2g[i]; 4851 pi->txpa_2g_high_temp[i] = pi->txpa_2g[i];
4857 } 4852 }
4858 4853
4859 cckpo = (u16)wlapi_getintvar(shim, BRCMS_SROM_CCK2GPO); 4854 cckpo = sprom->cck2gpo;
4860 offset_ofdm = (u32)wlapi_getintvar(shim, BRCMS_SROM_OFDM2GPO); 4855 offset_ofdm = sprom->ofdm2gpo;
4861 if (cckpo) { 4856 if (cckpo) {
4862 uint max_pwr_chan = txpwr; 4857 uint max_pwr_chan = txpwr;
4863 4858
@@ -4876,7 +4871,7 @@ static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi)
4876 } else { 4871 } else {
4877 u8 opo = 0; 4872 u8 opo = 0;
4878 4873
4879 opo = (u8)wlapi_getintvar(shim, BRCMS_SROM_OPO); 4874 opo = sprom->opo;
4880 4875
4881 for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++) 4876 for (i = TXP_FIRST_CCK; i <= TXP_LAST_CCK; i++)
4882 pi->tx_srom_max_rate_2g[i] = txpwr; 4877 pi->tx_srom_max_rate_2g[i] = txpwr;
@@ -4886,12 +4881,8 @@ static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi)
4886 ((offset_ofdm & 0xf) * 2); 4881 ((offset_ofdm & 0xf) * 2);
4887 offset_ofdm >>= 4; 4882 offset_ofdm >>= 4;
4888 } 4883 }
4889 offset_mcs = 4884 offset_mcs = sprom->mcs2gpo[1] << 16;
4890 wlapi_getintvar(shim, 4885 offset_mcs |= sprom->mcs2gpo[0];
4891 BRCMS_SROM_MCS2GPO1) << 16;
4892 offset_mcs |=
4893 (u16) wlapi_getintvar(shim,
4894 BRCMS_SROM_MCS2GPO0);
4895 pi_lcn->lcnphy_mcs20_po = offset_mcs; 4886 pi_lcn->lcnphy_mcs20_po = offset_mcs;
4896 for (i = TXP_FIRST_SISO_MCS_20; 4887 for (i = TXP_FIRST_SISO_MCS_20;
4897 i <= TXP_LAST_SISO_MCS_20; i++) { 4888 i <= TXP_LAST_SISO_MCS_20; i++) {
@@ -4901,25 +4892,17 @@ static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi)
4901 } 4892 }
4902 } 4893 }
4903 4894
4904 pi_lcn->lcnphy_rawtempsense = 4895 pi_lcn->lcnphy_rawtempsense = sprom->rawtempsense;
4905 (u16)wlapi_getintvar(shim, BRCMS_SROM_RAWTEMPSENSE); 4896 pi_lcn->lcnphy_measPower = sprom->measpower;
4906 pi_lcn->lcnphy_measPower = 4897 pi_lcn->lcnphy_tempsense_slope = sprom->tempsense_slope;
4907 (u8)wlapi_getintvar(shim, BRCMS_SROM_MEASPOWER); 4898 pi_lcn->lcnphy_hw_iqcal_en = sprom->hw_iqcal_en;
4908 pi_lcn->lcnphy_tempsense_slope = 4899 pi_lcn->lcnphy_iqcal_swp_dis = sprom->iqcal_swp_dis;
4909 (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPSENSE_SLOPE); 4900 pi_lcn->lcnphy_tempcorrx = sprom->tempcorrx;
4910 pi_lcn->lcnphy_hw_iqcal_en = 4901 pi_lcn->lcnphy_tempsense_option = sprom->tempsense_option;
4911 (bool)wlapi_getintvar(shim, BRCMS_SROM_HW_IQCAL_EN); 4902 pi_lcn->lcnphy_freqoffset_corr = sprom->freqoffset_corr;
4912 pi_lcn->lcnphy_iqcal_swp_dis = 4903 if (sprom->ant_available_bg > 1)
4913 (bool)wlapi_getintvar(shim, BRCMS_SROM_IQCAL_SWP_DIS);
4914 pi_lcn->lcnphy_tempcorrx =
4915 (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPCORRX);
4916 pi_lcn->lcnphy_tempsense_option =
4917 (u8)wlapi_getintvar(shim, BRCMS_SROM_TEMPSENSE_OPTION);
4918 pi_lcn->lcnphy_freqoffset_corr =
4919 (u8)wlapi_getintvar(shim, BRCMS_SROM_FREQOFFSET_CORR);
4920 if ((u8)wlapi_getintvar(shim, BRCMS_SROM_AA2G) > 1)
4921 wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi, 4904 wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi,
4922 (u8) wlapi_getintvar(shim, BRCMS_SROM_AA2G)); 4905 sprom->ant_available_bg);
4923 } 4906 }
4924 pi_lcn->lcnphy_cck_dig_filt_type = -1; 4907 pi_lcn->lcnphy_cck_dig_filt_type = -1;
4925 4908
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
index 812b6e38526e..13b261517cce 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
@@ -14386,30 +14386,30 @@ static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14386{ 14386{
14387 u16 bw40po, cddpo, stbcpo, bwduppo; 14387 u16 bw40po, cddpo, stbcpo, bwduppo;
14388 uint band_num; 14388 uint band_num;
14389 struct phy_shim_info *shim = pi->sh->physhim; 14389 struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
14390 14390
14391 if (pi->sh->sromrev >= 9) 14391 if (pi->sh->sromrev >= 9)
14392 return; 14392 return;
14393 14393
14394 bw40po = (u16) wlapi_getintvar(shim, BRCMS_SROM_BW40PO); 14394 bw40po = sprom->bw40po;
14395 pi->bw402gpo = bw40po & 0xf; 14395 pi->bw402gpo = bw40po & 0xf;
14396 pi->bw405gpo = (bw40po & 0xf0) >> 4; 14396 pi->bw405gpo = (bw40po & 0xf0) >> 4;
14397 pi->bw405glpo = (bw40po & 0xf00) >> 8; 14397 pi->bw405glpo = (bw40po & 0xf00) >> 8;
14398 pi->bw405ghpo = (bw40po & 0xf000) >> 12; 14398 pi->bw405ghpo = (bw40po & 0xf000) >> 12;
14399 14399
14400 cddpo = (u16) wlapi_getintvar(shim, BRCMS_SROM_CDDPO); 14400 cddpo = sprom->cddpo;
14401 pi->cdd2gpo = cddpo & 0xf; 14401 pi->cdd2gpo = cddpo & 0xf;
14402 pi->cdd5gpo = (cddpo & 0xf0) >> 4; 14402 pi->cdd5gpo = (cddpo & 0xf0) >> 4;
14403 pi->cdd5glpo = (cddpo & 0xf00) >> 8; 14403 pi->cdd5glpo = (cddpo & 0xf00) >> 8;
14404 pi->cdd5ghpo = (cddpo & 0xf000) >> 12; 14404 pi->cdd5ghpo = (cddpo & 0xf000) >> 12;
14405 14405
14406 stbcpo = (u16) wlapi_getintvar(shim, BRCMS_SROM_STBCPO); 14406 stbcpo = sprom->stbcpo;
14407 pi->stbc2gpo = stbcpo & 0xf; 14407 pi->stbc2gpo = stbcpo & 0xf;
14408 pi->stbc5gpo = (stbcpo & 0xf0) >> 4; 14408 pi->stbc5gpo = (stbcpo & 0xf0) >> 4;
14409 pi->stbc5glpo = (stbcpo & 0xf00) >> 8; 14409 pi->stbc5glpo = (stbcpo & 0xf00) >> 8;
14410 pi->stbc5ghpo = (stbcpo & 0xf000) >> 12; 14410 pi->stbc5ghpo = (stbcpo & 0xf000) >> 12;
14411 14411
14412 bwduppo = (u16) wlapi_getintvar(shim, BRCMS_SROM_BWDUPPO); 14412 bwduppo = sprom->bwduppo;
14413 pi->bwdup2gpo = bwduppo & 0xf; 14413 pi->bwdup2gpo = bwduppo & 0xf;
14414 pi->bwdup5gpo = (bwduppo & 0xf0) >> 4; 14414 pi->bwdup5gpo = (bwduppo & 0xf0) >> 4;
14415 pi->bwdup5glpo = (bwduppo & 0xf00) >> 8; 14415 pi->bwdup5glpo = (bwduppo & 0xf00) >> 8;
@@ -14419,242 +14419,137 @@ static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14419 band_num++) { 14419 band_num++) {
14420 switch (band_num) { 14420 switch (band_num) {
14421 case 0: 14421 case 0:
14422
14423 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g = 14422 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_2g =
14424 (s8) wlapi_getintvar(shim, 14423 sprom->core_pwr_info[0].maxpwr_2g;
14425 BRCMS_SROM_MAXP2GA0);
14426 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_2g = 14424 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_2g =
14427 (s8) wlapi_getintvar(shim, 14425 sprom->core_pwr_info[1].maxpwr_2g;
14428 BRCMS_SROM_MAXP2GA1);
14429 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_a1 = 14426 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_a1 =
14430 (s16) wlapi_getintvar(shim, 14427 sprom->core_pwr_info[0].pa_2g[0];
14431 BRCMS_SROM_PA2GW0A0);
14432 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_a1 = 14428 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_a1 =
14433 (s16) wlapi_getintvar(shim, 14429 sprom->core_pwr_info[1].pa_2g[0];
14434 BRCMS_SROM_PA2GW0A1);
14435 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b0 = 14430 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b0 =
14436 (s16) wlapi_getintvar(shim, 14431 sprom->core_pwr_info[0].pa_2g[1];
14437 BRCMS_SROM_PA2GW1A0);
14438 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b0 = 14432 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b0 =
14439 (s16) wlapi_getintvar(shim, 14433 sprom->core_pwr_info[1].pa_2g[1];
14440 BRCMS_SROM_PA2GW1A1);
14441 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b1 = 14434 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_2g_b1 =
14442 (s16) wlapi_getintvar(shim, 14435 sprom->core_pwr_info[0].pa_2g[2];
14443 BRCMS_SROM_PA2GW2A0);
14444 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b1 = 14436 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_2g_b1 =
14445 (s16) wlapi_getintvar(shim, 14437 sprom->core_pwr_info[1].pa_2g[2];
14446 BRCMS_SROM_PA2GW2A1);
14447 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_2g = 14438 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_2g =
14448 (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT2GA0); 14439 sprom->core_pwr_info[0].itssi_2g;
14449 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g = 14440 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_2g =
14450 (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT2GA1); 14441 sprom->core_pwr_info[1].itssi_2g;
14451 14442
14452 pi->cck2gpo = (u16) wlapi_getintvar(shim, 14443 pi->cck2gpo = sprom->cck2gpo;
14453 BRCMS_SROM_CCK2GPO); 14444
14454 14445 pi->ofdm2gpo = sprom->ofdm2gpo;
14455 pi->ofdm2gpo = 14446
14456 (u32) wlapi_getintvar(shim, 14447 pi->mcs2gpo[0] = sprom->mcs2gpo[0];
14457 BRCMS_SROM_OFDM2GPO); 14448 pi->mcs2gpo[1] = sprom->mcs2gpo[1];
14458 14449 pi->mcs2gpo[2] = sprom->mcs2gpo[2];
14459 pi->mcs2gpo[0] = 14450 pi->mcs2gpo[3] = sprom->mcs2gpo[3];
14460 (u16) wlapi_getintvar(shim, 14451 pi->mcs2gpo[4] = sprom->mcs2gpo[4];
14461 BRCMS_SROM_MCS2GPO0); 14452 pi->mcs2gpo[5] = sprom->mcs2gpo[5];
14462 pi->mcs2gpo[1] = 14453 pi->mcs2gpo[6] = sprom->mcs2gpo[6];
14463 (u16) wlapi_getintvar(shim, 14454 pi->mcs2gpo[7] = sprom->mcs2gpo[7];
14464 BRCMS_SROM_MCS2GPO1);
14465 pi->mcs2gpo[2] =
14466 (u16) wlapi_getintvar(shim,
14467 BRCMS_SROM_MCS2GPO2);
14468 pi->mcs2gpo[3] =
14469 (u16) wlapi_getintvar(shim,
14470 BRCMS_SROM_MCS2GPO3);
14471 pi->mcs2gpo[4] =
14472 (u16) wlapi_getintvar(shim,
14473 BRCMS_SROM_MCS2GPO4);
14474 pi->mcs2gpo[5] =
14475 (u16) wlapi_getintvar(shim,
14476 BRCMS_SROM_MCS2GPO5);
14477 pi->mcs2gpo[6] =
14478 (u16) wlapi_getintvar(shim,
14479 BRCMS_SROM_MCS2GPO6);
14480 pi->mcs2gpo[7] =
14481 (u16) wlapi_getintvar(shim,
14482 BRCMS_SROM_MCS2GPO7);
14483 break; 14455 break;
14484 case 1: 14456 case 1:
14485 14457
14486 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm = 14458 pi->nphy_pwrctrl_info[PHY_CORE_0].max_pwr_5gm =
14487 (s8) wlapi_getintvar(shim, BRCMS_SROM_MAXP5GA0); 14459 sprom->core_pwr_info[0].maxpwr_5g;
14488 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm = 14460 pi->nphy_pwrctrl_info[PHY_CORE_1].max_pwr_5gm =
14489 (s8) wlapi_getintvar(shim, 14461 sprom->core_pwr_info[1].maxpwr_5g;
14490 BRCMS_SROM_MAXP5GA1);
14491 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_a1 = 14462 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_a1 =
14492 (s16) wlapi_getintvar(shim, 14463 sprom->core_pwr_info[0].pa_5g[0];
14493 BRCMS_SROM_PA5GW0A0);
14494 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_a1 = 14464 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_a1 =
14495 (s16) wlapi_getintvar(shim, 14465 sprom->core_pwr_info[1].pa_5g[0];
14496 BRCMS_SROM_PA5GW0A1);
14497 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b0 = 14466 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b0 =
14498 (s16) wlapi_getintvar(shim, 14467 sprom->core_pwr_info[0].pa_5g[1];
14499 BRCMS_SROM_PA5GW1A0);
14500 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b0 = 14468 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b0 =
14501 (s16) wlapi_getintvar(shim, 14469 sprom->core_pwr_info[1].pa_5g[1];
14502 BRCMS_SROM_PA5GW1A1);
14503 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b1 = 14470 pi->nphy_pwrctrl_info[PHY_CORE_0].pwrdet_5gm_b1 =
14504 (s16) wlapi_getintvar(shim, 14471 sprom->core_pwr_info[0].pa_5g[2];
14505 BRCMS_SROM_PA5GW2A0);
14506 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b1 = 14472 pi->nphy_pwrctrl_info[PHY_CORE_1].pwrdet_5gm_b1 =
14507 (s16) wlapi_getintvar(shim, 14473 sprom->core_pwr_info[1].pa_5g[2];
14508 BRCMS_SROM_PA5GW2A1);
14509 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_5gm = 14474 pi->nphy_pwrctrl_info[PHY_CORE_0].idle_targ_5gm =
14510 (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT5GA0); 14475 sprom->core_pwr_info[0].itssi_5g;
14511 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm = 14476 pi->nphy_pwrctrl_info[PHY_CORE_1].idle_targ_5gm =
14512 (s8) wlapi_getintvar(shim, BRCMS_SROM_ITT5GA1); 14477 sprom->core_pwr_info[1].itssi_5g;
14513 14478
14514 pi->ofdm5gpo = 14479 pi->ofdm5gpo = sprom->ofdm5gpo;
14515 (u32) wlapi_getintvar(shim, 14480
14516 BRCMS_SROM_OFDM5GPO); 14481 pi->mcs5gpo[0] = sprom->mcs5gpo[0];
14517 14482 pi->mcs5gpo[1] = sprom->mcs5gpo[1];
14518 pi->mcs5gpo[0] = 14483 pi->mcs5gpo[2] = sprom->mcs5gpo[2];
14519 (u16) wlapi_getintvar(shim, 14484 pi->mcs5gpo[3] = sprom->mcs5gpo[3];
14520 BRCMS_SROM_MCS5GPO0); 14485 pi->mcs5gpo[4] = sprom->mcs5gpo[4];
14521 pi->mcs5gpo[1] = 14486 pi->mcs5gpo[5] = sprom->mcs5gpo[5];
14522 (u16) wlapi_getintvar(shim, 14487 pi->mcs5gpo[6] = sprom->mcs5gpo[6];
14523 BRCMS_SROM_MCS5GPO1); 14488 pi->mcs5gpo[7] = sprom->mcs5gpo[7];
14524 pi->mcs5gpo[2] =
14525 (u16) wlapi_getintvar(shim,
14526 BRCMS_SROM_MCS5GPO2);
14527 pi->mcs5gpo[3] =
14528 (u16) wlapi_getintvar(shim,
14529 BRCMS_SROM_MCS5GPO3);
14530 pi->mcs5gpo[4] =
14531 (u16) wlapi_getintvar(shim,
14532 BRCMS_SROM_MCS5GPO4);
14533 pi->mcs5gpo[5] =
14534 (u16) wlapi_getintvar(shim,
14535 BRCMS_SROM_MCS5GPO5);
14536 pi->mcs5gpo[6] =
14537 (u16) wlapi_getintvar(shim,
14538 BRCMS_SROM_MCS5GPO6);
14539 pi->mcs5gpo[7] =
14540 (u16) wlapi_getintvar(shim,
14541 BRCMS_SROM_MCS5GPO7);
14542 break; 14489 break;
14543 case 2: 14490 case 2:
14544 14491
14545 pi->nphy_pwrctrl_info[0].max_pwr_5gl = 14492 pi->nphy_pwrctrl_info[0].max_pwr_5gl =
14546 (s8) wlapi_getintvar(shim, 14493 sprom->core_pwr_info[0].maxpwr_5gl;
14547 BRCMS_SROM_MAXP5GLA0);
14548 pi->nphy_pwrctrl_info[1].max_pwr_5gl = 14494 pi->nphy_pwrctrl_info[1].max_pwr_5gl =
14549 (s8) wlapi_getintvar(shim, 14495 sprom->core_pwr_info[1].maxpwr_5gl;
14550 BRCMS_SROM_MAXP5GLA1);
14551 pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 = 14496 pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 =
14552 (s16) wlapi_getintvar(shim, 14497 sprom->core_pwr_info[0].pa_5gl[0];
14553 BRCMS_SROM_PA5GLW0A0);
14554 pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 = 14498 pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 =
14555 (s16) wlapi_getintvar(shim, 14499 sprom->core_pwr_info[1].pa_5gl[0];
14556 BRCMS_SROM_PA5GLW0A1);
14557 pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 = 14500 pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 =
14558 (s16) wlapi_getintvar(shim, 14501 sprom->core_pwr_info[0].pa_5gl[1];
14559 BRCMS_SROM_PA5GLW1A0);
14560 pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 = 14502 pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 =
14561 (s16) wlapi_getintvar(shim, 14503 sprom->core_pwr_info[1].pa_5gl[1];
14562 BRCMS_SROM_PA5GLW1A1);
14563 pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 = 14504 pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 =
14564 (s16) wlapi_getintvar(shim, 14505 sprom->core_pwr_info[0].pa_5gl[2];
14565 BRCMS_SROM_PA5GLW2A0);
14566 pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 = 14506 pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 =
14567 (s16) wlapi_getintvar(shim, 14507 sprom->core_pwr_info[1].pa_5gl[2];
14568 BRCMS_SROM_PA5GLW2A1);
14569 pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0; 14508 pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0;
14570 pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0; 14509 pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0;
14571 14510
14572 pi->ofdm5glpo = 14511 pi->ofdm5glpo = sprom->ofdm5glpo;
14573 (u32) wlapi_getintvar(shim, 14512
14574 BRCMS_SROM_OFDM5GLPO); 14513 pi->mcs5glpo[0] = sprom->mcs5glpo[0];
14575 14514 pi->mcs5glpo[1] = sprom->mcs5glpo[1];
14576 pi->mcs5glpo[0] = 14515 pi->mcs5glpo[2] = sprom->mcs5glpo[2];
14577 (u16) wlapi_getintvar(shim, 14516 pi->mcs5glpo[3] = sprom->mcs5glpo[3];
14578 BRCMS_SROM_MCS5GLPO0); 14517 pi->mcs5glpo[4] = sprom->mcs5glpo[4];
14579 pi->mcs5glpo[1] = 14518 pi->mcs5glpo[5] = sprom->mcs5glpo[5];
14580 (u16) wlapi_getintvar(shim, 14519 pi->mcs5glpo[6] = sprom->mcs5glpo[6];
14581 BRCMS_SROM_MCS5GLPO1); 14520 pi->mcs5glpo[7] = sprom->mcs5glpo[7];
14582 pi->mcs5glpo[2] =
14583 (u16) wlapi_getintvar(shim,
14584 BRCMS_SROM_MCS5GLPO2);
14585 pi->mcs5glpo[3] =
14586 (u16) wlapi_getintvar(shim,
14587 BRCMS_SROM_MCS5GLPO3);
14588 pi->mcs5glpo[4] =
14589 (u16) wlapi_getintvar(shim,
14590 BRCMS_SROM_MCS5GLPO4);
14591 pi->mcs5glpo[5] =
14592 (u16) wlapi_getintvar(shim,
14593 BRCMS_SROM_MCS5GLPO5);
14594 pi->mcs5glpo[6] =
14595 (u16) wlapi_getintvar(shim,
14596 BRCMS_SROM_MCS5GLPO6);
14597 pi->mcs5glpo[7] =
14598 (u16) wlapi_getintvar(shim,
14599 BRCMS_SROM_MCS5GLPO7);
14600 break; 14521 break;
14601 case 3: 14522 case 3:
14602 14523
14603 pi->nphy_pwrctrl_info[0].max_pwr_5gh = 14524 pi->nphy_pwrctrl_info[0].max_pwr_5gh =
14604 (s8) wlapi_getintvar(shim, 14525 sprom->core_pwr_info[0].maxpwr_5gh;
14605 BRCMS_SROM_MAXP5GHA0);
14606 pi->nphy_pwrctrl_info[1].max_pwr_5gh = 14526 pi->nphy_pwrctrl_info[1].max_pwr_5gh =
14607 (s8) wlapi_getintvar(shim, 14527 sprom->core_pwr_info[1].maxpwr_5gh;
14608 BRCMS_SROM_MAXP5GHA1);
14609 pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 = 14528 pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 =
14610 (s16) wlapi_getintvar(shim, 14529 sprom->core_pwr_info[0].pa_5gh[0];
14611 BRCMS_SROM_PA5GHW0A0);
14612 pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 = 14530 pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 =
14613 (s16) wlapi_getintvar(shim, 14531 sprom->core_pwr_info[1].pa_5gh[0];
14614 BRCMS_SROM_PA5GHW0A1);
14615 pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 = 14532 pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 =
14616 (s16) wlapi_getintvar(shim, 14533 sprom->core_pwr_info[0].pa_5gh[1];
14617 BRCMS_SROM_PA5GHW1A0);
14618 pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 = 14534 pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 =
14619 (s16) wlapi_getintvar(shim, 14535 sprom->core_pwr_info[1].pa_5gh[1];
14620 BRCMS_SROM_PA5GHW1A1);
14621 pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 = 14536 pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 =
14622 (s16) wlapi_getintvar(shim, 14537 sprom->core_pwr_info[0].pa_5gh[2];
14623 BRCMS_SROM_PA5GHW2A0);
14624 pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 = 14538 pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 =
14625 (s16) wlapi_getintvar(shim, 14539 sprom->core_pwr_info[1].pa_5gh[2];
14626 BRCMS_SROM_PA5GHW2A1);
14627 pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0; 14540 pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0;
14628 pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0; 14541 pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0;
14629 14542
14630 pi->ofdm5ghpo = 14543 pi->ofdm5ghpo = sprom->ofdm5ghpo;
14631 (u32) wlapi_getintvar(shim, 14544
14632 BRCMS_SROM_OFDM5GHPO); 14545 pi->mcs5ghpo[0] = sprom->mcs5ghpo[0];
14633 14546 pi->mcs5ghpo[1] = sprom->mcs5ghpo[1];
14634 pi->mcs5ghpo[0] = 14547 pi->mcs5ghpo[2] = sprom->mcs5ghpo[2];
14635 (u16) wlapi_getintvar(shim, 14548 pi->mcs5ghpo[3] = sprom->mcs5ghpo[3];
14636 BRCMS_SROM_MCS5GHPO0); 14549 pi->mcs5ghpo[4] = sprom->mcs5ghpo[4];
14637 pi->mcs5ghpo[1] = 14550 pi->mcs5ghpo[5] = sprom->mcs5ghpo[5];
14638 (u16) wlapi_getintvar(shim, 14551 pi->mcs5ghpo[6] = sprom->mcs5ghpo[6];
14639 BRCMS_SROM_MCS5GHPO1); 14552 pi->mcs5ghpo[7] = sprom->mcs5ghpo[7];
14640 pi->mcs5ghpo[2] =
14641 (u16) wlapi_getintvar(shim,
14642 BRCMS_SROM_MCS5GHPO2);
14643 pi->mcs5ghpo[3] =
14644 (u16) wlapi_getintvar(shim,
14645 BRCMS_SROM_MCS5GHPO3);
14646 pi->mcs5ghpo[4] =
14647 (u16) wlapi_getintvar(shim,
14648 BRCMS_SROM_MCS5GHPO4);
14649 pi->mcs5ghpo[5] =
14650 (u16) wlapi_getintvar(shim,
14651 BRCMS_SROM_MCS5GHPO5);
14652 pi->mcs5ghpo[6] =
14653 (u16) wlapi_getintvar(shim,
14654 BRCMS_SROM_MCS5GHPO6);
14655 pi->mcs5ghpo[7] =
14656 (u16) wlapi_getintvar(shim,
14657 BRCMS_SROM_MCS5GHPO7);
14658 break; 14553 break;
14659 } 14554 }
14660 } 14555 }
@@ -14664,45 +14559,34 @@ static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi)
14664 14559
14665static bool wlc_phy_txpwr_srom_read_nphy(struct brcms_phy *pi) 14560static bool wlc_phy_txpwr_srom_read_nphy(struct brcms_phy *pi)
14666{ 14561{
14667 struct phy_shim_info *shim = pi->sh->physhim; 14562 struct ssb_sprom *sprom = &pi->d11core->bus->sprom;
14668 14563
14669 pi->antswitch = (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWITCH); 14564 pi->antswitch = sprom->antswitch;
14670 pi->aa2g = (u8) wlapi_getintvar(shim, BRCMS_SROM_AA2G); 14565 pi->aa2g = sprom->ant_available_bg;
14671 pi->aa5g = (u8) wlapi_getintvar(shim, BRCMS_SROM_AA5G); 14566 pi->aa5g = sprom->ant_available_a;
14672 14567
14673 pi->srom_fem2g.tssipos = (u8) wlapi_getintvar(shim, 14568 pi->srom_fem2g.tssipos = sprom->fem.ghz2.tssipos;
14674 BRCMS_SROM_TSSIPOS2G); 14569 pi->srom_fem2g.extpagain = sprom->fem.ghz2.extpa_gain;
14675 pi->srom_fem2g.extpagain = (u8) wlapi_getintvar(shim, 14570 pi->srom_fem2g.pdetrange = sprom->fem.ghz2.pdet_range;
14676 BRCMS_SROM_EXTPAGAIN2G); 14571 pi->srom_fem2g.triso = sprom->fem.ghz2.tr_iso;
14677 pi->srom_fem2g.pdetrange = (u8) wlapi_getintvar(shim, 14572 pi->srom_fem2g.antswctrllut = sprom->fem.ghz2.antswlut;
14678 BRCMS_SROM_PDETRANGE2G); 14573
14679 pi->srom_fem2g.triso = (u8) wlapi_getintvar(shim, BRCMS_SROM_TRISO2G); 14574 pi->srom_fem5g.tssipos = sprom->fem.ghz5.tssipos;
14680 pi->srom_fem2g.antswctrllut = 14575 pi->srom_fem5g.extpagain = sprom->fem.ghz5.extpa_gain;
14681 (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL2G); 14576 pi->srom_fem5g.pdetrange = sprom->fem.ghz5.pdet_range;
14682 14577 pi->srom_fem5g.triso = sprom->fem.ghz5.tr_iso;
14683 pi->srom_fem5g.tssipos = (u8) wlapi_getintvar(shim, 14578 if (sprom->fem.ghz5.antswlut)
14684 BRCMS_SROM_TSSIPOS5G); 14579 pi->srom_fem5g.antswctrllut = sprom->fem.ghz5.antswlut;
14685 pi->srom_fem5g.extpagain = (u8) wlapi_getintvar(shim,
14686 BRCMS_SROM_EXTPAGAIN5G);
14687 pi->srom_fem5g.pdetrange = (u8) wlapi_getintvar(shim,
14688 BRCMS_SROM_PDETRANGE5G);
14689 pi->srom_fem5g.triso = (u8) wlapi_getintvar(shim, BRCMS_SROM_TRISO5G);
14690 if (wlapi_getvar(shim, BRCMS_SROM_ANTSWCTL5G))
14691 pi->srom_fem5g.antswctrllut =
14692 (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL5G);
14693 else 14580 else
14694 pi->srom_fem5g.antswctrllut = 14581 pi->srom_fem5g.antswctrllut = sprom->fem.ghz2.antswlut;
14695 (u8) wlapi_getintvar(shim, BRCMS_SROM_ANTSWCTL2G);
14696 14582
14697 wlc_phy_txpower_ipa_upd(pi); 14583 wlc_phy_txpower_ipa_upd(pi);
14698 14584
14699 pi->phy_txcore_disable_temp = 14585 pi->phy_txcore_disable_temp = sprom->tempthresh;
14700 (s16) wlapi_getintvar(shim, BRCMS_SROM_TEMPTHRESH);
14701 if (pi->phy_txcore_disable_temp == 0) 14586 if (pi->phy_txcore_disable_temp == 0)
14702 pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP; 14587 pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
14703 14588
14704 pi->phy_tempsense_offset = (s8) wlapi_getintvar(shim, 14589 pi->phy_tempsense_offset = sprom->tempoffset;
14705 BRCMS_SROM_TEMPOFFSET);
14706 if (pi->phy_tempsense_offset != 0) { 14590 if (pi->phy_tempsense_offset != 0) {
14707 if (pi->phy_tempsense_offset > 14591 if (pi->phy_tempsense_offset >
14708 (NPHY_SROM_TEMPSHIFT + NPHY_SROM_MAXTEMPOFFSET)) 14592 (NPHY_SROM_TEMPSHIFT + NPHY_SROM_MAXTEMPOFFSET))
@@ -14717,8 +14601,7 @@ static bool wlc_phy_txpwr_srom_read_nphy(struct brcms_phy *pi)
14717 pi->phy_txcore_enable_temp = 14601 pi->phy_txcore_enable_temp =
14718 pi->phy_txcore_disable_temp - PHY_HYSTERESIS_DELTATEMP; 14602 pi->phy_txcore_disable_temp - PHY_HYSTERESIS_DELTATEMP;
14719 14603
14720 pi->phycal_tempdelta = 14604 pi->phycal_tempdelta = sprom->phycal_tempdelta;
14721 (u8) wlapi_getintvar(shim, BRCMS_SROM_PHYCAL_TEMPDELTA);
14722 if (pi->phycal_tempdelta > NPHY_CAL_MAXTEMPDELTA) 14605 if (pi->phycal_tempdelta > NPHY_CAL_MAXTEMPDELTA)
14723 pi->phycal_tempdelta = 0; 14606 pi->phycal_tempdelta = 0;
14724 14607
@@ -21460,7 +21343,7 @@ void wlc_phy_antsel_init(struct brcms_phy_pub *ppi, bool lut_init)
21460 write_phy_reg(pi, 0xc8, 0x0); 21343 write_phy_reg(pi, 0xc8, 0x0);
21461 write_phy_reg(pi, 0xc9, 0x0); 21344 write_phy_reg(pi, 0xc9, 0x0);
21462 21345
21463 ai_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY); 21346 bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc, mask, mask);
21464 21347
21465 mc = bcma_read32(pi->d11core, D11REGOFFS(maccontrol)); 21348 mc = bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
21466 mc &= ~MCTL_GPOUT_SEL_MASK; 21349 mc &= ~MCTL_GPOUT_SEL_MASK;
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c b/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c
index 5926854f62e2..a0de5db0cd64 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.c
@@ -214,12 +214,3 @@ wlapi_copyto_objmem(struct phy_shim_info *physhim, uint offset, const void *buf,
214{ 214{
215 brcms_b_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel); 215 brcms_b_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel);
216} 216}
217
218char *wlapi_getvar(struct phy_shim_info *physhim, enum brcms_srom_id id)
219{
220 return getvar(physhim->wlc_hw->sih, id);
221}
222int wlapi_getintvar(struct phy_shim_info *physhim, enum brcms_srom_id id)
223{
224 return getintvar(physhim->wlc_hw->sih, id);
225}
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h b/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h
index 9168c459b185..2c5b66b75970 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h
@@ -175,8 +175,5 @@ extern void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint,
175extern void wlapi_high_update_phy_mode(struct phy_shim_info *physhim, 175extern void wlapi_high_update_phy_mode(struct phy_shim_info *physhim,
176 u32 phy_mode); 176 u32 phy_mode);
177extern u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim); 177extern u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
178extern char *wlapi_getvar(struct phy_shim_info *physhim, enum brcms_srom_id id);
179extern int wlapi_getintvar(struct phy_shim_info *physhim,
180 enum brcms_srom_id id);
181 178
182#endif /* _BRCM_PHY_SHIM_H_ */ 179#endif /* _BRCM_PHY_SHIM_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/pub.h b/drivers/net/wireless/brcm80211/brcmsmac/pub.h
index f0038ad7d7bf..aa5d67f8d874 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/pub.h
+++ b/drivers/net/wireless/brcm80211/brcmsmac/pub.h
@@ -22,232 +22,6 @@
22#include "types.h" 22#include "types.h"
23#include "defs.h" 23#include "defs.h"
24 24
25enum brcms_srom_id {
26 BRCMS_SROM_NULL,
27 BRCMS_SROM_CONT,
28 BRCMS_SROM_AA2G,
29 BRCMS_SROM_AA5G,
30 BRCMS_SROM_AG0,
31 BRCMS_SROM_AG1,
32 BRCMS_SROM_AG2,
33 BRCMS_SROM_AG3,
34 BRCMS_SROM_ANTSWCTL2G,
35 BRCMS_SROM_ANTSWCTL5G,
36 BRCMS_SROM_ANTSWITCH,
37 BRCMS_SROM_BOARDFLAGS2,
38 BRCMS_SROM_BOARDFLAGS,
39 BRCMS_SROM_BOARDNUM,
40 BRCMS_SROM_BOARDREV,
41 BRCMS_SROM_BOARDTYPE,
42 BRCMS_SROM_BW40PO,
43 BRCMS_SROM_BWDUPPO,
44 BRCMS_SROM_BXA2G,
45 BRCMS_SROM_BXA5G,
46 BRCMS_SROM_CC,
47 BRCMS_SROM_CCK2GPO,
48 BRCMS_SROM_CCKBW202GPO,
49 BRCMS_SROM_CCKBW20UL2GPO,
50 BRCMS_SROM_CCODE,
51 BRCMS_SROM_CDDPO,
52 BRCMS_SROM_DEVID,
53 BRCMS_SROM_ET1MACADDR,
54 BRCMS_SROM_EXTPAGAIN2G,
55 BRCMS_SROM_EXTPAGAIN5G,
56 BRCMS_SROM_FREQOFFSET_CORR,
57 BRCMS_SROM_HW_IQCAL_EN,
58 BRCMS_SROM_IL0MACADDR,
59 BRCMS_SROM_IQCAL_SWP_DIS,
60 BRCMS_SROM_LEDBH0,
61 BRCMS_SROM_LEDBH1,
62 BRCMS_SROM_LEDBH2,
63 BRCMS_SROM_LEDBH3,
64 BRCMS_SROM_LEDDC,
65 BRCMS_SROM_LEGOFDM40DUPPO,
66 BRCMS_SROM_LEGOFDMBW202GPO,
67 BRCMS_SROM_LEGOFDMBW205GHPO,
68 BRCMS_SROM_LEGOFDMBW205GLPO,
69 BRCMS_SROM_LEGOFDMBW205GMPO,
70 BRCMS_SROM_LEGOFDMBW20UL2GPO,
71 BRCMS_SROM_LEGOFDMBW20UL5GHPO,
72 BRCMS_SROM_LEGOFDMBW20UL5GLPO,
73 BRCMS_SROM_LEGOFDMBW20UL5GMPO,
74 BRCMS_SROM_MACADDR,
75 BRCMS_SROM_MCS2GPO0,
76 BRCMS_SROM_MCS2GPO1,
77 BRCMS_SROM_MCS2GPO2,
78 BRCMS_SROM_MCS2GPO3,
79 BRCMS_SROM_MCS2GPO4,
80 BRCMS_SROM_MCS2GPO5,
81 BRCMS_SROM_MCS2GPO6,
82 BRCMS_SROM_MCS2GPO7,
83 BRCMS_SROM_MCS32PO,
84 BRCMS_SROM_MCS5GHPO0,
85 BRCMS_SROM_MCS5GHPO1,
86 BRCMS_SROM_MCS5GHPO2,
87 BRCMS_SROM_MCS5GHPO3,
88 BRCMS_SROM_MCS5GHPO4,
89 BRCMS_SROM_MCS5GHPO5,
90 BRCMS_SROM_MCS5GHPO6,
91 BRCMS_SROM_MCS5GHPO7,
92 BRCMS_SROM_MCS5GLPO0,
93 BRCMS_SROM_MCS5GLPO1,
94 BRCMS_SROM_MCS5GLPO2,
95 BRCMS_SROM_MCS5GLPO3,
96 BRCMS_SROM_MCS5GLPO4,
97 BRCMS_SROM_MCS5GLPO5,
98 BRCMS_SROM_MCS5GLPO6,
99 BRCMS_SROM_MCS5GLPO7,
100 BRCMS_SROM_MCS5GPO0,
101 BRCMS_SROM_MCS5GPO1,
102 BRCMS_SROM_MCS5GPO2,
103 BRCMS_SROM_MCS5GPO3,
104 BRCMS_SROM_MCS5GPO4,
105 BRCMS_SROM_MCS5GPO5,
106 BRCMS_SROM_MCS5GPO6,
107 BRCMS_SROM_MCS5GPO7,
108 BRCMS_SROM_MCSBW202GPO,
109 BRCMS_SROM_MCSBW205GHPO,
110 BRCMS_SROM_MCSBW205GLPO,
111 BRCMS_SROM_MCSBW205GMPO,
112 BRCMS_SROM_MCSBW20UL2GPO,
113 BRCMS_SROM_MCSBW20UL5GHPO,
114 BRCMS_SROM_MCSBW20UL5GLPO,
115 BRCMS_SROM_MCSBW20UL5GMPO,
116 BRCMS_SROM_MCSBW402GPO,
117 BRCMS_SROM_MCSBW405GHPO,
118 BRCMS_SROM_MCSBW405GLPO,
119 BRCMS_SROM_MCSBW405GMPO,
120 BRCMS_SROM_MEASPOWER,
121 BRCMS_SROM_OFDM2GPO,
122 BRCMS_SROM_OFDM5GHPO,
123 BRCMS_SROM_OFDM5GLPO,
124 BRCMS_SROM_OFDM5GPO,
125 BRCMS_SROM_OPO,
126 BRCMS_SROM_PA0B0,
127 BRCMS_SROM_PA0B1,
128 BRCMS_SROM_PA0B2,
129 BRCMS_SROM_PA0ITSSIT,
130 BRCMS_SROM_PA0MAXPWR,
131 BRCMS_SROM_PA1B0,
132 BRCMS_SROM_PA1B1,
133 BRCMS_SROM_PA1B2,
134 BRCMS_SROM_PA1HIB0,
135 BRCMS_SROM_PA1HIB1,
136 BRCMS_SROM_PA1HIB2,
137 BRCMS_SROM_PA1HIMAXPWR,
138 BRCMS_SROM_PA1ITSSIT,
139 BRCMS_SROM_PA1LOB0,
140 BRCMS_SROM_PA1LOB1,
141 BRCMS_SROM_PA1LOB2,
142 BRCMS_SROM_PA1LOMAXPWR,
143 BRCMS_SROM_PA1MAXPWR,
144 BRCMS_SROM_PDETRANGE2G,
145 BRCMS_SROM_PDETRANGE5G,
146 BRCMS_SROM_PHYCAL_TEMPDELTA,
147 BRCMS_SROM_RAWTEMPSENSE,
148 BRCMS_SROM_REGREV,
149 BRCMS_SROM_REV,
150 BRCMS_SROM_RSSISAV2G,
151 BRCMS_SROM_RSSISAV5G,
152 BRCMS_SROM_RSSISMC2G,
153 BRCMS_SROM_RSSISMC5G,
154 BRCMS_SROM_RSSISMF2G,
155 BRCMS_SROM_RSSISMF5G,
156 BRCMS_SROM_RXCHAIN,
157 BRCMS_SROM_RXPO2G,
158 BRCMS_SROM_RXPO5G,
159 BRCMS_SROM_STBCPO,
160 BRCMS_SROM_TEMPCORRX,
161 BRCMS_SROM_TEMPOFFSET,
162 BRCMS_SROM_TEMPSENSE_OPTION,
163 BRCMS_SROM_TEMPSENSE_SLOPE,
164 BRCMS_SROM_TEMPTHRESH,
165 BRCMS_SROM_TRI2G,
166 BRCMS_SROM_TRI5GH,
167 BRCMS_SROM_TRI5GL,
168 BRCMS_SROM_TRI5G,
169 BRCMS_SROM_TRISO2G,
170 BRCMS_SROM_TRISO5G,
171 BRCMS_SROM_TSSIPOS2G,
172 BRCMS_SROM_TSSIPOS5G,
173 BRCMS_SROM_TXCHAIN,
174 /*
175 * per-path identifiers (see srom.c)
176 */
177 BRCMS_SROM_ITT2GA0,
178 BRCMS_SROM_ITT2GA1,
179 BRCMS_SROM_ITT2GA2,
180 BRCMS_SROM_ITT2GA3,
181 BRCMS_SROM_ITT5GA0,
182 BRCMS_SROM_ITT5GA1,
183 BRCMS_SROM_ITT5GA2,
184 BRCMS_SROM_ITT5GA3,
185 BRCMS_SROM_MAXP2GA0,
186 BRCMS_SROM_MAXP2GA1,
187 BRCMS_SROM_MAXP2GA2,
188 BRCMS_SROM_MAXP2GA3,
189 BRCMS_SROM_MAXP5GA0,
190 BRCMS_SROM_MAXP5GA1,
191 BRCMS_SROM_MAXP5GA2,
192 BRCMS_SROM_MAXP5GA3,
193 BRCMS_SROM_MAXP5GHA0,
194 BRCMS_SROM_MAXP5GHA1,
195 BRCMS_SROM_MAXP5GHA2,
196 BRCMS_SROM_MAXP5GHA3,
197 BRCMS_SROM_MAXP5GLA0,
198 BRCMS_SROM_MAXP5GLA1,
199 BRCMS_SROM_MAXP5GLA2,
200 BRCMS_SROM_MAXP5GLA3,
201 BRCMS_SROM_PA2GW0A0,
202 BRCMS_SROM_PA2GW0A1,
203 BRCMS_SROM_PA2GW0A2,
204 BRCMS_SROM_PA2GW0A3,
205 BRCMS_SROM_PA2GW1A0,
206 BRCMS_SROM_PA2GW1A1,
207 BRCMS_SROM_PA2GW1A2,
208 BRCMS_SROM_PA2GW1A3,
209 BRCMS_SROM_PA2GW2A0,
210 BRCMS_SROM_PA2GW2A1,
211 BRCMS_SROM_PA2GW2A2,
212 BRCMS_SROM_PA2GW2A3,
213 BRCMS_SROM_PA5GHW0A0,
214 BRCMS_SROM_PA5GHW0A1,
215 BRCMS_SROM_PA5GHW0A2,
216 BRCMS_SROM_PA5GHW0A3,
217 BRCMS_SROM_PA5GHW1A0,
218 BRCMS_SROM_PA5GHW1A1,
219 BRCMS_SROM_PA5GHW1A2,
220 BRCMS_SROM_PA5GHW1A3,
221 BRCMS_SROM_PA5GHW2A0,
222 BRCMS_SROM_PA5GHW2A1,
223 BRCMS_SROM_PA5GHW2A2,
224 BRCMS_SROM_PA5GHW2A3,
225 BRCMS_SROM_PA5GLW0A0,
226 BRCMS_SROM_PA5GLW0A1,
227 BRCMS_SROM_PA5GLW0A2,
228 BRCMS_SROM_PA5GLW0A3,
229 BRCMS_SROM_PA5GLW1A0,
230 BRCMS_SROM_PA5GLW1A1,
231 BRCMS_SROM_PA5GLW1A2,
232 BRCMS_SROM_PA5GLW1A3,
233 BRCMS_SROM_PA5GLW2A0,
234 BRCMS_SROM_PA5GLW2A1,
235 BRCMS_SROM_PA5GLW2A2,
236 BRCMS_SROM_PA5GLW2A3,
237 BRCMS_SROM_PA5GW0A0,
238 BRCMS_SROM_PA5GW0A1,
239 BRCMS_SROM_PA5GW0A2,
240 BRCMS_SROM_PA5GW0A3,
241 BRCMS_SROM_PA5GW1A0,
242 BRCMS_SROM_PA5GW1A1,
243 BRCMS_SROM_PA5GW1A2,
244 BRCMS_SROM_PA5GW1A3,
245 BRCMS_SROM_PA5GW2A0,
246 BRCMS_SROM_PA5GW2A1,
247 BRCMS_SROM_PA5GW2A2,
248 BRCMS_SROM_PA5GW2A3,
249};
250
251#define BRCMS_NUMRATES 16 /* max # of rates in a rateset */ 25#define BRCMS_NUMRATES 16 /* max # of rates in a rateset */
252 26
253/* phy types */ 27/* phy types */
@@ -565,8 +339,6 @@ extern void brcms_c_ampdu_flush(struct brcms_c_info *wlc,
565 struct ieee80211_sta *sta, u16 tid); 339 struct ieee80211_sta *sta, u16 tid);
566extern void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid, 340extern void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
567 u8 ba_wsize, uint max_rx_ampdu_bytes); 341 u8 ba_wsize, uint max_rx_ampdu_bytes);
568extern char *getvar(struct si_pub *sih, enum brcms_srom_id id);
569extern int getintvar(struct si_pub *sih, enum brcms_srom_id id);
570extern int brcms_c_module_register(struct brcms_pub *pub, 342extern int brcms_c_module_register(struct brcms_pub *pub,
571 const char *name, struct brcms_info *hdl, 343 const char *name, struct brcms_info *hdl,
572 int (*down_fn)(void *handle)); 344 int (*down_fn)(void *handle));
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/srom.c b/drivers/net/wireless/brcm80211/brcmsmac/srom.c
deleted file mode 100644
index b96f4b9d74bd..000000000000
--- a/drivers/net/wireless/brcm80211/brcmsmac/srom.c
+++ /dev/null
@@ -1,980 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/kernel.h>
18#include <linux/string.h>
19#include <linux/io.h>
20#include <linux/etherdevice.h>
21#include <linux/crc8.h>
22#include <stdarg.h>
23
24#include <chipcommon.h>
25#include <brcmu_utils.h>
26#include "pub.h"
27#include "nicpci.h"
28#include "aiutils.h"
29#include "otp.h"
30#include "srom.h"
31#include "soc.h"
32
33/*
34 * SROM CRC8 polynomial value:
35 *
36 * x^8 + x^7 +x^6 + x^4 + x^2 + 1
37 */
38#define SROM_CRC8_POLY 0xAB
39
40/* Maximum srom: 6 Kilobits == 768 bytes */
41#define SROM_MAX 768
42
43/* PCI fields */
44#define PCI_F0DEVID 48
45
46#define SROM_WORDS 64
47
48#define SROM_SSID 2
49
50#define SROM_WL1LHMAXP 29
51
52#define SROM_WL1LPAB0 30
53#define SROM_WL1LPAB1 31
54#define SROM_WL1LPAB2 32
55
56#define SROM_WL1HPAB0 33
57#define SROM_WL1HPAB1 34
58#define SROM_WL1HPAB2 35
59
60#define SROM_MACHI_IL0 36
61#define SROM_MACMID_IL0 37
62#define SROM_MACLO_IL0 38
63#define SROM_MACHI_ET1 42
64#define SROM_MACMID_ET1 43
65#define SROM_MACLO_ET1 44
66
67#define SROM_BXARSSI2G 40
68#define SROM_BXARSSI5G 41
69
70#define SROM_TRI52G 42
71#define SROM_TRI5GHL 43
72
73#define SROM_RXPO52G 45
74
75#define SROM_AABREV 46
76/* Fields in AABREV */
77#define SROM_BR_MASK 0x00ff
78#define SROM_CC_MASK 0x0f00
79#define SROM_CC_SHIFT 8
80#define SROM_AA0_MASK 0x3000
81#define SROM_AA0_SHIFT 12
82#define SROM_AA1_MASK 0xc000
83#define SROM_AA1_SHIFT 14
84
85#define SROM_WL0PAB0 47
86#define SROM_WL0PAB1 48
87#define SROM_WL0PAB2 49
88
89#define SROM_LEDBH10 50
90#define SROM_LEDBH32 51
91
92#define SROM_WL10MAXP 52
93
94#define SROM_WL1PAB0 53
95#define SROM_WL1PAB1 54
96#define SROM_WL1PAB2 55
97
98#define SROM_ITT 56
99
100#define SROM_BFL 57
101#define SROM_BFL2 28
102
103#define SROM_AG10 58
104
105#define SROM_CCODE 59
106
107#define SROM_OPO 60
108
109#define SROM_CRCREV 63
110
111#define SROM4_WORDS 220
112
113#define SROM4_TXCHAIN_MASK 0x000f
114#define SROM4_RXCHAIN_MASK 0x00f0
115#define SROM4_SWITCH_MASK 0xff00
116
117/* Per-path fields */
118#define MAX_PATH_SROM 4
119
120#define SROM4_CRCREV 219
121
122/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
123 * This is acombined srom for both MIMO and SISO boards, usable in
124 * the .130 4Kilobit OTP with hardware redundancy.
125 */
126#define SROM8_BREV 65
127
128#define SROM8_BFL0 66
129#define SROM8_BFL1 67
130#define SROM8_BFL2 68
131#define SROM8_BFL3 69
132
133#define SROM8_MACHI 70
134#define SROM8_MACMID 71
135#define SROM8_MACLO 72
136
137#define SROM8_CCODE 73
138#define SROM8_REGREV 74
139
140#define SROM8_LEDBH10 75
141#define SROM8_LEDBH32 76
142
143#define SROM8_LEDDC 77
144
145#define SROM8_AA 78
146
147#define SROM8_AG10 79
148#define SROM8_AG32 80
149
150#define SROM8_TXRXC 81
151
152#define SROM8_BXARSSI2G 82
153#define SROM8_BXARSSI5G 83
154#define SROM8_TRI52G 84
155#define SROM8_TRI5GHL 85
156#define SROM8_RXPO52G 86
157
158#define SROM8_FEM2G 87
159#define SROM8_FEM5G 88
160#define SROM8_FEM_ANTSWLUT_MASK 0xf800
161#define SROM8_FEM_ANTSWLUT_SHIFT 11
162#define SROM8_FEM_TR_ISO_MASK 0x0700
163#define SROM8_FEM_TR_ISO_SHIFT 8
164#define SROM8_FEM_PDET_RANGE_MASK 0x00f8
165#define SROM8_FEM_PDET_RANGE_SHIFT 3
166#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
167#define SROM8_FEM_EXTPA_GAIN_SHIFT 1
168#define SROM8_FEM_TSSIPOS_MASK 0x0001
169#define SROM8_FEM_TSSIPOS_SHIFT 0
170
171#define SROM8_THERMAL 89
172
173/* Temp sense related entries */
174#define SROM8_MPWR_RAWTS 90
175#define SROM8_TS_SLP_OPT_CORRX 91
176/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable,
177 * IQSWP: IQ CAL swap disable */
178#define SROM8_FOC_HWIQ_IQSWP 92
179
180/* Temperature delta for PHY calibration */
181#define SROM8_PHYCAL_TEMPDELTA 93
182
183/* Per-path offsets & fields */
184#define SROM8_PATH0 96
185#define SROM8_PATH1 112
186#define SROM8_PATH2 128
187#define SROM8_PATH3 144
188
189#define SROM8_2G_ITT_MAXP 0
190#define SROM8_2G_PA 1
191#define SROM8_5G_ITT_MAXP 4
192#define SROM8_5GLH_MAXP 5
193#define SROM8_5G_PA 6
194#define SROM8_5GL_PA 9
195#define SROM8_5GH_PA 12
196
197/* All the miriad power offsets */
198#define SROM8_2G_CCKPO 160
199
200#define SROM8_2G_OFDMPO 161
201#define SROM8_5G_OFDMPO 163
202#define SROM8_5GL_OFDMPO 165
203#define SROM8_5GH_OFDMPO 167
204
205#define SROM8_2G_MCSPO 169
206#define SROM8_5G_MCSPO 177
207#define SROM8_5GL_MCSPO 185
208#define SROM8_5GH_MCSPO 193
209
210#define SROM8_CDDPO 201
211#define SROM8_STBCPO 202
212#define SROM8_BW40PO 203
213#define SROM8_BWDUPPO 204
214
215/* SISO PA parameters are in the path0 spaces */
216#define SROM8_SISO 96
217
218/* Legacy names for SISO PA paramters */
219#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
220#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
221#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
222#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
223#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
224#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
225#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
226#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
227#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
228#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
229#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
230#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
231#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
232#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
233#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
234
235/* SROM REV 9 */
236#define SROM9_2GPO_CCKBW20 160
237#define SROM9_2GPO_CCKBW20UL 161
238#define SROM9_2GPO_LOFDMBW20 162
239#define SROM9_2GPO_LOFDMBW20UL 164
240
241#define SROM9_5GLPO_LOFDMBW20 166
242#define SROM9_5GLPO_LOFDMBW20UL 168
243#define SROM9_5GMPO_LOFDMBW20 170
244#define SROM9_5GMPO_LOFDMBW20UL 172
245#define SROM9_5GHPO_LOFDMBW20 174
246#define SROM9_5GHPO_LOFDMBW20UL 176
247
248#define SROM9_2GPO_MCSBW20 178
249#define SROM9_2GPO_MCSBW20UL 180
250#define SROM9_2GPO_MCSBW40 182
251
252#define SROM9_5GLPO_MCSBW20 184
253#define SROM9_5GLPO_MCSBW20UL 186
254#define SROM9_5GLPO_MCSBW40 188
255#define SROM9_5GMPO_MCSBW20 190
256#define SROM9_5GMPO_MCSBW20UL 192
257#define SROM9_5GMPO_MCSBW40 194
258#define SROM9_5GHPO_MCSBW20 196
259#define SROM9_5GHPO_MCSBW20UL 198
260#define SROM9_5GHPO_MCSBW40 200
261
262#define SROM9_PO_MCS32 202
263#define SROM9_PO_LOFDM40DUP 203
264
265/* SROM flags (see sromvar_t) */
266
267/* value continues as described by the next entry */
268#define SRFL_MORE 1
269#define SRFL_NOFFS 2 /* value bits can't be all one's */
270#define SRFL_PRHEX 4 /* value is in hexdecimal format */
271#define SRFL_PRSIGN 8 /* value is in signed decimal format */
272#define SRFL_CCODE 0x10 /* value is in country code format */
273#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
274#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
275/* do not generate a nvram param, entry is for mfgc */
276#define SRFL_NOVAR 0x80
277
278/* Max. nvram variable table size */
279#define MAXSZ_NVRAM_VARS 4096
280
281/*
282 * indicates type of value.
283 */
284enum brcms_srom_var_type {
285 BRCMS_SROM_STRING,
286 BRCMS_SROM_SNUMBER,
287 BRCMS_SROM_UNUMBER
288};
289
290/*
291 * storage type for srom variable.
292 *
293 * var_list: for linked list operations.
294 * varid: identifier of the variable.
295 * var_type: type of variable.
296 * buf: variable value when var_type == BRCMS_SROM_STRING.
297 * uval: unsigned variable value when var_type == BRCMS_SROM_UNUMBER.
298 * sval: signed variable value when var_type == BRCMS_SROM_SNUMBER.
299 */
300struct brcms_srom_list_head {
301 struct list_head var_list;
302 enum brcms_srom_id varid;
303 enum brcms_srom_var_type var_type;
304 union {
305 char buf[0];
306 u32 uval;
307 s32 sval;
308 };
309};
310
311struct brcms_sromvar {
312 enum brcms_srom_id varid;
313 u32 revmask;
314 u32 flags;
315 u16 off;
316 u16 mask;
317};
318
319struct brcms_varbuf {
320 char *base; /* pointer to buffer base */
321 char *buf; /* pointer to current position */
322 unsigned int size; /* current (residual) size in bytes */
323};
324
325/*
326 * Assumptions:
327 * - Ethernet address spans across 3 consecutive words
328 *
329 * Table rules:
330 * - Add multiple entries next to each other if a value spans across multiple
331 * words (even multiple fields in the same word) with each entry except the
332 * last having it's SRFL_MORE bit set.
333 * - Ethernet address entry does not follow above rule and must not have
334 * SRFL_MORE bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
335 * - The last entry's name field must be NULL to indicate the end of the table.
336 * Other entries must have non-NULL name.
337 */
338static const struct brcms_sromvar pci_sromvars[] = {
339 {BRCMS_SROM_DEVID, 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID,
340 0xffff},
341 {BRCMS_SROM_BOARDREV, 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
342 {BRCMS_SROM_BOARDFLAGS, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0,
343 0xffff},
344 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL1, 0xffff},
345 {BRCMS_SROM_BOARDFLAGS2, 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2,
346 0xffff},
347 {BRCMS_SROM_CONT, 0, 0, SROM8_BFL3, 0xffff},
348 {BRCMS_SROM_BOARDTYPE, 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
349 {BRCMS_SROM_BOARDNUM, 0xffffff00, 0, SROM8_MACLO, 0xffff},
350 {BRCMS_SROM_REGREV, 0xffffff00, 0, SROM8_REGREV, 0x00ff},
351 {BRCMS_SROM_LEDBH0, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
352 {BRCMS_SROM_LEDBH1, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
353 {BRCMS_SROM_LEDBH2, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
354 {BRCMS_SROM_LEDBH3, 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
355 {BRCMS_SROM_PA0B0, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
356 {BRCMS_SROM_PA0B1, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
357 {BRCMS_SROM_PA0B2, 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
358 {BRCMS_SROM_PA0ITSSIT, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
359 {BRCMS_SROM_PA0MAXPWR, 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
360 {BRCMS_SROM_OPO, 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
361 {BRCMS_SROM_AA2G, 0xffffff00, 0, SROM8_AA, 0x00ff},
362 {BRCMS_SROM_AA5G, 0xffffff00, 0, SROM8_AA, 0xff00},
363 {BRCMS_SROM_AG0, 0xffffff00, 0, SROM8_AG10, 0x00ff},
364 {BRCMS_SROM_AG1, 0xffffff00, 0, SROM8_AG10, 0xff00},
365 {BRCMS_SROM_AG2, 0xffffff00, 0, SROM8_AG32, 0x00ff},
366 {BRCMS_SROM_AG3, 0xffffff00, 0, SROM8_AG32, 0xff00},
367 {BRCMS_SROM_PA1B0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
368 {BRCMS_SROM_PA1B1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
369 {BRCMS_SROM_PA1B2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
370 {BRCMS_SROM_PA1LOB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
371 {BRCMS_SROM_PA1LOB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
372 {BRCMS_SROM_PA1LOB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
373 {BRCMS_SROM_PA1HIB0, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
374 {BRCMS_SROM_PA1HIB1, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
375 {BRCMS_SROM_PA1HIB2, 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
376 {BRCMS_SROM_PA1ITSSIT, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
377 {BRCMS_SROM_PA1MAXPWR, 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
378 {BRCMS_SROM_PA1LOMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
379 {BRCMS_SROM_PA1HIMAXPWR, 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
380 {BRCMS_SROM_BXA2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
381 {BRCMS_SROM_RSSISAV2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
382 {BRCMS_SROM_RSSISMC2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
383 {BRCMS_SROM_RSSISMF2G, 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
384 {BRCMS_SROM_BXA5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
385 {BRCMS_SROM_RSSISAV5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
386 {BRCMS_SROM_RSSISMC5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
387 {BRCMS_SROM_RSSISMF5G, 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
388 {BRCMS_SROM_TRI2G, 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
389 {BRCMS_SROM_TRI5G, 0xffffff00, 0, SROM8_TRI52G, 0xff00},
390 {BRCMS_SROM_TRI5GL, 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
391 {BRCMS_SROM_TRI5GH, 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
392 {BRCMS_SROM_RXPO2G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
393 {BRCMS_SROM_RXPO5G, 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
394 {BRCMS_SROM_TXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
395 SROM4_TXCHAIN_MASK},
396 {BRCMS_SROM_RXCHAIN, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
397 SROM4_RXCHAIN_MASK},
398 {BRCMS_SROM_ANTSWITCH, 0xffffff00, SRFL_NOFFS, SROM8_TXRXC,
399 SROM4_SWITCH_MASK},
400 {BRCMS_SROM_TSSIPOS2G, 0xffffff00, 0, SROM8_FEM2G,
401 SROM8_FEM_TSSIPOS_MASK},
402 {BRCMS_SROM_EXTPAGAIN2G, 0xffffff00, 0, SROM8_FEM2G,
403 SROM8_FEM_EXTPA_GAIN_MASK},
404 {BRCMS_SROM_PDETRANGE2G, 0xffffff00, 0, SROM8_FEM2G,
405 SROM8_FEM_PDET_RANGE_MASK},
406 {BRCMS_SROM_TRISO2G, 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
407 {BRCMS_SROM_ANTSWCTL2G, 0xffffff00, 0, SROM8_FEM2G,
408 SROM8_FEM_ANTSWLUT_MASK},
409 {BRCMS_SROM_TSSIPOS5G, 0xffffff00, 0, SROM8_FEM5G,
410 SROM8_FEM_TSSIPOS_MASK},
411 {BRCMS_SROM_EXTPAGAIN5G, 0xffffff00, 0, SROM8_FEM5G,
412 SROM8_FEM_EXTPA_GAIN_MASK},
413 {BRCMS_SROM_PDETRANGE5G, 0xffffff00, 0, SROM8_FEM5G,
414 SROM8_FEM_PDET_RANGE_MASK},
415 {BRCMS_SROM_TRISO5G, 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
416 {BRCMS_SROM_ANTSWCTL5G, 0xffffff00, 0, SROM8_FEM5G,
417 SROM8_FEM_ANTSWLUT_MASK},
418 {BRCMS_SROM_TEMPTHRESH, 0xffffff00, 0, SROM8_THERMAL, 0xff00},
419 {BRCMS_SROM_TEMPOFFSET, 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
420
421 {BRCMS_SROM_CCODE, 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
422 {BRCMS_SROM_MACADDR, 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
423 {BRCMS_SROM_LEDDC, 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC,
424 0xffff},
425 {BRCMS_SROM_RAWTEMPSENSE, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
426 0x01ff},
427 {BRCMS_SROM_MEASPOWER, 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS,
428 0xfe00},
429 {BRCMS_SROM_TEMPSENSE_SLOPE, 0xffffff00, SRFL_PRHEX,
430 SROM8_TS_SLP_OPT_CORRX, 0x00ff},
431 {BRCMS_SROM_TEMPCORRX, 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
432 0xfc00},
433 {BRCMS_SROM_TEMPSENSE_OPTION, 0xffffff00, SRFL_PRHEX,
434 SROM8_TS_SLP_OPT_CORRX, 0x0300},
435 {BRCMS_SROM_FREQOFFSET_CORR, 0xffffff00, SRFL_PRHEX,
436 SROM8_FOC_HWIQ_IQSWP, 0x000f},
437 {BRCMS_SROM_IQCAL_SWP_DIS, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
438 0x0010},
439 {BRCMS_SROM_HW_IQCAL_EN, 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
440 0x0020},
441 {BRCMS_SROM_PHYCAL_TEMPDELTA, 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA,
442 0x00ff},
443
444 {BRCMS_SROM_CCK2GPO, 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
445 {BRCMS_SROM_OFDM2GPO, 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
446 {BRCMS_SROM_CONT, 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
447 {BRCMS_SROM_OFDM5GPO, 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
448 {BRCMS_SROM_CONT, 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
449 {BRCMS_SROM_OFDM5GLPO, 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
450 {BRCMS_SROM_CONT, 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
451 {BRCMS_SROM_OFDM5GHPO, 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
452 {BRCMS_SROM_CONT, 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
453 {BRCMS_SROM_MCS2GPO0, 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
454 {BRCMS_SROM_MCS2GPO1, 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
455 {BRCMS_SROM_MCS2GPO2, 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
456 {BRCMS_SROM_MCS2GPO3, 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
457 {BRCMS_SROM_MCS2GPO4, 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
458 {BRCMS_SROM_MCS2GPO5, 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
459 {BRCMS_SROM_MCS2GPO6, 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
460 {BRCMS_SROM_MCS2GPO7, 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
461 {BRCMS_SROM_MCS5GPO0, 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
462 {BRCMS_SROM_MCS5GPO1, 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
463 {BRCMS_SROM_MCS5GPO2, 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
464 {BRCMS_SROM_MCS5GPO3, 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
465 {BRCMS_SROM_MCS5GPO4, 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
466 {BRCMS_SROM_MCS5GPO5, 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
467 {BRCMS_SROM_MCS5GPO6, 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
468 {BRCMS_SROM_MCS5GPO7, 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
469 {BRCMS_SROM_MCS5GLPO0, 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
470 {BRCMS_SROM_MCS5GLPO1, 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
471 {BRCMS_SROM_MCS5GLPO2, 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
472 {BRCMS_SROM_MCS5GLPO3, 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
473 {BRCMS_SROM_MCS5GLPO4, 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
474 {BRCMS_SROM_MCS5GLPO5, 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
475 {BRCMS_SROM_MCS5GLPO6, 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
476 {BRCMS_SROM_MCS5GLPO7, 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
477 {BRCMS_SROM_MCS5GHPO0, 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
478 {BRCMS_SROM_MCS5GHPO1, 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
479 {BRCMS_SROM_MCS5GHPO2, 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
480 {BRCMS_SROM_MCS5GHPO3, 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
481 {BRCMS_SROM_MCS5GHPO4, 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
482 {BRCMS_SROM_MCS5GHPO5, 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
483 {BRCMS_SROM_MCS5GHPO6, 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
484 {BRCMS_SROM_MCS5GHPO7, 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
485 {BRCMS_SROM_CDDPO, 0x00000100, 0, SROM8_CDDPO, 0xffff},
486 {BRCMS_SROM_STBCPO, 0x00000100, 0, SROM8_STBCPO, 0xffff},
487 {BRCMS_SROM_BW40PO, 0x00000100, 0, SROM8_BW40PO, 0xffff},
488 {BRCMS_SROM_BWDUPPO, 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
489
490 /* power per rate from sromrev 9 */
491 {BRCMS_SROM_CCKBW202GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
492 {BRCMS_SROM_CCKBW20UL2GPO, 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
493 {BRCMS_SROM_LEGOFDMBW202GPO, 0xfffffe00, SRFL_MORE,
494 SROM9_2GPO_LOFDMBW20, 0xffff},
495 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
496 {BRCMS_SROM_LEGOFDMBW20UL2GPO, 0xfffffe00, SRFL_MORE,
497 SROM9_2GPO_LOFDMBW20UL, 0xffff},
498 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
499 {BRCMS_SROM_LEGOFDMBW205GLPO, 0xfffffe00, SRFL_MORE,
500 SROM9_5GLPO_LOFDMBW20, 0xffff},
501 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
502 {BRCMS_SROM_LEGOFDMBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
503 SROM9_5GLPO_LOFDMBW20UL, 0xffff},
504 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
505 {BRCMS_SROM_LEGOFDMBW205GMPO, 0xfffffe00, SRFL_MORE,
506 SROM9_5GMPO_LOFDMBW20, 0xffff},
507 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
508 {BRCMS_SROM_LEGOFDMBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
509 SROM9_5GMPO_LOFDMBW20UL, 0xffff},
510 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
511 {BRCMS_SROM_LEGOFDMBW205GHPO, 0xfffffe00, SRFL_MORE,
512 SROM9_5GHPO_LOFDMBW20, 0xffff},
513 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
514 {BRCMS_SROM_LEGOFDMBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
515 SROM9_5GHPO_LOFDMBW20UL, 0xffff},
516 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
517 {BRCMS_SROM_MCSBW202GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20,
518 0xffff},
519 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
520 {BRCMS_SROM_MCSBW20UL2GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL,
521 0xffff},
522 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
523 {BRCMS_SROM_MCSBW402GPO, 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40,
524 0xffff},
525 {BRCMS_SROM_CONT, 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
526 {BRCMS_SROM_MCSBW205GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20,
527 0xffff},
528 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
529 {BRCMS_SROM_MCSBW20UL5GLPO, 0xfffffe00, SRFL_MORE,
530 SROM9_5GLPO_MCSBW20UL, 0xffff},
531 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
532 {BRCMS_SROM_MCSBW405GLPO, 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40,
533 0xffff},
534 {BRCMS_SROM_CONT, 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
535 {BRCMS_SROM_MCSBW205GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20,
536 0xffff},
537 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
538 {BRCMS_SROM_MCSBW20UL5GMPO, 0xfffffe00, SRFL_MORE,
539 SROM9_5GMPO_MCSBW20UL, 0xffff},
540 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
541 {BRCMS_SROM_MCSBW405GMPO, 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40,
542 0xffff},
543 {BRCMS_SROM_CONT, 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
544 {BRCMS_SROM_MCSBW205GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20,
545 0xffff},
546 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
547 {BRCMS_SROM_MCSBW20UL5GHPO, 0xfffffe00, SRFL_MORE,
548 SROM9_5GHPO_MCSBW20UL, 0xffff},
549 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
550 {BRCMS_SROM_MCSBW405GHPO, 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40,
551 0xffff},
552 {BRCMS_SROM_CONT, 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
553 {BRCMS_SROM_MCS32PO, 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
554 {BRCMS_SROM_LEGOFDM40DUPPO, 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
555
556 {BRCMS_SROM_NULL, 0, 0, 0, 0}
557};
558
559static const struct brcms_sromvar perpath_pci_sromvars[] = {
560 {BRCMS_SROM_MAXP2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
561 {BRCMS_SROM_ITT2GA0, 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
562 {BRCMS_SROM_ITT5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
563 {BRCMS_SROM_PA2GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
564 {BRCMS_SROM_PA2GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
565 {BRCMS_SROM_PA2GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
566 {BRCMS_SROM_MAXP5GA0, 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
567 {BRCMS_SROM_MAXP5GHA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
568 {BRCMS_SROM_MAXP5GLA0, 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
569 {BRCMS_SROM_PA5GW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
570 {BRCMS_SROM_PA5GW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
571 {BRCMS_SROM_PA5GW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
572 {BRCMS_SROM_PA5GLW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
573 {BRCMS_SROM_PA5GLW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1,
574 0xffff},
575 {BRCMS_SROM_PA5GLW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2,
576 0xffff},
577 {BRCMS_SROM_PA5GHW0A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
578 {BRCMS_SROM_PA5GHW1A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1,
579 0xffff},
580 {BRCMS_SROM_PA5GHW2A0, 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2,
581 0xffff},
582 {BRCMS_SROM_NULL, 0, 0, 0, 0}
583};
584
585/* crc table has the same contents for every device instance, so it can be
586 * shared between devices. */
587static u8 brcms_srom_crc8_table[CRC8_TABLE_SIZE];
588
589static uint mask_shift(u16 mask)
590{
591 uint i;
592 for (i = 0; i < (sizeof(mask) << 3); i++) {
593 if (mask & (1 << i))
594 return i;
595 }
596 return 0;
597}
598
599static uint mask_width(u16 mask)
600{
601 int i;
602 for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
603 if (mask & (1 << i))
604 return (uint) (i - mask_shift(mask) + 1);
605 }
606 return 0;
607}
608
609static inline void le16_to_cpu_buf(u16 *buf, uint nwords)
610{
611 while (nwords--)
612 *(buf + nwords) = le16_to_cpu(*(__le16 *)(buf + nwords));
613}
614
615static inline void cpu_to_le16_buf(u16 *buf, uint nwords)
616{
617 while (nwords--)
618 *(__le16 *)(buf + nwords) = cpu_to_le16(*(buf + nwords));
619}
620
621/*
622 * convert binary srom data into linked list of srom variable items.
623 */
624static int
625_initvars_srom_pci(u8 sromrev, u16 *srom, struct list_head *var_list)
626{
627 struct brcms_srom_list_head *entry;
628 enum brcms_srom_id id;
629 u16 w;
630 u32 val = 0;
631 const struct brcms_sromvar *srv;
632 uint width;
633 uint flags;
634 u32 sr = (1 << sromrev);
635 uint p;
636 uint pb = SROM8_PATH0;
637 const uint psz = SROM8_PATH1 - SROM8_PATH0;
638
639 /* first store the srom revision */
640 entry = kzalloc(sizeof(struct brcms_srom_list_head), GFP_KERNEL);
641 if (!entry)
642 return -ENOMEM;
643
644 entry->varid = BRCMS_SROM_REV;
645 entry->var_type = BRCMS_SROM_UNUMBER;
646 entry->uval = sromrev;
647 list_add(&entry->var_list, var_list);
648
649 for (srv = pci_sromvars; srv->varid != BRCMS_SROM_NULL; srv++) {
650 enum brcms_srom_var_type type;
651 u8 ea[ETH_ALEN];
652 u8 extra_space = 0;
653
654 if ((srv->revmask & sr) == 0)
655 continue;
656
657 flags = srv->flags;
658 id = srv->varid;
659
660 /* This entry is for mfgc only. Don't generate param for it, */
661 if (flags & SRFL_NOVAR)
662 continue;
663
664 if (flags & SRFL_ETHADDR) {
665 /*
666 * stored in string format XX:XX:XX:XX:XX:XX (17 chars)
667 */
668 ea[0] = (srom[srv->off] >> 8) & 0xff;
669 ea[1] = srom[srv->off] & 0xff;
670 ea[2] = (srom[srv->off + 1] >> 8) & 0xff;
671 ea[3] = srom[srv->off + 1] & 0xff;
672 ea[4] = (srom[srv->off + 2] >> 8) & 0xff;
673 ea[5] = srom[srv->off + 2] & 0xff;
674 /* 17 characters + string terminator - union size */
675 extra_space = 18 - sizeof(s32);
676 type = BRCMS_SROM_STRING;
677 } else {
678 w = srom[srv->off];
679 val = (w & srv->mask) >> mask_shift(srv->mask);
680 width = mask_width(srv->mask);
681
682 while (srv->flags & SRFL_MORE) {
683 srv++;
684 if (srv->off == 0)
685 continue;
686
687 w = srom[srv->off];
688 val +=
689 ((w & srv->mask) >> mask_shift(srv->
690 mask)) <<
691 width;
692 width += mask_width(srv->mask);
693 }
694
695 if ((flags & SRFL_NOFFS)
696 && ((int)val == (1 << width) - 1))
697 continue;
698
699 if (flags & SRFL_CCODE) {
700 type = BRCMS_SROM_STRING;
701 } else if (flags & SRFL_LEDDC) {
702 /* LED Powersave duty cycle has to be scaled:
703 *(oncount >> 24) (offcount >> 8)
704 */
705 u32 w32 = /* oncount */
706 (((val >> 8) & 0xff) << 24) |
707 /* offcount */
708 (((val & 0xff)) << 8);
709 type = BRCMS_SROM_UNUMBER;
710 val = w32;
711 } else if ((flags & SRFL_PRSIGN)
712 && (val & (1 << (width - 1)))) {
713 type = BRCMS_SROM_SNUMBER;
714 val |= ~0 << width;
715 } else
716 type = BRCMS_SROM_UNUMBER;
717 }
718
719 entry = kzalloc(sizeof(struct brcms_srom_list_head) +
720 extra_space, GFP_KERNEL);
721 if (!entry)
722 return -ENOMEM;
723 entry->varid = id;
724 entry->var_type = type;
725 if (flags & SRFL_ETHADDR) {
726 snprintf(entry->buf, 18, "%pM", ea);
727 } else if (flags & SRFL_CCODE) {
728 if (val == 0)
729 entry->buf[0] = '\0';
730 else
731 snprintf(entry->buf, 3, "%c%c",
732 (val >> 8), (val & 0xff));
733 } else {
734 entry->uval = val;
735 }
736
737 list_add(&entry->var_list, var_list);
738 }
739
740 for (p = 0; p < MAX_PATH_SROM; p++) {
741 for (srv = perpath_pci_sromvars;
742 srv->varid != BRCMS_SROM_NULL; srv++) {
743 if ((srv->revmask & sr) == 0)
744 continue;
745
746 if (srv->flags & SRFL_NOVAR)
747 continue;
748
749 w = srom[pb + srv->off];
750 val = (w & srv->mask) >> mask_shift(srv->mask);
751 width = mask_width(srv->mask);
752
753 /* Cheating: no per-path var is more than
754 * 1 word */
755 if ((srv->flags & SRFL_NOFFS)
756 && ((int)val == (1 << width) - 1))
757 continue;
758
759 entry =
760 kzalloc(sizeof(struct brcms_srom_list_head),
761 GFP_KERNEL);
762 if (!entry)
763 return -ENOMEM;
764 entry->varid = srv->varid+p;
765 entry->var_type = BRCMS_SROM_UNUMBER;
766 entry->uval = val;
767 list_add(&entry->var_list, var_list);
768 }
769 pb += psz;
770 }
771 return 0;
772}
773
774/*
775 * The crc check is done on a little-endian array, we need
776 * to switch the bytes around before checking crc (and
777 * then switch it back).
778 */
779static int do_crc_check(u16 *buf, unsigned nwords)
780{
781 u8 crc;
782
783 cpu_to_le16_buf(buf, nwords);
784 crc = crc8(brcms_srom_crc8_table, (void *)buf, nwords << 1, CRC8_INIT_VALUE);
785 le16_to_cpu_buf(buf, nwords);
786
787 return crc == CRC8_GOOD_VALUE(brcms_srom_crc8_table);
788}
789
790/*
791 * Read in and validate sprom.
792 * Return 0 on success, nonzero on error.
793 */
794static int
795sprom_read_pci(struct si_pub *sih, u16 *buf, uint nwords, bool check_crc)
796{
797 int err = 0;
798 uint i;
799 struct bcma_device *core;
800 uint sprom_offset;
801
802 /* determine core to read */
803 if (ai_get_ccrev(sih) < 32) {
804 core = ai_findcore(sih, BCMA_CORE_80211, 0);
805 sprom_offset = PCI_BAR0_SPROM_OFFSET;
806 } else {
807 core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
808 sprom_offset = CHIPCREGOFFS(sromotp);
809 }
810
811 /* read the sprom */
812 for (i = 0; i < nwords; i++)
813 buf[i] = bcma_read16(core, sprom_offset+i*2);
814
815 if (buf[0] == 0xffff)
816 /*
817 * The hardware thinks that an srom that starts with
818 * 0xffff is blank, regardless of the rest of the
819 * content, so declare it bad.
820 */
821 return -ENODATA;
822
823 if (check_crc && !do_crc_check(buf, nwords))
824 err = -EIO;
825
826 return err;
827}
828
829static int otp_read_pci(struct si_pub *sih, u16 *buf, uint nwords)
830{
831 u8 *otp;
832 uint sz = OTP_SZ_MAX / 2; /* size in words */
833 int err = 0;
834
835 otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
836 if (otp == NULL)
837 return -ENOMEM;
838
839 err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
840
841 sz = min_t(uint, sz, nwords);
842 memcpy(buf, otp, sz * 2);
843
844 kfree(otp);
845
846 /* Check CRC */
847 if (buf[0] == 0xffff)
848 /* The hardware thinks that an srom that starts with 0xffff
849 * is blank, regardless of the rest of the content, so declare
850 * it bad.
851 */
852 return -ENODATA;
853
854 /* fixup the endianness so crc8 will pass */
855 cpu_to_le16_buf(buf, sz);
856 if (crc8(brcms_srom_crc8_table, (u8 *) buf, sz * 2,
857 CRC8_INIT_VALUE) != CRC8_GOOD_VALUE(brcms_srom_crc8_table))
858 err = -EIO;
859 else
860 /* now correct the endianness of the byte array */
861 le16_to_cpu_buf(buf, sz);
862
863 return err;
864}
865
866/*
867 * Initialize nonvolatile variable table from sprom.
868 * Return 0 on success, nonzero on error.
869 */
870int srom_var_init(struct si_pub *sih)
871{
872 u16 *srom;
873 u8 sromrev = 0;
874 u32 sr;
875 int err = 0;
876
877 /*
878 * Apply CRC over SROM content regardless SROM is present or not.
879 */
880 srom = kmalloc(SROM_MAX, GFP_ATOMIC);
881 if (!srom)
882 return -ENOMEM;
883
884 crc8_populate_lsb(brcms_srom_crc8_table, SROM_CRC8_POLY);
885 if (ai_is_sprom_available(sih)) {
886 err = sprom_read_pci(sih, srom, SROM4_WORDS, true);
887
888 if (err == 0)
889 /* srom read and passed crc */
890 /* top word of sprom contains version and crc8 */
891 sromrev = srom[SROM4_CRCREV] & 0xff;
892 } else {
893 /* Use OTP if SPROM not available */
894 err = otp_read_pci(sih, srom, SROM4_WORDS);
895 if (err == 0)
896 /* OTP only contain SROM rev8/rev9 for now */
897 sromrev = srom[SROM4_CRCREV] & 0xff;
898 }
899
900 if (!err) {
901 struct si_info *sii = (struct si_info *)sih;
902
903 /* Bitmask for the sromrev */
904 sr = 1 << sromrev;
905
906 /*
907 * srom version check: Current valid versions: 8, 9
908 */
909 if ((sr & 0x300) == 0) {
910 err = -EINVAL;
911 goto errout;
912 }
913
914 INIT_LIST_HEAD(&sii->var_list);
915
916 /* parse SROM into name=value pairs. */
917 err = _initvars_srom_pci(sromrev, srom, &sii->var_list);
918 if (err)
919 srom_free_vars(sih);
920 }
921
922errout:
923 kfree(srom);
924 return err;
925}
926
927void srom_free_vars(struct si_pub *sih)
928{
929 struct si_info *sii;
930 struct brcms_srom_list_head *entry, *next;
931
932 sii = (struct si_info *)sih;
933 list_for_each_entry_safe(entry, next, &sii->var_list, var_list) {
934 list_del(&entry->var_list);
935 kfree(entry);
936 }
937}
938
939/*
940 * Search the name=value vars for a specific one and return its value.
941 * Returns NULL if not found.
942 */
943char *getvar(struct si_pub *sih, enum brcms_srom_id id)
944{
945 struct si_info *sii;
946 struct brcms_srom_list_head *entry;
947
948 sii = (struct si_info *)sih;
949
950 list_for_each_entry(entry, &sii->var_list, var_list)
951 if (entry->varid == id)
952 return &entry->buf[0];
953
954 /* nothing found */
955 return NULL;
956}
957
958/*
959 * Search the vars for a specific one and return its value as
960 * an integer. Returns 0 if not found.-
961 */
962int getintvar(struct si_pub *sih, enum brcms_srom_id id)
963{
964 struct si_info *sii;
965 struct brcms_srom_list_head *entry;
966 unsigned long res;
967
968 sii = (struct si_info *)sih;
969
970 list_for_each_entry(entry, &sii->var_list, var_list)
971 if (entry->varid == id) {
972 if (entry->var_type == BRCMS_SROM_SNUMBER ||
973 entry->var_type == BRCMS_SROM_UNUMBER)
974 return (int)entry->sval;
975 else if (!kstrtoul(&entry->buf[0], 0, &res))
976 return (int)res;
977 }
978
979 return 0;
980}
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/srom.h b/drivers/net/wireless/brcm80211/brcmsmac/srom.h
deleted file mode 100644
index f2a58f262c99..000000000000
--- a/drivers/net/wireless/brcm80211/brcmsmac/srom.h
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef _BRCM_SROM_H_
18#define _BRCM_SROM_H_
19
20#include "types.h"
21
22/* Prototypes */
23extern int srom_var_init(struct si_pub *sih);
24extern void srom_free_vars(struct si_pub *sih);
25
26extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
27 uint byteoff, uint nbytes, u16 *buf, bool check_crc);
28
29#endif /* _BRCM_SROM_H_ */
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/stf.c b/drivers/net/wireless/brcm80211/brcmsmac/stf.c
index d8f528eb180c..ed1d1aa71d2d 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/stf.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/stf.c
@@ -370,9 +370,11 @@ void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc)
370 370
371void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc) 371void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc)
372{ 372{
373 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
374
373 /* get available rx/tx chains */ 375 /* get available rx/tx chains */
374 wlc->stf->hw_txchain = (u8) getintvar(wlc->hw->sih, BRCMS_SROM_TXCHAIN); 376 wlc->stf->hw_txchain = sprom->txchain;
375 wlc->stf->hw_rxchain = (u8) getintvar(wlc->hw->sih, BRCMS_SROM_RXCHAIN); 377 wlc->stf->hw_rxchain = sprom->rxchain;
376 378
377 /* these parameter are intended to be used for all PHY types */ 379 /* these parameter are intended to be used for all PHY types */
378 if (wlc->stf->hw_txchain == 0 || wlc->stf->hw_txchain == 0xf) { 380 if (wlc->stf->hw_txchain == 0 || wlc->stf->hw_txchain == 0xf) {
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 21:59:10 -0500