diff options
Diffstat (limited to 'drivers/net/wireless/brcm80211/brcmsmac/aiutils.h')
| -rw-r--r-- | drivers/net/wireless/brcm80211/brcmsmac/aiutils.h | 76 |
1 files changed, 0 insertions, 76 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h index 106a7424a7cd..b51d1e421e24 100644 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h | |||
| @@ -38,88 +38,12 @@ | |||
| 38 | /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */ | 38 | /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */ |
| 39 | #define SI_PCIE_DMA_H32 0x80000000 | 39 | #define SI_PCIE_DMA_H32 0x80000000 |
| 40 | 40 | ||
| 41 | /* core codes */ | ||
| 42 | #define NODEV_CORE_ID 0x700 /* Invalid coreid */ | ||
| 43 | #define CC_CORE_ID 0x800 /* chipcommon core */ | ||
| 44 | #define ILINE20_CORE_ID 0x801 /* iline20 core */ | ||
| 45 | #define SRAM_CORE_ID 0x802 /* sram core */ | ||
| 46 | #define SDRAM_CORE_ID 0x803 /* sdram core */ | ||
| 47 | #define PCI_CORE_ID 0x804 /* pci core */ | ||
| 48 | #define MIPS_CORE_ID 0x805 /* mips core */ | ||
| 49 | #define ENET_CORE_ID 0x806 /* enet mac core */ | ||
| 50 | #define CODEC_CORE_ID 0x807 /* v90 codec core */ | ||
| 51 | #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ | ||
| 52 | #define ADSL_CORE_ID 0x809 /* ADSL core */ | ||
| 53 | #define ILINE100_CORE_ID 0x80a /* iline100 core */ | ||
| 54 | #define IPSEC_CORE_ID 0x80b /* ipsec core */ | ||
| 55 | #define UTOPIA_CORE_ID 0x80c /* utopia core */ | ||
| 56 | #define PCMCIA_CORE_ID 0x80d /* pcmcia core */ | ||
| 57 | #define SOCRAM_CORE_ID 0x80e /* internal memory core */ | ||
| 58 | #define MEMC_CORE_ID 0x80f /* memc sdram core */ | ||
| 59 | #define OFDM_CORE_ID 0x810 /* OFDM phy core */ | ||
| 60 | #define EXTIF_CORE_ID 0x811 /* external interface core */ | ||
| 61 | #define D11_CORE_ID 0x812 /* 802.11 MAC core */ | ||
| 62 | #define APHY_CORE_ID 0x813 /* 802.11a phy core */ | ||
| 63 | #define BPHY_CORE_ID 0x814 /* 802.11b phy core */ | ||
| 64 | #define GPHY_CORE_ID 0x815 /* 802.11g phy core */ | ||
| 65 | #define MIPS33_CORE_ID 0x816 /* mips3302 core */ | ||
| 66 | #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ | ||
| 67 | #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ | ||
| 68 | #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ | ||
| 69 | #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ | ||
| 70 | #define SDIOH_CORE_ID 0x81b /* sdio host core */ | ||
| 71 | #define ROBO_CORE_ID 0x81c /* roboswitch core */ | ||
| 72 | #define ATA100_CORE_ID 0x81d /* parallel ATA core */ | ||
| 73 | #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ | ||
| 74 | #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ | ||
| 75 | #define PCIE_CORE_ID 0x820 /* pci express core */ | ||
| 76 | #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ | ||
| 77 | #define SRAMC_CORE_ID 0x822 /* SRAM controller core */ | ||
| 78 | #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ | ||
| 79 | #define ARM11_CORE_ID 0x824 /* ARM 1176 core */ | ||
| 80 | #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ | ||
| 81 | #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ | ||
| 82 | #define PMU_CORE_ID 0x827 /* PMU core */ | ||
| 83 | #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ | ||
| 84 | #define SDIOD_CORE_ID 0x829 /* SDIO device core */ | ||
| 85 | #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ | ||
| 86 | #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ | ||
| 87 | #define MIPS74K_CORE_ID 0x82c /* mips 74k core */ | ||
| 88 | #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ | ||
| 89 | #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ | ||
| 90 | #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ | ||
| 91 | #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ | ||
| 92 | #define SC_CORE_ID 0x831 /* shared common core */ | ||
| 93 | #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ | ||
| 94 | #define SPIH_CORE_ID 0x833 /* SPI host core */ | ||
| 95 | #define I2S_CORE_ID 0x834 /* I2S core */ | ||
| 96 | #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ | ||
| 97 | #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ | ||
| 98 | #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ | ||
| 99 | #define DEF_AI_COMP 0xfff /* Default component, in ai chips it | ||
| 100 | * maps all unused address ranges | ||
| 101 | */ | ||
| 102 | |||
| 103 | /* chipcommon being the first core: */ | 41 | /* chipcommon being the first core: */ |
| 104 | #define SI_CC_IDX 0 | 42 | #define SI_CC_IDX 0 |
| 105 | 43 | ||
| 106 | /* SOC Interconnect types (aka chip types) */ | 44 | /* SOC Interconnect types (aka chip types) */ |
| 107 | #define SOCI_AI 1 | 45 | #define SOCI_AI 1 |
| 108 | 46 | ||
| 109 | /* Common core control flags */ | ||
| 110 | #define SICF_BIST_EN 0x8000 | ||
| 111 | #define SICF_PME_EN 0x4000 | ||
| 112 | #define SICF_CORE_BITS 0x3ffc | ||
| 113 | #define SICF_FGC 0x0002 | ||
| 114 | #define SICF_CLOCK_EN 0x0001 | ||
| 115 | |||
| 116 | /* Common core status flags */ | ||
| 117 | #define SISF_BIST_DONE 0x8000 | ||
| 118 | #define SISF_BIST_ERROR 0x4000 | ||
| 119 | #define SISF_GATED_CLK 0x2000 | ||
| 120 | #define SISF_DMA64 0x1000 | ||
| 121 | #define SISF_CORE_BITS 0x0fff | ||
| 122 | |||
| 123 | /* A register that is common to all cores to | 47 | /* A register that is common to all cores to |
| 124 | * communicate w/PMU regarding clock control. | 48 | * communicate w/PMU regarding clock control. |
| 125 | */ | 49 | */ |