diff options
Diffstat (limited to 'drivers/net/wireless/bcm43xx/bcm43xx.h')
-rw-r--r-- | drivers/net/wireless/bcm43xx/bcm43xx.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx.h b/drivers/net/wireless/bcm43xx/bcm43xx.h index fbc0c087f53c..8286678513b9 100644 --- a/drivers/net/wireless/bcm43xx/bcm43xx.h +++ b/drivers/net/wireless/bcm43xx/bcm43xx.h | |||
@@ -159,6 +159,7 @@ | |||
159 | 159 | ||
160 | /* Chipcommon registers. */ | 160 | /* Chipcommon registers. */ |
161 | #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04 | 161 | #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04 |
162 | #define BCM43xx_CHIPCOMMON_CTL 0x28 | ||
162 | #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0 | 163 | #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0 |
163 | #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4 | 164 | #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4 |
164 | #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8 | 165 | #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8 |
@@ -172,6 +173,33 @@ | |||
172 | /* SBTOPCI2 values. */ | 173 | /* SBTOPCI2 values. */ |
173 | #define BCM43xx_SBTOPCI2_PREFETCH 0x4 | 174 | #define BCM43xx_SBTOPCI2_PREFETCH 0x4 |
174 | #define BCM43xx_SBTOPCI2_BURST 0x8 | 175 | #define BCM43xx_SBTOPCI2_BURST 0x8 |
176 | #define BCM43xx_SBTOPCI2_MEMREAD_MULTI 0x20 | ||
177 | |||
178 | /* PCI-E core registers. */ | ||
179 | #define BCM43xx_PCIECORE_REG_ADDR 0x0130 | ||
180 | #define BCM43xx_PCIECORE_REG_DATA 0x0134 | ||
181 | #define BCM43xx_PCIECORE_MDIO_CTL 0x0128 | ||
182 | #define BCM43xx_PCIECORE_MDIO_DATA 0x012C | ||
183 | |||
184 | /* PCI-E registers. */ | ||
185 | #define BCM43xx_PCIE_TLP_WORKAROUND 0x0004 | ||
186 | #define BCM43xx_PCIE_DLLP_LINKCTL 0x0100 | ||
187 | |||
188 | /* PCI-E MDIO bits. */ | ||
189 | #define BCM43xx_PCIE_MDIO_ST 0x40000000 | ||
190 | #define BCM43xx_PCIE_MDIO_WT 0x10000000 | ||
191 | #define BCM43xx_PCIE_MDIO_DEV 22 | ||
192 | #define BCM43xx_PCIE_MDIO_REG 18 | ||
193 | #define BCM43xx_PCIE_MDIO_TA 0x00020000 | ||
194 | #define BCM43xx_PCIE_MDIO_TC 0x0100 | ||
195 | |||
196 | /* MDIO devices. */ | ||
197 | #define BCM43xx_MDIO_SERDES_RX 0x1F | ||
198 | |||
199 | /* SERDES RX registers. */ | ||
200 | #define BCM43xx_SERDES_RXTIMER 0x2 | ||
201 | #define BCM43xx_SERDES_CDR 0x6 | ||
202 | #define BCM43xx_SERDES_CDR_BW 0x7 | ||
175 | 203 | ||
176 | /* Chipcommon capabilities. */ | 204 | /* Chipcommon capabilities. */ |
177 | #define BCM43xx_CAPABILITIES_PCTL 0x00040000 | 205 | #define BCM43xx_CAPABILITIES_PCTL 0x00040000 |
@@ -221,6 +249,7 @@ | |||
221 | #define BCM43xx_COREID_USB20_HOST 0x819 | 249 | #define BCM43xx_COREID_USB20_HOST 0x819 |
222 | #define BCM43xx_COREID_USB20_DEV 0x81a | 250 | #define BCM43xx_COREID_USB20_DEV 0x81a |
223 | #define BCM43xx_COREID_SDIO_HOST 0x81b | 251 | #define BCM43xx_COREID_SDIO_HOST 0x81b |
252 | #define BCM43xx_COREID_PCIE 0x820 | ||
224 | 253 | ||
225 | /* Core Information Registers */ | 254 | /* Core Information Registers */ |
226 | #define BCM43xx_CIR_BASE 0xf00 | 255 | #define BCM43xx_CIR_BASE 0xf00 |
@@ -365,6 +394,9 @@ | |||
365 | #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7 | 394 | #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7 |
366 | #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4 | 395 | #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4 |
367 | 396 | ||
397 | /* FIXME: the next line is a guess as to what the maximum RSSI value might be */ | ||
398 | #define RX_RSSI_MAX 60 | ||
399 | |||
368 | /* Max size of a security key */ | 400 | /* Max size of a security key */ |
369 | #define BCM43xx_SEC_KEYSIZE 16 | 401 | #define BCM43xx_SEC_KEYSIZE 16 |
370 | /* Security algorithms. */ | 402 | /* Security algorithms. */ |