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path: root/drivers/net/wireless/bcm43xx/bcm43xx.h
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Diffstat (limited to 'drivers/net/wireless/bcm43xx/bcm43xx.h')
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx.h997
1 files changed, 0 insertions, 997 deletions
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx.h b/drivers/net/wireless/bcm43xx/bcm43xx.h
deleted file mode 100644
index 2ebd2edf5862..000000000000
--- a/drivers/net/wireless/bcm43xx/bcm43xx.h
+++ /dev/null
@@ -1,997 +0,0 @@
1#ifndef BCM43xx_H_
2#define BCM43xx_H_
3
4#include <linux/hw_random.h>
5#include <linux/version.h>
6#include <linux/kernel.h>
7#include <linux/spinlock.h>
8#include <linux/interrupt.h>
9#include <linux/stringify.h>
10#include <linux/pci.h>
11#include <net/ieee80211.h>
12#include <net/ieee80211softmac.h>
13#include <asm/atomic.h>
14#include <asm/io.h>
15
16
17#include "bcm43xx_debugfs.h"
18#include "bcm43xx_leds.h"
19
20
21#define PFX KBUILD_MODNAME ": "
22
23#define BCM43xx_SWITCH_CORE_MAX_RETRIES 50
24#define BCM43xx_IRQWAIT_MAX_RETRIES 100
25
26#define BCM43xx_IO_SIZE 8192
27
28/* Active Core PCI Configuration Register. */
29#define BCM43xx_PCICFG_ACTIVE_CORE 0x80
30/* SPROM control register. */
31#define BCM43xx_PCICFG_SPROMCTL 0x88
32/* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
33#define BCM43xx_PCICFG_ICR 0x94
34
35/* MMIO offsets */
36#define BCM43xx_MMIO_DMA0_REASON 0x20
37#define BCM43xx_MMIO_DMA0_IRQ_MASK 0x24
38#define BCM43xx_MMIO_DMA1_REASON 0x28
39#define BCM43xx_MMIO_DMA1_IRQ_MASK 0x2C
40#define BCM43xx_MMIO_DMA2_REASON 0x30
41#define BCM43xx_MMIO_DMA2_IRQ_MASK 0x34
42#define BCM43xx_MMIO_DMA3_REASON 0x38
43#define BCM43xx_MMIO_DMA3_IRQ_MASK 0x3C
44#define BCM43xx_MMIO_DMA4_REASON 0x40
45#define BCM43xx_MMIO_DMA4_IRQ_MASK 0x44
46#define BCM43xx_MMIO_DMA5_REASON 0x48
47#define BCM43xx_MMIO_DMA5_IRQ_MASK 0x4C
48#define BCM43xx_MMIO_STATUS_BITFIELD 0x120
49#define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
50#define BCM43xx_MMIO_GEN_IRQ_REASON 0x128
51#define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C
52#define BCM43xx_MMIO_RAM_CONTROL 0x130
53#define BCM43xx_MMIO_RAM_DATA 0x134
54#define BCM43xx_MMIO_PS_STATUS 0x140
55#define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
56#define BCM43xx_MMIO_SHM_CONTROL 0x160
57#define BCM43xx_MMIO_SHM_DATA 0x164
58#define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
59#define BCM43xx_MMIO_XMITSTAT_0 0x170
60#define BCM43xx_MMIO_XMITSTAT_1 0x174
61#define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
62#define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
63
64/* 32-bit DMA */
65#define BCM43xx_MMIO_DMA32_BASE0 0x200
66#define BCM43xx_MMIO_DMA32_BASE1 0x220
67#define BCM43xx_MMIO_DMA32_BASE2 0x240
68#define BCM43xx_MMIO_DMA32_BASE3 0x260
69#define BCM43xx_MMIO_DMA32_BASE4 0x280
70#define BCM43xx_MMIO_DMA32_BASE5 0x2A0
71/* 64-bit DMA */
72#define BCM43xx_MMIO_DMA64_BASE0 0x200
73#define BCM43xx_MMIO_DMA64_BASE1 0x240
74#define BCM43xx_MMIO_DMA64_BASE2 0x280
75#define BCM43xx_MMIO_DMA64_BASE3 0x2C0
76#define BCM43xx_MMIO_DMA64_BASE4 0x300
77#define BCM43xx_MMIO_DMA64_BASE5 0x340
78/* PIO */
79#define BCM43xx_MMIO_PIO1_BASE 0x300
80#define BCM43xx_MMIO_PIO2_BASE 0x310
81#define BCM43xx_MMIO_PIO3_BASE 0x320
82#define BCM43xx_MMIO_PIO4_BASE 0x330
83
84#define BCM43xx_MMIO_PHY_VER 0x3E0
85#define BCM43xx_MMIO_PHY_RADIO 0x3E2
86#define BCM43xx_MMIO_ANTENNA 0x3E8
87#define BCM43xx_MMIO_CHANNEL 0x3F0
88#define BCM43xx_MMIO_CHANNEL_EXT 0x3F4
89#define BCM43xx_MMIO_RADIO_CONTROL 0x3F6
90#define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8
91#define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA
92#define BCM43xx_MMIO_PHY_CONTROL 0x3FC
93#define BCM43xx_MMIO_PHY_DATA 0x3FE
94#define BCM43xx_MMIO_MACFILTER_CONTROL 0x420
95#define BCM43xx_MMIO_MACFILTER_DATA 0x422
96#define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
97#define BCM43xx_MMIO_GPIO_CONTROL 0x49C
98#define BCM43xx_MMIO_GPIO_MASK 0x49E
99#define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */
100#define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */
101#define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */
102#define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */
103#define BCM43xx_MMIO_RNG 0x65A
104#define BCM43xx_MMIO_POWERUP_DELAY 0x6A8
105
106/* SPROM offsets. */
107#define BCM43xx_SPROM_BASE 0x1000
108#define BCM43xx_SPROM_BOARDFLAGS2 0x1c
109#define BCM43xx_SPROM_IL0MACADDR 0x24
110#define BCM43xx_SPROM_ET0MACADDR 0x27
111#define BCM43xx_SPROM_ET1MACADDR 0x2a
112#define BCM43xx_SPROM_ETHPHY 0x2d
113#define BCM43xx_SPROM_BOARDREV 0x2e
114#define BCM43xx_SPROM_PA0B0 0x2f
115#define BCM43xx_SPROM_PA0B1 0x30
116#define BCM43xx_SPROM_PA0B2 0x31
117#define BCM43xx_SPROM_WL0GPIO0 0x32
118#define BCM43xx_SPROM_WL0GPIO2 0x33
119#define BCM43xx_SPROM_MAXPWR 0x34
120#define BCM43xx_SPROM_PA1B0 0x35
121#define BCM43xx_SPROM_PA1B1 0x36
122#define BCM43xx_SPROM_PA1B2 0x37
123#define BCM43xx_SPROM_IDL_TSSI_TGT 0x38
124#define BCM43xx_SPROM_BOARDFLAGS 0x39
125#define BCM43xx_SPROM_ANTENNA_GAIN 0x3a
126#define BCM43xx_SPROM_VERSION 0x3f
127
128/* BCM43xx_SPROM_BOARDFLAGS values */
129#define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
130#define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
131#define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
132#define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
133#define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
134#define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
135#define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
136#define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */
137#define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */
138#define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
139#define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */
140#define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */
141#define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */
142#define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */
143#define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
144#define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
145
146/* GPIO register offset, in both ChipCommon and PCI core. */
147#define BCM43xx_GPIO_CONTROL 0x6c
148
149/* SHM Routing */
150#define BCM43xx_SHM_SHARED 0x0001
151#define BCM43xx_SHM_WIRELESS 0x0002
152#define BCM43xx_SHM_PCM 0x0003
153#define BCM43xx_SHM_HWMAC 0x0004
154#define BCM43xx_SHM_UCODE 0x0300
155
156/* MacFilter offsets. */
157#define BCM43xx_MACFILTER_SELF 0x0000
158#define BCM43xx_MACFILTER_ASSOC 0x0003
159
160/* Chipcommon registers. */
161#define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04
162#define BCM43xx_CHIPCOMMON_CTL 0x28
163#define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0
164#define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4
165#define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8
166#define BCM43xx_CHIPCOMMON_SYSCLKCTL 0xC0
167
168/* PCI core specific registers. */
169#define BCM43xx_PCICORE_BCAST_ADDR 0x50
170#define BCM43xx_PCICORE_BCAST_DATA 0x54
171#define BCM43xx_PCICORE_SBTOPCI2 0x108
172
173/* SBTOPCI2 values. */
174#define BCM43xx_SBTOPCI2_PREFETCH 0x4
175#define BCM43xx_SBTOPCI2_BURST 0x8
176#define BCM43xx_SBTOPCI2_MEMREAD_MULTI 0x20
177
178/* PCI-E core registers. */
179#define BCM43xx_PCIECORE_REG_ADDR 0x0130
180#define BCM43xx_PCIECORE_REG_DATA 0x0134
181#define BCM43xx_PCIECORE_MDIO_CTL 0x0128
182#define BCM43xx_PCIECORE_MDIO_DATA 0x012C
183
184/* PCI-E registers. */
185#define BCM43xx_PCIE_TLP_WORKAROUND 0x0004
186#define BCM43xx_PCIE_DLLP_LINKCTL 0x0100
187
188/* PCI-E MDIO bits. */
189#define BCM43xx_PCIE_MDIO_ST 0x40000000
190#define BCM43xx_PCIE_MDIO_WT 0x10000000
191#define BCM43xx_PCIE_MDIO_DEV 22
192#define BCM43xx_PCIE_MDIO_REG 18
193#define BCM43xx_PCIE_MDIO_TA 0x00020000
194#define BCM43xx_PCIE_MDIO_TC 0x0100
195
196/* MDIO devices. */
197#define BCM43xx_MDIO_SERDES_RX 0x1F
198
199/* SERDES RX registers. */
200#define BCM43xx_SERDES_RXTIMER 0x2
201#define BCM43xx_SERDES_CDR 0x6
202#define BCM43xx_SERDES_CDR_BW 0x7
203
204/* Chipcommon capabilities. */
205#define BCM43xx_CAPABILITIES_PCTL 0x00040000
206#define BCM43xx_CAPABILITIES_PLLMASK 0x00030000
207#define BCM43xx_CAPABILITIES_PLLSHIFT 16
208#define BCM43xx_CAPABILITIES_FLASHMASK 0x00000700
209#define BCM43xx_CAPABILITIES_FLASHSHIFT 8
210#define BCM43xx_CAPABILITIES_EXTBUSPRESENT 0x00000040
211#define BCM43xx_CAPABILITIES_UARTGPIO 0x00000020
212#define BCM43xx_CAPABILITIES_UARTCLOCKMASK 0x00000018
213#define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT 3
214#define BCM43xx_CAPABILITIES_MIPSBIGENDIAN 0x00000004
215#define BCM43xx_CAPABILITIES_NRUARTSMASK 0x00000003
216
217/* PowerControl */
218#define BCM43xx_PCTL_IN 0xB0
219#define BCM43xx_PCTL_OUT 0xB4
220#define BCM43xx_PCTL_OUTENABLE 0xB8
221#define BCM43xx_PCTL_XTAL_POWERUP 0x40
222#define BCM43xx_PCTL_PLL_POWERDOWN 0x80
223
224/* PowerControl Clock Modes */
225#define BCM43xx_PCTL_CLK_FAST 0x00
226#define BCM43xx_PCTL_CLK_SLOW 0x01
227#define BCM43xx_PCTL_CLK_DYNAMIC 0x02
228
229#define BCM43xx_PCTL_FORCE_SLOW 0x0800
230#define BCM43xx_PCTL_FORCE_PLL 0x1000
231#define BCM43xx_PCTL_DYN_XTAL 0x2000
232
233/* COREIDs */
234#define BCM43xx_COREID_CHIPCOMMON 0x800
235#define BCM43xx_COREID_ILINE20 0x801
236#define BCM43xx_COREID_SDRAM 0x803
237#define BCM43xx_COREID_PCI 0x804
238#define BCM43xx_COREID_MIPS 0x805
239#define BCM43xx_COREID_ETHERNET 0x806
240#define BCM43xx_COREID_V90 0x807
241#define BCM43xx_COREID_USB11_HOSTDEV 0x80a
242#define BCM43xx_COREID_IPSEC 0x80b
243#define BCM43xx_COREID_PCMCIA 0x80d
244#define BCM43xx_COREID_EXT_IF 0x80f
245#define BCM43xx_COREID_80211 0x812
246#define BCM43xx_COREID_MIPS_3302 0x816
247#define BCM43xx_COREID_USB11_HOST 0x817
248#define BCM43xx_COREID_USB11_DEV 0x818
249#define BCM43xx_COREID_USB20_HOST 0x819
250#define BCM43xx_COREID_USB20_DEV 0x81a
251#define BCM43xx_COREID_SDIO_HOST 0x81b
252#define BCM43xx_COREID_PCIE 0x820
253
254/* Core Information Registers */
255#define BCM43xx_CIR_BASE 0xf00
256#define BCM43xx_CIR_SBTPSFLAG (BCM43xx_CIR_BASE + 0x18)
257#define BCM43xx_CIR_SBIMSTATE (BCM43xx_CIR_BASE + 0x90)
258#define BCM43xx_CIR_SBINTVEC (BCM43xx_CIR_BASE + 0x94)
259#define BCM43xx_CIR_SBTMSTATELOW (BCM43xx_CIR_BASE + 0x98)
260#define BCM43xx_CIR_SBTMSTATEHIGH (BCM43xx_CIR_BASE + 0x9c)
261#define BCM43xx_CIR_SBIMCONFIGLOW (BCM43xx_CIR_BASE + 0xa8)
262#define BCM43xx_CIR_SB_ID_HI (BCM43xx_CIR_BASE + 0xfc)
263
264/* Mask to get the Backplane Flag Number from SBTPSFLAG. */
265#define BCM43xx_BACKPLANE_FLAG_NR_MASK 0x3f
266
267/* SBIMCONFIGLOW values/masks. */
268#define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK 0x00000007
269#define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT 0
270#define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK 0x00000070
271#define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT 4
272#define BCM43xx_SBIMCONFIGLOW_CONNID_MASK 0x00ff0000
273#define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT 16
274
275/* sbtmstatelow state flags */
276#define BCM43xx_SBTMSTATELOW_RESET 0x01
277#define BCM43xx_SBTMSTATELOW_REJECT 0x02
278#define BCM43xx_SBTMSTATELOW_CLOCK 0x10000
279#define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000
280#define BCM43xx_SBTMSTATELOW_G_MODE_ENABLE 0x20000000
281
282/* sbtmstatehigh state flags */
283#define BCM43xx_SBTMSTATEHIGH_SERROR 0x00000001
284#define BCM43xx_SBTMSTATEHIGH_BUSY 0x00000004
285#define BCM43xx_SBTMSTATEHIGH_TIMEOUT 0x00000020
286#define BCM43xx_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
287#define BCM43xx_SBTMSTATEHIGH_A_PHY_AVAIL 0x00020000
288#define BCM43xx_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
289#define BCM43xx_SBTMSTATEHIGH_DMA64BIT 0x10000000
290#define BCM43xx_SBTMSTATEHIGH_GATEDCLK 0x20000000
291#define BCM43xx_SBTMSTATEHIGH_BISTFAILED 0x40000000
292#define BCM43xx_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
293
294/* sbimstate flags */
295#define BCM43xx_SBIMSTATE_IB_ERROR 0x20000
296#define BCM43xx_SBIMSTATE_TIMEOUT 0x40000
297
298/* PHYVersioning */
299#define BCM43xx_PHYTYPE_A 0x00
300#define BCM43xx_PHYTYPE_B 0x01
301#define BCM43xx_PHYTYPE_G 0x02
302
303/* PHYRegisters */
304#define BCM43xx_PHY_ILT_A_CTRL 0x0072
305#define BCM43xx_PHY_ILT_A_DATA1 0x0073
306#define BCM43xx_PHY_ILT_A_DATA2 0x0074
307#define BCM43xx_PHY_G_LO_CONTROL 0x0810
308#define BCM43xx_PHY_ILT_G_CTRL 0x0472
309#define BCM43xx_PHY_ILT_G_DATA1 0x0473
310#define BCM43xx_PHY_ILT_G_DATA2 0x0474
311#define BCM43xx_PHY_A_PCTL 0x007B
312#define BCM43xx_PHY_G_PCTL 0x0029
313#define BCM43xx_PHY_A_CRS 0x0029
314#define BCM43xx_PHY_RADIO_BITFIELD 0x0401
315#define BCM43xx_PHY_G_CRS 0x0429
316#define BCM43xx_PHY_NRSSILT_CTRL 0x0803
317#define BCM43xx_PHY_NRSSILT_DATA 0x0804
318
319/* RadioRegisters */
320#define BCM43xx_RADIOCTL_ID 0x01
321
322/* StatusBitField */
323#define BCM43xx_SBF_MAC_ENABLED 0x00000001
324#define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/
325#define BCM43xx_SBF_CORE_READY 0x00000004
326#define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/
327#define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/
328#define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/
329#define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000
330#define BCM43xx_SBF_MODE_NOTADHOC 0x00020000
331#define BCM43xx_SBF_MODE_AP 0x00040000
332#define BCM43xx_SBF_RADIOREG_LOCK 0x00080000
333#define BCM43xx_SBF_MODE_MONITOR 0x00400000
334#define BCM43xx_SBF_MODE_PROMISC 0x01000000
335#define BCM43xx_SBF_PS1 0x02000000
336#define BCM43xx_SBF_PS2 0x04000000
337#define BCM43xx_SBF_NO_SSID_BCAST 0x08000000
338#define BCM43xx_SBF_TIME_UPDATE 0x10000000
339#define BCM43xx_SBF_MODE_G 0x80000000
340
341/* Microcode */
342#define BCM43xx_UCODE_REVISION 0x0000
343#define BCM43xx_UCODE_PATCHLEVEL 0x0002
344#define BCM43xx_UCODE_DATE 0x0004
345#define BCM43xx_UCODE_TIME 0x0006
346#define BCM43xx_UCODE_STATUS 0x0040
347
348/* MicrocodeFlagsBitfield (addr + lo-word values?)*/
349#define BCM43xx_UCODEFLAGS_OFFSET 0x005E
350
351#define BCM43xx_UCODEFLAG_AUTODIV 0x0001
352#define BCM43xx_UCODEFLAG_UNKBGPHY 0x0002
353#define BCM43xx_UCODEFLAG_UNKBPHY 0x0004
354#define BCM43xx_UCODEFLAG_UNKGPHY 0x0020
355#define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040
356#define BCM43xx_UCODEFLAG_JAPAN 0x0080
357
358/* Hardware Radio Enable masks */
359#define BCM43xx_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
360#define BCM43xx_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
361
362/* Generic-Interrupt reasons. */
363#define BCM43xx_IRQ_READY (1 << 0)
364#define BCM43xx_IRQ_BEACON (1 << 1)
365#define BCM43xx_IRQ_PS (1 << 2)
366#define BCM43xx_IRQ_REG124 (1 << 5)
367#define BCM43xx_IRQ_PMQ (1 << 6)
368#define BCM43xx_IRQ_PIO_WORKAROUND (1 << 8)
369#define BCM43xx_IRQ_XMIT_ERROR (1 << 11)
370#define BCM43xx_IRQ_RX (1 << 15)
371#define BCM43xx_IRQ_SCAN (1 << 16)
372#define BCM43xx_IRQ_NOISE (1 << 18)
373#define BCM43xx_IRQ_XMIT_STATUS (1 << 29)
374
375#define BCM43xx_IRQ_ALL 0xffffffff
376#define BCM43xx_IRQ_INITIAL (BCM43xx_IRQ_PS | \
377 BCM43xx_IRQ_REG124 | \
378 BCM43xx_IRQ_PMQ | \
379 BCM43xx_IRQ_XMIT_ERROR | \
380 BCM43xx_IRQ_RX | \
381 BCM43xx_IRQ_SCAN | \
382 BCM43xx_IRQ_NOISE | \
383 BCM43xx_IRQ_XMIT_STATUS)
384
385
386/* Initial default iw_mode */
387#define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA
388
389/* Bus type PCI. */
390#define BCM43xx_BUSTYPE_PCI 0
391/* Bus type Silicone Backplane Bus. */
392#define BCM43xx_BUSTYPE_SB 1
393/* Bus type PCMCIA. */
394#define BCM43xx_BUSTYPE_PCMCIA 2
395
396/* Threshold values. */
397#define BCM43xx_MIN_RTS_THRESHOLD 1U
398#define BCM43xx_MAX_RTS_THRESHOLD 2304U
399#define BCM43xx_DEFAULT_RTS_THRESHOLD BCM43xx_MAX_RTS_THRESHOLD
400
401#define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
402#define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
403
404/* FIXME: the next line is a guess as to what the maximum RSSI value might be */
405#define RX_RSSI_MAX 60
406
407/* Max size of a security key */
408#define BCM43xx_SEC_KEYSIZE 16
409/* Security algorithms. */
410enum {
411 BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
412 BCM43xx_SEC_ALGO_WEP,
413 BCM43xx_SEC_ALGO_UNKNOWN,
414 BCM43xx_SEC_ALGO_AES,
415 BCM43xx_SEC_ALGO_WEP104,
416 BCM43xx_SEC_ALGO_TKIP,
417};
418
419#ifdef assert
420# undef assert
421#endif
422#ifdef CONFIG_BCM43XX_DEBUG
423#define assert(expr) \
424 do { \
425 if (unlikely(!(expr))) { \
426 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \
427 #expr, __FILE__, __LINE__, __FUNCTION__); \
428 } \
429 } while (0)
430#else
431#define assert(expr) do { /* nothing */ } while (0)
432#endif
433
434/* rate limited printk(). */
435#ifdef printkl
436# undef printkl
437#endif
438#define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0)
439/* rate limited printk() for debugging */
440#ifdef dprintkl
441# undef dprintkl
442#endif
443#ifdef CONFIG_BCM43XX_DEBUG
444# define dprintkl printkl
445#else
446# define dprintkl(f, x...) do { /* nothing */ } while (0)
447#endif
448
449/* Helper macro for if branches.
450 * An if branch marked with this macro is only taken in DEBUG mode.
451 * Example:
452 * if (DEBUG_ONLY(foo == bar)) {
453 * do something
454 * }
455 * In DEBUG mode, the branch will be taken if (foo == bar).
456 * In non-DEBUG mode, the branch will never be taken.
457 */
458#ifdef DEBUG_ONLY
459# undef DEBUG_ONLY
460#endif
461#ifdef CONFIG_BCM43XX_DEBUG
462# define DEBUG_ONLY(x) (x)
463#else
464# define DEBUG_ONLY(x) 0
465#endif
466
467/* debugging printk() */
468#ifdef dprintk
469# undef dprintk
470#endif
471#ifdef CONFIG_BCM43XX_DEBUG
472# define dprintk(f, x...) do { printk(f ,##x); } while (0)
473#else
474# define dprintk(f, x...) do { /* nothing */ } while (0)
475#endif
476
477
478struct net_device;
479struct pci_dev;
480struct bcm43xx_dmaring;
481struct bcm43xx_pioqueue;
482
483struct bcm43xx_initval {
484 __be16 offset;
485 __be16 size;
486 __be32 value;
487} __attribute__((__packed__));
488
489/* Values for bcm430x_sprominfo.locale */
490enum {
491 BCM43xx_LOCALE_WORLD = 0,
492 BCM43xx_LOCALE_THAILAND,
493 BCM43xx_LOCALE_ISRAEL,
494 BCM43xx_LOCALE_JORDAN,
495 BCM43xx_LOCALE_CHINA,
496 BCM43xx_LOCALE_JAPAN,
497 BCM43xx_LOCALE_USA_CANADA_ANZ,
498 BCM43xx_LOCALE_EUROPE,
499 BCM43xx_LOCALE_USA_LOW,
500 BCM43xx_LOCALE_JAPAN_HIGH,
501 BCM43xx_LOCALE_ALL,
502 BCM43xx_LOCALE_NONE,
503};
504
505#define BCM43xx_SPROM_SIZE 64 /* in 16-bit words. */
506struct bcm43xx_sprominfo {
507 u16 boardflags2;
508 u8 il0macaddr[6];
509 u8 et0macaddr[6];
510 u8 et1macaddr[6];
511 u8 et0phyaddr:5;
512 u8 et1phyaddr:5;
513 u8 boardrev;
514 u8 locale:4;
515 u8 antennas_aphy:2;
516 u8 antennas_bgphy:2;
517 u16 pa0b0;
518 u16 pa0b1;
519 u16 pa0b2;
520 u8 wl0gpio0;
521 u8 wl0gpio1;
522 u8 wl0gpio2;
523 u8 wl0gpio3;
524 u8 maxpower_aphy;
525 u8 maxpower_bgphy;
526 u16 pa1b0;
527 u16 pa1b1;
528 u16 pa1b2;
529 u8 idle_tssi_tgt_aphy;
530 u8 idle_tssi_tgt_bgphy;
531 u16 boardflags;
532 u16 antennagain_aphy;
533 u16 antennagain_bgphy;
534};
535
536/* Value pair to measure the LocalOscillator. */
537struct bcm43xx_lopair {
538 s8 low;
539 s8 high;
540 u8 used:1;
541};
542#define BCM43xx_LO_COUNT (14*4)
543
544struct bcm43xx_phyinfo {
545 /* Hardware Data */
546 u8 analog;
547 u8 type;
548 u8 rev;
549 u16 antenna_diversity;
550 u16 savedpctlreg;
551 u16 minlowsig[2];
552 u16 minlowsigpos[2];
553 u8 connected:1,
554 calibrated:1,
555 is_locked:1, /* used in bcm43xx_phy_{un}lock() */
556 dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */
557 /* LO Measurement Data.
558 * Use bcm43xx_get_lopair() to get a value.
559 */
560 struct bcm43xx_lopair *_lo_pairs;
561
562 /* TSSI to dBm table in use */
563 const s8 *tssi2dbm;
564 /* idle TSSI value */
565 s8 idle_tssi;
566
567 /* Values from bcm43xx_calc_loopback_gain() */
568 u16 loopback_gain[2];
569
570 /* PHY lock for core.rev < 3
571 * This lock is only used by bcm43xx_phy_{un}lock()
572 */
573 spinlock_t lock;
574
575 /* Firmware. */
576 const struct firmware *ucode;
577 const struct firmware *pcm;
578 const struct firmware *initvals0;
579 const struct firmware *initvals1;
580};
581
582
583struct bcm43xx_radioinfo {
584 u16 manufact;
585 u16 version;
586 u8 revision;
587
588 /* Desired TX power in dBm Q5.2 */
589 u16 txpower_desired;
590 /* TX Power control values. */
591 union {
592 /* B/G PHY */
593 struct {
594 u16 baseband_atten;
595 u16 radio_atten;
596 u16 txctl1;
597 u16 txctl2;
598 };
599 /* A PHY */
600 struct {
601 u16 txpwr_offset;
602 };
603 };
604
605 /* Current Interference Mitigation mode */
606 int interfmode;
607 /* Stack of saved values from the Interference Mitigation code.
608 * Each value in the stack is layed out as follows:
609 * bit 0-11: offset
610 * bit 12-15: register ID
611 * bit 16-32: value
612 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
613 */
614#define BCM43xx_INTERFSTACK_SIZE 26
615 u32 interfstack[BCM43xx_INTERFSTACK_SIZE];
616
617 /* Saved values from the NRSSI Slope calculation */
618 s16 nrssi[2];
619 s32 nrssislope;
620 /* In memory nrssi lookup table. */
621 s8 nrssi_lt[64];
622
623 /* current channel */
624 u8 channel;
625 u8 initial_channel;
626
627 u16 lofcal;
628
629 u16 initval;
630
631 u8 enabled:1;
632 /* ACI (adjacent channel interference) flags. */
633 u8 aci_enable:1,
634 aci_wlan_automatic:1,
635 aci_hw_rssi:1;
636};
637
638/* Data structures for DMA transmission, per 80211 core. */
639struct bcm43xx_dma {
640 struct bcm43xx_dmaring *tx_ring0;
641 struct bcm43xx_dmaring *tx_ring1;
642 struct bcm43xx_dmaring *tx_ring2;
643 struct bcm43xx_dmaring *tx_ring3;
644 struct bcm43xx_dmaring *tx_ring4;
645 struct bcm43xx_dmaring *tx_ring5;
646
647 struct bcm43xx_dmaring *rx_ring0;
648 struct bcm43xx_dmaring *rx_ring3; /* only available on core.rev < 5 */
649};
650
651/* Data structures for PIO transmission, per 80211 core. */
652struct bcm43xx_pio {
653 struct bcm43xx_pioqueue *queue0;
654 struct bcm43xx_pioqueue *queue1;
655 struct bcm43xx_pioqueue *queue2;
656 struct bcm43xx_pioqueue *queue3;
657};
658
659#define BCM43xx_MAX_80211_CORES 2
660
661/* Generic information about a core. */
662struct bcm43xx_coreinfo {
663 u8 available:1,
664 enabled:1,
665 initialized:1;
666 /** core_rev revision number */
667 u8 rev;
668 /** Index number for _switch_core() */
669 u8 index;
670 /** core_id ID number */
671 u16 id;
672 /** Core-specific data. */
673 void *priv;
674};
675
676/* Additional information for each 80211 core. */
677struct bcm43xx_coreinfo_80211 {
678 /* PHY device. */
679 struct bcm43xx_phyinfo phy;
680 /* Radio device. */
681 struct bcm43xx_radioinfo radio;
682 union {
683 /* DMA context. */
684 struct bcm43xx_dma dma;
685 /* PIO context. */
686 struct bcm43xx_pio pio;
687 };
688};
689
690/* Context information for a noise calculation (Link Quality). */
691struct bcm43xx_noise_calculation {
692 struct bcm43xx_coreinfo *core_at_start;
693 u8 channel_at_start;
694 u8 calculation_running:1;
695 u8 nr_samples;
696 s8 samples[8][4];
697};
698
699struct bcm43xx_stats {
700 u8 noise;
701 struct iw_statistics wstats;
702 /* Store the last TX/RX times here for updating the leds. */
703 unsigned long last_tx;
704 unsigned long last_rx;
705};
706
707struct bcm43xx_key {
708 u8 enabled:1;
709 u8 algorithm;
710};
711
712/* Driver initialization status. */
713enum {
714 BCM43xx_STAT_UNINIT, /* Uninitialized. */
715 BCM43xx_STAT_INITIALIZING, /* init_board() in progress. */
716 BCM43xx_STAT_INITIALIZED, /* Fully operational. */
717 BCM43xx_STAT_SHUTTINGDOWN, /* free_board() in progress. */
718 BCM43xx_STAT_RESTARTING, /* controller_restart() called. */
719};
720#define bcm43xx_status(bcm) atomic_read(&(bcm)->init_status)
721#define bcm43xx_set_status(bcm, stat) do { \
722 atomic_set(&(bcm)->init_status, (stat)); \
723 smp_wmb(); \
724 } while (0)
725
726/* *** THEORY OF LOCKING ***
727 *
728 * We have two different locks in the bcm43xx driver.
729 * => bcm->mutex: General sleeping mutex. Protects struct bcm43xx_private
730 * and the device registers. This mutex does _not_ protect
731 * against concurrency from the IRQ handler.
732 * => bcm->irq_lock: IRQ spinlock. Protects against IRQ handler concurrency.
733 *
734 * Please note that, if you only take the irq_lock, you are not protected
735 * against concurrency from the periodic work handlers.
736 * Most times you want to take _both_ locks.
737 */
738
739struct bcm43xx_private {
740 struct ieee80211_device *ieee;
741 struct ieee80211softmac_device *softmac;
742
743 struct net_device *net_dev;
744 struct pci_dev *pci_dev;
745 unsigned int irq;
746
747 void __iomem *mmio_addr;
748
749 spinlock_t irq_lock;
750 struct mutex mutex;
751
752 /* Driver initialization status BCM43xx_STAT_*** */
753 atomic_t init_status;
754
755 u16 was_initialized:1, /* for PCI suspend/resume. */
756 __using_pio:1, /* Internal, use bcm43xx_using_pio(). */
757 bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */
758 reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */
759 short_preamble:1, /* TRUE, if short preamble is enabled. */
760 firmware_norelease:1, /* Do not release the firmware. Used on suspend. */
761 radio_hw_enable:1; /* TRUE if radio is hardware enabled */
762
763 struct bcm43xx_stats stats;
764
765 /* Bus type we are connected to.
766 * This is currently always BCM43xx_BUSTYPE_PCI
767 */
768 u8 bustype;
769 u64 dma_mask;
770
771 u16 board_vendor;
772 u16 board_type;
773 u16 board_revision;
774
775 u16 chip_id;
776 u8 chip_rev;
777 u8 chip_package;
778
779 struct bcm43xx_sprominfo sprom;
780#define BCM43xx_NR_LEDS 4
781 struct bcm43xx_led leds[BCM43xx_NR_LEDS];
782 spinlock_t leds_lock;
783
784 /* The currently active core. */
785 struct bcm43xx_coreinfo *current_core;
786 struct bcm43xx_coreinfo *active_80211_core;
787 /* coreinfo structs for all possible cores follow.
788 * Note that a core might not exist.
789 * So check the coreinfo flags before using it.
790 */
791 struct bcm43xx_coreinfo core_chipcommon;
792 struct bcm43xx_coreinfo core_pci;
793 struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ];
794 /* Additional information, specific to the 80211 cores. */
795 struct bcm43xx_coreinfo_80211 core_80211_ext[ BCM43xx_MAX_80211_CORES ];
796 /* Number of available 80211 cores. */
797 int nr_80211_available;
798
799 u32 chipcommon_capabilities;
800
801 /* Reason code of the last interrupt. */
802 u32 irq_reason;
803 u32 dma_reason[6];
804 /* saved irq enable/disable state bitfield. */
805 u32 irq_savedstate;
806 /* Link Quality calculation context. */
807 struct bcm43xx_noise_calculation noisecalc;
808 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
809 int mac_suspended;
810
811 /* Threshold values. */
812 //TODO: The RTS thr has to be _used_. Currently, it is only set via WX.
813 u32 rts_threshold;
814
815 /* Interrupt Service Routine tasklet (bottom-half) */
816 struct tasklet_struct isr_tasklet;
817
818 /* Periodic tasks */
819 struct delayed_work periodic_work;
820 unsigned int periodic_state;
821
822 struct work_struct restart_work;
823
824 /* Informational stuff. */
825 char nick[IW_ESSID_MAX_SIZE + 1];
826
827 /* encryption/decryption */
828 u16 security_offset;
829 struct bcm43xx_key key[54];
830 u8 default_key_idx;
831
832 /* Random Number Generator. */
833 struct hwrng rng;
834 char rng_name[20 + 1];
835
836 /* Debugging stuff follows. */
837#ifdef CONFIG_BCM43XX_DEBUG
838 struct bcm43xx_dfsentry *dfsentry;
839#endif
840};
841
842
843static inline
844struct bcm43xx_private * bcm43xx_priv(struct net_device *dev)
845{
846 return ieee80211softmac_priv(dev);
847}
848
849struct device;
850
851static inline
852struct bcm43xx_private * dev_to_bcm(struct device *dev)
853{
854 struct net_device *net_dev;
855 struct bcm43xx_private *bcm;
856
857 net_dev = dev_get_drvdata(dev);
858 bcm = bcm43xx_priv(net_dev);
859
860 return bcm;
861}
862
863
864/* Helper function, which returns a boolean.
865 * TRUE, if PIO is used; FALSE, if DMA is used.
866 */
867#if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
868static inline
869int bcm43xx_using_pio(struct bcm43xx_private *bcm)
870{
871 return bcm->__using_pio;
872}
873#elif defined(CONFIG_BCM43XX_DMA)
874static inline
875int bcm43xx_using_pio(struct bcm43xx_private *bcm)
876{
877 return 0;
878}
879#elif defined(CONFIG_BCM43XX_PIO)
880static inline
881int bcm43xx_using_pio(struct bcm43xx_private *bcm)
882{
883 return 1;
884}
885#else
886# error "Using neither DMA nor PIO? Confused..."
887#endif
888
889/* Helper functions to access data structures private to the 80211 cores.
890 * Note that we _must_ have an 80211 core mapped when calling
891 * any of these functions.
892 */
893static inline
894struct bcm43xx_coreinfo_80211 *
895bcm43xx_current_80211_priv(struct bcm43xx_private *bcm)
896{
897 assert(bcm->current_core->id == BCM43xx_COREID_80211);
898 return bcm->current_core->priv;
899}
900static inline
901struct bcm43xx_pio * bcm43xx_current_pio(struct bcm43xx_private *bcm)
902{
903 assert(bcm43xx_using_pio(bcm));
904 return &(bcm43xx_current_80211_priv(bcm)->pio);
905}
906static inline
907struct bcm43xx_dma * bcm43xx_current_dma(struct bcm43xx_private *bcm)
908{
909 assert(!bcm43xx_using_pio(bcm));
910 return &(bcm43xx_current_80211_priv(bcm)->dma);
911}
912static inline
913struct bcm43xx_phyinfo * bcm43xx_current_phy(struct bcm43xx_private *bcm)
914{
915 return &(bcm43xx_current_80211_priv(bcm)->phy);
916}
917static inline
918struct bcm43xx_radioinfo * bcm43xx_current_radio(struct bcm43xx_private *bcm)
919{
920 return &(bcm43xx_current_80211_priv(bcm)->radio);
921}
922
923
924static inline
925struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy,
926 u16 radio_attenuation,
927 u16 baseband_attenuation)
928{
929 return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2));
930}
931
932
933static inline
934u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset)
935{
936 return ioread16(bcm->mmio_addr + offset);
937}
938
939static inline
940void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value)
941{
942 iowrite16(value, bcm->mmio_addr + offset);
943}
944
945static inline
946u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset)
947{
948 return ioread32(bcm->mmio_addr + offset);
949}
950
951static inline
952void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value)
953{
954 iowrite32(value, bcm->mmio_addr + offset);
955}
956
957static inline
958int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value)
959{
960 return pci_read_config_word(bcm->pci_dev, offset, value);
961}
962
963static inline
964int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value)
965{
966 return pci_read_config_dword(bcm->pci_dev, offset, value);
967}
968
969static inline
970int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value)
971{
972 return pci_write_config_word(bcm->pci_dev, offset, value);
973}
974
975static inline
976int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value)
977{
978 return pci_write_config_dword(bcm->pci_dev, offset, value);
979}
980
981/** Limit a value between two limits */
982#ifdef limit_value
983# undef limit_value
984#endif
985#define limit_value(value, min, max) \
986 ({ \
987 typeof(value) __value = (value); \
988 typeof(value) __min = (min); \
989 typeof(value) __max = (max); \
990 if (__value < __min) \
991 __value = __min; \
992 else if (__value > __max) \
993 __value = __max; \
994 __value; \
995 })
996
997#endif /* BCM43xx_H_ */
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