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-rw-r--r--drivers/net/wireless/b43/Kconfig6
-rw-r--r--drivers/net/wireless/b43/b43.h10
-rw-r--r--drivers/net/wireless/b43/dma.c9
-rw-r--r--drivers/net/wireless/b43/main.c38
-rw-r--r--drivers/net/wireless/b43/phy_ht.c708
-rw-r--r--drivers/net/wireless/b43/phy_ht.h83
-rw-r--r--drivers/net/wireless/b43/phy_lcn.c5
-rw-r--r--drivers/net/wireless/b43/phy_lp.c16
-rw-r--r--drivers/net/wireless/b43/phy_n.c716
-rw-r--r--drivers/net/wireless/b43/phy_n.h146
-rw-r--r--drivers/net/wireless/b43/radio_2056.c6
-rw-r--r--drivers/net/wireless/b43/radio_2059.c39
-rw-r--r--drivers/net/wireless/b43/radio_2059.h14
-rw-r--r--drivers/net/wireless/b43/sdio.h4
-rw-r--r--drivers/net/wireless/b43/tables_nphy.c101
-rw-r--r--drivers/net/wireless/b43/tables_nphy.h29
-rw-r--r--drivers/net/wireless/b43/tables_phy_lcn.c6
17 files changed, 1327 insertions, 609 deletions
diff --git a/drivers/net/wireless/b43/Kconfig b/drivers/net/wireless/b43/Kconfig
index 287c6b670a36..078e6f3477a9 100644
--- a/drivers/net/wireless/b43/Kconfig
+++ b/drivers/net/wireless/b43/Kconfig
@@ -131,7 +131,7 @@ config B43_PHY_LP
131 131
132config B43_PHY_HT 132config B43_PHY_HT
133 bool "Support for HT-PHY (high throughput) devices" 133 bool "Support for HT-PHY (high throughput) devices"
134 depends on B43 134 depends on B43 && B43_BCMA
135 ---help--- 135 ---help---
136 Support for the HT-PHY. 136 Support for the HT-PHY.
137 137
@@ -166,8 +166,8 @@ config B43_DEBUG
166 Broadcom 43xx debugging. 166 Broadcom 43xx debugging.
167 167
168 This adds additional runtime sanity checks and statistics to the driver. 168 This adds additional runtime sanity checks and statistics to the driver.
169 These checks and statistics might me expensive and hurt runtime performance 169 These checks and statistics might be expensive and hurt the runtime
170 of your system. 170 performance of your system.
171 This also adds the b43 debugfs interface. 171 This also adds the b43 debugfs interface.
172 172
173 Do not enable this, unless you are debugging the driver. 173 Do not enable this, unless you are debugging the driver.
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 10e288d470e7..7f3d461f7e8d 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -285,7 +285,9 @@ enum {
285#define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */ 285#define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */
286#define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */ 286#define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
287/* SHM_SHARED beacon/AP variables */ 287/* SHM_SHARED beacon/AP variables */
288#define B43_SHM_SH_BT_BASE0 0x0068 /* Beacon template base 0 */
288#define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */ 289#define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
290#define B43_SHM_SH_BT_BASE1 0x0468 /* Beacon template base 1 */
289#define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */ 291#define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
290#define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */ 292#define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
291#define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */ 293#define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
@@ -473,6 +475,12 @@ enum {
473#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */ 475#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
474#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */ 476#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
475 477
478/* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */
479#define B43_BCMA_CLKCTLST_80211_PLL_REQ 0x00000100
480#define B43_BCMA_CLKCTLST_PHY_PLL_REQ 0x00000200
481#define B43_BCMA_CLKCTLST_80211_PLL_ST 0x01000000
482#define B43_BCMA_CLKCTLST_PHY_PLL_ST 0x02000000
483
476/* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */ 484/* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */
477#define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */ 485#define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */
478#define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */ 486#define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */
@@ -972,7 +980,7 @@ static inline int b43_is_mode(struct b43_wl *wl, int type)
972 */ 980 */
973static inline enum ieee80211_band b43_current_band(struct b43_wl *wl) 981static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
974{ 982{
975 return wl->hw->conf.channel->band; 983 return wl->hw->conf.chandef.chan->band;
976} 984}
977 985
978static inline int b43_bus_may_powerdown(struct b43_wldev *wldev) 986static inline int b43_bus_may_powerdown(struct b43_wldev *wldev)
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
index 122146943bf2..523355b87659 100644
--- a/drivers/net/wireless/b43/dma.c
+++ b/drivers/net/wireless/b43/dma.c
@@ -419,8 +419,6 @@ static inline
419 419
420static int alloc_ringmemory(struct b43_dmaring *ring) 420static int alloc_ringmemory(struct b43_dmaring *ring)
421{ 421{
422 gfp_t flags = GFP_KERNEL;
423
424 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K 422 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
425 * alignment and 8K buffers for 64-bit DMA with 8K alignment. 423 * alignment and 8K buffers for 64-bit DMA with 8K alignment.
426 * In practice we could use smaller buffers for the latter, but the 424 * In practice we could use smaller buffers for the latter, but the
@@ -435,12 +433,9 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
435 433
436 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev, 434 ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
437 ring_mem_size, &(ring->dmabase), 435 ring_mem_size, &(ring->dmabase),
438 flags); 436 GFP_KERNEL | __GFP_ZERO);
439 if (!ring->descbase) { 437 if (!ring->descbase)
440 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
441 return -ENOMEM; 438 return -ENOMEM;
442 }
443 memset(ring->descbase, 0, ring_mem_size);
444 439
445 return 0; 440 return 0;
446} 441}
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 05682736e466..d377f77d30b5 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -1189,10 +1189,15 @@ static void b43_bcma_phy_reset(struct b43_wldev *dev)
1189 1189
1190static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode) 1190static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
1191{ 1191{
1192 u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
1193 B43_BCMA_CLKCTLST_PHY_PLL_REQ;
1194 u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
1195 B43_BCMA_CLKCTLST_PHY_PLL_ST;
1196
1192 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN); 1197 b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
1193 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST); 1198 bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
1194 b43_bcma_phy_reset(dev); 1199 b43_bcma_phy_reset(dev);
1195 bcma_core_pll_ctl(dev->dev->bdev, 0x300, 0x3000000, true); 1200 bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
1196} 1201}
1197#endif 1202#endif
1198 1203
@@ -1305,17 +1310,19 @@ static u32 b43_jssi_read(struct b43_wldev *dev)
1305{ 1310{
1306 u32 val = 0; 1311 u32 val = 0;
1307 1312
1308 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); 1313 val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
1309 val <<= 16; 1314 val <<= 16;
1310 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); 1315 val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
1311 1316
1312 return val; 1317 return val;
1313} 1318}
1314 1319
1315static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) 1320static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1316{ 1321{
1317 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); 1322 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
1318 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); 1323 (jssi & 0x0000FFFF));
1324 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
1325 (jssi & 0xFFFF0000) >> 16);
1319} 1326}
1320 1327
1321static void b43_generate_noise_sample(struct b43_wldev *dev) 1328static void b43_generate_noise_sample(struct b43_wldev *dev)
@@ -1618,7 +1625,7 @@ static void b43_upload_beacon0(struct b43_wldev *dev)
1618 1625
1619 if (wl->beacon0_uploaded) 1626 if (wl->beacon0_uploaded)
1620 return; 1627 return;
1621 b43_write_beacon_template(dev, 0x68, 0x18); 1628 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
1622 wl->beacon0_uploaded = true; 1629 wl->beacon0_uploaded = true;
1623} 1630}
1624 1631
@@ -1628,7 +1635,7 @@ static void b43_upload_beacon1(struct b43_wldev *dev)
1628 1635
1629 if (wl->beacon1_uploaded) 1636 if (wl->beacon1_uploaded)
1630 return; 1637 return;
1631 b43_write_beacon_template(dev, 0x468, 0x1A); 1638 b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
1632 wl->beacon1_uploaded = true; 1639 wl->beacon1_uploaded = true;
1633} 1640}
1634 1641
@@ -2775,9 +2782,7 @@ static int b43_gpio_init(struct b43_wldev *dev)
2775 switch (dev->dev->bus_type) { 2782 switch (dev->dev->bus_type) {
2776#ifdef CONFIG_B43_BCMA 2783#ifdef CONFIG_B43_BCMA
2777 case B43_BUS_BCMA: 2784 case B43_BUS_BCMA:
2778 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL, 2785 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
2779 (bcma_cc_read32(&dev->dev->bdev->bus->drv_cc,
2780 BCMA_CC_GPIOCTL) & ~mask) | set);
2781 break; 2786 break;
2782#endif 2787#endif
2783#ifdef CONFIG_B43_SSB 2788#ifdef CONFIG_B43_SSB
@@ -2802,8 +2807,7 @@ static void b43_gpio_cleanup(struct b43_wldev *dev)
2802 switch (dev->dev->bus_type) { 2807 switch (dev->dev->bus_type) {
2803#ifdef CONFIG_B43_BCMA 2808#ifdef CONFIG_B43_BCMA
2804 case B43_BUS_BCMA: 2809 case B43_BUS_BCMA:
2805 bcma_cc_write32(&dev->dev->bdev->bus->drv_cc, BCMA_CC_GPIOCTL, 2810 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
2806 0);
2807 break; 2811 break;
2808#endif 2812#endif
2809#ifdef CONFIG_B43_SSB 2813#ifdef CONFIG_B43_SSB
@@ -3111,7 +3115,7 @@ static int b43_chip_init(struct b43_wldev *dev)
3111 3115
3112 /* Probe Response Timeout value */ 3116 /* Probe Response Timeout value */
3113 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ 3117 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
3114 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); 3118 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
3115 3119
3116 /* Initially set the wireless operation mode. */ 3120 /* Initially set the wireless operation mode. */
3117 b43_adjust_opmode(dev); 3121 b43_adjust_opmode(dev);
@@ -3848,7 +3852,7 @@ static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3848 dev = wl->current_dev; 3852 dev = wl->current_dev;
3849 3853
3850 /* Switch the band (if necessary). This might change the active core. */ 3854 /* Switch the band (if necessary). This might change the active core. */
3851 err = b43_switch_band(wl, conf->channel); 3855 err = b43_switch_band(wl, conf->chandef.chan);
3852 if (err) 3856 if (err)
3853 goto out_unlock_mutex; 3857 goto out_unlock_mutex;
3854 3858
@@ -3878,8 +3882,8 @@ static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3878 3882
3879 /* Switch to the requested channel. 3883 /* Switch to the requested channel.
3880 * The firmware takes care of races with the TX handler. */ 3884 * The firmware takes care of races with the TX handler. */
3881 if (conf->channel->hw_value != phy->channel) 3885 if (conf->chandef.chan->hw_value != phy->channel)
3882 b43_switch_channel(dev, conf->channel->hw_value); 3886 b43_switch_channel(dev, conf->chandef.chan->hw_value);
3883 3887
3884 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR); 3888 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
3885 3889
@@ -5002,7 +5006,7 @@ static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
5002 if (idx != 0) 5006 if (idx != 0)
5003 return -ENOENT; 5007 return -ENOENT;
5004 5008
5005 survey->channel = conf->channel; 5009 survey->channel = conf->chandef.chan;
5006 survey->filled = SURVEY_INFO_NOISE_DBM; 5010 survey->filled = SURVEY_INFO_NOISE_DBM;
5007 survey->noise = dev->stats.link_noise; 5011 survey->noise = dev->stats.link_noise;
5008 5012
diff --git a/drivers/net/wireless/b43/phy_ht.c b/drivers/net/wireless/b43/phy_ht.c
index 7416c5e9154d..5d6833f18498 100644
--- a/drivers/net/wireless/b43/phy_ht.c
+++ b/drivers/net/wireless/b43/phy_ht.c
@@ -30,6 +30,17 @@
30#include "radio_2059.h" 30#include "radio_2059.h"
31#include "main.h" 31#include "main.h"
32 32
33/* Force values to keep compatibility with wl */
34enum ht_rssi_type {
35 HT_RSSI_W1 = 0,
36 HT_RSSI_W2 = 1,
37 HT_RSSI_NB = 2,
38 HT_RSSI_IQ = 3,
39 HT_RSSI_TSSI_2G = 4,
40 HT_RSSI_TSSI_5G = 5,
41 HT_RSSI_TBD = 6,
42};
43
33/************************************************** 44/**************************************************
34 * Radio 2059. 45 * Radio 2059.
35 **************************************************/ 46 **************************************************/
@@ -37,8 +48,9 @@
37static void b43_radio_2059_channel_setup(struct b43_wldev *dev, 48static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
38 const struct b43_phy_ht_channeltab_e_radio2059 *e) 49 const struct b43_phy_ht_channeltab_e_radio2059 *e)
39{ 50{
40 u8 i; 51 static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
41 u16 routing; 52 u16 r;
53 int core;
42 54
43 b43_radio_write(dev, 0x16, e->radio_syn16); 55 b43_radio_write(dev, 0x16, e->radio_syn16);
44 b43_radio_write(dev, 0x17, e->radio_syn17); 56 b43_radio_write(dev, 0x17, e->radio_syn17);
@@ -53,25 +65,17 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
53 b43_radio_write(dev, 0x41, e->radio_syn41); 65 b43_radio_write(dev, 0x41, e->radio_syn41);
54 b43_radio_write(dev, 0x43, e->radio_syn43); 66 b43_radio_write(dev, 0x43, e->radio_syn43);
55 b43_radio_write(dev, 0x47, e->radio_syn47); 67 b43_radio_write(dev, 0x47, e->radio_syn47);
56 b43_radio_write(dev, 0x4a, e->radio_syn4a); 68
57 b43_radio_write(dev, 0x58, e->radio_syn58); 69 for (core = 0; core < 3; core++) {
58 b43_radio_write(dev, 0x5a, e->radio_syn5a); 70 r = routing[core];
59 b43_radio_write(dev, 0x6a, e->radio_syn6a); 71 b43_radio_write(dev, r | 0x4a, e->radio_rxtx4a);
60 b43_radio_write(dev, 0x6d, e->radio_syn6d); 72 b43_radio_write(dev, r | 0x58, e->radio_rxtx58);
61 b43_radio_write(dev, 0x6e, e->radio_syn6e); 73 b43_radio_write(dev, r | 0x5a, e->radio_rxtx5a);
62 b43_radio_write(dev, 0x92, e->radio_syn92); 74 b43_radio_write(dev, r | 0x6a, e->radio_rxtx6a);
63 b43_radio_write(dev, 0x98, e->radio_syn98); 75 b43_radio_write(dev, r | 0x6d, e->radio_rxtx6d);
64 76 b43_radio_write(dev, r | 0x6e, e->radio_rxtx6e);
65 for (i = 0; i < 2; i++) { 77 b43_radio_write(dev, r | 0x92, e->radio_rxtx92);
66 routing = i ? R2059_RXRX1 : R2059_TXRX0; 78 b43_radio_write(dev, r | 0x98, e->radio_rxtx98);
67 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
68 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
69 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
70 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
71 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
72 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
73 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
74 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
75 } 79 }
76 80
77 udelay(50); 81 udelay(50);
@@ -87,7 +91,7 @@ static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
87 91
88static void b43_radio_2059_init(struct b43_wldev *dev) 92static void b43_radio_2059_init(struct b43_wldev *dev)
89{ 93{
90 const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 }; 94 const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3 };
91 const u16 radio_values[3][2] = { 95 const u16 radio_values[3][2] = {
92 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 }, 96 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
93 }; 97 };
@@ -106,17 +110,17 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
106 b43_radio_mask(dev, 0xc0, ~0x0080); 110 b43_radio_mask(dev, 0xc0, ~0x0080);
107 111
108 if (1) { /* FIXME */ 112 if (1) { /* FIXME */
109 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1); 113 b43_radio_set(dev, R2059_C3 | 0x4, 0x1);
110 udelay(10); 114 udelay(10);
111 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1); 115 b43_radio_set(dev, R2059_C3 | 0x0BF, 0x1);
112 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2); 116 b43_radio_maskset(dev, R2059_C3 | 0x19B, 0x3, 0x2);
113 117
114 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2); 118 b43_radio_set(dev, R2059_C3 | 0x4, 0x2);
115 udelay(100); 119 udelay(100);
116 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2); 120 b43_radio_mask(dev, R2059_C3 | 0x4, ~0x2);
117 121
118 for (i = 0; i < 10000; i++) { 122 for (i = 0; i < 10000; i++) {
119 if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) { 123 if (b43_radio_read(dev, R2059_C3 | 0x145) & 1) {
120 i = 0; 124 i = 0;
121 break; 125 break;
122 } 126 }
@@ -125,7 +129,7 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
125 if (i) 129 if (i)
126 b43err(dev->wl, "radio 0x945 timeout\n"); 130 b43err(dev->wl, "radio 0x945 timeout\n");
127 131
128 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1); 132 b43_radio_mask(dev, R2059_C3 | 0x4, ~0x1);
129 b43_radio_set(dev, 0xa, 0x60); 133 b43_radio_set(dev, 0xa, 0x60);
130 134
131 for (i = 0; i < 3; i++) { 135 for (i = 0; i < 3; i++) {
@@ -154,9 +158,84 @@ static void b43_radio_2059_init(struct b43_wldev *dev)
154} 158}
155 159
156/************************************************** 160/**************************************************
161 * RF
162 **************************************************/
163
164static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
165{
166 u8 i;
167
168 u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
169 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
170
171 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
172 for (i = 0; i < 200; i++) {
173 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
174 i = 0;
175 break;
176 }
177 msleep(1);
178 }
179 if (i)
180 b43err(dev->wl, "Forcing RF sequence timeout\n");
181
182 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
183}
184
185static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
186{
187 struct b43_phy_ht *htphy = dev->phy.ht;
188 static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
189 B43_PHY_HT_RF_CTL_INT_C2,
190 B43_PHY_HT_RF_CTL_INT_C3 };
191 int i;
192
193 if (enable) {
194 for (i = 0; i < 3; i++)
195 b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
196 } else {
197 for (i = 0; i < 3; i++)
198 htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
199 /* TODO: Does 5GHz band use different value (not 0x0400)? */
200 for (i = 0; i < 3; i++)
201 b43_phy_write(dev, regs[i], 0x0400);
202 }
203}
204
205/**************************************************
157 * Various PHY ops 206 * Various PHY ops
158 **************************************************/ 207 **************************************************/
159 208
209static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
210{
211 u16 tmp;
212 u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
213 B43_PHY_HT_CLASS_CTL_OFDM_EN |
214 B43_PHY_HT_CLASS_CTL_WAITED_EN;
215
216 tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
217 tmp &= allowed;
218 tmp &= ~mask;
219 tmp |= (val & mask);
220 b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
221
222 return tmp;
223}
224
225static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
226{
227 u16 bbcfg;
228
229 b43_phy_force_clock(dev, true);
230 bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
231 b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
232 udelay(1);
233 b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
234 b43_phy_force_clock(dev, false);
235
236 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
237}
238
160static void b43_phy_ht_zero_extg(struct b43_wldev *dev) 239static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
161{ 240{
162 u8 i, j; 241 u8 i, j;
@@ -176,10 +255,10 @@ static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
176{ 255{
177 u8 i; 256 u8 i;
178 257
179 const u16 ctl_regs[3][2] = { 258 static const u16 ctl_regs[3][2] = {
180 { B43_PHY_HT_AFE_CTL1, B43_PHY_HT_AFE_CTL2 }, 259 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
181 { B43_PHY_HT_AFE_CTL3, B43_PHY_HT_AFE_CTL4 }, 260 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
182 { B43_PHY_HT_AFE_CTL5, B43_PHY_HT_AFE_CTL6}, 261 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
183 }; 262 };
184 263
185 for (i = 0; i < 3; i++) { 264 for (i = 0; i < 3; i++) {
@@ -193,27 +272,6 @@ static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
193 } 272 }
194} 273}
195 274
196static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
197{
198 u8 i;
199
200 u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
201 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
202
203 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
204 for (i = 0; i < 200; i++) {
205 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
206 i = 0;
207 break;
208 }
209 msleep(1);
210 }
211 if (i)
212 b43err(dev->wl, "Forcing RF sequence timeout\n");
213
214 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
215}
216
217static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) 275static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
218{ 276{
219 clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES); 277 clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
@@ -240,15 +298,456 @@ static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
240} 298}
241 299
242/************************************************** 300/**************************************************
301 * Samples
302 **************************************************/
303
304static void b43_phy_ht_stop_playback(struct b43_wldev *dev)
305{
306 struct b43_phy_ht *phy_ht = dev->phy.ht;
307 u16 tmp;
308 int i;
309
310 tmp = b43_phy_read(dev, B43_PHY_HT_SAMP_STAT);
311 if (tmp & 0x1)
312 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, B43_PHY_HT_SAMP_CMD_STOP);
313 else if (tmp & 0x2)
314 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, 0x7FFF);
315
316 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0x0004);
317
318 for (i = 0; i < 3; i++) {
319 if (phy_ht->bb_mult_save[i] >= 0) {
320 b43_httab_write(dev, B43_HTTAB16(13, 0x63 + i * 4),
321 phy_ht->bb_mult_save[i]);
322 b43_httab_write(dev, B43_HTTAB16(13, 0x67 + i * 4),
323 phy_ht->bb_mult_save[i]);
324 }
325 }
326}
327
328static u16 b43_phy_ht_load_samples(struct b43_wldev *dev)
329{
330 int i;
331 u16 len = 20 << 3;
332
333 b43_phy_write(dev, B43_PHY_HT_TABLE_ADDR, 0x4400);
334
335 for (i = 0; i < len; i++) {
336 b43_phy_write(dev, B43_PHY_HT_TABLE_DATAHI, 0);
337 b43_phy_write(dev, B43_PHY_HT_TABLE_DATALO, 0);
338 }
339
340 return len;
341}
342
343static void b43_phy_ht_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
344 u16 wait)
345{
346 struct b43_phy_ht *phy_ht = dev->phy.ht;
347 u16 save_seq_mode;
348 int i;
349
350 for (i = 0; i < 3; i++) {
351 if (phy_ht->bb_mult_save[i] < 0)
352 phy_ht->bb_mult_save[i] = b43_httab_read(dev, B43_HTTAB16(13, 0x63 + i * 4));
353 }
354
355 b43_phy_write(dev, B43_PHY_HT_SAMP_DEP_CNT, samps - 1);
356 if (loops != 0xFFFF)
357 loops--;
358 b43_phy_write(dev, B43_PHY_HT_SAMP_LOOP_CNT, loops);
359 b43_phy_write(dev, B43_PHY_HT_SAMP_WAIT_CNT, wait);
360
361 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
362 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE,
363 B43_PHY_HT_RF_SEQ_MODE_CA_OVER);
364
365 /* TODO: find out mask bits! Do we need more function arguments? */
366 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
367 b43_phy_mask(dev, B43_PHY_HT_SAMP_CMD, ~0);
368 b43_phy_mask(dev, B43_PHY_HT_IQLOCAL_CMDGCTL, ~0);
369 b43_phy_set(dev, B43_PHY_HT_SAMP_CMD, 0x1);
370
371 for (i = 0; i < 100; i++) {
372 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & 1)) {
373 i = 0;
374 break;
375 }
376 udelay(10);
377 }
378 if (i)
379 b43err(dev->wl, "run samples timeout\n");
380
381 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
382}
383
384static void b43_phy_ht_tx_tone(struct b43_wldev *dev)
385{
386 u16 samp;
387
388 samp = b43_phy_ht_load_samples(dev);
389 b43_phy_ht_run_samples(dev, samp, 0xFFFF, 0);
390}
391
392/**************************************************
393 * RSSI
394 **************************************************/
395
396static void b43_phy_ht_rssi_select(struct b43_wldev *dev, u8 core_sel,
397 enum ht_rssi_type rssi_type)
398{
399 static const u16 ctl_regs[3][2] = {
400 { B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER, },
401 { B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER, },
402 { B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER, },
403 };
404 static const u16 radio_r[] = { R2059_C1, R2059_C2, R2059_C3, };
405 int core;
406
407 if (core_sel == 0) {
408 b43err(dev->wl, "RSSI selection for core off not implemented yet\n");
409 } else {
410 for (core = 0; core < 3; core++) {
411 /* Check if caller requested a one specific core */
412 if ((core_sel == 1 && core != 0) ||
413 (core_sel == 2 && core != 1) ||
414 (core_sel == 3 && core != 2))
415 continue;
416
417 switch (rssi_type) {
418 case HT_RSSI_TSSI_2G:
419 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 8);
420 b43_phy_set(dev, ctl_regs[core][0], 0x3 << 10);
421 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 9);
422 b43_phy_set(dev, ctl_regs[core][1], 0x1 << 10);
423
424 b43_radio_set(dev, R2059_C3 | 0xbf, 0x1);
425 b43_radio_write(dev, radio_r[core] | 0x159,
426 0x11);
427 break;
428 default:
429 b43err(dev->wl, "RSSI selection for type %d not implemented yet\n",
430 rssi_type);
431 }
432 }
433 }
434}
435
436static void b43_phy_ht_poll_rssi(struct b43_wldev *dev, enum ht_rssi_type type,
437 s32 *buf, u8 nsamp)
438{
439 u16 phy_regs_values[12];
440 static const u16 phy_regs_to_save[] = {
441 B43_PHY_HT_AFE_C1, B43_PHY_HT_AFE_C1_OVER,
442 0x848, 0x841,
443 B43_PHY_HT_AFE_C2, B43_PHY_HT_AFE_C2_OVER,
444 0x868, 0x861,
445 B43_PHY_HT_AFE_C3, B43_PHY_HT_AFE_C3_OVER,
446 0x888, 0x881,
447 };
448 u16 tmp[3];
449 int i;
450
451 for (i = 0; i < 12; i++)
452 phy_regs_values[i] = b43_phy_read(dev, phy_regs_to_save[i]);
453
454 b43_phy_ht_rssi_select(dev, 5, type);
455
456 for (i = 0; i < 6; i++)
457 buf[i] = 0;
458
459 for (i = 0; i < nsamp; i++) {
460 tmp[0] = b43_phy_read(dev, B43_PHY_HT_RSSI_C1);
461 tmp[1] = b43_phy_read(dev, B43_PHY_HT_RSSI_C2);
462 tmp[2] = b43_phy_read(dev, B43_PHY_HT_RSSI_C3);
463
464 buf[0] += ((s8)((tmp[0] & 0x3F) << 2)) >> 2;
465 buf[1] += ((s8)(((tmp[0] >> 8) & 0x3F) << 2)) >> 2;
466 buf[2] += ((s8)((tmp[1] & 0x3F) << 2)) >> 2;
467 buf[3] += ((s8)(((tmp[1] >> 8) & 0x3F) << 2)) >> 2;
468 buf[4] += ((s8)((tmp[2] & 0x3F) << 2)) >> 2;
469 buf[5] += ((s8)(((tmp[2] >> 8) & 0x3F) << 2)) >> 2;
470 }
471
472 for (i = 0; i < 12; i++)
473 b43_phy_write(dev, phy_regs_to_save[i], phy_regs_values[i]);
474}
475
476/**************************************************
477 * Tx/Rx
478 **************************************************/
479
480static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
481{
482 int i;
483
484 for (i = 0; i < 3; i++) {
485 u16 mask;
486 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
487
488 if (0) /* FIXME */
489 mask = 0x2 << (i * 4);
490 else
491 mask = 0;
492 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
493
494 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
495 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
496 tmp & 0xFF);
497 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
498 tmp & 0xFF);
499 }
500}
501
502static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
503{
504 struct b43_phy_ht *phy_ht = dev->phy.ht;
505 u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF |
506 B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN |
507 B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN;
508 static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
509 B43_PHY_HT_TXPCTL_CMD_C2,
510 B43_PHY_HT_TXPCTL_CMD_C3 };
511 static const u16 status_regs[3] = { B43_PHY_HT_TX_PCTL_STATUS_C1,
512 B43_PHY_HT_TX_PCTL_STATUS_C2,
513 B43_PHY_HT_TX_PCTL_STATUS_C3 };
514 int i;
515
516 if (!enable) {
517 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
518 /* We disable enabled TX pwr ctl, save it's state */
519 for (i = 0; i < 3; i++)
520 phy_ht->tx_pwr_idx[i] =
521 b43_phy_read(dev, status_regs[i]);
522 }
523 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
524 } else {
525 b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);
526
527 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
528 for (i = 0; i < 3; i++)
529 b43_phy_write(dev, cmd_regs[i], 0x32);
530 }
531
532 for (i = 0; i < 3; i++)
533 if (phy_ht->tx_pwr_idx[i] <=
534 B43_PHY_HT_TXPCTL_CMD_C1_INIT)
535 b43_phy_write(dev, cmd_regs[i],
536 phy_ht->tx_pwr_idx[i]);
537 }
538
539 phy_ht->tx_pwr_ctl = enable;
540}
541
542static void b43_phy_ht_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
543{
544 struct b43_phy_ht *phy_ht = dev->phy.ht;
545 static const u16 base[] = { 0x840, 0x860, 0x880 };
546 u16 save_regs[3][3];
547 s32 rssi_buf[6];
548 int core;
549
550 for (core = 0; core < 3; core++) {
551 save_regs[core][1] = b43_phy_read(dev, base[core] + 6);
552 save_regs[core][2] = b43_phy_read(dev, base[core] + 7);
553 save_regs[core][0] = b43_phy_read(dev, base[core] + 0);
554
555 b43_phy_write(dev, base[core] + 6, 0);
556 b43_phy_mask(dev, base[core] + 7, ~0xF); /* 0xF? Or just 0x6? */
557 b43_phy_set(dev, base[core] + 0, 0x0400);
558 b43_phy_set(dev, base[core] + 0, 0x1000);
559 }
560
561 b43_phy_ht_tx_tone(dev);
562 udelay(20);
563 b43_phy_ht_poll_rssi(dev, HT_RSSI_TSSI_2G, rssi_buf, 1);
564 b43_phy_ht_stop_playback(dev);
565 b43_phy_ht_reset_cca(dev);
566
567 phy_ht->idle_tssi[0] = rssi_buf[0] & 0xff;
568 phy_ht->idle_tssi[1] = rssi_buf[2] & 0xff;
569 phy_ht->idle_tssi[2] = rssi_buf[4] & 0xff;
570
571 for (core = 0; core < 3; core++) {
572 b43_phy_write(dev, base[core] + 0, save_regs[core][0]);
573 b43_phy_write(dev, base[core] + 6, save_regs[core][1]);
574 b43_phy_write(dev, base[core] + 7, save_regs[core][2]);
575 }
576}
577
578static void b43_phy_ht_tssi_setup(struct b43_wldev *dev)
579{
580 static const u16 routing[] = { R2059_C1, R2059_C2, R2059_C3, };
581 int core;
582
583 /* 0x159 is probably TX_SSI_MUX or TSSIG (by comparing to N-PHY) */
584 for (core = 0; core < 3; core++) {
585 b43_radio_set(dev, 0x8bf, 0x1);
586 b43_radio_write(dev, routing[core] | 0x0159, 0x0011);
587 }
588}
589
590static void b43_phy_ht_tx_power_ctl_setup(struct b43_wldev *dev)
591{
592 struct b43_phy_ht *phy_ht = dev->phy.ht;
593 struct ssb_sprom *sprom = dev->dev->bus_sprom;
594
595 u8 *idle = phy_ht->idle_tssi;
596 u8 target[3];
597 s16 a1[3], b0[3], b1[3];
598
599 u16 freq = dev->phy.channel_freq;
600 int i, c;
601
602 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
603 for (c = 0; c < 3; c++) {
604 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
605 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
606 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
607 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
608 }
609 } else if (freq >= 4900 && freq < 5100) {
610 for (c = 0; c < 3; c++) {
611 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
612 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
613 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
614 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
615 }
616 } else if (freq >= 5100 && freq < 5500) {
617 for (c = 0; c < 3; c++) {
618 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
619 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
620 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
621 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
622 }
623 } else if (freq >= 5500) {
624 for (c = 0; c < 3; c++) {
625 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
626 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
627 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
628 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
629 }
630 } else {
631 target[0] = target[1] = target[2] = 52;
632 a1[0] = a1[1] = a1[2] = -424;
633 b0[0] = b0[1] = b0[2] = 5612;
634 b1[0] = b1[1] = b1[2] = -1393;
635 }
636
637 b43_phy_set(dev, B43_PHY_HT_TSSIMODE, B43_PHY_HT_TSSIMODE_EN);
638 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1,
639 ~B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN & 0xFFFF);
640
641 /* TODO: Does it depend on sprom->fem.ghz2.tssipos? */
642 b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI, 0x4000);
643
644 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1,
645 ~B43_PHY_HT_TXPCTL_CMD_C1_INIT, 0x19);
646 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2,
647 ~B43_PHY_HT_TXPCTL_CMD_C2_INIT, 0x19);
648 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3,
649 ~B43_PHY_HT_TXPCTL_CMD_C3_INIT, 0x19);
650
651 b43_phy_set(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
652 B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF);
653
654 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
655 ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C1,
656 idle[0] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT);
657 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,
658 ~B43_PHY_HT_TXPCTL_IDLE_TSSI_C2,
659 idle[1] << B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT);
660 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2,
661 ~B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3,
662 idle[2] << B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT);
663
664 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID,
665 0xf0);
666 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2,
667 0x3 << B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT);
668#if 0
669 /* TODO: what to mask/set? */
670 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0)
671 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0)
672#endif
673
674 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
675 ~B43_PHY_HT_TXPCTL_TARG_PWR_C1,
676 target[0] << B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT);
677 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,
678 ~B43_PHY_HT_TXPCTL_TARG_PWR_C2 & 0xFFFF,
679 target[1] << B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT);
680 b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2,
681 ~B43_PHY_HT_TXPCTL_TARG_PWR2_C3,
682 target[2] << B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT);
683
684 for (c = 0; c < 3; c++) {
685 s32 num, den, pwr;
686 u32 regval[64];
687
688 for (i = 0; i < 64; i++) {
689 num = 8 * (16 * b0[c] + b1[c] * i);
690 den = 32768 + a1[c] * i;
691 pwr = max((4 * num + den / 2) / den, -8);
692 regval[i] = pwr;
693 }
694 b43_httab_write_bulk(dev, B43_HTTAB16(26 + c, 0), 64, regval);
695 }
696}
697
698/**************************************************
243 * Channel switching ops. 699 * Channel switching ops.
244 **************************************************/ 700 **************************************************/
245 701
702static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
703 struct ieee80211_channel *new_channel)
704{
705 struct bcma_device *core = dev->dev->bdev;
706 int spuravoid = 0;
707 u16 tmp;
708
709 /* Check for 13 and 14 is just a guess, we don't have enough logs. */
710 if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
711 spuravoid = 1;
712 bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
713 bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
714 bcma_core_pll_ctl(core,
715 B43_BCMA_CLKCTLST_80211_PLL_REQ |
716 B43_BCMA_CLKCTLST_PHY_PLL_REQ,
717 B43_BCMA_CLKCTLST_80211_PLL_ST |
718 B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
719
720 /* Values has been taken from wlc_bmac_switch_macfreq comments */
721 switch (spuravoid) {
722 case 2: /* 126MHz */
723 tmp = 0x2082;
724 break;
725 case 1: /* 123MHz */
726 tmp = 0x5341;
727 break;
728 default: /* 120MHz */
729 tmp = 0x8889;
730 }
731
732 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
733 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
734
735 /* TODO: reset PLL */
736
737 if (spuravoid)
738 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
739 else
740 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
741 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
742
743 b43_phy_ht_reset_cca(dev);
744}
745
246static void b43_phy_ht_channel_setup(struct b43_wldev *dev, 746static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
247 const struct b43_phy_ht_channeltab_e_phy *e, 747 const struct b43_phy_ht_channeltab_e_phy *e,
248 struct ieee80211_channel *new_channel) 748 struct ieee80211_channel *new_channel)
249{ 749{
250 bool old_band_5ghz; 750 bool old_band_5ghz;
251 u8 i;
252 751
253 old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */ 752 old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
254 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) { 753 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
@@ -264,25 +763,20 @@ static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
264 b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5); 763 b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
265 b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6); 764 b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
266 765
267 /* TODO: some ops on PHY regs 0x0B0 and 0xC0A */ 766 if (new_channel->hw_value == 14) {
268 767 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
269 /* TODO: separated function? */ 768 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
270 for (i = 0; i < 3; i++) { 769 } else {
271 u16 mask; 770 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
272 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8)); 771 B43_PHY_HT_CLASS_CTL_OFDM_EN);
772 if (new_channel->band == IEEE80211_BAND_2GHZ)
773 b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
774 }
273 775
274 if (0) /* FIXME */ 776 if (1) /* TODO: On N it's for early devices only, what about HT? */
275 mask = 0x2 << (i * 4); 777 b43_phy_ht_tx_power_fix(dev);
276 else
277 mask = 0;
278 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
279 778
280 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16); 779 b43_phy_ht_spur_avoid(dev, new_channel);
281 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
282 tmp & 0xFF);
283 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
284 tmp & 0xFF);
285 }
286 780
287 b43_phy_write(dev, 0x017e, 0x3830); 781 b43_phy_write(dev, 0x017e, 0x3830);
288} 782}
@@ -337,14 +831,29 @@ static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
337{ 831{
338 struct b43_phy *phy = &dev->phy; 832 struct b43_phy *phy = &dev->phy;
339 struct b43_phy_ht *phy_ht = phy->ht; 833 struct b43_phy_ht *phy_ht = phy->ht;
834 int i;
340 835
341 memset(phy_ht, 0, sizeof(*phy_ht)); 836 memset(phy_ht, 0, sizeof(*phy_ht));
837
838 phy_ht->tx_pwr_ctl = true;
839 for (i = 0; i < 3; i++)
840 phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1;
841
842 for (i = 0; i < 3; i++)
843 phy_ht->bb_mult_save[i] = -1;
342} 844}
343 845
344static int b43_phy_ht_op_init(struct b43_wldev *dev) 846static int b43_phy_ht_op_init(struct b43_wldev *dev)
345{ 847{
848 struct b43_phy_ht *phy_ht = dev->phy.ht;
346 u16 tmp; 849 u16 tmp;
347 u16 clip_state[3]; 850 u16 clip_state[3];
851 bool saved_tx_pwr_ctl;
852
853 if (dev->dev->bus_type != B43_BUS_BCMA) {
854 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
855 return -EOPNOTSUPP;
856 }
348 857
349 b43_phy_ht_tables_init(dev); 858 b43_phy_ht_tables_init(dev);
350 859
@@ -357,9 +866,9 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
357 866
358 b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3); 867 b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
359 868
360 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0); 869 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
361 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0); 870 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
362 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0); 871 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
363 872
364 b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20); 873 b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
365 b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20); 874 b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
@@ -371,8 +880,11 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
371 if (0) /* TODO: condition */ 880 if (0) /* TODO: condition */
372 ; /* TODO: PHY op on reg 0x217 */ 881 ; /* TODO: PHY op on reg 0x217 */
373 882
374 b43_phy_read(dev, 0xb0); /* TODO: what for? */ 883 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
375 b43_phy_set(dev, 0xb0, 0x1); 884 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
885 else
886 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
887 B43_PHY_HT_CLASS_CTL_CCK_EN);
376 888
377 b43_phy_set(dev, 0xb1, 0x91); 889 b43_phy_set(dev, 0xb1, 0x91);
378 b43_phy_write(dev, 0x32f, 0x0003); 890 b43_phy_write(dev, 0x32f, 0x0003);
@@ -448,12 +960,13 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
448 960
449 b43_mac_phy_clock_set(dev, true); 961 b43_mac_phy_clock_set(dev, true);
450 962
963 b43_phy_ht_pa_override(dev, false);
451 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX); 964 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
452 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX); 965 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
453 966 b43_phy_ht_pa_override(dev, true);
454 /* TODO: PHY op on reg 0xb0 */
455 967
456 /* TODO: Should we restore it? Or store it in global PHY info? */ 968 /* TODO: Should we restore it? Or store it in global PHY info? */
969 b43_phy_ht_classifier(dev, 0, 0);
457 b43_phy_ht_read_clip_detection(dev, clip_state); 970 b43_phy_ht_read_clip_detection(dev, clip_state);
458 971
459 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 972 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
@@ -462,6 +975,14 @@ static int b43_phy_ht_op_init(struct b43_wldev *dev)
462 b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0), 975 b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
463 B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late); 976 B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
464 977
978 saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
979 b43_phy_ht_tx_power_fix(dev);
980 b43_phy_ht_tx_power_ctl(dev, false);
981 b43_phy_ht_tx_power_ctl_idle_tssi(dev);
982 b43_phy_ht_tx_power_ctl_setup(dev);
983 b43_phy_ht_tssi_setup(dev);
984 b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
985
465 return 0; 986 return 0;
466} 987}
467 988
@@ -506,27 +1027,28 @@ static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
506static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on) 1027static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
507{ 1028{
508 if (on) { 1029 if (on) {
509 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00cd); 1030 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
510 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x0000); 1031 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
511 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00cd); 1032 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
512 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x0000); 1033 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
513 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00cd); 1034 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
514 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x0000); 1035 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
515 } else { 1036 } else {
516 b43_phy_write(dev, B43_PHY_HT_AFE_CTL1, 0x07ff); 1037 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
517 b43_phy_write(dev, B43_PHY_HT_AFE_CTL2, 0x00fd); 1038 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
518 b43_phy_write(dev, B43_PHY_HT_AFE_CTL3, 0x07ff); 1039 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
519 b43_phy_write(dev, B43_PHY_HT_AFE_CTL4, 0x00fd); 1040 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
520 b43_phy_write(dev, B43_PHY_HT_AFE_CTL5, 0x07ff); 1041 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
521 b43_phy_write(dev, B43_PHY_HT_AFE_CTL6, 0x00fd); 1042 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
522 } 1043 }
523} 1044}
524 1045
525static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev, 1046static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
526 unsigned int new_channel) 1047 unsigned int new_channel)
527{ 1048{
528 struct ieee80211_channel *channel = dev->wl->hw->conf.channel; 1049 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
529 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type; 1050 enum nl80211_channel_type channel_type =
1051 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
530 1052
531 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 1053 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
532 if ((new_channel < 1) || (new_channel > 14)) 1054 if ((new_channel < 1) || (new_channel > 14))
diff --git a/drivers/net/wireless/b43/phy_ht.h b/drivers/net/wireless/b43/phy_ht.h
index 6544c4293b34..6cae370d1018 100644
--- a/drivers/net/wireless/b43/phy_ht.h
+++ b/drivers/net/wireless/b43/phy_ht.h
@@ -12,18 +12,65 @@
12#define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ 12#define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
13#define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ 13#define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
14#define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ 14#define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
15#define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
16#define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
17#define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */
18#define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */
19#define B43_PHY_HT_IQLOCAL_CMDGCTL 0x0C2 /* I/Q LO cal command G control */
20#define B43_PHY_HT_SAMP_CMD 0x0C3 /* Sample command */
21#define B43_PHY_HT_SAMP_CMD_STOP 0x0002 /* Stop */
22#define B43_PHY_HT_SAMP_LOOP_CNT 0x0C4 /* Sample loop count */
23#define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */
24#define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */
25#define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */
26#define B43_PHY_HT_EST_PWR_C1 0x118
27#define B43_PHY_HT_EST_PWR_C2 0x119
28#define B43_PHY_HT_EST_PWR_C3 0x11A
29#define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */
30#define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */
31#define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */
15#define B43_PHY_HT_BW1 0x1CE 32#define B43_PHY_HT_BW1 0x1CE
16#define B43_PHY_HT_BW2 0x1CF 33#define B43_PHY_HT_BW2 0x1CF
17#define B43_PHY_HT_BW3 0x1D0 34#define B43_PHY_HT_BW3 0x1D0
18#define B43_PHY_HT_BW4 0x1D1 35#define B43_PHY_HT_BW4 0x1D1
19#define B43_PHY_HT_BW5 0x1D2 36#define B43_PHY_HT_BW5 0x1D2
20#define B43_PHY_HT_BW6 0x1D3 37#define B43_PHY_HT_BW6 0x1D3
38#define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */
39#define B43_PHY_HT_TXPCTL_CMD_C1_INIT 0x007F /* Init */
40#define B43_PHY_HT_TXPCTL_CMD_C1_COEFF 0x2000 /* Power control coefficients */
41#define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */
42#define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */
43#define B43_PHY_HT_TXPCTL_N 0x1E8 /* TX power control N num */
44#define B43_PHY_HT_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */
45#define B43_PHY_HT_TXPCTL_N_TSSID_SHIFT 0
46#define B43_PHY_HT_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */
47#define B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT 8
48#define B43_PHY_HT_TXPCTL_IDLE_TSSI 0x1E9 /* TX power control idle TSSI */
49#define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1 0x003F
50#define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT 0
51#define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2 0x3F00
52#define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT 8
53#define B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF 0x8000 /* Raw TSSI offset bin format */
54#define B43_PHY_HT_TXPCTL_TARG_PWR 0x1EA /* TX power control target power */
55#define B43_PHY_HT_TXPCTL_TARG_PWR_C1 0x00FF /* Power 0 */
56#define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0
57#define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */
58#define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8
59#define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED
60#define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE
61#define B43_PHY_HT_TXPCTL_CMD_C2 0x222
62#define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F
63#define B43_PHY_HT_RSSI_C1 0x219
64#define B43_PHY_HT_RSSI_C2 0x21A
65#define B43_PHY_HT_RSSI_C3 0x21B
21 66
22#define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) 67#define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E)
23#define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) 68#define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E)
24#define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E) 69#define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E)
25 70
26#define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000) 71#define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000)
72#define B43_PHY_HT_RF_SEQ_MODE_CA_OVER 0x0001 /* Core active override */
73#define B43_PHY_HT_RF_SEQ_MODE_TR_OVER 0x0002 /* Trigger override */
27#define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003) 74#define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003)
28#define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ 75#define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */
29#define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ 76#define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */
@@ -36,12 +83,28 @@
36 83
37#define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010) 84#define B43_PHY_HT_RF_CTL1 B43_PHY_EXTG(0x010)
38 85
39#define B43_PHY_HT_AFE_CTL1 B43_PHY_EXTG(0x110) 86#define B43_PHY_HT_RF_CTL_INT_C1 B43_PHY_EXTG(0x04c)
40#define B43_PHY_HT_AFE_CTL2 B43_PHY_EXTG(0x111) 87#define B43_PHY_HT_RF_CTL_INT_C2 B43_PHY_EXTG(0x06c)
41#define B43_PHY_HT_AFE_CTL3 B43_PHY_EXTG(0x114) 88#define B43_PHY_HT_RF_CTL_INT_C3 B43_PHY_EXTG(0x08c)
42#define B43_PHY_HT_AFE_CTL4 B43_PHY_EXTG(0x115) 89
43#define B43_PHY_HT_AFE_CTL5 B43_PHY_EXTG(0x118) 90#define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110)
44#define B43_PHY_HT_AFE_CTL6 B43_PHY_EXTG(0x119) 91#define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111)
92#define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114)
93#define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115)
94#define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118)
95#define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119)
96
97#define B43_PHY_HT_TXPCTL_CMD_C3 B43_PHY_EXTG(0x164)
98#define B43_PHY_HT_TXPCTL_CMD_C3_INIT 0x007F
99#define B43_PHY_HT_TXPCTL_IDLE_TSSI2 B43_PHY_EXTG(0x165) /* TX power control idle TSSI */
100#define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3 0x003F
101#define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT 0
102#define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */
103#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF
104#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0
105#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169)
106
107#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)
45 108
46 109
47/* Values for PHY registers used on channel switching */ 110/* Values for PHY registers used on channel switching */
@@ -56,6 +119,14 @@ struct b43_phy_ht_channeltab_e_phy {
56 119
57 120
58struct b43_phy_ht { 121struct b43_phy_ht {
122 u16 rf_ctl_int_save[3];
123
124 bool tx_pwr_ctl;
125 u8 tx_pwr_idx[3];
126
127 s32 bb_mult_save[3];
128
129 u8 idle_tssi[3];
59}; 130};
60 131
61 132
diff --git a/drivers/net/wireless/b43/phy_lcn.c b/drivers/net/wireless/b43/phy_lcn.c
index a13e28ef6246..0bafa3b17035 100644
--- a/drivers/net/wireless/b43/phy_lcn.c
+++ b/drivers/net/wireless/b43/phy_lcn.c
@@ -808,8 +808,9 @@ static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
808static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev, 808static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,
809 unsigned int new_channel) 809 unsigned int new_channel)
810{ 810{
811 struct ieee80211_channel *channel = dev->wl->hw->conf.channel; 811 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
812 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type; 812 enum nl80211_channel_type channel_type =
813 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
813 814
814 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 815 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
815 if ((new_channel < 1) || (new_channel > 14)) 816 if ((new_channel < 1) || (new_channel > 14))
diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c
index 3ae28561f7a4..92190dacf689 100644
--- a/drivers/net/wireless/b43/phy_lp.c
+++ b/drivers/net/wireless/b43/phy_lp.c
@@ -104,14 +104,8 @@ static void lpphy_read_band_sprom(struct b43_wldev *dev)
104 maxpwr = sprom->maxpwr_bg; 104 maxpwr = sprom->maxpwr_bg;
105 lpphy->max_tx_pwr_med_band = maxpwr; 105 lpphy->max_tx_pwr_med_band = maxpwr;
106 cckpo = sprom->cck2gpo; 106 cckpo = sprom->cck2gpo;
107 /*
108 * We don't read SPROM's opo as specs say. On rev8 SPROMs
109 * opo == ofdm2gpo and we don't know any SSB with LP-PHY
110 * and SPROM rev below 8.
111 */
112 B43_WARN_ON(sprom->revision < 8);
113 ofdmpo = sprom->ofdm2gpo;
114 if (cckpo) { 107 if (cckpo) {
108 ofdmpo = sprom->ofdm2gpo;
115 for (i = 0; i < 4; i++) { 109 for (i = 0; i < 4; i++) {
116 lpphy->tx_max_rate[i] = 110 lpphy->tx_max_rate[i] =
117 maxpwr - (ofdmpo & 0xF) * 2; 111 maxpwr - (ofdmpo & 0xF) * 2;
@@ -124,11 +118,11 @@ static void lpphy_read_band_sprom(struct b43_wldev *dev)
124 ofdmpo >>= 4; 118 ofdmpo >>= 4;
125 } 119 }
126 } else { 120 } else {
127 ofdmpo &= 0xFF; 121 u8 opo = sprom->opo;
128 for (i = 0; i < 4; i++) 122 for (i = 0; i < 4; i++)
129 lpphy->tx_max_rate[i] = maxpwr; 123 lpphy->tx_max_rate[i] = maxpwr;
130 for (i = 4; i < 15; i++) 124 for (i = 4; i < 15; i++)
131 lpphy->tx_max_rate[i] = maxpwr - ofdmpo; 125 lpphy->tx_max_rate[i] = maxpwr - opo;
132 } 126 }
133 } else { /* 5GHz */ 127 } else { /* 5GHz */
134 lpphy->tx_isolation_low_band = sprom->tri5gl; 128 lpphy->tx_isolation_low_band = sprom->tri5gl;
@@ -287,8 +281,8 @@ static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A); 281 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00); 282 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
289 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ || 283 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
290 (dev->dev->board_type == 0x048A) || ((dev->phy.rev == 0) && 284 (dev->dev->board_type == SSB_BOARD_BU4312) ||
291 (sprom->boardflags_lo & B43_BFL_FEM))) { 285 (dev->phy.rev == 0 && (sprom->boardflags_lo & B43_BFL_FEM))) {
292 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001); 286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
293 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400); 287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001); 288 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index b70f220bc4b3..7c970d3ae358 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -69,14 +69,27 @@ enum b43_nphy_rf_sequence {
69 B43_RFSEQ_UPDATE_GAINU, 69 B43_RFSEQ_UPDATE_GAINU,
70}; 70};
71 71
72enum b43_nphy_rssi_type { 72enum n_intc_override {
73 B43_NPHY_RSSI_X = 0, 73 N_INTC_OVERRIDE_OFF = 0,
74 B43_NPHY_RSSI_Y, 74 N_INTC_OVERRIDE_TRSW = 1,
75 B43_NPHY_RSSI_Z, 75 N_INTC_OVERRIDE_PA = 2,
76 B43_NPHY_RSSI_PWRDET, 76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 B43_NPHY_RSSI_TSSI_I, 77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78 B43_NPHY_RSSI_TSSI_Q, 78};
79 B43_NPHY_RSSI_TBD, 79
80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
88};
89
90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
80}; 93};
81 94
82static inline bool b43_nphy_ipa(struct b43_wldev *dev) 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
@@ -94,7 +107,7 @@ static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
94} 107}
95 108
96/************************************************** 109/**************************************************
97 * RF (just without b43_nphy_rf_control_intc_override) 110 * RF (just without b43_nphy_rf_ctl_intc_override)
98 **************************************************/ 111 **************************************************/
99 112
100/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
@@ -128,9 +141,9 @@ ok:
128} 141}
129 142
130/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */ 143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
131static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field, 144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
132 u16 value, u8 core, bool off, 145 u16 value, u8 core, bool off,
133 u8 override) 146 u8 override)
134{ 147{
135 const struct nphy_rf_control_override_rev7 *e; 148 const struct nphy_rf_control_override_rev7 *e;
136 u16 en_addrs[3][2] = { 149 u16 en_addrs[3][2] = {
@@ -168,8 +181,8 @@ static void b43_nphy_rf_control_override_rev7(struct b43_wldev *dev, u16 field,
168} 181}
169 182
170/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ 183/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
171static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, 184static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
172 u16 value, u8 core, bool off) 185 u16 value, u8 core, bool off)
173{ 186{
174 int i; 187 int i;
175 u8 index = fls(field); 188 u8 index = fls(field);
@@ -244,14 +257,14 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
244} 257}
245 258
246/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ 259/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
247static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, 260static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
248 u16 value, u8 core) 261 enum n_intc_override intc_override,
262 u16 value, u8 core)
249{ 263{
250 u8 i, j; 264 u8 i, j;
251 u16 reg, tmp, val; 265 u16 reg, tmp, val;
252 266
253 B43_WARN_ON(dev->phy.rev < 3); 267 B43_WARN_ON(dev->phy.rev < 3);
254 B43_WARN_ON(field > 4);
255 268
256 for (i = 0; i < 2; i++) { 269 for (i = 0; i < 2; i++) {
257 if ((core == 1 && i == 1) || (core == 2 && !i)) 270 if ((core == 1 && i == 1) || (core == 2 && !i))
@@ -261,12 +274,12 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
261 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 274 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
262 b43_phy_set(dev, reg, 0x400); 275 b43_phy_set(dev, reg, 0x400);
263 276
264 switch (field) { 277 switch (intc_override) {
265 case 0: 278 case N_INTC_OVERRIDE_OFF:
266 b43_phy_write(dev, reg, 0); 279 b43_phy_write(dev, reg, 0);
267 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 280 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
268 break; 281 break;
269 case 1: 282 case N_INTC_OVERRIDE_TRSW:
270 if (!i) { 283 if (!i) {
271 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, 284 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
272 0xFC3F, (value << 6)); 285 0xFC3F, (value << 6));
@@ -307,7 +320,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
307 0xFFFE); 320 0xFFFE);
308 } 321 }
309 break; 322 break;
310 case 2: 323 case N_INTC_OVERRIDE_PA:
311 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 324 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
312 tmp = 0x0020; 325 tmp = 0x0020;
313 val = value << 5; 326 val = value << 5;
@@ -317,7 +330,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
317 } 330 }
318 b43_phy_maskset(dev, reg, ~tmp, val); 331 b43_phy_maskset(dev, reg, ~tmp, val);
319 break; 332 break;
320 case 3: 333 case N_INTC_OVERRIDE_EXT_LNA_PU:
321 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 334 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
322 tmp = 0x0001; 335 tmp = 0x0001;
323 val = value; 336 val = value;
@@ -327,7 +340,7 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
327 } 340 }
328 b43_phy_maskset(dev, reg, ~tmp, val); 341 b43_phy_maskset(dev, reg, ~tmp, val);
329 break; 342 break;
330 case 4: 343 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
331 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 344 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
332 tmp = 0x0002; 345 tmp = 0x0002;
333 val = value << 1; 346 val = value << 1;
@@ -1011,7 +1024,7 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
1011 1024
1012 if (sprom->revision < 4) 1025 if (sprom->revision < 4)
1013 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM 1026 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
1014 && dev->dev->board_type == 0x46D 1027 && dev->dev->board_type == SSB_BOARD_CB2_4321
1015 && dev->dev->board_rev >= 0x41); 1028 && dev->dev->board_rev >= 0x41);
1016 else 1029 else
1017 workaround = 1030 workaround =
@@ -1207,8 +1220,9 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1207 1220
1208/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ 1221/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1209static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, 1222static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1210 s8 offset, u8 core, u8 rail, 1223 s8 offset, u8 core,
1211 enum b43_nphy_rssi_type type) 1224 enum n_rail_type rail,
1225 enum n_rssi_type rssi_type)
1212{ 1226{
1213 u16 tmp; 1227 u16 tmp;
1214 bool core1or5 = (core == 1) || (core == 5); 1228 bool core1or5 = (core == 1) || (core == 5);
@@ -1217,63 +1231,74 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1217 offset = clamp_val(offset, -32, 31); 1231 offset = clamp_val(offset, -32, 31);
1218 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); 1232 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1219 1233
1220 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) 1234 switch (rssi_type) {
1221 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); 1235 case N_RSSI_NB:
1222 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) 1236 if (core1or5 && rail == N_RAIL_I)
1223 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); 1237 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1224 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z)) 1238 if (core1or5 && rail == N_RAIL_Q)
1225 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); 1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1226 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z)) 1240 if (core2or5 && rail == N_RAIL_I)
1227 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); 1241 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1228 1242 if (core2or5 && rail == N_RAIL_Q)
1229 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) 1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1230 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); 1244 break;
1231 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) 1245 case N_RSSI_W1:
1232 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); 1246 if (core1or5 && rail == N_RAIL_I)
1233 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X)) 1247 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1234 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); 1248 if (core1or5 && rail == N_RAIL_Q)
1235 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X)) 1249 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1236 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); 1250 if (core2or5 && rail == N_RAIL_I)
1237 1251 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1238 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) 1252 if (core2or5 && rail == N_RAIL_Q)
1239 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); 1253 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1240 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) 1254 break;
1241 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); 1255 case N_RSSI_W2:
1242 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y)) 1256 if (core1or5 && rail == N_RAIL_I)
1243 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); 1257 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1244 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y)) 1258 if (core1or5 && rail == N_RAIL_Q)
1245 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); 1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1246 1260 if (core2or5 && rail == N_RAIL_I)
1247 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) 1261 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1248 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); 1262 if (core2or5 && rail == N_RAIL_Q)
1249 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) 1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1250 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); 1264 break;
1251 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD)) 1265 case N_RSSI_TBD:
1252 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); 1266 if (core1or5 && rail == N_RAIL_I)
1253 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD)) 1267 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1254 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); 1268 if (core1or5 && rail == N_RAIL_Q)
1255 1269 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1256 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) 1270 if (core2or5 && rail == N_RAIL_I)
1257 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); 1271 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1258 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) 1272 if (core2or5 && rail == N_RAIL_Q)
1259 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); 1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1260 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET)) 1274 break;
1261 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); 1275 case N_RSSI_IQ:
1262 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET)) 1276 if (core1or5 && rail == N_RAIL_I)
1263 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); 1277 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1264 1278 if (core1or5 && rail == N_RAIL_Q)
1265 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I)) 1279 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1266 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); 1280 if (core2or5 && rail == N_RAIL_I)
1267 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I)) 1281 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1268 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); 1282 if (core2or5 && rail == N_RAIL_Q)
1269 1283 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1270 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q)) 1284 break;
1271 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); 1285 case N_RSSI_TSSI_2G:
1272 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q)) 1286 if (core1or5)
1273 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); 1287 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1288 if (core2or5)
1289 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1290 break;
1291 case N_RSSI_TSSI_5G:
1292 if (core1or5)
1293 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1294 if (core2or5)
1295 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1296 break;
1297 }
1274} 1298}
1275 1299
1276static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1300static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1301 enum n_rssi_type rssi_type)
1277{ 1302{
1278 u8 i; 1303 u8 i;
1279 u16 reg, val; 1304 u16 reg, val;
@@ -1296,7 +1321,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1296 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; 1321 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1297 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); 1322 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1298 1323
1299 if (type < 3) { 1324 if (rssi_type == N_RSSI_W1 ||
1325 rssi_type == N_RSSI_W2 ||
1326 rssi_type == N_RSSI_NB) {
1300 reg = (i == 0) ? 1327 reg = (i == 0) ?
1301 B43_NPHY_AFECTL_C1 : 1328 B43_NPHY_AFECTL_C1 :
1302 B43_NPHY_AFECTL_C2; 1329 B43_NPHY_AFECTL_C2;
@@ -1307,9 +1334,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1307 B43_NPHY_RFCTL_LUT_TRSW_UP2; 1334 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1308 b43_phy_maskset(dev, reg, 0xFFC3, 0); 1335 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1309 1336
1310 if (type == 0) 1337 if (rssi_type == N_RSSI_W1)
1311 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; 1338 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1312 else if (type == 1) 1339 else if (rssi_type == N_RSSI_W2)
1313 val = 16; 1340 val = 16;
1314 else 1341 else
1315 val = 32; 1342 val = 32;
@@ -1320,9 +1347,9 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1320 B43_NPHY_TXF_40CO_B32S1; 1347 B43_NPHY_TXF_40CO_B32S1;
1321 b43_phy_set(dev, reg, 0x0020); 1348 b43_phy_set(dev, reg, 0x0020);
1322 } else { 1349 } else {
1323 if (type == 6) 1350 if (rssi_type == N_RSSI_TBD)
1324 val = 0x0100; 1351 val = 0x0100;
1325 else if (type == 3) 1352 else if (rssi_type == N_RSSI_IQ)
1326 val = 0x0200; 1353 val = 0x0200;
1327 else 1354 else
1328 val = 0x0300; 1355 val = 0x0300;
@@ -1334,7 +1361,8 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1334 b43_phy_maskset(dev, reg, 0xFCFF, val); 1361 b43_phy_maskset(dev, reg, 0xFCFF, val);
1335 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); 1362 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1336 1363
1337 if (type != 3 && type != 6) { 1364 if (rssi_type != N_RSSI_IQ &&
1365 rssi_type != N_RSSI_TBD) {
1338 enum ieee80211_band band = 1366 enum ieee80211_band band =
1339 b43_current_band(dev->wl); 1367 b43_current_band(dev->wl);
1340 1368
@@ -1344,7 +1372,7 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1344 val = 0x11; 1372 val = 0x11;
1345 reg = (i == 0) ? 0x2000 : 0x3000; 1373 reg = (i == 0) ? 0x2000 : 0x3000;
1346 reg |= B2055_PADDRV; 1374 reg |= B2055_PADDRV;
1347 b43_radio_write16(dev, reg, val); 1375 b43_radio_write(dev, reg, val);
1348 1376
1349 reg = (i == 0) ? 1377 reg = (i == 0) ?
1350 B43_NPHY_AFECTL_OVER1 : 1378 B43_NPHY_AFECTL_OVER1 :
@@ -1356,33 +1384,43 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1356 } 1384 }
1357} 1385}
1358 1386
1359static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1387static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1388 enum n_rssi_type rssi_type)
1360{ 1389{
1361 u16 val; 1390 u16 val;
1391 bool rssi_w1_w2_nb = false;
1362 1392
1363 if (type < 3) 1393 switch (rssi_type) {
1394 case N_RSSI_W1:
1395 case N_RSSI_W2:
1396 case N_RSSI_NB:
1364 val = 0; 1397 val = 0;
1365 else if (type == 6) 1398 rssi_w1_w2_nb = true;
1399 break;
1400 case N_RSSI_TBD:
1366 val = 1; 1401 val = 1;
1367 else if (type == 3) 1402 break;
1403 case N_RSSI_IQ:
1368 val = 2; 1404 val = 2;
1369 else 1405 break;
1406 default:
1370 val = 3; 1407 val = 3;
1408 }
1371 1409
1372 val = (val << 12) | (val << 14); 1410 val = (val << 12) | (val << 14);
1373 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); 1411 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1374 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); 1412 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1375 1413
1376 if (type < 3) { 1414 if (rssi_w1_w2_nb) {
1377 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, 1415 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1378 (type + 1) << 4); 1416 (rssi_type + 1) << 4);
1379 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, 1417 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1380 (type + 1) << 4); 1418 (rssi_type + 1) << 4);
1381 } 1419 }
1382 1420
1383 if (code == 0) { 1421 if (code == 0) {
1384 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); 1422 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1385 if (type < 3) { 1423 if (rssi_w1_w2_nb) {
1386 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1424 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1387 ~(B43_NPHY_RFCTL_CMD_RXEN | 1425 ~(B43_NPHY_RFCTL_CMD_RXEN |
1388 B43_NPHY_RFCTL_CMD_CORESEL)); 1426 B43_NPHY_RFCTL_CMD_CORESEL));
@@ -1398,7 +1436,7 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1398 } 1436 }
1399 } else { 1437 } else {
1400 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); 1438 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1401 if (type < 3) { 1439 if (rssi_w1_w2_nb) {
1402 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 1440 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1403 ~(B43_NPHY_RFCTL_CMD_RXEN | 1441 ~(B43_NPHY_RFCTL_CMD_RXEN |
1404 B43_NPHY_RFCTL_CMD_CORESEL), 1442 B43_NPHY_RFCTL_CMD_CORESEL),
@@ -1418,7 +1456,8 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1418} 1456}
1419 1457
1420/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ 1458/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1421static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) 1459static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1460 enum n_rssi_type type)
1422{ 1461{
1423 if (dev->phy.rev >= 3) 1462 if (dev->phy.rev >= 3)
1424 b43_nphy_rev3_rssi_select(dev, code, type); 1463 b43_nphy_rev3_rssi_select(dev, code, type);
@@ -1427,11 +1466,12 @@ static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1427} 1466}
1428 1467
1429/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ 1468/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1430static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) 1469static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1470 enum n_rssi_type rssi_type, u8 *buf)
1431{ 1471{
1432 int i; 1472 int i;
1433 for (i = 0; i < 2; i++) { 1473 for (i = 0; i < 2; i++) {
1434 if (type == 2) { 1474 if (rssi_type == N_RSSI_NB) {
1435 if (i == 0) { 1475 if (i == 0) {
1436 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, 1476 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1437 0xFC, buf[0]); 1477 0xFC, buf[0]);
@@ -1455,8 +1495,8 @@ static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1455} 1495}
1456 1496
1457/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ 1497/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1458static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, 1498static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1459 u8 nsamp) 1499 s32 *buf, u8 nsamp)
1460{ 1500{
1461 int i; 1501 int i;
1462 int out; 1502 int out;
@@ -1487,7 +1527,7 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1487 save_regs_phy[8] = 0; 1527 save_regs_phy[8] = 0;
1488 } 1528 }
1489 1529
1490 b43_nphy_rssi_select(dev, 5, type); 1530 b43_nphy_rssi_select(dev, 5, rssi_type);
1491 1531
1492 if (dev->phy.rev < 2) { 1532 if (dev->phy.rev < 2) {
1493 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); 1533 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
@@ -1574,7 +1614,7 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1574 1614
1575 u16 r; /* routing */ 1615 u16 r; /* routing */
1576 u8 rx_core_state; 1616 u8 rx_core_state;
1577 u8 core, i, j; 1617 int core, i, j, vcm;
1578 1618
1579 class = b43_nphy_classifier(dev, 0, 0); 1619 class = b43_nphy_classifier(dev, 0, 0);
1580 b43_nphy_classifier(dev, 7, 4); 1620 b43_nphy_classifier(dev, 7, 4);
@@ -1586,19 +1626,19 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1586 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++) 1626 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1587 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); 1627 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1588 1628
1589 b43_nphy_rf_control_intc_override(dev, 0, 0, 7); 1629 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1590 b43_nphy_rf_control_intc_override(dev, 1, 1, 7); 1630 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
1591 b43_nphy_rf_control_override(dev, 0x1, 0, 0, false); 1631 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1592 b43_nphy_rf_control_override(dev, 0x2, 1, 0, false); 1632 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1593 b43_nphy_rf_control_override(dev, 0x80, 1, 0, false); 1633 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1594 b43_nphy_rf_control_override(dev, 0x40, 1, 0, false); 1634 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1595 1635
1596 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1636 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1597 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false); 1637 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1598 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false); 1638 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1599 } else { 1639 } else {
1600 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false); 1640 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1601 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false); 1641 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1602 } 1642 }
1603 1643
1604 rx_core_state = b43_nphy_get_rx_core_state(dev); 1644 rx_core_state = b43_nphy_get_rx_core_state(dev);
@@ -1606,35 +1646,44 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1606 if (!(rx_core_state & (1 << core))) 1646 if (!(rx_core_state & (1 << core)))
1607 continue; 1647 continue;
1608 r = core ? B2056_RX1 : B2056_RX0; 1648 r = core ? B2056_RX1 : B2056_RX0;
1609 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, 2); 1649 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1610 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, 2); 1650 N_RSSI_NB);
1611 for (i = 0; i < 8; i++) { 1651 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1652 N_RSSI_NB);
1653
1654 /* Grab RSSI results for every possible VCM */
1655 for (vcm = 0; vcm < 8; vcm++) {
1612 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3, 1656 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1613 i << 2); 1657 vcm << 2);
1614 b43_nphy_poll_rssi(dev, 2, results[i], 8); 1658 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
1615 } 1659 }
1660
1661 /* Find out which VCM got the best results */
1616 for (i = 0; i < 4; i += 2) { 1662 for (i = 0; i < 4; i += 2) {
1617 s32 curr; 1663 s32 currd;
1618 s32 mind = 0x100000; 1664 s32 mind = 0x100000;
1619 s32 minpoll = 249; 1665 s32 minpoll = 249;
1620 u8 minvcm = 0; 1666 u8 minvcm = 0;
1621 if (2 * core != i) 1667 if (2 * core != i)
1622 continue; 1668 continue;
1623 for (j = 0; j < 8; j++) { 1669 for (vcm = 0; vcm < 8; vcm++) {
1624 curr = results[j][i] * results[j][i] + 1670 currd = results[vcm][i] * results[vcm][i] +
1625 results[j][i + 1] * results[j][i]; 1671 results[vcm][i + 1] * results[vcm][i];
1626 if (curr < mind) { 1672 if (currd < mind) {
1627 mind = curr; 1673 mind = currd;
1628 minvcm = j; 1674 minvcm = vcm;
1629 } 1675 }
1630 if (results[j][i] < minpoll) 1676 if (results[vcm][i] < minpoll)
1631 minpoll = results[j][i]; 1677 minpoll = results[vcm][i];
1632 } 1678 }
1633 vcm_final = minvcm; 1679 vcm_final = minvcm;
1634 results_min[i] = minpoll; 1680 results_min[i] = minpoll;
1635 } 1681 }
1682
1683 /* Select the best VCM */
1636 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3, 1684 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1637 vcm_final << 2); 1685 vcm_final << 2);
1686
1638 for (i = 0; i < 4; i++) { 1687 for (i = 0; i < 4; i++) {
1639 if (core != i / 2) 1688 if (core != i / 2)
1640 continue; 1689 continue;
@@ -1647,16 +1696,19 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1647 offset[i] = -32; 1696 offset[i] = -32;
1648 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1697 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1649 (i / 2 == 0) ? 1 : 2, 1698 (i / 2 == 0) ? 1 : 2,
1650 (i % 2 == 0) ? 0 : 1, 1699 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
1651 2); 1700 N_RSSI_NB);
1652 } 1701 }
1653 } 1702 }
1703
1654 for (core = 0; core < 2; core++) { 1704 for (core = 0; core < 2; core++) {
1655 if (!(rx_core_state & (1 << core))) 1705 if (!(rx_core_state & (1 << core)))
1656 continue; 1706 continue;
1657 for (i = 0; i < 2; i++) { 1707 for (i = 0; i < 2; i++) {
1658 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, i); 1708 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1659 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, i); 1709 N_RAIL_I, i);
1710 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1711 N_RAIL_Q, i);
1660 b43_nphy_poll_rssi(dev, i, poll_results, 8); 1712 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1661 for (j = 0; j < 4; j++) { 1713 for (j = 0; j < 4; j++) {
1662 if (j / 2 == core) { 1714 if (j / 2 == core) {
@@ -1696,8 +1748,13 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1696 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 1748 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1697 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 1749 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1698 } 1750 }
1699 rssical_radio_regs[0] = b43_radio_read(dev, 0x602B); 1751 if (dev->phy.rev >= 7) {
1700 rssical_radio_regs[0] = b43_radio_read(dev, 0x702B); 1752 } else {
1753 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1754 B2056_RX_RSSI_MISC);
1755 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1756 B2056_RX_RSSI_MISC);
1757 }
1701 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); 1758 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1702 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); 1759 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1703 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); 1760 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
@@ -1723,9 +1780,9 @@ static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1723} 1780}
1724 1781
1725/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ 1782/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1726static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) 1783static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
1727{ 1784{
1728 int i, j; 1785 int i, j, vcm;
1729 u8 state[4]; 1786 u8 state[4];
1730 u8 code, val; 1787 u8 code, val;
1731 u16 class, override; 1788 u16 class, override;
@@ -1743,10 +1800,10 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1743 s32 results[4][4] = { }; 1800 s32 results[4][4] = { };
1744 s32 miniq[4][2] = { }; 1801 s32 miniq[4][2] = { };
1745 1802
1746 if (type == 2) { 1803 if (type == N_RSSI_NB) {
1747 code = 0; 1804 code = 0;
1748 val = 6; 1805 val = 6;
1749 } else if (type < 2) { 1806 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
1750 code = 25; 1807 code = 25;
1751 val = 4; 1808 val = 4;
1752 } else { 1809 } else {
@@ -1765,63 +1822,63 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1765 override = 0x110; 1822 override = 0x110;
1766 1823
1767 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 1824 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1768 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); 1825 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
1769 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); 1826 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1770 b43_radio_write16(dev, B2055_C1_PD_RXTX, val); 1827 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
1771 1828
1772 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 1829 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1773 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); 1830 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
1774 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); 1831 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1775 b43_radio_write16(dev, B2055_C2_PD_RXTX, val); 1832 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
1776 1833
1777 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; 1834 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1778 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; 1835 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1779 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); 1836 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1780 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); 1837 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1781 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; 1838 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1782 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; 1839 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
1783 1840
1784 b43_nphy_rssi_select(dev, 5, type); 1841 b43_nphy_rssi_select(dev, 5, type);
1785 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); 1842 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1786 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); 1843 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
1787 1844
1788 for (i = 0; i < 4; i++) { 1845 for (vcm = 0; vcm < 4; vcm++) {
1789 u8 tmp[4]; 1846 u8 tmp[4];
1790 for (j = 0; j < 4; j++) 1847 for (j = 0; j < 4; j++)
1791 tmp[j] = i; 1848 tmp[j] = vcm;
1792 if (type != 1) 1849 if (type != N_RSSI_W2)
1793 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); 1850 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1794 b43_nphy_poll_rssi(dev, type, results[i], 8); 1851 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
1795 if (type < 2) 1852 if (type == N_RSSI_W1 || type == N_RSSI_W2)
1796 for (j = 0; j < 2; j++) 1853 for (j = 0; j < 2; j++)
1797 miniq[i][j] = min(results[i][2 * j], 1854 miniq[vcm][j] = min(results[vcm][2 * j],
1798 results[i][2 * j + 1]); 1855 results[vcm][2 * j + 1]);
1799 } 1856 }
1800 1857
1801 for (i = 0; i < 4; i++) { 1858 for (i = 0; i < 4; i++) {
1802 s32 mind = 0x100000; 1859 s32 mind = 0x100000;
1803 u8 minvcm = 0; 1860 u8 minvcm = 0;
1804 s32 minpoll = 249; 1861 s32 minpoll = 249;
1805 s32 curr; 1862 s32 currd;
1806 for (j = 0; j < 4; j++) { 1863 for (vcm = 0; vcm < 4; vcm++) {
1807 if (type == 2) 1864 if (type == N_RSSI_NB)
1808 curr = abs(results[j][i]); 1865 currd = abs(results[vcm][i] - code * 8);
1809 else 1866 else
1810 curr = abs(miniq[j][i / 2] - code * 8); 1867 currd = abs(miniq[vcm][i / 2] - code * 8);
1811 1868
1812 if (curr < mind) { 1869 if (currd < mind) {
1813 mind = curr; 1870 mind = currd;
1814 minvcm = j; 1871 minvcm = vcm;
1815 } 1872 }
1816 1873
1817 if (results[j][i] < minpoll) 1874 if (results[vcm][i] < minpoll)
1818 minpoll = results[j][i]; 1875 minpoll = results[vcm][i];
1819 } 1876 }
1820 results_min[i] = minpoll; 1877 results_min[i] = minpoll;
1821 vcm_final[i] = minvcm; 1878 vcm_final[i] = minvcm;
1822 } 1879 }
1823 1880
1824 if (type != 1) 1881 if (type != N_RSSI_W2)
1825 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); 1882 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1826 1883
1827 for (i = 0; i < 4; i++) { 1884 for (i = 0; i < 4; i++) {
@@ -1836,7 +1893,7 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1836 offset[i] = code - 32; 1893 offset[i] = code - 32;
1837 1894
1838 core = (i / 2) ? 2 : 1; 1895 core = (i / 2) ? 2 : 1;
1839 rail = (i % 2) ? 1 : 0; 1896 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
1840 1897
1841 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, 1898 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1842 type); 1899 type);
@@ -1847,37 +1904,37 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1847 1904
1848 switch (state[2]) { 1905 switch (state[2]) {
1849 case 1: 1906 case 1:
1850 b43_nphy_rssi_select(dev, 1, 2); 1907 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
1851 break; 1908 break;
1852 case 4: 1909 case 4:
1853 b43_nphy_rssi_select(dev, 1, 0); 1910 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
1854 break; 1911 break;
1855 case 2: 1912 case 2:
1856 b43_nphy_rssi_select(dev, 1, 1); 1913 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
1857 break; 1914 break;
1858 default: 1915 default:
1859 b43_nphy_rssi_select(dev, 1, 1); 1916 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
1860 break; 1917 break;
1861 } 1918 }
1862 1919
1863 switch (state[3]) { 1920 switch (state[3]) {
1864 case 1: 1921 case 1:
1865 b43_nphy_rssi_select(dev, 2, 2); 1922 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
1866 break; 1923 break;
1867 case 4: 1924 case 4:
1868 b43_nphy_rssi_select(dev, 2, 0); 1925 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
1869 break; 1926 break;
1870 default: 1927 default:
1871 b43_nphy_rssi_select(dev, 2, 1); 1928 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
1872 break; 1929 break;
1873 } 1930 }
1874 1931
1875 b43_nphy_rssi_select(dev, 0, type); 1932 b43_nphy_rssi_select(dev, 0, type);
1876 1933
1877 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); 1934 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1878 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); 1935 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1879 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); 1936 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1880 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); 1937 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1881 1938
1882 b43_nphy_classifier(dev, 7, class); 1939 b43_nphy_classifier(dev, 7, class);
1883 b43_nphy_write_clip_detection(dev, clip_state); 1940 b43_nphy_write_clip_detection(dev, clip_state);
@@ -1895,9 +1952,9 @@ static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1895 if (dev->phy.rev >= 3) { 1952 if (dev->phy.rev >= 3) {
1896 b43_nphy_rev3_rssi_cal(dev); 1953 b43_nphy_rev3_rssi_cal(dev);
1897 } else { 1954 } else {
1898 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z); 1955 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
1899 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X); 1956 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
1900 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y); 1957 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
1901 } 1958 }
1902} 1959}
1903 1960
@@ -1930,10 +1987,8 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1930 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); 1987 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1931 1988
1932 /* Set Clip 2 detect */ 1989 /* Set Clip 2 detect */
1933 b43_phy_set(dev, B43_NPHY_C1_CGAINI, 1990 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1934 B43_NPHY_C1_CGAINI_CL2DETECT); 1991 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1935 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1936 B43_NPHY_C2_CGAINI_CL2DETECT);
1937 1992
1938 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, 1993 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1939 0x17); 1994 0x17);
@@ -1967,22 +2022,22 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1967 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); 2022 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1968 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); 2023 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1969 2024
1970 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain); 2025 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
1971 b43_phy_write(dev, 0x2A7, e->init_gain); 2026 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2027
1972 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, 2028 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1973 e->rfseq_init); 2029 e->rfseq_init);
1974 2030
1975 /* TODO: check defines. Do not match variables names */ 2031 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
1976 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain); 2032 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
1977 b43_phy_write(dev, 0x2A9, e->cliphi_gain); 2033 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
1978 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain); 2034 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
1979 b43_phy_write(dev, 0x2AB, e->clipmd_gain); 2035 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
1980 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain); 2036 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
1981 b43_phy_write(dev, 0x2AD, e->cliplo_gain); 2037
1982 2038 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
1983 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin); 2039 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
1984 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl); 2040 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
1985 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1986 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); 2041 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1987 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); 2042 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1988 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 2043 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
@@ -2164,8 +2219,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2164 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); 2219 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2165 } 2220 }
2166 if (phy->rev <= 8) { 2221 if (phy->rev <= 8) {
2167 b43_phy_write(dev, 0x23F, 0x1B0); 2222 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2168 b43_phy_write(dev, 0x240, 0x1B0); 2223 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2169 } 2224 }
2170 if (phy->rev >= 8) 2225 if (phy->rev >= 8)
2171 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); 2226 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
@@ -2182,8 +2237,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2182 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, 2237 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2183 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); 2238 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2184 2239
2185 b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000); 2240 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2186 b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000); 2241 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2187 2242
2188 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154); 2243 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2189 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159); 2244 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
@@ -2260,11 +2315,11 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2260 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), 2315 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2261 rx2tx_lut_40_11n); 2316 rx2tx_lut_40_11n);
2262 } 2317 }
2263 b43_nphy_rf_control_override_rev7(dev, 16, 1, 3, false, 2); 2318 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
2264 } 2319 }
2265 b43_phy_write(dev, 0x32F, 0x3); 2320 b43_phy_write(dev, 0x32F, 0x3);
2266 if (phy->radio_rev == 4 || phy->radio_rev == 6) 2321 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2267 b43_nphy_rf_control_override_rev7(dev, 4, 1, 3, false, 0); 2322 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2268 2323
2269 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) { 2324 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2270 if (sprom->revision && 2325 if (sprom->revision &&
@@ -2450,8 +2505,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2450 u16 tmp16; 2505 u16 tmp16;
2451 u32 tmp32; 2506 u32 tmp32;
2452 2507
2453 b43_phy_write(dev, 0x23f, 0x1f8); 2508 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2454 b43_phy_write(dev, 0x240, 0x1f8); 2509 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
2455 2510
2456 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); 2511 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2457 tmp32 &= 0xffffff; 2512 tmp32 &= 0xffffff;
@@ -2464,8 +2519,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2464 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); 2519 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2465 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); 2520 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2466 2521
2467 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); 2522 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2468 b43_phy_write(dev, 0x2AE, 0x000C); 2523 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
2469 2524
2470 /* TX to RX */ 2525 /* TX to RX */
2471 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 2526 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
@@ -2490,7 +2545,7 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2490 0x2 : 0x9C40; 2545 0x2 : 0x9C40;
2491 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); 2546 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2492 2547
2493 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700); 2548 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
2494 2549
2495 if (!dev->phy.is_40mhz) { 2550 if (!dev->phy.is_40mhz) {
2496 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); 2551 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
@@ -2542,18 +2597,18 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2542 } 2597 }
2543 2598
2544 /* Dropped probably-always-true condition */ 2599 /* Dropped probably-always-true condition */
2545 b43_phy_write(dev, 0x224, 0x03eb); 2600 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2546 b43_phy_write(dev, 0x225, 0x03eb); 2601 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
2547 b43_phy_write(dev, 0x226, 0x0341); 2602 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2548 b43_phy_write(dev, 0x227, 0x0341); 2603 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2549 b43_phy_write(dev, 0x228, 0x042b); 2604 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2550 b43_phy_write(dev, 0x229, 0x042b); 2605 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2551 b43_phy_write(dev, 0x22a, 0x0381); 2606 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2552 b43_phy_write(dev, 0x22b, 0x0381); 2607 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2553 b43_phy_write(dev, 0x22c, 0x042b); 2608 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2554 b43_phy_write(dev, 0x22d, 0x042b); 2609 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2555 b43_phy_write(dev, 0x22e, 0x0381); 2610 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2556 b43_phy_write(dev, 0x22f, 0x0381); 2611 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
2557 2612
2558 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) 2613 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2559 ; /* TODO: 0x0080000000000000 HF */ 2614 ; /* TODO: 0x0080000000000000 HF */
@@ -2572,7 +2627,7 @@ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2572 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; 2627 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
2573 2628
2574 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || 2629 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
2575 dev->dev->board_type == 0x8B) { 2630 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
2576 delays1[0] = 0x1; 2631 delays1[0] = 0x1;
2577 delays1[5] = 0x14; 2632 delays1[5] = 0x14;
2578 } 2633 }
@@ -2789,10 +2844,6 @@ static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2789 * Tx and Rx 2844 * Tx and Rx
2790 **************************************************/ 2845 **************************************************/
2791 2846
2792void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
2793{//TODO
2794}
2795
2796static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev) 2847static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2797{//TODO 2848{//TODO
2798} 2849}
@@ -3124,21 +3175,21 @@ static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3124 b43_nphy_ipa_internal_tssi_setup(dev); 3175 b43_nphy_ipa_internal_tssi_setup(dev);
3125 3176
3126 if (phy->rev >= 7) 3177 if (phy->rev >= 7)
3127 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, false, 0); 3178 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3128 else if (phy->rev >= 3) 3179 else if (phy->rev >= 3)
3129 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false); 3180 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3130 3181
3131 b43_nphy_stop_playback(dev); 3182 b43_nphy_stop_playback(dev);
3132 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false); 3183 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3133 udelay(20); 3184 udelay(20);
3134 tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1); 3185 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3135 b43_nphy_stop_playback(dev); 3186 b43_nphy_stop_playback(dev);
3136 b43_nphy_rssi_select(dev, 0, 0); 3187 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3137 3188
3138 if (phy->rev >= 7) 3189 if (phy->rev >= 7)
3139 b43_nphy_rf_control_override_rev7(dev, 0x2000, 0, 3, true, 0); 3190 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3140 else if (phy->rev >= 3) 3191 else if (phy->rev >= 3)
3141 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true); 3192 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3142 3193
3143 if (phy->rev >= 3) { 3194 if (phy->rev >= 3) {
3144 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; 3195 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
@@ -3577,8 +3628,8 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3577 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); 3628 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3578 } 3629 }
3579 3630
3580 b43_nphy_rf_control_intc_override(dev, 2, 0, 3); 3631 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
3581 b43_nphy_rf_control_override(dev, 8, 0, 3, false); 3632 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
3582 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 3633 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3583 3634
3584 if (core == 0) { 3635 if (core == 0) {
@@ -3588,8 +3639,10 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3588 rxval = 4; 3639 rxval = 4;
3589 txval = 2; 3640 txval = 2;
3590 } 3641 }
3591 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1)); 3642 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3592 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core)); 3643 core + 1);
3644 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3645 2 - core);
3593} 3646}
3594#endif 3647#endif
3595 3648
@@ -3851,9 +3904,13 @@ static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3851 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 3904 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3852 } 3905 }
3853 3906
3854 /* TODO use some definitions */ 3907 if (dev->phy.rev >= 7) {
3855 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); 3908 } else {
3856 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); 3909 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
3910 rssical_radio_regs[0]);
3911 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
3912 rssical_radio_regs[1]);
3913 }
3857 3914
3858 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); 3915 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3859 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); 3916 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
@@ -3884,75 +3941,75 @@ static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3884 tmp = (i == 0) ? 0x2000 : 0x3000; 3941 tmp = (i == 0) ? 0x2000 : 0x3000;
3885 offset = i * 11; 3942 offset = i * 11;
3886 3943
3887 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); 3944 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
3888 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); 3945 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
3889 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); 3946 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
3890 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); 3947 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
3891 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); 3948 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
3892 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); 3949 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
3893 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); 3950 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
3894 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); 3951 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
3895 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); 3952 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
3896 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); 3953 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
3897 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); 3954 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
3898 3955
3899 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 3956 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3900 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); 3957 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3901 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 3958 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3902 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 3959 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
3903 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 3960 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
3904 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 3961 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
3905 if (nphy->ipa5g_on) { 3962 if (nphy->ipa5g_on) {
3906 b43_radio_write16(dev, tmp | B2055_PADDRV, 4); 3963 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
3907 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); 3964 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
3908 } else { 3965 } else {
3909 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 3966 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
3910 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); 3967 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
3911 } 3968 }
3912 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 3969 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
3913 } else { 3970 } else {
3914 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); 3971 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3915 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 3972 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3916 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 3973 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
3917 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 3974 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
3918 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 3975 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
3919 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); 3976 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
3920 if (nphy->ipa2g_on) { 3977 if (nphy->ipa2g_on) {
3921 b43_radio_write16(dev, tmp | B2055_PADDRV, 6); 3978 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
3922 b43_radio_write16(dev, tmp | B2055_XOCTL2, 3979 b43_radio_write(dev, tmp | B2055_XOCTL2,
3923 (dev->phy.rev < 5) ? 0x11 : 0x01); 3980 (dev->phy.rev < 5) ? 0x11 : 0x01);
3924 } else { 3981 } else {
3925 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 3982 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
3926 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 3983 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
3927 } 3984 }
3928 } 3985 }
3929 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); 3986 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
3930 b43_radio_write16(dev, tmp | B2055_XOMISC, 0); 3987 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
3931 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); 3988 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
3932 } 3989 }
3933 } else { 3990 } else {
3934 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); 3991 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
3935 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); 3992 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3936 3993
3937 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); 3994 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
3938 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); 3995 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3939 3996
3940 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); 3997 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
3941 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); 3998 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3942 3999
3943 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); 4000 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
3944 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); 4001 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3945 4002
3946 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); 4003 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
3947 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); 4004 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
3948 4005
3949 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & 4006 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3950 B43_NPHY_BANDCTL_5GHZ)) { 4007 B43_NPHY_BANDCTL_5GHZ)) {
3951 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); 4008 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
3952 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); 4009 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
3953 } else { 4010 } else {
3954 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); 4011 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
3955 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); 4012 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
3956 } 4013 }
3957 4014
3958 if (dev->phy.rev < 2) { 4015 if (dev->phy.rev < 2) {
@@ -4148,9 +4205,9 @@ static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4148 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 4205 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4149 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 4206 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4150 4207
4151 b43_nphy_rf_control_intc_override(dev, 2, 1, 3); 4208 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4152 b43_nphy_rf_control_intc_override(dev, 1, 2, 1); 4209 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4153 b43_nphy_rf_control_intc_override(dev, 1, 8, 2); 4210 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
4154 4211
4155 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 4212 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4156 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 4213 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
@@ -4683,7 +4740,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4683 4740
4684 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | 4741 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4685 (cur_lna << 2)); 4742 (cur_lna << 2));
4686 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, 4743 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
4687 false); 4744 false);
4688 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 4745 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4689 b43_nphy_stop_playback(dev); 4746 b43_nphy_stop_playback(dev);
@@ -4732,7 +4789,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4732 break; 4789 break;
4733 } 4790 }
4734 4791
4735 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); 4792 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
4736 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 4793 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4737 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 4794 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4738 4795
@@ -4801,18 +4858,6 @@ static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4801 * N-PHY init 4858 * N-PHY init
4802 **************************************************/ 4859 **************************************************/
4803 4860
4804/*
4805 * Upload the N-PHY tables.
4806 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
4807 */
4808static void b43_nphy_tables_init(struct b43_wldev *dev)
4809{
4810 if (dev->phy.rev < 3)
4811 b43_nphy_rev0_1_2_tables_init(dev);
4812 else
4813 b43_nphy_rev3plus_tables_init(dev);
4814}
4815
4816/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ 4861/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4817static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) 4862static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4818{ 4863{
@@ -4892,7 +4937,7 @@ static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4892} 4937}
4893 4938
4894/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */ 4939/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
4895int b43_phy_initn(struct b43_wldev *dev) 4940static int b43_phy_initn(struct b43_wldev *dev)
4896{ 4941{
4897 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4942 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4898 struct b43_phy *phy = &dev->phy; 4943 struct b43_phy *phy = &dev->phy;
@@ -4962,7 +5007,7 @@ int b43_phy_initn(struct b43_wldev *dev)
4962 5007
4963 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || 5008 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
4964 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && 5009 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4965 dev->dev->board_type == 0x8B)) 5010 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
4966 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); 5011 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4967 else 5012 else
4968 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); 5013 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
@@ -5104,63 +5149,11 @@ static void b43_chantab_phy_upload(struct b43_wldev *dev,
5104/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */ 5149/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5105static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid) 5150static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5106{ 5151{
5107 struct bcma_drv_cc __maybe_unused *cc;
5108 u32 __maybe_unused pmu_ctl;
5109
5110 switch (dev->dev->bus_type) { 5152 switch (dev->dev->bus_type) {
5111#ifdef CONFIG_B43_BCMA 5153#ifdef CONFIG_B43_BCMA
5112 case B43_BUS_BCMA: 5154 case B43_BUS_BCMA:
5113 cc = &dev->dev->bdev->bus->drv_cc; 5155 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5114 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) { 5156 avoid);
5115 if (avoid) {
5116 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
5117 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
5118 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
5119 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5120 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
5121 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5122 } else {
5123 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
5124 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
5125 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
5126 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5127 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
5128 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5129 }
5130 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
5131 } else if (dev->dev->chip_id == 0x4716) {
5132 if (avoid) {
5133 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
5134 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
5135 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
5136 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5137 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
5138 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5139 } else {
5140 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
5141 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
5142 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
5143 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
5144 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
5145 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
5146 }
5147 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
5148 BCMA_CC_PMU_CTL_NOILPONW;
5149 } else if (dev->dev->chip_id == 0x4322 ||
5150 dev->dev->chip_id == 0x4340 ||
5151 dev->dev->chip_id == 0x4341) {
5152 bcma_chipco_pll_write(cc, 0x0, 0x11100070);
5153 bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
5154 bcma_chipco_pll_write(cc, 0x5, 0x88888854);
5155 if (avoid)
5156 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
5157 else
5158 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
5159 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
5160 } else {
5161 return;
5162 }
5163 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
5164 break; 5157 break;
5165#endif 5158#endif
5166#ifdef CONFIG_B43_SSB 5159#ifdef CONFIG_B43_SSB
@@ -5531,8 +5524,9 @@ static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5531static int b43_nphy_op_switch_channel(struct b43_wldev *dev, 5524static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5532 unsigned int new_channel) 5525 unsigned int new_channel)
5533{ 5526{
5534 struct ieee80211_channel *channel = dev->wl->hw->conf.channel; 5527 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5535 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type; 5528 enum nl80211_channel_type channel_type =
5529 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5536 5530
5537 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 5531 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5538 if ((new_channel < 1) || (new_channel > 14)) 5532 if ((new_channel < 1) || (new_channel > 14))
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h
index 092c0140c249..9a5b6bc27d24 100644
--- a/drivers/net/wireless/b43/phy_n.h
+++ b/drivers/net/wireless/b43/phy_n.h
@@ -54,10 +54,15 @@
54#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7 54#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
55#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ 55#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
56#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */ 56#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
57#define B43_NPHY_REV3_C1_INITGAIN_A B43_PHY_N(0x020)
57#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */ 58#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
59#define B43_NPHY_REV3_C1_INITGAIN_B B43_PHY_N(0x021)
58#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */ 60#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
61#define B43_NPHY_REV3_C1_CLIP_HIGAIN_A B43_PHY_N(0x022)
59#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */ 62#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
63#define B43_NPHY_REV3_C1_CLIP_HIGAIN_B B43_PHY_N(0x023)
60#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */ 64#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */
65#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A B43_PHY_N(0x024)
61#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */ 66#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */
62#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */ 67#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
63#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */ 68#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
@@ -107,10 +112,15 @@
107#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7 112#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
108#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */ 113#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
109#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */ 114#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
115#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B B43_PHY_N(0x036)
110#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */ 116#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
117#define B43_NPHY_REV3_C1_CLIP_LOGAIN_A B43_PHY_N(0x037)
111#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */ 118#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
119#define B43_NPHY_REV3_C1_CLIP_LOGAIN_B B43_PHY_N(0x038)
112#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */ 120#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
121#define B43_NPHY_REV3_C1_CLIP2_GAIN_A B43_PHY_N(0x039)
113#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */ 122#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
123#define B43_NPHY_REV3_C1_CLIP2_GAIN_B B43_PHY_N(0x03A)
114#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */ 124#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */
115#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */ 125#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
116#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */ 126#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
@@ -706,10 +716,146 @@
706#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */ 716#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */
707#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ 717#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
708#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 718#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
719#define B43_NPHY_ED_CRSEN B43_PHY_N(0x223)
720#define B43_NPHY_ED_CRS40ASSERTTHRESH0 B43_PHY_N(0x224)
721#define B43_NPHY_ED_CRS40ASSERTTHRESH1 B43_PHY_N(0x225)
722#define B43_NPHY_ED_CRS40DEASSERTTHRESH0 B43_PHY_N(0x226)
723#define B43_NPHY_ED_CRS40DEASSERTTHRESH1 B43_PHY_N(0x227)
724#define B43_NPHY_ED_CRS20LASSERTTHRESH0 B43_PHY_N(0x228)
725#define B43_NPHY_ED_CRS20LASSERTTHRESH1 B43_PHY_N(0x229)
726#define B43_NPHY_ED_CRS20LDEASSERTTHRESH0 B43_PHY_N(0x22A)
727#define B43_NPHY_ED_CRS20LDEASSERTTHRESH1 B43_PHY_N(0x22B)
728#define B43_NPHY_ED_CRS20UASSERTTHRESH0 B43_PHY_N(0x22C)
729#define B43_NPHY_ED_CRS20UASSERTTHRESH1 B43_PHY_N(0x22D)
730#define B43_NPHY_ED_CRS20UDEASSERTTHRESH0 B43_PHY_N(0x22E)
731#define B43_NPHY_ED_CRS20UDEASSERTTHRESH1 B43_PHY_N(0x22F)
732#define B43_NPHY_ED_CRS B43_PHY_N(0x230)
733#define B43_NPHY_TIMEOUTEN B43_PHY_N(0x231)
734#define B43_NPHY_OFDMPAYDECODETIMEOUTLEN B43_PHY_N(0x232)
735#define B43_NPHY_CCKPAYDECODETIMEOUTLEN B43_PHY_N(0x233)
736#define B43_NPHY_NONPAYDECODETIMEOUTLEN B43_PHY_N(0x234)
737#define B43_NPHY_TIMEOUTSTATUS B43_PHY_N(0x235)
738#define B43_NPHY_RFCTRLCORE0GPIO0 B43_PHY_N(0x236)
739#define B43_NPHY_RFCTRLCORE0GPIO1 B43_PHY_N(0x237)
740#define B43_NPHY_RFCTRLCORE0GPIO2 B43_PHY_N(0x238)
741#define B43_NPHY_RFCTRLCORE0GPIO3 B43_PHY_N(0x239)
742#define B43_NPHY_RFCTRLCORE1GPIO0 B43_PHY_N(0x23A)
743#define B43_NPHY_RFCTRLCORE1GPIO1 B43_PHY_N(0x23B)
744#define B43_NPHY_RFCTRLCORE1GPIO2 B43_PHY_N(0x23C)
745#define B43_NPHY_RFCTRLCORE1GPIO3 B43_PHY_N(0x23D)
746#define B43_NPHY_BPHYTESTCONTROL B43_PHY_N(0x23E)
747/* REV3+ */
748#define B43_NPHY_FORCEFRONT0 B43_PHY_N(0x23F)
749#define B43_NPHY_FORCEFRONT1 B43_PHY_N(0x240)
750#define B43_NPHY_NORMVARHYSTTH B43_PHY_N(0x241)
751#define B43_NPHY_TXCCKERROR B43_PHY_N(0x242)
752#define B43_NPHY_AFESEQINITDACGAIN B43_PHY_N(0x243)
753#define B43_NPHY_TXANTSWLUT B43_PHY_N(0x244)
754#define B43_NPHY_CORECONFIG B43_PHY_N(0x245)
755#define B43_NPHY_ANTENNADIVDWELLTIME B43_PHY_N(0x246)
756#define B43_NPHY_ANTENNACCKDIVDWELLTIME B43_PHY_N(0x247)
757#define B43_NPHY_ANTENNADIVBACKOFFGAIN B43_PHY_N(0x248)
758#define B43_NPHY_ANTENNADIVMINGAIN B43_PHY_N(0x249)
759#define B43_NPHY_BRDSEL_NORMVARHYSTTH B43_PHY_N(0x24A)
760#define B43_NPHY_RXANTSWITCHCTRL B43_PHY_N(0x24B)
761#define B43_NPHY_ENERGYDROPTIMEOUTLEN2 B43_PHY_N(0x24C)
762#define B43_NPHY_ML_LOG_TXEVM0 B43_PHY_N(0x250)
763#define B43_NPHY_ML_LOG_TXEVM1 B43_PHY_N(0x251)
764#define B43_NPHY_ML_LOG_TXEVM2 B43_PHY_N(0x252)
765#define B43_NPHY_ML_LOG_TXEVM3 B43_PHY_N(0x253)
766#define B43_NPHY_ML_LOG_TXEVM4 B43_PHY_N(0x254)
767#define B43_NPHY_ML_LOG_TXEVM5 B43_PHY_N(0x255)
768#define B43_NPHY_ML_LOG_TXEVM6 B43_PHY_N(0x256)
769#define B43_NPHY_ML_LOG_TXEVM7 B43_PHY_N(0x257)
770#define B43_NPHY_ML_SCALE_TWEAK B43_PHY_N(0x258)
771#define B43_NPHY_MLUA B43_PHY_N(0x259)
772#define B43_NPHY_ZFUA B43_PHY_N(0x25A)
773#define B43_NPHY_CHANUPSYM01 B43_PHY_N(0x25B)
774#define B43_NPHY_CHANUPSYM2 B43_PHY_N(0x25C)
775#define B43_NPHY_RXSTRNFILT20NUM00 B43_PHY_N(0x25D)
776#define B43_NPHY_RXSTRNFILT20NUM01 B43_PHY_N(0x25E)
777#define B43_NPHY_RXSTRNFILT20NUM02 B43_PHY_N(0x25F)
778#define B43_NPHY_RXSTRNFILT20DEN00 B43_PHY_N(0x260)
779#define B43_NPHY_RXSTRNFILT20DEN01 B43_PHY_N(0x261)
780#define B43_NPHY_RXSTRNFILT20NUM10 B43_PHY_N(0x262)
781#define B43_NPHY_RXSTRNFILT20NUM11 B43_PHY_N(0x263)
782#define B43_NPHY_RXSTRNFILT20NUM12 B43_PHY_N(0x264)
783#define B43_NPHY_RXSTRNFILT20DEN10 B43_PHY_N(0x265)
784#define B43_NPHY_RXSTRNFILT20DEN11 B43_PHY_N(0x266)
785#define B43_NPHY_RXSTRNFILT40NUM00 B43_PHY_N(0x267)
786#define B43_NPHY_RXSTRNFILT40NUM01 B43_PHY_N(0x268)
787#define B43_NPHY_RXSTRNFILT40NUM02 B43_PHY_N(0x269)
788#define B43_NPHY_RXSTRNFILT40DEN00 B43_PHY_N(0x26A)
789#define B43_NPHY_RXSTRNFILT40DEN01 B43_PHY_N(0x26B)
790#define B43_NPHY_RXSTRNFILT40NUM10 B43_PHY_N(0x26C)
791#define B43_NPHY_RXSTRNFILT40NUM11 B43_PHY_N(0x26D)
792#define B43_NPHY_RXSTRNFILT40NUM12 B43_PHY_N(0x26E)
793#define B43_NPHY_RXSTRNFILT40DEN10 B43_PHY_N(0x26F)
794#define B43_NPHY_RXSTRNFILT40DEN11 B43_PHY_N(0x270)
795#define B43_NPHY_CRSHIGHPOWTHRESHOLD1 B43_PHY_N(0x271)
796#define B43_NPHY_CRSHIGHPOWTHRESHOLD2 B43_PHY_N(0x272)
797#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD B43_PHY_N(0x273)
798#define B43_NPHY_CRSHIGHPOWTHRESHOLD1L B43_PHY_N(0x274)
799#define B43_NPHY_CRSHIGHPOWTHRESHOLD2L B43_PHY_N(0x275)
800#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL B43_PHY_N(0x276)
801#define B43_NPHY_CRSHIGHPOWTHRESHOLD1U B43_PHY_N(0x277)
802#define B43_NPHY_CRSHIGHPOWTHRESHOLD2U B43_PHY_N(0x278)
803#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU B43_PHY_N(0x279)
804#define B43_NPHY_CRSACIDETECTTHRESH B43_PHY_N(0x27A)
805#define B43_NPHY_CRSACIDETECTTHRESHL B43_PHY_N(0x27B)
806#define B43_NPHY_CRSACIDETECTTHRESHU B43_PHY_N(0x27C)
807#define B43_NPHY_CRSMINPOWER0 B43_PHY_N(0x27D)
808#define B43_NPHY_CRSMINPOWER1 B43_PHY_N(0x27E)
809#define B43_NPHY_CRSMINPOWER2 B43_PHY_N(0x27F)
810#define B43_NPHY_CRSMINPOWERL0 B43_PHY_N(0x280)
811#define B43_NPHY_CRSMINPOWERL1 B43_PHY_N(0x281)
812#define B43_NPHY_CRSMINPOWERL2 B43_PHY_N(0x282)
813#define B43_NPHY_CRSMINPOWERU0 B43_PHY_N(0x283)
814#define B43_NPHY_CRSMINPOWERU1 B43_PHY_N(0x284)
815#define B43_NPHY_CRSMINPOWERU2 B43_PHY_N(0x285)
816#define B43_NPHY_STRPARAM B43_PHY_N(0x286)
817#define B43_NPHY_STRPARAML B43_PHY_N(0x287)
818#define B43_NPHY_STRPARAMU B43_PHY_N(0x288)
819#define B43_NPHY_BPHYCRSMINPOWER0 B43_PHY_N(0x289)
820#define B43_NPHY_BPHYCRSMINPOWER1 B43_PHY_N(0x28A)
821#define B43_NPHY_BPHYCRSMINPOWER2 B43_PHY_N(0x28B)
822#define B43_NPHY_BPHYFILTDEN0COEF B43_PHY_N(0x28C)
823#define B43_NPHY_BPHYFILTDEN1COEF B43_PHY_N(0x28D)
824#define B43_NPHY_BPHYFILTDEN2COEF B43_PHY_N(0x28E)
825#define B43_NPHY_BPHYFILTNUM0COEF B43_PHY_N(0x28F)
826#define B43_NPHY_BPHYFILTNUM1COEF B43_PHY_N(0x290)
827#define B43_NPHY_BPHYFILTNUM2COEF B43_PHY_N(0x291)
828#define B43_NPHY_BPHYFILTNUM01COEF2 B43_PHY_N(0x292)
829#define B43_NPHY_BPHYFILTBYPASS B43_PHY_N(0x293)
830#define B43_NPHY_SGILTRNOFFSET B43_PHY_N(0x294)
831#define B43_NPHY_RADAR_T2_MIN B43_PHY_N(0x295)
832#define B43_NPHY_TXPWRCTRLDAMPING B43_PHY_N(0x296)
709#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */ 833#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */
710#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */ 834#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */
835#define B43_NPHY_EPS_OVERRIDEI_0 B43_PHY_N(0x299)
836#define B43_NPHY_EPS_OVERRIDEQ_0 B43_PHY_N(0x29A)
711#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */ 837#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */
712#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */ 838#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */
839#define B43_NPHY_EPS_OVERRIDEI_1 B43_PHY_N(0x29D)
840#define B43_NPHY_EPS_OVERRIDEQ_1 B43_PHY_N(0x29E)
841#define B43_NPHY_PAPD_CAL_ADDRESS B43_PHY_N(0x29F)
842#define B43_NPHY_PAPD_CAL_YREFEPSILON B43_PHY_N(0x2A0)
843#define B43_NPHY_PAPD_CAL_SETTLE B43_PHY_N(0x2A1)
844#define B43_NPHY_PAPD_CAL_CORRELATE B43_PHY_N(0x2A2)
845#define B43_NPHY_PAPD_CAL_SHIFTS0 B43_PHY_N(0x2A3)
846#define B43_NPHY_PAPD_CAL_SHIFTS1 B43_PHY_N(0x2A4)
847#define B43_NPHY_SAMPLE_START_ADDR B43_PHY_N(0x2A5)
848#define B43_NPHY_RADAR_ADC_TO_DBM B43_PHY_N(0x2A6)
849#define B43_NPHY_REV3_C2_INITGAIN_A B43_PHY_N(0x2A7)
850#define B43_NPHY_REV3_C2_INITGAIN_B B43_PHY_N(0x2A8)
851#define B43_NPHY_REV3_C2_CLIP_HIGAIN_A B43_PHY_N(0x2A9)
852#define B43_NPHY_REV3_C2_CLIP_HIGAIN_B B43_PHY_N(0x2AA)
853#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A B43_PHY_N(0x2AB)
854#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B B43_PHY_N(0x2AC)
855#define B43_NPHY_REV3_C2_CLIP_LOGAIN_A B43_PHY_N(0x2AD)
856#define B43_NPHY_REV3_C2_CLIP_LOGAIN_B B43_PHY_N(0x2AE)
857#define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF)
858#define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0)
713 859
714#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */ 860#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */
715#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A) 861#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A)
diff --git a/drivers/net/wireless/b43/radio_2056.c b/drivers/net/wireless/b43/radio_2056.c
index ce037fb6789a..b4fd9345d673 100644
--- a/drivers/net/wireless/b43/radio_2056.c
+++ b/drivers/net/wireless/b43/radio_2056.c
@@ -2980,7 +2980,7 @@ static const struct b2056_inittab_entry b2056_inittab_rev8_rx[] = {
2980 .rx = prefix##_rx, \ 2980 .rx = prefix##_rx, \
2981 .rx_length = ARRAY_SIZE(prefix##_rx) 2981 .rx_length = ARRAY_SIZE(prefix##_rx)
2982 2982
2983struct b2056_inittabs_pts b2056_inittabs[] = { 2983static const struct b2056_inittabs_pts b2056_inittabs[] = {
2984 [3] = { INITTABSPTS(b2056_inittab_rev3) }, 2984 [3] = { INITTABSPTS(b2056_inittab_rev3) },
2985 [4] = { INITTABSPTS(b2056_inittab_rev4) }, 2985 [4] = { INITTABSPTS(b2056_inittab_rev4) },
2986 [5] = { INITTABSPTS(b2056_inittab_rev5) }, 2986 [5] = { INITTABSPTS(b2056_inittab_rev5) },
@@ -9035,7 +9035,7 @@ static void b2056_upload_inittab(struct b43_wldev *dev, bool ghz5,
9035void b2056_upload_inittabs(struct b43_wldev *dev, 9035void b2056_upload_inittabs(struct b43_wldev *dev,
9036 bool ghz5, bool ignore_uploadflag) 9036 bool ghz5, bool ignore_uploadflag)
9037{ 9037{
9038 struct b2056_inittabs_pts *pts; 9038 const struct b2056_inittabs_pts *pts;
9039 9039
9040 if (dev->phy.rev >= ARRAY_SIZE(b2056_inittabs)) { 9040 if (dev->phy.rev >= ARRAY_SIZE(b2056_inittabs)) {
9041 B43_WARN_ON(1); 9041 B43_WARN_ON(1);
@@ -9057,7 +9057,7 @@ void b2056_upload_inittabs(struct b43_wldev *dev,
9057 9057
9058void b2056_upload_syn_pll_cp2(struct b43_wldev *dev, bool ghz5) 9058void b2056_upload_syn_pll_cp2(struct b43_wldev *dev, bool ghz5)
9059{ 9059{
9060 struct b2056_inittabs_pts *pts; 9060 const struct b2056_inittabs_pts *pts;
9061 const struct b2056_inittab_entry *e; 9061 const struct b2056_inittab_entry *e;
9062 9062
9063 if (dev->phy.rev >= ARRAY_SIZE(b2056_inittabs)) { 9063 if (dev->phy.rev >= ARRAY_SIZE(b2056_inittabs)) {
diff --git a/drivers/net/wireless/b43/radio_2059.c b/drivers/net/wireless/b43/radio_2059.c
index d4ce8a12ff9a..38e31d857e3e 100644
--- a/drivers/net/wireless/b43/radio_2059.c
+++ b/drivers/net/wireless/b43/radio_2059.c
@@ -27,7 +27,7 @@
27 27
28#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \ 28#define RADIOREGS(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
29 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ 29 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
30 r20, r21, r22, r23, r24, r25, r26, r27, r28) \ 30 r20) \
31 .radio_syn16 = r00, \ 31 .radio_syn16 = r00, \
32 .radio_syn17 = r01, \ 32 .radio_syn17 = r01, \
33 .radio_syn22 = r02, \ 33 .radio_syn22 = r02, \
@@ -41,22 +41,14 @@
41 .radio_syn41 = r10, \ 41 .radio_syn41 = r10, \
42 .radio_syn43 = r11, \ 42 .radio_syn43 = r11, \
43 .radio_syn47 = r12, \ 43 .radio_syn47 = r12, \
44 .radio_syn4a = r13, \ 44 .radio_rxtx4a = r13, \
45 .radio_syn58 = r14, \ 45 .radio_rxtx58 = r14, \
46 .radio_syn5a = r15, \ 46 .radio_rxtx5a = r15, \
47 .radio_syn6a = r16, \ 47 .radio_rxtx6a = r16, \
48 .radio_syn6d = r17, \ 48 .radio_rxtx6d = r17, \
49 .radio_syn6e = r18, \ 49 .radio_rxtx6e = r18, \
50 .radio_syn92 = r19, \ 50 .radio_rxtx92 = r19, \
51 .radio_syn98 = r20, \ 51 .radio_rxtx98 = r20
52 .radio_rxtx4a = r21, \
53 .radio_rxtx58 = r22, \
54 .radio_rxtx5a = r23, \
55 .radio_rxtx6a = r24, \
56 .radio_rxtx6d = r25, \
57 .radio_rxtx6e = r26, \
58 .radio_rxtx92 = r27, \
59 .radio_rxtx98 = r28
60 52
61#define PHYREGS(r0, r1, r2, r3, r4, r5) \ 53#define PHYREGS(r0, r1, r2, r3, r4, r5) \
62 .phy_regs.bw1 = r0, \ 54 .phy_regs.bw1 = r0, \
@@ -70,91 +62,78 @@ static const struct b43_phy_ht_channeltab_e_radio2059 b43_phy_ht_channeltab_radi
70 { .freq = 2412, 62 { .freq = 2412,
71 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 63 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
72 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03, 64 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
73 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
74 0x00, 0x00, 0x00, 0xf0, 0x00), 65 0x00, 0x00, 0x00, 0xf0, 0x00),
75 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), 66 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
76 }, 67 },
77 { .freq = 2417, 68 { .freq = 2417,
78 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 69 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
79 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03, 70 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x03,
80 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
81 0x00, 0x00, 0x00, 0xf0, 0x00), 71 0x00, 0x00, 0x00, 0xf0, 0x00),
82 PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441), 72 PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
83 }, 73 },
84 { .freq = 2422, 74 { .freq = 2422,
85 RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76, 75 RADIOREGS(0x4e, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x76,
86 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03, 76 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
87 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
88 0x00, 0x00, 0x00, 0xf0, 0x00), 77 0x00, 0x00, 0x00, 0xf0, 0x00),
89 PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f), 78 PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
90 }, 79 },
91 { .freq = 2427, 80 { .freq = 2427,
92 RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b, 81 RADIOREGS(0x52, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x7b,
93 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03, 82 0x09, 0x0f, 0x09, 0x00, 0x09, 0x00, 0x61, 0x03,
94 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
95 0x00, 0x00, 0x00, 0xf0, 0x00), 83 0x00, 0x00, 0x00, 0xf0, 0x00),
96 PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d), 84 PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
97 }, 85 },
98 { .freq = 2432, 86 { .freq = 2432,
99 RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80, 87 RADIOREGS(0x55, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x80,
100 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03, 88 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
101 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
102 0x00, 0x00, 0x00, 0xf0, 0x00), 89 0x00, 0x00, 0x00, 0xf0, 0x00),
103 PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a), 90 PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
104 }, 91 },
105 { .freq = 2437, 92 { .freq = 2437,
106 RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85, 93 RADIOREGS(0x58, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x85,
107 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03, 94 0x09, 0x0f, 0x08, 0x00, 0x08, 0x00, 0x61, 0x03,
108 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
109 0x00, 0x00, 0x00, 0xf0, 0x00), 95 0x00, 0x00, 0x00, 0xf0, 0x00),
110 PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438), 96 PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
111 }, 97 },
112 { .freq = 2442, 98 { .freq = 2442,
113 RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a, 99 RADIOREGS(0x5c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8a,
114 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 100 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
115 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
116 0x00, 0x00, 0x00, 0xf0, 0x00), 101 0x00, 0x00, 0x00, 0xf0, 0x00),
117 PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436), 102 PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
118 }, 103 },
119 { .freq = 2447, 104 { .freq = 2447,
120 RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f, 105 RADIOREGS(0x5f, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x8f,
121 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 106 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
122 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
123 0x00, 0x00, 0x00, 0xf0, 0x00), 107 0x00, 0x00, 0x00, 0xf0, 0x00),
124 PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434), 108 PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
125 }, 109 },
126 { .freq = 2452, 110 { .freq = 2452,
127 RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94, 111 RADIOREGS(0x62, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x94,
128 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03, 112 0x09, 0x0f, 0x07, 0x00, 0x07, 0x00, 0x61, 0x03,
129 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
130 0x00, 0x00, 0x00, 0xf0, 0x00), 113 0x00, 0x00, 0x00, 0xf0, 0x00),
131 PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431), 114 PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
132 }, 115 },
133 { .freq = 2457, 116 { .freq = 2457,
134 RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99, 117 RADIOREGS(0x66, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x99,
135 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03, 118 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
136 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
137 0x00, 0x00, 0x00, 0xf0, 0x00), 119 0x00, 0x00, 0x00, 0xf0, 0x00),
138 PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f), 120 PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
139 }, 121 },
140 { .freq = 2462, 122 { .freq = 2462,
141 RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e, 123 RADIOREGS(0x69, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x9e,
142 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03, 124 0x09, 0x0f, 0x06, 0x00, 0x06, 0x00, 0x61, 0x03,
143 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
144 0x00, 0x00, 0x00, 0xf0, 0x00), 125 0x00, 0x00, 0x00, 0xf0, 0x00),
145 PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d), 126 PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
146 }, 127 },
147 { .freq = 2467, 128 { .freq = 2467,
148 RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3, 129 RADIOREGS(0x6c, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa3,
149 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03, 130 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
150 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
151 0x00, 0x00, 0x00, 0xf0, 0x00), 131 0x00, 0x00, 0x00, 0xf0, 0x00),
152 PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b), 132 PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
153 }, 133 },
154 { .freq = 2472, 134 { .freq = 2472,
155 RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8, 135 RADIOREGS(0x70, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0xa8,
156 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03, 136 0x09, 0x0f, 0x05, 0x00, 0x05, 0x00, 0x61, 0x03,
157 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x61, 0x03,
158 0x00, 0x00, 0x00, 0xf0, 0x00), 137 0x00, 0x00, 0x00, 0xf0, 0x00),
159 PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429), 138 PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
160 }, 139 },
diff --git a/drivers/net/wireless/b43/radio_2059.h b/drivers/net/wireless/b43/radio_2059.h
index e4d69e55e9fe..40a82d7f510c 100644
--- a/drivers/net/wireless/b43/radio_2059.h
+++ b/drivers/net/wireless/b43/radio_2059.h
@@ -5,9 +5,9 @@
5 5
6#include "phy_ht.h" 6#include "phy_ht.h"
7 7
8#define R2059_SYN 0x000 8#define R2059_C1 0x000
9#define R2059_TXRX0 0x400 9#define R2059_C2 0x400
10#define R2059_RXRX1 0x800 10#define R2059_C3 0x800
11#define R2059_ALL 0xC00 11#define R2059_ALL 0xC00
12 12
13/* Values for various registers uploaded on channel switching */ 13/* Values for various registers uploaded on channel switching */
@@ -28,14 +28,6 @@ struct b43_phy_ht_channeltab_e_radio2059 {
28 u8 radio_syn41; 28 u8 radio_syn41;
29 u8 radio_syn43; 29 u8 radio_syn43;
30 u8 radio_syn47; 30 u8 radio_syn47;
31 u8 radio_syn4a;
32 u8 radio_syn58;
33 u8 radio_syn5a;
34 u8 radio_syn6a;
35 u8 radio_syn6d;
36 u8 radio_syn6e;
37 u8 radio_syn92;
38 u8 radio_syn98;
39 u8 radio_rxtx4a; 31 u8 radio_rxtx4a;
40 u8 radio_rxtx58; 32 u8 radio_rxtx58;
41 u8 radio_rxtx5a; 33 u8 radio_rxtx5a;
diff --git a/drivers/net/wireless/b43/sdio.h b/drivers/net/wireless/b43/sdio.h
index fb633094403a..1e93926f388f 100644
--- a/drivers/net/wireless/b43/sdio.h
+++ b/drivers/net/wireless/b43/sdio.h
@@ -25,12 +25,12 @@ void b43_sdio_exit(void);
25#else /* CONFIG_B43_SDIO */ 25#else /* CONFIG_B43_SDIO */
26 26
27 27
28int b43_sdio_request_irq(struct b43_wldev *dev, 28static inline int b43_sdio_request_irq(struct b43_wldev *dev,
29 void (*handler)(struct b43_wldev *dev)) 29 void (*handler)(struct b43_wldev *dev))
30{ 30{
31 return -ENODEV; 31 return -ENODEV;
32} 32}
33void b43_sdio_free_irq(struct b43_wldev *dev) 33static inline void b43_sdio_free_irq(struct b43_wldev *dev)
34{ 34{
35} 35}
36static inline int b43_sdio_init(void) 36static inline int b43_sdio_init(void)
diff --git a/drivers/net/wireless/b43/tables_nphy.c b/drivers/net/wireless/b43/tables_nphy.c
index aaca60c6f575..94c755fdda14 100644
--- a/drivers/net/wireless/b43/tables_nphy.c
+++ b/drivers/net/wireless/b43/tables_nphy.c
@@ -2174,7 +2174,7 @@ static const u16 b43_ntab_loftlt1_r3[] = {
2174/* volatile tables, PHY revision >= 3 */ 2174/* volatile tables, PHY revision >= 3 */
2175 2175
2176/* indexed by antswctl2g */ 2176/* indexed by antswctl2g */
2177static const u16 b43_ntab_antswctl2g_r3[4][32] = { 2177static const u16 b43_ntab_antswctl_r3[4][32] = {
2178 { 2178 {
2179 0x0082, 0x0082, 0x0211, 0x0222, 0x0328, 2179 0x0082, 0x0082, 0x0211, 0x0222, 0x0328,
2180 0x0000, 0x0000, 0x0000, 0x0144, 0x0000, 2180 0x0000, 0x0000, 0x0000, 0x0144, 0x0000,
@@ -2800,7 +2800,7 @@ static const struct nphy_rf_control_override_rev7
2800 { 0x0010, 0x344, 0x345, 0x0010, 4 }, 2800 { 0x0010, 0x344, 0x345, 0x0010, 4 },
2801}; 2801};
2802 2802
2803struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = { 2803static struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = {
2804 { 10, 14, 19, 27 }, 2804 { 10, 14, 19, 27 },
2805 { -5, 6, 10, 15 }, 2805 { -5, 6, 10, 15 },
2806 { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, 2806 { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA },
@@ -2811,7 +2811,7 @@ struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = {
2811 0x18, 0x18, 0x18, 2811 0x18, 0x18, 0x18,
2812 0x01D0, 0x5, 2812 0x01D0, 0x5,
2813}; 2813};
2814struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = { 2814static struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = {
2815 { /* 2GHz */ 2815 { /* 2GHz */
2816 { /* PHY rev 3 */ 2816 { /* PHY rev 3 */
2817 { 7, 11, 16, 23 }, 2817 { 7, 11, 16, 23 },
@@ -3095,9 +3095,55 @@ void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
3095} 3095}
3096 3096
3097#define ntab_upload(dev, offset, data) do { \ 3097#define ntab_upload(dev, offset, data) do { \
3098 b43_ntab_write_bulk(dev, offset, offset##_SIZE, data); \ 3098 b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \
3099 } while (0) 3099 } while (0)
3100void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev) 3100
3101static void b43_nphy_tables_init_rev3(struct b43_wldev *dev)
3102{
3103 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3104 u8 antswlut;
3105
3106 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3107 antswlut = sprom->fem.ghz5.antswlut;
3108 else
3109 antswlut = sprom->fem.ghz2.antswlut;
3110
3111 /* Static tables */
3112 ntab_upload(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
3113 ntab_upload(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
3114 ntab_upload(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
3115 ntab_upload(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
3116 ntab_upload(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
3117 ntab_upload(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
3118 ntab_upload(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
3119 ntab_upload(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
3120 ntab_upload(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
3121 ntab_upload(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
3122 ntab_upload(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
3123 ntab_upload(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
3124 ntab_upload(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
3125 ntab_upload(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
3126 ntab_upload(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
3127 ntab_upload(dev, B43_NTAB_C0_ESTPLT_R3, b43_ntab_estimatepowerlt0_r3);
3128 ntab_upload(dev, B43_NTAB_C1_ESTPLT_R3, b43_ntab_estimatepowerlt1_r3);
3129 ntab_upload(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
3130 ntab_upload(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
3131 ntab_upload(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
3132 ntab_upload(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
3133 ntab_upload(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
3134 ntab_upload(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
3135 ntab_upload(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
3136 ntab_upload(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
3137
3138 /* Volatile tables */
3139 if (antswlut < ARRAY_SIZE(b43_ntab_antswctl_r3))
3140 ntab_upload(dev, B43_NTAB_ANT_SW_CTL_R3,
3141 b43_ntab_antswctl_r3[antswlut]);
3142 else
3143 B43_WARN_ON(1);
3144}
3145
3146static void b43_nphy_tables_init_rev0(struct b43_wldev *dev)
3101{ 3147{
3102 /* Static tables */ 3148 /* Static tables */
3103 ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct); 3149 ntab_upload(dev, B43_NTAB_FRAMESTRUCT, b43_ntab_framestruct);
@@ -3130,48 +3176,13 @@ void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
3130 ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1); 3176 ntab_upload(dev, B43_NTAB_C1_LOFEEDTH, b43_ntab_loftlt1);
3131} 3177}
3132 3178
3133#define ntab_upload_r3(dev, offset, data) do { \ 3179/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables */
3134 b43_ntab_write_bulk(dev, offset, ARRAY_SIZE(data), data); \ 3180void b43_nphy_tables_init(struct b43_wldev *dev)
3135 } while (0)
3136void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev)
3137{ 3181{
3138 struct ssb_sprom *sprom = dev->dev->bus_sprom; 3182 if (dev->phy.rev >= 3)
3139 3183 b43_nphy_tables_init_rev3(dev);
3140 /* Static tables */
3141 ntab_upload_r3(dev, B43_NTAB_FRAMESTRUCT_R3, b43_ntab_framestruct_r3);
3142 ntab_upload_r3(dev, B43_NTAB_PILOT_R3, b43_ntab_pilot_r3);
3143 ntab_upload_r3(dev, B43_NTAB_TMAP_R3, b43_ntab_tmap_r3);
3144 ntab_upload_r3(dev, B43_NTAB_INTLEVEL_R3, b43_ntab_intlevel_r3);
3145 ntab_upload_r3(dev, B43_NTAB_TDTRN_R3, b43_ntab_tdtrn_r3);
3146 ntab_upload_r3(dev, B43_NTAB_NOISEVAR0_R3, b43_ntab_noisevar0_r3);
3147 ntab_upload_r3(dev, B43_NTAB_NOISEVAR1_R3, b43_ntab_noisevar1_r3);
3148 ntab_upload_r3(dev, B43_NTAB_MCS_R3, b43_ntab_mcs_r3);
3149 ntab_upload_r3(dev, B43_NTAB_TDI20A0_R3, b43_ntab_tdi20a0_r3);
3150 ntab_upload_r3(dev, B43_NTAB_TDI20A1_R3, b43_ntab_tdi20a1_r3);
3151 ntab_upload_r3(dev, B43_NTAB_TDI40A0_R3, b43_ntab_tdi40a0_r3);
3152 ntab_upload_r3(dev, B43_NTAB_TDI40A1_R3, b43_ntab_tdi40a1_r3);
3153 ntab_upload_r3(dev, B43_NTAB_PILOTLT_R3, b43_ntab_pilotlt_r3);
3154 ntab_upload_r3(dev, B43_NTAB_CHANEST_R3, b43_ntab_channelest_r3);
3155 ntab_upload_r3(dev, B43_NTAB_FRAMELT_R3, b43_ntab_framelookup_r3);
3156 ntab_upload_r3(dev, B43_NTAB_C0_ESTPLT_R3,
3157 b43_ntab_estimatepowerlt0_r3);
3158 ntab_upload_r3(dev, B43_NTAB_C1_ESTPLT_R3,
3159 b43_ntab_estimatepowerlt1_r3);
3160 ntab_upload_r3(dev, B43_NTAB_C0_ADJPLT_R3, b43_ntab_adjustpower0_r3);
3161 ntab_upload_r3(dev, B43_NTAB_C1_ADJPLT_R3, b43_ntab_adjustpower1_r3);
3162 ntab_upload_r3(dev, B43_NTAB_C0_GAINCTL_R3, b43_ntab_gainctl0_r3);
3163 ntab_upload_r3(dev, B43_NTAB_C1_GAINCTL_R3, b43_ntab_gainctl1_r3);
3164 ntab_upload_r3(dev, B43_NTAB_C0_IQLT_R3, b43_ntab_iqlt0_r3);
3165 ntab_upload_r3(dev, B43_NTAB_C1_IQLT_R3, b43_ntab_iqlt1_r3);
3166 ntab_upload_r3(dev, B43_NTAB_C0_LOFEEDTH_R3, b43_ntab_loftlt0_r3);
3167 ntab_upload_r3(dev, B43_NTAB_C1_LOFEEDTH_R3, b43_ntab_loftlt1_r3);
3168
3169 /* Volatile tables */
3170 if (sprom->fem.ghz2.antswlut < ARRAY_SIZE(b43_ntab_antswctl2g_r3))
3171 ntab_upload_r3(dev, B43_NTAB_ANT_SW_CTL_R3,
3172 b43_ntab_antswctl2g_r3[sprom->fem.ghz2.antswlut]);
3173 else 3184 else
3174 B43_WARN_ON(1); 3185 b43_nphy_tables_init_rev0(dev);
3175} 3186}
3176 3187
3177/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ 3188/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
diff --git a/drivers/net/wireless/b43/tables_nphy.h b/drivers/net/wireless/b43/tables_nphy.h
index c600700ceedc..9ff33adcff89 100644
--- a/drivers/net/wireless/b43/tables_nphy.h
+++ b/drivers/net/wireless/b43/tables_nphy.h
@@ -115,22 +115,22 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
115#define B43_NTAB_NOISEVAR11_SIZE 256 115#define B43_NTAB_NOISEVAR11_SIZE 256
116#define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */ 116#define B43_NTAB_C0_ESTPLT B43_NTAB8 (0x1A, 0x000) /* Estimate Power Lookup Table Core 0 */
117#define B43_NTAB_C0_ESTPLT_SIZE 64 117#define B43_NTAB_C0_ESTPLT_SIZE 64
118#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
119#define B43_NTAB_C1_ESTPLT_SIZE 64
120#define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */ 118#define B43_NTAB_C0_ADJPLT B43_NTAB8 (0x1A, 0x040) /* Adjust Power Lookup Table Core 0 */
121#define B43_NTAB_C0_ADJPLT_SIZE 128 119#define B43_NTAB_C0_ADJPLT_SIZE 128
122#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
123#define B43_NTAB_C1_ADJPLT_SIZE 128
124#define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */ 120#define B43_NTAB_C0_GAINCTL B43_NTAB32(0x1A, 0x0C0) /* Gain Control Lookup Table Core 0 */
125#define B43_NTAB_C0_GAINCTL_SIZE 128 121#define B43_NTAB_C0_GAINCTL_SIZE 128
126#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
127#define B43_NTAB_C1_GAINCTL_SIZE 128
128#define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */ 122#define B43_NTAB_C0_IQLT B43_NTAB32(0x1A, 0x140) /* IQ Lookup Table Core 0 */
129#define B43_NTAB_C0_IQLT_SIZE 128 123#define B43_NTAB_C0_IQLT_SIZE 128
130#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
131#define B43_NTAB_C1_IQLT_SIZE 128
132#define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */ 124#define B43_NTAB_C0_LOFEEDTH B43_NTAB16(0x1A, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 0 */
133#define B43_NTAB_C0_LOFEEDTH_SIZE 128 125#define B43_NTAB_C0_LOFEEDTH_SIZE 128
126#define B43_NTAB_C1_ESTPLT B43_NTAB8 (0x1B, 0x000) /* Estimate Power Lookup Table Core 1 */
127#define B43_NTAB_C1_ESTPLT_SIZE 64
128#define B43_NTAB_C1_ADJPLT B43_NTAB8 (0x1B, 0x040) /* Adjust Power Lookup Table Core 1 */
129#define B43_NTAB_C1_ADJPLT_SIZE 128
130#define B43_NTAB_C1_GAINCTL B43_NTAB32(0x1B, 0x0C0) /* Gain Control Lookup Table Core 1 */
131#define B43_NTAB_C1_GAINCTL_SIZE 128
132#define B43_NTAB_C1_IQLT B43_NTAB32(0x1B, 0x140) /* IQ Lookup Table Core 1 */
133#define B43_NTAB_C1_IQLT_SIZE 128
134#define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */ 134#define B43_NTAB_C1_LOFEEDTH B43_NTAB16(0x1B, 0x1C0) /* Local Oscillator Feed Through Lookup Table Core 1 */
135#define B43_NTAB_C1_LOFEEDTH_SIZE 128 135#define B43_NTAB_C1_LOFEEDTH_SIZE 128
136 136
@@ -154,15 +154,17 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
154#define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */ 154#define B43_NTAB_CHANEST_R3 B43_NTAB32(22, 0) /* channel estimate */
155#define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */ 155#define B43_NTAB_FRAMELT_R3 B43_NTAB8(24, 0) /* frame lookup */
156#define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */ 156#define B43_NTAB_C0_ESTPLT_R3 B43_NTAB8(26, 0) /* estimated power lookup 0 */
157#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
158#define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */ 157#define B43_NTAB_C0_ADJPLT_R3 B43_NTAB8(26, 64) /* adjusted power lookup 0 */
159#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
160#define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */ 158#define B43_NTAB_C0_GAINCTL_R3 B43_NTAB32(26, 192) /* gain control lookup 0 */
161#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
162#define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */ 159#define B43_NTAB_C0_IQLT_R3 B43_NTAB32(26, 320) /* I/Q lookup 0 */
163#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
164#define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */ 160#define B43_NTAB_C0_LOFEEDTH_R3 B43_NTAB16(26, 448) /* Local Oscillator Feed Through lookup 0 */
161#define B43_NTAB_C0_PAPD_COMP_R3 B43_NTAB16(26, 576)
162#define B43_NTAB_C1_ESTPLT_R3 B43_NTAB8(27, 0) /* estimated power lookup 1 */
163#define B43_NTAB_C1_ADJPLT_R3 B43_NTAB8(27, 64) /* adjusted power lookup 1 */
164#define B43_NTAB_C1_GAINCTL_R3 B43_NTAB32(27, 192) /* gain control lookup 1 */
165#define B43_NTAB_C1_IQLT_R3 B43_NTAB32(27, 320) /* I/Q lookup 1 */
165#define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */ 166#define B43_NTAB_C1_LOFEEDTH_R3 B43_NTAB16(27, 448) /* Local Oscillator Feed Through lookup 1 */
167#define B43_NTAB_C1_PAPD_COMP_R3 B43_NTAB16(27, 576)
166 168
167#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18 169#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_40_SIZE 18
168#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18 170#define B43_NTAB_TX_IQLO_CAL_LOFT_LADDER_20_SIZE 18
@@ -182,8 +184,7 @@ void b43_ntab_write(struct b43_wldev *dev, u32 offset, u32 value);
182void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset, 184void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
183 unsigned int nr_elements, const void *_data); 185 unsigned int nr_elements, const void *_data);
184 186
185void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev); 187void b43_nphy_tables_init(struct b43_wldev *dev);
186void b43_nphy_rev3plus_tables_init(struct b43_wldev *dev);
187 188
188const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev); 189const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev);
189 190
diff --git a/drivers/net/wireless/b43/tables_phy_lcn.c b/drivers/net/wireless/b43/tables_phy_lcn.c
index 5176363cadf2..e347b8d80ea4 100644
--- a/drivers/net/wireless/b43/tables_phy_lcn.c
+++ b/drivers/net/wireless/b43/tables_phy_lcn.c
@@ -313,7 +313,7 @@ static const u32 b43_lcntab_0x18[] = {
313 * TX gain. 313 * TX gain.
314 **************************************************/ 314 **************************************************/
315 315
316const struct b43_lcntab_tx_gain_tbl_entry 316static const struct b43_lcntab_tx_gain_tbl_entry
317 b43_lcntab_tx_gain_tbl_2ghz_ext_pa_rev0[B43_LCNTAB_TX_GAIN_SIZE] = { 317 b43_lcntab_tx_gain_tbl_2ghz_ext_pa_rev0[B43_LCNTAB_TX_GAIN_SIZE] = {
318 { 0x03, 0x00, 0x1f, 0x0, 0x48 }, 318 { 0x03, 0x00, 0x1f, 0x0, 0x48 },
319 { 0x03, 0x00, 0x1f, 0x0, 0x46 }, 319 { 0x03, 0x00, 0x1f, 0x0, 0x46 },
@@ -449,7 +449,7 @@ const struct b43_lcntab_tx_gain_tbl_entry
449 * SW control. 449 * SW control.
450 **************************************************/ 450 **************************************************/
451 451
452const u16 b43_lcntab_sw_ctl_4313_epa_rev0[] = { 452static const u16 b43_lcntab_sw_ctl_4313_epa_rev0[] = {
453 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, 453 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008,
454 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001, 454 0x0004, 0x0001, 0x0002, 0x0008, 0x0004, 0x0001,
455 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008, 455 0x0002, 0x0008, 0x0004, 0x0001, 0x0002, 0x0008,
@@ -631,7 +631,7 @@ static void b43_phy_lcn_upload_static_tables(struct b43_wldev *dev)
631 lcntab_upload(dev, B43_LCNTAB32(0x18, 0), b43_lcntab_0x18); 631 lcntab_upload(dev, B43_LCNTAB32(0x18, 0), b43_lcntab_0x18);
632} 632}
633 633
634void b43_phy_lcn_load_tx_gain_tab(struct b43_wldev *dev, 634static void b43_phy_lcn_load_tx_gain_tab(struct b43_wldev *dev,
635 const struct b43_lcntab_tx_gain_tbl_entry *gain_table) 635 const struct b43_lcntab_tx_gain_tbl_entry *gain_table)
636{ 636{
637 u32 i; 637 u32 i;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 12:50:11 -0500