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path: root/drivers/net/wireless/b43/tables_nphy.h
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Diffstat (limited to 'drivers/net/wireless/b43/tables_nphy.h')
-rw-r--r--drivers/net/wireless/b43/tables_nphy.h59
1 files changed, 3 insertions, 56 deletions
diff --git a/drivers/net/wireless/b43/tables_nphy.h b/drivers/net/wireless/b43/tables_nphy.h
index 8fc1da9f8fe5..4ec593ba3eef 100644
--- a/drivers/net/wireless/b43/tables_nphy.h
+++ b/drivers/net/wireless/b43/tables_nphy.h
@@ -3,7 +3,6 @@
3 3
4#include <linux/types.h> 4#include <linux/types.h>
5 5
6
7struct b43_phy_n_sfo_cfg { 6struct b43_phy_n_sfo_cfg {
8 u16 phy_bw1a; 7 u16 phy_bw1a;
9 u16 phy_bw2; 8 u16 phy_bw2;
@@ -13,52 +12,6 @@ struct b43_phy_n_sfo_cfg {
13 u16 phy_bw6; 12 u16 phy_bw6;
14}; 13};
15 14
16struct b43_nphy_channeltab_entry_rev2 {
17 /* The channel number */
18 u8 channel;
19 /* The channel frequency in MHz */
20 u16 freq;
21 /* An unknown value */
22 u16 unk2;
23 /* Radio register values on channelswitch */
24 u8 radio_pll_ref;
25 u8 radio_rf_pllmod0;
26 u8 radio_rf_pllmod1;
27 u8 radio_vco_captail;
28 u8 radio_vco_cal1;
29 u8 radio_vco_cal2;
30 u8 radio_pll_lfc1;
31 u8 radio_pll_lfr1;
32 u8 radio_pll_lfc2;
33 u8 radio_lgbuf_cenbuf;
34 u8 radio_lgen_tune1;
35 u8 radio_lgen_tune2;
36 u8 radio_c1_lgbuf_atune;
37 u8 radio_c1_lgbuf_gtune;
38 u8 radio_c1_rx_rfr1;
39 u8 radio_c1_tx_pgapadtn;
40 u8 radio_c1_tx_mxbgtrim;
41 u8 radio_c2_lgbuf_atune;
42 u8 radio_c2_lgbuf_gtune;
43 u8 radio_c2_rx_rfr1;
44 u8 radio_c2_tx_pgapadtn;
45 u8 radio_c2_tx_mxbgtrim;
46 /* PHY register values on channelswitch */
47 struct b43_phy_n_sfo_cfg phy_regs;
48};
49
50struct b43_nphy_channeltab_entry_rev3 {
51 /* The channel number */
52 u8 channel;
53 /* The channel frequency in MHz */
54 u16 freq;
55 /* Radio register values on channelswitch */
56 /* TODO */
57 /* PHY register values on channelswitch */
58 struct b43_phy_n_sfo_cfg phy_regs;
59};
60
61
62struct b43_wldev; 15struct b43_wldev;
63 16
64struct nphy_txiqcal_ladder { 17struct nphy_txiqcal_ladder {
@@ -82,18 +35,12 @@ struct nphy_rf_control_override_rev3 {
82 u8 val_addr1; 35 u8 val_addr1;
83}; 36};
84 37
85/* Upload the default register value table. 38/* Get the NPHY Channel Switch Table entry for a channel.
86 * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz
87 * table is uploaded. If "ignore_uploadflag" is true, we upload any value
88 * and ignore the "UPLOAD" flag. */
89void b2055_upload_inittab(struct b43_wldev *dev,
90 bool ghz5, bool ignore_uploadflag);
91
92
93/* Get the NPHY Channel Switch Table entry for a channel number.
94 * Returns NULL on failure to find an entry. */ 39 * Returns NULL on failure to find an entry. */
95const struct b43_nphy_channeltab_entry_rev2 * 40const struct b43_nphy_channeltab_entry_rev2 *
96b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel); 41b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel);
42const struct b43_nphy_channeltab_entry_rev3 *
43b43_nphy_get_chantabent_rev3(struct b43_wldev *dev, u16 freq);
97 44
98 45
99/* The N-PHY tables. */ 46/* The N-PHY tables. */